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* | drm/amd/display: Use hardware max low point when sampling OTFLeo (Sunpeng) Li2018-02-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | The MAX_LOW_POINT macro should reflect the maximum low point within hardware. Otherwise, sampling for the hardware points from the output transfer function (OTF) will be incorrect. Also, fix usage of MAX_LOW_POINT accordingly. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Make couple functions in DCE80 TG staticHarry Wentland2018-02-192-68/+63
| | | | | | | | | | | | | | Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Re-use DCE100 display_power_gating for DCE80Harry Wentland2018-02-193-38/+6
| | | | | | | | | | | | | | | | | | Both functions are the same Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Remove unused DCE80 compressorHarry Wentland2018-02-193-913/+1
| | | | | | | | | | | | | | Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Keep eDP stream enabled during boot.Yongqiang Sun2018-02-193-24/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This path fixed specific eDP panel cold boot black screen due to unnecessary enable link. Change: In case of boot up with eDP, if OS is going to set mode on eDP, keep eDP light up, do not disable and reset corresponding HW. This change may affect dce asics and S3/S4 Resume with multi-monitor. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: dal 3.1.34Tony Cheng2018-02-191-1/+1
| | | | | | | | | | | | | | Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: disable seamless vp adjustment for mirrored surfaceDmytro Laktyushkin2018-02-191-4/+4
| | | | | | | | | | | | | | Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: add monitor patch for delay after DP receive power upMartin Tsai2018-02-192-0/+7
| | | | | | | | | | | | | | Signed-off-by: Martin Tsai <martin.tsai@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Change blackout time to 0 on CZ/STHarry Wentland2018-02-191-4/+4
| | | | | | | | | | | | | | | | | | | | These should only be non-0 if big hammer w/a is implemented. Currently DC doesn't implement it, so leave them 0. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: add force_trigger even to static screen controlCharlene Liu2018-02-193-0/+5
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: dal 3.1.33Tony Cheng2018-02-191-1/+1
| | | | | | | | | | | | | | Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: boot up/S4 fix mainlink off before BL.Charlene Liu2018-02-191-1/+1
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: VGA black screen from s3 when attached to hookHersen Wu2018-02-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | [Description] For MST, DC already notify MST sink for MST mode, DC stll check DP SINK DPCD register to see if MST enabled. DP RX firmware may not handle this properly. Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Rearchitecture HDMI HPDJohn Barberiz2018-02-192-0/+36
| | | | | | | | | | | | | | | | | | | | - Disabled HPD filter and used HPD software timer instead - Allows DM to disable HPD filtering Signed-off-by: John Barberiz <jbarberi@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: Unify the dm resume calls into oneMikita Lipski2018-02-191-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | amdgpu_dm_display_resume is now called from dm_resume to unify DAL resume call into a single function call There is no more need to separately call 2 resume functions for DM. Initially they were separated to resume display state after cursor is pinned. But because there is no longer any corruption with the cursor - the calls can be merged into one function hook. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Remove unused CFLAGS entry in DML MakefileHarry Wentland2018-02-191-1/+0
| | | | | | | | | | | | | | | | Missed that with a previous change that removed unused files. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | amdgpu/dc/calcs: Support clang option for stack alignmentMatthias Kaehlcke2018-02-191-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | calcs uses the compiler option -mpreferred-stack-boundary=4 to configure a stack alignment of 16 bytes. Clang uses the option -mstack-alignment instead, which expects as parameter the alignment in bytes, and not a power of two like -mpreferred-stack-boundary. Probe for both compiler options and use the correct one, similar to what is done in arch/x86/Makefile. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | amdgpu/dc/dml: Support clang option for stack alignmentMatthias Kaehlcke2018-02-191-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DML uses the compiler option -mpreferred-stack-boundary=4 to configure a stack alignment of 16 bytes. Clang uses the option -mstack-alignment instead, which expects as parameter the alignment in bytes, and not a power of two like -mpreferred-stack-boundary. Probe for both compiler options and use the correct one, similar to what is done in arch/x86/Makefile. Reported-by: Guenter Roeck <groeck@chromium.org> Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | amdgpu/dc/calcs: Consolidate redundant CFLAGSMatthias Kaehlcke2018-02-191-3/+5
| | | | | | | | | | | | | | | | | | Use a variable for common CFLAGS instead of specifying the same flags for every source file. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | amdgpu/dc/dml: Consolidate redundant CFLAGSMatthias Kaehlcke2018-02-191-7/+8
| | | | | | | | | | | | | | | | | | Use a variable for common CFLAGS instead of specifying the same flags for every source file. Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | amdgpu/dc: Fix enum mismatch in calls to program_color_matrix()Matthias Kaehlcke2018-02-192-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver passes GRAPHICS_CSC_ADJUST_TYPE_SW of type enum graphics_csc_adjust_type to program_color_matrix(), however the function expects a parameter of type enum grph_color_adjust_option. Supposedly the intention was to pass GRPH_COLOR_MATRIX_SW, which has the same value as GRAPHICS_CSC_ADJUST_TYPE_SW, so the mismatch didn't cause any trouble. Pass GRPH_COLOR_MATRIX_SW to program_color_matrix() instead of GRAPHICS_CSC_ADJUST_TYPE_SW, this also fixes the following warning when building the kernel with clang: drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.c:1129:24: error: implicit conversion from enumeration type 'enum graphics_csc_adjust_type' to different enumeration type 'enum grph_color_adjust_option' [-Werror,-Wenum-conversion] xfm_dce, tbl_entry, GRAPHICS_CSC_ADJUST_TYPE_SW); Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Remove extra pairs of parentheses in dce_calcs.cMatthias Kaehlcke2018-02-191-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The double parentheses are not needed. Removing them fixes multiple warnings like this when building with clang: drivers/gpu/drm/amd/amdgpu/../display/dc/calcs/dce_calcs.c:617:42: error: equality comparison with extraneous parentheses [-Werror,-Wparentheses-equality] if ((data->graphics_micro_tile_mode == bw_def_rotated_micro_tiling)) { Signed-off-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Guenter Roeck <groeck@chromium.org> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add primary tmz_c and meta tmz tmz_c.Yongqiang Sun2018-02-192-6/+23
| | | | | | | | | | | | | | Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: enable #PME code path for RV.Charlene Liu2018-02-191-3/+3
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: dal 3.1.32Tony Cheng2018-02-191-1/+1
| | | | | | | | | | | | | | Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Optimize regamma calculationsKrunoslav Kovac2018-02-194-52/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are several optimizations: 1) Use predefined SRGB, don't calculate. This is the most common case. 2) Precompute HW X points at boot since they're fixed in ColModule 3) Precompute PQ - it never changes and is very CPU intensive in fixed pt. 4) Reduce number of points in ColModule to 512 (32x16) from 1024. This also requires reducing some regions for legacy DCEs to 16 pts at most. Performance 1) is super-fast, build_output_tf is 1-2us, down from 25000-30000. Programming also fast since only one reg write. 2)+3) gives build_output_tf for PQ in ~100us range, down from ~80000-110000 2) + 4) results in slightly over 50% improvement. It gives an idea of the savings when we can't use SRGB or PQ table (e.g. sdr white level > 80). There's also a bit of refactoring: renaming some stuff that was misleading and removing a lot of magic numbers that novices might not be able to understand where they come from and what they mean. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: resume from S3 bypass power down HW block.Charlene Liu2018-02-197-11/+33
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: add eDP 1.2+ polling for T7Charlene Liu2018-02-194-5/+33
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: dal 3.1.31Tony Cheng2018-02-191-1/+1
| | | | | | | | | | | | | | Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fixed if statement parameters to add a delay on disconnectJohn Barberiz2018-02-191-2/+2
| | | | | | | | | | | | | | Signed-off-by: John Barberiz <jbarberi@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add return value for detect dp.Yongqiang Sun2018-02-193-14/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | System soft hang when hotplug specific 4K DP panel due to link caps read error and incorrect link setting parmas to enable dp. Add status check for DPCD read and add return value for detect dp, in case of false, return from caller, avoid further false operation. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix boot-up on vega10Roman Li2018-02-191-7/+12
| | | | | | | | | | | | | | | | | | | | | | Fixing null-deref on Vega10 due to regression after 'fix cursor related Pstate hang' change. Added null checks in setting cursor position. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Remove couple of unused OPTC registersNikola Cornij2018-02-192-4/+5
| | | | | | | | | | | | | | Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: turn off cursor when disconnect planeEric Yang2018-02-191-0/+3
| | | | | | | | | | | | | | | | | | | | As a precaution to prevent cases where cursor is enabled on a pipe that is disabled, always turn off cursor when disconnecting plane. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Expose is_rgb_cspace function in hw_sequencerEric Bernstein2018-02-193-2/+2
| | | | | | | | | | | | | | Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: WBSCL filter init calculation fixesKen Chalmers2018-02-192-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | * Previous code did some calculations with a mix of normal integers and integers aligned as U2.24 fixed-point values. * There were bugs in the conversion of the final result into the S4.19 values required for the registers. Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: remove unused function prototypesEric Yang2018-02-192-8/+2
| | | | | | | | | | | | | | Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix cursor related Pstate hangEric Yang2018-02-194-66/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move cursor programming to inside the OTG_MASTER_UPDATE_LOCK If graphics plane go from 1 pipe to hsplit, the cursor updates after mpc programming and unlock. Which means there is a window of time where cursor is enabled on the wrong pipe if it's on the right side of the screen (i.e. case where cursor need to move from pipe 0 to pipe 3 post split). This will cause pstate hang. Solution is to program the cursor while still locked. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Set irq state only on existing crtcsMikita Lipski2018-02-191-4/+2
| | | | | | | | | | | | | | | | | | | | | | Because AMDGPU_CRTC_IRQ_VLINE1 = 6, it expected 6 more crtcs to be programed with disabled irq state in amdgpu_irq_disable_all. That caused errors and accessed the wrong memory location. Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Null check for gamma correction.Yongqiang Sun2018-02-191-1/+2
| | | | | | | | | | | | | | Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Check hubp in pipe_ctx not in res_pool.Yongqiang Sun2018-02-191-1/+1
| | | | | | | | | | | | | | | | | | | | When disable plane, check power gate flag in hubp with pipe_ctx, not with res_pool. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: dal 3.1.30Tony Cheng2018-02-191-1/+1
| | | | | | | | | | | | | | Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Bypass gamma set if not standard typeJohn Barberiz2018-02-192-1/+5
| | | | | | | | | | | | | | | | | | | | If non-standard gamma type detected set identity matrix flag so that we can bypass the gamma mode. Signed-off-by: John Barberiz <jbarberi@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: wait for T9 after backlight off mainlink blank.Charlene Liu2018-02-193-2/+4
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fix multiple definitions of handle_crc_irqLeo (Sunpeng) Li2018-02-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_DEBUG_FS is disabled, then CRC should also be disabled. Therefore, amdgpu_dm_crtc_handle_crc_irq was redefined as a no-op function within amdgpu_dm.h. However, since amdgpu_dm.h is included in multiple files, this caused conflicts when linking during compile. Therefore, Use a macro to define the function as a no-op instead. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fixed non-native modes not lighting upJerry (Fangzhi) Zuo2018-02-191-1/+3
| | | | | | | | | | | | | | | | | | | | There is no need to call drm_mode_set_crtcinfo() again once crtc timing is decided. Otherwise non-native/unsupported timing might get overwritten. Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Remove return when no EDID read.Martin Tsai2018-02-191-2/+0
| | | | | | | | | | | | | | Signed-off-by: Martin Tsai <martin.tsai@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: BL setting save/restoreCharlene Liu2018-02-191-0/+9
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: remove unused display_vblank_wait interfaceAlex Deucher2018-02-191-1/+0
| | | | | | | | | | | | | | No longer used since we changed the MC programming sequence. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix incompatible structure layoutsArnd Bergmann2018-02-193-61/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building the amd display driver with link-time optimizations revealed a bug that caused dal_cmd_tbl_helper_dce80_get_table() and dal_cmd_tbl_helper_dce110_get_table() get called with an incompatible return type between the two callers in command_table_helper.c and command_table_helper2.c: drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.h:31: error: type of 'dal_cmd_tbl_helper_dce80_get_table' does not match original declaration [-Werror=lto-type-mismatch] const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void); drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.c:351: note: 'dal_cmd_tbl_helper_dce80_get_table' was previously declared here const struct command_table_helper *dal_cmd_tbl_helper_dce80_get_table(void) drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.h:32: error: type of 'dal_cmd_tbl_helper_dce110_get_table' does not match original declaration [-Werror=lto-type-mismatch] const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void); drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.c:361: note: 'dal_cmd_tbl_helper_dce110_get_table' was previously declared here const struct command_table_helper *dal_cmd_tbl_helper_dce110_get_table(void) The two versions of the structure are obviously derived from the same one, but have diverged over time, before they got added to the kernel. This moves the structure to a new shared header file and uses the superset of the members, to ensure the interfaces are all compatible. Fixes: ae79c310b1a6 ("drm/amd/display: Add DCE12 bios parser support") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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