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* | drm/amd/display: Fix unused variable compilation errorLeo (Sunpeng) Li2018-02-191-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dce110/dce110_hw_sequencer.c: In function ‘dce110_blank_stream’: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dce110/dce110_hw_sequencer.c:1008:31: error: unused variable ‘params’ [-Werror=unused-variable] struct encoder_unblank_param params = { { 0 } }; Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: eDP sequence BL off first then DP blank.Charlene Liu2018-02-196-6/+29
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add debug flag for p010_mpo_supportGeling Li2018-02-191-0/+1
| | | | | | | | | | | | | | Signed-off-by: Geling Li <geling.li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Force full update on pixel_format_changeKrunoslav Kovac2018-02-192-1/+2
| | | | | | | | | | | | | | Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: dal 3.1.29Tony Cheng2018-02-191-1/+1
| | | | | | | | | | | | | | Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: dpms off mute az audio endpoint only.Charlene Liu2018-02-193-1/+7
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: revert to hacking bounding box for pipe splitDmytro Laktyushkin2018-02-191-25/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Directly editing pipe config outside of formula is error prone and results in higher clocks being used when splitting. For this reason we reverted to using bounding box hacking to split. Since sometimes this erroneusly results in higher dpm being required we unhack the bounding box and recalculate to allow dpm0 is possible. Side effect is we will lose some stutter efficiency in non dpm0 cases. This is not a big concern since increased stutter efficiency saves an order of magnitude less power than lower dpm. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: disable az_clock_gating for endpoint register access onlyCharlene Liu2018-02-191-1/+17
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Define dpp1_set_cursor_position in headerArun Pandey2018-02-191-0/+6
| | | | | | | | | | | | | | Signed-off-by: Arun Pandey <Arun.Pandey@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: fix backlight not off at resume from S4Charlene Liu2018-02-191-6/+27
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Add timing generator count to resource pool.Yongqiang Sun2018-02-198-4/+12
| | | | | | | | | | | | | | | | | | Use tg count in resource pool for further reference. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Synchronize update plane addr for freesyncSivapiriyanKumarasamy2018-02-191-16/+31
| | | | | | | | | | | | | | | | | | Lock top_pipe when doing update plane addr for split pipe freesync case Signed-off-by: SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Call update_stream_signal directly from amdgpu_dmHarry Wentland2018-02-192-1/+3
| | | | | | | | | | | | | | | | | | | | There's no good place in DC to cover all place where stream signal should be updated. update_stream_signal depends on timing which comes from DM. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Move output_tf to stream_state/updateYongqiang Sun2018-02-192-1/+2
| | | | | | | | | | | | | | Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Remove unused param in DMLKen Chalmers2018-02-191-1/+0
| | | | | | | | | | Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Update the register GRPH_SWAP_CNTL if surface pixel format ↵Duke Du2018-02-193-0/+5
| | | | | | | | | | | | | | changed. Signed-off-by: Duke Du <Duke.Du@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: dc: Remove unused display_mode_vba.cHarry Wentland2018-02-197-8611/+4
| | | | | | | | | | | | | | | | | | | | We're currently not using this. v2: More files and includes to remove. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amdgpu: rename amdgpu_get_crtc_scanoutposSamuel Li2018-02-191-1/+1
| | | | | | | | | | | | | | | | | | Add display to the name for consistency. Signed-off-by: Samuel Li <Samuel.Li@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/dc: include new ip and ip_offset headersHawking Zhang2018-02-1912-12/+24
| | | | | | | | | | | | Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: [RS4][RV] SDR Brightness BoostKrunoslav Kovac2018-02-192-1/+10
| | | | | | | | | | | | | | | | | | | | We assume FP16 1.0 frame buffer value maps to 80 nits. DC changes are to make this configurable. Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Update dcn10_init_hw for FPGAEric Bernstein2018-02-191-16/+19
| | | | | | | | | | | | | | | | | | | | Update dcn10_init_hw such that initialization of relevant HW blocks for Maximus FPGA are also initialized (and not skipped). Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Implement CRTC CRC for DCE110Leo (Sunpeng) Li2018-02-191-0/+122
| | | | | | | | | | | | | | | | | | | | Implement the timing generator hooks for configure_crc and get_crc. Also implement is_tg_enabled, as configure_crc uses it. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Implement interface for CRC on CRTCLeo (Sunpeng) Li2018-02-193-0/+140
| | | | | | | | | | | | | | | | | | | | Add interfaces in DC for per CRTC CRC configuration and fetching. Also implement amdgpu_dm functions to hook onto DRM. Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: clean up DCHUBBUB register definition in hwseqEric Bernstein2018-02-191-75/+1
| | | | | | | | | | | | | | | | | | | | Cleanup to remove unused register definition from hw sequencer header file since implementation moved from hw sequencer to dchubub file. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Refactor remove mpcc processing.Yongqiang Sun2018-02-191-14/+5
| | | | | | | | | | | | | | | | | | No need to use loop find opp, use opp in stream_res. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Move opp reg access from hwss to opp module.Yongqiang Sun2018-02-195-15/+29
| | | | | | | | | | | | | | Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: disablePSR in UpdatePlanes in PassiveLevelCharlene Liu2018-02-191-0/+3
| | | | | | | | | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fix null-derefs on non-dcn buildsRoman Li2018-02-192-2/+4
| | | | | | | | | | | | | | | | | | | | Fixing regression introduced by 'Use real BE and FE index to program regs.' Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Move dpp reg access from hwss to dpp module.Yongqiang Sun2018-02-196-43/+49
| | | | | | | | | | | | | | Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Check opplist in pipe ctx not in res pool.Yongqiang Sun2018-02-191-6/+6
| | | | | | | | | | | | | | Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fix check for setting input TFAndrew Jiang2018-02-196-15/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | We no longer change the plane state pointer for full updates, and as such, we weren't setting the input transfer function and programming the degamma registers when we are supposed to. Check for a full update, an input TF change, or a gamma change in the update flags instead to correct this. Signed-off-by: Andrew Jiang <Andrew.Jiang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Define remove_stream_from_ctx resource funcNikola Cornij2018-02-192-0/+8
| | | | | | | | | | | | | | | | | | This will allow us to clean up resources on a stream as needed. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Log which clocks are unsupportedHarry Wentland2018-02-191-1/+4
| | | | | | | | | | | | | | | | | | | | It would be useful to know which clocks are unsupported when logging an error message about unsupported clocks. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Use real BE and FE index to program regs.Yongqiang Sun2018-02-197-33/+55
| | | | | | | | | | | | | | | | | | | | | | In case of some pipes are fused, pipe_idx should not be used to program pipe regs. Instead of that, BE and FE inst number should be used for reg index. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Move hubp reg access from hwss to hubp module.Yongqiang Sun2018-02-195-21/+36
| | | | | | | | | | | | | | Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Don't block dual-link DVI modesHarry Wentland2018-02-191-2/+1
| | | | | | | | | | | | | | Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Don't allow dual-link DVI on all ASICs.Harry Wentland2018-02-196-2/+10
| | | | | | | | | | | | | | | | | | | | | | Our APUs (Carrizo, Stoney, Raven) don't support it. v2: Don't use is_apu as other ASICs might also not support it Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Disable eDP with a proper sequence.Yongqiang Sun2018-02-194-33/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Proper sequence should be: disable backlight dp blank disable output edp power off In enable accelatate mode, all the encoder and controller are disabled, so move disable eDP to the function is the easiest way to implement. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: dal 3.1.28Tony Cheng2018-02-191-1/+1
| | | | | | | | | | | | | | Signed-off-by: Tony Cheng <tony.cheng@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Pass signal directly to enable_tmds_outputHarry Wentland2018-02-195-18/+9
| | | | | | | | | | | | | | | | | | | | This makes the check for HDMI and dual-link DVI a bit more straightforward. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Move MAX_TMDS_CLOCK define to headerHarry Wentland2018-02-192-10/+0
| | | | | | | | | | | | | | Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: disable eDP backlight for extend monitor only reboot use case.Yongqiang Sun2018-02-191-1/+27
| | | | | | | | | | | | | | Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Pass full 3x4 remap matrix for color transformKrunoslav Kovac2018-02-196-139/+28
| | | | | | | | | | | | | | Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Prevent master programming in multisyncMikita Lipski2018-02-192-2/+4
| | | | | | | | | | | | | | | | | | Verify that the stream is master - and program only the slave displays Signed-off-by: Mikita Lipski <mikita.lipski@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fix FBC topology changeRoman Li2018-02-191-4/+19
| | | | | | | | | | | | | | | | | | With FBC enabled there was a potential null-deref on topology change due to hardcorded pipe index. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Use pipe_control_lock instead of tg lock.Yongqiang Sun2018-02-191-2/+2
| | | | | | | | | | | | | | Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: cleanup after FBC init reworkRoman Li2018-02-192-6/+0
| | | | | | | | | | | | | | | | | | | | | | After reworking FBC init for dynamic mem alloc old FBC init code in DC became redundant. Removing it. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Eliminate several Maximus-specific code pathsKen Chalmers2018-02-193-45/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows Maximus emulation to more closely mirror actual silicon execution. * Enable pool->base.display_clock creation on Maximus. * Enable rest of dce110_apply_ctx_to_hw on Maximus. * Remove apply_ctx_to_hw_fpga (no longer necessary with the full dce110_apply_ctx_to_hw enabled). * Disable the dmcu->funcs->set_psr_wait_loop call in dce112_set_clock for Maximus (this was the only fix-up necessary after enabling dce110_apply_ctx_to_hw; everything else works unmodified on Maximus). Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: Fix Maximus pixel clock programmingKen Chalmers2018-02-191-11/+1
| | | | | | | | | | | | | | | | | | Maximus testing now defaults to a 700 MHz emulated dispclk Signed-off-by: Ken Chalmers <ken.chalmers@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/amd/display: PME sw wa to support waking AZ D3Charlene Liu2018-02-192-1/+14
|/ | | | | | | Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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