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* dmaengine: rcar-dmac: Fix too early/late system suspend/resume callbacksGeert Uytterhoeven2018-04-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | If serial console wake-up is enabled ("echo enabled > /sys/.../ttySC0/power/wakeup"), and any serial input is received while the system is suspended, serial port input no longer works after system resume. Note that: 1) The system can still be woken up using the serial console, 2) Serial port input keeps working if the system is woken up in some other way (e.g. Wake-on-LAN or gpio-keys), and no serial input was received while suspended. To fix this, replace SET_LATE_SYSTEM_SLEEP_PM_OPS() by SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(), as the callbacks installed by the former happen too early resp. late in the suspend resp. resume process. Reported-by: RVC test team via Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Fixes: 1131b0a4af911de5 ("dmaengine: rcar-dmac: Make DMAC reinit during system resume explicit") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: Check the done lists in rcar_dmac_chan_get_residue()Yoshihiro Shimoda2018-03-051-0/+9
| | | | | | | | | | | | | | | | | | | | | | This patch fixes an issue that a race condition happens between a client driver and the rcar-dmac driver: - The rcar_dmac_isr_transfer_end() is called. - The done list appears, and desc.running is the next active list. - rcar_dmac_chan_get_residue() is called by a client driver before rcar_dmac_isr_channel_thread() is called. - The rcar_dmac_chan_get_residue() will not find any descriptors. - And, the following WARNING happens: WARN(1, "No descriptor for cookie!"); The sh-sci driver with HSCIF (921,600bps) on R-Car H3 can cause this situation. So, this patch checks the done lists in rcar_dmac_chan_get_residue() and returns zero if the done lists has the argument cookie. Tested-by: Nguyen Viet Dung <dung.nguyen.aj@renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge tag 'dmaengine-4.16-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2018-01-311-1/+43
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull dmaengine updates from Vinod Koul: "This time is smallish update with updates mainly to drivers: - updates to xilinx and zynqmp dma controllers - update reside calculation for rcar controller - more RSTify fixes for documentation - add support for race free transfer termination and updating for users for that - support for new rev of hidma with addition new APIs to get device match data in ACPI/OF - random updates to bunch of other drivers" * tag 'dmaengine-4.16-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (47 commits) dmaengine: dmatest: fix container_of member in dmatest_callback dmaengine: stm32-dmamux: Remove unnecessary platform_get_resource() error check dmaengine: sprd: statify 'sprd_dma_prep_dma_memcpy' dmaengine: qcom_hidma: simplify DT resource parsing dmaengine: xilinx_dma: Free BD consistent memory dmaengine: xilinx_dma: Fix warning variable prev set but not used dmaengine: xilinx_dma: properly configure the SG mode bit in the driver for cdma dmaengine: doc: format struct fields using monospace dmaengine: doc: fix bullet list formatting dmaengine: ti-dma-crossbar: Fix event mapping for TPCC_EVT_MUX_60_63 dmaengine: cppi41: Fix channel queues array size check dmaengine: imx-sdma: Add MODULE_FIRMWARE dmaengine: xilinx_dma: Fix typos dmaengine: xilinx_dma: Differentiate probe based on the ip type dmaengine: xilinx_dma: fix style issues from checkpatch dmaengine: xilinx_dma: Fix kernel doc warnings dmaengine: xilinx_dma: Fix race condition in the driver for multiple descriptor scenario dmaeninge: xilinx_dma: Fix bug in multiple frame stores scenario in vdma dmaengine: xilinx_dma: Check for channel idle state before submitting dma descriptor dmaengine: zynqmp_dma: Fix race condition in the probe ...
| * dmaengine: rcar-dmac: use TCRB instead of TCR for residueKuninori Morimoto2017-11-291-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SYS/RT/Audio DMAC includes independent data buffers for reading and writing. Therefore, the read transfer counter and write transfer counter have different values. TCR indicates read counter, and TCRB indicates write counter. The relationship is like below. TCR TCRB [SOURCE] -> [DMAC] -> [SINK] In the MEM_TO_DEV direction, what really matters is how much data has been written to the device. If the DMA is interrupted between read and write, then, the data doesn't end up in the destination, so shouldn't be counted. TCRB is thus the register we should use in this cases. In the DEV_TO_MEM direction, the situation is more complex. Both the read and write side are important. What matters from a data consumer point of view is how much data has been written to memory. On the other hand, if the transfer is interrupted between read and write, we'll end up losing data. It can also be important to report. In the MEM_TO_MEM direction, what matters is of course how much data has been written to memory from data consumer point of view. Here, because read and write have independent data buffers, it will take a while for TCR and TCRB to become equal. Thus we should check TCRB in this case, too. Thus, all cases we should check TCRB instead of TCR. Without this patch, Sound Capture has noise after PulseAudio support (= 07b7acb51d2 ("ASoC: rsnd: update pointer more accurate")), because the recorder will use wrong residue counter which indicates transferred from sound device, but in reality the data was not yet put to memory and recorder will record it. However, because DMAC is buffering data until it can be transferable size, TCRB might not be updated. For example, if consumer doesn't know how much data can be received, it requests enough size to DMAC. But in reality, it might receive very few data. In such case, DMAC just buffered it until transferable size, and no TCRB updated. In such case, this buffered data will be transferred if CHCR::DE bit was cleared, and this is happen if rcar_dmac_chan_halt(). In other word, it happen when consumer called dmaengine_terminate_all(). Because of this behavior, it need to flush buffered data when it returns "residue" (= dmaengine_tx_status()). Otherwise, consumer might calculate wrong things if it called dmaengine_tx_status() and dmaengine_terminate_all() consecutively. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Tested-by: Ryo Kodama <ryo.kodama.vz@renesas.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: rcar-dmac: ensure CHCR DE bit is actually 0 after clearingKuninori Morimoto2017-11-291-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DMAC reads data from source device, and buffered it until transferable size for sink device. Because of this behavior, DMAC is including buffered data . Now, CHCR DE bit is controlling DMA transfer enable/disable. If DE bit was cleared during data transferring, or during buffering, it will flush buffered data if source device was peripheral device (The buffered data will be removed if source device was memory). Because of this behavior, driver should ensure that DE bit is actually 0 after clearing. This patch adds new rcar_dmac_chcr_de_barrier() and call it after CHCR register access. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Tested-by: Ryo Kodama <ryo.kodama.vz@renesas.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | dmaengine: rcar-dmac: Make DMAC reinit during system resume explicitGeert Uytterhoeven2018-01-171-17/+7
|/ | | | | | | | | | | | | | | | | | The current (empty) system sleep callbacks rely on the PM core to force a runtime resume to reinitialize the DMAC registers during system resume. Without a reinitialization, e.g. SCIF DMA will hang silently after a system resume on R-Car Gen3. Make this explicit by using pm_runtime_force_{suspend,resume}() as the system sleep callbacks instead. Use SET_LATE_SYSTEM_SLEEP_PM_OPS() as DMA engines must be initialized before all DMA slave devices. Fixes: 17218e0092f8 "PM / genpd: Stop/start devices without pm_runtime_force_suspend/resume()" Suggested-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* dmaengine: rcar-dmac: initialize all data before registering IRQ handlerKuninori Morimoto2017-08-251-42/+43
| | | | | | | | | | | | | | | | Anton Volkov noticed that engine->dev is NULL before of_dma_controller_register() in probe. Thus there might be a NULL pointer dereference in rcar_dmac_chan_start_xfer while accessing chan->chan.device->dev which is equal to (&dmac->engine)->dev. On same reason, same and similar things will happen if we didn't initialize all necessary data before calling register irq function. To be more safety code, this patch initialize all necessary data before calling register irq function. Reported-by: Anton Volkov <avolkov@ispras.ru> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge tag 'dmaengine-4.13-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2017-07-081-6/+21
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull dmaengine updates from Vinod Koul: - removal of AVR32 support in dw driver as AVR32 is gone - new driver for Broadcom stream buffer accelerator (SBA) RAID driver - add support for Faraday Technology FTDMAC020 in amba-pl08x driver - IOMMU support in pl330 driver - updates to bunch of drivers * tag 'dmaengine-4.13-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (36 commits) dmaengine: qcom_hidma: correct API violation for submit dmaengine: zynqmp_dma: Remove max len check in zynqmp_dma_prep_memcpy dmaengine: tegra-apb: Really fix runtime-pm usage dmaengine: fsl_raid: make of_device_ids const. dmaengine: qcom_hidma: allow ACPI/DT parameters to be overridden dmaengine: fsldma: set BWC, DAHTS and SAHTS values correctly dmaengine: Kconfig: Simplify the help text for MXS_DMA dmaengine: pl330: Delete unused functions dmaengine: Replace WARN_TAINT_ONCE() with pr_warn_once() dmaengine: Kconfig: Extend the dependency for MXS_DMA dmaengine: mxs: Use %zu for printing a size_t variable dmaengine: ste_dma40: Cleanup scatterlist layering violations dmaengine: imx-dma: cleanup scatterlist layering violations dmaengine: use proper name for the R-Car SoC dmaengine: imx-sdma: Fix compilation warning. dmaengine: imx-sdma: Handle return value of clk_prepare_enable dmaengine: pl330: Add IOMMU support to slave tranfers dmaengine: DW DMAC: Handle return value of clk_prepare_enable dmaengine: pl08x: use GENMASK() to create bitmasks dmaengine: pl08x: Add support for Faraday Technology FTDMAC020 ...
| * dmaengine: rcar-dmac: wait for ISR to finish before freeing resourcesNiklas Söderlund2017-05-191-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes a race condition where the channel resources could be freed before the ISR had finished running resulting in a NULL pointer reference from the ISR. [ 167.148934] Unable to handle kernel NULL pointer dereference at virtual address 00000000 [ 167.157051] pgd = ffff80003c641000 [ 167.160449] [00000000] *pgd=000000007c507003, *pud=000000007c4ff003, *pmd=0000000000000000 [ 167.168719] Internal error: Oops: 96000046 [#1] PREEMPT SMP [ 167.174289] Modules linked in: [ 167.177348] CPU: 3 PID: 10547 Comm: dma_ioctl Not tainted 4.11.0-rc1-00001-g8d92afddc2f6633a #73 [ 167.186131] Hardware name: Renesas Salvator-X board based on r8a7795 (DT) [ 167.192917] task: ffff80003a411a00 task.stack: ffff80003bcd4000 [ 167.198850] PC is at rcar_dmac_chan_prep_sg+0xe0/0x400 [ 167.203985] LR is at rcar_dmac_chan_prep_sg+0x48/0x400 Based of previous work by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: rcar-dmac: implement device_synchronize()Niklas Söderlund2017-05-191-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Implement the device_synchronize() callback which wait until a dma channel is stopped to provide a synchronization point. This protects the driver from multiple race conditions when terminating and freeing resources. E.g. the completion callback still running after device_terminate_all() has completed. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: rcar-dmac: store channel IRQ in struct rcar_dmac_chanNiklas Söderlund2017-05-191-5/+8
| | | | | | | | | | | | | | | | | | | | The IRQ number is needed after probe to be able to add synchronisation points in other places in the driver when freeing resources and to implement a device_synchronize() callback. Store the IRQ number in the struct rcar_dmac_chan so that it can be used later. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | rcar-dmac: fixup descriptor pointer for descriptor modeKuninori Morimoto2017-05-301-0/+3
|/ | | | | | | | | | | In descriptor mode, the descriptor running pointer is not maintained by the interrupt handler, thus, driver finds the running descriptor from the descriptor pointer field in the CHCRB register. But, CHCRB::DPTR indicates *next* descriptor pointer, not current. Thus, The residue calculation will be missed. This patch fixup it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: enable descriptor mode on 40bitKuninori Morimoto2017-03-271-20/+32
| | | | | | | | | | | | | | SYS-DMAC can use 40bit address transfer, and it supports Descriptor Mode too. Current SYS-DMAC driver disables Descriptor Mode if it was 40bit address today. But it can use Descriptor Mode with 40bit if transfer Source/Destination address are located in same 4GiB region in the 40 bit address space. This patch enables it if all condition was clear Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge tag 'dmaengine-4.11-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2017-02-211-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull dmaengine updates from Vinod Koul: "This time we fairly boring and bit small update. - Support for Intel iDMA 32-bit hardware - deprecate broken support for channel switching in async_tx - bunch of updates on stm32-dma - Cyclic support for zx dma and making in generic zx dma driver - Small updates to bunch of other drivers" * tag 'dmaengine-4.11-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (29 commits) async_tx: deprecate broken support for channel switching dmaengine: rcar-dmac: Widen DMA mask to 40 bits dmaengine: sun6i: allow build on ARM64 platforms (sun50i) dmaengine: Provide a wrapper for memcpy operations dmaengine: zx: fix build warning dmaengine: dw: we do support Merrifield SoC in PCI mode dmaengine: dw: add support of iDMA 32-bit hardware dmaengine: dw: introduce register mappings for iDMA 32-bit dmaengine: dw: introduce block2bytes() and bytes2block() dmaengine: dw: extract dwc_chan_pause() for future use dmaengine: dw: replace convert_burst() with one liner dmaengine: dw: register IRQ and DMA pool with instance ID dmaengine: dw: Fix data corruption in large device to memory transfers dmaengine: ste_dma40: indicate granularity on channels dmaengine: ste_dma40: indicate directions on channels dmaengine: stm32-dma: Add error messages if xlate fails dmaengine: dw: pci: remove LPE Audio DMA ID dmaengine: stm32-dma: Add max_burst support dmaengine: stm32-dma: Add synchronization support dmaengine: stm32-dma: Fix residue computation issue in cyclic mode ...
| * dmaengine: rcar-dmac: Widen DMA mask to 40 bitsGeert Uytterhoeven2017-02-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | By default, the DMA mask covers only the low 32-bit address space, which causes SWIOTLB on arm64 to fall back to a bounce buffer for DMA transfers involving memory outside the 32-bit address space. The R-Car DMA controller hardware supports a 40-bit address space, hence widen the DMA mask to 40 bits to actually make use of this feature. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | dmaengine: rcar-dmac: unmap slave resource when channel is freedNiklas Söderlund2017-01-131-0/+8
|/ | | | | | | | | | | | The slave mapping should be removed together with other channel resources when the channel is freed. If it's not unmapped it will hang around forever after the channel is freed. Fixes: 9f878603dbdb7db3 ("dmaengine: rcar-dmac: add iommu support for slave transfers") Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge branch 'topic/iommu' into for-linusVinod Koul2016-10-031-22/+94
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| * dmaengine: rcar-dmac: add iommu support for slave transfersNiklas Söderlund2016-09-261-8/+74
| | | | | | | | | | | | | | | | | | Enable slave transfers to a device behind a IPMMU by mapping the slave addresses using the dma-mapping API. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: rcar-dmac: group slave configurationNiklas Söderlund2016-09-261-16/+22
| | | | | | | | | | | | | | | | | | | | | | Group slave address and transfer size in own structs for source and destination. This is in preparation for hooking up the dma-mapping API to the slave addresses. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | dmaengine: sh_rcar-dmac: convert callback to helper functionDave Jiang2016-08-081-9/+7
|/ | | | | | | | | | | This is in preperation of moving to a callback that provides results to the callback for the transaction. The conversion will maintain current behavior and the driver must convert to new callback mechanism at a later time in order to receive results. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: Fix residue reporting for pending descriptorsLaurent Pinchart2016-07-081-2/+29
| | | | | | | | | | | | | Cookies corresponding to pending transfers have a residue value equal to the full size of the corresponding descriptor. The driver miscomputes that and uses the size of the active descriptor instead. Fix it. Reported-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> [geert: Also check desc.active list] Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: Fixed active descriptor initializingMuhammad Hamza Farooq2016-07-081-0/+2
| | | | | | | | | | | Running descriptor pointer is set to NULL upon freeing resources. Other- wise, rcar_dmac_issue_pending might not start new transfers Signed-off-by: Muhammad Hamza Farooq <mfarooq@visteon.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: warn if transfer cannot start as TE = 1Niklas Söderlund2016-07-081-1/+1
| | | | | | | | | | | | | The documentation states one should make sure both DE and TE are cleared before starting a transaction. This patch extends the current warning to look at both DE and TE. Based on previous work from Muhammad Hamza Farooq. Suggested-by: Muhammad Hamza Farooq <mfarooq@visteon.com> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: use result of updated get_residue in tx_statusMuhammad Hamza Farooq2016-07-081-0/+4
| | | | | | | | | | | | | | The hardware might have complete the transfer but the interrupt handler might not have had a chance to run. If rcar_dmac_chan_get_residue() which reads HW registers finds that there is no residue return DMA_COMPLETE. Signed-off-by: Muhammad Hamza Farooq <mfarooq@visteon.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> [Niklas: add explanation in commit message] Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: use list_add() on rcar_dmac_desc_put()Kuninori Morimoto2016-05-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | For each descriptor, in addition to the memory used by the descriptors structure itself, the driver allocates a list of chunks as well as a buffer for hardware descriptors. Descriptors themselves are preallocated, and allocation of the chunks and buffer is performed the first time the descriptor is used. The memory isn't freed when the transfer is completed, as the chunks and buffer will be needed again when the descriptor is reused internally, so the driver keeps the memory around. If only a few descriptors are used concurrently, the current list_add_tail() implementation will result in all preallocated descriptors being used before going back to the first one, and will thus allocate chunks and a buffer for all preallocated descriptors. Using list_add() will put the complete descriptor at the head of the list of available descriptors, so the next transfer will be more likely to reuse a descriptor that already has associated memory instead of one that has never been used before. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: clear pertinence number of channelsKuninori Morimoto2016-03-031-1/+1
| | | | | | | | | | | DMACHCLR clears each channels, but its channel number is based on its SoC or IP. Current driver is using fixed 0x7fff (= for 15ch), it is not good match for Gen3 or Gen2 Audio DMAC. This patch fixes it Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge tag 'dmaengine-4.2-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2015-06-291-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull dmaengine updates from Vinod Koul: "This time we have support for few new devices, few new features and odd fixes spread thru the subsystem. New devices added: - support for CSRatlas7 dma controller - Allwinner H3(sun8i) controller - TI DMA crossbar driver on DRA7x - new pxa driver New features added: - memset support is bought back now that we have a user in xdmac controller - interleaved transfers support different source and destination strides - supporting DMA routers and configuration thru DT - support for reusing descriptors - xdmac memset and interleaved transfer support - hdmac support for interleaved transfers - omap-dma support for memcpy Others: - Constify platform_device_id - mv_xor fixes and improvements" * tag 'dmaengine-4.2-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (46 commits) dmaengine: xgene: fix file permission dmaengine: fsl-edma: clear pending interrupts on initialization dmaengine: xdmac: Add memset support Documentation: dmaengine: document DMA_CTRL_ACK dmaengine: virt-dma: don't always free descriptor upon completion dmaengine: Revert "drivers/dma: remove unused support for MEMSET operations" dmaengine: hdmac: Implement interleaved transfers dmaengine: Move icg helpers to global header dmaengine: mv_xor: improve descriptors list handling and reduce locking dmaengine: mv_xor: Enlarge descriptor pool size dmaengine: mv_xor: add support for a38x command in descriptor mode dmaengine: mv_xor: Rename function for consistent naming dmaengine: mv_xor: bug fix for racing condition in descriptors cleanup dmaengine: pl330: fix wording in mcbufsz message dmaengine: sirf: add CSRatlas7 SoC support dmaengine: xgene-dma: Fix "incorrect type in assignement" warnings dmaengine: fix kernel-doc documentation dmaengine: pxa_dma: add support for legacy transition dmaengine: pxa_dma: add debug information dmaengine: pxa: add pxa dmaengine driver ...
| * dmaengine: rcar-dmac: Use DECLARE_BITMAPJoe Perches2015-05-251-1/+1
| | | | | | | | | | | | | | Use the generic mechanism to declare a bitmap instead of unsigned long. Signed-off-by: Joe Perches <joe@perches.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | dmaengine: rcar-dmac: fixup spinlock in rcar-dmacKuninori Morimoto2015-05-221-16/+21
|/ | | | | | | | | | | | | | | | Current rcar-dmac driver is using spin_lock_irq() / spin_unlock_irq() in some functions. But, some other driver might call DMAEngine API during interrupt disabled. In such case, rcar-dmac side spin_unlock_irq() forcefully allows all interrupts. Therefore, other driver receives unexpected interruption, and its exclusive access control will be broken. This patch replaces spin_lock_irq() to spin_lock_irqsave(), and spin_unlock_irq() to spin_unlock_irqrestore(). Reported-by: Cao Minh Hiep <cm-hiep@jinso.co.jp> Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
* dmaengine: rcar-dmac: Disable channel 0 when using IOMMULaurent Pinchart2015-02-161-1/+16
| | | | | | | | | | | | | A still unconfirmed hardware bug prevents the IPMMU microTLB 0 to be flushed correctly, resulting in memory corruption. DMAC 0 channel 0 is connected to microTLB 0 on currently supported platforms, so we can't use it with the IPMMU. As the IOMMU API operates at the device level we can't disable it selectively, so ignore channel 0 for now if the device is part of an IOMMU group. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: Work around descriptor mode IOMMU errataLaurent Pinchart2015-02-161-0/+14
| | | | | | | | | | | When descriptor memory is accessed through an IOMMU the DMADAR register isn't initialized automatically from the first descriptor at beginning of transfer by the DMAC like it should. Initialize it manually with the destination address of the first chunk. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: Allocate hardware descriptors with DMAC deviceLaurent Pinchart2015-02-161-4/+4
| | | | | | | | | | | | When wired to an IOMMU to access data, the DMAC accesses the hardware descriptors through the IOMMU as well. We're using the DMA mapping API to allocate the descriptors, but with a NULL device at the moment, which prevents IOMMU mappings from being created. Fix this by passing the DMAC device instead. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: Fix oops due to unintialized list in error ISRLaurent Pinchart2015-02-161-10/+11
| | | | | | | | | | | The error interrupt handler stops and reinitializes all channels. This causes a crash for channels that have never been used, as their descriptor lists are uninitialized. Fix it by initializing the descriptor lists at probe time. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: Fix spinlock issues in interruptLaurent Pinchart2015-02-161-4/+4
| | | | | | | | | The rcar_dmac_desc_put() function is called in interrupt context and must thus use spin_lock_irqsave() instead of spin_lock_irq(). Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: Fix uninitialized variable usageLaurent Pinchart2015-02-121-38/+31
| | | | | | | | | | The desc variable is used uninitialized in the rcar_dmac_desc_get() and rcar_dmac_xfer_chunk_get() functions if descriptors need to be allocated. Fix it. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: rcar-dmac: Handle hardware descriptor allocation failureJürg Billeter2014-12-231-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If the atomic DMA coherent pool is too small, disable use of hardware descriptor lists instead of crashing the system: ERROR: 256 KiB atomic DMA coherent pool is too small! Please increase it with coherent_pool= kernel parameter! Unable to handle kernel NULL pointer dereference at virtual address 00000004 Internal error: Oops: a07 [#1] PREEMPT SMP ARM PC is at rcar_dmac_chan_reinit+0x3c/0x160 LR is at _raw_spin_lock_irqsave+0x18/0x5c [<802132c0>] (rcar_dmac_chan_reinit) from [<80214818>] (rcar_dmac_isr_error+0x84/0xa0) [<80214818>] (rcar_dmac_isr_error) from [<80060484>] (handle_irq_event_percpu+0x50/0x150) [<80060484>] (handle_irq_event_percpu) from [<800605c0>] (handle_irq_event+0x3c/0x5c) [<800605c0>] (handle_irq_event) from [<8006350c>] (handle_fasteoi_irq+0xb8/0x198) [<8006350c>] (handle_fasteoi_irq) from [<8005fdb0>] (generic_handle_irq+0x20/0x30) [<8005fdb0>] (generic_handle_irq) from [<8000fcd0>] (handle_IRQ+0x50/0xc4) [<8000fcd0>] (handle_IRQ) from [<800092cc>] (gic_handle_irq+0x28/0x5c) [<800092cc>] (gic_handle_irq) from [<80012700>] (__irq_svc+0x40/0x70) Kernel panic - not syncing: Fatal exception in interrupt Signed-off-by: Jürg Billeter <j@bitron.ch> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
* dmaengine: rcar-dmac: Cache hardware descriptors memoryLaurent Pinchart2014-12-231-20/+58
| | | | | | | | | | | | | | | | | | | | Unlike DMA transfers descriptors that are preallocated and cached, memory used to store hardware descriptors is allocated and freed with the DMA coherent allocation API for every transfer. Besides degrading performances, this creates a CMA stress test that seems to cause issues. Running dmatest with the noverify option produces [ 50.066539] alloc_contig_range test_pages_isolated(6b845, 6b846) failed [ 50.235180] alloc_contig_range test_pages_isolated(6b848, 6b84e) failed [ 52.964584] alloc_contig_range test_pages_isolated(6b847, 6b848) failed [ 54.127113] alloc_contig_range test_pages_isolated(6b843, 6b844) failed [ 56.270253] alloc_contig_range test_pages_isolated(6b84c, 6b850) failed The root cause needs to be fixed, but in the meantime, as a workaround and a performance improvement, cache hardware descriptors. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
* dmaengine: rcar-dmac: Implement support for hardware descriptor listsLaurent Pinchart2014-12-231-51/+253
| | | | | | | | | The DMAC supports hardware-based auto-configuration from descriptor lists. This reduces the number of interrupts required for processing a DMA transfer. Support that mode in the driver. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
* dmaengine: rcar-dmac: Add Renesas R-Car Gen2 DMA Controller (DMAC) driverLaurent Pinchart2014-12-231-0/+1503
The DMAC is a general purpose multi-channel DMA controller that supports both slave and memcpy transfers. The driver currently supports the DMAC found in the r8a7790 and r8a7791 SoCs. Support for compatible DMA controllers (such as the audio DMAC) will be added later. Feature-wise, automatic hardware handling of descriptors chains isn't supported yet. LPAE support is implemented. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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