| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | powerpc: Fix for getting CPU number in power_save_ppc32_restore() | Kumar Gala | 2008-09-03 | 1 | -1/+2 |
| | | | | | | | | | | | | | | | | | | | The calculation to get TI_CPU based off of SPRG3 was just plain wrong, meaning that we were getting garbage for the CPU number on 6xx/G3/G4 based SMP boxes in this code. Just offset off the stack pointer (to get to thread_info) like all the other references to TI_CPU do. This was pointed out by Chen Gong <G.Chen@freescale.com> [paulus@samba.org - use rlwinm r12,r11,... instead of rlwinm r12,r1,...; tophys()] Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org> | ||||
| * | powerpc/e500mc: flush L2 on NAP for e500mc | Kumar Gala | 2008-06-26 | 1 | -0/+9 |
| | | | | | | | | | | | | | If we have an L2CSR register (e500mc) we need to flush the L2 before going to nap. We use the HW flush mechanism provided in that register. The code reuses the CPU_FTR_604_PERF_MON bit as it is no longer used by any code in the kernel. Additionally we didn't reuse the exist L2CR feature bit as this is intended for the 7xxx L2CR register and L2CSR is part of the new Freescale "Book-E" registers. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> | ||||
| * | powerpc/85xx: add DOZE/NAP support for e500 core | Kumar Gala | 2008-06-26 | 1 | -0/+84 |
| The e500 core enter DOZE/NAP power-saving modes when the core go to cpu_idle routine. The power management default running mode is DOZE, If the user echo 1 > /proc/sys/kernel/powersave-nap the system will change to NAP running mode. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> | |||||
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index : blackbird-obmc-linux | |
| Blackbird™ Linux sources for OpenBMC | Raptor Computing Systems |
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