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* davinci: build list of unused EDMA events dynamicallySudhakar Rajashekhara2010-02-046-47/+43
| | | | | | | | | | | | | | | | Currently, the edma_noevent list is passed from platform data. But on some architectures, there will be many EDMA channels which will not be used at all. This patch scans all the platform devices and then builds a list of events which are not being used. The unused event list will be used to allocate EDMA channels in case of EDMA_CHANNEL_ANY usage instead of the edma_noevent being used earlier for this purpose. This patch is based on David Brownells's suggestion at http://article.gmane.org/gmane.linux.davinci/15176. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Fix edma_alloc_channel api for EDMA_CHANNEL_ANY caseSudhakar Rajashekhara2010-02-041-2/+4
| | | | | | | | | | | Though edma_alloc_channel api was looping through the available channel controllers in EDMA_CHANNEL_ANY case, it was never returning the channel for 2nd channel controller, if 1st channel controller had no free channels. This issue has been fixed with this patch. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Keep count of channel controllers on a platformSudhakar Rajashekhara2010-02-041-1/+3
| | | | | | | | | | | Some architectures have only one channel controller, but the edma_alloc_channel api loops twice to findout the free channel available in EDMA_CHANNEL_ANY case. A new variable has been introduced to keep count of number of channel controllers being used on a particular architecture. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: Correct return value of edma_alloc_channel apiSudhakar Rajashekhara2010-02-041-1/+1
| | | | | | | | | | | | | Currently, edma_alloc_channel api is returning the channel number without prepending the controller on which the channel was allocated. So, if a channel is allocated on 2nd controller, calls subsequent to edma_alloc_channel would never know that channel was allocated on the 2nd controller, and continue to operate on 1st controller, resulting in edma failure. This patch fixes this issue. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: add CDCE949 support on DM6467 EVMNageswari Srinivasan2010-02-042-1/+32
| | | | | | | | | | | | | | | | | | | | | | This patch adds the CDCE949 reference oscillator to the davinci clock list. On the DM6467T EVM, the CDCE949 is responsible for generating the pixel clock for display. On the DM6467 EVM, this pixel clock was being obtained from an internal source. This is not possible on the DM6467T EVM because of the presence of a 33MHz oscillator. The TSIF module also requires the CDCE949 to generate the data clocks. The actual clock definitions will be added by patches adding support for DM6467T VPIF and TSIF. This patch mearly lays the foundation for that work. Signed-off-by: Nageswari Srinivasan <nageswari@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: add support for CDCE949 clock synthesizerNageswari Srinivasan2010-02-042-0/+308
| | | | | | | | | | | | | | | | | | | | | | This patch adds support for TI's CDCE949 - a clock synthesizer with 4 PLLs and 9 outputs. It is used on DM6467 EVM. On the EVM, it generates clocks required for VPIF, TSIF and Audio modules. This patch adds it as part of the DaVinci clock framework. Testing: The various frequency outputs on Y1 have been tested using a out-of-tree VPIF video driver supporting HD video. The register values for Y5 frequency outputs have been derived from TSIF driver sources in MontaVista LSP kernel, but actual output has not been tested for lack of TSIF driver which actually works on the latest kernel. Signed-off-by: Nageswari Srinivasan <nageswari@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: da850/omap-l138 EVM: register for suspend supportSekhar Nori2010-02-041-0/+17
| | | | | Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: da850/omap-l138: add support for SoC suspendSekhar Nori2010-02-043-0/+44
| | | | | | | | | | | | | | | | | | This patch adds support for registering for suspend-to-RAM functionality on da850/omap-l138 SoCs. da850 supports wakeup based on external event and RTC alarm. Currently only RTC alarm based wakeup is supported. Support for wakeup based on external event will be added as later improvements. For scheduling an alarm event on RTC some useful code is present in Documentation/rtc.txt Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: add power management supportSekhar Nori2010-02-045-0/+438
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds core power management (suspend-to-RAM) support for DaVinci SoCs. The code depends on the the "deepsleep" feature to suspend the SoC and saves power by gating the input clock. The wakeup can be based on an external event as supported by the SoC. Assembly code (in sleep.S) is added to aid gating DDR2 clocks. Code doing this work should not be accessing DDR2. The assembly code is relocated to SRAM by the code in pm.c The support has been validated on DA850/OMAP-L138 only though the code is (hopefully) generic enough that other SoCs supporting deepsleep feature simply requires SoC specific code to start using this driver. Note that all the device drivers don't support suspend/resume still and are being worked on. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* DaVinci: DM365: Changing default queue for DM365.Sandeep Paulraj2010-02-041-1/+1
| | | | | | | | | In DM365 Q0, Q1 and Q2 are used by codecs. LSP drivers should use Q3. This patch changes the default queue for DM365. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: clock: Check CLK_PSC flag before disabling PSCChaithrika U S2010-02-041-1/+2
| | | | | | | | | | | | Some modules do not have PSC to control their clocks. The 'lpsc' field in the clk structure is 0 for such clocks. In the clock disable function check for CLK PSC flag before disabling the PSC. If this is not taken care of then it may so happen that module controlled by LPSC 0 is erroneously disabled. Signed-off-by: Chaithrika U S <chaithrika@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* TI Davinci EMAC : Re-use driver for other platforms.Sriramakrishnan2010-02-046-41/+5
| | | | | | | | | | | | The davinci EMAC peripheral is also available on other TI platforms -notably TI AM3517 SoC. This patch modifies the config option and the platform structure header files so that the driver can be reused on non-davinci platforms as well. Signed-off-by: Sriramakrishnan <srk@ti.com> Acked-by: Chaithrika U S <chaithrika@ti.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: da850/omap-l138: Enable 4-bit eccSudhakar Rajashekhara2010-02-041-0/+1
| | | | | | | | This patch initializes the platform data to enable 4-bit ecc support on DA850/OMAP-L138. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: da850/omap-l138: Modify NOR partition infoSudhakar Rajashekhara2010-02-041-1/+13
| | | | | | | | | | | | | On DA850/OMAP-L138, NOR flash partition was starting from offset ZERO erasing the UBL and u-boot when the complete NOR is erased. This patch moves the start of the partition to 512K, after the bootloaders and u-boot env variables. This patch also creates a new partition on NOR Flash to store Linux kernel image. Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: move /proc/davinci_clocks to debugfsSekhar Nori2010-02-041-31/+11
| | | | | | | | | | | Move /proc/davinci_clocks to /sys/kernel/debug/davinci_clocks (debugfs). debugfs is more suited for this since the clock dump is debug information. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: make /proc/davinci_clocks display multi-rooted clock treeSekhar Nori2010-02-041-4/+7
| | | | | | | | | | | | This patch modifies clock dump to take care of clock tress rooted at multiple oscillators. Current code assumes the entire tree is rooted on a single oscillator. When using off-chip clock synthesizers, some of the clocks can be obtained from a different on-board oscillator. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: add support for DM6467T EVMSekhar Nori2010-02-044-2/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DM6467T (T for Turbo) is a newer and faster DM6467 part from TI. The new part supports 1080p video and has the ARM running at 495MHz. More SoC information: http://focus.ti.com/docs/prod/folders/print/tms320dm6467t.html Spectrum Digital, Inc has a new EVM for this part. It is _mostly_ same as the older DM6467 EVM except for a 33MHz crystal input and THS8200 video encoder for 1080p support. The meat of this patch is dedicated to initializing the crystal frequency from EVM board file. Additional notes: I did consider some alternative ways to make the crystal input board specific including - (1) having board code initialize the crystal frequency using the first member of soc_info->cpu_clks array (2) introducing a new ref_clk_rate member in soc_info structure. But, the current way seems to be the simplest and least intruding considering that both the clock array and SoC info structure are actually private to the SoC file. Also the fact that davinci_common_init() initializes both the soc_info and clocks in one go. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: board-dm646x-evm.c: arrange related code togetherSekhar Nori2010-02-041-45/+45
| | | | | | | | | | | | | Currently all the #defines and static variables in the board-dm646x-evm.c file are located right at the start of the file because of which the related code is not together - making reading the code difficult. This patch moves around the code keeping related code together. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: explain CLOCK_TICK_RATE of 27MHz in include/mach/timex.hSekhar Nori2010-02-041-1/+6
| | | | | | | | | | | | Leave a comment explaining the constant value of 27Mhz used in include/mach/timex.h for all DaVinci platforms. Many of the platforms actually run at 24MHz timer frequency (Eg. EVMs of DM355, DM365 and OMAP-L1). The comment also serves as a porting alert. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: da850/omap-l138: create static map for SRAMSekhar Nori2010-02-042-0/+9
| | | | | | | | | | | | | Create static map for internal SRAM and populate SRAM base and size in soc_info structure to allow SRAM allocation functions from arch/arm/mach-davinci/sram.c to work. On DA850 SRAM is used for suspend-to-RAM implementation in places where DDR2 cannot be accessed as its clocks are stopped. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: da850/omap-l138: unlock PLL registers during initSekhar Nori2010-02-041-6/+13
| | | | | | | | | | | | | | | | | On omap-l1 devices the PLL registers can be locked from writes. Currently the cpufreq rate setting code unlocks PLL0 before the write actually happens. With suspend support getting added PLL1 registers need be be unlocked as well. To facilitate this, unlock both PLLs during the init time itself. This also obviates the need to unlock PLL registers for each CPUFreq transtition. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: cpuidle: move mapping of DDR2 controller registers out of driverSekhar Nori2010-02-044-30/+21
| | | | | | | | | | | When suspend is supported, both cpuidle and suspend code need to work on DDR2 registers. Instead of mapping the DDR2 registers twice, do it once outside of cpuidle driver and let cpuidle driver get the virtual base address of DDR2 registers. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: make it possible to include clock.h and psc.h in assembly codeSekhar Nori2010-02-042-3/+11
| | | | | | | | | | | | | psc.h contains register defines for PSC module which need to be accessed in assembly code which helps the DA850/OMAP-L138 SoC go to sleep. Shutting down DDR clock using PSC is a part of the sleep procedure. Also, the PLL related hardware definitions in clock.h are needed in assembly code to bypass the DDR2 PLL. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: move PSC register definitions from psc.c to psc.hSekhar Nori2010-02-042-11/+11
| | | | | | | | | | | | | | The motivation behind the change is to use the same definitions in the assembly code responsible for suspending the SoC, a part of which is to clock gate the DDR2 clock. Note that the assembly code cannot invoke the C function meant for this. The main reason being that stack in DDR2 cannot be accessed while DDR2 clock is being clock gated. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: move DDR2 controller defines to memory.hSekhar Nori2010-02-042-4/+5
| | | | | | | | | | | Move defintions of DDR2 controller registers to memory.h from cpuidle.c. The motivation behind the change is to be able to use these defintions in assembly code that puts DDR2 in self-refresh and enables the SoC to enter suspend state. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: move PLL wait time values to clock.hSekhar Nori2010-02-042-12/+18
| | | | | | | | | | | | | As suspend support is added, the code supporting the suspend operation needs to bypass PLLs and needs to access the same wait time values as the PLL code in clock.c. To facilitate this, move the PLL wait times to clock.h where they can be accessed by suspend code. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* davinci: da8xx/omapl1: add support for the second sysconfig moduleSekhar Nori2010-02-046-19/+28
| | | | | | | | | | | | | OMAP-L138 adds a second SYSCFG region having useful functionality like deep sleep, pull up/down control and SATA clock stop. This patch makes provision for accessing registers from second SYSCFG region in da8xx code. Note that OMAP-L137 has a single SYSCFG region. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* DaVinci - Adding platform & board changes for vpfe capture on DM365Murali Karicheri2010-02-043-1/+174
| | | | | | | | | | | | This patch adds following changes:- 1) add sub device configuration data for TVP5146 used by vpfe capture 2) registers platform devices for vpfe_capture, isif and vpss 3) defines hardware resources for the devices listed under 2) 4) defines clock aliase for isif driver 5) adding setup_pinmux() for isif Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
* [ARM] Update mach-typesRussell King2010-01-281-1/+59
| | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* Merge branch 'fix' of ↵Russell King2010-01-283-6/+15
|\ | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6
| * [ARM] pxa: fix irq suspend/resume for pxa25xEric Miao2010-01-131-4/+10
| | | | | | | | | | | | | | PXA25x does not have IPR registers, saving and restoring should happen only for pxa27x and pxa3xx. Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * [ARM] pxa: fix the incorrect naming of AC97 reset pin config for pxa26xEric Miao2010-01-131-2/+4
| | | | | | | | | | | | | | GPIO89_AC97_nRESET is really a PXA26x specific option and was incorrectly named. Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
| * [ARM] pxa/corgi: fix incorrect default GPIO for UDC VbusEric Miao2010-01-131-0/+1
| | | | | | | | | | | | | | There is no such GPIO for udc vbus sensing, put '-1' instead of default '0' as '0' does mean a valid GPIO. Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* | Merge branch 'for-rmk' of git://git.marvell.com/orionRussell King2010-01-274-6/+118
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| * | [ARM] orion5x: D-link DNS-323 rev. B1 power-offErik Benada2010-01-241-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes power LED blinking and power-off on DNS-323 rev. B1. GPIO pin 3 has to be set to 1 to stop power LED blinking and to allow the LED to be controlled via leds-gpio. This pin has to be also set to 1 for power-off to work. To power-off the rev. B1 machine, pin 8 has to be set to 1 and then set to 0 to do actual power-off. Tested on my DNS-323 rev. B1 Signed-off-by: Erik Benada <erikbenada@yahoo.ca> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * | [ARM] Orion5x: add GPIO LED and buttons for wrt350n v2Dirk Teurlings2010-01-131-0/+79
| | | | | | | | | | | | | | | | | | Signed-off-by: Dirk Teurlings <dirk@upexia.nl> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * | [ARM] Kirkwood: drive USB VBUS pin on rd88f6192-nas high on bootSaeed Bishara2010-01-101-0/+6
| | | | | | | | | | | | | | | | | | Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
| * | [ARM] Orion: fix PCIe inbound window programming when RAM size is not a ↵Lennert Buytenhek2009-12-281-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | power of two The PCIe inbound window size is supposed to be a power of two. If the total amount of RAM installed in the system is not a power of two, round it up such that it is. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Signed-off-by: Nicolas Pitre <nico@marvell.com>
* | | Merge branch 'omap-fixes-for-linus' of ↵Linus Torvalds2010-01-2523-131/+229
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6 * 'omap-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (25 commits) OMAP2/3: DMTIMER: Clear pending interrupts when stopping a timer PM debug: Fix warning when no CONFIG_DEBUG_FS OMAP3: PM: DSS PM_WKEN to refill DMA OMAP: timekeeping: time should not stop during suspend OMAP3: PM: Force write last pad config register into save area OMAP: omap3_pm_get_suspend_state() error ignored in pwrdm_suspend_get() OMAP3: PM: Enable wake-up from McBSP2, 3 and 4 modules OMAP3: PM debug: fix build error when !CONFIG_DEBUG_FS OMAP3: PM: Removing redundant and potentially dangerous PRCM configration OMAP3: Fixed ARM aux ctrl register save/restore OMAP3: CPUidle: Fixed timer resolution OMAP3: PM: Remove duplicate code blocks OMAP3: PM: Disable interrupt controller AUTOIDLE before WFI OMAP3: PM: Enable system control module autoidle OMAP3: PM: Ack pending interrupts before entering suspend omap: Enable GPMC clock in gpmc_init OMAP1 clock: fix for "BUG: spinlock lockup on CPU#0" OMAP4: clocks: Fix the clksel_rate struct DPLL divs OMAP4: PRCM: Fix the base address for CHIRONSS reg defines OMAP: dma_chan[lch_head].flag & OMAP_DMA_ACTIVE tested twice in omap_dma_unlink_lch() ...
| * | | OMAP2/3: DMTIMER: Clear pending interrupts when stopping a timerTero Kristo2010-01-211-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP GP timers keep running for a few cycles after they are stopped, which can cause the timer to expire and generate an interrupt. The pending interrupt will prevent e.g. OMAP from entering suspend, thus we ack it manually. Only applicable on OMAP2/3/4. Signed-off-by: Tero Kristo <tero.kristo@nokia.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | Merge branch 'omap-fixes' into omap-fixes-for-linusTony Lindgren2010-01-206-31/+66
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| | * | | omap: Enable GPMC clock in gpmc_initOlof Johansson2010-01-201-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Don't assume that gpmc_l3_clk is on, enable it before touching configuration registers. Note that the current code assumes that this clock is always enabled. We are already setting smart idle and L3 autogating for GPMC clock in gpmc_init. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | OMAP: dma_chan[lch_head].flag & OMAP_DMA_ACTIVE tested twice in ↵Roel Kluin2010-01-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap_dma_unlink_lch() The same flag and bits were tested twice. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | omap3: Fix cpu detectionTony Lindgren2010-01-192-18/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to set the omap_chip.oc carefully for the clocks to work. To fix this, set the omap_chip.oc in omap3_check_features() based on the CONTROL_IDCODE and silicon revision registers. Also add handling for 34xx es3.1.2 as es3.1 for now. Fixes booting on at least overo board. Based on an earlier patch by Paul Walmsley <paul@pwsan.com>. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | omap: Fix functions for dynamic remuxing of pinsTony Lindgren2010-01-192-11/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the omap_mux_read and write available for board code, and rename omap_mux_set_board_signals into omap_mux_write_array. Also add the related prototypes and comments into mux.h. In some cases we want to change the signals dynamically, mostly for power management. Note that we cannot use the signal names as they are set __init to save memory. Signed-off-by: Tony Lindgren <tony@atomide.com>
| | * | | omap: Fix cmdline muxingTony Lindgren2010-01-191-2/+5
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Looks like cmdline muxing got broken at some point when we decided to limit muxing to __init code. Currently omap_mux_entry list is not yet initialized when we try to initialize cmdline muxing. Fix this by calling omap_mux_init_list() before calling omap_mux_set_cmdline_signals(). Reported-by: Philip Balister <philip@balister.org> Tested-by: Philip Balister <philip@balister.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
| * | | Merge branch 'pm-fixes' of ↵Tony Lindgren2010-01-209-45/+95
| |\ \ \ | | | | | | | | | | | | | | | master.kernel.org:/pub/scm/linux/kernel/git/khilman/linux-omap-pm into omap-fixes-for-linus
| | * | | PM debug: Fix warning when no CONFIG_DEBUG_FSSergio Aguirre2010-01-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following warning when CONFIG_DEBUG_FS wasn't selected: arch/arm/mach-omap2/pm-debug.c:57: warning: 'pm_dbg_init' declared 'static' but never defined Signed-off-by: Sergio Aguirre <saaguirre@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | | OMAP3: PM: DSS PM_WKEN to refill DMASubramani Venkatesh2010-01-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, DSS does not wakeup when there is a DMA request. DSS wake up event must be enabled so that the DMA request to refill the FIFO will wake up the CORE domain. Signed-off-by: Subramani Venkatesh <subramani.venkatesh@windriver.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
| | * | | OMAP: timekeeping: time should not stop during suspendKevin Hilman2010-01-201-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During suspend, the kernel timekeeping subsystem is shut down. Before suspend and upon resume, it uses a weak function read_persistent_clock() to determine the amount of time that elapsed during suspend. This function was not implemented on OMAP, so from the timekeeping subsystem perspective (and thus userspace as well) it appeared that no time elapsed during suspend. This patch uses the 32k sync timer as a the persistent clock. NOTE: This does *NOT* fully handle wrapping of the 32k sync timer, so more than one wrapping of the 32k sync timer during suspend may cause problems. Also note there are not interrupts when the 32k sync timer wraps, so something else has to be done. Reported-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
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