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* OMAP2 clock/powerdomain: off by 1 error in loop timeout comparisonsRoel Kluin2009-06-191-1/+1
| | | | | | | | with while (i++ < MAX_CLOCK_ENABLE_WAIT); i can reach MAX_CLOCK_ENABLE_WAIT + 1 after the loop, so if (i == MAX_CLOCK_ENABLE_WAIT) that's still success. Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* [ARM] OMAP3 pwrdm: add hardware save-and-restore (SAR) supportPaul Walmsley2008-08-211-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP3430ES2+ introduces a new feature: optional powerdomain context hardware save-and-restore (SAR). Currently, this feature only applies to USBHOST and USBTLL module context when the USBHOST or CORE powerdomains enter a low-power sleep state[1]. This feature avoids re-enumeration of USB devices when the powerdomains return from idle, which is potentially time-consuming. This patch adds support for enabling and disabling hardware save-and-restore to the powerdomain code. Three new functions are added, pwrdm_enable_hdwr_sar(), pwrdm_disable_hdwr_sar(), and pwrdm_can_hdwr_sar(). A new struct powerdomain "flags" field is added, with a PWRDM_HAS_HDWR_SAR flag to indicate powerdomains with SAR support. Thanks to Jouni Högander <jouni.hogander@nokia.com> for reviewing an earlier version of these patches, and Richard Woodruff <r-woodruff2@ti.com> for clarifying the purpose of these bits. 1. For the USBHOST controller module, context loss occurs when the USBHOST powerdomain enters off-idle. For USBTLL, context loss occurs either if CORE enters off-idle, or if the CORE logic is configured to turn off when CORE enters retention-idle (OSWR). 34xx ES2 TRM 4.8.6.1.1, 4.8.6.1.2 Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: OMAP2: Clockdomain: Connect clockdomain code to powerdomain codePaul Walmsley2008-08-191-0/+136
| | | | | | | | | | | | | | | Thie patch adds code to the powerdomain layer to track the clockdomains associated with each powerdomain. It also modifies the clockdomain code to register clockdomains with their corresponding powerdomain when the clockdomain is registered. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP2: Powerdomain: Add base OMAP2/3 powerdomain codePaul Walmsley2008-08-191-0/+909
This patch creates an interface to the powerdomain registers in the PRM/CM modules on OMAP2/3. This interface is intended to be used by PM code, e.g., pm.c; not by device drivers directly. Each powerdomain will be defined in later patches as static structures. Also defined are dependencies between powerdomains, used for adding and removing PM_WKDEP and CM_SLEEPDEP bits. The powerdomain structures are linked into a list at boot by pwrdm_register(), similar to the OMAP clock code. The patch adds a Kconfig option, CONFIG_OMAP_DEBUG_POWERDOMAIN, which when enabled will emit verbose debug messages via pr_debug(). Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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