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* arm: dts: fix unit-address leading 0sRob Herring2017-10-201-4/+4
| | | | | | | | | | | | | Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h headerChen-Yu Tsai2017-03-271-1/+0
| | | | | | | | | | | | | | | | | All dts files for the sunxi platform have been switched to the generic pinconf bindings. As a result, the sunxi specific pinctrl macros are no longer used. Remove the #include entry with the following command: sed --follow-symlinks -i -e '/pinctrl\/sun4i-a10.h/D' \ arch/arm/boot/dts/sun?i*.* arch/arm/boot/dts/sun9i-a80.dtsi was then edited to remove the extra empty line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: gr8: Use common sun5i DTSIMaxime Ripard2017-03-061-588/+29
| | | | | | | | | | | Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of the extra nodes defined there actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it, and include the sun5i DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2017-02-251-464/+56
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The usual collection of new drivers, non-critical fixes, and updates to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits) clk: renesas: mstp: ensure register writes complete clk: qcom: Do not drop device node twice clk: mvebu: adjust clock handling for the CP110 system controller clk: mvebu: Expand mv98dx3236-core-clock support clk: zte: add i2s clocks for zx296718 clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i clk: sunxi-ng: Check kzalloc() for errors and cleanup error path clk: tegra: Add BPMP clock driver clk: uniphier: add eMMC clock for LD11 and LD20 SoCs clk: uniphier: add NAND clock for all UniPhier SoCs ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: qcom: SDHCI enablement on Nexus 5X / 6P ...
| * ARM: gr8: Convert to CCUMaxime Ripard2017-01-231-464/+56
| | | | | | | | | | | | | | Now that we have a driver for the GR8, we can convert our DT to it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sunxi: Convert pinctrl nodes to generic bindingsMaxime Ripard2016-12-261-42/+42
| | | | | | | | | | | | | | | | Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* | ARM: sunxi: Remove useless allwinner,pull propertyMaxime Ripard2016-12-261-19/+0
| | | | | | | | | | | | | | | | | | | | | | | | The allwinner,pull property set to NO_PULL was really considered our default (and wasn't even changing the default value in the code). Remove these properties to make it obvious that we do not set anything in such a case. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* | ARM: sunxi: Remove useless allwinner,drive propertyMaxime Ripard2016-12-261-19/+0
|/ | | | | | | | | The allwinner,drive property set to 10mA was really considered as our default. Remove all those properties entirely to make that obvious. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: gr8: Add UART3 pinsMaxime Ripard2016-11-221-0/+14
| | | | | | | The UART3 pins were missing from the DTSI. Add them. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: gr8: Add UART2 pinsMaxime Ripard2016-11-221-0/+14
| | | | | | | The UART2 pins were missing from the DTSI. Add them. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: gr8: Add missing pwm channel 1 pinMaxime Ripard2016-11-221-0/+7
| | | | | | | | The PWM controller has two different channels, but only the first pin was exposed in the DTSI. Add the other one. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: gr8: Fix typo in the i2s mclk pin groupMaxime Ripard2016-11-221-1/+1
| | | | | | | There was a dumb copy and paste mistake here, fix it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: gr8: Add the UART3Maxime Ripard2016-11-221-0/+10
| | | | | | | | The GR8 has access to the UART3 controller, which was missing in the DTSI. Add it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: gr8: Rename the DTSI and relevant DTSMaxime Ripard2016-11-221-0/+1087
Reviews have found that sun5i was a better prefix after all for the GR8. Rename the relevant device trees before it's too late. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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