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* ARM: dts: augment Ux500 to use DT cpufreqLinus Walleij2017-08-221-7/+8
| | | | | | | | | This adds the operating points to the Ux500 device tree and deletes the old special-purpose cpufreq node, as we can now use the generic DT cpufreq driver. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge back cpufreq core changes for v4.12.Rafael J. Wysocki2017-04-151-5/+0
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| * cpufreq: dbx500: Manage cooling device from cpufreq driverViresh Kumar2017-03-161-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The best place to register the CPU cooling device is from the cpufreq driver as we would know if all the resources are already available or not. That's what is done for the cpufreq-dt.c driver as well. The cpu-cooling driver for dbx500 platform was just (un)registering with the thermal framework and that can be handled easily by the cpufreq driver as well and in proper sequence as well. Get rid of the cooling driver and its its users and manage everything from the cpufreq driver instead. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
* | ARM: dts: add the AB8500 clocks to the device treeLinus Walleij2017-03-131-0/+19
|/ | | | | | | | | | This adds the AB8500 clocks to the device tree using the new bindings from the clk subsystem, making audio work again. Cc: Lee Jones <lee.jones@linaro.org> Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: dts: add the AB8500 sysclk to the device treesLinus Walleij2017-01-311-0/+2
| | | | | | | | | This clock has been missing since some early stages of device tree conversion. Adding the right clocks to the device tree makes USB work again. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: dts: Ux500: move compatible string to chipsetLinus Walleij2016-06-081-0/+1
| | | | | | | | Move the compatible string "stericsson,ab8500" from the board definitions into the main node in the chipset file where it belongs. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: dts: ux500: use the GIC include headerLinus Walleij2016-03-291-45/+46
| | | | | | | | Use the <dt-bindings/interrupt-controller/arm-gic.h> header for generating the flags for the first cell of the interrupt definitions. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: dts: ux500: use the GPIO DT headerLinus Walleij2016-03-291-0/+1
| | | | | | | | | | | Use the <dt-bindings/gpio/gpio.h> header instead of using hardcoded values for the GPIO flags. Eradicate the totally bogus "0x4" flag used and set that to GPIO_ACTIVE_HIGH as is proper, switch the inverted card detect on the Snowball to flag using GPIO_ACTIVE_LOW instead of using the MMC-specific inversion flag. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: remove regulator-compatible usageJavier Martinez Canillas2015-11-171-33/+0
| | | | | | | | | | | The regulator-compatible property from the regulator DT binding was deprecated and the correct approach is to use the node's name. This patch has no functional changes since the values of the node's name and the regulator-compatible match for all the regulators. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Merge tag 'pinctrl-v4.3-1' of ↵Linus Torvalds2015-09-041-10/+13
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v4.3 development cycle. Like with GPIO it's a lot of stuff. If my subsystems are any sign of the overall tempo of the kernel v4.3 will be a gigantic diff. [ It looks like 4.3 is calmer than 4.2 in most other subsystems, but we'll see - Linus ] Core changes: - It is possible configure groups in debugfs. - Consolidation of chained IRQ handler install/remove replacing all call sites where irq_set_handler_data() and irq_set_chained_handler() were done in succession with a combined call to irq_set_chained_handler_and_data(). This series was created by Thomas Gleixner after the problem was observed by Russell King. - Tglx also made another series of patches switching __irq_set_handler_locked() for irq_set_handler_locked() which is way cleaner. - Tglx also wrote a good bunch of patches to make use of irq_desc_get_xxx() accessors and avoid looking up irq_descs from IRQ numbers. The goal is to get rid of the irq number from the handlers in the IRQ flow which is nice. Driver feature enhancements: - Power management support for the SiRF SoC Atlas 7. - Power down support for the Qualcomm driver. - Intel Cherryview and Baytrail: switch drivers to use raw spinlocks in IRQ handlers to play nice with the realtime patch set. - Rework and new modes handling for Qualcomm SPMI-MPP. - Pinconf power source config for SH PFC. New drivers and subdrivers: - A new driver for Conexant Digicolor CX92755. - A new driver for UniPhier PH1-LD4, PH1-Pro4, PH1-sLD8, PH1-Pro5, ProXtream2 and PH1-LD6b SoC pin control support. - Reverse-egineered the S/PDIF settings for the Allwinner sun4i driver. - Support for Qualcomm Technologies QDF2xxx ARM64 SoCs - A new Freescale i.mx6ul subdriver. Cleanup: - Remove platform data support in a number of SH PFC subdrivers" * tag 'pinctrl-v4.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (95 commits) pinctrl: at91: fix null pointer dereference pinctrl: mediatek: Implement wake handler and suspend resume pinctrl: mediatek: Fix multiple registration issue. pinctrl: sh-pfc: r8a7794: add USB pin groups pinctrl: at91: Use generic irq_{request,release}_resources() pinctrl: cherryview: Use raw_spinlock for locking pinctrl: baytrail: Use raw_spinlock for locking pinctrl: imx6ul: Remove .owner field pinctrl: zynq: Fix typos in smc0_nand_grp and smc0_nor_grp pinctrl: sh-pfc: Implement pinconf power-source param for voltage switching clk: rockchip: add pclk_pd_pmu to the list of rk3288 critical clocks pinctrl: sun4i: add spdif to pin description. pinctrl: atlas7: clear ugly branch statements for pull and drivestrength pinctrl: baytrail: Serialize all register access pinctrl: baytrail: Drop FSF mailing address pinctrl: rockchip: only enable gpio clock when it setting pinctrl/mediatek: fix spelling mistake in dev_err error message pinctrl: cherryview: Serialize all register access pinctrl: UniPhier: PH1-Pro5: add I2C ch6 pin-mux setting pinctrl: nomadik: reflect current input value ...
| * pinctrl/ARM: move GPIO and pinctrl deps to device treeLinus Walleij2015-07-271-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This gets the GPIO ranges out of the driver and into the device tree where they belong. Standard DT bindings already exist for this. Since no systems with this are deployed we can just augment all device trees and the drivers at the same time and simplify the world. This also defines the array of GPIO chips related to the pin controller. Cc: arm@kernel.org Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | Merge tag 'clk-for-linus-4.3' of ↵Linus Torvalds2015-08-311-0/+7
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Michael Turquette: "The clk framework changes for 4.3 are mostly updates to existing drivers and the addition of new clock drivers. Stephen Boyd has also done a lot of subsystem-wide driver clean-ups (thanks!). There are also fixes to the framework core and changes to better split clock provider drivers from clock consumer drivers" * tag 'clk-for-linus-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (227 commits) clk: s5pv210: add missing call to samsung_clk_of_add_provider() clk: pistachio: correct critical clock list clk: pistachio: Fix PLL rate calculation in integer mode clk: pistachio: Fix override of clk-pll settings from boot loader clk: pistachio: Fix 32bit integer overflows clk: tegra: Fix some static checker problems clk: qcom: Fix MSM8916 prng clock enable bit clk: Add missing header for 'bool' definition to clk-conf.h drivers/clk: appropriate __init annotation for const data clk: rockchip: register pll mux before pll itself clk: add bindings for the Ux500 clocks clk/ARM: move Ux500 PRCC bases to the device tree clk: remove duplicated code with __clk_set_parent_after clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw) clk: Constify clk_hw argument to provider APIs clk: Hi6220: add stub clock driver dt-bindings: clk: Hi6220: Document stub clock driver dt-bindings: arm: Hi6220: add doc for SRAM controller clk: atlas7: fix pll missed divide NR in fraction mode clk: atlas7: fix bit field and its root clk for coresight_tpiu ...
| * | clk/ARM: move Ux500 PRCC bases to the device treeLinus Walleij2015-08-241-0/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | The base addresses for the Ux500 PRCC controllers are hardcoded, let's move them to the clock node in the device tree and delete the constants. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | ARM: ux500: add an SMP enablement type and move cpu nodesLinus Walleij2015-08-061-26/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "cpus" node cannot be inside the "soc" node, while this works for the CoreSight blocks, the early boot code will look for "cpus" directly under the root node, so this is a hard convention. So move the CPU nodes. Augment the "reg" property to match what is actually in the hardware: 0x300 and 0x301 respectively. Then add an SMP enablement type to be used by the SMP init code, "ste,dbx500-smp". Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* | ARM: ux500: define serial port aliasesLinus Walleij2015-07-141-3/+3
|/ | | | | | | | | | | This enumerates the PL011 serial ports on the Ux500. This is necessary to do if we want to remove one of the serial ports, since userspace depends on console to be present on ttyAMA2 and we must not break userspace. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: ux500: define the backupram in the device treeLinus Walleij2015-05-181-0/+9
| | | | | | | | The Ux500 SOCs have a special backup RAM that needs to be defined in the device tree. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: add SCU and WD to device treeLinus Walleij2015-05-151-0/+12
| | | | | | | | | The Ux500 like other Cortex-A9 SoC's has a Snoop Control Unit (SCU) and a Watchdog in the same address range as the local timers. Add these to the SoC device tree. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge tag 'ux500-v4.2-dt' of ↵Arnd Bergmann2015-05-131-0/+154
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/dt Merge "Ux500 Device Tree changes for the v4.2 series" form Linus Walleij: Define CPU topology, connect that with CoreSight blocks, add sensor information to DT boards. * tag 'ux500-v4.2-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson: ARM: ux500: add the sensors to the STUIB board ARM: ux500: assign the sensor trigger IRQs ARM: ux500: fix lsm303dlh magnetometer compat string ARM: ux500: add CoreSight blocks to DTS file ARM: ux500: define CPU topology
| * ARM: ux500: add CoreSight blocks to DTS fileLinus Walleij2015-05-131-0/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This registers all the CoreSight blocks on the DB8500 SoC: each core has a PTM (v1.0, r1p0-00rel0) connected, both connected to a funnel (DK-TM908-r0p1-00rel0) which in turn connects to a replicator (DM-TM909-r0p1-00rel0). The replicator has two outputs, port 0 to a TPIU interface and port 1 to an ETB (DK-TM907-r0p3-00rel0). The CoreSight blocks are all clocked by the APEATCLK from the PRCMU and their AHB interconnect is clocked from a separate clock called APETRACECLK. The SoC also has a CTI/CTM block which can be added later as we have upstream support in the CoreSight subsystem. Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: ux500: define CPU topologyLinus Walleij2015-04-271-0/+26
| | | | | | | | | | | | | | The CPU topology is unspecified for Ux500 but will be needed for things like CoreSight. Let's just add it. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* | ARM: ux500: Move GPIO regulator for SD-card into board DTSsUlf Hansson2015-04-271-17/+0
|/ | | | | | | | | | | The GPIO regulator for the SD-card isn't a ux500 SOC configuration, but instead it's specific to the board. Move the definition of it, into the board DTSs. Fixes: c94a4ab7af3f ("ARM: ux500: Disable the MMCI gpio-regulator by default") Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Add i2c devices to the VAPE PM domainUlf Hansson2014-10-281-0/+5
| | | | | | | | The i2c-nomadik driver handle these devices properly from a runtime PM perspective. Therefore, let's add them into VAPE PM domain for ux500. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Add spi and ssp devices to the VAPE PM domainUlf Hansson2014-10-281-0/+6
| | | | | | | | The spi-pl022 driver handle these devices properly from a runtime PM perspective. Therefore, let's add them into VAPE PM domain for ux500. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Add sdi devices to the VAPE PM domainUlf Hansson2014-10-281-0/+7
| | | | | | | | | The mmci driver handle these devices properly from a runtime PM perspective, including register context save/restore. Therefore let's add them into VAPE PM domain for ux500. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Add DT node for ux500 PM domainsUlf Hansson2014-10-281-0/+4
| | | | | | | | Add a DT node for the ux500 PM domains. Follow the DT semantics of the generic PM domain. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: add some DB8500 DMA channel infoLinus Walleij2014-07-071-0/+10
| | | | | | | | | This adds some missing DMA channel information to the disabled MMC/SD/SDIO blocks number 3 and 5, and notes that the assignment of MSP channels vary with ASIC variant. Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: switch SSP/SPI clock name to "SSPCLK"Linus Walleij2014-02-261-6/+6
| | | | | | | | | | | As noted in recent discussions the name of the core clock for the PL022 derived SPI blocks is erroneously named in the Ux500 device trees. The kernel doesn't currently use the name, but may do so soon so let use rename all these clocks in accordance with the name given in the PL022 TRM (ARM DDI 0194G). Reviewed-by: Mark Brown <broonie@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: create MCDE node to collect resourcesLinus Walleij2013-11-261-0/+17
| | | | | | | | | | As we need to connect resources such as pin mappings and clocks when deleting board files, we create a MCDE node even though there is no driver for it. As it is only using standard bindings right now, this does not matter much. When a proper driver is written for the MCDE, it can augment this node with custom properties. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Add DMA config bindings for MSP devicesLee Jones2013-11-261-0/+15
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: register all SSP and SPI blocksLinus Walleij2013-10-181-1/+74
| | | | | | | | | This adds the SSP and SPI blocks to the device tree and makes them active. Only this way can their clocks be properly gated off at boot. Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: fix I2C4 clock bitLinus Walleij2013-10-181-1/+1
| | | | | | | | | The PCLK for I2C4 is controlled by bit 10 in the PCKEN registers while the KCLK is controlled by bit 9 on the KCKEN, it's one of these odd assymetric things. Correct the PCLK bit to 10. Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: fix clock for GPIO blocks 6 and 7Linus Walleij2013-10-181-2/+2
| | | | | | | | | The clock assignment in the device tree for GPIO blocks 6 and 7 was incorrect, indicating this was managed by bit 1 on PRCC 2 while it was in fact bit 11 on PRCC 2. Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: fix clock for GPIO block 8Linus Walleij2013-10-181-1/+1
| | | | | | | | | The clock assignment in the device tree for GPIO block 8 was incorrect, indicating this was managed by bit 1 on PRCC 6 while it was in fact bit 1 on PRCC 5. Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Provide a Device Tree node for CPUFreq in the DBx500Lee Jones2013-09-261-0/+7
| | | | | | | This is required to fetch the ARMSS clock when booting with DT. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Provide a clock lookup for the Hash driverLee Jones2013-09-261-0/+1
| | | | | | | | The common clock framework will use the 'clock' property provided to do a clock lookup when Device Tree is enabled. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Provide a clock lookup for the Crypto driverLee Jones2013-09-261-0/+1
| | | | | | | | The common clock framework will use the 'clock' property provided to do a clock lookup when Device Tree is enabled. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Fix trivial white-space error in the DBX500 DTSI fileLee Jones2013-09-261-1/+1
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Add a DT node for the Nomadik System Timer (MTU0)Lee Jones2013-09-261-0/+11
| | | | | | | | | The MTU0 is required for full booting of the system. The driver has been previously DT:ed and is in use on the Nomadik platform, but we also need to enable it on ux500 based systems. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Supply the TWD Timer clock lookup to the DBX500 DTLee Jones2013-09-261-0/+2
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Add TWD (fixed-factor) clock node to DBx500 Device TreeLee Jones2013-09-261-0/+4
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Supply the RTC clock lookup to the DBX500 DTLee Jones2013-09-261-0/+3
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Add RTC (fixed-frequency) clock node to DBx500 Device TreeLee Jones2013-09-261-0/+4
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Supply the MSP (Audio) clocks lookup to the DBX500 DTLee Jones2013-09-261-0/+16
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Supply the SDI (MMC) clocks lookup to the DBX500 DTLee Jones2013-09-261-0/+20
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Supply the UART clocks lookup to the DBX500 DTLee Jones2013-09-261-0/+9
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Supply the I2C clocks lookup to the DBX500 DTLee Jones2013-09-261-0/+14
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Add PRCC Kernel clock node to DBx500 Device TreeLee Jones2013-09-261-0/+4
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Supply the USB clock lookup to the DBX500 DTLee Jones2013-09-261-0/+2
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Supply the GPIO clocks lookup to the DBX500 DTLee Jones2013-09-261-0/+18
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: ux500: Add PRCC Peripheral clock node to DBx500 Device TreeLee Jones2013-09-261-0/+4
| | | | | Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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