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* ARM: dts: meson8b: use stable UART bindings with correct gate clockMartin Blumenstingl2017-12-061-4/+12
| | | | | | | | | | Switch to the stable UART bindings and add the correct gate clocks to the non-AO UART nodes. This fixes the non-AO UARTs if the bootloader didn't un-gate the clocks. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: drop "sana" clock from SAR ADCXingyu Chen2017-12-061-3/+2
| | | | | | | | | | The SAR ADC modules doesn't require The "sana" clock. Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: add more L2 cache settingsMartin Blumenstingl2017-12-061-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | Amlogic's vendor kernel prints these PL310 L2 cache controller settings during boot: 8 ways, 2048 sets, CACHE_ID 0x4100a0c9, Cache size: 524288 B AUX_CTRL 0x7ec60001, PERFETCH_CTRL 0x75000007, POWER_CTRL 0x00000000 TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222 Add the "prefetch-data", "prefetch-instr" and "arm,shared-override" properties to get the same L2 cache controller configuration as the vendor kernel. Four differences still remain: - L310_AUX_CTRL_EARLY_BRESP is enabled by the vendor kernel, however this is only supported on Cortex-A9 cores (Meson8b has Cortex-A5 cores though) - L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0 driver - bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h - L310_AUX_CTRL_FULL_LINE_ZERO is enabled by the vendor kernel which is also only supported on Cortex-A9 cores Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* Merge tag 'amlogic-dt64' of ↵Arnd Bergmann2017-10-301-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt Pull "Amlogic 64-bit platforms: DT updates for v4.15" from Kevin Hilman: - new SoC support: A113D - new boards: Tronsmart Vega S96, Khadas vim2 - reserved memory fixups - gpio-names cleanups - MMC cleanups, enable high-speed modes - misc cleanups * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson-axg: add initial A113D SoC DT support dt-bindings: arm: amlogic: Add Meson AXG binding ARM64: dts: meson-gx: remove unnecessary uart compatible ARM64: dts: meson-gx: remove unnecessary clocks properties ARM64: dts: meson-gxl: Add alternate ARM Trusted Firmware reserved memory zone ARM64: dts: meson-gxm: enable HS400 on the vim2 ARM64: dts: meson-gxbb-nexbox-a95x: Enable USB Nodes dt-bindings: arm: amlogic: Add Tronsmart Vega S96 binding ARM64: dts: meson-gxm: Add Vega S96 board ARM64: dts: meson-gxm: Add support for Khadas VIM2 ARM64: dts: meson-gxl: Take eMMC data strobe out of eMMC pins ARM64: dts: meson-gxl: adjust libretech-cc gpio-line-names ARM64: dts: meson-gxl: adjust kvim gpio-line-names ARM64: dts: meson-gxbb: adjust odroid-c2 gpio-line-names ARM64: dts: meson-gxbb: adjust nanopi-k2 gpio-line-names ARM64: dts: meson-gx: adjust gpio-ranges for TEST_N ARM64: dts: meson-gx: remove gpio offset ARM: dts: meson8: remove gpio offset ARM64: dts: meson-gxl-libretech-cc: enable internal phy leds ARM64: dts: meson-gxl-libretech-cc: enable saradc
| * ARM: dts: meson8: remove gpio offsetJerome Brunet2017-10-111-1/+1
| | | | | | | | | | | | | | | | | | Remove pin offset on the AO controller. meson pinctrl no longer has this quirk Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | ARM: dts: meson: add the efuse nodeMartin Blumenstingl2017-10-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Meson6, Meson8 and Meson8b use a similar IP block which has access to 512 bytes of efuse data. During SoC manufacturing some calibration settings for the CVBS connector and the internal temperature sensor are written to this efuse. On some boards it additionally stores for example the MAC addresses. The efuse is enabled on Meson8 and Meson8b but kept disabled on Meson6 since we do not have a clock driver there (which is required to read data from the efuse). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | ARM: dts: meson8b: enable gpio interrupt controllerJerome Brunet2017-10-291-0/+6
| | | | | | | | | | | | | | | | Add gpio interrupt controller node to the meson8b boards Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | ARM: dts: meson8b: add support for booting the secondary CPU coresCarlo Caione2017-10-291-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting the secondary CPU cores involves the following nodes/devices: - SCU (Snoop-Control-Unit, for which we already have a DT node) - a reset line for each CPU core, provided by the reset-controller which is built into the clock-controller - the PMU (power management unit) which controls the power of the CPU cores - a range in the SRAM specifically reserved for booting secondary CPU cores - the "enable-method" which activates booting the secondary CPU cores This adds all required nodes and properties to boot the secondary CPU cores. Signed-off-by: Carlo Caione <carlo@caione.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Linus Lüssing <linus.luessing@c0d3.blue> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | ARM: dts: meson: add the SDIO MMC controllerMartin Blumenstingl2017-10-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Meson6, Meson8 and Meson8b are using the same MMC controller IP. This adds the MMC controller node to meson.dtsi so it can be used by all SoCs. The controller itself is a bit special, because it has multiple slots. Each slot is accessed through a sub-node of the controller. However, currently the driver for this hardware only supports one slot. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | ARM: dts: meson8b: add reserved memory zone to fix silent freezesLinus Lüssing2017-10-061-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far, the stress-ng tool for instance quickly resulted in a silent freeze of the system with no prior notice on a serial console when running its filesystem or memory stressor classes. Even with a panic-on-OOM and reboot-on-panic (vm.panic_on_oom=1, kernel.panic=10) configured, the system would neither reboot nor would the OOM killer get any chance to otherwise do its job. The Amlogic reference source code uses a 2MB PHYS_OFFSET. With these 2MB reserved via DT, stress-ng was able to run on an Odroid C1+ just fine for several hours, the OOM killer was able to kill processes again and if configured would successfully trigger a reboot of the system. Fixes: 4a69fcd3a108 ("ARM: meson: Add DTS for Odroid-C1 and Tronfy MXQ boards") Signed-off-by: Linus Lüssing <linus.luessing@c0d3.blue> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | ARM: dts: meson: add SoC information nodesMartin Blumenstingl2017-10-061-0/+5
|/ | | | | | | | | | | | | | | | The SoC type and version information is encoded in different register blocks. The SoC type information is part of the "assist" registers. The misc version information is part of the "bootrom" registers. On Meson8, Meson8b and Meson8m2 there is additionally information about the minor version. This information is stored in the "analog top" registers. Add the nodes for these register blocks so we can decode the SoC type and version information. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: mark the clock controller also as reset controllerMartin Blumenstingl2017-08-011-0/+1
| | | | | | | | | The clock controller provides a few reset lines as well. Add the corresponding CPU cores. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: use the existing wdt node to override the compatibleMartin Blumenstingl2017-07-281-6/+4
| | | | | | | | | | | | Meson8b has to define it's own compatible string for the watchdog. This patch removes the duplicate resource (register region and interrupt) definition from meson8b.dtsi and simply re-uses these values from meson.dtsi (as the register offset, size and interrupt are identical). This is purely cosmetic and does not change any functionality. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: move the pwm_ab and pwm_cd nodes to meson.dtsiMartin Blumenstingl2017-07-281-14/+8
| | | | | | | | | | | | According to the vendor kernel sources these also exist (at the same address) on Meson6 and Meson8. This can be found by running $ grep -R "define PWM_PWM_[A-D]" arch/arm/ in the Amlogic GPL kernel tree (arm-src-kernel-2015-01-15-321cfb5a46). pwm_ef does not seem to exist on older SoCs, so we keep it in meson8b.dtsi for now. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8bMartin Blumenstingl2017-06-161-0/+5
| | | | | | | | | | | Until now clk81 was used as gate clock for the ethernet controller on Meson8 whereas Meson8b did not configure a gate clock at all. Use CLKID_ETH for both SoCs, which is the real gate clock for the ethernet controller. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: add the SCU device nodeMartin Blumenstingl2017-06-161-0/+5
| | | | | | | | | | Amlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be used during SMP boot. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: add USB support on Meson8 and Meson8bMartin Blumenstingl2017-06-161-0/+26
| | | | | | | | | | | | | This adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to meson.dtsi (as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: add the hardware random number generatorMartin Blumenstingl2017-06-161-0/+6
| | | | | | | | | | | | | All supported Meson SoCs have a random number generator in CBUS. Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two 32-bit random number registers. The existing meson-rng driver only supports the lower 32-bit - but it still works fine on the older SoCs apart from this small limitation. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: add the SAR ADCMartin Blumenstingl2017-06-161-0/+8
| | | | | | | | | | This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8 and Meson8b to allow boards to use it. Some boards use it to connect a button to it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: Extend L2 cache controller node for Meson8 and Meson8bCarlo Caione2017-05-261-0/+6
| | | | | | | | | | | This patch extends the L2 cache controller node for the Amlogic Meson8 and Meson8b SoCs with some missing parameters. These are taken from the Amlogic GPL kernel source. Signed-off-by: Carlo Caione <carlo@endlessm.com> [apply the change to Meson8 and Meson8b and updated description] Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: inherit meson.dtsi from meson8b.dtsiMartin Blumenstingl2017-05-261-126/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently only meson6.dtsi and meson8.dtsi inherit the generic meson.dtsi. However, since the Meson8b platform is basically a slightly updated version of Meson8 we can safely inherit meson.dtsi. An indicator for this are the nodes which are identical in meson.dtsi and meson8b.dtsi (L2, gic, timer, uart_AO, uart_A, uart_B, uart_C). Additionally this makes the following devices available on Meson8b which were not avaialble before (however, since all affected drivers support Meson6, Meson8 and the whole GX series there's no reason to assume that they are not working): - i2c_a and i2c_B - the IR receiver - SPFIC (SPI flash controller) - the dwmac ethernet controller Differences between Meson8 and Meson8b seem to be: - ARM Cortex-A5 core instead of Cortex-A9 on Meson8 - dwmac on Meson8b supports RGMII - small pinctrl updates Inheriting meson.dtsi makes it easier to maintain by removing duplicate definitions. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: Add gpio-ranges propertiesNeil Armstrong2017-03-281-0/+2
| | | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: Add Meson8b PWM Controller nodesNeil Armstrong2016-09-071-0/+21
| | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: amlogic: Enable Reset Controller on Meson8b platformsNeil Armstrong2016-06-141-0/+7
| | | | | | | Update DTSI file to add the reset controller node. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8bCarlo Caione2016-03-301-2/+10
| | | | | | Signed-off-by: Carlo Caione <carlo@endlessm.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Tested-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: Add watchdog nodeCarlo Caione2016-01-041-0/+6
| | | | | | With this patch we add the watchdog node in the meson8b DTS file. Signed-off-by: Carlo Caione <carlo@endlessm.com>
* ARM: meson: Add DTS for Odroid-C1 and Tronfy MXQ boardsCarlo Caione2015-10-081-0/+186
Signed-off-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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