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-rw-r--r--arch/m68k/include/asm/m53xxacr.h18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/m68k/include/asm/m53xxacr.h b/arch/m68k/include/asm/m53xxacr.h
index 532fbb91185f..74c81c9b177e 100644
--- a/arch/m68k/include/asm/m53xxacr.h
+++ b/arch/m68k/include/asm/m53xxacr.h
@@ -48,5 +48,23 @@
#define ACR_CM_IMPRE 0x00000060 /* Cache inhibited, imprecise */
#define ACR_WPROTECT 0x00000004 /* Write protect region */
+/*
+ * Set the cache controller settings we will use. This default in the
+ * CACR is cache inhibited, we use the ACR register to set cacheing
+ * enabled on the regions we want (eg RAM).
+ */
+#ifdef CONFIG_COLDFIRE_SW_A7
+#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE)
+#else
+#define CACHE_MODE (CACR_EC + CACR_ESB + CACR_DCM_PRE + CACR_EUSP)
+#endif
+
+#define CACHE_INIT CACR_CINVA
+
+#define ACR0_MODE ((CONFIG_RAMBASE & 0xff000000) + \
+ (0x000f0000) + \
+ (ACR_ENABLE + ACR_ANY + ACR_CM_CB))
+#define ACR1_MODE 0
+
/****************************************************************************/
#endif /* m53xxsim_h */
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