10 files changed, 411 insertions, 1058 deletions

diff --git a/arch/arm/mach-spear6xx/Makefile b/arch/arm/mach-spear6xx/Makefile
index 76e5750552fc..898831d93f37 100644
--- a/arch/arm/mach-spear6xx/Makefile
+++ b/arch/arm/mach-spear6xx/Makefile
@@ -3,4 +3,4 @@
 #
 
 # common files
-obj-y	+= clock.o spear6xx.o
+obj-y	+= spear6xx.o
diff --git a/arch/arm/mach-spear6xx/Makefile.boot b/arch/arm/mach-spear6xx/Makefile.boot
index 4674a4c221db..af493da37ab6 100644
--- a/arch/arm/mach-spear6xx/Makefile.boot
+++ b/arch/arm/mach-spear6xx/Makefile.boot
@@ -1,3 +1,5 @@
 zreladdr-y	+= 0x00008000
 params_phys-y	:= 0x00000100
 initrd_phys-y	:= 0x00800000
+
+dtb-$(CONFIG_BOARD_SPEAR600_DT)	+= spear600-evb.dtb
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
deleted file mode 100644
index a86499a8a15f..000000000000
--- a/arch/arm/mach-spear6xx/clock.c
+++ /dev/null
@@ -1,683 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/clock.c
- *
- * SPEAr6xx machines clock framework source file
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <plat/clock.h>
-#include <mach/misc_regs.h>
-
-/* root clks */
-/* 32 KHz oscillator clock */
-static struct clk osc_32k_clk = {
-	.flags = ALWAYS_ENABLED,
-	.rate = 32000,
-};
-
-/* 30 MHz oscillator clock */
-static struct clk osc_30m_clk = {
-	.flags = ALWAYS_ENABLED,
-	.rate = 30000000,
-};
-
-/* clock derived from 32 KHz osc clk */
-/* rtc clock */
-static struct clk rtc_clk = {
-	.pclk = &osc_32k_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = RTC_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* clock derived from 30 MHz osc clk */
-/* pll masks structure */
-static struct pll_clk_masks pll1_masks = {
-	.mode_mask = PLL_MODE_MASK,
-	.mode_shift = PLL_MODE_SHIFT,
-	.norm_fdbk_m_mask = PLL_NORM_FDBK_M_MASK,
-	.norm_fdbk_m_shift = PLL_NORM_FDBK_M_SHIFT,
-	.dith_fdbk_m_mask = PLL_DITH_FDBK_M_MASK,
-	.dith_fdbk_m_shift = PLL_DITH_FDBK_M_SHIFT,
-	.div_p_mask = PLL_DIV_P_MASK,
-	.div_p_shift = PLL_DIV_P_SHIFT,
-	.div_n_mask = PLL_DIV_N_MASK,
-	.div_n_shift = PLL_DIV_N_SHIFT,
-};
-
-/* pll1 configuration structure */
-static struct pll_clk_config pll1_config = {
-	.mode_reg = PLL1_CTR,
-	.cfg_reg = PLL1_FRQ,
-	.masks = &pll1_masks,
-};
-
-/* pll rate configuration table, in ascending order of rates */
-struct pll_rate_tbl pll_rtbl[] = {
-	{.mode = 0, .m = 0x85, .n = 0x0C, .p = 0x1}, /* 266 MHz */
-	{.mode = 0, .m = 0xA6, .n = 0x0C, .p = 0x1}, /* 332 MHz */
-};
-
-/* PLL1 clock */
-static struct clk pll1_clk = {
-	.flags = ENABLED_ON_INIT,
-	.pclk = &osc_30m_clk,
-	.en_reg = PLL1_CTR,
-	.en_reg_bit = PLL_ENABLE,
-	.calc_rate = &pll_calc_rate,
-	.recalc = &pll_clk_recalc,
-	.set_rate = &pll_clk_set_rate,
-	.rate_config = {pll_rtbl, ARRAY_SIZE(pll_rtbl), 1},
-	.private_data = &pll1_config,
-};
-
-/* PLL3 48 MHz clock */
-static struct clk pll3_48m_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk = &osc_30m_clk,
-	.rate = 48000000,
-};
-
-/* watch dog timer clock */
-static struct clk wdt_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk = &osc_30m_clk,
-	.recalc = &follow_parent,
-};
-
-/* clock derived from pll1 clk */
-/* cpu clock */
-static struct clk cpu_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk = &pll1_clk,
-	.recalc = &follow_parent,
-};
-
-/* ahb masks structure */
-static struct bus_clk_masks ahb_masks = {
-	.mask = PLL_HCLK_RATIO_MASK,
-	.shift = PLL_HCLK_RATIO_SHIFT,
-};
-
-/* ahb configuration structure */
-static struct bus_clk_config ahb_config = {
-	.reg = CORE_CLK_CFG,
-	.masks = &ahb_masks,
-};
-
-/* ahb rate configuration table, in ascending order of rates */
-struct bus_rate_tbl bus_rtbl[] = {
-	{.div = 3}, /* == parent divided by 4 */
-	{.div = 2}, /* == parent divided by 3 */
-	{.div = 1}, /* == parent divided by 2 */
-	{.div = 0}, /* == parent divided by 1 */
-};
-
-/* ahb clock */
-static struct clk ahb_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk = &pll1_clk,
-	.calc_rate = &bus_calc_rate,
-	.recalc = &bus_clk_recalc,
-	.set_rate = &bus_clk_set_rate,
-	.rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-	.private_data = &ahb_config,
-};
-
-/* auxiliary synthesizers masks */
-static struct aux_clk_masks aux_masks = {
-	.eq_sel_mask = AUX_EQ_SEL_MASK,
-	.eq_sel_shift = AUX_EQ_SEL_SHIFT,
-	.eq1_mask = AUX_EQ1_SEL,
-	.eq2_mask = AUX_EQ2_SEL,
-	.xscale_sel_mask = AUX_XSCALE_MASK,
-	.xscale_sel_shift = AUX_XSCALE_SHIFT,
-	.yscale_sel_mask = AUX_YSCALE_MASK,
-	.yscale_sel_shift = AUX_YSCALE_SHIFT,
-};
-
-/* uart configurations */
-static struct aux_clk_config uart_synth_config = {
-	.synth_reg = UART_CLK_SYNT,
-	.masks = &aux_masks,
-};
-
-/* aux rate configuration table, in ascending order of rates */
-struct aux_rate_tbl aux_rtbl[] = {
-	/* For PLL1 = 332 MHz */
-	{.xscale = 1, .yscale = 8, .eq = 1}, /* 41.5 MHz */
-	{.xscale = 1, .yscale = 4, .eq = 1}, /* 83 MHz */
-	{.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
-};
-
-/* uart synth clock */
-static struct clk uart_synth_clk = {
-	.en_reg = UART_CLK_SYNT,
-	.en_reg_bit = AUX_SYNT_ENB,
-	.pclk = &pll1_clk,
-	.calc_rate = &aux_calc_rate,
-	.recalc = &aux_clk_recalc,
-	.set_rate = &aux_clk_set_rate,
-	.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
-	.private_data = &uart_synth_config,
-};
-
-/* uart parents */
-static struct pclk_info uart_pclk_info[] = {
-	{
-		.pclk = &uart_synth_clk,
-		.pclk_val = AUX_CLK_PLL1_VAL,
-	}, {
-		.pclk = &pll3_48m_clk,
-		.pclk_val = AUX_CLK_PLL3_VAL,
-	},
-};
-
-/* uart parent select structure */
-static struct pclk_sel uart_pclk_sel = {
-	.pclk_info = uart_pclk_info,
-	.pclk_count = ARRAY_SIZE(uart_pclk_info),
-	.pclk_sel_reg = PERIP_CLK_CFG,
-	.pclk_sel_mask = UART_CLK_MASK,
-};
-
-/* uart0 clock */
-static struct clk uart0_clk = {
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = UART0_CLK_ENB,
-	.pclk_sel = &uart_pclk_sel,
-	.pclk_sel_shift = UART_CLK_SHIFT,
-	.recalc = &follow_parent,
-};
-
-/* uart1 clock */
-static struct clk uart1_clk = {
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = UART1_CLK_ENB,
-	.pclk_sel = &uart_pclk_sel,
-	.pclk_sel_shift = UART_CLK_SHIFT,
-	.recalc = &follow_parent,
-};
-
-/* firda configurations */
-static struct aux_clk_config firda_synth_config = {
-	.synth_reg = FIRDA_CLK_SYNT,
-	.masks = &aux_masks,
-};
-
-/* firda synth clock */
-static struct clk firda_synth_clk = {
-	.en_reg = FIRDA_CLK_SYNT,
-	.en_reg_bit = AUX_SYNT_ENB,
-	.pclk = &pll1_clk,
-	.calc_rate = &aux_calc_rate,
-	.recalc = &aux_clk_recalc,
-	.set_rate = &aux_clk_set_rate,
-	.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
-	.private_data = &firda_synth_config,
-};
-
-/* firda parents */
-static struct pclk_info firda_pclk_info[] = {
-	{
-		.pclk = &firda_synth_clk,
-		.pclk_val = AUX_CLK_PLL1_VAL,
-	}, {
-		.pclk = &pll3_48m_clk,
-		.pclk_val = AUX_CLK_PLL3_VAL,
-	},
-};
-
-/* firda parent select structure */
-static struct pclk_sel firda_pclk_sel = {
-	.pclk_info = firda_pclk_info,
-	.pclk_count = ARRAY_SIZE(firda_pclk_info),
-	.pclk_sel_reg = PERIP_CLK_CFG,
-	.pclk_sel_mask = FIRDA_CLK_MASK,
-};
-
-/* firda clock */
-static struct clk firda_clk = {
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = FIRDA_CLK_ENB,
-	.pclk_sel = &firda_pclk_sel,
-	.pclk_sel_shift = FIRDA_CLK_SHIFT,
-	.recalc = &follow_parent,
-};
-
-/* clcd configurations */
-static struct aux_clk_config clcd_synth_config = {
-	.synth_reg = CLCD_CLK_SYNT,
-	.masks = &aux_masks,
-};
-
-/* firda synth clock */
-static struct clk clcd_synth_clk = {
-	.en_reg = CLCD_CLK_SYNT,
-	.en_reg_bit = AUX_SYNT_ENB,
-	.pclk = &pll1_clk,
-	.calc_rate = &aux_calc_rate,
-	.recalc = &aux_clk_recalc,
-	.set_rate = &aux_clk_set_rate,
-	.rate_config = {aux_rtbl, ARRAY_SIZE(aux_rtbl), 2},
-	.private_data = &clcd_synth_config,
-};
-
-/* clcd parents */
-static struct pclk_info clcd_pclk_info[] = {
-	{
-		.pclk = &clcd_synth_clk,
-		.pclk_val = AUX_CLK_PLL1_VAL,
-	}, {
-		.pclk = &pll3_48m_clk,
-		.pclk_val = AUX_CLK_PLL3_VAL,
-	},
-};
-
-/* clcd parent select structure */
-static struct pclk_sel clcd_pclk_sel = {
-	.pclk_info = clcd_pclk_info,
-	.pclk_count = ARRAY_SIZE(clcd_pclk_info),
-	.pclk_sel_reg = PERIP_CLK_CFG,
-	.pclk_sel_mask = CLCD_CLK_MASK,
-};
-
-/* clcd clock */
-static struct clk clcd_clk = {
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = CLCD_CLK_ENB,
-	.pclk_sel = &clcd_pclk_sel,
-	.pclk_sel_shift = CLCD_CLK_SHIFT,
-	.recalc = &follow_parent,
-};
-
-/* gpt synthesizer masks */
-static struct gpt_clk_masks gpt_masks = {
-	.mscale_sel_mask = GPT_MSCALE_MASK,
-	.mscale_sel_shift = GPT_MSCALE_SHIFT,
-	.nscale_sel_mask = GPT_NSCALE_MASK,
-	.nscale_sel_shift = GPT_NSCALE_SHIFT,
-};
-
-/* gpt rate configuration table, in ascending order of rates */
-struct gpt_rate_tbl gpt_rtbl[] = {
-	/* For pll1 = 332 MHz */
-	{.mscale = 4, .nscale = 0}, /* 41.5 MHz */
-	{.mscale = 2, .nscale = 0}, /* 55.3 MHz */
-	{.mscale = 1, .nscale = 0}, /* 83 MHz */
-};
-
-/* gpt0 synth clk config*/
-static struct gpt_clk_config gpt0_synth_config = {
-	.synth_reg = PRSC1_CLK_CFG,
-	.masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt0_synth_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk = &pll1_clk,
-	.calc_rate = &gpt_calc_rate,
-	.recalc = &gpt_clk_recalc,
-	.set_rate = &gpt_clk_set_rate,
-	.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-	.private_data = &gpt0_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt0_pclk_info[] = {
-	{
-		.pclk = &gpt0_synth_clk,
-		.pclk_val = AUX_CLK_PLL1_VAL,
-	}, {
-		.pclk = &pll3_48m_clk,
-		.pclk_val = AUX_CLK_PLL3_VAL,
-	},
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt0_pclk_sel = {
-	.pclk_info = gpt0_pclk_info,
-	.pclk_count = ARRAY_SIZE(gpt0_pclk_info),
-	.pclk_sel_reg = PERIP_CLK_CFG,
-	.pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt0 ARM1 subsystem timer clock */
-static struct clk gpt0_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk_sel = &gpt0_pclk_sel,
-	.pclk_sel_shift = GPT0_CLK_SHIFT,
-	.recalc = &follow_parent,
-};
-
-
-/* Note: gpt0 and gpt1 share same parent clocks */
-/* gpt parent select structure */
-static struct pclk_sel gpt1_pclk_sel = {
-	.pclk_info = gpt0_pclk_info,
-	.pclk_count = ARRAY_SIZE(gpt0_pclk_info),
-	.pclk_sel_reg = PERIP_CLK_CFG,
-	.pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt1 timer clock */
-static struct clk gpt1_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk_sel = &gpt1_pclk_sel,
-	.pclk_sel_shift = GPT1_CLK_SHIFT,
-	.recalc = &follow_parent,
-};
-
-/* gpt2 synth clk config*/
-static struct gpt_clk_config gpt2_synth_config = {
-	.synth_reg = PRSC2_CLK_CFG,
-	.masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt2_synth_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk = &pll1_clk,
-	.calc_rate = &gpt_calc_rate,
-	.recalc = &gpt_clk_recalc,
-	.set_rate = &gpt_clk_set_rate,
-	.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-	.private_data = &gpt2_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt2_pclk_info[] = {
-	{
-		.pclk = &gpt2_synth_clk,
-		.pclk_val = AUX_CLK_PLL1_VAL,
-	}, {
-		.pclk = &pll3_48m_clk,
-		.pclk_val = AUX_CLK_PLL3_VAL,
-	},
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt2_pclk_sel = {
-	.pclk_info = gpt2_pclk_info,
-	.pclk_count = ARRAY_SIZE(gpt2_pclk_info),
-	.pclk_sel_reg = PERIP_CLK_CFG,
-	.pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt2 timer clock */
-static struct clk gpt2_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk_sel = &gpt2_pclk_sel,
-	.pclk_sel_shift = GPT2_CLK_SHIFT,
-	.recalc = &follow_parent,
-};
-
-/* gpt3 synth clk config*/
-static struct gpt_clk_config gpt3_synth_config = {
-	.synth_reg = PRSC3_CLK_CFG,
-	.masks = &gpt_masks,
-};
-
-/* gpt synth clock */
-static struct clk gpt3_synth_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk = &pll1_clk,
-	.calc_rate = &gpt_calc_rate,
-	.recalc = &gpt_clk_recalc,
-	.set_rate = &gpt_clk_set_rate,
-	.rate_config = {gpt_rtbl, ARRAY_SIZE(gpt_rtbl), 2},
-	.private_data = &gpt3_synth_config,
-};
-
-/* gpt parents */
-static struct pclk_info gpt3_pclk_info[] = {
-	{
-		.pclk = &gpt3_synth_clk,
-		.pclk_val = AUX_CLK_PLL1_VAL,
-	}, {
-		.pclk = &pll3_48m_clk,
-		.pclk_val = AUX_CLK_PLL3_VAL,
-	},
-};
-
-/* gpt parent select structure */
-static struct pclk_sel gpt3_pclk_sel = {
-	.pclk_info = gpt3_pclk_info,
-	.pclk_count = ARRAY_SIZE(gpt3_pclk_info),
-	.pclk_sel_reg = PERIP_CLK_CFG,
-	.pclk_sel_mask = GPT_CLK_MASK,
-};
-
-/* gpt3 timer clock */
-static struct clk gpt3_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk_sel = &gpt3_pclk_sel,
-	.pclk_sel_shift = GPT3_CLK_SHIFT,
-	.recalc = &follow_parent,
-};
-
-/* clock derived from pll3 clk */
-/* usbh0 clock */
-static struct clk usbh0_clk = {
-	.pclk = &pll3_48m_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = USBH0_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* usbh1 clock */
-static struct clk usbh1_clk = {
-	.pclk = &pll3_48m_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = USBH1_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* usbd clock */
-static struct clk usbd_clk = {
-	.pclk = &pll3_48m_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = USBD_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* clock derived from ahb clk */
-/* apb masks structure */
-static struct bus_clk_masks apb_masks = {
-	.mask = HCLK_PCLK_RATIO_MASK,
-	.shift = HCLK_PCLK_RATIO_SHIFT,
-};
-
-/* apb configuration structure */
-static struct bus_clk_config apb_config = {
-	.reg = CORE_CLK_CFG,
-	.masks = &apb_masks,
-};
-
-/* apb clock */
-static struct clk apb_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk = &ahb_clk,
-	.calc_rate = &bus_calc_rate,
-	.recalc = &bus_clk_recalc,
-	.set_rate = &bus_clk_set_rate,
-	.rate_config = {bus_rtbl, ARRAY_SIZE(bus_rtbl), 2},
-	.private_data = &apb_config,
-};
-
-/* i2c clock */
-static struct clk i2c_clk = {
-	.pclk = &ahb_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = I2C_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* dma clock */
-static struct clk dma_clk = {
-	.pclk = &ahb_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = DMA_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* jpeg clock */
-static struct clk jpeg_clk = {
-	.pclk = &ahb_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = JPEG_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* gmac clock */
-static struct clk gmac_clk = {
-	.pclk = &ahb_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = GMAC_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* smi clock */
-static struct clk smi_clk = {
-	.pclk = &ahb_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = SMI_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* fsmc clock */
-static struct clk fsmc_clk = {
-	.pclk = &ahb_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = FSMC_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* clock derived from apb clk */
-/* adc clock */
-static struct clk adc_clk = {
-	.pclk = &apb_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = ADC_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* ssp0 clock */
-static struct clk ssp0_clk = {
-	.pclk = &apb_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = SSP0_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* ssp1 clock */
-static struct clk ssp1_clk = {
-	.pclk = &apb_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = SSP1_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* ssp2 clock */
-static struct clk ssp2_clk = {
-	.pclk = &apb_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = SSP2_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* gpio0 ARM subsystem clock */
-static struct clk gpio0_clk = {
-	.flags = ALWAYS_ENABLED,
-	.pclk = &apb_clk,
-	.recalc = &follow_parent,
-};
-
-/* gpio1 clock */
-static struct clk gpio1_clk = {
-	.pclk = &apb_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = GPIO1_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-/* gpio2 clock */
-static struct clk gpio2_clk = {
-	.pclk = &apb_clk,
-	.en_reg = PERIP1_CLK_ENB,
-	.en_reg_bit = GPIO2_CLK_ENB,
-	.recalc = &follow_parent,
-};
-
-static struct clk dummy_apb_pclk;
-
-/* array of all spear 6xx clock lookups */
-static struct clk_lookup spear_clk_lookups[] = {
-	{ .con_id = "apb_pclk",		.clk = &dummy_apb_pclk},
-	/* root clks */
-	{ .con_id = "osc_32k_clk",	.clk = &osc_32k_clk},
-	{ .con_id = "osc_30m_clk",	.clk = &osc_30m_clk},
-	/* clock derived from 32 KHz os		 clk */
-	{ .dev_id = "rtc-spear",	.clk = &rtc_clk},
-	/* clock derived from 30 MHz os		 clk */
-	{ .con_id = "pll1_clk",		.clk = &pll1_clk},
-	{ .con_id = "pll3_48m_clk",	.clk = &pll3_48m_clk},
-	{ .dev_id = "wdt",		.clk = &wdt_clk},
-	/* clock derived from pll1 clk */
-	{ .con_id = "cpu_clk",		.clk = &cpu_clk},
-	{ .con_id = "ahb_clk",		.clk = &ahb_clk},
-	{ .con_id = "uart_synth_clk",	.clk = &uart_synth_clk},
-	{ .con_id = "firda_synth_clk",	.clk = &firda_synth_clk},
-	{ .con_id = "clcd_synth_clk",	.clk = &clcd_synth_clk},
-	{ .con_id = "gpt0_synth_clk",	.clk = &gpt0_synth_clk},
-	{ .con_id = "gpt2_synth_clk",	.clk = &gpt2_synth_clk},
-	{ .con_id = "gpt3_synth_clk",	.clk = &gpt3_synth_clk},
-	{ .dev_id = "d0000000.serial",	.clk = &uart0_clk},
-	{ .dev_id = "d0080000.serial",	.clk = &uart1_clk},
-	{ .dev_id = "firda",		.clk = &firda_clk},
-	{ .dev_id = "clcd",		.clk = &clcd_clk},
-	{ .dev_id = "gpt0",		.clk = &gpt0_clk},
-	{ .dev_id = "gpt1",		.clk = &gpt1_clk},
-	{ .dev_id = "gpt2",		.clk = &gpt2_clk},
-	{ .dev_id = "gpt3",		.clk = &gpt3_clk},
-	/* clock derived from pll3 clk */
-	{ .dev_id = "designware_udc",	.clk = &usbd_clk},
-	{ .con_id = "usbh.0_clk",	.clk = &usbh0_clk},
-	{ .con_id = "usbh.1_clk",	.clk = &usbh1_clk},
-	/* clock derived from ahb clk */
-	{ .con_id = "apb_clk",		.clk = &apb_clk},
-	{ .dev_id = "d0200000.i2c",	.clk = &i2c_clk},
-	{ .dev_id = "dma",		.clk = &dma_clk},
-	{ .dev_id = "jpeg",		.clk = &jpeg_clk},
-	{ .dev_id = "gmac",		.clk = &gmac_clk},
-	{ .dev_id = "smi",		.clk = &smi_clk},
-	{ .dev_id = "fsmc-nand",	.clk = &fsmc_clk},
-	/* clock derived from apb clk */
-	{ .dev_id = "adc",		.clk = &adc_clk},
-	{ .dev_id = "ssp-pl022.0",	.clk = &ssp0_clk},
-	{ .dev_id = "ssp-pl022.1",	.clk = &ssp1_clk},
-	{ .dev_id = "ssp-pl022.2",	.clk = &ssp2_clk},
-	{ .dev_id = "f0100000.gpio",	.clk = &gpio0_clk},
-	{ .dev_id = "fc980000.gpio",	.clk = &gpio1_clk},
-	{ .dev_id = "d8100000.gpio",	.clk = &gpio2_clk},
-};
-
-void __init spear6xx_clk_init(void)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
-		clk_register(&spear_clk_lookups[i]);
-
-	clk_init();
-}
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 116b99301cf5..65514b159370 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -15,34 +15,9 @@
 #define __MACH_GENERIC_H
 
 #include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/amba/bus.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-/*
- * Each GPT has 2 timer channels
- * Following GPT channels will be used as clock source and clockevent
- */
-#define SPEAR_GPT0_BASE		SPEAR6XX_CPU_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ	IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ	IRQ_CPU_GPT1_2
-
-/* Add spear6xx family device structure declarations here */
-extern struct amba_device gpio_device[];
-extern struct amba_device uart_device[];
-extern struct sys_timer spear6xx_timer;
-
-/* Add spear6xx family function declarations here */
-void __init spear_setup_timer(void);
-void __init spear6xx_map_io(void);
-void __init spear6xx_init_irq(void);
-void __init spear6xx_init(void);
-void __init spear600_init(void);
-void __init spear6xx_clk_init(void);
 
+void __init spear_setup_of_timer(void);
 void spear_restart(char, const char *);
-
-/* Add spear600 machine device structure declarations here */
+void __init spear6xx_clk_init(void);
 
 #endif /* __MACH_GENERIC_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/hardware.h b/arch/arm/mach-spear6xx/include/mach/hardware.h
index 0b3f96ae2848..40a8c178f10d 100644
--- a/arch/arm/mach-spear6xx/include/mach/hardware.h
+++ b/arch/arm/mach-spear6xx/include/mach/hardware.h
@@ -1,23 +1 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/hardware.h
- *
- * Hardware definitions for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Rajeev Kumar<rajeev-dlh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#include <plat/hardware.h>
-#include <mach/spear.h>
-
-/* Vitual to physical translation of statically mapped space */
-#define IO_ADDRESS(x)		(x | 0xF0000000)
-
-#endif /* __MACH_HARDWARE_H */
+/* empty */
diff --git a/arch/arm/mach-spear6xx/include/mach/irqs.h b/arch/arm/mach-spear6xx/include/mach/irqs.h
index 8f214b03d75d..37a5c411a866 100644
--- a/arch/arm/mach-spear6xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear6xx/include/mach/irqs.h
@@ -16,82 +16,10 @@
 
 /* IRQ definitions */
 /* VIC 1 */
-#define IRQ_INTRCOMM_SW_IRQ			0
-#define IRQ_INTRCOMM_CPU_1			1
-#define IRQ_INTRCOMM_CPU_2			2
-#define IRQ_INTRCOMM_RAS2A11_1			3
-#define IRQ_INTRCOMM_RAS2A11_2			4
-#define IRQ_INTRCOMM_RAS2A12_1			5
-#define IRQ_INTRCOMM_RAS2A12_2			6
-#define IRQ_GEN_RAS_0				7
-#define IRQ_GEN_RAS_1				8
-#define IRQ_GEN_RAS_2				9
-#define IRQ_GEN_RAS_3				10
-#define IRQ_GEN_RAS_4				11
-#define IRQ_GEN_RAS_5				12
-#define IRQ_GEN_RAS_6				13
-#define IRQ_GEN_RAS_7				14
-#define IRQ_GEN_RAS_8				15
-#define IRQ_CPU_GPT1_1				16
-#define IRQ_CPU_GPT1_2				17
-#define IRQ_LOCAL_GPIO				18
-#define IRQ_PLL_UNLOCK				19
-#define IRQ_JPEG				20
-#define IRQ_FSMC				21
-#define IRQ_IRDA				22
-#define IRQ_RESERVED				23
-#define IRQ_UART_0				24
-#define IRQ_UART_1				25
-#define IRQ_SSP_1				26
-#define IRQ_SSP_2				27
-#define IRQ_I2C					28
-#define IRQ_GEN_RAS_9				29
-#define IRQ_GEN_RAS_10				30
-#define IRQ_GEN_RAS_11				31
-
-/* VIC 2 */
-#define IRQ_APPL_GPT1_1				32
-#define IRQ_APPL_GPT1_2				33
-#define IRQ_APPL_GPT2_1				34
-#define IRQ_APPL_GPT2_2				35
-#define IRQ_APPL_GPIO				36
-#define IRQ_APPL_SSP				37
-#define IRQ_APPL_ADC				38
-#define IRQ_APPL_RESERVED			39
-#define IRQ_AHB_EXP_MASTER			40
-#define IRQ_DDR_CONTROLLER			41
-#define IRQ_BASIC_DMA				42
-#define IRQ_BASIC_RESERVED1			43
-#define IRQ_BASIC_SMI				44
-#define IRQ_BASIC_CLCD				45
-#define IRQ_EXP_AHB_1				46
-#define IRQ_EXP_AHB_2				47
-#define IRQ_BASIC_GPT1_1			48
-#define IRQ_BASIC_GPT1_2			49
-#define IRQ_BASIC_RTC				50
-#define IRQ_BASIC_GPIO				51
-#define IRQ_BASIC_WDT				52
-#define IRQ_BASIC_RESERVED			53
-#define IRQ_AHB_EXP_SLAVE			54
-#define IRQ_GMAC_1				55
-#define IRQ_GMAC_2				56
-#define IRQ_USB_DEV				57
-#define IRQ_USB_H_OHCI_0			58
-#define IRQ_USB_H_EHCI_0			59
-#define IRQ_USB_H_OHCI_1			60
-#define IRQ_USB_H_EHCI_1			61
-#define IRQ_EXP_AHB_3				62
-#define IRQ_EXP_AHB_4				63
-
 #define IRQ_VIC_END				64
 
 /* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE	IRQ_VIC_END
-#define SPEAR_GPIO0_INT_BASE	SPEAR_GPIO_INT_BASE
-#define SPEAR_GPIO1_INT_BASE	(SPEAR_GPIO0_INT_BASE + 8)
-#define SPEAR_GPIO2_INT_BASE	(SPEAR_GPIO1_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END	(SPEAR_GPIO2_INT_BASE + 8)
-#define VIRTUAL_IRQS		(SPEAR_GPIO_INT_END - IRQ_VIC_END)
-#define NR_IRQS			(IRQ_VIC_END + VIRTUAL_IRQS)
+#define VIRTUAL_IRQS				24
+#define NR_IRQS					(IRQ_VIC_END + VIRTUAL_IRQS)
 
 #endif	/* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/misc_regs.h b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
index 68c20a007b0d..179e45774b3a 100644
--- a/arch/arm/mach-spear6xx/include/mach/misc_regs.h
+++ b/arch/arm/mach-spear6xx/include/mach/misc_regs.h
@@ -14,161 +14,9 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
 
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
 #define MISC_BASE		IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
-
-#define SOC_CFG_CTR		(MISC_BASE + 0x000)
-#define DIAG_CFG_CTR		(MISC_BASE + 0x004)
-#define PLL1_CTR		(MISC_BASE + 0x008)
-#define PLL1_FRQ		(MISC_BASE + 0x00C)
-#define PLL1_MOD		(MISC_BASE + 0x010)
-#define PLL2_CTR		(MISC_BASE + 0x014)
-/* PLL_CTR register masks */
-#define PLL_ENABLE		2
-#define PLL_MODE_SHIFT		4
-#define PLL_MODE_MASK		0x3
-#define PLL_MODE_NORMAL		0
-#define PLL_MODE_FRACTION	1
-#define PLL_MODE_DITH_DSB	2
-#define PLL_MODE_DITH_SSB	3
-
-#define PLL2_FRQ		(MISC_BASE + 0x018)
-/* PLL FRQ register masks */
-#define PLL_DIV_N_SHIFT		0
-#define PLL_DIV_N_MASK		0xFF
-#define PLL_DIV_P_SHIFT		8
-#define PLL_DIV_P_MASK		0x7
-#define PLL_NORM_FDBK_M_SHIFT	24
-#define PLL_NORM_FDBK_M_MASK	0xFF
-#define PLL_DITH_FDBK_M_SHIFT	16
-#define PLL_DITH_FDBK_M_MASK	0xFFFF
-
-#define PLL2_MOD		(MISC_BASE + 0x01C)
-#define PLL_CLK_CFG		(MISC_BASE + 0x020)
-#define CORE_CLK_CFG		(MISC_BASE + 0x024)
-/* CORE CLK CFG register masks */
-#define PLL_HCLK_RATIO_SHIFT	10
-#define PLL_HCLK_RATIO_MASK	0x3
-#define HCLK_PCLK_RATIO_SHIFT	8
-#define HCLK_PCLK_RATIO_MASK	0x3
-
-#define PERIP_CLK_CFG		(MISC_BASE + 0x028)
-/* PERIP_CLK_CFG register masks */
-#define CLCD_CLK_SHIFT		2
-#define CLCD_CLK_MASK		0x3
-#define UART_CLK_SHIFT		4
-#define UART_CLK_MASK		0x1
-#define FIRDA_CLK_SHIFT		5
-#define FIRDA_CLK_MASK		0x3
-#define GPT0_CLK_SHIFT		8
-#define GPT1_CLK_SHIFT		10
-#define GPT2_CLK_SHIFT		11
-#define GPT3_CLK_SHIFT		12
-#define GPT_CLK_MASK		0x1
-#define AUX_CLK_PLL3_VAL	0
-#define AUX_CLK_PLL1_VAL	1
-
-#define PERIP1_CLK_ENB		(MISC_BASE + 0x02C)
-/* PERIP1_CLK_ENB register masks */
-#define UART0_CLK_ENB		3
-#define UART1_CLK_ENB		4
-#define SSP0_CLK_ENB		5
-#define SSP1_CLK_ENB		6
-#define I2C_CLK_ENB		7
-#define JPEG_CLK_ENB		8
-#define FSMC_CLK_ENB		9
-#define FIRDA_CLK_ENB		10
-#define GPT2_CLK_ENB		11
-#define GPT3_CLK_ENB		12
-#define GPIO2_CLK_ENB		13
-#define SSP2_CLK_ENB		14
-#define ADC_CLK_ENB		15
-#define GPT1_CLK_ENB		11
-#define RTC_CLK_ENB		17
-#define GPIO1_CLK_ENB		18
-#define DMA_CLK_ENB		19
-#define SMI_CLK_ENB		21
-#define CLCD_CLK_ENB		22
-#define GMAC_CLK_ENB		23
-#define USBD_CLK_ENB		24
-#define USBH0_CLK_ENB		25
-#define USBH1_CLK_ENB		26
-
-#define SOC_CORE_ID		(MISC_BASE + 0x030)
-#define RAS_CLK_ENB		(MISC_BASE + 0x034)
-#define PERIP1_SOF_RST		(MISC_BASE + 0x038)
-/* PERIP1_SOF_RST register masks */
-#define JPEG_SOF_RST		8
-
-#define SOC_USER_ID		(MISC_BASE + 0x03C)
-#define RAS_SOF_RST		(MISC_BASE + 0x040)
-#define PRSC1_CLK_CFG		(MISC_BASE + 0x044)
-#define PRSC2_CLK_CFG		(MISC_BASE + 0x048)
-#define PRSC3_CLK_CFG		(MISC_BASE + 0x04C)
-/* gpt synthesizer register masks */
-#define GPT_MSCALE_SHIFT	0
-#define GPT_MSCALE_MASK		0xFFF
-#define GPT_NSCALE_SHIFT	12
-#define GPT_NSCALE_MASK		0xF
-
-#define AMEM_CLK_CFG		(MISC_BASE + 0x050)
-#define EXPI_CLK_CFG		(MISC_BASE + 0x054)
-#define CLCD_CLK_SYNT		(MISC_BASE + 0x05C)
-#define FIRDA_CLK_SYNT		(MISC_BASE + 0x060)
-#define UART_CLK_SYNT		(MISC_BASE + 0x064)
-#define GMAC_CLK_SYNT		(MISC_BASE + 0x068)
-#define RAS1_CLK_SYNT		(MISC_BASE + 0x06C)
-#define RAS2_CLK_SYNT		(MISC_BASE + 0x070)
-#define RAS3_CLK_SYNT		(MISC_BASE + 0x074)
-#define RAS4_CLK_SYNT		(MISC_BASE + 0x078)
-/* aux clk synthesiser register masks for irda to ras4 */
-#define AUX_SYNT_ENB		31
-#define AUX_EQ_SEL_SHIFT	30
-#define AUX_EQ_SEL_MASK		1
-#define AUX_EQ1_SEL		0
-#define AUX_EQ2_SEL		1
-#define AUX_XSCALE_SHIFT	16
-#define AUX_XSCALE_MASK		0xFFF
-#define AUX_YSCALE_SHIFT	0
-#define AUX_YSCALE_MASK		0xFFF
-
-#define ICM1_ARB_CFG		(MISC_BASE + 0x07C)
-#define ICM2_ARB_CFG		(MISC_BASE + 0x080)
-#define ICM3_ARB_CFG		(MISC_BASE + 0x084)
-#define ICM4_ARB_CFG		(MISC_BASE + 0x088)
-#define ICM5_ARB_CFG		(MISC_BASE + 0x08C)
-#define ICM6_ARB_CFG		(MISC_BASE + 0x090)
-#define ICM7_ARB_CFG		(MISC_BASE + 0x094)
-#define ICM8_ARB_CFG		(MISC_BASE + 0x098)
-#define ICM9_ARB_CFG		(MISC_BASE + 0x09C)
 #define DMA_CHN_CFG		(MISC_BASE + 0x0A0)
-#define USB2_PHY_CFG		(MISC_BASE + 0x0A4)
-#define GMAC_CFG_CTR		(MISC_BASE + 0x0A8)
-#define EXPI_CFG_CTR		(MISC_BASE + 0x0AC)
-#define PRC1_LOCK_CTR		(MISC_BASE + 0x0C0)
-#define PRC2_LOCK_CTR		(MISC_BASE + 0x0C4)
-#define PRC3_LOCK_CTR		(MISC_BASE + 0x0C8)
-#define PRC4_LOCK_CTR		(MISC_BASE + 0x0CC)
-#define PRC1_IRQ_CTR		(MISC_BASE + 0x0D0)
-#define PRC2_IRQ_CTR		(MISC_BASE + 0x0D4)
-#define PRC3_IRQ_CTR		(MISC_BASE + 0x0D8)
-#define PRC4_IRQ_CTR		(MISC_BASE + 0x0DC)
-#define PWRDOWN_CFG_CTR		(MISC_BASE + 0x0E0)
-#define COMPSSTL_1V8_CFG	(MISC_BASE + 0x0E4)
-#define COMPSSTL_2V5_CFG	(MISC_BASE + 0x0E8)
-#define COMPCOR_3V3_CFG		(MISC_BASE + 0x0EC)
-#define SSTLPAD_CFG_CTR		(MISC_BASE + 0x0F0)
-#define BIST1_CFG_CTR		(MISC_BASE + 0x0F4)
-#define BIST2_CFG_CTR		(MISC_BASE + 0x0F8)
-#define BIST3_CFG_CTR		(MISC_BASE + 0x0FC)
-#define BIST4_CFG_CTR		(MISC_BASE + 0x100)
-#define BIST5_CFG_CTR		(MISC_BASE + 0x104)
-#define BIST1_STS_RES		(MISC_BASE + 0x108)
-#define BIST2_STS_RES		(MISC_BASE + 0x10C)
-#define BIST3_STS_RES		(MISC_BASE + 0x110)
-#define BIST4_STS_RES		(MISC_BASE + 0x114)
-#define BIST5_STS_RES		(MISC_BASE + 0x118)
-#define SYSERR_CFG_CTR		(MISC_BASE + 0x11C)
 
 #endif /* __MACH_MISC_REGS_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/spear.h b/arch/arm/mach-spear6xx/include/mach/spear.h
index 7fd621532def..cb8ed2f4dc85 100644
--- a/arch/arm/mach-spear6xx/include/mach/spear.h
+++ b/arch/arm/mach-spear6xx/include/mach/spear.h
@@ -15,69 +15,25 @@
 #define __MACH_SPEAR6XX_H
 
 #include <asm/memory.h>
-#include <mach/spear600.h>
 
-#define SPEAR6XX_ML_SDRAM_BASE		UL(0x00000000)
 /* ICM1 - Low speed connection */
 #define SPEAR6XX_ICM1_BASE		UL(0xD0000000)
-
+#define VA_SPEAR6XX_ICM1_BASE		UL(0xFD000000)
 #define SPEAR6XX_ICM1_UART0_BASE	UL(0xD0000000)
-#define VA_SPEAR6XX_ICM1_UART0_BASE	IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE)
-
-#define SPEAR6XX_ICM1_UART1_BASE	UL(0xD0080000)
-#define SPEAR6XX_ICM1_SSP0_BASE		UL(0xD0100000)
-#define SPEAR6XX_ICM1_SSP1_BASE		UL(0xD0180000)
-#define SPEAR6XX_ICM1_I2C_BASE		UL(0xD0200000)
-#define SPEAR6XX_ICM1_JPEG_BASE		UL(0xD0800000)
-#define SPEAR6XX_ICM1_IRDA_BASE		UL(0xD1000000)
-#define SPEAR6XX_ICM1_FSMC_BASE		UL(0xD1800000)
-#define SPEAR6XX_ICM1_NAND_BASE		UL(0xD2000000)
-#define SPEAR6XX_ICM1_SRAM_BASE		UL(0xD2800000)
-
-/* ICM2 - Application Subsystem */
-#define SPEAR6XX_ICM2_BASE		UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR0_BASE		UL(0xD8000000)
-#define SPEAR6XX_ICM2_TMR1_BASE		UL(0xD8080000)
-#define SPEAR6XX_ICM2_GPIO_BASE		UL(0xD8100000)
-#define SPEAR6XX_ICM2_SSP2_BASE		UL(0xD8180000)
-#define SPEAR6XX_ICM2_ADC_BASE		UL(0xD8200000)
+#define VA_SPEAR6XX_ICM1_UART0_BASE	(VA_SPEAR6XX_ICM1_2_BASE | SPEAR6XX_ICM1_UART0_BASE)
 
 /* ML-1, 2 - Multi Layer CPU Subsystem */
 #define SPEAR6XX_ML_CPU_BASE		UL(0xF0000000)
-#define SPEAR6XX_CPU_TMR_BASE		UL(0xF0000000)
-#define SPEAR6XX_CPU_GPIO_BASE		UL(0xF0100000)
-#define SPEAR6XX_CPU_VIC_SEC_BASE	UL(0xF1000000)
-#define VA_SPEAR6XX_CPU_VIC_SEC_BASE	IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE)
-#define SPEAR6XX_CPU_VIC_PRI_BASE	UL(0xF1100000)
-#define VA_SPEAR6XX_CPU_VIC_PRI_BASE	IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE)
+#define VA_SPEAR6XX_ML_CPU_BASE		UL(0xF0000000)
 
 /* ICM3 - Basic Subsystem */
-#define SPEAR6XX_ICM3_BASE		UL(0xF8000000)
-#define SPEAR6XX_ICM3_SMEM_BASE		UL(0xF8000000)
 #define SPEAR6XX_ICM3_SMI_CTRL_BASE	UL(0xFC000000)
-#define SPEAR6XX_ICM3_CLCD_BASE		UL(0xFC200000)
+#define VA_SPEAR6XX_ICM3_SMI_CTRL_BASE	UL(0xFC000000)
 #define SPEAR6XX_ICM3_DMA_BASE		UL(0xFC400000)
-#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE	UL(0xFC600000)
-#define SPEAR6XX_ICM3_TMR_BASE		UL(0xFC800000)
-#define SPEAR6XX_ICM3_WDT_BASE		UL(0xFC880000)
-#define SPEAR6XX_ICM3_RTC_BASE		UL(0xFC900000)
-#define SPEAR6XX_ICM3_GPIO_BASE		UL(0xFC980000)
 #define SPEAR6XX_ICM3_SYS_CTRL_BASE	UL(0xFCA00000)
-#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE	IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE)
+#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE	(VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_SYS_CTRL_BASE)
 #define SPEAR6XX_ICM3_MISC_REG_BASE	UL(0xFCA80000)
-#define VA_SPEAR6XX_ICM3_MISC_REG_BASE	IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE)
-
-/* ICM4 - High Speed Connection */
-#define SPEAR6XX_ICM4_BASE		UL(0xE0000000)
-#define SPEAR6XX_ICM4_GMAC_BASE		UL(0xE0800000)
-#define SPEAR6XX_ICM4_USBD_FIFO_BASE	UL(0xE1000000)
-#define SPEAR6XX_ICM4_USBD_CSR_BASE	UL(0xE1100000)
-#define SPEAR6XX_ICM4_USBD_PLDT_BASE	UL(0xE1200000)
-#define SPEAR6XX_ICM4_USB_EHCI0_BASE	UL(0xE1800000)
-#define SPEAR6XX_ICM4_USB_OHCI0_BASE	UL(0xE1900000)
-#define SPEAR6XX_ICM4_USB_EHCI1_BASE	UL(0xE2000000)
-#define SPEAR6XX_ICM4_USB_OHCI1_BASE	UL(0xE2100000)
-#define SPEAR6XX_ICM4_USB_ARB_BASE	UL(0xE2800000)
+#define VA_SPEAR6XX_ICM3_MISC_REG_BASE	(VA_SPEAR6XX_ICM3_SMI_CTRL_BASE | SPEAR6XX_ICM3_MISC_REG_BASE)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE		SPEAR6XX_ICM1_UART0_BASE
diff --git a/arch/arm/mach-spear6xx/include/mach/spear600.h b/arch/arm/mach-spear6xx/include/mach/spear600.h
deleted file mode 100644
index c068cc50b0fb..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/spear600.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-spear66xx/include/mach/spear600.h
- *
- * SPEAr600 Machine specific definition
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifdef	CONFIG_MACH_SPEAR600
-
-#ifndef __MACH_SPEAR600_H
-#define __MACH_SPEAR600_H
-
-#endif /* __MACH_SPEAR600_H */
-
-#endif /* CONFIG_MACH_SPEAR600 */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2ed8b14c82c8..2e2e3596583e 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -13,41 +13,404 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/amba/pl08x.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <asm/hardware/pl080.h>
 #include <asm/hardware/vic.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <plat/pl080.h>
 #include <mach/generic.h>
-#include <mach/hardware.h>
+#include <mach/spear.h>
 
-/* Following will create static virtual/physical mappings */
-static struct map_desc spear6xx_io_desc[] __initdata = {
+/* dmac device registration */
+static struct pl08x_channel_data spear600_dma_info[] = {
 	{
-		.virtual	= VA_SPEAR6XX_ICM1_UART0_BASE,
-		.pfn		= __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE
+		.bus_id = "ssp1_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
 	}, {
-		.virtual	= VA_SPEAR6XX_CPU_VIC_PRI_BASE,
-		.pfn		= __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE
+		.bus_id = "ssp1_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
 	}, {
-		.virtual	= VA_SPEAR6XX_CPU_VIC_SEC_BASE,
-		.pfn		= __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
-		.length		= SZ_4K,
-		.type		= MT_DEVICE
+		.bus_id = "uart0_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart0_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart1_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "uart1_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp2_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp2_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ssp0_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ssp0_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "i2c_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "irda",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "adc",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "to_jpeg",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "from_jpeg",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 0,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras0_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras1_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras2_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras3_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras4_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
+	}, {
+		.bus_id = "ras7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 1,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB1,
 	}, {
-		.virtual	= VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
-		.pfn		= __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
-		.length		= SZ_4K,
+		.bus_id = "ext0_rx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext0_tx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext1_rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext1_tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext2_rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext2_tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext3_rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext3_tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext4_rx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext4_tx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext5_rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext5_tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext6_rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext6_tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext7_rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	}, {
+		.bus_id = "ext7_tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.muxval = 2,
+		.cctl = 0,
+		.periph_buses = PL08X_AHB2,
+	},
+};
+
+struct pl08x_platform_data pl080_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		.cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
+			PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+			PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+			PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
+			PL080_CONTROL_PROT_SYS),
+	},
+	.lli_buses = PL08X_AHB1,
+	.mem_buses = PL08X_AHB1,
+	.get_signal = pl080_get_signal,
+	.put_signal = pl080_put_signal,
+	.slave_channels = spear600_dma_info,
+	.num_slave_channels = ARRAY_SIZE(spear600_dma_info),
+};
+
+/*
+ * Following will create 16MB static virtual/physical mappings
+ * PHYSICAL		VIRTUAL
+ * 0xF0000000		0xF0000000
+ * 0xF1000000		0xF1000000
+ * 0xD0000000		0xFD000000
+ * 0xFC000000		0xFC000000
+ */
+struct map_desc spear6xx_io_desc[] __initdata = {
+	{
+		.virtual	= VA_SPEAR6XX_ML_CPU_BASE,
+		.pfn		= __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
+		.length		= 2 * SZ_16M,
+		.type		= MT_DEVICE
+	},	{
+		.virtual	= VA_SPEAR6XX_ICM1_BASE,
+		.pfn		= __phys_to_pfn(SPEAR6XX_ICM1_BASE),
+		.length		= SZ_16M,
 		.type		= MT_DEVICE
 	}, {
-		.virtual	= VA_SPEAR6XX_ICM3_MISC_REG_BASE,
-		.pfn		= __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
-		.length		= SZ_4K,
+		.virtual	= VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
+		.pfn		= __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
+		.length		= SZ_16M,
 		.type		= MT_DEVICE
 	},
 };
@@ -56,9 +419,6 @@ static struct map_desc spear6xx_io_desc[] __initdata = {
 void __init spear6xx_map_io(void)
 {
 	iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
-
-	/* This will initialize clock framework */
-	spear6xx_clk_init();
 }
 
 static void __init spear6xx_timer_init(void)
@@ -66,6 +426,8 @@ static void __init spear6xx_timer_init(void)
 	char pclk_name[] = "pll3_48m_clk";
 	struct clk *gpt_clk, *pclk;
 
+	spear6xx_clk_init();
+
 	/* get the system timer clock */
 	gpt_clk = clk_get_sys("gpt0", NULL);
 	if (IS_ERR(gpt_clk)) {
@@ -85,16 +447,24 @@ static void __init spear6xx_timer_init(void)
 	clk_put(gpt_clk);
 	clk_put(pclk);
 
-	spear_setup_timer();
+	spear_setup_of_timer();
 }
 
 struct sys_timer spear6xx_timer = {
 	.init = spear6xx_timer_init,
 };
 
+/* Add auxdata to pass platform data */
+struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
+	OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
+			&pl080_plat_data),
+	{}
+};
+
 static void __init spear600_dt_init(void)
 {
-	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	of_platform_populate(NULL, of_default_bus_match_table,
+			spear6xx_auxdata_lookup, NULL);
 }
 
 static const char *spear600_dt_board_compat[] = {