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-rw-r--r--arch/arm/mach-mvebu/Kconfig7
-rw-r--r--arch/arm/mach-mvebu/armada-370-xp.c4
-rw-r--r--arch/arm/mach-mvebu/coherency_ll.S16
3 files changed, 17 insertions, 10 deletions
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 80a8bcacd9d5..9eb63d724602 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -10,12 +10,11 @@ config ARCH_MVEBU
select PLAT_ORION
select SPARSE_IRQ
select CLKDEV_LOOKUP
- select MVEBU_CLK_CORE
- select MVEBU_CLK_CPU
- select MVEBU_CLK_GATING
select MVEBU_MBUS
select ZONE_DMA if ARM_LPAE
select ARCH_REQUIRE_GPIOLIB
+ select MIGHT_HAVE_PCI
+ select PCI_QUIRKS if PCI
if ARCH_MVEBU
@@ -30,6 +29,7 @@ config MACH_ARMADA_370_XP
config MACH_ARMADA_370
bool "Marvell Armada 370 boards"
+ select ARMADA_370_CLK
select MACH_ARMADA_370_XP
select PINCTRL_ARMADA_370
help
@@ -38,6 +38,7 @@ config MACH_ARMADA_370
config MACH_ARMADA_XP
bool "Marvell Armada XP boards"
+ select ARMADA_XP_CLK
select MACH_ARMADA_370_XP
select PINCTRL_ARMADA_XP
help
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 0dbc370f9e35..97cbb8021919 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -14,11 +14,11 @@
#include <linux/kernel.h>
#include <linux/init.h>
+#include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/io.h>
#include <linux/time-armada-370-xp.h>
-#include <linux/clk/mvebu.h>
#include <linux/dma-mapping.h>
#include <linux/mbus.h>
#include <asm/hardware/cache-l2x0.h>
@@ -68,7 +68,7 @@ static void __init armada_370_xp_mbus_init(void)
static void __init armada_370_xp_timer_and_clk_init(void)
{
- mvebu_clocks_init();
+ of_clk_init(NULL);
armada_370_xp_timer_init();
coherency_init();
armada_370_xp_mbus_init();
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index 53e8391192cd..5476669ba905 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -32,15 +32,21 @@ ENTRY(ll_set_cpu_coherent)
/* Add CPU to SMP group - Atomic */
add r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
- ldr r2, [r3]
+1:
+ ldrex r2, [r3]
orr r2, r2, r1
- str r2, [r3]
+ strex r0, r2, [r3]
+ cmp r0, #0
+ bne 1b
/* Enable coherency on CPU - Atomic */
- add r3, r0, #ARMADA_XP_CFB_CFG_REG_OFFSET
- ldr r2, [r3]
+ add r3, r3, #ARMADA_XP_CFB_CFG_REG_OFFSET
+1:
+ ldrex r2, [r3]
orr r2, r2, r1
- str r2, [r3]
+ strex r0, r2, [r3]
+ cmp r0, #0
+ bne 1b
dsb
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