ATTR_SPD_DRAM_DEVICE_TYPE TARGET_TYPE_DIMM DRAM Device Type. Located in DDR3/DDR4 SPD byte 2. uint8 DDR3 = 0x0b, DDR4 = 0x0c ATTR_SPD_MODULE_TYPE TARGET_TYPE_DIMM Module Type. Located in DDR3/DDR4 SPD byte 3, bits 3-0. Note that CDIMM designation here is obsolete. See ATTR_SPD_CUSTOM uint8 CDIMM = 0x00, RDIMM = 0x01, UDIMM = 0x02, SO_DIMM=0x03, LRDIMM = 0x0b ATTR_SPD_CUSTOM TARGET_TYPE_DIMM Module Type is CUSTOM Located in DDR3/DDR4 SPD byte 3, bit 7. (Most significant bit) If bit 7 (reserved) is a '1' then this attribute value should be set to YES uint8 NO = 0x0, YES = 0x1 ATTR_SPD_SDRAM_DENSITY TARGET_TYPE_DIMM DRAM Density. Located in DDR3/DDR4 SPD byte 4, bits 3-0. uint8 D256MB = 0x00, D512Mb = 0x01, D1GB = 0x02, D2GB = 0x03, D4GB = 0x04, D8GB = 0x05, D16GB = 0x06, D32GB=0x07 ATTR_SPD_SDRAM_BANKS TARGET_TYPE_DIMM Number of banks. Located in DDR3 SPD byte 4, bits 6-4. Located in DDR4 SPD byte 4, bits 5-4. The raw data has different meanings for DDR3 and DDR4. HWPs must use this DDR neutral enumeration to decode. Platform support must call an Accessor HWP. uint8 B8 = 0x00, B16 = 0x01, B32 = 0x02, B64 = 0x03, B4 = 0x04, UNKNOWN = 0xff ATTR_SPD_SDRAM_ROWS TARGET_TYPE_DIMM Number of Rows. Located in DDR3/DDR4 SPD byte 5, bits 5-3. uint8 R12 = 0x00, R13 = 0x01, R14 = 0x02, R15 = 0x03, R16 = 0x04, R17 = 0x05, R18 = 0x06 ATTR_SPD_SDRAM_COLUMNS TARGET_TYPE_DIMM Number of Columns. Located in DDR3/DDR4 SPD byte 5, bits 2-0. uint8 C9 = 0x00, C10 = 0x01, C11 = 0x02, C12 = 0x03 ATTR_SPD_MODULE_NOMINAL_VOLTAGE TARGET_TYPE_DIMM Nominal voltage (bitmap). Located in DDR3 SPD byte 6, bits 2-0. Located in DDR4 SPD byte 11, bits 5-0. The raw data has different meanings for DDR3 and DDR4. HWPs must use this DDR neutral enumeration to decode. Platform support must call an Accessor HWP. uint8 NOTOP1_5 = 0x01, OP1_35 = 0x02, OP1_2X = 0x04, OP1_2V = 0x08, END1_2V = 0x10 ATTR_SPD_NUM_RANKS TARGET_TYPE_DIMM Number of ranks. Located in DDR3 SPD byte 7, bits 5-3. Located in DDR4 SPD byte 12, bits 5-3. uint8 R1 = 0x00, R2 = 0x01, R4 = 0x03, RX = 0xFF ATTR_SPD_DRAM_WIDTH TARGET_TYPE_DIMM DRAM Width. Located in DDR3 SPD byte 7, bits 2-0. Located in DDR4 SPD byte 12, bits 2-0. uint8 W4 = 0x00, W8 = 0x01, W16 = 0x02, W32 = 0x03 ATTR_SPD_MODULE_MEMORY_BUS_WIDTH TARGET_TYPE_DIMM Module Memory Bus Width. Located in DDR3 SPD byte 8, bits 4-0 Located in DDR4 SPD byte 13, bits 4-0. Bits 4-3 contain the Bus Width Extension (ECC) Bits 2-0 contain the Primary Bus Width uint8 W8 = 0x00, W16 = 0x01, W32 = 0x02, W64 = 0x03, WE8 = 0x08, WE16 = 0x09, WE32 = 0x0a, WE64 = 0x0b ATTR_SPD_TCKMIN TARGET_TYPE_DIMM Minimum cycle time (tCKmin). Located in DDR3 SPD byte 12. Located in DDR4 SPD byte 18. uint8 ATTR_SPD_CAS_LATENCIES_SUPPORTED TARGET_TYPE_DIMM CAS Latencies supported (bitmap). Located in DDR3 SPD byte 14 (LSB) and byte 15. Located in DDR4 SPD byte 20 (LSB) through byte 23 The raw data has different meanings for DDR3 and DDR4. HWPs must use this DDR neutral enumeration to decode. Platform support must call an Accessor HWP. uint32 CL_24 = 0x00100000, CL_23 = 0x00080000, CL_22 = 0x00040000, CL_21 = 0x00020000, CL_20 = 0x00010000, CL_19 = 0x00008000, CL_18 = 0x00004000, CL_17 = 0x00002000, CL_16 = 0x00001000, CL_15 = 0x00000800, CL_14 = 0x00000400, CL_13 = 0x00000200, CL_12 = 0x00000100, CL_11 = 0x00000080, CL_10 = 0x00000040, CL_9 = 0x00000020, CL_8 = 0x00000010, CL_7 = 0x00000008, CL_6 = 0x00000004, CL_5 = 0x00000002, CL_4 = 0x00000001 ATTR_SPD_TAAMIN TARGET_TYPE_DIMM Minimum CAS Latency Time (tAAmin). Located in DDR3 SPD byte 16. Located in DDR4 SPD byte 24. uint8 ATTR_SPD_TRCDMIN TARGET_TYPE_DIMM Minimum RAS# to CAS# Delay Time (tRCDmin). Located in DDR3 SPD byte 18. Located in DDR4 SPD byte 25. uint8 ATTR_SPD_TRPMIN TARGET_TYPE_DIMM Minimum Row Precharge Delay Time (tRPmin). Located in DDR3 SPD byte 20. Located in DDR4 SPD byte 26. uint8 ATTR_SPD_TRASMIN TARGET_TYPE_DIMM Minimum Active to Precharge Delay Time (tRASmin). Located in DDR3 SPD byte 21, bits 3-0 and byte 22 (LSB). Located in DDR4 SPD byte 27, bits 3-0 and byte 28 (LSB) uint32 ATTR_SPD_TRCMIN TARGET_TYPE_DIMM Minimum Active to Active/Refresh Delay Time (tRCmin). Located in DDR3 SPD byte 21, bits 7-4 and byte 23 (LSB). Located in DDR4 SPD byte 27, bits 7-4 and byte 29 (LSB) uint32 ATTR_SPD_TFAWMIN TARGET_TYPE_DIMM Minimum Four Activate Window Delay Time (tFAWmin). Located in DDR3 SPD byte 28, bits 3-0 and byte 29 (LSB). Located in DDR4 SPD byte 36, bits 3-0 and byte 37 (LSB). uint32 ATTR_SPD_SDRAM_OPTIONAL_FEATURES TARGET_TYPE_DIMM SDRAM Optional Features (bitmap). Located in DDR3 SPD byte 30. Located in DDR4 SPD byte 7, will be reserved and set to 0x0. uint8 DLL_OFF = 0x80, RZQ7 = 0x02, RZQ6 = 0x01 ATTR_SPD_SDRAM_THERMAL_AND_REFRESH_OPTIONS TARGET_TYPE_DIMM SDRAM Thermal and Refresh Options (bitmap). Located in DDR3 SPD byte 31. Located in DDR4 SPD byte 8, will be reserved and set to 0x0. uint8 PASR = 0x80, ODTS = 0x08, ASR = 0x05, ETRR = 0x02, ETR = 0x01 ATTR_SPD_MODULE_THERMAL_SENSOR TARGET_TYPE_DIMM Module Thermal Sensor. Located in DDR3 SPD byte 32. Located in DDR4 SPD byte 14. uint8 PRESENT = 0x80, ACCURACY_MASK = 0x7F ATTR_SPD_SDRAM_DEVICE_TYPE TARGET_TYPE_DIMM SDRAM Device Type. Located in DDR3 SPD byte 33, bit 7. Located in DDR4 SPD byte 6, bit 7. uint8 STANDARD_MONOLITHIC = 0x00, NON_STANDARD = 0x01 ATTR_SPD_SDRAM_DEVICE_TYPE_SIGNAL_LOADING TARGET_TYPE_DIMM SDRAM Device Type Signal Loading for stacked DRAMs. Located in DDR3 SPD byte 33, bits 1-0. Located in DDR4 SPD byte 6, bit 1-0. uint8 NOT_SPECIFIED = 0x00, MULTI_LOAD_STACK = 0x01, SINGLE_LOAD_STACK = 0x02 ATTR_SPD_SDRAM_DIE_COUNT TARGET_TYPE_DIMM SDRAM Device Type Die Count. Located in DDR3 SPD byte 33, bits 6-4. Located in DDR4 SPD byte 6, bit 6-4. uint8 DIE1 = 0x00, DIE2 = 0x01, DIE4 = 0x02, DIE8 = 0x03 ATTR_SPD_FINE_OFFSET_TCKMIN TARGET_TYPE_DIMM Fine Offset for SDRAM Minimum Cycle Time (tCKmin). Located in DDR3 SPD byte 34. Located in DDR4 SPD byte 125. uint8 ATTR_SPD_FINE_OFFSET_TAAMIN TARGET_TYPE_DIMM Fine Offset for Minimum CAS Latency Time (tAAmin). Located in DDR3 SPD byte 35. Located in DDR4 SPD byte 123. uint8 ATTR_SPD_FINE_OFFSET_TRCDMIN TARGET_TYPE_DIMM Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin). Located in DDR3 SPD byte 36. Located in DDR4 SPD byte 122. uint8 ATTR_SPD_FINE_OFFSET_TRPMIN TARGET_TYPE_DIMM Fine Offset for Minimum Row Precharge Delay Time (tRPmin). Located in DDR3 SPD byte 37. Located in DDR4 SPD byte 121. uint8 ATTR_SPD_FINE_OFFSET_TRCMIN TARGET_TYPE_DIMM Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin). Located in DDR3 SPD byte 38. Located in DDR4 SPD byte 120. uint8 ATTR_SPD_NUM_OF_REGISTERS_USED_ON_RDIMM TARGET_TYPE_DIMM Number of Registers used on RDIMM. Located in DDR3 SPD byte 63 bits 1-0. uint8 ATTR_SPD_MODULE_SPECIFIC_SECTION TARGET_TYPE_DIMM Module Specific Section. Located in DDR3 SPD bytes 60d - 116d. Located in DDR4 SPD bytes 128 - 255d. uint8 57 ATTR_SPD_MODULE_ID_MODULE_MANUFACTURERS_JEDEC_ID_CODE TARGET_TYPE_DIMM Module ID: Module Manufacturer's JEDEC ID Code. Located in DDR3 SPD bytes 117 (LSB) to 118. Located in DDR4 SPD bytes 320 (LSB) to 321. uint32 ATTR_SPD_MODULE_ID_MODULE_MANUFACTURING_LOCATION TARGET_TYPE_DIMM Module ID: Module Manufacturing Location. Located in DDR3 SPD byte 119. Located in DDR4 SPD byte 322. uint8 ATTR_SPD_MODULE_ID_MODULE_MANUFACTURING_DATE TARGET_TYPE_DIMM Module ID: Module Manufacturing Date. Located in DDR3 SPD bytes 120 (BCD year) to byte 121 (BCD week) (LSB). Located in DDR4 SPD bytes 323 (BCD year) to byte 324 (BCD week) (LSB). uint32 ATTR_SPD_MODULE_ID_MODULE_SERIAL_NUMBER TARGET_TYPE_DIMM Module ID: Module Serial Number. Located in DDR3 SPD bytes 122 (LSB) to 125. Located in DDR4 SPD bytes 325 (LSB) to 328. uint32 ATTR_SPD_CYCLICAL_REDUNDANCY_CODE TARGET_TYPE_DIMM Cyclical Redundancy Code. Located in DDR3 SPD bytes 126 (LSB) to 127. uint32 ATTR_SPD_MODULE_PART_NUMBER TARGET_TYPE_DIMM Module Part Number. Located in DDR3 SPD bytes 128 - 145. Located in DDR4 SPD bytes 329 - 348. uint8 18 ATTR_SPD_MODULE_REVISION_CODE TARGET_TYPE_DIMM Module Revision Code. Located in DDR3 SPD bytes 146 (LSB) to 147. Located in DDR4 SPD byte 349 The raw data has a different size for DDR3 and DDR4. HWPs must use this DDR neutral attribute. Platform support must call an Accessor HWP. uint32 ATTR_SPD_DRAM_MANUFACTURER_JEDEC_ID_CODE TARGET_TYPE_DIMM DRAM Manufacturer JEDEC ID Code. Located in DDR3 SPD bytes 148 (LSB) to 149. Located in DDR4 SPD bytes 350 (LSB) to 351. uint32 ATTR_SPD_BAD_DQ_DATA TARGET_TYPE_DIMM Bad DQ pin data stored in DIMM SPD. This data is in a special fomat. This must only be called by a firmware HWP that knows how to decode the data. HWP/PLAT firmware that needs to get/set the Bad DQ Bitmap from a Centaur DQ point of view must use the ATTR_BAD_DQ_BITMAP attribute. uint8 80 ATTR_VPD_DIMM_RCD_CNTL_WORD_0_15 TARGET_TYPE_DIMM RCD Control Word. Supplied by VPD, used by mss_eff_config.C and mss_draminit.C . Each dimm will have a value. consumer: mss_dram_init, mss_eff_config firmware notes: In order to make this readable to the OpenPower: It is necessary to swap the nibbles for a given byte. IE this is pulled from SPD bytes 69 - 76. The attribute would contain byte 69 nibble 1, followed by byte 69 nibble 0, followed by byte 70 nibble 1, and so forth. uint64 ATTR_VPD_DIMM_RCD_OUTPUT_TIMING TARGET_TYPE_MBA_CHIPLET RCD Timing. Supplied by VPD, used by mss_eff_config.C. Each dimm will have a value. consumer: mss_eff_config uint8 1T = 0x01, 3T = 0x03 2 2 ATTR_SPD_FTB_DIVIDEND TARGET_TYPE_DIMM Fine Timebase Dividend. Located in DDR3 SPD byte 9, bits 7-4. uint8 ATTR_SPD_FTB_DIVISOR TARGET_TYPE_DIMM Fine Timebase Divisor. Located in DDR3 SPD byte 9, bits 3-0. uint8 ATTR_SPD_MTB_DIVIDEND TARGET_TYPE_DIMM Medium Timebase Dividend. Located in DDR3 SPD byte 10. uint8 ATTR_SPD_MTB_DIVISOR TARGET_TYPE_DIMM Medium Timebase Divisor. Located in DDR3 SPD byte 11. uint8 ATTR_SPD_TWRMIN TARGET_TYPE_DIMM Minimum Write Recovery Time (tWRmin). Located in DDR3 SPD byte 17. uint8 ATTR_SPD_TRRDMIN TARGET_TYPE_DIMM Minimum Row Active to Row Active Delay Time (tRRDmin). Located in DDR3 SPD byte 19. uint8 ATTR_SPD_TRFCMIN TARGET_TYPE_DIMM Minimum Refresh Recovery Delay Time (tRFCmin). Located in DDR3 SPD byte 24 (LSB) and byte 25. uint32 ATTR_SPD_TWTRMIN TARGET_TYPE_DIMM Minimum Internal Write to Read Command Delay Time (tWTRmin). Located in DDR3 SPD byte 26. uint8 ATTR_SPD_TRTPMIN TARGET_TYPE_DIMM Minimum Internal Read to Precharge Command Delay Time (tRTPmin). Located in DDR3 SPD byte 27. uint8 ATTR_SPD_LR_ADDR_MIRRORING TARGET_TYPE_DIMM Load Reduced address mirroring attribute. Located in DDR3 SPD byte 63 bits 1-0. uint8 NO_RANKS = 0x00, ODD_RANKS = 0x01 ATTR_SPD_LR_F0RC3_F0RC2 TARGET_TYPE_DIMM Load Reduced F0RC3/F0RC2. Timing control AND Drive strength, Address/Command AND QxCS_n Located in DDR3 SPD byte 67. uint8 ATTR_SPD_LR_F0RC5_F0RC4 TARGET_TYPE_DIMM Load Reduced F0RC5/F0RC4. Drive strength, QxODT AND QxCKE and Clock. Located in DDR3 SPD byte 68. uint8 ATTR_SPD_LR_F1RC11_F1RC8 TARGET_TYPE_DIMM Load Reduced F1RC11/F1RC8. Extended delay for clocks, QxCS_n and QxODT AND QxCKE. Located in DDR3 SPD byte 69. uint8 ATTR_SPD_LR_F1RC13_F1RC12 TARGET_TYPE_DIMM Load Reduced F1RC13/F1RC12. Additive delay for QxCS_n and QxCA. Located in DDR3 SPD byte 70. uint8 ATTR_SPD_LR_F1RC15_F1RC14 TARGET_TYPE_DIMM Load Reduced F1RC15/F1RC14. Additive delay for QxODT and QxCKE. Located in DDR3 SPD byte 71. uint8 ATTR_SPD_LR_F3RC9_F3RC8_FOR_800_1066 TARGET_TYPE_DIMM Load Reduced F3RC9/F3RC8 for 800 AND 1066. DRAM interface MDQ Termination and Drive strength. Located in DDR3 SPD byte 72. uint8 ATTR_SPD_LR_F34RC11_F34RC10_FOR_800_1066 TARGET_TYPE_DIMM Load Reduced F[3,4]RC11/F[3,4]RC10 for 800 AND 1066. Rank 0AND1 Read and Write QxODT control. Located in DDR3 SPD byte 73. uint8 ATTR_SPD_LR_F56RC11_F56RC10_FOR_800_1066 TARGET_TYPE_DIMM Load Reduced F[5,6]RC11/F[5,6]RC10 for 800 AND 1066. Rank 2AND3 Read and Write QxODT control. Located in DDR3 SPD byte 74. uint8 ATTR_SPD_LR_F78RC11_F78RC10_FOR_800_1066 TARGET_TYPE_DIMM Load Reduced F[7,8]RC11/F[7,8]RC10 for 800 AND 1066. Rank 4AND5 Read and Write QxODT control. Located in DDR3 SPD byte 75. uint8 ATTR_SPD_LR_F910RC11_F910RC10_FOR_800_1066 TARGET_TYPE_DIMM Load Reduced F[9,10]RC11/F[9,10]RC10 for 800 AND 1066. Rank 6AND7 Read and Write QxODT control. Located in DDR3 SPD byte 76. uint8 ATTR_SPD_LR_MR12_FOR_800_1066 TARGET_TYPE_DIMM Load Reduced MR1,2 registers for 800 AND 1066. DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks. Located in DDR3 SPD byte 77. uint8 ATTR_SPD_LR_F3RC9_F3RC8_FOR_1333_1600 TARGET_TYPE_DIMM Load Reduced F3RC9/F3RC8 for 1333 AND 1600. DRAM interface MDQ Termination and Drive strength. Located in DDR3 SPD byte 78. uint8 ATTR_SPD_LR_F34RC11_F34RC10_FOR_1333_1600 TARGET_TYPE_DIMM Load Reduced F[3,4]RC11/F[3,4]RC10 for 1333 AND 1600. Rank 0AND1 Read and Write QxODT control. Located in DDR3 SPD byte 79. uint8 ATTR_SPD_LR_F56RC11_F56RC10_FOR_1333_1600 TARGET_TYPE_DIMM Load Reduced F[5,6]RC11/F[5,6]RC10 for 1333 AND 1600. Rank 2AND3 Read and Write QxODT control. Located in DDR3 SPD byte 80. uint8 ATTR_SPD_LR_F78RC11_F78RC10_FOR_1333_1600 TARGET_TYPE_DIMM Load Reduced F[7,8]RC11/F[7,8]RC10 for 1333 AND 1600. Rank 4AND5 Read and Write QxODT control. Located in DDR3 SPD byte 81. uint8 ATTR_SPD_LR_F910RC11_F910RC10_FOR_1333_1600 TARGET_TYPE_DIMM Load Reduced F[9,10]RC11/F[9,10]RC10 for 1333 AND 1600. Rank 6AND7 Read and Write QxODT control. Located in DDR3 SPD byte 82. uint8 ATTR_SPD_LR_MR12_FOR_1333_1600 TARGET_TYPE_DIMM Load Reduced MR1,2 registers for 1333 AND 1600. DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks. Located in DDR3 SPD byte 83. uint8 ATTR_SPD_LR_F3RC9_F3RC8_FOR_1866_2133 TARGET_TYPE_DIMM Load Reduced F3RC9/F3RC8 for 1866 AND 2133. DRAM interface MDQ Termination and Drive strength. Located in DDR3 SPD byte 84. uint8 ATTR_SPD_LR_F34RC11_F34RC10_FOR_1866_2133 TARGET_TYPE_DIMM Load Reduced F[3,4]RC11/F[3,4]RC10 for 1866 AND 2133. Rank 0AND1 Read and Write QxODT control. Located in DDR3 SPD byte 85. uint8 ATTR_SPD_LR_F56RC11_F56RC10_FOR_1866_2133 TARGET_TYPE_DIMM Load Reduced F[5,6]RC11/F[5,6]RC10 for 1866 AND 2133. Rank 2AND3 Read and Write QxODT control. Located in DDR3 SPD byte 86. uint8 ATTR_SPD_LR_F78RC11_F78RC10_FOR_1866_2133 TARGET_TYPE_DIMM Load Reduced F[7,8]RC11/F[7,8]RC10 for 1866 AND 2133. Rank 4AND5 Read and Write QxODT control. Located in DDR3 SPD byte 87. uint8 ATTR_SPD_LR_F910RC11_F910RC10_FOR_1866_2133 TARGET_TYPE_DIMM Load Reduced F[9,10]RC11/F[9,10]RC10 for 1866 AND 2133. Rank 6AND7 Read and Write QxODT control. Located in DDR3 SPD byte 88. uint8 ATTR_SPD_LR_MR12_FOR_1866_2133 TARGET_TYPE_DIMM Load Reduced MR1,2 registers for 1866 AND 2133. DRAM Rtt_WR for all ranks, DRAM Rtt_Nom for ranks 0 and 1, DRAM driver impedance for all ranks. Located in DDR3 SPD byte 89. uint8 ATTR_SPD_SDRAM_BANKGROUPS_DDR4 TARGET_TYPE_DIMM Number of bank groups. Located in DDR4 SPD byte 4, bits 7-6. uint8 BG0 = 0x00, BG2 = 0x01, BG4 = 0x02 ATTR_SPD_TIMEBASE_MTB_DDR4 TARGET_TYPE_DIMM defines a value in picoseconds that represents the fundamental timebase for medium grain timing calculations. This value is used as a multiplier for formulating subsequent timing parameters. Located in DDR4 SPD byte 17, bits 3-2. uint8 PS125 = 0x00 ATTR_SPD_TIMEBASE_FTB_DDR4 TARGET_TYPE_DIMM defines a value in picoseconds that represents the fundamental timebase for fine grain timing calculations. This value is used as a multiplier for formulating subsequent timing parameters. Located in DDR4 SPD byte 17, bits 1-0. uint8 PS1 = 0x00 ATTR_SPD_TCKMAX_DDR4 TARGET_TYPE_DIMM Maximum cycle time (tCKmax). Located in DDR4 SPD byte 19. uint8 ATTR_SPD_TRFC1MIN_DDR4 TARGET_TYPE_DIMM Minimum SDRAM Refresh Recovery Time Delay in medium timebase (MTB) units Located in DDR4 SPD bytes 30(MSB) and 31(LSB). uint32 ATTR_SPD_TRFC2MIN_DDR4 TARGET_TYPE_DIMM Minimum SDRAM Refresh Recovery Time Delay in medium timebase (MTB) units Located in DDR4 SPD bytes 32(MSB) and 33(LSB). uint32 ATTR_SPD_TRFC4MIN_DDR4 TARGET_TYPE_DIMM Minimum SDRAM Refresh Recovery Time Dealy in medium timebase (MTB) units. Located in DDR4 SPD byte 34(LSB) bits 15-8 and SPD byte 35(MSB) 7-0. uint32 ATTR_SPD_TRRDSMIN_DDR4 TARGET_TYPE_DIMM The minimum SDRAM Activate to Activate Delay Time to different bank groups in medium timebase (MTB) units. Controller designers must also note that at some frequencies, a minimum number of clocks may be required resulting in a larger tRRD_Smin value than indicated in the SPD. For example, tRRD_Smin for DDR4-1600 must be 4 clocks. Located in DDR4 SPD byte 38 uint8 ATTR_SPD_TRRDLMIN_DDR4 TARGET_TYPE_DIMM The minimum SDRAM Activate to Activate Delay Time to same bank groups in medium timebase (MTB) units. Controller designers must also note that at some frequencies, a minimum number of clocks may be required resulting in a larger tRRD_Smin value than indicated in the SPD. For example, tRRD_Lmin for DDR4-1600 must be 4 clocks. Located in DDR4 SPD byte 39 uint8 ATTR_SPD_TCCDLMIN_DDR4 TARGET_TYPE_DIMM The minimum SDRAM CAS to CAS Delay Time to same bank groups in medium timebase (MTB) units. Controller designers must also note that at some frequencies, a minimum number of clocks may be required resulting in a larger tCCD_Lmin value than indicated in the SPD. For example, tCCD_Lmin for DDR4-2133 must be 6 clocks. Located in DDR4 SPD byte 40 uint8 ATTR_SPD_FINE_OFFSET_TCCDLMIN_DDR4 TARGET_TYPE_DIMM Modifies the calculation of SPD Byte 40 with a fine correction using FTB units. The value of tCCD_Lmin comes from the SDRAM data sheet. This value is a two.s complement multiplier for FTB units, ranging from +127 to -128. Located in DDR4 SPD byte 117 uint8 ATTR_SPD_FINE_OFFSET_TRRDLMIN_DDR4 TARGET_TYPE_DIMM Modifies the calculation of SPD Byte 39 with a fine correction using FTB units. The value of tRRD_Lmin comes from the SDRAM data sheet. This value is a two.s complement multiplier for FTB units, ranging from +127 to -128. Located in DDR4 SPD byte 118 uint8 ATTR_SPD_FINE_OFFSET_TRRDSMIN_DDR4 TARGET_TYPE_DIMM Modifies the calculation of SPD Byte 38 (MTB units) with a fine correction using FTB units. The value of tRRD_Smin comes from the SDRAM data sheet. This value is a two.s complement multiplier for FTB units, ranging from +127 to -128. Located in DDR4 SPD byte 119 uint8 ATTR_SPD_FINE_OFFSET_TCKMAX_DDR4 TARGET_TYPE_DIMM Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmax). Located in DDR4 SPD byte 124. uint8 ATTR_SPD_CRC_BASE_CONFIG_DDR4 TARGET_TYPE_DIMM contains the calculated CRC for bytes 0~125 (0x000~0x07D) in the SPD Located in DDR4 SPD byte 126(LSB) and 127(MSB). uint32 ATTR_SPD_DRAM_STEPPING_DDR4 TARGET_TYPE_DIMM Defines the vendor die revision level (often called the .stepping.) of the DRAMs on the module. This byte is optional. For modules without DRAM stepping information, this byte should be programmed to 0xFF. Located in DDR4 SPD byte 352 uint8 ATTR_SPD_CRC_MNFG_SEC_DDR4 TARGET_TYPE_DIMM contains the calculated CRC for bytes 320~381 (0x140~0x17D) in the SPD Located in DDR4 SPD byte 382(LSB) and 383(MSB). uint32 ATTR_VPD_VERSION TARGET_TYPE_DIMM The VPD Version of this DIMM. The version number can be an indication of when different DIMM keywords are valid and is loaded from the platform. A version number of zero is unknown. uint32 ATTR_SPD_SDRAM_BANKS_DDR3 TARGET_TYPE_DIMM Number of banks. Located in DDR3 SPD byte 4, bits 6-4. This attribute must only be used by an Accessor HWP. Regular HWPs must use ATTR_SPD_SDRAM_BANKS. uint8 B8 = 0x00, B16 = 0x01, B32 = 0x02, B64 = 0x03 ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3 TARGET_TYPE_DIMM Nominal voltage (bitmap). Located in DDR3 SPD byte 6, bits 2-0. This attribute must only be used by an Accessor HWP. Regular HWPs must use ATTR_SPD_MODULE_NOMINAL_VOLTAGE. uint8 NOTOP1_5 = 0x01, OP1_35 = 0x02, OP1_2X = 0x04 ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3 TARGET_TYPE_DIMM CAS Latencies supported (bitmap). Located in DDR3 SPD byte 14 (LSB) and byte 15. This attribute must only be used by an Accessor HWP. Regular HWPs must use ATTR_SPD_CAS_LATENCIES_SUPPORTED. uint32 CL_18 = 0x00004000, CL_17 = 0x00002000, CL_16 = 0x00001000, CL_15 = 0x00000800, CL_14 = 0x00000400, CL_13 = 0x00000200, CL_12 = 0x00000100, CL_11 = 0x00000080, CL_10 = 0x00000040, CL_9 = 0x00000020, CL_8 = 0x00000010, CL_7 = 0x00000008, CL_6 = 0x00000004, CL_5 = 0x00000002, CL_4 = 0x00000001 ATTR_SPD_MODULE_REVISION_CODE_DDR3 TARGET_TYPE_DIMM Module Revision Code. Located in DDR3 SPD bytes 146 (LSB) to 147. This attribute must only be used by an Accessor HWP. Regular HWPs must use ATTR_SPD_MODULE_REVISION_CODE. uint32 ATTR_SPD_SDRAM_BANKS_DDR4 TARGET_TYPE_DIMM Number of banks. Located in DDR4 SPD byte 4, bits 5-4. This attribute must only be used by an Accessor HWP. Regular HWPs must use ATTR_SPD_SDRAM_BANKS. uint8 B4 = 0x00, B8 = 0x01 ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR4 TARGET_TYPE_DIMM Nominal voltage (bitmap). Located in DDR4 SPD byte 11, bits 5-0. This attribute must only be used by an Accessor HWP. Regular HWPs must use ATTR_SPD_MODULE_NOMINAL_VOLTAGE. uint8 OP1_2V = 0x01, END1_2V = 0x02, OPTBD1V = 0x04, ENDTBD1V = 0x08, OPTBD2V = 0x10, ENDTBD2V = 0x20 ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4 TARGET_TYPE_DIMM CAS Latencies supported (bitmap). Located in DDR4 SPD byte 20 (LSB) through byte 23. This attribute must only be used by an Accessor HWP. Regular HWPs must use ATTR_SPD_CAS_LATENCIES_SUPPORTED. uint32 CL_24 = 0x00020000, CL_23 = 0x00010000, CL_22 = 0x00008000, CL_21 = 0x00004000, CL_20 = 0x00002000, CL_19 = 0x00001000, CL_18 = 0x00000800, CL_17 = 0x00000400, CL_16 = 0x00000200, CL_15 = 0x00000100, CL_14 = 0x00000080, CL_13 = 0x00000040, CL_12 = 0x00000020, CL_11 = 0x00000010, CL_10 = 0x00000008, CL_9 = 0x00000004, CL_8 = 0x00000002, CL_7 = 0x00000001 ATTR_SPD_MODULE_REVISION_CODE_DDR4 TARGET_TYPE_DIMM Module Revision Code. Located in DDR4 SPD byte 349 This attribute must only be used by an Accessor HWP. Regular HWPs must use ATTR_SPD_MODULE_REVISION_CODE. uint8 ATTR_VPD_DRAM_ADDRESS_MIRRORING TARGET_TYPE_MBA_CHIPLET The C-DIMM ranks that have address mirroring. This data is in the Record:VSPD, Keyword:AM field in C-DIMM VPD. This attribute is only valid for C-DIMMs, an error should be returned if queried from IS-DIMMs. Note: Muliple ranks can be mirrored. uint8 RANK0_MIRRORED = 0x08, RANK1_MIRRORED = 0x04, RANK2_MIRRORED = 0x02, RANK3_MIRRORED = 0x01 2 2 ATTR_VPD_ODT_RD TARGET_TYPE_MBA_CHIPLET Read ODT. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT),mss_eff_cnfg_termination consumer: various.C files and initfiles firmware notes: none uint8 2 2 4 ATTR_VPD_ODT_WR TARGET_TYPE_MBA_CHIPLET Write ODT. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Creator: VPD(MT)/ mss_eff_cnfg_termination consumer: various.C and initfile firmware notes: none uint8 2 2 4 ATTR_VPD_DRAM_RON TARGET_TYPE_MBA_CHIPLET DRAM Ron. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. OHM48 is for DDR4. creator: VPD(MT)/mss_eff_cnfg_termination consumer: various.C files (no initfile) firmware notes: none This Attribute is to be interpreted as an Integer uint8 INVALID = 0, OHM34 = 34, OHM40 = 40, OHM48 = 48 2 2 ATTR_VPD_DRAM_RTT_NOM TARGET_TYPE_MBA_CHIPLET DRAM Rtt_Nom. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT),mss_eff_cnfg_termination consumer: various.C files (no initfiles) firmware notes: none This Attribute is to be interpreted as an Integer uint8 DISABLE = 0, OHM20 = 20, OHM30 = 30, OHM34 = 34, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM240 = 240 2 2 4 ATTR_VPD_DRAM_RTT_WR TARGET_TYPE_MBA_CHIPLET DRAM Rtt_WR. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Creator: VPD(MT), mss_eff_cnfg_termination consumer: various.C files (no initfiles) firmware notes: none This Attribute is to be interpreted as an Integer uint8 DISABLE = 0, OHM60 = 60, OHM120 = 120, OHM240 = 240, HIGHZ = 1 2 2 4 ATTR_VPD_DRAM_WR_VREF TARGET_TYPE_MBA_CHIPLET DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT) or mss_eff_cnfg_termination consumer: various.C and initfile firmware notes: none This is the nominal value This is for DDR3 This Attribute is to be interpreted as an Integer uint32 VDD420 = 420, VDD425 = 425, VDD430 = 430, VDD435 = 435, VDD440 = 440, VDD445 = 445, VDD450 = 450, VDD455 = 455, VDD460 = 460, VDD465 = 465, VDD470 = 470, VDD475 = 475, VDD480 = 480, VDD485 = 485, VDD490 = 490, VDD495 = 495, VDD500 = 500, VDD505 = 505, VDD510 = 510, VDD515 = 515, VDD520 = 520, VDD525 = 525, VDD530 = 530, VDD535 = 535, VDD540 = 540, VDD545 = 545, VDD550 = 550, VDD555 = 555, VDD560 = 560, VDD565 = 565, VDD570 = 570, VDD575 = 575 2 ATTR_VPD_DRAM_WRDDR4_VREF TARGET_TYPE_MBA_CHIPLET DRAM Write Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT) or mss_eff_cnfg_termination consumer: various firmware notes: none This is the nominal value This is for DDR4 The value is from 0 to 50 uint8 2 ATTR_VPD_CEN_DRV_IMP_DQ_DQS TARGET_TYPE_MBA_CHIPLET Centaur DQ and DQS Drive Impedance Used in various locations and comes from the MT Keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT)/mss_eff_cnfg_termination consumer: initfile,various.C files firmware notes: none This is the nominal value This Attribute is to be interpreted as an Integer uint8 OHM24_FFE0 = 0x0A, OHM30_FFE0 = 0x08, OHM30_FFE480 = 0x48, OHM30_FFE240 = 0x38, OHM30_FFE160 = 0x28, OHM30_FFE120 = 0x18, OHM34_FFE0 = 0x07, OHM34_FFE480 = 0x47, OHM34_FFE240 = 0x37, OHM34_FFE160 = 0x27, OHM34_FFE120 = 0x17, OHM40_FFE0 = 0x06, OHM40_FFE480 = 0x46, OHM40_FFE240 = 0x36, OHM40_FFE160 = 0x26, OHM40_FFE120 = 0x16 2 ATTR_VPD_CEN_DRV_IMP_ADDR TARGET_TYPE_MBA_CHIPLET Centaur Address Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: mss_eff_cnfg_termination consumer: initfile and various.C firmware notes: none This is the nominal value This Attribute is to be interpreted as an Integer uint8 OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40 2 ATTR_VPD_CEN_DRV_IMP_CNTL TARGET_TYPE_MBA_CHIPLET Centaur Control Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT)/mss_eff_cnfg_termination consumer: initfile,various .C firmware notes: none This is the nominal value This Attribute is to be interpreted as an Integer uint8 OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40 2 ATTR_VPD_CEN_DRV_IMP_CLK TARGET_TYPE_MBA_CHIPLET Centaur Clock Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT),mss_eff_cnfg_termination consumer: initfiles,various firmware notes: none This is the nominal value This Attribute is to be interpreted as an Integer uint8 OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40 2 ATTR_VPD_CEN_DRV_IMP_SPCKE TARGET_TYPE_MBA_CHIPLET Centaur Spare Clock Drive Impedance Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT) , mss_eff_cnfg_termination consumer: initfiles, various.C firmware notes: none This is the nominal value This Attribute is to be interpreted as an Integer uint8 OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40 2 ATTR_VPD_CEN_RCV_IMP_DQ_DQS TARGET_TYPE_MBA_CHIPLET Centaur DQ and DQS Receiver Impedance Used in various locations and it comes from the VPD MT keyword for custom DIMMs or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD, mss_eff_cnfg_termination Consumer: initfile + C code firmware notes: none This is the nominal value This Attribute is to be interpreted as an Integer uint8 OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40, OHM48 = 48, OHM60 = 60, OHM80 = 80, OHM120 = 120, OHM160 = 160, OHM240 = 240 2 ATTR_VPD_CEN_SLEW_RATE_DQ_DQS TARGET_TYPE_MBA_CHIPLET Centaur DQ and DQS Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT), mss_eff_cnfg_termination consumer: initfiles,various.C firmware notes: none This is the nominal value This Attribute is to be interpreted as an Integer except MAX uint8 SLEW_3V_NS = 3, SLEW_4V_NS = 4, SLEW_5V_NS = 5, SLEW_6V_NS = 6, SLEW_MAXV_NS = 7 2 ATTR_VPD_CEN_SLEW_RATE_ADDR TARGET_TYPE_MBA_CHIPLET Centaur Address Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT),mss_eff_cnfg_termination consumer: initfile,various .C files firmware notes: none This is the nominal value This Attribute is to be interpreted as an Integer except Max uint8 SLEW_3V_NS = 3, SLEW_4V_NS = 4, SLEW_5V_NS = 5, SLEW_6V_NS = 6, SLEW_MAXV_NS = 7 2 ATTR_VPD_CEN_SLEW_RATE_CLK TARGET_TYPE_MBA_CHIPLET Centaur Clock Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT)mss_eff_cnfg_termination consumer: initfile,various.C files firmware notes: none This is the nominal value This Attribute is to be interpreted as an Integer except max uint8 SLEW_3V_NS = 3, SLEW_4V_NS = 4, SLEW_5V_NS = 5, SLEW_6V_NS = 6, SLEW_MAXV_NS = 7 2 ATTR_VPD_CEN_SLEW_RATE_SPCKE TARGET_TYPE_MBA_CHIPLET Centaur Spare Clock Slew Rate Used in various locations and comes from the MT keyword or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT) or mss_eff_cnfg_termination consumer: initfile,various.C firmware notes: none This is the nominal value This Attribute is to be interpreted as an Integer except max uint8 SLEW_3V_NS = 3, SLEW_4V_NS = 4, SLEW_5V_NS = 5, SLEW_6V_NS = 6, SLEW_MAXV_NS = 7 2 ATTR_VPD_CEN_SLEW_RATE_CNTL TARGET_TYPE_MBA_CHIPLET Centaur Control Slew Rate Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Slowest slew rate is 0, incrementing by one. The lower the number the slower the slew rate the higher the faster. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. creator: VPD(MT),mss_eff_cnfg_termination consumer:initfile, various .C files firmware notes: none This is the nominal value This Attribute is to be interpreted as an Integer except for max uint8 SLEW_3V_NS = 3, SLEW_4V_NS = 4, SLEW_5V_NS = 5, SLEW_6V_NS = 6, SLEW_MAXV_NS = 7 2 ATTR_VPD_CEN_RD_VREF TARGET_TYPE_MBA_CHIPLET Centaur Read Vref. Used in various locations and comes from the MT keyword of the VPD or is computed in mss_eff_cnfg_termination. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Creator: VPD(MT) or mss_eff_cnfg_termination consumer: various.C and initfiles firmware notes: none This is the nominal value This Attribute is to be interpreted as an Integer uint32 VDD40375 = 40375, VDD41750 = 41750, VDD43125 = 43125, VDD44500 = 44500, VDD45875 = 45875, VDD47250 = 47250, VDD48625 = 48625, VDD50000 = 50000, VDD51375 = 51375, VDD52750 = 52750, VDD54125 = 54125, VDD55500 = 55500, VDD56875 = 56875, VDD58250 = 58250, VDD59625 = 59625, VDD61000 = 61000, VDD60375 = 60375, VDD61750 = 61750, VDD63125 = 63125, VDD64500 = 64500, VDD65875 = 65875, VDD67250 = 67250, VDD68625 = 68625, VDD70000 = 70000, VDD71375 = 71375, VDD72750 = 72750, VDD74125 = 74125, VDD75500 = 75500, VDD76875 = 76875, VDD78250 = 78250, VDD79625 = 79625, VDD81000 = 81000 2 ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CLK_P0 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CLK_P1 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CLK_P0 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CLK_P1 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A0 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A1 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A2 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A3 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A4 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A5 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A6 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A7 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A8 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A9 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A10 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A11 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A12 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A13 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A14 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_A15 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_BA0 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_BA1 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_BA2 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_CASN uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_RASN uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_CMD_WEN uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_PAR TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_PAR uint8 2 ATTR_VPD_CEN_PHASE_ROT_M_ACTN TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M_ACTN uint8 2 ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE0 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE1 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE2 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CKE3 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN0 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN1 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN2 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_CSN3 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_ODT0 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M0_CNTL_ODT1 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE0 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE1 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE2 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CKE3 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN0 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN1 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN2 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_CSN3 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_ODT0 uint8 2 ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1 TARGET_TYPE_MBA_CHIPLET Phase rotator value that comes from MR keyword on the CDIMM VPD. This controls the IO M1_CNTL_ODT1 uint8 2 ATTR_VPD_CKE_PRI_MAP TARGET_TYPE_MBA_CHIPLET This value comes from the VPD keyword MT bytes 54 and 55 MT(54:55) for the Logical DIMM associated with port A. Bytes 118:119 for port B, 182:183 for port C and 246:247 for port D. In the end, the AB and CD portions form a 32 bit word for each mba to write into the corresponding ddrphy register uint32 2 ATTR_VPD_CKE_PWR_MAP TARGET_TYPE_MBA_CHIPLET This value comes from the VPD keyword MT bytes 56 to 59 MT(56:59) for the Logical DIMM associated with port A. Bytes 120:123 for port B, 184:187 for port C and 248:251 for port D. The values for Port A concatenated with port B forms the value for one MBA. C concat D forms the value for the other MBA uint64 ATTR_VPD_GPO TARGET_TYPE_MBA_CHIPLET This value comes from the VPD keyword MT bytes 61 MT(61) for the Logical DIMM associated with port A. Bytes 125 for port B, 189 for port C and 253 for port D uint8 2 ATTR_VPD_RLO TARGET_TYPE_MBA_CHIPLET This value comes from the VPD keyword MT byte 60 bits 4:7 for the Logical DIMM associated with port A. Byte 124 bits 4:7 for port B, 188 bits 4:7 for port C and 252 bits 4:7 for port D uint8 2 ATTR_VPD_WLO TARGET_TYPE_MBA_CHIPLET This value comes from the VPD keyword MT byte 60 bits 0:3 for the Logical DIMM associated with port A. Byte 124 bits 0:3 for port B, 188 bits 0:3 for port C and 252 bits 0:3 for port D uint8 2 ATTR_VPD_TSYS_ADR TARGET_TYPE_MBA_CHIPLET This value comes from the VPD MR keyword byte 49 for ports A and B and byte 177 for port C and D. This means that all ADR blocks use this value on an mba level uint8 2 ATTR_VPD_TSYS_DP18 TARGET_TYPE_MBA_CHIPLET This value comes from the VPD MR keyword byte 113 for ports A and B and byte 241 for port C and D. This means all DP18 blocks use this value on a mba level uint8 2 ATTR_VPD_CDIMM_SENSOR_MAP_PRIMARY TARGET_TYPE_MEMBUF_CHIP Custom DIMM Sensor Map for Primary I2C Port (1 byte of data): 0x00 No sensors attached 0x01 DIMM sensor 0 attached 0x02 DIMM sensor 1 attached 0x04 DIMM sensor 2 attached 0x08 DIMM sensor 3 attached 0x10 DIMM sensor 4 attached 0x20 DIMM sensor 5 attached 0x40 DIMM sensor 6 attached 0x80 DIMM sensor 7 attached Comes from the VPD MW Keyword uint8 ATTR_VPD_CDIMM_SENSOR_MAP_SECONDARY TARGET_TYPE_MEMBUF_CHIP Custom DIMM Sensor Map for Secondary I2C Port (1 byte of data): 0x00 No sensors attached 0x01 DIMM sensor 0 attached 0x02 DIMM sensor 1 attached 0x04 DIMM sensor 2 attached 0x08 DIMM sensor 3 attached 0x10 DIMM sensor 4 attached 0x20 DIMM sensor 5 attached 0x40 DIMM sensor 6 attached 0x80 DIMM sensor 7 attached Comes from the VPD MW Keyword uint8 ATTR_VPD_DRAM_2N_MODE_ENABLED TARGET_TYPE_MBA_CHIPLET Describes if this MBA is in 2N address mode. The DIMM attributes associated with this MBA describes if this mode is needed for SI. Come from the VPD and consumed in the mba_def.initfile. uint8 FALSE = 0, TRUE = 1 ATTR_CDIMM_VPD_MASTER_POWER_SLOPE TARGET_TYPE_MEMBUF_CHIP Master Power Slope that comes from the VPD MW Keyword uint32 ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT TARGET_TYPE_MEMBUF_CHIP Master Power Intercept that comes from the VPD MW Keyword uint32 ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE TARGET_TYPE_MEMBUF_CHIP Supplier Power Slope that comes from the VPD the MV Keyword uint32 ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT TARGET_TYPE_MEMBUF_CHIP Supplier Power Intercept that comes from MV Keyword uint32 ATTR_L4_BANK_DELETE_VPD TARGET_TYPE_MEMBUF_CHIP L4 Bank Delete settings in VPD. Denotes what banks have been deleted from the L4. Data will be pulled from CDIMM VPD if CDIMM present. Data will be pulled from backplane VPD if IS DIMMs present. uint32 ATTR_SPD_MODSPEC_COM_REF_RAW_CARD_REV TARGET_TYPE_DIMM Reference Raw Card Revision Located in DDR3 SPD byte 62 bits 6-5. Located in DDR4 SPD byte 130 bits 6-5. uint8 ATTR_SPD_MODSPEC_COM_REF_RAW_CARD TARGET_TYPE_DIMM Reference Raw Card Located in DDR3 SPD byte 62 bit 7 + bits 4-0. Located in DDR4 SPD byte 130 bit 7 + bits 4-0. uint8 A = 0x00, B = 0x01, C = 0x02, D = 0x03, E = 0x04, F = 0x05, G = 0x06, H = 0x07, J = 0x08, K = 0x09, L = 0x0a, M = 0x0b, N = 0x0c, P = 0x0d, R = 0x0e, T = 0x0f, U = 0x10, V = 0x11, W = 0x12, Y = 0x13, AA = 0x14, AB = 0x15, AC = 0x16, AD = 0x17, AE = 0x18, AF = 0x19, AG = 0x1a, AH = 0x1b, AJ = 0x1c, AK = 0x1d, AL = 0x1e, AM = 0x20, AN = 0x21, AP = 0x22, AR = 0x23, AT = 0x24, AU = 0x25, AV = 0x26, AW = 0x27, AY = 0x28, BA = 0x29, BB = 0x2a, BC = 0x2b, BD = 0x2c, BE = 0x2d, BF = 0x2e, BG = 0x2f, BH = 0x30, BJ = 0x31, BK = 0x32, BL = 0x33, BM = 0x34, BN = 0x35, BP = 0x36, BR = 0x37, BT = 0x38, BU = 0x39, BV = 0x3a, BW = 0x3b, BY = 0x3c, CA = 0x3d, CB = 0x3e, ZZ = 0x3f ATTR_VPD_POWER_CONTROL_CAPABLE TARGET_TYPE_MEMBUF_CHIP Capable power control settings. uint8 NONE = 0x00, SLOWEXIT_CAPABLE = 0x01, FASTEXIT_CAPABLE = 0x02, FASTSLOW_CAPABLE = 0x03 ATTR_VPD_DIMM_RCD_IBT TARGET_TYPE_MBA_CHIPLET RCD IBT. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each dimm will have a value. creator: mss_eff_cnfg consumer: mss_dram_init firmware notes: none uint32 IBT_OFF = 0, IBT_100 = 100, IBT_150 = 150, IBT_200 = 200, IBT_300 = 300 2 2