# IBM_PROLOG_BEGIN_TAG
# This is an automatically generated prolog.
#
# $Source: src/usr/diag/prdf/common/plat/centaur/centaur_membuf.rule $
#
# OpenPOWER HostBoot Project
#
# Contributors Listed Below - COPYRIGHT 2016,2019
# [+] International Business Machines Corp.
#
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
# implied. See the License for the specific language governing
# permissions and limitations under the License.
#
# IBM_PROLOG_END_TAG

chip centaur_membuf
{
    name        "CENTAUR MEMBUF target";
    targettype  TYPE_MEMBUF;
    sigoff      0x9000;
    dump        DUMP_CONTENT_HW;
    scomlen     64;

# Import signatures
.include "prdfP9ProcMbCommonExtraSig.H";
.include "prdfCenMembufExtraSig.H";
.include "prdfLaneRepairExtraSig.H";

 #############################################################################
 #                                                                           #
 #  ######                                                                   #
 #  #     #  ######   ####     ###    ####    #####  ######  #####    ####   #
 #  #     #  #       #    #     #    #          #    #       #    #  #       #
 #  ######   #####   #          #     ####      #    #####   #    #   ####   #
 #  #   #    #       #  ###     #         #     #    #       #####        #  #
 #  #    #   #       #    #     #    #    #     #    #       #   #   #    #  #
 #  #     #  ######   ####     ###    ####      #    ######  #    #   ####   #
 #                                                                           #
 #############################################################################

    ############################################################################
    # Global Attention FIR
    ############################################################################

    register GLOBAL_CS_FIR
    {
        name        "Global Checkstop Attention FIR";
        scomaddr    0x500F001C;
        capture     group default;
    };

    register GLOBAL_RE_FIR
    {
        name        "Global Recoverable Attention FIR";
        scomaddr    0x500F001B;
        capture     group default;
    };

    ############################################################################
    # Global Special Attention FIR
    ############################################################################

    register GLOBAL_SPA_FIR
    {
        name        "Global Special Attention FIR";
        scomaddr    0x500F001A;
        capture     group default;
    };

    ############################################################################
    # TP Chiplet FIR
    ############################################################################

    register TP_CHIPLET_CS_FIR
    {
        name        "TP Chiplet Checkstop FIR";
        scomaddr    0x01040000;
        capture     group default;
    };

    register TP_CHIPLET_RE_FIR
    {
        name        "TP Chiplet Recoverable FIR";
        scomaddr    0x01040001;
        capture     group default;
    };

    register TP_CHIPLET_FIR_MASK
    {
        name        "TP Chiplet FIR MASK";
        scomaddr    0x01040002;
        capture     group default;
    };

    ############################################################################
    # Centaur chip TP_LFIR
    ############################################################################

    register TP_LFIR
    {
        name        "Centaur chip TP_LFIR";
        scomaddr    0x0104000A;
        reset       (&, 0x0104000B);
        mask        (|, 0x0104000F);
        capture     group default;
    };

    register TP_LFIR_MASK
    {
        name        "Centaur chip TP_LFIR MASK";
        scomaddr    0x0104000D;
        capture     group default;
    };

    register TP_LFIR_ACT0
    {
        name        "Centaur chip TP_LFIR ACT0";
        scomaddr    0x01040010;
        capture     group default;
        capture     req nonzero("TP_LFIR");
    };

    register TP_LFIR_ACT1
    {
        name        "Centaur chip TP_LFIR ACT1";
        scomaddr    0x01040011;
        capture     group default;
        capture     req nonzero("TP_LFIR");
    };

    ############################################################################
    # NEST Chiplet FIR
    ############################################################################

    register NEST_CHIPLET_CS_FIR
    {
        name        "NEST Chiplet Checkstop FIR";
        scomaddr    0x02040000;
        capture     group default;
    };

    register NEST_CHIPLET_RE_FIR
    {
        name        "NEST Chiplet Recoverable FIR";
        scomaddr    0x02040001;
        capture     group default;
    };

    register NEST_CHIPLET_FIR_MASK
    {
        name        "NEST Chiplet FIR MASK";
        scomaddr    0x02040002;
        capture     group default;
    };

    ############################################################################
    # Centaur chip NEST_LFIR
    ############################################################################

    register NEST_LFIR
    {
        name        "Centaur chip NEST_LFIR";
        scomaddr    0x0204000A;
        reset       (&, 0x0204000B);
        mask        (|, 0x0204000F);
        capture     group default;
    };

    register NEST_LFIR_MASK
    {
        name        "Centaur chip NEST_LFIR MASK";
        scomaddr    0x0204000D;
        capture     group default;
    };

    register NEST_LFIR_ACT0
    {
        name        "Centaur chip NEST_LFIR ACT0";
        scomaddr    0x02040010;
        capture     group default;
        capture     req nonzero("NEST_LFIR");
    };

    register NEST_LFIR_ACT1
    {
        name        "Centaur chip NEST_LFIR ACT1";
        scomaddr    0x02040011;
        capture     group default;
        capture     req nonzero("NEST_LFIR");
    };

    ############################################################################
    # Centaur chip DMIFIR
    ############################################################################

    register DMIFIR
    {
        name        "Centaur chip DMIFIR";
        scomaddr    0x02010400;
        reset       (&, 0x02010401);
        mask        (|, 0x02010405);
        capture     group default;
    };

    register DMIFIR_MASK
    {
        name        "Centaur chip DMIFIR MASK";
        scomaddr    0x02010403;
        capture     group default;
    };

    register DMIFIR_ACT0
    {
        name        "Centaur chip DMIFIR ACT0";
        scomaddr    0x02010406;
        capture     group default;
        capture     req nonzero("DMIFIR");
    };

    register DMIFIR_ACT1
    {
        name        "Centaur chip DMIFIR ACT1";
        scomaddr    0x02010407;
        capture     group default;
        capture     req nonzero("DMIFIR");
    };

    ############################################################################
    # Centaur chip MBIFIR
    ############################################################################

    register MBIFIR
    {
        name        "Centaur chip MBIFIR";
        scomaddr    0x02010800;
        reset       (&, 0x02010801);
        mask        (|, 0x02010805);
        capture     group default;
    };

    register MBIFIR_MASK
    {
        name        "Centaur chip MBIFIR MASK";
        scomaddr    0x02010803;
        capture     group default;
    };

    register MBIFIR_ACT0
    {
        name        "Centaur chip MBIFIR ACT0";
        scomaddr    0x02010806;
        capture     group default;
        capture     req nonzero("MBIFIR");
    };

    register MBIFIR_ACT1
    {
        name        "Centaur chip MBIFIR ACT1";
        scomaddr    0x02010807;
        capture     group default;
        capture     req nonzero("MBIFIR");
    };

    ############################################################################
    # Centaur chip MBSFIR
    ############################################################################

    register MBSFIR
    {
        name        "Centaur chip MBSFIR";
        scomaddr    0x02011400;
        reset       (&, 0x02011401);
        mask        (|, 0x02011405);
        capture     group default;
    };

    register MBSFIR_MASK
    {
        name        "Centaur chip MBSFIR MASK";
        scomaddr    0x02011403;
        capture     group default;
    };

    register MBSFIR_ACT0
    {
        name        "Centaur chip MBSFIR ACT0";
        scomaddr    0x02011406;
        capture     group default;
        capture     req nonzero("MBSFIR");
    };

    register MBSFIR_ACT1
    {
        name        "Centaur chip MBSFIR ACT1";
        scomaddr    0x02011407;
        capture     group default;
        capture     req nonzero("MBSFIR");
    };

    ############################################################################
    # Centaur chip MBSSECUREFIR
    ############################################################################

    # This register is hardwired to channel failure (checkstop) and we cannot
    # mask or change the state of the action registers.
    register MBSSECUREFIR
    {
        name        "Centaur chip MBSSECUREFIR";
        scomaddr    0x0201141e;
        reset       (&, 0x0201141f);
        capture     group default;
    };

    ############################################################################
    # Centaur chip MBSECCFIR 0
    ############################################################################

    register MBSECCFIR_0
    {
        name        "Centaur chip MBSECCFIR 0";
        scomaddr    0x02011440;
        reset       (&, 0x02011441);
        mask        (|, 0x02011445);
        capture     group default;
        capture     group MaintCmdRegs_mba0;
    };

    register MBSECCFIR_0_MASK
    {
        name        "Centaur chip MBSECCFIR 0 MASK";
        scomaddr    0x02011443;
        capture     group default;
        capture     group MaintCmdRegs_mba0;
    };

    register MBSECCFIR_0_ACT0
    {
        name        "Centaur chip MBSECCFIR 0 ACT0";
        scomaddr    0x02011446;
        capture     group default;
        capture     group MaintCmdRegs_mba0;
        capture     req nonzero("MBSECCFIR_0");
    };

    register MBSECCFIR_0_ACT1
    {
        name        "Centaur chip MBSECCFIR 0 ACT1";
        scomaddr    0x02011447;
        capture     group default;
        capture     group MaintCmdRegs_mba0;
        capture     req nonzero("MBSECCFIR_0");
    };

    ############################################################################
    # Centaur chip MBSECCFIR 1
    ############################################################################

    register MBSECCFIR_1
    {
        name        "Centaur chip MBSECCFIR 1";
        scomaddr    0x02011480;
        reset       (&, 0x02011481);
        mask        (|, 0x02011485);
        capture     group default;
        capture     group MaintCmdRegs_mba1;
    };

    register MBSECCFIR_1_MASK
    {
        name        "Centaur chip MBSECCFIR 1 MASK";
        scomaddr    0x02011483;
        capture     group default;
        capture     group MaintCmdRegs_mba1;
    };

    register MBSECCFIR_1_ACT0
    {
        name        "Centaur chip MBSECCFIR 1 ACT0";
        scomaddr    0x02011486;
        capture     group default;
        capture     group MaintCmdRegs_mba1;
        capture     req nonzero("MBSECCFIR_1");
    };

    register MBSECCFIR_1_ACT1
    {
        name        "Centaur chip MBSECCFIR 1 ACT1";
        scomaddr    0x02011487;
        capture     group default;
        capture     group MaintCmdRegs_mba1;
        capture     req nonzero("MBSECCFIR_1");
    };

    ############################################################################
    # Centaur chip SCACFIR
    ############################################################################

    register SCACFIR
    {
        name        "Centaur chip SCACFIR";
        scomaddr    0x020115c0;
        reset       (&, 0x020115c1);
        mask        (|, 0x020115c5);
        capture     group default;
    };

    register SCACFIR_MASK
    {
        name        "Centaur chip SCACFIR MASK";
        scomaddr    0x020115c3;
        capture     group default;
    };

    register SCACFIR_ACT0
    {
        name        "Centaur chip SCACFIR ACT0";
        scomaddr    0x020115c6;
        capture     group default;
        capture     req nonzero("SCACFIR");
    };

    register SCACFIR_ACT1
    {
        name        "Centaur chip SCACFIR ACT1";
        scomaddr    0x020115c7;
        capture     group default;
        capture     req nonzero("SCACFIR");
    };

    ############################################################################
    # Centaur chip MCBISTFIR 0
    ############################################################################

    register MCBISTFIR_0
    {
        name        "Centaur chip MCBISTFIR 0";
        scomaddr    0x02011600;
        reset       (&, 0x02011601);
        mask        (|, 0x02011605);
        capture     group default;
    };

    register MCBISTFIR_0_MASK
    {
        name        "Centaur chip MCBISTFIR 0 MASK";
        scomaddr    0x02011603;
        capture     group default;
    };

    register MCBISTFIR_0_ACT0
    {
        name        "Centaur chip MCBISTFIR 0 ACT0";
        scomaddr    0x02011606;
        capture     group default;
        capture     req nonzero("MCBISTFIR_0");
    };

    register MCBISTFIR_0_ACT1
    {
        name        "Centaur chip MCBISTFIR 0 ACT1";
        scomaddr    0x02011607;
        capture     group default;
        capture     req nonzero("MCBISTFIR_0");
    };

    ############################################################################
    # Centaur chip MCBISTFIR 1
    ############################################################################

    register MCBISTFIR_1
    {
        name        "Centaur chip MCBISTFIR 1";
        scomaddr    0x02011700;
        reset       (&, 0x02011701);
        mask        (|, 0x02011705);
        capture     group default;
    };

    register MCBISTFIR_1_MASK
    {
        name        "Centaur chip MCBISTFIR 1 MASK";
        scomaddr    0x02011703;
        capture     group default;
    };

    register MCBISTFIR_1_ACT0
    {
        name        "Centaur chip MCBISTFIR 1 ACT0";
        scomaddr    0x02011706;
        capture     group default;
        capture     req nonzero("MCBISTFIR_1");
    };

    register MCBISTFIR_1_ACT1
    {
        name        "Centaur chip MCBISTFIR 1 ACT1";
        scomaddr    0x02011707;
        capture     group default;
        capture     req nonzero("MCBISTFIR_1");
    };

    ############################################################################
    # MEM Chiplet FIR
    ############################################################################

    register MEM_CHIPLET_CS_FIR
    {
        name        "MEM Chiplet Checkstop FIR";
        scomaddr    0x03040000;
        capture     group MemChipletRegs;
    };

    register MEM_CHIPLET_RE_FIR
    {
        name        "MEM Chiplet Recoverable FIR";
        scomaddr    0x03040001;
        capture     group MemChipletRegs;
    };

    register MEM_CHIPLET_FIR_MASK
    {
        name        "MEM Chiplet FIR MASK";
        scomaddr    0x03040002;
        capture     group MemChipletRegs;
    };

    ############################################################################
    # MEM Chiplet Special Attention FIR
    ############################################################################

    register MEM_CHIPLET_SPA_FIR
    {
        name        "MEM Chiplet Special Attention FIR";
        scomaddr    0x03040004;
        capture     group MemChipletRegs;
    };

    register MEM_CHIPLET_SPA_FIR_MASK
    {
        name        "MEM Chiplet Special Attention FIR MASK";
        scomaddr    0x03040007;
        capture     group MemChipletRegs;
    };

    ############################################################################
    # Centaur chip MEM_LFIR
    ############################################################################

    register MEM_LFIR
    {
        name        "Centaur chip MEM_LFIR";
        scomaddr    0x0304000A;
        reset       (&, 0x0304000B);
        mask        (|, 0x0304000F);
        capture     group MemChipletRegs;
    };

    register MEM_LFIR_MASK
    {
        name        "Centaur chip MEM_LFIR MASK";
        scomaddr    0x0304000D;
        capture     group MemChipletRegs;
    };

    register MEM_LFIR_ACT0
    {
        name        "Centaur chip MEM_LFIR ACT0";
        scomaddr    0x03040010;
        capture     group MemChipletRegs;
        capture     req nonzero("MEM_LFIR");
    };

    register MEM_LFIR_ACT1
    {
        name        "Centaur chip MEM_LFIR ACT1";
        scomaddr    0x03040011;
        capture     group MemChipletRegs;
        capture     req nonzero("MEM_LFIR");
    };

# Include registers not defined by the xml
.include "centaur_membuf_regs.rule";

};

 ##############################################################################
 #                                                                            #
 # ####                                 #                                     #
 # #   # #   # #    #####  ###      #  # #    ##  ##### ###  ###  #   #  ###  #
 # #   # #   # #    #     #        #  #   #  #  #   #    #  #   # ##  # #     #
 # ####  #   # #    ####   ###    #  ####### #      #    #  #   # # # #  ###  #
 # #  #  #   # #    #         #  #   #     # #  #   #    #  #   # #  ##     # #
 # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
 #                                                                            #
 ##############################################################################

################################################################################
# Global Attention FIR
################################################################################

rule rGLOBAL_FIR
{
  UNIT_CS:
    GLOBAL_CS_FIR;
  RECOVERABLE:
    GLOBAL_RE_FIR;
};

group gGLOBAL_FIR attntype UNIT_CS, RECOVERABLE
    filter singlebit
{
    /** GLOBAL_FIR[1]
     *  Attention from TP chiplet
     */
    (rGLOBAL_FIR, bit(1)) ? analyze(gTP_CHIPLET_FIR);

    /** GLOBAL_FIR[2]
     *  Attention from NEST chiplet
     */
    (rGLOBAL_FIR, bit(2)) ? analyze(gNEST_CHIPLET_FIR);

    /** GLOBAL_FIR[3]
     *  Attention from MEM chiplet
     */
    (rGLOBAL_FIR, bit(3)) ? analyzeMemChipletFir;

};

################################################################################
# Global Special Attention FIR
################################################################################

rule rGLOBAL_SPA_FIR
{
  HOST_ATTN:
    GLOBAL_SPA_FIR;
};

group gGLOBAL_SPA_FIR attntype HOST_ATTN
    filter singlebit
{
    /** GLOBAL_SPA_FIR[3]
     *  Attention from MEM chiplet
     */
    (rGLOBAL_SPA_FIR, bit(3)) ? analyzeMemChipletSpa;

};

################################################################################
# TP Chiplet FIR
################################################################################

rule rTP_CHIPLET_FIR
{
  UNIT_CS:
     TP_CHIPLET_CS_FIR       & ~TP_CHIPLET_FIR_MASK & `1fffffffffffffff`;
  RECOVERABLE:
    (TP_CHIPLET_RE_FIR >> 2) & ~TP_CHIPLET_FIR_MASK & `1fffffffffffffff`;
};

group gTP_CHIPLET_FIR
    filter singlebit
{
    /** TP_CHIPLET_FIR[3]
     *  Attention from TP_LFIR
     */
    (rTP_CHIPLET_FIR, bit(3)) ? analyzeTP_LFIR;

};

################################################################################
# Centaur chip TP_LFIR
################################################################################

rule rTP_LFIR
{
  UNIT_CS:
    TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & ~TP_LFIR_ACT1;
  RECOVERABLE:
    TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 &  TP_LFIR_ACT1;
};

group gTP_LFIR
    filter singlebit,
           cs_root_cause(19,20)
{
    /** TP_LFIR[0]
     *  CFIR internal parity error
     */
    (rTP_LFIR, bit(0)) ? threshold_and_mask_self;

    /** TP_LFIR[1]
     *  GPIO (PCB error)
     */
    (rTP_LFIR, bit(1)) ? defaultMaskedError;

    /** TP_LFIR[2]
     *  CC (PCB error)
     */
    (rTP_LFIR, bit(2)) ? defaultMaskedError;

    /** TP_LFIR[3]
     *  CC (OPCG, parity, scan collision, ...)
     */
    (rTP_LFIR, bit(3)) ? defaultMaskedError;

    /** TP_LFIR[4]
     *  PSC (PCB error)
     */
    (rTP_LFIR, bit(4)) ? defaultMaskedError;

    /** TP_LFIR[5]
     *  PSC (parity error)
     */
    (rTP_LFIR, bit(5)) ? defaultMaskedError;

    /** TP_LFIR[6]
     *  Thermal (parity error)
     */
    (rTP_LFIR, bit(6)) ? defaultMaskedError;

    /** TP_LFIR[7]
     *  Thermal (PCB error)
     */
    (rTP_LFIR, bit(7)) ? defaultMaskedError;

    /** TP_LFIR[8]
     *  Thermal (critical trip error)
     */
    (rTP_LFIR, bit(8)) ? defaultMaskedError;

    /** TP_LFIR[9]
     *  Thermal (fatal trip error)
     */
    (rTP_LFIR, bit(9)) ? defaultMaskedError;

    /** TP_LFIR[10]
     *  Thermal (voltage trip error)
     */
    (rTP_LFIR, bit(10)) ? defaultMaskedError;

    /** TP_LFIR[11]
     *  Trace Array ( error)
     */
    (rTP_LFIR, bit(11)) ? defaultMaskedError;

    /** TP_LFIR[12]
     *  Trace Array ( error)
     */
    (rTP_LFIR, bit(12)) ? defaultMaskedError;

    /** TP_LFIR[13:14]
     *  ITR
     */
    (rTP_LFIR, bit(13|14)) ? threshold_and_mask_self;

    /** TP_LFIR[15]
     *  ITR (itr_tc_pcbsl_slave_fir_err)
     */
    (rTP_LFIR, bit(15)) ? defaultMaskedError;

    /** TP_LFIR[16:18]
     *  PIB
     */
    (rTP_LFIR, bit(16|17|18)) ? defaultMaskedError;

    /** TP_LFIR[19]
     *  NEST PLL unlock
     */
    (rTP_LFIR, bit(19)) ? pll_unlock_UERE;

    /** TP_LFIR[20]
     *  MEM PLL unlock
     */
    (rTP_LFIR, bit(20)) ? pll_unlock_UERE;

    /** TP_LFIR[21:39]
     *  Reserved
     */
    (rTP_LFIR, bit(21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError;

    /** TP_LFIR[40]
     *  malfunction alert (local xstop in another chiplet)
     */
    (rTP_LFIR, bit(40)) ? defaultMaskedError;

};

################################################################################
# NEST Chiplet FIR
################################################################################

rule rNEST_CHIPLET_FIR
{
  UNIT_CS:
     NEST_CHIPLET_CS_FIR       & ~NEST_CHIPLET_FIR_MASK & `1fffffffffffffff`;
  RECOVERABLE:
    (NEST_CHIPLET_RE_FIR >> 2) & ~NEST_CHIPLET_FIR_MASK & `1fffffffffffffff`;
};

group gNEST_CHIPLET_FIR
    filter priority(3,6,5,7)
{
    # NOTE: The MBIFIR must be analyzed before the DMIFIR and both the MBIFIR
    # and DMIFIR must be analyzed before the MBSFIR. All other FIRs will be
    # analyzed in order.

    /** NEST_CHIPLET_FIR[3]
     *  Attention from NEST_LFIR
     */
    (rNEST_CHIPLET_FIR, bit(3)) ? analyzeNEST_LFIR;

    /** NEST_CHIPLET_FIR[5]
     *  Attention from DMIFIR
     */
    (rNEST_CHIPLET_FIR, bit(5)) ? analyzeDMIFIR;

    /** NEST_CHIPLET_FIR[6]
     *  Attention from MBIFIR
     */
    (rNEST_CHIPLET_FIR, bit(6)) ? analyzeMBIFIR;

    /** NEST_CHIPLET_FIR[7]
     *  Attention from MBSFIR
     */
    (rNEST_CHIPLET_FIR, bit(7)) ? analyzeMBSFIR;

    /** NEST_CHIPLET_FIR[8]
     *  Attention from MCBISTFIR
     */
    (rNEST_CHIPLET_FIR, bit(8)) ? analyzeMCBISTFIR_0;

    /** NEST_CHIPLET_FIR[9]
     *  Attention from MCBISTFIR
     */
    (rNEST_CHIPLET_FIR, bit(9)) ? analyzeMCBISTFIR_1;

    /** NEST_CHIPLET_FIR[10]
     *  Attention from MBSECCFIR
     */
    (rNEST_CHIPLET_FIR, bit(10)) ? analyzeMBSECCFIR_0;

    /** NEST_CHIPLET_FIR[11]
     *  Attention from MBSECCFIR
     */
    (rNEST_CHIPLET_FIR, bit(11)) ? analyzeMBSECCFIR_1;

    /** NEST_CHIPLET_FIR[13]
     *  Attention from SCACFIR
     */
    (rNEST_CHIPLET_FIR, bit(13)) ? analyzeSCACFIR;

    /** NEST_CHIPLET_FIR[14]
     *  Attention from MBSSECUREFIR
     */
    (rNEST_CHIPLET_FIR, bit(14)) ? analyzeMBSSECUREFIR;

};

################################################################################
# Centaur chip NEST_LFIR
################################################################################

rule rNEST_LFIR
{
  UNIT_CS:
    NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & ~NEST_LFIR_ACT1;
  RECOVERABLE:
    NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 &  NEST_LFIR_ACT1;
};

group gNEST_LFIR
    filter singlebit,
           cs_root_cause
{
    /** NEST_LFIR[0]
     *  CFIR internal parity error
     */
    (rNEST_LFIR, bit(0)) ? threshold_and_mask_self;

    /** NEST_LFIR[1]
     *  GPIO (PCB error)
     */
    (rNEST_LFIR, bit(1)) ? defaultMaskedError;

    /** NEST_LFIR[2]
     *  CC (PCB error)
     */
    (rNEST_LFIR, bit(2)) ? defaultMaskedError;

    /** NEST_LFIR[3]
     *  CC (OPCG, parity, scan collision, ...)
     */
    (rNEST_LFIR, bit(3)) ? defaultMaskedError;

    /** NEST_LFIR[4]
     *  PSC (PCB error)
     */
    (rNEST_LFIR, bit(4)) ? defaultMaskedError;

    /** NEST_LFIR[5]
     *  PSC (parity error)
     */
    (rNEST_LFIR, bit(5)) ? defaultMaskedError;

    /** NEST_LFIR[6]
     *  Thermal (parity error)
     */
    (rNEST_LFIR, bit(6)) ? defaultMaskedError;

    /** NEST_LFIR[7]
     *  Thermal (PCB error)
     */
    (rNEST_LFIR, bit(7)) ? defaultMaskedError;

    /** NEST_LFIR[8]
     *  Thermal (critical trip error)
     */
    (rNEST_LFIR, bit(8)) ? defaultMaskedError;

    /** NEST_LFIR[9]
     *  Thermal (fatal trip error)
     */
    (rNEST_LFIR, bit(9)) ? defaultMaskedError;

    /** NEST_LFIR[10]
     *  Thermal (voltage trip error)
     */
    (rNEST_LFIR, bit(10)) ? defaultMaskedError;

    /** NEST_LFIR[11]
     *  Trace Array ( error)
     */
    (rNEST_LFIR, bit(11)) ? defaultMaskedError;

    /** NEST_LFIR[12]
     *  Trace Array ( error)
     */
    (rNEST_LFIR, bit(12)) ? defaultMaskedError;

    /** NEST_LFIR[13:39]
     *  Reserved
     */
    (rNEST_LFIR, bit(13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError;

    /** NEST_LFIR[40]
     *  malfunction alert (local xstop in another chiplet)
     */
    (rNEST_LFIR, bit(40)) ? defaultMaskedError;

};

################################################################################
# Centaur chip DMIFIR
################################################################################

rule rDMIFIR
{
  UNIT_CS:
    DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & ~DMIFIR_ACT1;
  RECOVERABLE:
    DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 &  DMIFIR_ACT1;
};

group gDMIFIR
    filter priority(10,2,11,12,9),
           cs_root_cause(12)
{
    /** DMIFIR[0]
     *  RX invalid state or parity error
     */
    (rDMIFIR, bit(0)) ? defaultMaskedError;

    /** DMIFIR[1]
     *  TX invalid state or parity error
     */
    (rDMIFIR, bit(1)) ? defaultMaskedError;

    /** DMIFIR[2]
     *  GCR hang error
     */
    (rDMIFIR, bit(2)) ? self_th_1;

    /** DMIFIR[3:7]
     *  Reserved
     */
    (rDMIFIR, bit(3|4|5|6|7)) ? defaultMaskedError;

    /** DMIFIR[8]
     *  Training error
     */
    (rDMIFIR, bit(8)) ? defaultMaskedError;

    /** DMIFIR[9]
     *  Spare lane deployed
     */
    (rDMIFIR, bit(9)) ? spareDeployed_dmibus;

    /** DMIFIR[10]
     *  Max spares exceeded
     */
    (rDMIFIR, bit(10)) ? maxSparesExceeded_dmibus;

    /** DMIFIR[11]
     *  Recal or dynamic repair error
     */
    (rDMIFIR, bit(11)) ? calloutBusInterface_dmibus_th1;

    /** DMIFIR[12]
     *  Too many bus errors
     */
    (rDMIFIR, bit(12)) ? tooManyBusErrors_dmibus_UERE;

    /** DMIFIR[13:15]
     *  Reserved
     */
    (rDMIFIR, bit(13|14|15)) ? defaultMaskedError;

    /** DMIFIR[16:23]
     *  Bus 1 - unused
     */
    (rDMIFIR, bit(16|17|18|19|20|21|22|23)) ? defaultMaskedError;

    /** DMIFIR[24:31]
     *  Bus 2 - unused
     */
    (rDMIFIR, bit(24|25|26|27|28|29|30|31)) ? defaultMaskedError;

    /** DMIFIR[32:39]
     *  Bus 3 - unused
     */
    (rDMIFIR, bit(32|33|34|35|36|37|38|39)) ? defaultMaskedError;

    /** DMIFIR[40:47]
     *  Bus 4 - unused
     */
    (rDMIFIR, bit(40|41|42|43|44|45|46|47)) ? defaultMaskedError;

    /** DMIFIR[48]
     *  scom error
     */
    (rDMIFIR, bit(48)) ? threshold_and_mask_self;

    /** DMIFIR[49]
     *  scom error
     */
    (rDMIFIR, bit(49)) ? threshold_and_mask_self;

};

################################################################################
# Centaur chip MBIFIR
################################################################################

rule rMBIFIR
{
  UNIT_CS:
    MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & ~MBIFIR_ACT1;
  RECOVERABLE:
    MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 &  MBIFIR_ACT1;
};

group gMBIFIR
    filter priority(8,9,19,20,6,0,16,5,10),
           cs_root_cause(0,6,8,9,19,20)
{
    /** MBIFIR[0]
     *  Replay Timeout
     */
    (rMBIFIR, bit(0)) ? replay_timeout_UERE;

    /** MBIFIR[1]
     *  Channel Fail
     */
    (rMBIFIR, bit(1)) ? defaultMaskedError;

    /** MBIFIR[2]
     *  CRC Error
     */
    (rMBIFIR, bit(2)) ? defaultMaskedError;

    /** MBIFIR[3]
     *  Frame NoAck
     */
    (rMBIFIR, bit(3)) ? defaultMaskedError;

    /** MBIFIR[4]
     *  Seqid Out of Order
     */
    (rMBIFIR, bit(4)) ? defaultMaskedError;

    /** MBIFIR[5]
     *  Replay Buffer ECC CE
     */
    (rMBIFIR, bit(5)) ? self_th_5perHour;

    /** MBIFIR[6]
     *  Replay Buffer ECC UE
     */
    (rMBIFIR, bit(6)) ? self_th_1_UERE;

    /** MBIFIR[7]
     *  MBI State Machine Timeout
     */
    (rMBIFIR, bit(7)) ? defaultMaskedError;

    /** MBIFIR[8]
     *  MBI Internal Control Parity Error
     */
    (rMBIFIR, bit(8)) ? self_th_1_UERE;

    /** MBIFIR[9]
     *  MBI Data Flow Parity Error
     */
    (rMBIFIR, bit(9)) ? self_th_1_UERE;

    /** MBIFIR[10]
     *  CRC Performance Degradation
     */
    (rMBIFIR, bit(10)) ? defaultMaskedError;

    /** MBIFIR[11]
     *  Global Host MC Checkstop
     */
    (rMBIFIR, bit(11)) ? defaultMaskedError;

    /** MBIFIR[12]
     *  Host MC Tracestop
     */
    (rMBIFIR, bit(12)) ? defaultMaskedError;

    /** MBIFIR[13]
     *  Channel Interlock Fail
     */
    (rMBIFIR, bit(13)) ? defaultMaskedError;

    /** MBIFIR[14]
     *  Host MC Local Checkstop
     */
    (rMBIFIR, bit(14)) ? defaultMaskedError;

    /** MBIFIR[15]
     *  FRTL Counter Overflow
     */
    (rMBIFIR, bit(15)) ? defaultMaskedError;

    /** MBIFIR[16]
     *  SCOM Register parity error
     */
    (rMBIFIR, bit(16)) ? self_th_1;

    /** MBIFIR[17]
     *  IO Fault
     */
    (rMBIFIR, bit(17)) ? defaultMaskedError;

    /** MBIFIR[18]
     *  Multiple Replay
     */
    (rMBIFIR, bit(18)) ? defaultMaskedError;

    /** MBIFIR[19]
     *  MBICFG parity error
     */
    (rMBIFIR, bit(19)) ? self_th_1_UERE;

    /** MBIFIR[20]
     *  Replay Buffer Overrun
     */
    (rMBIFIR, bit(20)) ? calloutBusInterface_dmibus_th1_UERE;

    /** MBIFIR[21]
     *  WAT error
     */
    (rMBIFIR, bit(21)) ? defaultMaskedError;

    /** MBIFIR[22:24]
     *  Reserved
     */
    (rMBIFIR, bit(22|23|24)) ? defaultMaskedError;

    /** MBIFIR[25]
     *  internal scom error
     */
    (rMBIFIR, bit(25)) ? threshold_and_mask_self;

    /** MBIFIR[26]
     *  internal scom error clone
     */
    (rMBIFIR, bit(26)) ? threshold_and_mask_self;

};

################################################################################
# Centaur chip MBSFIR
################################################################################

rule rMBSFIR
{
  UNIT_CS:
    MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & ~MBSFIR_ACT1;
  RECOVERABLE:
    MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 &  MBSFIR_ACT1;
};

group gMBSFIR
    filter singlebit,
           cs_root_cause(0,1,2,4,6,8,10,13,16,18,20,27,30)
{
    /** MBSFIR[0]
     *  HOST_PROTOCOL_ERROR
     */
    (rMBSFIR, bit(0)) ? calloutBusInterface_dmibus_th1_UERE;

    /** MBSFIR[1]
     *  INT_PROTOCOL_ERROR
     */
    (rMBSFIR, bit(1)) ? self_th_1_UERE;

    /** MBSFIR[2]
     *  INVALID_ADDRESS_ERROR
     */
    (rMBSFIR, bit(2)) ? calloutBusInterface_dmibus_th1_UERE;

    /** MBSFIR[3]
     *  EXTERNAL_TIMEOUT
     */
    (rMBSFIR, bit(3)) ? defaultMaskedError;

    /** MBSFIR[4]
     *  INTERNAL_TIMEOUT
     */
    (rMBSFIR, bit(4)) ? mbs_internal_timeout;

    /** MBSFIR[5]
     *  INT_BUFFER_CE
     */
    (rMBSFIR, bit(5)) ? self_th_32perDay;

    /** MBSFIR[6]
     *  INT_BUFFER_UE
     */
    (rMBSFIR, bit(6)) ? self_th_1_UERE;

    /** MBSFIR[7]
     *  INT_BUFFER_SUE
     */
    (rMBSFIR, bit(7)) ? defaultMaskedError;

    /** MBSFIR[8]
     *  INT_PARITY_ERROR
     */
    (rMBSFIR, bit(8)) ? self_th_1_UERE;

    /** MBSFIR[9]
     *  CACHE_SRW_CE
     */
    (rMBSFIR, bit(9)) ? l4_cache_srw_ce;

    /** MBSFIR[10]
     *  CACHE_SRW_UE
     */
    (rMBSFIR, bit(10)) ? l4_cache_srw_ue_UERE;

    /** MBSFIR[11]
     *  CACHE_SRW_SUE
     */
    (rMBSFIR, bit(11)) ? defaultMaskedError;

    /** MBSFIR[12]
     *  CACHE_CO_CE
     */
    (rMBSFIR, bit(12)) ? l4_cache_co_ce;

    /** MBSFIR[13]
     *  CACHE_CO_UE
     */
    (rMBSFIR, bit(13)) ? l4_cache_co_ue_UERE;

    /** MBSFIR[14]
     *  CACHE_CO_SUE
     */
    (rMBSFIR, bit(14)) ? defaultMaskedError;

    /** MBSFIR[15]
     *  DIR_CE
     */
    (rMBSFIR, bit(15)) ? l4_th_32perDay;

    /** MBSFIR[16]
     *  DIR_UE
     */
    (rMBSFIR, bit(16)) ? l4_th_1_UERE;

    /** MBSFIR[17]
     *  DIR_MEMBER_DELETED
     */
    (rMBSFIR, bit(17)) ? defaultMaskedError;

    /** MBSFIR[18]
     *  DIR_ALL_MEMBERS_DELETED
     */
    (rMBSFIR, bit(18)) ? l4_th_1_UERE;

    /** MBSFIR[19]
     *  LRU_ERROR
     */
    (rMBSFIR, bit(19)) ? l4_th_32perDay;

    /** MBSFIR[20]
     *  EDRAM ERROR
     */
    (rMBSFIR, bit(20)) ? l4_th_1_UERE;

    /** MBSFIR[21]
     *  EMERGENCY_THROTTLE_SET
     */
    (rMBSFIR, bit(21)) ? defaultMaskedError;

    /** MBSFIR[22]
     *  HOST_INBAND_READ_ERROR
     */
    (rMBSFIR, bit(22)) ? defaultMaskedError;

    /** MBSFIR[23]
     *  HOST_INBAND_WRITE_ERROR
     */
    (rMBSFIR, bit(23)) ? defaultMaskedError;

    /** MBSFIR[24]
     *  OCC_INBAND_READ_ERROR
     */
    (rMBSFIR, bit(24)) ? defaultMaskedError;

    /** MBSFIR[25]
     *  OCC_INBAND_WRITE_ERROR
     */
    (rMBSFIR, bit(25)) ? defaultMaskedError;

    /** MBSFIR[26]
     *  SRB_BUFFER_CE
     */
    (rMBSFIR, bit(26)) ? threshold_and_mask_self;

    /** MBSFIR[27]
     *  SRB_BUFFER_UE
     */
    (rMBSFIR, bit(27)) ? self_th_1_UERE;

    /** MBSFIR[28]
     *  SRB_BUFFER_SUE
     */
    (rMBSFIR, bit(28)) ? defaultMaskedError;

    /** MBSFIR[29]
     *  DIR_PURGE_CE
     */
    (rMBSFIR, bit(29)) ? defaultMaskedError;

    /** MBSFIR[30]
     *  PROXIMAL_CE_UE
     */
    (rMBSFIR, bit(30)) ? l4_th_1_UERE;

    /** MBSFIR[31:32]
     *  Spare
     */
    (rMBSFIR, bit(31|32)) ? defaultMaskedError;

    /** MBSFIR[33]
     *  SCOM FIR error
     */
    (rMBSFIR, bit(33)) ? threshold_and_mask_self;

    /** MBSFIR[34]
     *  SCOM FIR error clone
     */
    (rMBSFIR, bit(34)) ? threshold_and_mask_self;

};

################################################################################
# Centaur chip MBSSECUREFIR
################################################################################

rule rMBSSECUREFIR
{
  UNIT_CS:
    MBSSECUREFIR;
};

group gMBSSECUREFIR
    filter singlebit,
           cs_root_cause(0,1,2,3,4,5)
{
    /** MBSSECUREFIR[0]
     *  Invalid MBSXCR access
     */
    (rMBSSECUREFIR, bit(0)) ? level2_th_1_UERE;

    /** MBSSECUREFIR[1]
     *  Invalid MBSXCR01 access
     */
    (rMBSSECUREFIR, bit(1)) ? level2_th_1_UERE;

    /** MBSSECUREFIR[2]
     *  Invalid MBSXCR23 access
     */
    (rMBSSECUREFIR, bit(2)) ? level2_th_1_UERE;

    /** MBSSECUREFIR[3]
     *  Invalid MBSXCRMS access
     */
    (rMBSSECUREFIR, bit(3)) ? level2_th_1_UERE;

    /** MBSSECUREFIR[4]
     *  spare
     */
    (rMBSSECUREFIR, bit(4)) ? level2_th_1_UERE;

    /** MBSSECUREFIR[5]
     *  Invalid SIR mask or action reg access
     */
    (rMBSSECUREFIR, bit(5)) ? level2_th_1_UERE;

};

################################################################################
# Centaur chip MBSECCFIR 0
################################################################################

rule rMBSECCFIR_0
{
  UNIT_CS:
    MBSECCFIR_0 & ~MBSECCFIR_0_MASK & ~MBSECCFIR_0_ACT0 & ~MBSECCFIR_0_ACT1;
  RECOVERABLE:
    MBSECCFIR_0 & ~MBSECCFIR_0_MASK & ~MBSECCFIR_0_ACT0 &  MBSECCFIR_0_ACT1;
};

group gMBSECCFIR_0
    filter priority(19,41),
           cs_root_cause(19,44,47,49)
{
    /** MBSECCFIR_0[0]
     *  Memory chip mark on rank 0
     */
    (rMBSECCFIR_0, bit(0)) ? verify_chip_mark_rnk0_mba0;

    /** MBSECCFIR_0[1]
     *  Memory chip mark on rank 1
     */
    (rMBSECCFIR_0, bit(1)) ? verify_chip_mark_rnk1_mba0;

    /** MBSECCFIR_0[2]
     *  Memory chip mark on rank 2
     */
    (rMBSECCFIR_0, bit(2)) ? verify_chip_mark_rnk2_mba0;

    /** MBSECCFIR_0[3]
     *  Memory chip mark on rank 3
     */
    (rMBSECCFIR_0, bit(3)) ? verify_chip_mark_rnk3_mba0;

    /** MBSECCFIR_0[4]
     *  Memory chip mark on rank 4
     */
    (rMBSECCFIR_0, bit(4)) ? verify_chip_mark_rnk4_mba0;

    /** MBSECCFIR_0[5]
     *  Memory chip mark on rank 5
     */
    (rMBSECCFIR_0, bit(5)) ? verify_chip_mark_rnk5_mba0;

    /** MBSECCFIR_0[6]
     *  Memory chip mark on rank 6
     */
    (rMBSECCFIR_0, bit(6)) ? verify_chip_mark_rnk6_mba0;

    /** MBSECCFIR_0[7]
     *  Memory chip mark on rank 7
     */
    (rMBSECCFIR_0, bit(7)) ? verify_chip_mark_rnk7_mba0;

    /** MBSECCFIR_0[8:15]
     *  Reserved
     */
    (rMBSECCFIR_0, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError;

    /** MBSECCFIR_0[16]
     *  Memory NCE
     */
    (rMBSECCFIR_0, bit(16)) ? mainline_nce_handling_mba0;

    /** MBSECCFIR_0[17]
     *  Memory RCE
     */
    (rMBSECCFIR_0, bit(17)) ? mainline_rce_pue_handling_mba0;

    /** MBSECCFIR_0[18]
     *  Memory SUE
     */
    (rMBSECCFIR_0, bit(18)) ? defaultMaskedError;

    /** MBSECCFIR_0[19]
     *  Memory UE
     */
    (rMBSECCFIR_0, bit(19)) ? mainline_ue_handling_mba0_UERE;

    /** MBSECCFIR_0[20:27]
     *  Maintenance chip mark
     */
    (rMBSECCFIR_0, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError;

    /** MBSECCFIR_0[28:35]
     *  Reserved
     */
    (rMBSECCFIR_0, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError;

    /** MBSECCFIR_0[36]
     *  Maintenance NCE
     */
    (rMBSECCFIR_0, bit(36)) ? defaultMaskedError;

    /** MBSECCFIR_0[37]
     *  Maintenance SCE
     */
    (rMBSECCFIR_0, bit(37)) ? defaultMaskedError;

    /** MBSECCFIR_0[38]
     *  Maintenance MCE
     */
    (rMBSECCFIR_0, bit(38)) ? defaultMaskedError;

    /** MBSECCFIR_0[39]
     *  Maintenance RCE
     */
    (rMBSECCFIR_0, bit(39)) ? defaultMaskedError;

    /** MBSECCFIR_0[40]
     *  Maintenance SUE
     */
    (rMBSECCFIR_0, bit(40)) ? defaultMaskedError;

    /** MBSECCFIR_0[41]
     *  Maintenance UE
     */
    (rMBSECCFIR_0, bit(41)) ? defaultMaskedError;

    /** MBSECCFIR_0[42]
     *  MPE during use maintenance mark mode
     */
    (rMBSECCFIR_0, bit(42)) ? defaultMaskedError;

    /** MBSECCFIR_0[43]
     *  Prefetch Memory UE
     */
    (rMBSECCFIR_0, bit(43)) ? mainline_rce_pue_handling_mba0;

    /** MBSECCFIR_0[44]
     *  Memory RCD parity error
     */
    (rMBSECCFIR_0, bit(44)) ? self_th_1_UERE; # CUMULUS_10

    /** MBSECCFIR_0[45]
     *  Maintenance RCD parity error
     */
    (rMBSECCFIR_0, bit(45)) ? defaultMaskedError;

    /** MBSECCFIR_0[46]
     *  Recoverable config reg PE
     */
    (rMBSECCFIR_0, bit(46)) ? mba0_th_1;

    /** MBSECCFIR_0[47]
     *  Unrecoverable config reg PE
     */
    (rMBSECCFIR_0, bit(47)) ? mba0_th_1_UERE;

    /** MBSECCFIR_0[48]
     *  Maskable config reg PE
     */
    (rMBSECCFIR_0, bit(48)) ? threshold_and_mask_mba0;

    /** MBSECCFIR_0[49]
     *  ECC datapath parity error
     */
    (rMBSECCFIR_0, bit(49)) ? mba0_th_1_UERE;

    /** MBSECCFIR_0[50]
     *  internal scom error
     */
    (rMBSECCFIR_0, bit(50)) ? threshold_and_mask_mba0;

    /** MBSECCFIR_0[51]
     *  internal scom error clone
     */
    (rMBSECCFIR_0, bit(51)) ? threshold_and_mask_mba0;

};

################################################################################
# Centaur chip MBSECCFIR 1
################################################################################

rule rMBSECCFIR_1
{
  UNIT_CS:
    MBSECCFIR_1 & ~MBSECCFIR_1_MASK & ~MBSECCFIR_1_ACT0 & ~MBSECCFIR_1_ACT1;
  RECOVERABLE:
    MBSECCFIR_1 & ~MBSECCFIR_1_MASK & ~MBSECCFIR_1_ACT0 &  MBSECCFIR_1_ACT1;
};

group gMBSECCFIR_1
    filter priority(19,41),
           cs_root_cause(19,44,47,49)
{
    /** MBSECCFIR_1[0]
     *  Memory chip mark on rank 0
     */
    (rMBSECCFIR_1, bit(0)) ? verify_chip_mark_rnk0_mba1;

    /** MBSECCFIR_1[1]
     *  Memory chip mark on rank 1
     */
    (rMBSECCFIR_1, bit(1)) ? verify_chip_mark_rnk1_mba1;

    /** MBSECCFIR_1[2]
     *  Memory chip mark on rank 2
     */
    (rMBSECCFIR_1, bit(2)) ? verify_chip_mark_rnk2_mba1;

    /** MBSECCFIR_1[3]
     *  Memory chip mark on rank 3
     */
    (rMBSECCFIR_1, bit(3)) ? verify_chip_mark_rnk3_mba1;

    /** MBSECCFIR_1[4]
     *  Memory chip mark on rank 4
     */
    (rMBSECCFIR_1, bit(4)) ? verify_chip_mark_rnk4_mba1;

    /** MBSECCFIR_1[5]
     *  Memory chip mark on rank 5
     */
    (rMBSECCFIR_1, bit(5)) ? verify_chip_mark_rnk5_mba1;

    /** MBSECCFIR_1[6]
     *  Memory chip mark on rank 6
     */
    (rMBSECCFIR_1, bit(6)) ? verify_chip_mark_rnk6_mba1;

    /** MBSECCFIR_1[7]
     *  Memory chip mark on rank 7
     */
    (rMBSECCFIR_1, bit(7)) ? verify_chip_mark_rnk7_mba1;

    /** MBSECCFIR_1[8:15]
     *  Reserved
     */
    (rMBSECCFIR_1, bit(8|9|10|11|12|13|14|15)) ? defaultMaskedError;

    /** MBSECCFIR_1[16]
     *  Memory NCE
     */
    (rMBSECCFIR_1, bit(16)) ? mainline_nce_handling_mba1;

    /** MBSECCFIR_1[17]
     *  Memory RCE
     */
    (rMBSECCFIR_1, bit(17)) ? mainline_rce_pue_handling_mba1;

    /** MBSECCFIR_1[18]
     *  Memory SUE
     */
    (rMBSECCFIR_1, bit(18)) ? defaultMaskedError;

    /** MBSECCFIR_1[19]
     *  Memory UE
     */
    (rMBSECCFIR_1, bit(19)) ? mainline_ue_handling_mba1_UERE;

    /** MBSECCFIR_1[20:27]
     *  Maintenance chip mark
     */
    (rMBSECCFIR_1, bit(20|21|22|23|24|25|26|27)) ? defaultMaskedError;

    /** MBSECCFIR_1[28:35]
     *  Reserved
     */
    (rMBSECCFIR_1, bit(28|29|30|31|32|33|34|35)) ? defaultMaskedError;

    /** MBSECCFIR_1[36]
     *  Maintenance NCE
     */
    (rMBSECCFIR_1, bit(36)) ? defaultMaskedError;

    /** MBSECCFIR_1[37]
     *  Maintenance SCE
     */
    (rMBSECCFIR_1, bit(37)) ? defaultMaskedError;

    /** MBSECCFIR_1[38]
     *  Maintenance MCE
     */
    (rMBSECCFIR_1, bit(38)) ? defaultMaskedError;

    /** MBSECCFIR_1[39]
     *  Maintenance RCE
     */
    (rMBSECCFIR_1, bit(39)) ? defaultMaskedError;

    /** MBSECCFIR_1[40]
     *  Maintenance SUE
     */
    (rMBSECCFIR_1, bit(40)) ? defaultMaskedError;

    /** MBSECCFIR_1[41]
     *  Maintenance UE
     */
    (rMBSECCFIR_1, bit(41)) ? defaultMaskedError;

    /** MBSECCFIR_1[42]
     *  MPE during use maintenance mark mode
     */
    (rMBSECCFIR_1, bit(42)) ? defaultMaskedError;

    /** MBSECCFIR_1[43]
     *  Prefetch Memory UE
     */
    (rMBSECCFIR_1, bit(43)) ? mainline_rce_pue_handling_mba1;

    /** MBSECCFIR_1[44]
     *  Memory RCD parity error
     */
    (rMBSECCFIR_1, bit(44)) ? self_th_1_UERE; # CUMULUS_10

    /** MBSECCFIR_1[45]
     *  Maintenance RCD parity error
     */
    (rMBSECCFIR_1, bit(45)) ? defaultMaskedError;

    /** MBSECCFIR_1[46]
     *  Recoverable config reg PE
     */
    (rMBSECCFIR_1, bit(46)) ? mba1_th_1;

    /** MBSECCFIR_1[47]
     *  Unrecoverable config reg PE
     */
    (rMBSECCFIR_1, bit(47)) ? mba1_th_1_UERE;

    /** MBSECCFIR_1[48]
     *  Maskable config reg PE
     */
    (rMBSECCFIR_1, bit(48)) ? threshold_and_mask_mba1;

    /** MBSECCFIR_1[49]
     *  ECC datapath parity error
     */
    (rMBSECCFIR_1, bit(49)) ? mba1_th_1_UERE;

    /** MBSECCFIR_1[50]
     *  internal scom error
     */
    (rMBSECCFIR_1, bit(50)) ? threshold_and_mask_mba1;

    /** MBSECCFIR_1[51]
     *  internal scom error clone
     */
    (rMBSECCFIR_1, bit(51)) ? threshold_and_mask_mba1;

};

################################################################################
# Centaur chip SCACFIR
################################################################################

rule rSCACFIR
{
  UNIT_CS:
    SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 & ~SCACFIR_ACT1;
  RECOVERABLE:
    SCACFIR & ~SCACFIR_MASK & ~SCACFIR_ACT0 &  SCACFIR_ACT1;
};

group gSCACFIR
    filter singlebit,
           cs_root_cause(25,26)
{
    /** SCACFIR[0]
     *  I2CM(0) Invalid Address
     */
    (rSCACFIR, bit(0)) ? defaultMaskedError;

    /** SCACFIR[1]
     *  I2CM(1) Invalid Write
     */
    (rSCACFIR, bit(1)) ? defaultMaskedError;

    /** SCACFIR[2]
     *  I2CM(2) Invalid Read
     */
    (rSCACFIR, bit(2)) ? defaultMaskedError;

    /** SCACFIR[3]
     *  I2CM(3) Pib Address Parity Error
     */
    (rSCACFIR, bit(3)) ? defaultMaskedError;

    /** SCACFIR[4]
     *  I2CM(4) Pib Parity Error
     */
    (rSCACFIR, bit(4)) ? defaultMaskedError;

    /** SCACFIR[5]
     *  I2CM(5) LB parity error
     */
    (rSCACFIR, bit(5)) ? defaultMaskedError;

    /** SCACFIR[6:9]
     *  spare
     */
    (rSCACFIR, bit(6|7|8|9)) ? defaultMaskedError;

    /** SCACFIR[10]
     *  I2CM(45) : Invalid Command
     */
    (rSCACFIR, bit(10)) ? defaultMaskedError;

    /** SCACFIR[11]
     *  I2CM(46) : Parity Error
     */
    (rSCACFIR, bit(11)) ? defaultMaskedError;

    /** SCACFIR[12]
     *  I2CM(47): Backend Overrun Error
     */
    (rSCACFIR, bit(12)) ? defaultMaskedError;

    /** SCACFIR[13]
     *  I2CM(48): Backend Access Error
     */
    (rSCACFIR, bit(13)) ? defaultMaskedError;

    /** SCACFIR[14]
     *  I2CM(49): Arbitration Lost Error
     */
    (rSCACFIR, bit(14)) ? defaultMaskedError;

    /** SCACFIR[15]
     *  I2CM(50): Nack Received Error
     */
    (rSCACFIR, bit(15)) ? defaultMaskedError;

    /** SCACFIR[16]
     *  I2CM(53): Stop Error
     */
    (rSCACFIR, bit(16)) ? defaultMaskedError;

    /** SCACFIR[17]
     *  Local PIB Response code 1
     */
    (rSCACFIR, bit(17)) ? defaultMaskedError;

    /** SCACFIR[18]
     *  Local PIB Response code 2
     */
    (rSCACFIR, bit(18)) ? defaultMaskedError;

    /** SCACFIR[19]
     *  Local PIB Response code 3
     */
    (rSCACFIR, bit(19)) ? defaultMaskedError;

    /** SCACFIR[20]
     *  Local PIB Response code 4
     */
    (rSCACFIR, bit(20)) ? defaultMaskedError;

    /** SCACFIR[21]
     *  Local PIB Response code 5
     */
    (rSCACFIR, bit(21)) ? defaultMaskedError;

    /** SCACFIR[22]
     *  Local PIB Response code 6
     */
    (rSCACFIR, bit(22)) ? defaultMaskedError;

    /** SCACFIR[23]
     *  Local PIB Response code 7
     */
    (rSCACFIR, bit(23)) ? defaultMaskedError;

    /** SCACFIR[24]
     *  Stall Threshold Error
     */
    (rSCACFIR, bit(24)) ? defaultMaskedError;

    /** SCACFIR[25]
     *  Parity Error on Internal Register
     */
    (rSCACFIR, bit(25)) ? self_th_1_UERE;

    /** SCACFIR[26]
     *  Parity Error on Pib Target Register
     */
    (rSCACFIR, bit(26)) ? self_th_1_UERE;

    /** SCACFIR[27:31]
     *  Reserved
     */
    (rSCACFIR, bit(27|28|29|30|31)) ? defaultMaskedError;

    /** SCACFIR[32]
     *  State Machine / Ctrl Logic Error
     */
    (rSCACFIR, bit(32)) ? self_th_1;

    /** SCACFIR[33]
     *  Register access error
     */
    (rSCACFIR, bit(33)) ? level2_th_1;

    /** SCACFIR[34]
     *  PIB error initiating RESET cmd to I2CM
     */
    (rSCACFIR, bit(34)) ? defaultMaskedError;

    /** SCACFIR[35]
     *  Internal SCOM Error
     */
    (rSCACFIR, bit(35)) ? threshold_and_mask_self;

    /** SCACFIR[36]
     *  Internal SCOM Error
     */
    (rSCACFIR, bit(36)) ? threshold_and_mask_self;

};

################################################################################
# Centaur chip MCBISTFIR 0
################################################################################

rule rMCBISTFIR_0
{
  UNIT_CS:
    MCBISTFIR_0 & ~MCBISTFIR_0_MASK & ~MCBISTFIR_0_ACT0 & ~MCBISTFIR_0_ACT1;
  RECOVERABLE:
    MCBISTFIR_0 & ~MCBISTFIR_0_MASK & ~MCBISTFIR_0_ACT0 &  MCBISTFIR_0_ACT1;
};

group gMCBISTFIR_0
    filter singlebit,
           cs_root_cause(0,1)
{
    /** MCBISTFIR_0[0]
     *  SCOM Parity Errors
     */
    (rMCBISTFIR_0, bit(0)) ? mba0_th_1_UERE;

    /** MCBISTFIR_0[1]
     *  MBX parity errors
     */
    (rMCBISTFIR_0, bit(1)) ? mba0_th_1_UERE;

    /** MCBISTFIR_0[2]
     *  DRAM event 0 error
     */
    (rMCBISTFIR_0, bit(2)) ? defaultMaskedError;

    /** MCBISTFIR_0[3]
     *  DRAM event 1 error
     */
    (rMCBISTFIR_0, bit(3)) ? defaultMaskedError;

    /** MCBISTFIR_0[4:14]
     *  Reserved
     */
    (rMCBISTFIR_0, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError;

    /** MCBISTFIR_0[15]
     *  SCOM FIR error
     */
    (rMCBISTFIR_0, bit(15)) ? threshold_and_mask_mba0;

    /** MCBISTFIR_0[16]
     *  SCOM FIR error clone
     */
    (rMCBISTFIR_0, bit(16)) ? threshold_and_mask_mba0;

};

################################################################################
# Centaur chip MCBISTFIR 1
################################################################################

rule rMCBISTFIR_1
{
  UNIT_CS:
    MCBISTFIR_1 & ~MCBISTFIR_1_MASK & ~MCBISTFIR_1_ACT0 & ~MCBISTFIR_1_ACT1;
  RECOVERABLE:
    MCBISTFIR_1 & ~MCBISTFIR_1_MASK & ~MCBISTFIR_1_ACT0 &  MCBISTFIR_1_ACT1;
};

group gMCBISTFIR_1
    filter singlebit,
           cs_root_cause(0,1)
{
    /** MCBISTFIR_1[0]
     *  SCOM Parity Errors
     */
    (rMCBISTFIR_1, bit(0)) ? mba1_th_1_UERE;

    /** MCBISTFIR_1[1]
     *  MBX parity errors
     */
    (rMCBISTFIR_1, bit(1)) ? mba1_th_1_UERE;

    /** MCBISTFIR_1[2]
     *  DRAM event 0 error
     */
    (rMCBISTFIR_1, bit(2)) ? defaultMaskedError;

    /** MCBISTFIR_1[3]
     *  DRAM event 1 error
     */
    (rMCBISTFIR_1, bit(3)) ? defaultMaskedError;

    /** MCBISTFIR_1[4:14]
     *  Reserved
     */
    (rMCBISTFIR_1, bit(4|5|6|7|8|9|10|11|12|13|14)) ? defaultMaskedError;

    /** MCBISTFIR_1[15]
     *  SCOM FIR error
     */
    (rMCBISTFIR_1, bit(15)) ? threshold_and_mask_mba1;

    /** MCBISTFIR_1[16]
     *  SCOM FIR error clone
     */
    (rMCBISTFIR_1, bit(16)) ? threshold_and_mask_mba1;

};

################################################################################
# MEM Chiplet FIR
################################################################################

rule rMEM_CHIPLET_FIR
{
  UNIT_CS:
     MEM_CHIPLET_CS_FIR       & ~MEM_CHIPLET_FIR_MASK & `1fffffffffffffff`;
  RECOVERABLE:
    (MEM_CHIPLET_RE_FIR >> 2) & ~MEM_CHIPLET_FIR_MASK & `1fffffffffffffff`;
};

group gMEM_CHIPLET_FIR
    filter singlebit
{
    /** MEM_CHIPLET_FIR[3]
     *  Attention from MEM_LFIR
     */
    (rMEM_CHIPLET_FIR, bit(3)) ? analyzeMEM_LFIR;

    /** MEM_CHIPLET_FIR[5]
     *  Attention from MBACALFIR 0
     */
    (rMEM_CHIPLET_FIR, bit(5)) ? analyzeConnectedMBA0;

    /** MEM_CHIPLET_FIR[6]
     *  Attention from MBAFIR 0
     */
    (rMEM_CHIPLET_FIR, bit(6)) ? analyzeConnectedMBA0;

    /** MEM_CHIPLET_FIR[7]
     *  Attention from MBACALFIR 1
     */
    (rMEM_CHIPLET_FIR, bit(7)) ? analyzeConnectedMBA1;

    /** MEM_CHIPLET_FIR[8]
     *  Attention from MBAFIR 1
     */
    (rMEM_CHIPLET_FIR, bit(8)) ? analyzeConnectedMBA1;

    /** MEM_CHIPLET_FIR[9]
     *  Attention from MBADDRPHYFIR 0
     */
    (rMEM_CHIPLET_FIR, bit(9)) ? analyzeConnectedMBA0;

    /** MEM_CHIPLET_FIR[10]
     *  Attention from MBADDRPHYFIR 1
     */
    (rMEM_CHIPLET_FIR, bit(10)) ? analyzeConnectedMBA1;

    /** MEM_CHIPLET_FIR[12]
     *  Attention from MBASECUREFIR 0
     */
    (rMEM_CHIPLET_FIR, bit(12)) ? analyzeConnectedMBA0;

    /** MEM_CHIPLET_FIR[13]
     *  Attention from MBASECUREFIR 1
     */
    (rMEM_CHIPLET_FIR, bit(13)) ? analyzeConnectedMBA1;

};

################################################################################
# MEM Chiplet Special Attention FIR
################################################################################

rule rMEM_CHIPLET_SPA_FIR
{
  HOST_ATTN:
    MEM_CHIPLET_SPA_FIR & ~MEM_CHIPLET_SPA_FIR_MASK;
};

group gMEM_CHIPLET_SPA_FIR
    filter singlebit
{
    /** MEM_CHIPLET_SPA_FIR[0]
     *  Attention from MBASPA 0
     */
    (rMEM_CHIPLET_SPA_FIR, bit(0)) ? analyzeConnectedMBA0;

    /** MEM_CHIPLET_SPA_FIR[1]
     *  Attention from MBASPA 1
     */
    (rMEM_CHIPLET_SPA_FIR, bit(1)) ? analyzeConnectedMBA1;

};

################################################################################
# Centaur chip MEM_LFIR
################################################################################

rule rMEM_LFIR
{
  UNIT_CS:
    MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 & ~MEM_LFIR_ACT1;
  RECOVERABLE:
    MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 &  MEM_LFIR_ACT1;
};

group gMEM_LFIR
    filter singlebit,
           cs_root_cause
{
    /** MEM_LFIR[0]
     *  CFIR internal parity error
     */
    (rMEM_LFIR, bit(0)) ? threshold_and_mask_self;

    /** MEM_LFIR[1]
     *  GPIO (PCB error)
     */
    (rMEM_LFIR, bit(1)) ? defaultMaskedError;

    /** MEM_LFIR[2]
     *  CC (PCB error)
     */
    (rMEM_LFIR, bit(2)) ? defaultMaskedError;

    /** MEM_LFIR[3]
     *  CC (OPCG, parity, scan collision, ...)
     */
    (rMEM_LFIR, bit(3)) ? defaultMaskedError;

    /** MEM_LFIR[4]
     *  PSC (PCB error)
     */
    (rMEM_LFIR, bit(4)) ? defaultMaskedError;

    /** MEM_LFIR[5]
     *  PSC (parity error)
     */
    (rMEM_LFIR, bit(5)) ? defaultMaskedError;

    /** MEM_LFIR[6]
     *  Thermal (parity error)
     */
    (rMEM_LFIR, bit(6)) ? defaultMaskedError;

    /** MEM_LFIR[7]
     *  Thermal (PCB error)
     */
    (rMEM_LFIR, bit(7)) ? defaultMaskedError;

    /** MEM_LFIR[8]
     *  Thermal (critical trip error)
     */
    (rMEM_LFIR, bit(8)) ? defaultMaskedError;

    /** MEM_LFIR[9]
     *  Thermal (fatal trip error)
     */
    (rMEM_LFIR, bit(9)) ? defaultMaskedError;

    /** MEM_LFIR[10]
     *  Thermal (voltage trip error)
     */
    (rMEM_LFIR, bit(10)) ? defaultMaskedError;

    /** MEM_LFIR[11]
     *  MBA01 Trace Array ( error)
     */
    (rMEM_LFIR, bit(11)) ? defaultMaskedError;

    /** MEM_LFIR[12]
     *  MBA01 Trace Array ( error)
     */
    (rMEM_LFIR, bit(12)) ? defaultMaskedError;

    /** MEM_LFIR[13]
     *  MBA23 Trace Array ( error)
     */
    (rMEM_LFIR, bit(13)) ? defaultMaskedError;

    /** MEM_LFIR[14]
     *  MBA23 Trace Array ( error)
     */
    (rMEM_LFIR, bit(14)) ? defaultMaskedError;

    /** MEM_LFIR[15:39]
     *  Reserved
     */
    (rMEM_LFIR, bit(15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39)) ? defaultMaskedError;

    /** MEM_LFIR[40]
     *  malfunction alert (local xstop in another chiplet)
     */
    (rMEM_LFIR, bit(40)) ? defaultMaskedError;

};

 ##############################################################################
 #                                                                            #
 #    #                                  ###                                  #
 #   # #    ##  ##### ###  ###  #   #   #   # #     #    ###   ###  ###  ###  #
 #  #   #  #  #   #    #  #   # ##  #   #     #    # #  #     #     #   #     #
 # ####### #      #    #  #   # # # #   #     #   #####  ###   ###  ##   ###  #
 # #     # #  #   #    #  #   # #  ##   #   # #   #   #     #     # #       # #
 # #     #  ##    #   ###  ###  #   #    ###  ### #   #  ###   ###  ###  ###  #
 #                                                                            #
 ##############################################################################

# Include the actions defined for this target
.include "centaur_common_actions.rule";
.include "centaur_membuf_actions.rule";