From 90fc4d2acbf077a421219d82cfa9886c52ceaec5 Mon Sep 17 00:00:00 2001 From: Louis Stermole Date: Tue, 30 May 2017 13:06:59 -0500 Subject: Add PHY DP16 DRIFT_LIMITS regs and DD2_BLUE_WATERFALL_EXT field API Change-Id: Ia891488d7de965a99c8cf3c457fccba9603773ad Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41136 Tested-by: PPE CI Reviewed-by: JACOB L. HARVEY Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: ANDRE A. MARIN Reviewed-by: STEPHEN GLANCY Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41167 Reviewed-by: Daniel M. Crowell --- .../include/p9_mc_scom_addresses_fld_fixes.H | 6 + .../chips/p9/procedures/hwp/memory/lib/phy/dp16.C | 10 ++ .../chips/p9/procedures/hwp/memory/lib/phy/dp16.H | 183 +++++++++++++++++++++ 3 files changed, 199 insertions(+) (limited to 'src') diff --git a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H index 1a7dc1d70..794a20ff8 100644 --- a/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H +++ b/src/import/chips/p9/common/include/p9_mc_scom_addresses_fld_fixes.H @@ -147,6 +147,8 @@ static const uint64_t SH_FLD_4_BIT15_LEN = 99990097; static const uint64_t SH_FLD_01_DD2_PERBIT_RDVREF_DISABLE = 99990098; static const uint64_t SH_FLD_23_DD2_PERBIT_RDVREF_DISABLE = 99990099; static const uint64_t SH_FLD_4_DD2_PERBIT_RDVREF_DISABLE = 99990100; +static const uint64_t SH_FLD_01_DD2_BLUE_EXTEND_RANGE = 99990101; +static const uint64_t SH_FLD_01_DD2_BLUE_EXTEND_RANGE_LEN = 99990102; REG64_FLD( MCA_DDRPHY_DP16_SYSCLK_PR0_P0_0_01_ENABLE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , 0 ); @@ -583,4 +585,8 @@ REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4_4_BIT15 , 57 , SH_UNT_M REG64_FLD( MCA_DDRPHY_DP16_RD_VREF_DAC_7_P0_4_4_BIT15_LEN , 7 , SH_UNT_MCA , SH_ACS_SCOM_RW , SH_FLD_4_BIT15_LEN ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_BLUE_EXTEND_RANGE , 48 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DD2_BLUE_EXTEND_RANGE ); +REG64_FLD( MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_BLUE_EXTEND_RANGE_LEN , 2 , SH_UNT_MCA , SH_ACS_SCOM_RW , + SH_FLD_01_DD2_BLUE_EXTEND_RANGE_LEN ); #endif diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C index 441163229..4652ecde4 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.C @@ -322,6 +322,16 @@ const std::vector< uint64_t > dp16Traits::DD2_RD_VREF_CNTRL_REG }, }; +// Definition of the DP16 DRIFT_LIMITS registers +const std::vector< uint64_t > dp16Traits::DRIFT_LIMITS_REG = +{ + MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0, + MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_1, + MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_2, + MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_3, + MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_4, +}; + // Definition of the DP16 RD_VREF Calibration enable registers const std::vector< uint64_t > dp16Traits::RD_VREF_CAL_ENABLE_REG = { diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H index c54fa8e18..9f1c2f177 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/dp16.H @@ -49,6 +49,19 @@ namespace mss { +/// +/// @brief Enumeration of DD2_BLUE_EXTEND_RANGE settings in DP16_DRIFT_LIMITS reg +/// @note Each name denotes the RDCLK phase shift lower and upper bounds, with +/// setting '2' being invalid. +/// +enum blue_waterfall_range : uint64_t +{ + ZERO_TO_THREE = 0, + ONE_TO_FOUR = 1, + RESERVED = 2, + TWO_TO_FIVE = 3 +}; + /// /// @brief Given a mt/s, create a PHY 'standard' bit field for that freq. /// @param[in] i_freq the value from mss::freq for your target @@ -166,6 +179,7 @@ class dp16Traits static const std::vector< std::pair > CTLE_CNTRL_REG; static const std::vector< uint64_t > DD1_RD_VREF_CNTRL_REG; static const std::vector< uint64_t > DD2_RD_VREF_CNTRL_REG; + static const std::vector< uint64_t > DRIFT_LIMITS_REG; static const std::vector>> BIT_DISABLE_REG; @@ -254,6 +268,10 @@ class dp16Traits // Both blue and red waterfalls are the same number of bits WATERFALL_LEN = MCA_DDRPHY_DP16_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_01_RDCLK_SELECT0_LEN, + // These are only valid on Nimbus DD2 and later + DD2_WATERFALL_RNG = MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_BLUE_EXTEND_RANGE, + DD2_WATERFALL_RNG_LEN = MCA_DDRPHY_DP16_DRIFT_LIMITS_P0_0_01_DD2_BLUE_EXTEND_RANGE_LEN, + //////////////////////////////////////// // WR VREF register field information // //////////////////////////////////////// @@ -1146,6 +1164,120 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Read DRIFT_LIMITS +/// @tparam I DP16 instance +/// @tparam T fapi2 Target Type - derived +/// @tparam TT traits type defaults to dp16Traits +/// @param[in] i_target the fapi2 target of the port +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< uint64_t I, fapi2::TargetType T, typename TT = dp16Traits > +inline fapi2::ReturnCode read_drift_limits( const fapi2::Target& i_target, fapi2::buffer& o_data ) +{ + static_assert( I < TT::DP_COUNT, "dp16 instance out of range"); + + FAPI_TRY( mss::getScom(i_target, TT::DRIFT_LIMITS_REG[I], o_data) ); + FAPI_INF("drift_limits dp16<%d>: 0x%016lx", I, o_data); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Read DRIFT_LIMITS +/// @tparam T fapi2 Target Type - derived +/// @tparam TT traits type defaults to dp16Traits +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_dp the DP16 instance +/// @param[out] o_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = dp16Traits > +inline fapi2::ReturnCode read_drift_limits( const fapi2::Target& i_target, + const uint64_t i_dp, + fapi2::buffer& o_data ) +{ + switch (i_dp) + { + case(0): + return ( read_drift_limits<0>(i_target, o_data) ); + + case(1): + return ( read_drift_limits<1>(i_target, o_data) ); + + case(2): + return ( read_drift_limits<2>(i_target, o_data) ); + + case(3): + return ( read_drift_limits<3>(i_target, o_data) ); + + case(4): + return ( read_drift_limits<4>(i_target, o_data) ); + + default: + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } +} + +/// +/// @brief Write DRIFT_LIMITS +/// @tparam I DP16 instance +/// @tparam T fapi2 Target Type - derived +/// @tparam TT traits type defaults to dp16Traits +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< uint64_t I, fapi2::TargetType T, typename TT = dp16Traits > +inline fapi2::ReturnCode write_drift_limits( const fapi2::Target& i_target, const fapi2::buffer& i_data ) +{ + static_assert( I < TT::DP_COUNT, "dp16 instance out of range"); + + FAPI_INF("drift_limits dp16<%d>: 0x%016lx", I, i_data); + FAPI_TRY( mss::putScom(i_target, TT::DRIFT_LIMITS_REG[I], i_data) ); + +fapi_try_exit: + return fapi2::current_err; +} + +/// +/// @brief Write DRIFT_LIMITS +/// @tparam T fapi2 Target Type - derived +/// @tparam TT traits type defaults to dp16Traits +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_dp the DP16 instance +/// @param[in] i_data the value of the register +/// @return fapi2::ReturnCode FAPI2_RC_SUCCESS if ok +/// +template< fapi2::TargetType T, typename TT = dp16Traits > +inline fapi2::ReturnCode write_drift_limits( const fapi2::Target& i_target, + const uint64_t i_dp, + const fapi2::buffer& i_data ) +{ + switch (i_dp) + { + case(0): + return ( write_drift_limits<0>(i_target, i_data) ); + + case(1): + return ( write_drift_limits<1>(i_target, i_data) ); + + case(2): + return ( write_drift_limits<2>(i_target, i_data) ); + + case(3): + return ( write_drift_limits<3>(i_target, i_data) ); + + case(4): + return ( write_drift_limits<4>(i_target, i_data) ); + + default: + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } +} + //////////////////////////////////////// // all the WR VREF scom accessors // //////////////////////////////////////// @@ -1915,6 +2047,57 @@ inline void set_gate_delay( fapi2::buffer& io_data, const uint64_t i_g io_data.insertFromRight(i_gate_delay); } +/// +/// @brief Get the blue waterfall extended range setting (DD2 and later only) +/// @tparam T fapi2 Target Type - derived +/// @tparam TT traits type defaults to dp16Traits +/// @param[in] i_target the fapi2 target of the port +/// @param[in] i_data the value of the register +/// @param[out] o_value the enumerated value of the range +/// @note this will return the ZERO_TO_THREE enumeration for DD1 +/// +template< fapi2::TargetType T, typename TT = dp16Traits > +inline void get_blue_waterfall_range( const fapi2::Target& i_target, + const fapi2::buffer& i_data, + blue_waterfall_range& o_value ) +{ + if (mss::chip_ec_nimbus_lt_2_0(i_target)) + { + o_value = blue_waterfall_range::ZERO_TO_THREE; + FAPI_ERR("get_blue_waterfall_range called on DD1 part"); + return; + } + + uint64_t l_out = 0; + i_data.extractToRight(l_out); + FAPI_INF("get_blue_waterfall_range: 0x%01lx", l_out); + o_value = static_cast(l_out); +} + +/// +/// @brief Set the blue waterfall extended range setting (DD2 and later only) +/// @tparam T fapi2 Target Type - derived +/// @tparam TT traits type defaults to dp16Traits +/// @param[in] i_target the fapi2 target of the port +/// @param[in, out] io_data the value of the register +/// @param[in] i_value the enumerated value of the range +/// @note this will do nothing for a DD1 part +/// +template< fapi2::TargetType T, typename TT = dp16Traits > +inline void set_blue_waterfall_range( const fapi2::Target& i_target, + fapi2::buffer& io_data, + const blue_waterfall_range i_value ) +{ + if (mss::chip_ec_nimbus_lt_2_0(i_target)) + { + FAPI_ERR("set_blue_waterfall_range called on DD1 part"); + return; + } + + io_data.insertFromRight(i_value); + FAPI_INF("set_blue_waterfall_range: 0x%01lx", i_value); +} + } // close namespace dp16 } // close namespace mss -- cgit v1.2.3