From 5c187fcbf2bc91d5870b49153a4fdf53c91ce1d7 Mon Sep 17 00:00:00 2001 From: Dan Crowell Date: Sat, 16 Feb 2019 15:22:54 -0600 Subject: Handle partial-bad MCS logic correctly One of the rewritten PG rules was incorrect for modules that have a MCS marked bad, e.g. Sforza. Change-Id: I30672b51f81ba74b51ece6e878e462106c090350 CQ: SW457231 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/72010 Reviewed-by: Matt Derksen Tested-by: Jenkins Server Reviewed-by: Ilya Smirnov Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Matthew Raybuck Reviewed-by: William G. Hoffa --- src/include/usr/hwas/common/pgLogic.H | 14 +++++++++----- src/usr/hwas/common/pgLogic.C | 4 ++++ 2 files changed, 13 insertions(+), 5 deletions(-) (limited to 'src') diff --git a/src/include/usr/hwas/common/pgLogic.H b/src/include/usr/hwas/common/pgLogic.H index 8ecb1631c..cfe5d599f 100644 --- a/src/include/usr/hwas/common/pgLogic.H +++ b/src/include/usr/hwas/common/pgLogic.H @@ -163,6 +163,10 @@ namespace PARTIAL_GOOD extern const size_t MCS_R1_CU_MASK; // Rule 2 only applies to chip units 2 & 3 extern const size_t MCS_R2_CU_MASK; + // Rule 3 only applies to chip units 0 & 2 + extern const size_t MCS_R3_CU_MASK; + // Rule 4 only applies to chip units 1 & 3 + extern const size_t MCS_R4_CU_MASK; // NPU // PG/AG Masks @@ -611,7 +615,7 @@ namespace PARTIAL_GOOD MCS_R1_CU_MASK, NO_SPECIAL_RULE ), - // MCS Rule 1: For chip units 2 and 3. Check MCS23 + // MCS Rule 2: For chip units 2 and 3. Check MCS23 new PartialGoodRule ( {&PREDICATE_NIMBUS}, @@ -621,7 +625,7 @@ namespace PARTIAL_GOOD MCS_R2_CU_MASK, NO_SPECIAL_RULE ), - // MCS Rule 3: For chip units 0 and 1. Check bits in the + // MCS Rule 3: For chip units 0 and 2. Check bits in the // MCxx entry including specific IOM bit, but // not the other bits in the partial good // region. @@ -631,10 +635,10 @@ namespace PARTIAL_GOOD MCS_R3_PG_MASK, MCS_ALL_GOOD_MASK, USE_CHIPLET_ID, - MCS_R1_CU_MASK, + MCS_R3_CU_MASK, NO_SPECIAL_RULE ), - // MCS Rule 4: For chip units 2 and 3. Check bits in the + // MCS Rule 4: For chip units 1 and 3. Check bits in the // MCxx entry including specific IOM bit, but // not the other bits in the partial good // region. @@ -644,7 +648,7 @@ namespace PARTIAL_GOOD MCS_R4_PG_MASK, MCS_ALL_GOOD_MASK, USE_CHIPLET_ID, - MCS_R2_CU_MASK, + MCS_R4_CU_MASK, NO_SPECIAL_RULE ), }// End of PG Rules for MCS Target diff --git a/src/usr/hwas/common/pgLogic.C b/src/usr/hwas/common/pgLogic.C index 7c88e9786..307527fc3 100644 --- a/src/usr/hwas/common/pgLogic.C +++ b/src/usr/hwas/common/pgLogic.C @@ -169,6 +169,10 @@ namespace PARTIAL_GOOD const size_t MCS_R1_CU_MASK = 0x0003; // Rule 2 only applies to chip units 2 & 3 const size_t MCS_R2_CU_MASK = 0x000C; + // Rule 3 only applies to chip units 0 & 2 + const size_t MCS_R3_CU_MASK = 0x0005; + // Rule 4 only applies to chip units 1 & 3 + const size_t MCS_R4_CU_MASK = 0x000A; // NPU // PG/AG Masks -- cgit v1.2.3