From 0101df38954bc3db866c9aef7fba9cf116cf2306 Mon Sep 17 00:00:00 2001 From: Louis Stermole Date: Fri, 24 Aug 2018 14:15:08 -0500 Subject: Multiple fixes to enable p9c draminit_training_adv during IPL Increase poll limit for PDA operations on p9c to fix CCS hangs Reduce repetitive access to ATTR_CEN_VPD_ODT_WR in PDA code Reduce repetitive access to ATTR_CEN_VPD_ISDIMMTOC4DQ/S in generic_shmoo Reduce repetitive access to ATTR_BAD_DQ_BITMAP in generic_shmoo Change-Id: Ibe130c590bbb5b50a7c31fa0b0add4c891c4505a CQ:SW446241 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65190 Tested-by: HWSV CI Reviewed-by: STEPHEN GLANCY Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: ANDRE A. MARIN Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65292 Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes --- .../hwp/memory/p9c_mss_access_delay_reg.C | 29 ++++- .../hwp/memory/p9c_mss_access_delay_reg.H | 27 ++++- .../procedures/hwp/memory/p9c_mss_ddr4_pda.C | 40 ++++--- .../procedures/hwp/memory/p9c_mss_ddr4_pda.H | 5 +- .../memory/p9c_mss_draminit_training_advanced.C | 26 +++-- .../hwp/memory/p9c_mss_eff_config_shmoo.C | 3 +- .../procedures/hwp/memory/p9c_mss_generic_shmoo.C | 119 ++++++++++++++------- .../procedures/hwp/memory/p9c_mss_generic_shmoo.H | 2 + .../centaur/procedures/hwp/memory/p9c_mss_mcbist.H | 6 +- .../procedures/hwp/memory/p9c_mss_mcbist_common.C | 12 ++- 10 files changed, 195 insertions(+), 74 deletions(-) (limited to 'src') diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.C index 5fe9c8e72..7b636b68b 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.C @@ -1915,13 +1915,17 @@ extern "C" { ///@param[in] i_input_index_u8=0-79/0-71/0-8/0-19 ///@param[in] i_verbose-extra print statements ///@param[out] C4 bit=o_value + ///@param[in] i_isdm_c4_dq optional param to specify ATTR_CEN_VPD_ISDIMMTOC4DQ and skip attr access (default = nullptr) + ///@param[in] i_isdm_c4_dqs optional param to specify ATTR_CEN_VPD_ISDIMMTOC4DQS and skip attr access (default = nullptr) ///@return fapi2::returnCode fapi2::ReturnCode rosetta_map(const fapi2::Target& i_target_mba, const uint8_t i_port, const input_type i_input_type_e, const uint8_t i_input_index, const bool i_verbose, - uint8_t& o_value) //This function is used by some other procedures + uint8_t& o_value, + uint8_t i_isdm_c4_dq[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQ_ENTRIES], + uint8_t i_isdm_c4_dqs[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQS_ENTRIES]) { // Boundary check is done again uint8_t l_mbapos = 0; @@ -1951,8 +1955,27 @@ extern "C" { if(l_dimmtype != fapi2::ENUM_ATTR_CEN_EFF_CUSTOM_DIMM_YES) { - FAPI_TRY(isdimmdqs_workaround(i_target_centaur, l_isdm_c4_dqs)); - FAPI_TRY(isdimmdq_workaround(i_target_centaur, l_isdm_c4_dq)); + if (i_isdm_c4_dq == nullptr) + { + FAPI_TRY(isdimmdq_workaround(i_target_centaur, l_isdm_c4_dq)); + } + else + { + std::copy(&i_isdm_c4_dq[0][0], + &i_isdm_c4_dq[0][0] + (MAX_PORTS_PER_CEN * DIMM_TO_C4_DQ_ENTRIES), + &l_isdm_c4_dq[0][0]); + } + + if (i_isdm_c4_dqs == nullptr) + { + FAPI_TRY(isdimmdqs_workaround(i_target_centaur, l_isdm_c4_dqs)); + } + else + { + std::copy(&i_isdm_c4_dqs[0][0], + &i_isdm_c4_dqs[0][0] + (MAX_PORTS_PER_CEN * DIMM_TO_C4_DQS_ENTRIES), + &l_isdm_c4_dqs[0][0]); + } } diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.H index 2899a8de3..65375e42c 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.H +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_access_delay_reg.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -48,6 +48,7 @@ // Includes //------------------------------------------------------------------------------ #include +#include //---------------------------------------------------------------------- @@ -205,6 +206,24 @@ typedef fapi2::ReturnCode (*p9c_mss_access_delay_reg_FP_t)(const fapi2::Target& i_target, + uint8_t (&o_isdimm_dq)[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQ_ENTRIES]); + + /// + /// @brief Worksaround old VPD that does not have the isdimmdq attribute + /// @param[in] i_target - centaur target on which to operate + /// @param[out] o_isdimm_dqs - the attribute data + /// @return fapi2::returnCode + /// + fapi2::ReturnCode isdimmdqs_workaround(const fapi2::Target& i_target, + uint8_t (&o_isdimm_dqs)[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQS_ENTRIES]); + /// @brief Reads or Writes delay values /// @param[in] i_target_mba Reference to centaur.mba target /// @param[in] i_access_type_e Access type (READ or WRITE) @@ -309,13 +328,17 @@ extern "C" { /// @param[in] i_input_index Input index /// @param[in] i_verbose 1 = Verbose tracing /// @param[out] o_value Output C4 bit + /// @param[in] i_isdm_c4_dq optional param to specify ATTR_CEN_VPD_ISDIMMTOC4DQ and skip attr access (default = nullptr) + /// @param[in] i_isdm_c4_dqs optional param to specify ATTR_CEN_VPD_ISDIMMTOC4DQS and skip attr access (default = nullptr) /// @return ReturnCode fapi2::ReturnCode rosetta_map(const fapi2::Target& i_target_mba, const uint8_t i_port, const input_type i_input_type_e, uint8_t i_input_index, const bool i_verbose, - uint8_t& o_value); + uint8_t& o_value, + uint8_t i_isdm_c4_dq[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQ_ENTRIES] = nullptr, + uint8_t i_isdm_c4_dqs[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQS_ENTRIES] = nullptr); /// @brief Gets the rank pair /// @param[in] i_target_mba Reference to centaur.mba target diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.C index dc0ba80fd..1f7f86391 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.C @@ -69,9 +69,11 @@ extern "C" { /// @param[in] di DIMM /// @param[in] r Rank /// @param[in] p Port + /// @param[in] i_odt_wr nominal write ODT settings /// PDA_MRS_Storage::PDA_MRS_Storage(const uint8_t ad, const uint32_t an, const uint8_t dr, const uint8_t di, - const uint8_t r, const uint8_t p) + const uint8_t r, const uint8_t p, + const uint8_t (&i_odt_wr)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM]) { attribute_data = ad; attribute_name = an; @@ -81,6 +83,10 @@ extern "C" { port = p; MRS = 0xFF; pda_string[0] = '\0'; + + std::copy(&i_odt_wr[0][0][0], + &i_odt_wr[0][0][0] + (MAX_PORTS_PER_MBA * MAX_DIMM_PER_PORT * MAX_RANKS_PER_DIMM), + &odt_wr[0][0][0]); } /// @@ -625,6 +631,9 @@ extern "C" { dimm = temp.dimm ; rank = temp.rank ; port = temp.port ; + std::copy(&odt_wr[0][0][0], + &odt_wr[0][0][0] + (MAX_PORTS_PER_MBA * MAX_DIMM_PER_PORT * MAX_RANKS_PER_DIMM), + &temp.odt_wr[0][0][0]); } /// @@ -668,7 +677,8 @@ extern "C" { uint32_t l_port_number = 0; uint32_t dimm_number = i_dimm; uint32_t rank_number = i_rank; - const uint32_t NUM_POLL = 10; + // Increased polling parameters to avoid CCS hung errors in HB + const uint32_t NUM_POLL = 10000; const uint32_t WAIT_TIMER = 1500; uint64_t reg_address = 0; fapi2::buffer data_buffer; @@ -984,6 +994,7 @@ extern "C" { //Execute the CCS array FAPI_INF("Executing the CCS array\n"); + FAPI_INF("mss_ddr4_setup_pda: Number of polls: %d, wait timer: %d", NUM_POLL, WAIT_TIMER); FAPI_TRY(mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER)); io_ccs_inst_cnt = 0; @@ -1047,9 +1058,11 @@ extern "C" { uint8_t dram_stack[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {0}; uint8_t num_spare[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0}; uint8_t wr_vref[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0}; + uint8_t odt_wr[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0}; uint8_t dram_width = 0; uint8_t array[][2][19] = {{{0x18, 0x18, 0x1c, 0x1c, 0x18, 0x18, 0x1c, 0x1c, 0x18, 0x1c, 0x18, 0x18, 0x1c, 0x1c, 0x1c, 0x18, 0x1c, 0x18, 0x18}, {0x18, 0x1c, 0x20, 0x1c, 0x20, 0x1c, 0x20, 0x20, 0x1c, 0x1c, 0x20, 0x1c, 0x18, 0x1c, 0x1c, 0x1c, 0x1c, 0x18, 0x18}}, {{0x18, 0x1c, 0x1c, 0x1c, 0x20, 0x1c, 0x20, 0x18, 0x18, 0x18, 0x1c, 0x1c, 0x1c, 0x18, 0x18, 0x1c, 0x18, 0x18, 0x1c}, {0x18, 0x1c, 0x18, 0x1c, 0x20, 0x1c, 0x18, 0x1c, 0x20, 0x1c, 0x1c, 0x1c, 0x1c, 0x24, 0x1c, 0x1c, 0x1c, 0x1c, 0x1c}}}; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_STACK_TYPE, i_target, dram_stack)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_VPD_ODT_WR, i_target, odt_wr)); //get num master ranks per dimm for 3DS if(dram_stack[0][0] == fapi2::ENUM_ATTR_CEN_EFF_STACK_TYPE_STACK_3DS) @@ -1119,7 +1132,7 @@ extern "C" { } i_pda.push_back(PDA_MRS_Storage(array[port][dimm][dram], fapi2::ATTR_CEN_EFF_VREF_DQ_TRAIN_VALUE, dram, dimm, rank, - port)); + port, odt_wr)); FAPI_INF("PDA STRING: %d %s", i_pda.size() - 1, i_pda[i_pda.size() - 1].c_str()); }//for each dram }//for each rank @@ -1199,7 +1212,8 @@ extern "C" { } uint32_t io_ccs_inst_cnt = 0; - const uint32_t NUM_POLL = 10; + // Increased polling parameters to avoid CCS hung errors in HB + const uint32_t NUM_POLL = 10000; const uint32_t WAIT_TIMER = 1500; fapi2::buffer data_buffer_64; fapi2::variable_buffer address_16(16); @@ -1236,7 +1250,6 @@ extern "C" { uint8_t wl_launch_time = 0; uint8_t odt_hold_time = 0; uint8_t post_odt_nop_idle = 0; - uint8_t odt_wr[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0}; bool prev_dram_set = false; vector scom_storage; uint8_t prev_dram = 0; @@ -1276,7 +1289,6 @@ extern "C" { FAPI_TRY(rasn_1.clearBit(0, 1)); FAPI_TRY(casn_1.clearBit(0, 1)); FAPI_TRY(wen_1.clearBit(0, 1)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_VPD_ODT_WR, i_target, odt_wr)); //runs through each PDA command for(uint32_t i = 0; i < i_pda.size(); i++) @@ -1334,7 +1346,7 @@ extern "C" { FAPI_TRY(mss_disable_cid(i_target, csn_8, cke_4)); - FAPI_TRY(odt_4.insert(odt_wr[prev_port][prev_dimm][prev_rank], 0, 4, 0)); + FAPI_TRY(odt_4.insert(i_pda[i].odt_wr[prev_port][prev_dimm][prev_rank], 0, 4, 0)); // Send out to the CCS array FAPI_TRY(mss_ccs_inst_arry_0( i_target, io_ccs_inst_cnt, @@ -1417,7 +1429,7 @@ extern "C" { FAPI_TRY(mss_disable_cid(i_target, csn_8, cke_4)); - FAPI_TRY(odt_4.insert(odt_wr[prev_port][prev_dimm][prev_rank], 0, 4, 0)); + FAPI_TRY(odt_4.insert(i_pda[i].odt_wr[prev_port][prev_dimm][prev_rank], 0, 4, 0)); // Send out to the CCS array FAPI_TRY(mss_ccs_inst_arry_0( i_target, @@ -1513,6 +1525,7 @@ extern "C" { //Execute the CCS array FAPI_INF("Executing the CCS array\n"); + FAPI_INF("mss_ddr4_run_pda_by_dimm_rank: Number of polls: %d, wait timer: %d", NUM_POLL, WAIT_TIMER); FAPI_TRY(mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER)); io_ccs_inst_cnt = 0; @@ -1590,7 +1603,7 @@ extern "C" { FAPI_TRY(address_16_backup.insert(address_16, 0, 16, 0)); FAPI_TRY(bank_3_backup.clearBit(0, 3)); FAPI_TRY(bank_3_backup.insert(bank_3, 0, 3, 0)); - FAPI_TRY(odt_4.insert(odt_wr[prev_port][prev_dimm][prev_rank], 0, 4, 0)); + FAPI_TRY(odt_4.insert(i_pda[0].odt_wr[prev_port][prev_dimm][prev_rank], 0, 4, 0)); //loads the previous DRAM if (( address_mirror_map[prev_port][prev_dimm] & (0x08 >> prev_rank) ) && (is_sim == 0)) @@ -1778,6 +1791,7 @@ extern "C" { //Execute the CCS array FAPI_INF("Executing the CCS array\n"); + FAPI_INF("mss_ddr4_run_pda_by_dimm_rank: Number of polls: %d, wait timer: %d", NUM_POLL, WAIT_TIMER); FAPI_TRY(mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER)); //loops through and clears out the storage class @@ -1873,7 +1887,8 @@ extern "C" { uint32_t l_port_number = 0; uint32_t dimm_number = i_dimm; uint32_t rank_number = i_rank; - const uint32_t NUM_POLL = 10; + // Increased polling parameters to avoid CCS hung errors in HB + const uint32_t NUM_POLL = 10000; const uint32_t WAIT_TIMER = 1500; uint64_t reg_address = 0; fapi2::buffer data_buffer; @@ -1905,11 +1920,11 @@ extern "C" { fapi2::variable_buffer csn_8_odt(8); uint8_t dram_gen = 0; fapi2::variable_buffer mrs3(16); - uint8_t odt_wr[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0}; uint8_t dram_stack[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {0}; uint8_t dimm_type = 0; uint8_t is_sim = 0; uint8_t address_mirror_map[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT] = {0}; //address_mirror_map[port][dimm] + uint8_t odt_wr[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM] = {0}; uint8_t mpr_op = 0; // MPR Op uint8_t mpr_page = 0; // MPR Page Selection uint8_t geardown_mode = 0; // Gear Down Mode @@ -1933,11 +1948,11 @@ extern "C" { FAPI_TRY(csn_8_odt.clearBit(7, 1)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_GEN, i_target, dram_gen)); - FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_VPD_ODT_WR, i_target, odt_wr)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_STACK_TYPE, i_target, dram_stack)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DIMM_TYPE, i_target, dimm_type)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target(), is_sim)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_ADDRESS_MIRRORING, i_target, address_mirror_map)); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_VPD_ODT_WR, i_target, odt_wr)); // WORKAROUNDS FAPI_TRY(fapi2::getScom(i_target, CEN_MBA_CCS_MODEQ, data_buffer)); @@ -2209,6 +2224,7 @@ extern "C" { //Execute the CCS array FAPI_INF("Executing the CCS array\n"); + FAPI_INF("mss_ddr4_disable_pda: Number of polls: %d, wait timer: %d", NUM_POLL, WAIT_TIMER); FAPI_TRY(mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER)); //Disable CCS diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.H index cc884d770..5fa79a222 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.H +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_ddr4_pda.H @@ -38,6 +38,7 @@ #define _MSS_DDR4_PDA_H #include #include +#include using namespace std; extern "C" @@ -57,6 +58,7 @@ extern "C" uint8_t dram; uint8_t rank; uint8_t port; + uint8_t odt_wr[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM]; /// /// @brief PDA MRS storage constructor @@ -66,9 +68,10 @@ extern "C" /// @param[in] di DIMM position /// @param[in] r rank /// @param[in] p port + /// @param[in] i_odt_wr nominal write ODT settings /// PDA_MRS_Storage(const uint8_t ad, const uint32_t an, const uint8_t dr, const uint8_t di, const uint8_t r, - const uint8_t p); + const uint8_t p, const uint8_t (&i_odt_wr)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM]); /// /// @brief Destructor diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C index 8378e9749..f28da8afe 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_draminit_training_advanced.C @@ -888,10 +888,12 @@ fapi_try_exit: /// /// @brief set new wr vref values on a DRAM basis (PDA) /// @param[in] i_target_mba Centaur input MBA +/// @param[in] i_odt_wr nominal write ODT settings /// @param[in] i_pda_nibble_table table of vref values from training /// @return FAPI2_RC_SUCCESS iff successful /// fapi2::ReturnCode set_wr_vref_by_dram(const fapi2::Target& i_target_mba, + const uint8_t (&i_odt_wr)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM], const uint32_t ( &i_pda_nibble_table)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM][MAX_DRAMS_PER_RANK_X4][2]) { @@ -940,21 +942,21 @@ fapi2::ReturnCode set_wr_vref_by_dram(const fapi2::Target& i_target_mba, + const uint8_t (&i_odt_wr)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM], const uint8_t (&i_vref_values)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM][MAX_DRAMS_PER_RANK_X4], uint32_t (&io_pda_nibble_table)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM][MAX_DRAMS_PER_RANK_X4][2]) { @@ -1030,7 +1034,7 @@ fapi2::ReturnCode wr_vref_test_helper(const fapi2::Target& i_target_mba, + const uint8_t (&i_odt_wr)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM], uint32_t (&io_pda_nibble_table)[MAX_PORTS_PER_MBA][MAX_DIMM_PER_PORT][MAX_RANKS_PER_DIMM][MAX_DRAMS_PER_RANK_X4][2]) { constexpr uint8_t MAX_VREF = 50; @@ -1170,7 +1176,7 @@ fapi2::ReturnCode wr_vref_ternary_search(const fapi2::Target l_target_centaur; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_STACK_TYPE, i_target, eff_stack_type)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_DRAM_GEN, i_target, l_dram_gen)); @@ -151,6 +152,8 @@ extern "C" iv_MAX_RANKS[0] = num_ranks_per_dimm[0][0] + num_ranks_per_dimm[0][1]; iv_MAX_RANKS[1] = num_ranks_per_dimm[1][0] + num_ranks_per_dimm[1][1]; + l_target_centaur = i_target.getParent(); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CEN_EFF_SCHMOO_MODE, i_target, l_shmoo_param)); iv_shmoo_param = l_shmoo_param; FAPI_INF(" +++++ The iv_shmoo_param = %d ++++ ", iv_shmoo_param); @@ -158,11 +161,21 @@ extern "C" if ( l_attr_eff_dimm_type_u8 == fapi2::ENUM_ATTR_CEN_EFF_CUSTOM_DIMM_YES ) { iv_MAX_BYTES = 10; + std::fill(&iv_isdm_c4_dq[0][0], + &iv_isdm_c4_dq[0][0] + (MAX_PORTS_PER_CEN * DIMM_TO_C4_DQ_ENTRIES), + 0); + std::fill(&iv_isdm_c4_dqs[0][0], + &iv_isdm_c4_dqs[0][0] + (MAX_PORTS_PER_CEN * DIMM_TO_C4_DQS_ENTRIES), + 0); } else { iv_dmm_type = 1; iv_MAX_BYTES = 9; + + // Cache these attrs for when we do mcb_error_map + FAPI_TRY(isdimmdq_workaround(l_target_centaur, iv_isdm_c4_dq)); + FAPI_TRY(isdimmdqs_workaround(l_target_centaur, iv_isdm_c4_dqs)); } for(uint8_t l_rnk = 0; l_rnk < iv_MAX_RANKS[0]; l_rnk++) @@ -523,7 +536,7 @@ extern "C" FAPI_DBG("%s: checking error map ", mss::c_str(i_target)); FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, - iv_count_bad_dq), "Failed mcb_error_map"); + iv_count_bad_dq, iv_isdm_c4_dq, iv_isdm_c4_dqs), "Failed mcb_error_map"); for (uint8_t l_p = 0; l_p < MAX_PORT; l_p++) { @@ -533,6 +546,19 @@ extern "C" const uint8_t l_rank = iv_valid_rank[l_p][l_rnk]; const uint8_t l_dimm_rank = l_rank % MAX_RANKS_PER_DIMM; + if(l_rank > 3) + { + l_faulted_dimm = 1; + } + else + { + l_faulted_dimm = 0; + } + + // Get the bad DQ Bitmap for l_port, l_dimm, l_rank + FAPI_TRY(dimmGetBadDqBitmap(i_target, l_p, l_faulted_dimm, l_dimm_rank, l_dqBitmap), + "Error from dimmGetBadDqBitmap on %s.", mss::c_str(i_target)); + for (uint8_t l_byte = 0; l_byte < DIMM_DQ_RANK_BITMAP_SIZE; l_byte++) { //Nibble loop @@ -544,19 +570,6 @@ extern "C" l_faulted_rank = l_rank; l_faulted_port = l_p; - if(l_rank > 3) - { - l_faulted_dimm = 1; - } - else - { - l_faulted_dimm = 0; - } - - // Get the bad DQ Bitmap for l_port, l_dimm, l_rank - FAPI_TRY(dimmGetBadDqBitmap(i_target, l_p, l_faulted_dimm, l_dimm_rank, l_dqBitmap), - "Error from dimmGetBadDqBitmap on %s.", mss::c_str(i_target)); - if (l_dram_width == fapi2::ENUM_ATTR_EFF_DRAM_WIDTH_X8) { l_dqBitmap[l_byte] = 0xff; @@ -698,7 +711,8 @@ extern "C" l_max_byte = 9; } - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, iv_isdm_c4_dq, + iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); for (l_rnk = 0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++) @@ -799,7 +813,8 @@ extern "C" l_max_nibble = 18; } - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, iv_isdm_c4_dq, + iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); for (l_p = 0; l_p < MAX_PORT; l_p++) @@ -1035,7 +1050,7 @@ extern "C" { l_dq = 8 * l_byte + 4 * l_nibble + l_bit; FAPI_INF("Before access call"); - FAPI_TRY(mss_access_delay_reg_schmoo(i_target, l_access_type_e, l_p, i_rnk, l_input_type_e, l_dq, 1, val)); + FAPI_TRY(mss_access_delay_reg_schmoo(i_target, l_access_type_e, l_p, i_rnk, l_input_type_e, l_dq, 0, val)); SHMOO.MBA.P[l_p].S[i_rnk].K.nom_val[l_dq] = val; SHMOO.MBA.P[l_p].S[i_rnk].K.rb_regval[l_dq] = val; SHMOO.MBA.P[l_p].S[i_rnk].K.lb_regval[l_dq] = val; @@ -1186,12 +1201,13 @@ extern "C" SHMOO.MBA.P[l_p].S[rank].K.rb_regval[l_dq] = SHMOO.MBA.P[l_p].S[rank].K.nom_val[l_dq] + l_delay; - FAPI_TRY(mss_access_delay_reg_schmoo(i_target, l_access_type_e, l_p, rank, l_input_type_e, l_dq, 1, + FAPI_TRY(mss_access_delay_reg_schmoo(i_target, l_access_type_e, l_p, rank, l_input_type_e, l_dq, 0, SHMOO.MBA.P[l_p].S[rank].K.rb_regval[l_dq])); } - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq)); + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs)); if(l_p == 0) @@ -1253,7 +1269,7 @@ extern "C" for (l_n = 0; l_n < l_SCHMOO_NIBBLES; l_n++) { - FAPI_TRY(mss_access_delay_reg_schmoo(i_target, l_access_type_e, l_p, rank, l_input_type_e, l_dq, 1, + FAPI_TRY(mss_access_delay_reg_schmoo(i_target, l_access_type_e, l_p, rank, l_input_type_e, l_dq, 0, SHMOO.MBA.P[l_p].S[rank].K.nom_val[l_dq])); l_dq = l_dq + 4; } @@ -1288,7 +1304,8 @@ extern "C" SHMOO.MBA.P[l_p].S[rank].K.lb_regval[l_dq])); } - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq)); + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs)); if(l_p == 0) { @@ -1445,7 +1462,8 @@ extern "C" do { l_status = 0; - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq)); + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs)); for (l_rank = 0; l_rank < iv_MAX_RANKS[l_p]; l_rank++) @@ -1588,7 +1606,8 @@ extern "C" { l_status = 0; - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq)); + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs)); for (l_rank = 0; l_rank < iv_MAX_RANKS[l_p]; l_rank++) { @@ -1760,7 +1779,8 @@ extern "C" FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: ecb_error_map failed!!"); if(iv_dmm_type == 1) @@ -1918,7 +1938,8 @@ extern "C" FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); } // end bound == right @@ -2049,7 +2070,8 @@ extern "C" } FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); } @@ -2092,7 +2114,8 @@ extern "C" FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); if(iv_dmm_type == 1) @@ -2213,7 +2236,8 @@ extern "C" } //end of bit FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); } @@ -2318,7 +2342,8 @@ extern "C" FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); } //end of Left @@ -2362,7 +2387,8 @@ extern "C" FAPI_INF("\nWRT_DQS --- > CDIMM X8 - Scenario = %d", scenario); FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); if(iv_dmm_type == 1) @@ -2529,7 +2555,8 @@ extern "C" FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); } @@ -2674,7 +2701,8 @@ extern "C" FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); } //end of bound Left @@ -2718,7 +2746,8 @@ extern "C" FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); if(iv_dmm_type == 1) @@ -2887,7 +2916,8 @@ extern "C" FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); } @@ -3034,7 +3064,8 @@ extern "C" FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq), + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs), "generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); } //end of LEFT @@ -3260,7 +3291,8 @@ extern "C" const auto l_target_centaur = i_target.getParent(); FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, - iv_count_bad_dq), "generic_shmoo::print report: mcb_error_map failed!!"); + iv_count_bad_dq, iv_isdm_c4_dq, iv_isdm_c4_dqs), + "generic_shmoo::print report: mcb_error_map failed!!"); if (iv_dmm_type == 1) { @@ -3996,7 +4028,8 @@ extern "C" do { l_status = 0; - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq)); + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs)); for (l_rank = 0; l_rank < iv_MAX_RANKS[l_p]; l_rank++) { @@ -4103,6 +4136,8 @@ extern "C" } // end for dq } // end for rank + FAPI_DBG("%s knob_update_bin_composite: Running RIGHT, shmoo number %d of a possible 8", + mss::c_str(i_target), count_cycle); FAPI_TRY(do_mcbist_reset(i_target), "generic_shmoo::find_bound do_mcbist_reset failed"); FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); @@ -4144,7 +4179,8 @@ extern "C" { l_status = 0; - FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq)); + FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, iv_count_bad_dq, + iv_isdm_c4_dq, iv_isdm_c4_dqs)); for (l_rank = 0; l_rank < iv_MAX_RANKS[l_p]; l_rank++) { @@ -4252,6 +4288,9 @@ extern "C" } } + FAPI_DBG("%s knob_update_bin_composite: Running LEFT, shmoo number %d of a possible 8", + mss::c_str(i_target), count_cycle); + FAPI_TRY(do_mcbist_reset(i_target), "generic_shmoo::find_bound do_mcbist_reset failed"); FAPI_TRY(do_mcbist_test(i_target), "generic_shmoo::find_bound do_mcbist_test failed"); FAPI_TRY(check_error_map(i_target, l_p, pass), "generic_shmoo::find_bound do_mcbist_test failed"); @@ -4648,7 +4687,7 @@ extern "C" uint8_t l_CDarray0[DIMM_TO_C4_DQ_ENTRIES] = { 0 }; uint8_t l_CDarray1[DIMM_TO_C4_DQ_ENTRIES] = { 0 }; FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, - iv_count_bad_dq), "Failed mcb_error_map"); + iv_count_bad_dq, iv_isdm_c4_dq, iv_isdm_c4_dqs), "Failed mcb_error_map"); } for(l_p = 0; l_p < MAX_PORT; l_p++) @@ -4691,7 +4730,7 @@ extern "C" uint8_t l_CDarray0[DIMM_TO_C4_DQ_ENTRIES] = { 0 }; uint8_t l_CDarray1[DIMM_TO_C4_DQ_ENTRIES] = { 0 }; FAPI_TRY(mcb_error_map(i_target, iv_mcbist_error_map, l_CDarray0, l_CDarray1, - iv_count_bad_dq), "Failed mcb_error_map"); + iv_count_bad_dq, iv_isdm_c4_dq, iv_isdm_c4_dqs), "Failed mcb_error_map"); } for(l_p = 0; l_p < MAX_PORT; l_p++) diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.H index 6fa66f498..8c3b1da12 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.H +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_generic_shmoo.H @@ -93,6 +93,8 @@ class generic_shmoo uint16_t iv_dqs_rb_regval[MAX_PORT][MAX_RANK][MAX_DQ]; uint16_t iv_dqs_lb_regval[MAX_PORT][MAX_RANK][MAX_DQ]; uint16_t iv_dqs_nom_val[MAX_PORT][MAX_RANK][MAX_DQ]; + uint8_t iv_isdm_c4_dq[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQ_ENTRIES]; + uint8_t iv_isdm_c4_dqs[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQS_ENTRIES]; public: diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.H b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.H index 7b54fc0e1..6d18fd148 100755 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.H +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist.H @@ -305,13 +305,17 @@ extern "C" /// @param[in] i_CDarray0[80] /// @param[in] i_CDarray1[80] /// @param[in] count_bad_dq[2] + /// @param[in] i_isdm_c4_dq optional param to specify ATTR_CEN_VPD_ISDIMMTOC4DQ and skip attr access (default = nullptr) + /// @param[in] i_isdm_c4_dqs optional param to specify ATTR_CEN_VPD_ISDIMMTOC4DQS and skip attr access (default = nullptr) /// @return FAPI2_RC_SUCCESS iff successful /// fapi2::ReturnCode mcb_error_map(const fapi2::Target& i_target_mba, uint8_t o_error_map[MAX_PORTS_PER_MBA][MAX_RANKS_PER_PORT][MAX_BYTES_PER_RANK][MAX_NIBBLES_PER_BYTE], uint8_t i_CDarray0[DIMM_DQ_SPD_DATA_SIZE], uint8_t i_CDarray1[DIMM_DQ_SPD_DATA_SIZE], - uint8_t count_bad_dq[2]); + uint8_t count_bad_dq[2], + uint8_t i_isdm_c4_dq[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQ_ENTRIES] = nullptr, + uint8_t i_isdm_c4_dqs[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQS_ENTRIES] = nullptr); /// /// @brief Based on parameters passed we write data into Register being passed diff --git a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C index 44fb2f411..085833e98 100644 --- a/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C +++ b/src/import/chips/centaur/procedures/hwp/memory/p9c_mss_mcbist_common.C @@ -838,13 +838,17 @@ extern "C" /// @param[in] i_CDarray0[80] /// @param[in] i_CDarray1[80] /// @param[in] count_bad_dq[2] + /// @param[in] i_isdm_c4_dq optional param to specify ATTR_CEN_VPD_ISDIMMTOC4DQ and skip attr access (default = nullptr) + /// @param[in] i_isdm_c4_dqs optional param to specify ATTR_CEN_VPD_ISDIMMTOC4DQS and skip attr access (default = nullptr) /// @return FAPI2_RC_SUCCESS iff successful /// fapi2::ReturnCode mcb_error_map(const fapi2::Target& i_target_mba, uint8_t o_error_map[MAX_PORTS_PER_MBA][MAX_RANKS_PER_PORT][MAX_BYTES_PER_RANK][MAX_NIBBLES_PER_BYTE], uint8_t i_CDarray0[DIMM_DQ_SPD_DATA_SIZE], uint8_t i_CDarray1[DIMM_DQ_SPD_DATA_SIZE], - uint8_t count_bad_dq[2]) + uint8_t count_bad_dq[2], + uint8_t i_isdm_c4_dq[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQ_ENTRIES], + uint8_t i_isdm_c4_dqs[MAX_PORTS_PER_CEN][DIMM_TO_C4_DQS_ENTRIES]) { fapi2::buffer l_mcbem1ab; fapi2::buffer l_mcbem2ab; @@ -1155,14 +1159,14 @@ extern "C" //port 0 for (l_i = 0; l_i < ISDIMM_MAX_DQ_72; l_i++) { - FAPI_TRY(rosetta_map(i_target_mba, 0, l_input_type_e, l_i, 0, o_val)); + FAPI_TRY(rosetta_map(i_target_mba, 0, l_input_type_e, l_i, 0, o_val, i_isdm_c4_dq, i_isdm_c4_dqs)); cdimm_dq0[o_val] = l_i; } //port 1 for (l_i = 0; l_i < ISDIMM_MAX_DQ_72; l_i++) { - FAPI_TRY(rosetta_map(i_target_mba, 1, l_input_type_e, l_i, 0, o_val)); + FAPI_TRY(rosetta_map(i_target_mba, 1, l_input_type_e, l_i, 0, o_val, i_isdm_c4_dq, i_isdm_c4_dqs)); cdimm_dq1[o_val] = l_i; } @@ -1493,7 +1497,7 @@ extern "C" FAPI_TRY(rosetta_map(i_target_mba, l_port, l_input_type_e, i_input_index_u8, - 0, o_val)); + 0, o_val, i_isdm_c4_dq, i_isdm_c4_dqs)); i_byte1 = o_val / BITS_PER_BYTE; i_nibble1 = o_val % BITS_PER_BYTE; -- cgit v1.2.1