From 2cdeb532a7d25232ae2f498aa122635374ae6fb6 Mon Sep 17 00:00:00 2001 From: Dean Sanner Date: Tue, 18 Mar 2014 10:59:30 -0500 Subject: Move PCI mem addresses below 46 bits for NVIDIA CUDA Adapter Change-Id: Ia162ac38be1f0aa92ef1e6168c94a4de26634fd4 CQ: SW251480 Backport: release-fips810 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9978 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III --- src/include/usr/hwpf/hwp/procMemConsts.H | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/include/usr/hwpf') diff --git a/src/include/usr/hwpf/hwp/procMemConsts.H b/src/include/usr/hwpf/hwp/procMemConsts.H index 9a1282b04..9aab51ef0 100644 --- a/src/include/usr/hwpf/hwp/procMemConsts.H +++ b/src/include/usr/hwpf/hwp/procMemConsts.H @@ -58,6 +58,14 @@ const uint64_t PCIE_BAR0_SIZE = 0x0000001000000000ULL; const uint64_t PCIE_BAR1_SIZE = 0x0000000080000000ULL; const uint64_t PCIE_BAR2_SIZE = 0x0000000000001000ULL; +// 4 PHB per chip, 4chips per node, max 4 nodes +const uint64_t PCIE_BAR0_OFFSET_MASK = ((PCIE_BAR0_SIZE*4*4*4)-1); +const uint64_t PCIE_BAR1_OFFSET_MASK = ((PCIE_BAR1_SIZE*4*4*4)-1); +const uint64_t SAPPHIRE_PCIE_BAR0_BASE = 0x00003B0000000000; +const uint64_t SAPPHIRE_PCIE_BAR1_BASE = 0x00003FE000000000; + + + // PHB Register Address Space - line 90 Overall Map // size is 1_MB const uint64_t PHB_REGS_SIZE = 0x0000000000100000ULL; -- cgit v1.2.3