From 5ef559321401f8b1d71de95f707f595a57ed522f Mon Sep 17 00:00:00 2001 From: Christian Geddes Date: Mon, 13 Nov 2017 12:47:28 -0600 Subject: Move bbuild up to b1109a_1746.910 and remove workaround Hostboot has fallen behind in updating the backing build for Fips. This commit handles that and removes workarounds that we had in workarounds.postsimsetup CMVC-Prereq: 1038850 Change-Id: I959e12352ca6866d184896a0c661bbbf6d95570b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49605 Tested-by: Jenkins Server Reviewed-by: Nicholas E. Bofferding Reviewed-by: Michael Baiocchi Reviewed-by: Stephen M. Cprek Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Marshall J. Wilks Reviewed-by: Christian R. Geddes --- src/build/citest/etc/bbuild | 2 +- src/build/citest/etc/workarounds.postsimsetup | 7 ++----- 2 files changed, 3 insertions(+), 6 deletions(-) (limited to 'src/build/citest') diff --git a/src/build/citest/etc/bbuild b/src/build/citest/etc/bbuild index cdf8125eb..a3df5c642 100644 --- a/src/build/citest/etc/bbuild +++ b/src/build/citest/etc/bbuild @@ -1 +1 @@ -/esw/fips910/Builds/b1019a_1742.910 +/esw/fips910/Builds/b1109a_1746.910 diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index ec3ec2ce1..d25a6baed 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -33,8 +33,5 @@ #cp $BACKING_BUILD/src/simu/data/cec-chip/base_cec_chip_file $sb/simu/data/cec-chip #patch -p0 $sb/simu/data/cec-chip/base_cec_chip_file $PROJECT_ROOT/src/build/citest/etc/patches/my_patch_File - - -echo "Switch to simulating P9N DD2.0 by default" -sbex -t 1034628 - +#Simulation stalls while running Hostboot standalone simics +sbex -t 1038850 \ No newline at end of file -- cgit v1.2.1