From fcfd722a6abb01f780c10de0f5d801a9c4210ebd Mon Sep 17 00:00:00 2001 From: Dean Sanner Date: Tue, 5 Dec 2017 15:10:45 -0600 Subject: Support HB running in SMF Support SMF for P9N/P9C. Lots of minor tweaks to make this work, but the biggest is to run userspace in problem state This is needed because for SMF Hostboot will need to run in S=1, HV=0,PR=1 (and kernel in S=1, HV=1, PR=0) This commit makes P9 HB userpsace run in HV=0 PR=1 and kernel in HV=1, PR=0. Change-Id: Ia4771df5e8858c6b7ae54b0746e62b283afb4bc4 RTC: 197243 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/50530 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Dean Sanner Reviewed-by: Nicholas E. Bofferding Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell --- src/bootloader/bl_start.S | 34 +++++++++++++++++++++++++++++++--- src/bootloader/bootloader.C | 12 +++++++++++- 2 files changed, 42 insertions(+), 4 deletions(-) (limited to 'src/bootloader') diff --git a/src/bootloader/bl_start.S b/src/bootloader/bl_start.S index 0780575d6..ebb0fd0a7 100644 --- a/src/bootloader/bl_start.S +++ b/src/bootloader/bl_start.S @@ -64,8 +64,11 @@ .set HBBL_vsx_unavail, 0xF40 .set HBBL_fac_unavail, 0xF60 .set HBBL_hype_fac_unavail, 0xF80 -.set HBBL_softpatch, 0x1500 -.set HBBL_debug, 0x1600 +.set HBBL_softpatch, 0x1500 +.set HBBL_debug, 0x1600 +.set P9N_URMOR_HACK, 0x7C797BA6 +.set MSR_SMF_MASK, 0x0000000000400000 +.set MSR_SMF_AND_MASK, 0x40 ;// used to isolate the SMF bit with andis .section .text.bootloaderasm @@ -349,6 +352,9 @@ STD_INTERRUPT(debug, HBBL_debug) ;// ;// @param[in] r3 - Hostboot HRMOR ;// @param[in] r4 - Hostboot Entry + ;// @param[in] r5 - Apply P9C/P9N hack. Due to a bug on p9 chips, URMOR val + ;// comes with operation code attached to it. We need to + ;// subtract that op code to get the actual URMOR value. ;// .global enterHBB enterHBB: @@ -370,9 +376,31 @@ enterHBB: blr switchToHBB: - ;// Update HRMOR + ;// Update HRMOR and URMOR + ;// for secure systems URMOR must == HRMOR for HBB + ;// Since SBE always keeps HRMOR == URMOR, HBBL uses + ;// HRMOR for backward compatibility, but it must + ;// adjust URMOR when jumping to HBB mtspr HRMOR, r3 + ;// Check to see if SMF bit is off... if so skip + ;// URMOR set as don't have permissions + mfmsr r6 + andis. r6, r6, MSR_SMF_AND_MASK ;// Check if 41 (SMF) is on + beq skip_urmor ;// if result of AND = zero then CR[EQ] bit set + + cmpwi cr0, r5, 0x1 ;// Hack requested == 0x1 + bne cr0, skip_urmor_hack + + ;// Due to bug in P9N, P9C early levels need to subtract op-code + lis r10, P9N_URMOR_HACK@h + ori r10, r10, P9N_URMOR_HACK@l + sub r3,r3,r10 + +skip_urmor_hack: + mtspr URMOR, r3 +skip_urmor: + ;// Clear out SLBs, ERATs, etc. isync slbia diff --git a/src/bootloader/bootloader.C b/src/bootloader/bootloader.C index a2cf3fe84..2b9217c98 100644 --- a/src/bootloader/bootloader.C +++ b/src/bootloader/bootloader.C @@ -35,6 +35,8 @@ #include #include #include +#include + #include @@ -530,8 +532,16 @@ namespace Bootloader{ writeScratchReg(MMIO_SCRATCH_HOSTBOOT_ACTIVE, hostboot_string); + //Determine if P9N or P9C and apply URMOR hack + uint64_t l_urmor_hack_required = 0x0; + PVR_t l_pvr(getPVR()); + if((l_pvr.chipFamily == PVR_t::P9_ALL)) + { + l_urmor_hack_required = 1; + } + // Start executing HBB - enterHBB(HBB_HRMOR, HBB_RUNNING_OFFSET); + enterHBB(HBB_HRMOR, HBB_RUNNING_OFFSET, l_urmor_hack_required); } else { -- cgit v1.2.3