From f8a7a5a564ec6a552b784eba7a0dd3615f65268c Mon Sep 17 00:00:00 2001 From: Louis Stermole Date: Wed, 6 Feb 2019 09:36:23 -0500 Subject: Move MSS MRW attributes to generic XML Change-Id: I13c4b88523b4ebda84193dd711f0fbb0772672f7 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71436 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: HWSV CI Tested-by: Hostboot CI Reviewed-by: ANDRE A. MARIN Reviewed-by: STEPHEN GLANCY Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71465 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes --- .../hwp/memory/lib/mss_attribute_accessors.H | 5428 ++++++++++---------- .../xml/attribute_info/memory_mrw_attributes.xml | 594 --- .../generic_memory_mrw_attributes.xml | 532 ++ src/usr/targeting/common/genHwsvMrwXml.pl | 2 - .../common/xmltohb/hb_customized_attrs.xml | 5 - 5 files changed, 3246 insertions(+), 3315 deletions(-) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H index f47729e87..c482989dd 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H +++ b/src/import/chips/p9/procedures/hwp/memory/lib/mss_attribute_accessors.H @@ -14142,500 +14142,478 @@ fapi_try_exit: /// -/// @brief ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT getter -/// @param[out] uint16_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint64_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Machine Readable Workbook safe mode throttle value for numerator -/// cfg_nm_n_per_port Set to below optimum value/ rate. On a per port (MCA) basis -/// Also used for emergency mode throttle MBA_FARB4Q_EMERGENCY_N Used to thermally -/// protect the system in all supported environmental conditions when OCC is not -/// functional Consumer: thermal_init, -/// initfile +/// @note Each MCA value is a 64-bit vector, where each byte represents an unsupported +/// rank configuration. Each nibble in the byte represents the total count of ranks +/// (master and slave) on each DIMM. The left-most nibble represents slot 0 and the +/// right represents +/// 1. /// -inline fapi2::ReturnCode mrw_safemode_mem_throttled_n_commands_per_port(uint16_t& o_value) +inline fapi2::ReturnCode mrw_unsupported_rank_config(const fapi2::Target& i_target, + uint64_t& o_value) { + uint64_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT, - fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG, i_target.getParent(), + l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT getter -/// @param[out] uint64_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A) +/// @brief ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint64_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Machine Readable Workbook Thermal Memory Power Limit Used to calculate throttles -/// to be at or under the power limit Per DIMM basis KEY (0-19): In order DIMM_SIZE -/// = bits 0-3, DIMM_GEN = 4-5, DIMM_TYPE = 6-7, DIMM_WIDTH = 8-10, DIMM_DENSITY = -/// 11-13, DIMM_STACK_TYPE = 14-15, DRAM_MFGID = 16-18, DIMMS_PER_PORT = 19-20, Bits -/// 21-32: Not used VALUE (bits 32-63) in cW: VMEM+VPP thermal power limit per DIMM -/// = 32-63 Consumers: eff_config_thermal and -/// bulk_pwr_throttles +/// @note Each MCA value is a 64-bit vector, where each byte represents an unsupported +/// rank configuration. Each nibble in the byte represents the total count of ranks +/// (master and slave) on each DIMM. The left-most nibble represents slot 0 and the +/// right represents +/// 1. /// -inline fapi2::ReturnCode mrw_thermal_memory_power_limit(uint64_t* o_array) +inline fapi2::ReturnCode mrw_unsupported_rank_config(const fapi2::Target& i_target, + uint64_t& o_value) { - uint64_t l_value[10]; + uint64_t l_value[2]; + auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT, fapi2::Target(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG, l_mca.getParent(), l_value) ); - memcpy(o_array, &l_value, 80); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_PWR_INTERCEPT getter +/// @brief ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG getter +/// @param[in] const ref to the fapi2::Target /// @param[out] uint64_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A) +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Machine Readable Workbook Power Curve Intercept for DIMM Used to get the VDDR -/// and VDDR+VPP power curve for each DIMM Decoded and used to set -/// ATTR_MSS_TOTAL_PWR_INTERCEPT Key Value pair KEY (0-19): In order DIMM_SIZE = -/// bits 0-3, DIMM_GEN = 4-5, DIMM_TYPE = 6-7, DIMM_WIDTH = 8-10, DIMM_DENSITY = -/// 11-13, DIMM_STACK_TYPE = 14-15, DRAM_MFGID = 16-18, DIMMS_PER_PORT = 19-20, Bits -/// 21-32: Not used VALUE (bits 32-63) in cW: VMEM power curve = 32-47 VMEM+VPP -/// power curve = 48-63 Consumers: -/// eff_config_thermal +/// @note Each MCA value is a 64-bit vector, where each byte represents an unsupported +/// rank configuration. Each nibble in the byte represents the total count of ranks +/// (master and slave) on each DIMM. The left-most nibble represents slot 0 and the +/// right represents +/// 1. /// -inline fapi2::ReturnCode mrw_pwr_intercept(uint64_t* o_array) +inline fapi2::ReturnCode mrw_unsupported_rank_config(const fapi2::Target& i_target, + uint64_t* o_array) { - uint64_t l_value[100]; + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_PWR_INTERCEPT, fapi2::Target(), l_value) ); - memcpy(o_array, &l_value, 800); + uint64_t l_value[2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG, i_target, l_value) ); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_PWR_INTERCEPT: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } + /// -/// @brief ATTR_MSS_MRW_PWR_SLOPE getter -/// @param[out] uint64_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A) +/// @brief ATTR_MSS_VPD_MR_0_VERSION_LAYOUT getter +/// @param[in] const ref to the TARGET_TYPE_MCS +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (NODIM A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Machine Readable Workbook Power Curve Slope for DIMM Used to get the VDDR and -/// VDDR+VPP power curve for each DIMM Decoded and used to set -/// ATTR_MSS_TOTAL_PWR_INTERCEPT Key Value pair KEY (0-19): In order DIMM_SIZE = -/// bits 0-3, DIMM_GEN = 4-5, DIMM_TYPE = 6-7, DIMM_WIDTH = 8-10, DIMM_DENSITY = -/// 11-13, DIMM_STACK_TYPE = 14-15, DRAM_MFGID = 16-18, DIMMS_PER_PORT = 19-20, Bits -/// 21-32: Not used VALUE (bits 32-63) in cW: VMEM power curve = 32-47 VMEM+VPP -/// power curve = 48-63 Consumers: -/// eff_config_thermal +/// @note MR Keyword Layout Version Number. Increases when attributes are added, removed, +/// or redefined. Does not +/// reset. /// -inline fapi2::ReturnCode mrw_pwr_slope(uint64_t* o_array) +inline fapi2::ReturnCode vpd_mr_0_version_layout(const fapi2::Target& i_target, + uint8_t& o_value) { - uint64_t l_value[100]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_PWR_SLOPE, fapi2::Target(), l_value) ); - memcpy(o_array, &l_value, 800); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_0_VERSION_LAYOUT, i_target, o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_PWR_SLOPE: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_0_VERSION_LAYOUT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_REFRESH_RATE_REQUEST getter +/// @brief ATTR_MSS_VPD_MR_1_VERSION_DATA getter +/// @param[in] const ref to the TARGET_TYPE_MCS /// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @note Generated by gen_accessors.pl generateParameters (NODIM A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Machine Readable Workbook Refresh Rate Desired refresh interval used in refresh -/// register 0, MBAREF0Q_CFG_REFRESH_INTERVAL 7.8 us (SINGLE) 3.9 us (DOUBLE) 7.02 -/// us (SINGLE_10_PERCENT_FASTER) 3.51 us -/// (DOUBLE_10_PERCENT_FASTER) +/// @note MR Keyword Data Version Number. Increases when data changes with the above +/// layout version. Resets when layout version number +/// increments. /// -inline fapi2::ReturnCode mrw_refresh_rate_request(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_1_version_data(const fapi2::Target& i_target, uint8_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_REFRESH_RATE_REQUEST, fapi2::Target(), - o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_1_VERSION_DATA, i_target, o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_REFRESH_RATE_REQUEST: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_1_VERSION_DATA: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_2_SIGNATURE_HASH getter +/// @param[in] const ref to the TARGET_TYPE_MCS +/// @param[out] uint32_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (NODIM A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Machine Readable Workbook DIMM power curve percent uplift for this system at max -/// utilization. Value should be 0 for -/// ISDIMMs +/// @note Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of +/// data. /// -inline fapi2::ReturnCode mrw_dimm_power_curve_percent_uplift(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_2_signature_hash(const fapi2::Target& i_target, + uint32_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT, fapi2::Target(), - o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_2_SIGNATURE_HASH, i_target, o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_2_SIGNATURE_HASH: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_DPHY_GPO getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Machine Readable Workbook DIMM power curve percent uplift for this system at -/// idle utilization. Value should be 0 for -/// ISDIMMs +/// @note Global phy offset in number of +/// clocks /// -inline fapi2::ReturnCode mrw_dimm_power_curve_percent_uplift_idle(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_dphy_gpo(const fapi2::Target& i_target, uint8_t& o_value) { + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE, - fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_GPO, i_target.getParent(), l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_GPO: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS getter -/// @param[out] uint32_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_DPHY_GPO getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Machine Readable Workbook for the number of M DRAM clocks. One approach to -/// curbing DRAM power usage is by throttling traffic through a programmable N -/// commands over M -/// window. +/// @note Global phy offset in number of +/// clocks /// -inline fapi2::ReturnCode mrw_mem_m_dram_clocks(uint32_t& o_value) +inline fapi2::ReturnCode vpd_mr_dphy_gpo(const fapi2::Target& i_target, uint8_t& o_value) { + uint8_t l_value[2]; + auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS, fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_GPO, l_mca.getParent(), l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_GPO: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL getter -/// @param[out] uint32_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_DPHY_GPO getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Machine Readable Workbook value for maximum dram data bus utilization in centi -/// percent (c%). Used to determine memory throttle values. Max databus utilization -/// on a per port basis Default to -/// 90% +/// @note Global phy offset in number of +/// clocks /// -inline fapi2::ReturnCode mrw_max_dram_databus_util(uint32_t& o_value) +inline fapi2::ReturnCode vpd_mr_dphy_gpo(const fapi2::Target& i_target, uint8_t* o_array) { + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL, fapi2::Target(), - o_value) ); + uint8_t l_value[2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_GPO, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_GPO: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_DPHY_RLO getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory power control settings for IDLE powersave mode Used by OCC when entering -/// idle power-save -/// mode +/// @note Read latency offset in number of +/// clocks /// -inline fapi2::ReturnCode mrw_idle_power_control_requested(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_dphy_rlo(const fapi2::Target& i_target, uint8_t& o_value) { + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED, fapi2::Target(), - o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_RLO, i_target.getParent(), l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_RLO: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4 getter -/// @param[out] uint32_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_DPHY_RLO getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Machine Readable Workbook VMEM regulator power limit per DIMM assuming a full -/// configuration. Units in cW Consumed in -/// mss_eff_config_thermal +/// @note Read latency offset in number of +/// clocks /// -inline fapi2::ReturnCode mrw_vmem_regulator_power_limit_per_dimm_ddr4(uint32_t& o_value) +inline fapi2::ReturnCode vpd_mr_dphy_rlo(const fapi2::Target& i_target, uint8_t& o_value) { + uint8_t l_value[2]; + auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4, - fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_RLO, l_mca.getParent(), l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_RLO: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_DPHY_RLO getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Machine Readable Workbook value for the maximum possible number of dimms that -/// can be installed under any of the VMEM regulators. Consumed in -/// eff_config_thermal to calculate -/// mem_watt_target +/// @note Read latency offset in number of +/// clocks /// -inline fapi2::ReturnCode mrw_max_number_dimms_possible_per_vmem_regulator(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_dphy_rlo(const fapi2::Target& i_target, uint8_t* o_array) { + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR, - fapi2::Target(), o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR: 0x%lx (system target)", - uint64_t(fapi2::current_err)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MSS_MRW_FINE_REFRESH_MODE getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Fine refresh mode. Sets DDR4 MRS3. ZZ uses normal mode. From JEDEC DDR4 Spec -/// 1716.78C from 07-2016 Page 47 Table -/// 4.9.1 -/// -inline fapi2::ReturnCode mrw_fine_refresh_mode(uint8_t& o_value) -{ + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_FINE_REFRESH_MODE, fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_RLO, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_FINE_REFRESH_MODE: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_RLO: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_TEMP_REFRESH_RANGE getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_DPHY_WLO getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Temperature refresh range. Sets DDR4 MRS4. Should be defaulted to extended -/// range. NORMAL for running at 85 degrees C or less, EXTENDED for 95 or less -/// degrees C Used for calculating periodic refresh intervals JEDEC DDR4 spec -/// 1716.78C from 07-2016 page 46 -/// 4.8.1 +/// @note Write latency offset in number of +/// clocks /// -inline fapi2::ReturnCode mrw_temp_refresh_range(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_dphy_wlo(const fapi2::Target& i_target, uint8_t& o_value) { + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_TEMP_REFRESH_RANGE, fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, i_target.getParent(), l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_TEMP_REFRESH_RANGE: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_WLO: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_DPHY_WLO getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note For resetting the phy delay values at the beginning of calling -/// mss_draminit_training. YES means the vaules will be -/// reset. +/// @note Write latency offset in number of +/// clocks /// -inline fapi2::ReturnCode mrw_reset_delay_before_cal(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_dphy_wlo(const fapi2::Target& i_target, uint8_t& o_value) { + uint8_t l_value[2]; + auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL, fapi2::Target(), - o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, l_mca.getParent(), l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_WLO: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS getter -/// @param[out] uint16_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_DPHY_WLO getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Describes the settings for periodic calibration for all ports: Reading left to -/// right. (DEFAULT: 0xD90C -> Byte 0(11011001), Byte 1(00001100)) For each bit: OFF -/// = 0, ON = 1. Setting to 0 indicates to disable periodic memcal. Byte 0: 0: ZCAL -/// 1: SYSCK_ALIGN 2: RDCENTERING 3: RDLCK_ALIGN 4: DQS_ALIGN 5: RDCLK_UPDATE 6: -/// PER_DUTYCYCLE 7: PERCAL_PWR_DIS Byte 1: 0: PERCAL_REPEAT 1: PERCAL_REPEAT 2: -/// PERCAL_REPEAT 3: SINGLE_BIT_MPR 4: MBA_CFG_0 5: MBA_CFG_1 6: SPARE 7: -/// SPARE +/// @note Write latency offset in number of +/// clocks /// -inline fapi2::ReturnCode mrw_periodic_memcal_mode_options(uint16_t& o_value) +inline fapi2::ReturnCode vpd_mr_dphy_wlo(const fapi2::Target& i_target, uint8_t* o_array) { + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS, fapi2::Target(), - o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS: 0x%lx (system target)", - uint64_t(fapi2::current_err)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS getter -/// @param[out] uint16_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Describes the settings for periodic ZQ calibration for all ports: Reading left -/// to right. For each bit: OFF = 0, ON = 1. Setting to 0 indicates to disable -/// periodic zqcal. Byte 0: 0: ZQCAL All others reserved for future -/// use -/// -inline fapi2::ReturnCode mrw_periodic_zqcal_mode_options(uint16_t& o_value) -{ + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS, fapi2::Target(), - o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_WLO: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_DRAM_2N_MODE getter +/// @brief ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET getter +/// @param[in] const ref to the TARGET_TYPE_MCS /// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @note Generated by gen_accessors.pl generateParameters (NODIM A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Allows user to manually turn on and off 2N Mode. AUTO indicates to use Signal -/// Integrity generated setting (from -/// VPD). +/// @note Default value for 2N Mode from Signal Integrity. 0x01 = 1N Mode , 0x02 = 2N +/// Mode /// -inline fapi2::ReturnCode mrw_dram_2n_mode(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_2n_mode_autoset(const fapi2::Target& i_target, + uint8_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DRAM_2N_MODE, fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET, i_target, o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_DRAM_2N_MODE: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00 getter /// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint64_t +/// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Each MCA value is a 64-bit vector, where each byte represents an unsupported -/// rank configuration. Each nibble in the byte represents the total count of ranks -/// (master and slave) on each DIMM. The left-most nibble represents slot 0 and the -/// right represents -/// 1. +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode mrw_unsupported_rank_config(const fapi2::Target& i_target, - uint64_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target& i_target, + uint8_t& o_value) { - uint64_t l_value[2]; + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00 getter /// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint64_t +/// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Each MCA value is a 64-bit vector, where each byte represents an unsupported -/// rank configuration. Each nibble in the byte represents the total count of ranks -/// (master and slave) on each DIMM. The left-most nibble represents slot 0 and the -/// right represents -/// 1. +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode mrw_unsupported_rank_config(const fapi2::Target& i_target, - uint64_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target& i_target, + uint8_t& o_value) { - uint64_t l_value[2]; + uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00 getter /// @param[in] const ref to the fapi2::Target -/// @param[out] uint64_t* memory to store the value +/// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Each MCA value is a 64-bit vector, where each byte represents an unsupported -/// rank configuration. Each nibble in the byte represents the total count of ranks -/// (master and slave) on each DIMM. The left-most nibble represents slot 0 and the -/// right represents -/// 1. +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode mrw_unsupported_rank_config(const fapi2::Target& i_target, - uint64_t* o_array) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target& i_target, + uint8_t* o_array) { if (o_array == nullptr) { @@ -14643,273 +14621,335 @@ inline fapi2::ReturnCode mrw_unsupported_rank_config(const fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Enables DRAM Write -/// CRC +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode mrw_dram_write_crc(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target& i_target, + uint8_t& o_value) { + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DRAM_WRITE_CRC, fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01, i_target.getParent(), + l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_DRAM_WRITE_CRC: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_TEMP_REFRESH_MODE getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01 getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Used in MR4 A3 Temperature refresh mode Should be defaulted to -/// disable +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode mrw_temp_refresh_mode(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target& i_target, + uint8_t& o_value) { + uint8_t l_value[2]; + auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_TEMP_REFRESH_MODE, fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01, l_mca.getParent(), + l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_TEMP_REFRESH_MODE: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_FORCE_BCMODE_OFF getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01 getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note An override switch to shut off broadcast mode Enum values: YES: broadcast mode -/// is forced off NO: broadcast mode uses the default -/// value +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode mrw_force_bcmode_off(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target& i_target, + uint8_t* o_array) { + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_FORCE_BCMODE_OFF, fapi2::Target(), o_value) ); + uint8_t l_value[2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_FORCE_BCMODE_OFF: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_NVDIMM_PLUG_RULES getter -/// @param[out] uint64_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02 getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note A bitmap containing the plug rules for NVDIMM. 1 if a DIMM supports an NVDIMM -/// being plugged in, 0 if it does not DIMM slot 0 is the left most bit The index to -/// the bitmap is the position of the DIMM target As such, a bitmap of 0b10010000, -/// would allow NVDIMM plugged into DIMM0 and DIMM3 Note: this attribute is a 64 bit -/// number to account for 16 DIMM per processor if there is ever a 4 processor -/// system +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode mrw_nvdimm_plug_rules(uint64_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target& i_target, + uint8_t& o_value) { + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_NVDIMM_PLUG_RULES, fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02, i_target.getParent(), + l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_NVDIMM_PLUG_RULES: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02 getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Switch that allows unsupported raw card references by providing a default raw -/// card -/// setting. +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode mrw_allow_unsupported_rcw(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target& i_target, + uint8_t& o_value) { + uint8_t l_value[2]; + auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW, fapi2::Target(), - o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02, l_mca.getParent(), + l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_SUPPORTED_DRAM_WIDTH getter -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02 getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Bitmap of DRAM widths supported by a system. A 1 indicates that the system -/// supports a density. Enums below represent the the bit location in the attribute -/// for a given DRAM width. Default value is 0xC -> both x4/x8 -/// supported +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode mrw_supported_dram_width(uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target& i_target, + uint8_t* o_array) { + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_SUPPORTED_DRAM_WIDTH, fapi2::Target(), - o_value) ); + uint8_t l_value[2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_SUPPORTED_DRAM_WIDTH: 0x%lx (system target)", - uint64_t(fapi2::current_err)); + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } - /// -/// @brief ATTR_MSS_VPD_MR_0_VERSION_LAYOUT getter -/// @param[in] const ref to the TARGET_TYPE_MCS -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (NODIM A) +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03 getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note MR Keyword Layout Version Number. Increases when attributes are added, removed, -/// or redefined. Does not -/// reset. +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode vpd_mr_0_version_layout(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target& i_target, uint8_t& o_value) { + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_0_VERSION_LAYOUT, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03, i_target.getParent(), + l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_0_VERSION_LAYOUT: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_1_VERSION_DATA getter -/// @param[in] const ref to the TARGET_TYPE_MCS -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (NODIM A) +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03 getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note MR Keyword Data Version Number. Increases when data changes with the above -/// layout version. Resets when layout version number -/// increments. +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode vpd_mr_1_version_data(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target& i_target, + uint8_t& o_value) { + uint8_t l_value[2]; + auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_1_VERSION_DATA, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03, l_mca.getParent(), + l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_1_VERSION_DATA: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_2_SIGNATURE_HASH getter -/// @param[in] const ref to the TARGET_TYPE_MCS -/// @param[out] uint32_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (NODIM A) +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03 getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of -/// data. +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode vpd_mr_2_signature_hash(const fapi2::Target& i_target, - uint32_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target& i_target, + uint8_t* o_array) { - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_2_SIGNATURE_HASH, i_target, o_value) ); - return fapi2::current_err; - + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + uint8_t l_value[2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03, i_target, l_value) ); + memcpy(o_array, &l_value, 2); + return fapi2::current_err; + fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_2_SIGNATURE_HASH: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_DPHY_GPO getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Global phy offset in number of -/// clocks +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode vpd_mr_dphy_gpo(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target& i_target, + uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_GPO, i_target.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04, i_target.getParent(), + l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_GPO: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_DPHY_GPO getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Global phy offset in number of -/// clocks +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode vpd_mr_dphy_gpo(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target& i_target, + uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_GPO, l_mca.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04, l_mca.getParent(), + l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_GPO: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_DPHY_GPO getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Global phy offset in number of -/// clocks +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode vpd_mr_dphy_gpo(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target& i_target, + uint8_t* o_array) { if (o_array == nullptr) { @@ -14919,73 +14959,81 @@ inline fapi2::ReturnCode vpd_mr_dphy_gpo(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Read latency offset in number of -/// clocks +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode vpd_mr_dphy_rlo(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target& i_target, + uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_RLO, i_target.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05, i_target.getParent(), + l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_RLO: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_DPHY_RLO getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Read latency offset in number of -/// clocks +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode vpd_mr_dphy_rlo(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target& i_target, + uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_RLO, l_mca.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05, l_mca.getParent(), + l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_RLO: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_DPHY_RLO getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Read latency offset in number of -/// clocks +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode vpd_mr_dphy_rlo(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target& i_target, + uint8_t* o_array) { if (o_array == nullptr) { @@ -14995,73 +15043,81 @@ inline fapi2::ReturnCode vpd_mr_dphy_rlo(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Write latency offset in number of -/// clocks +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode vpd_mr_dphy_wlo(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target& i_target, + uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, i_target.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06, i_target.getParent(), + l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_WLO: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_DPHY_WLO getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Write latency offset in number of -/// clocks +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode vpd_mr_dphy_wlo(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target& i_target, + uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_DPHY_WLO, l_mca.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06, l_mca.getParent(), + l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_DPHY_WLO: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_DPHY_WLO getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Write latency offset in number of -/// clocks +/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// one cycle of +/// clock. /// -inline fapi2::ReturnCode vpd_mr_dphy_wlo(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target& i_target, + uint8_t* o_array) { if (o_array == nullptr) { @@ -15071,40 +15127,18 @@ inline fapi2::ReturnCode vpd_mr_dphy_wlo(const fapi2::Target& i_target, - uint8_t& o_value) -{ - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET, i_target, o_value) ); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_2N_MODE_AUTOSET: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -15113,24 +15147,24 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -15139,25 +15173,25 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A00 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -15166,7 +15200,7 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -15177,18 +15211,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a00(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -15197,24 +15231,24 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -15223,25 +15257,25 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A01 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -15250,7 +15284,7 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -15261,18 +15295,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a01(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -15281,24 +15315,24 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -15307,25 +15341,25 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A02 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -15334,7 +15368,7 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -15345,18 +15379,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a02(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -15365,24 +15399,24 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -15391,25 +15425,25 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A03 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -15418,7 +15452,7 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -15429,18 +15463,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a03(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -15449,24 +15483,24 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -15475,25 +15509,25 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A04 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -15502,7 +15536,7 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -15513,18 +15547,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a04(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -15533,24 +15567,24 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -15559,25 +15593,25 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A05 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -15586,7 +15620,7 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -15597,18 +15631,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a05(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -15617,24 +15651,24 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -15643,25 +15677,25 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A06 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -15670,7 +15704,7 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -15681,18 +15715,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a06(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -15701,24 +15735,24 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -15727,25 +15761,25 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A07 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -15754,7 +15788,7 @@ fapi_try_exit: /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -15765,80 +15799,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a07(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// @note Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// @note Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A08 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// @note Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -15849,80 +15883,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a08(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// @note Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// @note Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A09 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of +/// @note Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of /// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -15933,80 +15967,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a09(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Bank Group of BG# in ticks. Ticks are 1/128 of one +/// cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Bank Group of BG# in ticks. Ticks are 1/128 of one +/// cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A10 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Bank Group of BG# in ticks. Ticks are 1/128 of one +/// cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -16017,80 +16051,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a10(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Bank Group of BA# in ticks. Ticks are 1/128 of one +/// cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Bank Group of BA# in ticks. Ticks are 1/128 of one +/// cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A11 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Bank Group of BA# in ticks. Ticks are 1/128 of one +/// cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -16101,80 +16135,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a11(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. +/// Ticks are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. +/// Ticks are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A12 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. +/// Ticks are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -16185,80 +16219,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a12(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. +/// Ticks are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. +/// Ticks are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A13 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. +/// Ticks are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -16269,80 +16303,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a13(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. +/// Ticks are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. +/// Ticks are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_A17 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of command/address of A## in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. +/// Ticks are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -16353,80 +16387,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_a17(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one +/// cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one +/// cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one +/// cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -16437,80 +16471,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba0(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1, i_target.getParent(), - l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15, + i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1, l_mca.getParent(), - l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15, + l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BA1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Bank Address of BA# in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -16521,80 +16555,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_ba1(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Bank Group of BG# in ticks. Ticks are 1/128 of one -/// cycle of +/// @note Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0, i_target.getParent(), - l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16, + i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Bank Group of BG# in ticks. Ticks are 1/128 of one -/// cycle of +/// @note Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0, l_mca.getParent(), - l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16, + l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Bank Group of BG# in ticks. Ticks are 1/128 of one -/// cycle of +/// @note Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -16605,80 +16639,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg0(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Bank Group of BA# in ticks. Ticks are 1/128 of one -/// cycle of +/// @note Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1, i_target.getParent(), - l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14, + i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Bank Group of BA# in ticks. Ticks are 1/128 of one -/// cycle of +/// @note Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_BG1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Bank Group of BA# in ticks. Ticks are 1/128 of one -/// cycle of +/// @note Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -16689,80 +16723,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_bg1(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. -/// Ticks are 1/128 of one cycle of +/// @note Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 +/// of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. -/// Ticks are 1/128 of one cycle of +/// @note Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 +/// of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. -/// Ticks are 1/128 of one cycle of +/// @note Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 +/// of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -16773,80 +16807,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c0(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. -/// Ticks are 1/128 of one cycle of +/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. -/// Ticks are 1/128 of one cycle of +/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. -/// Ticks are 1/128 of one cycle of +/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -16857,80 +16891,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c1(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. -/// Ticks are 1/128 of one cycle of +/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. -/// Ticks are 1/128 of one cycle of +/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_ADDR_C2 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip ID of C# in ticks. Only used in TSV Dimms. -/// Ticks are 1/128 of one cycle of +/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -16941,80 +16975,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_addr_c2(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one -/// cycle of +/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one -/// cycle of +/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ACTN getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Activate for ACTN in ticks. Ticks are 1/128 of one -/// cycle of +/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -17025,80 +17059,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_actn(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are +/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are /// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15, - i_target.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, i_target.getParent(), + l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are +/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are /// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15, - l_mca.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, l_mca.getParent(), + l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Column Access Strobe for CASN in ticks. Ticks are +/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are /// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -17109,80 +17143,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_casn_a15(const fapi2::Targ uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15, i_target, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, i_target, l_value) ); memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_CASN_A15: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks +/// are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16, - i_target.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, i_target.getParent(), + l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks +/// are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16, - l_mca.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, l_mca.getParent(), + l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Row Access Strobe for RASN in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks +/// are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -17193,80 +17227,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_rasn_a16(const fapi2::Targ uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16, i_target, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, i_target, l_value) ); memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_RASN_A16: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks +/// are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14, - i_target.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, i_target.getParent(), + l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks +/// are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Write Enable for WEN in ticks. Ticks are 1/128 of -/// one cycle of +/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks +/// are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -17277,80 +17311,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_addr_wen_a14(const fapi2::Targe uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14, i_target, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, i_target, l_value) ); memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_ADDR_WEN_A14: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 -/// of one cycle of +/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 -/// of one cycle of +/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CMD_PAR getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of the Parity Input for PAR in ticks. Ticks are 1/128 -/// of one cycle of +/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are +/// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -17361,18 +17395,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cmd_par(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -17381,24 +17415,24 @@ fapi_try_exit: /// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -17407,25 +17441,25 @@ fapi_try_exit: /// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -17434,7 +17468,7 @@ fapi_try_exit: /// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -17445,80 +17479,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke0(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are +/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are /// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are +/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are /// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CKE1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are +/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are /// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -17529,18 +17563,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_cke1(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -17549,24 +17583,24 @@ fapi_try_exit: /// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -17575,25 +17609,25 @@ fapi_try_exit: /// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -17602,7 +17636,7 @@ fapi_try_exit: /// 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -17613,80 +17647,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn0(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks +/// are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks +/// are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_CSN1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks +/// are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -17697,18 +17731,18 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_csn1(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) @@ -17717,24 +17751,24 @@ fapi_try_exit: /// are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) @@ -17743,25 +17777,25 @@ fapi_try_exit: /// are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) @@ -17770,7 +17804,7 @@ fapi_try_exit: /// are 1/128 of one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -17781,80 +17815,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt0(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks -/// are 1/128 of one cycle of +/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks -/// are 1/128 of one cycle of +/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D0_ODT1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks -/// are 1/128 of one cycle of +/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -17865,80 +17899,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d0_odt1(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -17949,80 +17983,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke0(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CKE1 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock Enable for Dimm#_CKE# in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -18033,80 +18067,80 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_cke1(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0, l_mca.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN0 getter +/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are -/// 1/128 of one cycle of +/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of +/// one cycle of /// clock. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -18117,165 +18151,168 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn0(const fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_VPD_MR_TSYS_ADR getter +/// @param[in] const ref to the TARGET_TYPE_MCS +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (NODIM A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are -/// 1/128 of one cycle of -/// clock. +/// @note ADR WRClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of +/// clock. Phase Rotator Static Offset value used to determine the Phase of the +/// WrClk with respect to SysClk. For zero delay simulations, or simulations where +/// the delay of the SysClk tree and the WrClk tree are equal, Set this field to +/// 60h /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_tsys_adr(const fapi2::Target& i_target, uint8_t& o_value) { - uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, i_target.getParent(), - l_value) ); - o_value = l_value[mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_TSYS_ADR, i_target, o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_TSYS_ADR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @brief ATTR_MSS_VPD_MR_TSYS_DATA getter +/// @param[in] const ref to the TARGET_TYPE_MCS +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (NODIM A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are -/// 1/128 of one cycle of -/// clock. +/// @note DP16 WrClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of +/// clock. Phase Rotator Static Offset value used to determine the Phase of the +/// WrClk with respect to SysClk. For zero delay simulations, or simulations where +/// the delay of the SysClk tree and the WrClk tree are equal, Set this field to +/// 60h /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mr_tsys_data(const fapi2::Target& i_target, uint8_t& o_value) { - uint8_t l_value[2]; - auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, l_mca.getParent(), - l_value) ); - o_value = l_value[mss::index(l_mca)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_TSYS_DATA, i_target, o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_TSYS_DATA: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } + /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1 getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @brief ATTR_MSS_VPD_MT_0_VERSION_LAYOUT getter +/// @param[in] const ref to the TARGET_TYPE_MCS +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (NODIM A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Chip Select for Dimm#_CSN# in ticks. Ticks are -/// 1/128 of one cycle of -/// clock. +/// @note MT Keyword Layout Version Number. Increases when attributes are added, removed, +/// or redefined. Does not +/// reset. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_csn1(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_0_version_layout(const fapi2::Target& i_target, + uint8_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - uint8_t l_value[2]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_0_VERSION_LAYOUT, i_target, o_value) ); + return fapi2::current_err; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1, i_target, l_value) ); - memcpy(o_array, &l_value, 2); +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_0_VERSION_LAYOUT: 0x%lx (target: %s)", + uint64_t(fapi2::current_err), mss::c_str(i_target)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_VPD_MT_1_VERSION_DATA getter +/// @param[in] const ref to the TARGET_TYPE_MCS +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (NODIM A) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note MT Keyword Data Version Number. Increases when data changes with the above +/// layout version. Resets when layout version number +/// increments. +/// +inline fapi2::ReturnCode vpd_mt_1_version_data(const fapi2::Target& i_target, uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_1_VERSION_DATA, i_target, o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_CSN1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_1_VERSION_DATA: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_VPD_MT_2_SIGNATURE_HASH getter +/// @param[in] const ref to the TARGET_TYPE_MCS +/// @param[out] uint32_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (NODIM A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks -/// are 1/128 of one cycle of -/// clock. +/// @note Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of +/// data. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_2_signature_hash(const fapi2::Target& i_target, + uint32_t& o_value) { - uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, i_target.getParent(), - l_value) ); - o_value = l_value[mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_2_SIGNATURE_HASH, i_target, o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_2_SIGNATURE_HASH: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 getter +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @note Generated by gen_accessors.pl generateParameters (F) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks -/// are 1/128 of one cycle of -/// clock. +/// @note Register Clock Driver, Input Bus Termination for Command/Address in tens of +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_ca(const fapi2::Target& i_target, uint8_t& o_value) { - uint8_t l_value[2]; + uint8_t l_value[2][2]; auto l_mca = i_target.getParent(); + auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, l_mca.getParent(), - l_value) ); - o_value = l_value[mss::index(l_mca)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA, l_mcs, l_value) ); + o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0 getter -/// @param[in] const ref to the fapi2::Target +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA getter +/// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @note Generated by gen_accessors.pl generateParameters (G) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks -/// are 1/128 of one cycle of -/// clock. +/// @note Register Clock Driver, Input Bus Termination for Command/Address in tens of +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_ca(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -18283,82 +18320,84 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt0(const fapi2::Target(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0, i_target, l_value) ); - memcpy(o_array, &l_value, 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT0: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (H) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks -/// are 1/128 of one cycle of -/// clock. +/// @note Register Clock Driver, Input Bus Termination for Command/Address in tens of +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_ca(const fapi2::Target& i_target, uint8_t* o_array) { - uint8_t l_value[2]; + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, i_target.getParent(), - l_value) ); - o_value = l_value[mss::index(i_target)]; + uint8_t l_value[2][2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA, i_target, l_value) ); + memcpy(o_array, &l_value, 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 getter +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @note Generated by gen_accessors.pl generateParameters (F) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks -/// are 1/128 of one cycle of -/// clock. +/// @note Register Clock Driver, Input Bus Termination for Clock Enable in tens of +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cke(const fapi2::Target& i_target, uint8_t& o_value) { - uint8_t l_value[2]; + uint8_t l_value[2][2]; auto l_mca = i_target.getParent(); + auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, l_mca.getParent(), - l_value) ); - o_value = l_value[mss::index(l_mca)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE, l_mcs, l_value) ); + o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1 getter -/// @param[in] const ref to the fapi2::Target +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE getter +/// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @note Generated by gen_accessors.pl generateParameters (G) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of On Die Termination for Dimm#_ODT# in ticks. Ticks -/// are 1/128 of one cycle of -/// clock. +/// @note Register Clock Driver, Input Bus Termination for Clock Enable in tens of +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cke(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -18367,83 +18406,85 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_cntl_d1_odt1(const fapi2::Target(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1, i_target, l_value) ); - memcpy(o_array, &l_value, 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_CNTL_D1_ODT1: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (H) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of -/// one cycle of -/// clock. +/// @note Register Clock Driver, Input Bus Termination for Clock Enable in tens of +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cke(const fapi2::Target& i_target, + uint8_t* o_array) { - uint8_t l_value[2]; + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target.getParent(), - l_value) ); - o_value = l_value[mss::index(i_target)]; + uint8_t l_value[2][2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE, i_target, l_value) ); + memcpy(o_array, &l_value, 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @note Generated by gen_accessors.pl generateParameters (F) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of -/// one cycle of -/// clock. +/// @note Register Clock Driver, Input Bus Termination for Chip Select in tens of +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cs(const fapi2::Target& i_target, uint8_t& o_value) { - uint8_t l_value[2]; + uint8_t l_value[2][2]; auto l_mca = i_target.getParent(); + auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, l_mca.getParent(), - l_value) ); - o_value = l_value[mss::index(l_mca)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS, l_mcs, l_value) ); + o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN getter -/// @param[in] const ref to the fapi2::Target +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS getter +/// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @note Generated by gen_accessors.pl generateParameters (G) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of -/// one cycle of -/// clock. +/// @note Register Clock Driver, Input Bus Termination for Chip Select in tens of +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cs(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -18451,82 +18492,84 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkn(const fapi2::Target(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN, i_target, l_value) ); - memcpy(o_array, &l_value, 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKN: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (H) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of -/// one cycle of -/// clock. +/// @note Register Clock Driver, Input Bus Termination for Chip Select in tens of +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cs(const fapi2::Target& i_target, uint8_t* o_array) { - uint8_t l_value[2]; + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target.getParent(), - l_value) ); - o_value = l_value[mss::index(i_target)]; + uint8_t l_value[2][2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS, i_target, l_value) ); + memcpy(o_array, &l_value, 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @note Generated by gen_accessors.pl generateParameters (F) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of -/// one cycle of -/// clock. +/// @note Register Clock Driver, Input Bus Termination for On Die Termination in tens of +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_odt(const fapi2::Target& i_target, uint8_t& o_value) { - uint8_t l_value[2]; + uint8_t l_value[2][2]; auto l_mca = i_target.getParent(); + auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, l_mca.getParent(), - l_value) ); - o_value = l_value[mss::index(l_mca)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT, l_mcs, l_value) ); + o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP getter -/// @param[in] const ref to the fapi2::Target +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT getter +/// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @note Generated by gen_accessors.pl generateParameters (G) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of -/// one cycle of -/// clock. +/// @note Register Clock Driver, Input Bus Termination for On Die Termination in tens of +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_odt(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -18535,82 +18578,91 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d0_clkp(const fapi2::Target(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP, i_target, l_value) ); - memcpy(o_array, &l_value, 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D0_CLKP: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (H) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of -/// one cycle of -/// clock. +/// @note Register Clock Driver, Input Bus Termination for On Die Termination in tens of +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_odt(const fapi2::Target& i_target, + uint8_t* o_array) { - uint8_t l_value[2]; + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target.getParent(), - l_value) ); - o_value = l_value[mss::index(i_target)]; + uint8_t l_value[2][2]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT, i_target, l_value) ); + memcpy(o_array, &l_value, 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter +/// @brief ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS getter /// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of -/// one cycle of -/// clock. +/// @note DQ and DQS Drive Impedance for +/// [Port][DIMM][RANK]. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target& i_target, + uint8_t* o_array) { - uint8_t l_value[2]; + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + uint8_t l_value[2][2][4]; auto l_mca = i_target.getParent(); + auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, l_mca.getParent(), - l_value) ); - o_value = l_value[mss::index(l_mca)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN getter -/// @param[in] const ref to the fapi2::Target +/// @brief ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS getter +/// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @note Generated by gen_accessors.pl generateParameters (B) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of -/// one cycle of -/// clock. +/// @note DQ and DQS Drive Impedance for +/// [Port][DIMM][RANK]. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target& i_target, +inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) @@ -18619,83 +18671,90 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkn(const fapi2::Target(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN, i_target, l_value) ); - memcpy(o_array, &l_value, 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKN: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (C) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of -/// one cycle of -/// clock. +/// @note DQ and DQS Drive Impedance for +/// [Port][DIMM][RANK]. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target& i_target, + uint8_t* o_array) { - uint8_t l_value[2]; + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target.getParent(), - l_value) ); - o_value = l_value[mss::index(i_target)]; + uint8_t l_value[2][2][4]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS, i_target, l_value) ); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter +/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_NOM getter /// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of -/// one cycle of -/// clock. +/// @note DRAM side Nominal Termination Resistance in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target& i_target, uint8_t* o_array) { - uint8_t l_value[2]; + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } + + uint8_t l_value[2][2][4]; auto l_mca = i_target.getParent(); + auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, l_mca.getParent(), - l_value) ); - o_value = l_value[mss::index(l_mca)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_NOM, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_NOM: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP getter -/// @param[in] const ref to the fapi2::Target +/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_NOM getter +/// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @note Generated by gen_accessors.pl generateParameters (B) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Phase rotator delay value of Clock for Dimm#_CLK# in ticks. Ticks are 1/128 of -/// one cycle of -/// clock. +/// @note DRAM side Nominal Termination Resistance in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -18703,170 +18762,209 @@ inline fapi2::ReturnCode vpd_mr_mc_phase_rot_d1_clkp(const fapi2::Target(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP, i_target, l_value) ); - memcpy(o_array, &l_value, 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_NOM, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_MC_PHASE_ROT_D1_CLKP: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_NOM: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_TSYS_ADR getter -/// @param[in] const ref to the TARGET_TYPE_MCS -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (NODIM A) +/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_NOM getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (C) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note ADR WRClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of -/// clock. Phase Rotator Static Offset value used to determine the Phase of the -/// WrClk with respect to SysClk. For zero delay simulations, or simulations where -/// the delay of the SysClk tree and the WrClk tree are equal, Set this field to -/// 60h +/// @note DRAM side Nominal Termination Resistance in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_tsys_adr(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target& i_target, uint8_t* o_array) { + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_TSYS_ADR, i_target, o_value) ); + uint8_t l_value[2][2][4]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_NOM, i_target, l_value) ); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_TSYS_ADR: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_NOM: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MR_TSYS_DATA getter -/// @param[in] const ref to the TARGET_TYPE_MCS -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (NODIM A) +/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_PARK getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DP16 WrClk Phase Rotator Offset Value in ticks. Ticks are 1/128 of one cycle of -/// clock. Phase Rotator Static Offset value used to determine the Phase of the -/// WrClk with respect to SysClk. For zero delay simulations, or simulations where -/// the delay of the SysClk tree and the WrClk tree are equal, Set this field to -/// 60h +/// @note DRAM side Park Termination Resistance in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mr_tsys_data(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target& i_target, uint8_t* o_array) { + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MR_TSYS_DATA, i_target, o_value) ); + uint8_t l_value[2][2][4]; + auto l_mca = i_target.getParent(); + auto l_mcs = l_mca.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_PARK, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MR_TSYS_DATA: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_PARK: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } - /// -/// @brief ATTR_MSS_VPD_MT_0_VERSION_LAYOUT getter -/// @param[in] const ref to the TARGET_TYPE_MCS -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (NODIM A) +/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_PARK getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (B) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note MT Keyword Layout Version Number. Increases when attributes are added, removed, -/// or redefined. Does not -/// reset. +/// @note DRAM side Park Termination Resistance in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_0_version_layout(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target& i_target, uint8_t* o_array) { + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_0_VERSION_LAYOUT, i_target, o_value) ); + uint8_t l_value[2][2][4]; + auto l_mcs = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_PARK, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_0_VERSION_LAYOUT: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_PARK: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_1_VERSION_DATA getter -/// @param[in] const ref to the TARGET_TYPE_MCS -/// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (NODIM A) +/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_PARK getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (C) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note MT Keyword Data Version Number. Increases when data changes with the above -/// layout version. Resets when layout version number -/// increments. +/// @note DRAM side Park Termination Resistance in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_1_version_data(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target& i_target, uint8_t* o_array) { + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_1_VERSION_DATA, i_target, o_value) ); + uint8_t l_value[2][2][4]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_PARK, i_target, l_value) ); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_1_VERSION_DATA: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_PARK: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_2_SIGNATURE_HASH getter -/// @param[in] const ref to the TARGET_TYPE_MCS -/// @param[out] uint32_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (NODIM A) +/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_WR getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Hash Signature for the MT Keyword. The hash signature is 32bits for 256 bytes of -/// data. +/// @note DRAM side Write Termination Resistance in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_2_signature_hash(const fapi2::Target& i_target, - uint32_t& o_value) +inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target& i_target, uint8_t* o_array) { + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_2_SIGNATURE_HASH, i_target, o_value) ); + uint8_t l_value[2][2][4]; + auto l_mca = i_target.getParent(); + auto l_mcs = l_mca.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_WR, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_2_SIGNATURE_HASH: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_WR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (F) +/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_WR getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (B) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination for Command/Address in tens of +/// @note DRAM side Write Termination Resistance in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_ca(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target& i_target, uint8_t* o_array) { - uint8_t l_value[2][2]; - auto l_mca = i_target.getParent(); - auto l_mcs = l_mca.getParent(); + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA, l_mcs, l_value) ); - o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; + uint8_t l_value[2][2][4]; + auto l_mcs = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_WR, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_WR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA getter -/// @param[in] const ref to the fapi2::Target +/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_WR getter +/// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (G) +/// @note Generated by gen_accessors.pl generateParameters (C) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination for Command/Address in tens of +/// @note DRAM side Write Termination Resistance in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_ca(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -18874,85 +18972,81 @@ inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_ca(const fapi2::Target(); + uint8_t l_value[2][2][4]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_WR, i_target, l_value) ); + memcpy(o_array, &l_value, 16); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_WR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (H) +/// @brief ATTR_MSS_VPD_MT_MC_BIAS_TRIM getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination for Command/Address in tens of -/// Ohms. +/// @note Adjusts the receiver internal current bias. ONLY set range 0-7. Default value is +/// 3. [VPD Value] = [Binary bit value set in register] 0 = 110 (Minimal power) 1 = +/// 010 2 = 100 3 = 000 (Default) 4 = 111 5 = 011 6 = 101 7 = 001 (Maximum +/// power) /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_ca(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_bias_trim(const fapi2::Target& i_target, uint8_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2]; + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA, i_target, l_value) ); - memcpy(o_array, &l_value, 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_BIAS_TRIM, i_target.getParent(), l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CA: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_BIAS_TRIM: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE getter +/// @brief ATTR_MSS_VPD_MT_MC_BIAS_TRIM getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (F) +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination for Clock Enable in tens of -/// Ohms. +/// @note Adjusts the receiver internal current bias. ONLY set range 0-7. Default value is +/// 3. [VPD Value] = [Binary bit value set in register] 0 = 110 (Minimal power) 1 = +/// 010 2 = 100 3 = 000 (Default) 4 = 111 5 = 011 6 = 101 7 = 001 (Maximum +/// power) /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cke(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_bias_trim(const fapi2::Target& i_target, uint8_t& o_value) { - uint8_t l_value[2][2]; + uint8_t l_value[2]; auto l_mca = i_target.getParent(); - auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE, l_mcs, l_value) ); - o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_BIAS_TRIM, l_mca.getParent(), l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_BIAS_TRIM: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE getter -/// @param[in] const ref to the fapi2::Target +/// @brief ATTR_MSS_VPD_MT_MC_BIAS_TRIM getter +/// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (G) +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination for Clock Enable in tens of -/// Ohms. +/// @note Adjusts the receiver internal current bias. ONLY set range 0-7. Default value is +/// 3. [VPD Value] = [Binary bit value set in register] 0 = 110 (Minimal power) 1 = +/// 010 2 = 100 3 = 000 (Default) 4 = 111 5 = 011 6 = 101 7 = 001 (Maximum +/// power) /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cke(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_bias_trim(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -18960,85 +19054,98 @@ inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cke(const fapi2::Target(); + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_BIAS_TRIM, i_target, l_value) ); + memcpy(o_array, &l_value, 2); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_BIAS_TRIM: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (H) +/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint32_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination for Clock Enable in tens of -/// Ohms. +/// @note Selects the number of enabled pullup branches during READ mode. ONLY set range +/// 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit +/// 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = +/// DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = +/// DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = +/// DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = +/// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits +/// 8-15) /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cke(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target& i_target, + uint32_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2]; + uint32_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE, i_target, l_value) ); - memcpy(o_array, &l_value, 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP, i_target.getParent(), + l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CKE: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS getter +/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP getter /// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (F) +/// @param[out] ref to the value uint32_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination for Chip Select in tens of -/// Ohms. +/// @note Selects the number of enabled pullup branches during READ mode. ONLY set range +/// 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit +/// 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = +/// DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = +/// DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = +/// DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = +/// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits +/// 8-15) /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cs(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target& i_target, + uint32_t& o_value) { - uint8_t l_value[2][2]; + uint32_t l_value[2]; auto l_mca = i_target.getParent(); - auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS, l_mcs, l_value) ); - o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP, l_mca.getParent(), + l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (G) +/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint32_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination for Chip Select in tens of -/// Ohms. +/// @note Selects the number of enabled pullup branches during READ mode. ONLY set range +/// 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit +/// 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = +/// DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = +/// DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = +/// DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = +/// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits +/// 8-15) /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cs(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target& i_target, + uint32_t* o_array) { if (o_array == nullptr) { @@ -19046,85 +19153,98 @@ inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cs(const fapi2::Target(); + uint32_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (H) +/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint32_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination for Chip Select in tens of -/// Ohms. +/// @note Selects the number of enabled pulldown branches during WRITE mode. ONLY set +/// range 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches +/// selected) Bit 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits +/// 8-15) Bit 6-8 = DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits +/// 8-15) Bit 12-14 = DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits +/// 8-15) Bit 18-20 = DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits +/// 8-15) Bit 24-26 = DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits +/// 8-15) /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_cs(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target& i_target, + uint32_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2]; + uint32_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS, i_target, l_value) ); - memcpy(o_array, &l_value, 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN, i_target.getParent(), + l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_CS: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT getter +/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN getter /// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (F) +/// @param[out] ref to the value uint32_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination for On Die Termination in tens of -/// Ohms. +/// @note Selects the number of enabled pulldown branches during WRITE mode. ONLY set +/// range 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches +/// selected) Bit 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits +/// 8-15) Bit 6-8 = DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits +/// 8-15) Bit 12-14 = DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits +/// 8-15) Bit 18-20 = DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits +/// 8-15) Bit 24-26 = DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits +/// 8-15) /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_odt(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target& i_target, + uint32_t& o_value) { - uint8_t l_value[2][2]; + uint32_t l_value[2]; auto l_mca = i_target.getParent(); - auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT, l_mcs, l_value) ); - o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN, l_mca.getParent(), + l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (G) +/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint32_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination for On Die Termination in tens of -/// Ohms. +/// @note Selects the number of enabled pulldown branches during WRITE mode. ONLY set +/// range 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches +/// selected) Bit 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits +/// 8-15) Bit 6-8 = DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits +/// 8-15) Bit 12-14 = DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits +/// 8-15) Bit 18-20 = DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits +/// 8-15) Bit 24-26 = DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits +/// 8-15) /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_odt(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target& i_target, + uint32_t* o_array) { if (o_array == nullptr) { @@ -19132,92 +19252,98 @@ inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_odt(const fapi2::Target(); + uint32_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (H) +/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint32_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Register Clock Driver, Input Bus Termination for On Die Termination in tens of -/// Ohms. +/// @note Selects the number of enabled pullup branches during WRITE mode. ONLY set range +/// 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit +/// 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = +/// DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = +/// DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = +/// DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = +/// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits +/// 8-15) /// -inline fapi2::ReturnCode vpd_mt_dimm_rcd_ibt_odt(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target& i_target, + uint32_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2]; + uint32_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT, i_target, l_value) ); - memcpy(o_array, &l_value, 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP, i_target.getParent(), + l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DIMM_RCD_IBT_ODT: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS getter +/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP getter /// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (A) +/// @param[out] ref to the value uint32_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DQ and DQS Drive Impedance for -/// [Port][DIMM][RANK]. +/// @note Selects the number of enabled pullup branches during WRITE mode. ONLY set range +/// 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit +/// 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = +/// DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = +/// DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = +/// DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = +/// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits +/// 8-15) /// -inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target& i_target, + uint32_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2][4]; + uint32_t l_value[2]; auto l_mca = i_target.getParent(); - auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP, l_mca.getParent(), + l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (B) +/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint32_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DQ and DQS Drive Impedance for -/// [Port][DIMM][RANK]. +/// @note Selects the number of enabled pullup branches during WRITE mode. ONLY set range +/// 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit +/// 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = +/// DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = +/// DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = +/// DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = +/// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits +/// 8-15) /// -inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target& i_target, + uint32_t* o_array) { if (o_array == nullptr) { @@ -19225,120 +19351,106 @@ inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target(); + uint32_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP, i_target, l_value) ); + memcpy(o_array, &l_value, 8); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (C) +/// @brief ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint64_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DQ and DQS Drive Impedance for -/// [Port][DIMM][RANK]. +/// @note Sets the capacitance value in the RC source degeneration. ONLY set range 0-3. +/// (b00 = No capacitor selected, b01 = more caps selected, b10 = even more caps +/// selected, b11 = maximum capacitors selected) Bit 0-1 = DP16 Block 0 Nibble 0 Bit +/// 16-17 = DP16 Block 2 Nibble 0 Bit 32-33 = DP16 Block 4 Nibble 0 Bit 2-3 = DP16 +/// Block 0 Nibble 1 Bit 18-19 = DP16 Block 2 Nibble 1 Bit 34-35 = DP16 Block 4 +/// Nibble 1 Bit 4-5 = DP16 Block 0 Nibble 2 Bit 20-21 = DP16 Block 2 Nibble 2 Bit +/// 36-37 = DP16 Block 4 Nibble 2 Bit 6-7 = DP16 Block 0 Nibble 3 Bit 22-23 = DP16 +/// Block 2 Nibble 3 Bit 38-39 = DP16 Block 4 Nibble 3 Bit 8-9 = DP16 Block 1 Nibble +/// 0 Bit 24-25 = DP16 Block 3 Nibble 0 Bit 10-11 = DP16 Block 1 Nibble 1 Bit 26-27 +/// = DP16 Block 3 Nibble 1 Bit 12-13 = DP16 Block 1 Nibble 2 Bit 28-29 = DP16 Block +/// 3 Nibble 2 Bit 14-15 = DP16 Block 1 Nibble 3 Bit 30-31 = DP16 Block 3 Nibble +/// 3 /// -inline fapi2::ReturnCode vpd_mt_dram_drv_imp_dq_dqs(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target& i_target, uint64_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2][4]; + uint64_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS, i_target, l_value) ); - memcpy(o_array, &l_value, 16); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP, i_target.getParent(), l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_NOM getter +/// @brief ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP getter /// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (A) +/// @param[out] ref to the value uint64_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DRAM side Nominal Termination Resistance in -/// Ohms. +/// @note Sets the capacitance value in the RC source degeneration. ONLY set range 0-3. +/// (b00 = No capacitor selected, b01 = more caps selected, b10 = even more caps +/// selected, b11 = maximum capacitors selected) Bit 0-1 = DP16 Block 0 Nibble 0 Bit +/// 16-17 = DP16 Block 2 Nibble 0 Bit 32-33 = DP16 Block 4 Nibble 0 Bit 2-3 = DP16 +/// Block 0 Nibble 1 Bit 18-19 = DP16 Block 2 Nibble 1 Bit 34-35 = DP16 Block 4 +/// Nibble 1 Bit 4-5 = DP16 Block 0 Nibble 2 Bit 20-21 = DP16 Block 2 Nibble 2 Bit +/// 36-37 = DP16 Block 4 Nibble 2 Bit 6-7 = DP16 Block 0 Nibble 3 Bit 22-23 = DP16 +/// Block 2 Nibble 3 Bit 38-39 = DP16 Block 4 Nibble 3 Bit 8-9 = DP16 Block 1 Nibble +/// 0 Bit 24-25 = DP16 Block 3 Nibble 0 Bit 10-11 = DP16 Block 1 Nibble 1 Bit 26-27 +/// = DP16 Block 3 Nibble 1 Bit 12-13 = DP16 Block 1 Nibble 2 Bit 28-29 = DP16 Block +/// 3 Nibble 2 Bit 14-15 = DP16 Block 1 Nibble 3 Bit 30-31 = DP16 Block 3 Nibble +/// 3 /// -inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target& i_target, + uint64_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2][4]; + uint64_t l_value[2]; auto l_mca = i_target.getParent(); - auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_NOM, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP, l_mca.getParent(), l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_NOM: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_NOM getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (B) +/// @brief ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint64_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DRAM side Nominal Termination Resistance in -/// Ohms. -/// -inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target& i_target, uint8_t* o_array) -{ - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2][4]; - auto l_mcs = i_target.getParent(); - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_NOM, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_NOM: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_NOM getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (C) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DRAM side Nominal Termination Resistance in -/// Ohms. +/// @note Sets the capacitance value in the RC source degeneration. ONLY set range 0-3. +/// (b00 = No capacitor selected, b01 = more caps selected, b10 = even more caps +/// selected, b11 = maximum capacitors selected) Bit 0-1 = DP16 Block 0 Nibble 0 Bit +/// 16-17 = DP16 Block 2 Nibble 0 Bit 32-33 = DP16 Block 4 Nibble 0 Bit 2-3 = DP16 +/// Block 0 Nibble 1 Bit 18-19 = DP16 Block 2 Nibble 1 Bit 34-35 = DP16 Block 4 +/// Nibble 1 Bit 4-5 = DP16 Block 0 Nibble 2 Bit 20-21 = DP16 Block 2 Nibble 2 Bit +/// 36-37 = DP16 Block 4 Nibble 2 Bit 6-7 = DP16 Block 0 Nibble 3 Bit 22-23 = DP16 +/// Block 2 Nibble 3 Bit 38-39 = DP16 Block 4 Nibble 3 Bit 8-9 = DP16 Block 1 Nibble +/// 0 Bit 24-25 = DP16 Block 3 Nibble 0 Bit 10-11 = DP16 Block 1 Nibble 1 Bit 26-27 +/// = DP16 Block 3 Nibble 1 Bit 12-13 = DP16 Block 1 Nibble 2 Bit 28-29 = DP16 Block +/// 3 Nibble 2 Bit 14-15 = DP16 Block 1 Nibble 3 Bit 30-31 = DP16 Block 3 Nibble +/// 3 /// -inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target& i_target, uint64_t* o_array) { if (o_array == nullptr) { @@ -19346,89 +19458,106 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_nom(const fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (A) +/// @brief ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint64_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DRAM side Park Termination Resistance in -/// Ohms. +/// @note Sets the resistance value in the RC source degeneration. Also defines the CTLE's +/// DC Gain. ONLY set range 0-7. (b000 = max resistance, b001 to b110 = decreasing +/// resistance, b111 = min resistance) Bit 0-2 = DP16 Block 0 Nibble 0 Bit 24-26 = +/// DP16 Block 2 Nibble 0 Bit 48-50 = DP16 Block 4 Nibble 0 Bit 3-5 = DP16 Block 0 +/// Nibble 1 Bit 27-29 = DP16 Block 2 Nibble 1 Bit 51-53 = DP16 Block 4 Nibble 1 Bit +/// 6-8 = DP16 Block 0 Nibble 2 Bit 30-32 = DP16 Block 2 Nibble 2 Bit 54-56 = DP16 +/// Block 4 Nibble 2 Bit 9-11 = DP16 Block 0 Nibble 3 Bit 33-35 = DP16 Block 2 +/// Nibble 3 Bit 57-59 = DP16 Block 4 Nibble 3 Bit 12-14 = DP16 Block 1 Nibble 0 Bit +/// 36-38 = DP16 Block 3 Nibble 0 Bit 15-17 = DP16 Block 1 Nibble 1 Bit 39-41 = DP16 +/// Block 3 Nibble 1 Bit 18-20 = DP16 Block 1 Nibble 2 Bit 42-44 = DP16 Block 3 +/// Nibble 2 Bit 21-23 = DP16 Block 1 Nibble 3 Bit 45-47 = DP16 Block 3 Nibble +/// 3 /// -inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target& i_target, uint64_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2][4]; - auto l_mca = i_target.getParent(); - auto l_mcs = l_mca.getParent(); + uint64_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_PARK, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES, i_target.getParent(), l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_PARK: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_PARK getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (B) +/// @brief ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint64_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DRAM side Park Termination Resistance in -/// Ohms. +/// @note Sets the resistance value in the RC source degeneration. Also defines the CTLE's +/// DC Gain. ONLY set range 0-7. (b000 = max resistance, b001 to b110 = decreasing +/// resistance, b111 = min resistance) Bit 0-2 = DP16 Block 0 Nibble 0 Bit 24-26 = +/// DP16 Block 2 Nibble 0 Bit 48-50 = DP16 Block 4 Nibble 0 Bit 3-5 = DP16 Block 0 +/// Nibble 1 Bit 27-29 = DP16 Block 2 Nibble 1 Bit 51-53 = DP16 Block 4 Nibble 1 Bit +/// 6-8 = DP16 Block 0 Nibble 2 Bit 30-32 = DP16 Block 2 Nibble 2 Bit 54-56 = DP16 +/// Block 4 Nibble 2 Bit 9-11 = DP16 Block 0 Nibble 3 Bit 33-35 = DP16 Block 2 +/// Nibble 3 Bit 57-59 = DP16 Block 4 Nibble 3 Bit 12-14 = DP16 Block 1 Nibble 0 Bit +/// 36-38 = DP16 Block 3 Nibble 0 Bit 15-17 = DP16 Block 1 Nibble 1 Bit 39-41 = DP16 +/// Block 3 Nibble 1 Bit 18-20 = DP16 Block 1 Nibble 2 Bit 42-44 = DP16 Block 3 +/// Nibble 2 Bit 21-23 = DP16 Block 1 Nibble 3 Bit 45-47 = DP16 Block 3 Nibble +/// 3 /// -inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target& i_target, + uint64_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2][4]; - auto l_mcs = i_target.getParent(); + uint64_t l_value[2]; + auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_PARK, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES, l_mca.getParent(), l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_PARK: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_PARK getter +/// @brief ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES getter /// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (C) +/// @param[out] uint64_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DRAM side Park Termination Resistance in -/// Ohms. +/// @note Sets the resistance value in the RC source degeneration. Also defines the CTLE's +/// DC Gain. ONLY set range 0-7. (b000 = max resistance, b001 to b110 = decreasing +/// resistance, b111 = min resistance) Bit 0-2 = DP16 Block 0 Nibble 0 Bit 24-26 = +/// DP16 Block 2 Nibble 0 Bit 48-50 = DP16 Block 4 Nibble 0 Bit 3-5 = DP16 Block 0 +/// Nibble 1 Bit 27-29 = DP16 Block 2 Nibble 1 Bit 51-53 = DP16 Block 4 Nibble 1 Bit +/// 6-8 = DP16 Block 0 Nibble 2 Bit 30-32 = DP16 Block 2 Nibble 2 Bit 54-56 = DP16 +/// Block 4 Nibble 2 Bit 9-11 = DP16 Block 0 Nibble 3 Bit 33-35 = DP16 Block 2 +/// Nibble 3 Bit 57-59 = DP16 Block 4 Nibble 3 Bit 12-14 = DP16 Block 1 Nibble 0 Bit +/// 36-38 = DP16 Block 3 Nibble 0 Bit 15-17 = DP16 Block 1 Nibble 1 Bit 39-41 = DP16 +/// Block 3 Nibble 1 Bit 18-20 = DP16 Block 1 Nibble 2 Bit 42-44 = DP16 Block 3 +/// Nibble 2 Bit 21-23 = DP16 Block 1 Nibble 3 Bit 45-47 = DP16 Block 3 Nibble +/// 3 /// -inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target& i_target, uint64_t* o_array) { if (o_array == nullptr) { @@ -19436,89 +19565,75 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_park(const fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (A) +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DRAM side Write Termination Resistance in +/// @note Memory Controller side Drive Impedance for Clock in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target& i_target, uint8_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2][4]; - auto l_mca = i_target.getParent(); - auto l_mcs = l_mca.getParent(); + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_WR, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, i_target.getParent(), l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_WR: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_WR getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (B) +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DRAM side Write Termination Resistance in +/// @note Memory Controller side Drive Impedance for Clock in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target& i_target, uint8_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2][4]; - auto l_mcs = i_target.getParent(); + uint8_t l_value[2]; + auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_DRAM_RTT_WR, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, l_mca.getParent(), l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_DRAM_RTT_WR: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_DRAM_RTT_WR getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (C) +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DRAM side Write Termination Resistance in +/// @note Memory Controller side Drive Impedance for Clock in /// Ohms. /// -inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -19526,81 +19641,83 @@ inline fapi2::ReturnCode vpd_mt_dram_rtt_wr(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Adjusts the receiver internal current bias. ONLY set range 0-7. Default value is -/// 3. [VPD Value] = [Binary bit value set in register] 0 = 110 (Minimal power) 1 = -/// 010 2 = 100 3 = 000 (Default) 4 = 111 5 = 011 6 = 101 7 = 001 (Maximum -/// power) +/// @note Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and +/// Activate Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_bias_trim(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cmd_addr(const fapi2::Target& i_target, + uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_BIAS_TRIM, i_target.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR, i_target.getParent(), + l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_BIAS_TRIM: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_BIAS_TRIM getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Adjusts the receiver internal current bias. ONLY set range 0-7. Default value is -/// 3. [VPD Value] = [Binary bit value set in register] 0 = 110 (Minimal power) 1 = -/// 010 2 = 100 3 = 000 (Default) 4 = 111 5 = 011 6 = 101 7 = 001 (Maximum -/// power) +/// @note Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and +/// Activate Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_bias_trim(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cmd_addr(const fapi2::Target& i_target, + uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_BIAS_TRIM, l_mca.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR, l_mca.getParent(), + l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_BIAS_TRIM: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_BIAS_TRIM getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Adjusts the receiver internal current bias. ONLY set range 0-7. Default value is -/// 3. [VPD Value] = [Binary bit value set in register] 0 = 110 (Minimal power) 1 = -/// 010 2 = 100 3 = 000 (Default) 4 = 111 5 = 011 6 = 101 7 = 001 (Maximum -/// power) +/// @note Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and +/// Activate Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_bias_trim(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cmd_addr(const fapi2::Target& i_target, + uint8_t* o_array) { if (o_array == nullptr) { @@ -19610,96 +19727,78 @@ inline fapi2::ReturnCode vpd_mt_mc_bias_trim(const fapi2::Target -/// @param[out] ref to the value uint32_t +/// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Selects the number of enabled pullup branches during READ mode. ONLY set range -/// 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit -/// 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = -/// DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = -/// DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = -/// DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = -/// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits -/// 8-15) +/// @note Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset +/// Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target& i_target, - uint32_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target& i_target, uint8_t& o_value) { - uint32_t l_value[2]; + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL getter /// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint32_t +/// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Selects the number of enabled pullup branches during READ mode. ONLY set range -/// 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit -/// 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = -/// DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = -/// DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = -/// DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = -/// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits -/// 8-15) +/// @note Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset +/// Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target& i_target, - uint32_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target& i_target, + uint8_t& o_value) { - uint32_t l_value[2]; + uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP, l_mca.getParent(), - l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_RD_UP getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL getter /// @param[in] const ref to the fapi2::Target -/// @param[out] uint32_t* memory to store the value +/// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Selects the number of enabled pullup branches during READ mode. ONLY set range -/// 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit -/// 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = -/// DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = -/// DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = -/// DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = -/// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits -/// 8-15) +/// @note Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset +/// Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target& i_target, - uint32_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -19707,98 +19806,79 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_rd_up(const fapi2::Target -/// @param[out] ref to the value uint32_t +/// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Selects the number of enabled pulldown branches during WRITE mode. ONLY set -/// range 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches -/// selected) Bit 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits -/// 8-15) Bit 6-8 = DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits -/// 8-15) Bit 12-14 = DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits -/// 8-15) Bit 18-20 = DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits -/// 8-15) Bit 24-26 = DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits -/// 8-15) +/// @note Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target& i_target, - uint32_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cscid(const fapi2::Target& i_target, + uint8_t& o_value) { - uint32_t l_value[2]; + uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN, i_target.getParent(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID getter /// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint32_t +/// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Selects the number of enabled pulldown branches during WRITE mode. ONLY set -/// range 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches -/// selected) Bit 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits -/// 8-15) Bit 6-8 = DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits -/// 8-15) Bit 12-14 = DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits -/// 8-15) Bit 18-20 = DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits -/// 8-15) Bit 24-26 = DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits -/// 8-15) +/// @note Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target& i_target, - uint32_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cscid(const fapi2::Target& i_target, + uint8_t& o_value) { - uint32_t l_value[2]; + uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN, l_mca.getParent(), - l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_DOWN getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID getter /// @param[in] const ref to the fapi2::Target -/// @param[out] uint32_t* memory to store the value +/// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Selects the number of enabled pulldown branches during WRITE mode. ONLY set -/// range 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches -/// selected) Bit 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits -/// 8-15) Bit 6-8 = DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits -/// 8-15) Bit 12-14 = DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits -/// 8-15) Bit 18-20 = DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits -/// 8-15) Bit 24-26 = DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits -/// 8-15) +/// @note Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target& i_target, - uint32_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cscid(const fapi2::Target& i_target, + uint8_t* o_array) { if (o_array == nullptr) { @@ -19806,98 +19886,89 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_down(const fapi2::Target -/// @param[out] ref to the value uint32_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (F) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Selects the number of enabled pullup branches during WRITE mode. ONLY set range -/// 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit -/// 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = -/// DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = -/// DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = -/// DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = -/// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits -/// 8-15) +/// @note Memory Controller side Drive Impedance for [PORT][DP16] Data and Data Strobe +/// Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target& i_target, - uint32_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target& i_target, + uint8_t& o_value) { - uint32_t l_value[2]; + uint8_t l_value[2][5]; + auto l_mca = i_target.getParent(); + auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP, i_target.getParent(), - l_value) ); - o_value = l_value[mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, l_mcs, l_value) ); + o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint32_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (G) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Selects the number of enabled pullup branches during WRITE mode. ONLY set range -/// 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit -/// 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = -/// DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = -/// DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = -/// DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = -/// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits -/// 8-15) +/// @note Memory Controller side Drive Impedance for [PORT][DP16] Data and Data Strobe +/// Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target& i_target, - uint32_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target& i_target, + uint8_t* o_array) { - uint32_t l_value[2]; - auto l_mca = i_target.getParent(); + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP, l_mca.getParent(), - l_value) ); - o_value = l_value[mss::index(l_mca)]; + uint8_t l_value[2][5]; + auto l_mcs = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 5); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DQ_ACBOOST_WR_UP getter +/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS getter /// @param[in] const ref to the fapi2::Target -/// @param[out] uint32_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (H) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Selects the number of enabled pullup branches during WRITE mode. ONLY set range -/// 0-7. Eg. 0x02 = b010 (1 branch selected), 0x06 = b110 (2 branches selected) Bit -/// 0-2 = DP16 Block 0 (DQ Bits 0-7) Bit 3-5 = DP16 Block 0 (DQ Bits 8-15) Bit 6-8 = -/// DP16 Block 1 (DQ Bits 0-7) Bit 9-11 = DP16 Block 1 (DQ Bits 8-15) Bit 12-14 = -/// DP16 Block 2 (DQ Bits 0-7) Bit 15-17 = DP16 Block 2 (DQ Bits 8-15) Bit 18-20 = -/// DP16 Block 3 (DQ Bits 0-7) Bit 21-23 = DP16 Block 3 (DQ Bits 8-15) Bit 24-26 = -/// DP16 Block 4 (DQ Bits 0-7) Bit 27-29 = DP16 Block 4 (DQ Bits -/// 8-15) -/// -inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target& i_target, - uint32_t* o_array) +/// @note Memory Controller side Drive Impedance for [PORT][DP16] Data and Data Strobe +/// Lines in +/// Ohms. +/// +inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target& i_target, + uint8_t* o_array) { if (o_array == nullptr) { @@ -19905,106 +19976,89 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_acboost_wr_up(const fapi2::Target -/// @param[out] ref to the value uint64_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value uint8_t +/// @note Generated by gen_accessors.pl generateParameters (F) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Sets the capacitance value in the RC source degeneration. ONLY set range 0-3. -/// (b00 = No capacitor selected, b01 = more caps selected, b10 = even more caps -/// selected, b11 = maximum capacitors selected) Bit 0-1 = DP16 Block 0 Nibble 0 Bit -/// 16-17 = DP16 Block 2 Nibble 0 Bit 32-33 = DP16 Block 4 Nibble 0 Bit 2-3 = DP16 -/// Block 0 Nibble 1 Bit 18-19 = DP16 Block 2 Nibble 1 Bit 34-35 = DP16 Block 4 -/// Nibble 1 Bit 4-5 = DP16 Block 0 Nibble 2 Bit 20-21 = DP16 Block 2 Nibble 2 Bit -/// 36-37 = DP16 Block 4 Nibble 2 Bit 6-7 = DP16 Block 0 Nibble 3 Bit 22-23 = DP16 -/// Block 2 Nibble 3 Bit 38-39 = DP16 Block 4 Nibble 3 Bit 8-9 = DP16 Block 1 Nibble -/// 0 Bit 24-25 = DP16 Block 3 Nibble 0 Bit 10-11 = DP16 Block 1 Nibble 1 Bit 26-27 -/// = DP16 Block 3 Nibble 1 Bit 12-13 = DP16 Block 1 Nibble 2 Bit 28-29 = DP16 Block -/// 3 Nibble 2 Bit 14-15 = DP16 Block 1 Nibble 3 Bit 30-31 = DP16 Block 3 Nibble -/// 3 +/// @note Memory Controller side Receiver Impedance for [PORT][DP16] Data and Data Strobe +/// Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target& i_target, uint64_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target& i_target, + uint8_t& o_value) { - uint64_t l_value[2]; + uint8_t l_value[2][5]; + auto l_mca = i_target.getParent(); + auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP, i_target.getParent(), l_value) ); - o_value = l_value[mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS, l_mcs, l_value) ); + o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint64_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @brief ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (G) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Sets the capacitance value in the RC source degeneration. ONLY set range 0-3. -/// (b00 = No capacitor selected, b01 = more caps selected, b10 = even more caps -/// selected, b11 = maximum capacitors selected) Bit 0-1 = DP16 Block 0 Nibble 0 Bit -/// 16-17 = DP16 Block 2 Nibble 0 Bit 32-33 = DP16 Block 4 Nibble 0 Bit 2-3 = DP16 -/// Block 0 Nibble 1 Bit 18-19 = DP16 Block 2 Nibble 1 Bit 34-35 = DP16 Block 4 -/// Nibble 1 Bit 4-5 = DP16 Block 0 Nibble 2 Bit 20-21 = DP16 Block 2 Nibble 2 Bit -/// 36-37 = DP16 Block 4 Nibble 2 Bit 6-7 = DP16 Block 0 Nibble 3 Bit 22-23 = DP16 -/// Block 2 Nibble 3 Bit 38-39 = DP16 Block 4 Nibble 3 Bit 8-9 = DP16 Block 1 Nibble -/// 0 Bit 24-25 = DP16 Block 3 Nibble 0 Bit 10-11 = DP16 Block 1 Nibble 1 Bit 26-27 -/// = DP16 Block 3 Nibble 1 Bit 12-13 = DP16 Block 1 Nibble 2 Bit 28-29 = DP16 Block -/// 3 Nibble 2 Bit 14-15 = DP16 Block 1 Nibble 3 Bit 30-31 = DP16 Block 3 Nibble -/// 3 +/// @note Memory Controller side Receiver Impedance for [PORT][DP16] Data and Data Strobe +/// Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target& i_target, - uint64_t& o_value) +inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target& i_target, + uint8_t* o_array) { - uint64_t l_value[2]; - auto l_mca = i_target.getParent(); + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP, l_mca.getParent(), l_value) ); - o_value = l_value[mss::index(l_mca)]; + uint8_t l_value[2][5]; + auto l_mcs = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 5); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DQ_CTLE_CAP getter +/// @brief ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS getter /// @param[in] const ref to the fapi2::Target -/// @param[out] uint64_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (H) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Sets the capacitance value in the RC source degeneration. ONLY set range 0-3. -/// (b00 = No capacitor selected, b01 = more caps selected, b10 = even more caps -/// selected, b11 = maximum capacitors selected) Bit 0-1 = DP16 Block 0 Nibble 0 Bit -/// 16-17 = DP16 Block 2 Nibble 0 Bit 32-33 = DP16 Block 4 Nibble 0 Bit 2-3 = DP16 -/// Block 0 Nibble 1 Bit 18-19 = DP16 Block 2 Nibble 1 Bit 34-35 = DP16 Block 4 -/// Nibble 1 Bit 4-5 = DP16 Block 0 Nibble 2 Bit 20-21 = DP16 Block 2 Nibble 2 Bit -/// 36-37 = DP16 Block 4 Nibble 2 Bit 6-7 = DP16 Block 0 Nibble 3 Bit 22-23 = DP16 -/// Block 2 Nibble 3 Bit 38-39 = DP16 Block 4 Nibble 3 Bit 8-9 = DP16 Block 1 Nibble -/// 0 Bit 24-25 = DP16 Block 3 Nibble 0 Bit 10-11 = DP16 Block 1 Nibble 1 Bit 26-27 -/// = DP16 Block 3 Nibble 1 Bit 12-13 = DP16 Block 1 Nibble 2 Bit 28-29 = DP16 Block -/// 3 Nibble 2 Bit 14-15 = DP16 Block 1 Nibble 3 Bit 30-31 = DP16 Block 3 Nibble -/// 3 +/// @note Memory Controller side Receiver Impedance for [PORT][DP16] Data and Data Strobe +/// Lines in +/// Ohms. /// -inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target& i_target, uint64_t* o_array) +inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target& i_target, + uint8_t* o_array) { if (o_array == nullptr) { @@ -20012,106 +20066,95 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_cap(const fapi2::Target -/// @param[out] ref to the value uint64_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_VPD_MT_ODT_RD getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Sets the resistance value in the RC source degeneration. Also defines the CTLE's -/// DC Gain. ONLY set range 0-7. (b000 = max resistance, b001 to b110 = decreasing -/// resistance, b111 = min resistance) Bit 0-2 = DP16 Block 0 Nibble 0 Bit 24-26 = -/// DP16 Block 2 Nibble 0 Bit 48-50 = DP16 Block 4 Nibble 0 Bit 3-5 = DP16 Block 0 -/// Nibble 1 Bit 27-29 = DP16 Block 2 Nibble 1 Bit 51-53 = DP16 Block 4 Nibble 1 Bit -/// 6-8 = DP16 Block 0 Nibble 2 Bit 30-32 = DP16 Block 2 Nibble 2 Bit 54-56 = DP16 -/// Block 4 Nibble 2 Bit 9-11 = DP16 Block 0 Nibble 3 Bit 33-35 = DP16 Block 2 -/// Nibble 3 Bit 57-59 = DP16 Block 4 Nibble 3 Bit 12-14 = DP16 Block 1 Nibble 0 Bit -/// 36-38 = DP16 Block 3 Nibble 0 Bit 15-17 = DP16 Block 1 Nibble 1 Bit 39-41 = DP16 -/// Block 3 Nibble 1 Bit 18-20 = DP16 Block 1 Nibble 2 Bit 42-44 = DP16 Block 3 -/// Nibble 2 Bit 21-23 = DP16 Block 1 Nibble 3 Bit 45-47 = DP16 Block 3 Nibble -/// 3 +/// @note READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to +/// fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 +/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 +/// ODT1][N/A][N/A] /// -inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target& i_target, uint64_t& o_value) +inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target& i_target, uint8_t* o_array) { - uint64_t l_value[2]; + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES, i_target.getParent(), l_value) ); - o_value = l_value[mss::index(i_target)]; + uint8_t l_value[2][2][4]; + auto l_mca = i_target.getParent(); + auto l_mcs = l_mca.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_RD, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_ODT_RD: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint64_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @brief ATTR_MSS_VPD_MT_ODT_RD getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (B) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Sets the resistance value in the RC source degeneration. Also defines the CTLE's -/// DC Gain. ONLY set range 0-7. (b000 = max resistance, b001 to b110 = decreasing -/// resistance, b111 = min resistance) Bit 0-2 = DP16 Block 0 Nibble 0 Bit 24-26 = -/// DP16 Block 2 Nibble 0 Bit 48-50 = DP16 Block 4 Nibble 0 Bit 3-5 = DP16 Block 0 -/// Nibble 1 Bit 27-29 = DP16 Block 2 Nibble 1 Bit 51-53 = DP16 Block 4 Nibble 1 Bit -/// 6-8 = DP16 Block 0 Nibble 2 Bit 30-32 = DP16 Block 2 Nibble 2 Bit 54-56 = DP16 -/// Block 4 Nibble 2 Bit 9-11 = DP16 Block 0 Nibble 3 Bit 33-35 = DP16 Block 2 -/// Nibble 3 Bit 57-59 = DP16 Block 4 Nibble 3 Bit 12-14 = DP16 Block 1 Nibble 0 Bit -/// 36-38 = DP16 Block 3 Nibble 0 Bit 15-17 = DP16 Block 1 Nibble 1 Bit 39-41 = DP16 -/// Block 3 Nibble 1 Bit 18-20 = DP16 Block 1 Nibble 2 Bit 42-44 = DP16 Block 3 -/// Nibble 2 Bit 21-23 = DP16 Block 1 Nibble 3 Bit 45-47 = DP16 Block 3 Nibble -/// 3 +/// @note READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to +/// fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 +/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 +/// ODT1][N/A][N/A] /// -inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target& i_target, - uint64_t& o_value) +inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target& i_target, uint8_t* o_array) { - uint64_t l_value[2]; - auto l_mca = i_target.getParent(); + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES, l_mca.getParent(), l_value) ); - o_value = l_value[mss::index(l_mca)]; + uint8_t l_value[2][2][4]; + auto l_mcs = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_RD, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_ODT_RD: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DQ_CTLE_RES getter +/// @brief ATTR_MSS_VPD_MT_ODT_RD getter /// @param[in] const ref to the fapi2::Target -/// @param[out] uint64_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (C) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Sets the resistance value in the RC source degeneration. Also defines the CTLE's -/// DC Gain. ONLY set range 0-7. (b000 = max resistance, b001 to b110 = decreasing -/// resistance, b111 = min resistance) Bit 0-2 = DP16 Block 0 Nibble 0 Bit 24-26 = -/// DP16 Block 2 Nibble 0 Bit 48-50 = DP16 Block 4 Nibble 0 Bit 3-5 = DP16 Block 0 -/// Nibble 1 Bit 27-29 = DP16 Block 2 Nibble 1 Bit 51-53 = DP16 Block 4 Nibble 1 Bit -/// 6-8 = DP16 Block 0 Nibble 2 Bit 30-32 = DP16 Block 2 Nibble 2 Bit 54-56 = DP16 -/// Block 4 Nibble 2 Bit 9-11 = DP16 Block 0 Nibble 3 Bit 33-35 = DP16 Block 2 -/// Nibble 3 Bit 57-59 = DP16 Block 4 Nibble 3 Bit 12-14 = DP16 Block 1 Nibble 0 Bit -/// 36-38 = DP16 Block 3 Nibble 0 Bit 15-17 = DP16 Block 1 Nibble 1 Bit 39-41 = DP16 -/// Block 3 Nibble 1 Bit 18-20 = DP16 Block 1 Nibble 2 Bit 42-44 = DP16 Block 3 -/// Nibble 2 Bit 21-23 = DP16 Block 1 Nibble 3 Bit 45-47 = DP16 Block 3 Nibble -/// 3 +/// @note READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to +/// fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 +/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 +/// ODT1][N/A][N/A] /// -inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target& i_target, uint64_t* o_array) +inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -20119,75 +20162,95 @@ inline fapi2::ReturnCode vpd_mt_mc_dq_ctle_res(const fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_VPD_MT_ODT_WR getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock in -/// Ohms. +/// @note WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT +/// to fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 +/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 +/// ODT1][N/A][N/A] /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target& i_target, uint8_t* o_array) { - uint8_t l_value[2]; + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, i_target.getParent(), l_value) ); - o_value = l_value[mss::index(i_target)]; + uint8_t l_value[2][2][4]; + auto l_mca = i_target.getParent(); + auto l_mcs = l_mca.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_WR, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_ODT_WR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @brief ATTR_MSS_VPD_MT_ODT_WR getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] uint8_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (B) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock in -/// Ohms. +/// @note WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT +/// to fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 +/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 +/// ODT1][N/A][N/A] /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target& i_target, uint8_t* o_array) { - uint8_t l_value[2]; - auto l_mca = i_target.getParent(); + if (o_array == nullptr) + { + FAPI_ERR("nullptr passed to attribute accessor %s", __func__); + return fapi2::FAPI2_RC_INVALID_PARAMETER; + } - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK, l_mca.getParent(), l_value) ); - o_value = l_value[mss::index(l_mca)]; + uint8_t l_value[2][2][4]; + auto l_mcs = i_target.getParent(); + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_WR, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_ODT_WR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CLK getter +/// @brief ATTR_MSS_VPD_MT_ODT_WR getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @note Generated by gen_accessors.pl generateParameters (C) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock in -/// Ohms. +/// @note WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT +/// to fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 +/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 +/// ODT1][N/A][N/A] /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -20195,83 +20258,87 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_clk(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and -/// Activate Lines in -/// Ohms. +/// @note Number of clocks used for read/write preamble. Calibration only uses 1 nCK +/// preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. The value +/// of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for +/// READ preamble, and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK +/// preamble for both READ and +/// WRITE /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cmd_addr(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR, i_target.getParent(), - l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_PREAMBLE, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_PREAMBLE: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR getter +/// @brief ATTR_MSS_VPD_MT_PREAMBLE getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and -/// Activate Lines in -/// Ohms. +/// @note Number of clocks used for read/write preamble. Calibration only uses 1 nCK +/// preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. The value +/// of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for +/// READ preamble, and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK +/// preamble for both READ and +/// WRITE /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cmd_addr(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR, l_mca.getParent(), - l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_PREAMBLE, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_PREAMBLE: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CMD_ADDR getter +/// @brief ATTR_MSS_VPD_MT_PREAMBLE getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Address, Bank Address, Bank Group and -/// Activate Lines in -/// Ohms. +/// @note Number of clocks used for read/write preamble. Calibration only uses 1 nCK +/// preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. The value +/// of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for +/// READ preamble, and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK +/// preamble for both READ and +/// WRITE /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cmd_addr(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -20281,78 +20348,76 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cmd_addr(const fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset -/// Lines in -/// Ohms. +/// @note DRAM side Write Vref setting for DDR4. Bit encode is 01234567. Bit 0 is unused. +/// Bit 1 is the Range. Bits 2-7 is the Value. Refer to the VrefDQ Training Table in +/// JEDEC. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_vref_dram_wr(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL, i_target.getParent(), - l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_VREF_DRAM_WR, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_VREF_DRAM_WR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL getter +/// @brief ATTR_MSS_VPD_MT_VREF_DRAM_WR getter /// @param[in] const ref to the fapi2::Target /// @param[out] ref to the value uint8_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset -/// Lines in -/// Ohms. +/// @note DRAM side Write Vref setting for DDR4. Bit encode is 01234567. Bit 0 is unused. +/// Bit 1 is the Range. Bits 2-7 is the Value. Refer to the VrefDQ Training Table in +/// JEDEC. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_vref_dram_wr(const fapi2::Target& i_target, uint8_t& o_value) { uint8_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL, l_mca.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_VREF_DRAM_WR, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_VREF_DRAM_WR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CNTL getter +/// @brief ATTR_MSS_VPD_MT_VREF_DRAM_WR getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Clock Enable, ODT, Parity, and Reset -/// Lines in -/// Ohms. +/// @note DRAM side Write Vref setting for DDR4. Bit encode is 01234567. Bit 0 is unused. +/// Bit 1 is the Range. Bits 2-7 is the Value. Refer to the VrefDQ Training Table in +/// JEDEC. /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_vref_dram_wr(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -20362,77 +20427,76 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cntl(const fapi2::Target -/// @param[out] ref to the value uint8_t +/// @param[out] ref to the value uint32_t /// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in -/// Ohms. +/// @note Memory Controller side Read Vref setting. Dividing by 1000 gives you percentage +/// of +/// Vdd /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cscid(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target& i_target, uint32_t& o_value) { - uint8_t l_value[2]; + uint32_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID, i_target.getParent(), - l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_VREF_MC_RD, i_target.getParent(), l_value) ); o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_VREF_MC_RD: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID getter +/// @brief ATTR_MSS_VPD_MT_VREF_MC_RD getter /// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t +/// @param[out] ref to the value uint32_t /// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in -/// Ohms. +/// @note Memory Controller side Read Vref setting. Dividing by 1000 gives you percentage +/// of +/// Vdd /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cscid(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target& i_target, uint32_t& o_value) { - uint8_t l_value[2]; + uint32_t l_value[2]; auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID, l_mca.getParent(), l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_VREF_MC_RD, l_mca.getParent(), l_value) ); o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_VREF_MC_RD: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_CSCID getter +/// @brief ATTR_MSS_VPD_MT_VREF_MC_RD getter /// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value +/// @param[out] uint32_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for Chip Select and Chip ID Lines in -/// Ohms. +/// @note Memory Controller side Read Vref setting. Dividing by 1000 gives you percentage +/// of +/// Vdd /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cscid(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target& i_target, uint32_t* o_array) { if (o_array == nullptr) { @@ -20440,179 +20504,81 @@ inline fapi2::ReturnCode vpd_mt_mc_drv_imp_cscid(const fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (F) +/// @brief ATTR_MSS_VPD_MT_WINDAGE_RD_CTR getter +/// @param[in] const ref to the fapi2::Target +/// @param[out] ref to the value int16_t +/// @note Generated by gen_accessors.pl generateParameters (D) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for [PORT][DP16] Data and Data Strobe -/// Lines in -/// Ohms. +/// @note Derived from calibration/characterization of read centering. Number of windage +/// offset in units of pico-seconds[ps]. Default is 0 Specification of the value in +/// this file is 2's compliment +/// hex /// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target& i_target, int16_t& o_value) { - uint8_t l_value[2][5]; - auto l_mca = i_target.getParent(); - auto l_mcs = l_mca.getParent(); + int16_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, l_mcs, l_value) ); - o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_WINDAGE_RD_CTR, i_target.getParent(), l_value) ); + o_value = l_value[mss::index(i_target)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_WINDAGE_RD_CTR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (G) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for [PORT][DP16] Data and Data Strobe -/// Lines in -/// Ohms. -/// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target& i_target, - uint8_t* o_array) -{ - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][5]; - auto l_mcs = i_target.getParent(); - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 5); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (H) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Drive Impedance for [PORT][DP16] Data and Data Strobe -/// Lines in -/// Ohms. -/// -inline fapi2::ReturnCode vpd_mt_mc_drv_imp_dq_dqs(const fapi2::Target& i_target, - uint8_t* o_array) -{ - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][5]; - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS, i_target, l_value) ); - memcpy(o_array, &l_value, 10); - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_DRV_IMP_DQ_DQS: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS getter +/// @brief ATTR_MSS_VPD_MT_WINDAGE_RD_CTR getter /// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (F) +/// @param[out] ref to the value int16_t +/// @note Generated by gen_accessors.pl generateParameters (D.1) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Receiver Impedance for [PORT][DP16] Data and Data Strobe -/// Lines in -/// Ohms. +/// @note Derived from calibration/characterization of read centering. Number of windage +/// offset in units of pico-seconds[ps]. Default is 0 Specification of the value in +/// this file is 2's compliment +/// hex /// -inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target& i_target, int16_t& o_value) { - uint8_t l_value[2][5]; + int16_t l_value[2]; auto l_mca = i_target.getParent(); - auto l_mcs = l_mca.getParent(); - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS, l_mcs, l_value) ); - o_value = l_value[mss::index(l_mca)][mss::index(i_target)]; - return fapi2::current_err; - -fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); - return fapi2::current_err; -} - -/// -/// @brief ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (G) -/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Receiver Impedance for [PORT][DP16] Data and Data Strobe -/// Lines in -/// Ohms. -/// -inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target& i_target, - uint8_t* o_array) -{ - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][5]; - auto l_mcs = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 5); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_WINDAGE_RD_CTR, l_mca.getParent(), l_value) ); + o_value = l_value[mss::index(l_mca)]; return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_WINDAGE_RD_CTR: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_MC_RCV_IMP_DQ_DQS getter +/// @brief ATTR_MSS_VPD_MT_WINDAGE_RD_CTR getter /// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (H) +/// @param[out] int16_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (E) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Receiver Impedance for [PORT][DP16] Data and Data Strobe -/// Lines in -/// Ohms. +/// @note Derived from calibration/characterization of read centering. Number of windage +/// offset in units of pico-seconds[ps]. Default is 0 Specification of the value in +/// this file is 2's compliment +/// hex /// -inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target& i_target, - uint8_t* o_array) +inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target& i_target, int16_t* o_array) { if (o_array == nullptr) { @@ -20620,30 +20586,32 @@ inline fapi2::ReturnCode vpd_mt_mc_rcv_imp_dq_dqs(const fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to -/// fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 -/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 -/// ODT1][N/A][N/A] +/// @note The Memory Clock Enable MAP is a bit map describing the Memory Clock Enable +/// signal to its respective rank. There are 8 bits, but only 4 are currently used +/// [DIMM0 CKE0][DIMM0 CKE1][N/A][N/A][DIMM1 CKE0][DIMM1 CKE1][N/A][N/A] E.g. 0x80 +/// -> 0b10000000, which means DIMM0 CKE0 is mapped to that +/// rank. /// -inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_cke_map(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -20655,28 +20623,29 @@ inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target(); auto l_mcs = l_mca.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_RD, l_mcs, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_CKE_MAP, l_mcs, l_value) ); memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_ODT_RD: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_CKE_MAP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_ODT_RD getter +/// @brief ATTR_MSS_VPD_CKE_MAP getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (B) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to -/// fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 -/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 -/// ODT1][N/A][N/A] +/// @note The Memory Clock Enable MAP is a bit map describing the Memory Clock Enable +/// signal to its respective rank. There are 8 bits, but only 4 are currently used +/// [DIMM0 CKE0][DIMM0 CKE1][N/A][N/A][DIMM1 CKE0][DIMM1 CKE1][N/A][N/A] E.g. 0x80 +/// -> 0b10000000, which means DIMM0 CKE0 is mapped to that +/// rank. /// -inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_cke_map(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -20687,28 +20656,29 @@ inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_RD, l_mcs, l_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_CKE_MAP, l_mcs, l_value) ); memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_ODT_RD: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_CKE_MAP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_ODT_RD getter +/// @brief ATTR_MSS_VPD_CKE_MAP getter /// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value /// @note Generated by gen_accessors.pl generateParameters (C) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note READ, On Die Termination triggering bitmap. Use bitmap to determine which ODT to -/// fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 -/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 -/// ODT1][N/A][N/A] +/// @note The Memory Clock Enable MAP is a bit map describing the Memory Clock Enable +/// signal to its respective rank. There are 8 bits, but only 4 are currently used +/// [DIMM0 CKE0][DIMM0 CKE1][N/A][N/A][DIMM1 CKE0][DIMM1 CKE1][N/A][N/A] E.g. 0x80 +/// -> 0b10000000, which means DIMM0 CKE0 is mapped to that +/// rank. /// -inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_cke_map(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -20718,28 +20688,28 @@ inline fapi2::ReturnCode vpd_mt_odt_rd(const fapi2::Target +/// @brief ATTR_MSS_VPD_DQ_MAP getter +/// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (A) +/// @note Generated by gen_accessors.pl generateParameters (G) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT -/// to fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 -/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 -/// ODT1][N/A][N/A] +/// @note [PORT][Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) +/// Pin to the Module Package Data (DQ) +/// Pinout /// -inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_dq_map(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -20747,32 +20717,30 @@ inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target(); - auto l_mcs = l_mca.getParent(); + uint8_t l_value[2][72]; + auto l_mcs = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_WR, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_DQ_MAP, l_mcs, l_value) ); + memcpy(o_array, &(l_value[mss::index(i_target)][0]), 72); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_ODT_WR: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_DQ_MAP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_ODT_WR getter -/// @param[in] const ref to the fapi2::Target +/// @brief ATTR_MSS_VPD_DQ_MAP getter +/// @param[in] const ref to the fapi2::Target /// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (B) +/// @note Generated by gen_accessors.pl generateParameters (H) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT -/// to fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 -/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 -/// ODT1][N/A][N/A] +/// @note [PORT][Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) +/// Pin to the Module Package Data (DQ) +/// Pinout /// -inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode vpd_dq_map(const fapi2::Target& i_target, uint8_t* o_array) { if (o_array == nullptr) { @@ -20780,723 +20748,755 @@ inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target(); + uint8_t l_value[2][72]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_WR, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_DQ_MAP, i_target, l_value) ); + memcpy(o_array, &l_value, 144); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_ODT_WR: 0x%lx (target: %s)", + FAPI_ERR("failed accessing ATTR_MSS_VPD_DQ_MAP: 0x%lx (target: %s)", uint64_t(fapi2::current_err), mss::c_str(i_target)); return fapi2::current_err; } + /// -/// @brief ATTR_MSS_VPD_MT_ODT_WR getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (C) +/// @brief ATTR_MSS_OVERRIDE_MEMDIAGS_BCMODE getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note WRITE, On Die Termination triggering bitmap. Use bitmap to determine which ODT -/// to fire for the designated rank. The bits in 8 bit field are [Dimm0 ODT0][Dimm0 -/// ODT1][N/A][N/A][Dimm1 ODT0][Dimm1 -/// ODT1][N/A][N/A] +/// @note A switch for memdiags broadcast +/// mode /// -inline fapi2::ReturnCode vpd_mt_odt_wr(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode override_memdiags_bcmode(uint8_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][2][4]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_ODT_WR, i_target, l_value) ); - memcpy(o_array, &l_value, 16); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_OVERRIDE_MEMDIAGS_BCMODE, fapi2::Target(), + o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_ODT_WR: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MSS_OVERRIDE_MEMDIAGS_BCMODE: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } + /// -/// @brief ATTR_MSS_VPD_MT_PREAMBLE getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MAX_ALLOWED_DIMM_FREQ getter +/// @param[out] uint32_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Number of clocks used for read/write preamble. Calibration only uses 1 nCK -/// preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. The value -/// of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for -/// READ preamble, and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK -/// preamble for both READ and -/// WRITE +/// @note Maximum frequency (in MHz) that this system can run the DIMMs at. There are 5 +/// possible values determined by the dimm configuration. For configurations which +/// have mixed rank configurations, the lowest frequency based on ranks of either +/// DIMM is chosen. For example if there was a 1R and a 2R DIMM installed, and 1R +/// dual drop was a lower max freq than 2R dual drop, then the 1R max freq would be +/// the max allowed. [0]=One rank, single drop [1]=Two rank, single drop [2]=Four +/// rank, single drop [3]=One rank, dual drop [4]=Two rank, dual drop A value of +/// zero would indicate an unsupported configuration. Note: Do not use this +/// attribute to limit configurations, it is not checked during plug rules. If you +/// have an unsupported configuration, use the value 0 as the maximum +/// freq. /// -inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode max_allowed_dimm_freq(uint32_t* o_array) { - uint8_t l_value[2]; + uint32_t l_value[5]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_PREAMBLE, i_target.getParent(), l_value) ); - o_value = l_value[mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MAX_ALLOWED_DIMM_FREQ, fapi2::Target(), l_value) ); + memcpy(o_array, &l_value, 20); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_PREAMBLE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MAX_ALLOWED_DIMM_FREQ: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_PREAMBLE getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @brief ATTR_REQUIRED_SYNCH_MODE getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Number of clocks used for read/write preamble. Calibration only uses 1 nCK -/// preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. The value -/// of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for -/// READ preamble, and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK -/// preamble for both READ and -/// WRITE +/// @note Specify the system policy to enforce synchronous mode between memory and nest. +/// This drives the value of ATTR_MEM_IN_SYNCH_MODE. UNDETERMINED : Run +/// synchronously if the dimm and nest freq matches ALWAYS : Require matching +/// frequencies and deconfigure memory that does not match the nest NEVER : Do not +/// run synchronously, even if the frequencies +/// match /// -inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode required_synch_mode(uint8_t& o_value) { - uint8_t l_value[2]; - auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_PREAMBLE, l_mca.getParent(), l_value) ); - o_value = l_value[mss::index(l_mca)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_REQUIRED_SYNCH_MODE, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_PREAMBLE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_REQUIRED_SYNCH_MODE: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } + /// -/// @brief ATTR_MSS_VPD_MT_PREAMBLE getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @brief ATTR_IS_SIMULATION getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Number of clocks used for read/write preamble. Calibration only uses 1 nCK -/// preamble (DEFAULT). Mainline has both 1 nCK and 2 nCK preamble option. The value -/// of "0" means 1 nCK preamble, the value of "1" means 2 nCK preamble. Bit 3 for -/// READ preamble, and Bit 7 for WRITE preamble. E.g. 0b00010001 means 2 nCK -/// preamble for both READ and -/// WRITE +/// @note env: 1 = Awan/HWSimulator. 0 = +/// Simics/RealHW. /// -inline fapi2::ReturnCode vpd_mt_preamble(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode is_simulation(uint8_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_PREAMBLE, i_target, l_value) ); - memcpy(o_array, &l_value, 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_PREAMBLE: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_IS_SIMULATION: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_VREF_DRAM_WR getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MNFG_FLAGS getter +/// @param[out] uint64_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DRAM side Write Vref setting for DDR4. Bit encode is 01234567. Bit 0 is unused. -/// Bit 1 is the Range. Bits 2-7 is the Value. Refer to the VrefDQ Training Table in -/// JEDEC. +/// @note The manufacturing flags. This is a bitfield. Each bit is a flag and multiple +/// flags can be +/// set /// -inline fapi2::ReturnCode vpd_mt_vref_dram_wr(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode mnfg_flags(uint64_t& o_value) { - uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_VREF_DRAM_WR, i_target.getParent(), l_value) ); - o_value = l_value[mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MNFG_FLAGS, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_VREF_DRAM_WR: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MNFG_FLAGS: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } + /// -/// @brief ATTR_MSS_VPD_MT_VREF_DRAM_WR getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint8_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @brief ATTR_FREQ_PB_MHZ getter +/// @param[out] uint32_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DRAM side Write Vref setting for DDR4. Bit encode is 01234567. Bit 0 is unused. -/// Bit 1 is the Range. Bits 2-7 is the Value. Refer to the VrefDQ Training Table in -/// JEDEC. +/// @note The frequency of a processor's nest mesh clock, in MHz. This is the same for all +/// chips in the system. Provided by the +/// MRW. /// -inline fapi2::ReturnCode vpd_mt_vref_dram_wr(const fapi2::Target& i_target, uint8_t& o_value) +inline fapi2::ReturnCode freq_pb_mhz(uint32_t& o_value) { - uint8_t l_value[2]; - auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_VREF_DRAM_WR, l_mca.getParent(), l_value) ); - o_value = l_value[mss::index(l_mca)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_PB_MHZ, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_VREF_DRAM_WR: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_FREQ_PB_MHZ: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } + /// -/// @brief ATTR_MSS_VPD_MT_VREF_DRAM_WR getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @brief ATTR_MEM_MRW_IS_PLANAR getter +/// @param[in] const ref to the TARGET_TYPE_OCMB_CHIP +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (PROC_CHIP) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note DRAM side Write Vref setting for DDR4. Bit encode is 01234567. Bit 0 is unused. -/// Bit 1 is the Range. Bits 2-7 is the Value. Refer to the VrefDQ Training Table in -/// JEDEC. +/// @note Indicates if the DIMM connected to this controller are in a planar +/// configuration /// -inline fapi2::ReturnCode vpd_mt_vref_dram_wr(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode mem_mrw_is_planar(const fapi2::Target& i_target, + uint8_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_VREF_DRAM_WR, i_target, l_value) ); - memcpy(o_array, &l_value, 2); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_MRW_IS_PLANAR, i_target, o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_VREF_DRAM_WR: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MEM_MRW_IS_PLANAR: 0x%lx", + uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_VREF_MC_RD getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint32_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT getter +/// @param[out] uint16_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Read Vref setting. Dividing by 1000 gives you percentage -/// of -/// Vdd +/// @note Machine Readable Workbook safe mode throttle value for numerator +/// cfg_nm_n_per_port Set to below optimum value/ rate. On a per port basis Also +/// used for emergency mode throttle FARB4Q_EMERGENCY_N Used to thermally protect +/// the system in all supported environmental conditions when OCC is not functional +/// Consumer: thermal_init, +/// initfile /// -inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target& i_target, uint32_t& o_value) +inline fapi2::ReturnCode mrw_safemode_mem_throttled_n_commands_per_port(uint16_t& o_value) { - uint32_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_VREF_MC_RD, i_target.getParent(), l_value) ); - o_value = l_value[mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT, + fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_VREF_MC_RD: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_VREF_MC_RD getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value uint32_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @brief ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT getter +/// @param[out] uint64_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Read Vref setting. Dividing by 1000 gives you percentage -/// of -/// Vdd +/// @note Machine Readable Workbook Thermal Memory Power Limit Used to calculate throttles +/// to be at or under the power limit Per DIMM basis KEY (0-19): In order DIMM_SIZE +/// = bits 0-3, DIMM_GEN = 4-5, DIMM_TYPE = 6-7, DIMM_WIDTH = 8-10, DIMM_DENSITY = +/// 11-13, DIMM_STACK_TYPE = 14-15, DRAM_MFGID = 16-18, DIMMS_PER_PORT = 19-20, Bits +/// 21-32: Not used VALUE (bits 32-63) in cW: VMEM+VPP thermal power limit per DIMM +/// = 32-63 Consumers: eff_config_thermal and +/// bulk_pwr_throttles /// -inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target& i_target, uint32_t& o_value) +inline fapi2::ReturnCode mrw_thermal_memory_power_limit(uint64_t* o_array) { - uint32_t l_value[2]; - auto l_mca = i_target.getParent(); + uint64_t l_value[10]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_VREF_MC_RD, l_mca.getParent(), l_value) ); - o_value = l_value[mss::index(l_mca)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT, fapi2::Target(), + l_value) ); + memcpy(o_array, &l_value, 80); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_VREF_MC_RD: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_VREF_MC_RD getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint32_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @brief ATTR_MSS_MRW_PWR_INTERCEPT getter +/// @param[out] uint64_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory Controller side Read Vref setting. Dividing by 1000 gives you percentage -/// of -/// Vdd +/// @note Machine Readable Workbook Power Curve Intercept for DIMM Used to get the VDDR +/// and VDDR+VPP power curve for each DIMM Decoded and used to set +/// ATTR_MSS_TOTAL_PWR_INTERCEPT Key Value pair KEY (0-19): In order DIMM_SIZE = +/// bits 0-3, DIMM_GEN = 4-5, DIMM_TYPE = 6-7, DIMM_WIDTH = 8-10, DIMM_DENSITY = +/// 11-13, DIMM_STACK_TYPE = 14-15, DRAM_MFGID = 16-18, DIMMS_PER_PORT = 19-20, Bits +/// 21-32: Not used VALUE (bits 32-63) in cW: VMEM power curve = 32-47 VMEM+VPP +/// power curve = 48-63 Consumers: +/// eff_config_thermal /// -inline fapi2::ReturnCode vpd_mt_vref_mc_rd(const fapi2::Target& i_target, uint32_t* o_array) +inline fapi2::ReturnCode mrw_pwr_intercept(uint64_t* o_array) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } + uint64_t l_value[100]; - uint32_t l_value[2]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_PWR_INTERCEPT, fapi2::Target(), l_value) ); + memcpy(o_array, &l_value, 800); + return fapi2::current_err; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_VREF_MC_RD, i_target, l_value) ); - memcpy(o_array, &l_value, 8); +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_PWR_INTERCEPT: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MRW_PWR_SLOPE getter +/// @param[out] uint64_t* memory to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Machine Readable Workbook Power Curve Slope for DIMM Used to get the VDDR and +/// VDDR+VPP power curve for each DIMM Decoded and used to set +/// ATTR_MSS_TOTAL_PWR_INTERCEPT Key Value pair KEY (0-19): In order DIMM_SIZE = +/// bits 0-3, DIMM_GEN = 4-5, DIMM_TYPE = 6-7, DIMM_WIDTH = 8-10, DIMM_DENSITY = +/// 11-13, DIMM_STACK_TYPE = 14-15, DRAM_MFGID = 16-18, DIMMS_PER_PORT = 19-20, Bits +/// 21-32: Not used VALUE (bits 32-63) in cW: VMEM power curve = 32-47 VMEM+VPP +/// power curve = 48-63 Consumers: +/// eff_config_thermal +/// +inline fapi2::ReturnCode mrw_pwr_slope(uint64_t* o_array) +{ + uint64_t l_value[100]; + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_PWR_SLOPE, fapi2::Target(), l_value) ); + memcpy(o_array, &l_value, 800); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_VREF_MC_RD: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_PWR_SLOPE: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_WINDAGE_RD_CTR getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value int16_t -/// @note Generated by gen_accessors.pl generateParameters (D) +/// @brief ATTR_MSS_MRW_REFRESH_RATE_REQUEST getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Derived from calibration/characterization of read centering. Number of windage -/// offset in units of pico-seconds[ps]. Default is 0 Specification of the value in -/// this file is 2's compliment -/// hex +/// @note Machine Readable Workbook Refresh Rate Desired refresh interval used in refresh +/// register 0, MBAREF0Q_CFG_REFRESH_INTERVAL 7.8 us (SINGLE) 3.9 us (DOUBLE) 7.02 +/// us (SINGLE_10_PERCENT_FASTER) 3.51 us +/// (DOUBLE_10_PERCENT_FASTER) /// -inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target& i_target, int16_t& o_value) +inline fapi2::ReturnCode mrw_refresh_rate_request(uint8_t& o_value) { - int16_t l_value[2]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_WINDAGE_RD_CTR, i_target.getParent(), l_value) ); - o_value = l_value[mss::index(i_target)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_REFRESH_RATE_REQUEST, fapi2::Target(), + o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_WINDAGE_RD_CTR: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_REFRESH_RATE_REQUEST: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_WINDAGE_RD_CTR getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] ref to the value int16_t -/// @note Generated by gen_accessors.pl generateParameters (D.1) +/// @brief ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Derived from calibration/characterization of read centering. Number of windage -/// offset in units of pico-seconds[ps]. Default is 0 Specification of the value in -/// this file is 2's compliment -/// hex +/// @note Machine Readable Workbook DIMM power curve percent uplift for this system at max +/// utilization. Value should be 0 for +/// ISDIMMs /// -inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target& i_target, int16_t& o_value) +inline fapi2::ReturnCode mrw_dimm_power_curve_percent_uplift(uint8_t& o_value) { - int16_t l_value[2]; - auto l_mca = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_WINDAGE_RD_CTR, l_mca.getParent(), l_value) ); - o_value = l_value[mss::index(l_mca)]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT, fapi2::Target(), + o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_WINDAGE_RD_CTR: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_MT_WINDAGE_RD_CTR getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] int16_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (E) +/// @brief ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Derived from calibration/characterization of read centering. Number of windage -/// offset in units of pico-seconds[ps]. Default is 0 Specification of the value in -/// this file is 2's compliment -/// hex +/// @note Machine Readable Workbook DIMM power curve percent uplift for this system at +/// idle utilization. Value should be 0 for +/// ISDIMMs /// -inline fapi2::ReturnCode vpd_mt_windage_rd_ctr(const fapi2::Target& i_target, int16_t* o_array) +inline fapi2::ReturnCode mrw_dimm_power_curve_percent_uplift_idle(uint8_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - int16_t l_value[2]; + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE, + fapi2::Target(), o_value) ); + return fapi2::current_err; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_MT_WINDAGE_RD_CTR, i_target, l_value) ); - memcpy(o_array, &l_value, 4); +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS getter +/// @param[out] uint32_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Machine Readable Workbook for the number of M DRAM clocks. One approach to +/// curbing DRAM power usage is by throttling traffic through a programmable N +/// commands over M +/// window. +/// +inline fapi2::ReturnCode mrw_mem_m_dram_clocks(uint32_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_MT_WINDAGE_RD_CTR: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } +/// +/// @brief ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL getter +/// @param[out] uint32_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Machine Readable Workbook value for maximum dram data bus utilization in centi +/// percent (c%). Used to determine memory throttle values. Max databus utilization +/// on a per port basis Default to +/// 90% +/// +inline fapi2::ReturnCode mrw_max_dram_databus_util(uint32_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL, fapi2::Target(), + o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} /// -/// @brief ATTR_MSS_VPD_CKE_MAP getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (A) +/// @brief ATTR_MSS_MRW_POWER_CONTROL_REQUESTED getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note The Memory Clock Enable MAP is a bit map describing the Memory Clock Enable -/// signal to its respective rank. There are 8 bits, but only 4 are currently used -/// [DIMM0 CKE0][DIMM0 CKE1][N/A][N/A][DIMM1 CKE0][DIMM1 CKE1][N/A][N/A] E.g. 0x80 -/// -> 0b10000000, which means DIMM0 CKE0 is mapped to that -/// rank. +/// @note Memory power control settings programmed during IPL Used by OCC when exiting +/// idle power-save +/// mode /// -inline fapi2::ReturnCode vpd_cke_map(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode mrw_power_control_requested(uint8_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - uint8_t l_value[2][2][4]; - auto l_mca = i_target.getParent(); - auto l_mcs = l_mca.getParent(); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target(), + o_value) ); + return fapi2::current_err; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_CKE_MAP, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(l_mca)][mss::index(i_target)][0]), 4); +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_POWER_CONTROL_REQUESTED: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Memory power control settings for IDLE powersave mode Used by OCC when entering +/// idle power-save +/// mode +/// +inline fapi2::ReturnCode mrw_idle_power_control_requested(uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED, fapi2::Target(), + o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_CKE_MAP: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_CKE_MAP getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (B) +/// @brief ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4 getter +/// @param[out] uint32_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note The Memory Clock Enable MAP is a bit map describing the Memory Clock Enable -/// signal to its respective rank. There are 8 bits, but only 4 are currently used -/// [DIMM0 CKE0][DIMM0 CKE1][N/A][N/A][DIMM1 CKE0][DIMM1 CKE1][N/A][N/A] E.g. 0x80 -/// -> 0b10000000, which means DIMM0 CKE0 is mapped to that -/// rank. +/// @note Machine Readable Workbook VMEM regulator power limit per DIMM assuming a full +/// configuration. Units in cW Consumed in +/// mss_eff_config_thermal /// -inline fapi2::ReturnCode vpd_cke_map(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode mrw_vmem_regulator_power_limit_per_dimm_ddr4(uint32_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - uint8_t l_value[2][2][4]; - auto l_mcs = i_target.getParent(); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4, + fapi2::Target(), o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Machine Readable Workbook value for the maximum possible number of dimms that +/// can be installed under any of the VMEM regulators. Consumed in +/// eff_config_thermal to calculate +/// mem_watt_target +/// +inline fapi2::ReturnCode mrw_max_number_dimms_possible_per_vmem_regulator(uint8_t& o_value) +{ + + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR, + fapi2::Target(), o_value) ); + return fapi2::current_err; + +fapi_try_exit: + FAPI_ERR("failed accessing ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR: 0x%lx (system target)", + uint64_t(fapi2::current_err)); + return fapi2::current_err; +} + +/// +/// @brief ATTR_MSS_MRW_FINE_REFRESH_MODE getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) +/// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK +/// @note Fine refresh mode. Sets DDR4 MRS3. ZZ uses normal mode. From JEDEC DDR4 Spec +/// 1716.78C from 07-2016 Page 47 Table +/// 4.9.1 +/// +inline fapi2::ReturnCode mrw_fine_refresh_mode(uint8_t& o_value) +{ - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_CKE_MAP, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 8); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_FINE_REFRESH_MODE, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_CKE_MAP: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_FINE_REFRESH_MODE: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_CKE_MAP getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (C) +/// @brief ATTR_MSS_MRW_TEMP_REFRESH_RANGE getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note The Memory Clock Enable MAP is a bit map describing the Memory Clock Enable -/// signal to its respective rank. There are 8 bits, but only 4 are currently used -/// [DIMM0 CKE0][DIMM0 CKE1][N/A][N/A][DIMM1 CKE0][DIMM1 CKE1][N/A][N/A] E.g. 0x80 -/// -> 0b10000000, which means DIMM0 CKE0 is mapped to that -/// rank. +/// @note Temperature refresh range. Sets DDR4 MRS4. Should be defaulted to extended +/// range. NORMAL for running at 85 degrees C or less, EXTENDED for 95 or less +/// degrees C Used for calculating periodic refresh intervals JEDEC DDR4 spec +/// 1716.78C from 07-2016 page 46 +/// 4.8.1 /// -inline fapi2::ReturnCode vpd_cke_map(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode mrw_temp_refresh_range(uint8_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - uint8_t l_value[2][2][4]; - - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_CKE_MAP, i_target, l_value) ); - memcpy(o_array, &l_value, 16); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_TEMP_REFRESH_RANGE, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_CKE_MAP: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_TEMP_REFRESH_RANGE: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } - /// -/// @brief ATTR_MSS_VPD_DQ_MAP getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (G) +/// @brief ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note [PORT][Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) -/// Pin to the Module Package Data (DQ) -/// Pinout +/// @note For resetting the phy delay values at the beginning of calling +/// mss_draminit_training. YES means the vaules will be +/// reset. /// -inline fapi2::ReturnCode vpd_dq_map(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode mrw_reset_delay_before_cal(uint8_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][72]; - auto l_mcs = i_target.getParent(); - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_DQ_MAP, l_mcs, l_value) ); - memcpy(o_array, &(l_value[mss::index(i_target)][0]), 72); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL, fapi2::Target(), + o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_DQ_MAP: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_VPD_DQ_MAP getter -/// @param[in] const ref to the fapi2::Target -/// @param[out] uint8_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (H) +/// @brief ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS getter +/// @param[out] uint16_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note [PORT][Dimm DQ PIN] The map from the Dual Inline Memory Module (DIMM) Data (DQ) -/// Pin to the Module Package Data (DQ) -/// Pinout +/// @note Describes the settings for periodic calibration for all ports: Reading left to +/// right. (DEFAULT: 0xD90C -> Byte 0(11011001), Byte 1(00001100)) For each bit: OFF +/// = 0, ON = 1. Setting to 0 indicates to disable periodic memcal. Byte 0: 0: ZCAL +/// 1: SYSCK_ALIGN 2: RDCENTERING 3: RDLCK_ALIGN 4: DQS_ALIGN 5: RDCLK_UPDATE 6: +/// PER_DUTYCYCLE 7: PERCAL_PWR_DIS Byte 1: 0: PERCAL_REPEAT 1: PERCAL_REPEAT 2: +/// PERCAL_REPEAT 3: SINGLE_BIT_MPR 4: MBA_CFG_0 5: MBA_CFG_1 6: SPARE 7: +/// SPARE /// -inline fapi2::ReturnCode vpd_dq_map(const fapi2::Target& i_target, uint8_t* o_array) +inline fapi2::ReturnCode mrw_periodic_memcal_mode_options(uint16_t& o_value) { - if (o_array == nullptr) - { - FAPI_ERR("nullptr passed to attribute accessor %s", __func__); - return fapi2::FAPI2_RC_INVALID_PARAMETER; - } - - uint8_t l_value[2][72]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_VPD_DQ_MAP, i_target, l_value) ); - memcpy(o_array, &l_value, 144); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS, fapi2::Target(), + o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_VPD_DQ_MAP: 0x%lx (target: %s)", - uint64_t(fapi2::current_err), mss::c_str(i_target)); + FAPI_ERR("failed accessing ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS: 0x%lx (system target)", + uint64_t(fapi2::current_err)); return fapi2::current_err; } - /// -/// @brief ATTR_MSS_OVERRIDE_MEMDIAGS_BCMODE getter -/// @param[out] uint8_t& reference to store the value +/// @brief ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS getter +/// @param[out] uint16_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note A switch for memdiags broadcast -/// mode +/// @note Describes the settings for periodic ZQ calibration for all ports: Reading left +/// to right. For each bit: OFF = 0, ON = 1. Setting to 0 indicates to disable +/// periodic zqcal. Byte 0: 0: ZQCAL All others reserved for future +/// use /// -inline fapi2::ReturnCode override_memdiags_bcmode(uint8_t& o_value) +inline fapi2::ReturnCode mrw_periodic_zqcal_mode_options(uint16_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_OVERRIDE_MEMDIAGS_BCMODE, fapi2::Target(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_OVERRIDE_MEMDIAGS_BCMODE: 0x%lx (system target)", + FAPI_ERR("failed accessing ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } - /// -/// @brief ATTR_MAX_ALLOWED_DIMM_FREQ getter -/// @param[out] uint32_t* memory to store the value -/// @note Generated by gen_accessors.pl generateParameters (SYSTEM A) +/// @brief ATTR_MSS_MRW_DRAM_2N_MODE getter +/// @param[out] uint8_t& reference to store the value +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Maximum frequency (in MHz) that this system can run the DIMMs at. There are 5 -/// possible values determined by the dimm configuration. For configurations which -/// have mixed rank configurations, the lowest frequency based on ranks of either -/// DIMM is chosen. For example if there was a 1R and a 2R DIMM installed, and 1R -/// dual drop was a lower max freq than 2R dual drop, then the 1R max freq would be -/// the max allowed. [0]=One rank, single drop [1]=Two rank, single drop [2]=Four -/// rank, single drop [3]=One rank, dual drop [4]=Two rank, dual drop A value of -/// zero would indicate an unsupported configuration. Note: Do not use this -/// attribute to limit configurations, it is not checked during plug rules. If you -/// have an unsupported configuration, use the value 0 as the maximum -/// freq. +/// @note Allows user to manually turn on and off 2N Mode. AUTO indicates to use Signal +/// Integrity generated setting (from +/// VPD). /// -inline fapi2::ReturnCode max_allowed_dimm_freq(uint32_t* o_array) +inline fapi2::ReturnCode mrw_dram_2n_mode(uint8_t& o_value) { - uint32_t l_value[5]; - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MAX_ALLOWED_DIMM_FREQ, fapi2::Target(), l_value) ); - memcpy(o_array, &l_value, 20); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DRAM_2N_MODE, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MAX_ALLOWED_DIMM_FREQ: 0x%lx (system target)", + FAPI_ERR("failed accessing ATTR_MSS_MRW_DRAM_2N_MODE: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_REQUIRED_SYNCH_MODE getter +/// @brief ATTR_MSS_MRW_DRAM_WRITE_CRC getter /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Specify the system policy to enforce synchronous mode between memory and nest. -/// This drives the value of ATTR_MEM_IN_SYNCH_MODE. UNDETERMINED : Run -/// synchronously if the dimm and nest freq matches ALWAYS : Require matching -/// frequencies and deconfigure memory that does not match the nest NEVER : Do not -/// run synchronously, even if the frequencies -/// match +/// @note Enables DRAM Write +/// CRC /// -inline fapi2::ReturnCode required_synch_mode(uint8_t& o_value) +inline fapi2::ReturnCode mrw_dram_write_crc(uint8_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_REQUIRED_SYNCH_MODE, fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_DRAM_WRITE_CRC, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_REQUIRED_SYNCH_MODE: 0x%lx (system target)", + FAPI_ERR("failed accessing ATTR_MSS_MRW_DRAM_WRITE_CRC: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } - /// -/// @brief ATTR_IS_SIMULATION getter +/// @brief ATTR_MSS_MRW_TEMP_REFRESH_MODE getter /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note env: 1 = Awan/HWSimulator. 0 = -/// Simics/RealHW. +/// @note Used in MR4 A3 Temperature refresh mode Should be defaulted to +/// disable /// -inline fapi2::ReturnCode is_simulation(uint8_t& o_value) +inline fapi2::ReturnCode mrw_temp_refresh_mode(uint8_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_IS_SIMULATION, fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_TEMP_REFRESH_MODE, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_IS_SIMULATION: 0x%lx (system target)", + FAPI_ERR("failed accessing ATTR_MSS_MRW_TEMP_REFRESH_MODE: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MNFG_FLAGS getter -/// @param[out] uint64_t& reference to store the value +/// @brief ATTR_MSS_MRW_FORCE_BCMODE_OFF getter +/// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note The manufacturing flags. This is a bitfield. Each bit is a flag and multiple -/// flags can be -/// set +/// @note An override switch to shut off broadcast mode Enum values: YES: broadcast mode +/// is forced off NO: broadcast mode uses the default +/// value /// -inline fapi2::ReturnCode mnfg_flags(uint64_t& o_value) +inline fapi2::ReturnCode mrw_force_bcmode_off(uint8_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MNFG_FLAGS, fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_FORCE_BCMODE_OFF, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MNFG_FLAGS: 0x%lx (system target)", + FAPI_ERR("failed accessing ATTR_MSS_MRW_FORCE_BCMODE_OFF: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } - /// -/// @brief ATTR_FREQ_PB_MHZ getter -/// @param[out] uint32_t& reference to store the value +/// @brief ATTR_MSS_MRW_NVDIMM_PLUG_RULES getter +/// @param[out] uint64_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note The frequency of a processor's nest mesh clock, in MHz. This is the same for all -/// chips in the system. Provided by the -/// MRW. +/// @note A bitmap containing the plug rules for NVDIMM. 1 if a DIMM supports an NVDIMM +/// being plugged in, 0 if it does not DIMM slot 0 is the left most bit The index to +/// the bitmap is the position of the DIMM target As such, a bitmap of 0b10010000, +/// would allow NVDIMM plugged into DIMM0 and DIMM3 Note: this attribute is a 64 bit +/// number to account for 16 DIMM per processor if there is ever a 4 processor +/// system /// -inline fapi2::ReturnCode freq_pb_mhz(uint32_t& o_value) +inline fapi2::ReturnCode mrw_nvdimm_plug_rules(uint64_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_FREQ_PB_MHZ, fapi2::Target(), o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_NVDIMM_PLUG_RULES, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_FREQ_PB_MHZ: 0x%lx (system target)", + FAPI_ERR("failed accessing ATTR_MSS_MRW_NVDIMM_PLUG_RULES: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } - /// -/// @brief ATTR_MEM_MRW_IS_PLANAR getter -/// @param[in] const ref to the TARGET_TYPE_OCMB_CHIP +/// @brief ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW getter /// @param[out] uint8_t& reference to store the value -/// @note Generated by gen_accessors.pl generateParameters (PROC_CHIP) +/// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Indicates if the DIMM connected to this controller are in a planar -/// configuration +/// @note Switch that allows unsupported raw card references by providing a default raw +/// card +/// setting. /// -inline fapi2::ReturnCode mem_mrw_is_planar(const fapi2::Target& i_target, - uint8_t& o_value) +inline fapi2::ReturnCode mrw_allow_unsupported_rcw(uint8_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MEM_MRW_IS_PLANAR, i_target, o_value) ); + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW, fapi2::Target(), + o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MEM_MRW_IS_PLANAR: 0x%lx", + FAPI_ERR("failed accessing ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } /// -/// @brief ATTR_MSS_MRW_POWER_CONTROL_REQUESTED getter +/// @brief ATTR_MSS_MRW_SUPPORTED_DRAM_WIDTH getter /// @param[out] uint8_t& reference to store the value /// @note Generated by gen_accessors.pl generateParameters (SYSTEM) /// @return fapi2::ReturnCode - FAPI2_RC_SUCCESS iff get is OK -/// @note Memory power control settings programmed during IPL Used by OCC when exiting -/// idle power-save -/// mode +/// @note Bitmap of DRAM widths supported by a system. A 1 indicates that the system +/// supports a density. Enums below represent the the bit location in the attribute +/// for a given DRAM width. Default value is 0xC -> both x4/x8 +/// supported /// -inline fapi2::ReturnCode mrw_power_control_requested(uint8_t& o_value) +inline fapi2::ReturnCode mrw_supported_dram_width(uint8_t& o_value) { - FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_POWER_CONTROL_REQUESTED, fapi2::Target(), + FAPI_TRY( FAPI_ATTR_GET(fapi2::ATTR_MSS_MRW_SUPPORTED_DRAM_WIDTH, fapi2::Target(), o_value) ); return fapi2::current_err; fapi_try_exit: - FAPI_ERR("failed accessing ATTR_MSS_MRW_POWER_CONTROL_REQUESTED: 0x%lx (system target)", + FAPI_ERR("failed accessing ATTR_MSS_MRW_SUPPORTED_DRAM_WIDTH: 0x%lx (system target)", uint64_t(fapi2::current_err)); return fapi2::current_err; } diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml index b4ab25916..078f79284 100755 --- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mrw_attributes.xml @@ -25,510 +25,6 @@ - - ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT - TARGET_TYPE_SYSTEM - - Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_port - Set to below optimum value/ rate. - On a per port (MCA) basis - Also used for emergency mode throttle MBA_FARB4Q_EMERGENCY_N - Used to thermally protect the system in all supported environmental conditions when OCC is not functional - Consumer: thermal_init, initfile - - uint16 - 32 - - - - mrw_safemode_mem_throttled_n_commands_per_port - - - - ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT - TARGET_TYPE_SYSTEM - - Machine Readable Workbook Thermal Memory Power Limit - Used to calculate throttles to be at or under the power limit - Per DIMM basis - KEY (0-19): In order - DIMM_SIZE = bits 0-3, - DIMM_GEN = 4-5, - DIMM_TYPE = 6-7, - DIMM_WIDTH = 8-10, - DIMM_DENSITY = 11-13, - DIMM_STACK_TYPE = 14-15, - DRAM_MFGID = 16-18, - DIMMS_PER_PORT = 19-20, - Bits 21-32: Not used - VALUE (bits 32-63) in cW: - VMEM+VPP thermal power limit per DIMM = 32-63 - Consumers: eff_config_thermal and bulk_pwr_throttles - - uint64 - cW - 0xfffff80000000794 - 10 - - - - mrw_thermal_memory_power_limit - - - - ATTR_MSS_MRW_PWR_INTERCEPT - TARGET_TYPE_SYSTEM - - Machine Readable Workbook Power Curve Intercept for DIMM - Used to get the VDDR and VDDR+VPP power curve for each DIMM - Decoded and used to set ATTR_MSS_TOTAL_PWR_INTERCEPT - Key Value pair - KEY (0-19): In order - DIMM_SIZE = bits 0-3, - DIMM_GEN = 4-5, - DIMM_TYPE = 6-7, - DIMM_WIDTH = 8-10, - DIMM_DENSITY = 11-13, - DIMM_STACK_TYPE = 14-15, - DRAM_MFGID = 16-18, - DIMMS_PER_PORT = 19-20, - Bits 21-32: Not used - VALUE (bits 32-63) in cW: - VMEM power curve = 32-47 - VMEM+VPP power curve = 48-63 - Consumers: eff_config_thermal - - uint64 - - - 100 - 0xfffff8000384044C - mrw_pwr_intercept - - - - ATTR_MSS_MRW_PWR_SLOPE - TARGET_TYPE_SYSTEM - - Machine Readable Workbook Power Curve Slope for DIMM - Used to get the VDDR and VDDR+VPP power curve for each DIMM - Decoded and used to set ATTR_MSS_TOTAL_PWR_INTERCEPT - Key Value pair - KEY (0-19): In order - DIMM_SIZE = bits 0-3, - DIMM_GEN = 4-5, - DIMM_TYPE = 6-7, - DIMM_WIDTH = 8-10, - DIMM_DENSITY = 11-13, - DIMM_STACK_TYPE = 14-15, - DRAM_MFGID = 16-18, - DIMMS_PER_PORT = 19-20, - Bits 21-32: Not used - VALUE (bits 32-63) in cW: - VMEM power curve = 32-47 - VMEM+VPP power curve = 48-63 - Consumers: eff_config_thermal - - uint64 - - - 100 - 0xfffff800041A044C - mrw_pwr_slope - - - - ATTR_MSS_MRW_REFRESH_RATE_REQUEST - TARGET_TYPE_SYSTEM - - Machine Readable Workbook Refresh Rate - Desired refresh interval used in refresh register 0, MBAREF0Q_CFG_REFRESH_INTERVAL - 7.8 us (SINGLE) - 3.9 us (DOUBLE) - 7.02 us (SINGLE_10_PERCENT_FASTER) - 3.51 us (DOUBLE_10_PERCENT_FASTER) - - uint8 - - - DOUBLE=0, - SINGLE=1, - SINGLE_10_PERCENT_FASTER=2, - DOUBLE_10_PERCENT_FASTER=3 - - 0x0 - - mrw_refresh_rate_request - - - - ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT - TARGET_TYPE_SYSTEM - - Machine Readable Workbook DIMM power curve percent uplift - for this system at max utilization. - Value should be 0 for ISDIMMs - - uint8 - - 0x0 - - mrw_dimm_power_curve_percent_uplift - - - - ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE - TARGET_TYPE_SYSTEM - - Machine Readable Workbook DIMM power curve percent uplift - for this system at idle utilization. - Value should be 0 for ISDIMMs - - uint8 - - 0x0 - - - mrw_dimm_power_curve_percent_uplift_idle - - - - ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS - TARGET_TYPE_SYSTEM - - Machine Readable Workbook for the number of M DRAM clocks. - One approach to curbing DRAM power usage is by throttling - traffic through a programmable N commands over M window. - - uint32 - - 0x00000200 - - mrw_mem_m_dram_clocks - - - - ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL - TARGET_TYPE_SYSTEM - - Machine Readable Workbook value for maximum dram data bus utilization in centi percent (c%). - Used to determine memory throttle values. - Max databus utilization on a per port basis - Default to 90% - - uint32 - - c% - 0x00002328 - - mrw_max_dram_databus_util - - - - ATTR_MSS_MRW_MCS_PREFETCH_RETRY_THRESHOLD - TARGET_TYPE_SYSTEM - - Option to control MCS prefetch retry threshold, for performance optimization. - This attribute controls the number of retries in the prefetch engine. - Retry threshold available ranges from 16 to 30. - Note: Values outside those ranges will default to 30. - In MRW. - - uint8 - - - - - - - - ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED - TARGET_TYPE_SYSTEM - - Memory power control settings for IDLE powersave mode - Used by OCC when entering idle power-save mode - - uint8 - OFF = 0x00, POWER_DOWN = 0x01, PD_AND_STR = 0x02, PD_AND_STR_CLK_STOP = 0x03 - - OFF - - mrw_idle_power_control_requested - - - - ATTR_MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE - TARGET_TYPE_SYSTEM - - Machine Readable Workbook enablement of the HWP code to adjust the - VMEM regulator power limit based on number of installed DIMMs. - - uint8 - FALSE = 0, TRUE = 1 - - - - - - - ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR3 - TARGET_TYPE_SYSTEM - - Machine Readable Workbook VMEM regulator power limit per CDIMM assuming a full configuration. Units in cW - Used for Cumulus - Consumed in mss_eff_config_thermal - - uint32 - - cW - - - - - - ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4 - TARGET_TYPE_SYSTEM - - Machine Readable Workbook VMEM regulator power limit per DIMM assuming a full configuration. Units in cW - Consumed in mss_eff_config_thermal - - uint32 - - cW - 0x000006A4 - - - mrw_vmem_regulator_power_limit_per_dimm_ddr4 - - - - ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR - TARGET_TYPE_SYSTEM - - Machine Readable Workbook value for the maximum possible number - of dimms that can be installed under any of the VMEM regulators. - Consumed in eff_config_thermal to calculate mem_watt_target - - uint8 - - - - mrw_max_number_dimms_possible_per_vmem_regulator - - - - ATTR_MSS_MRW_AVDD_OFFSET_ENABLE - TARGET_TYPE_SYSTEM - Used for to determine whether to apply an offset to AVDD. Supplied by MRW. - uint8 - ENABLE = 1, DISABLE = 0 - - - - - - - ATTR_MSS_MRW_VDD_OFFSET_ENABLE - TARGET_TYPE_SYSTEM - Used for to determine whether to apply an offset to VDD. Supplied by MRW. - uint8 - ENABLE = 1, DISABLE = 0 - - - - - - - ATTR_MSS_MRW_VCS_OFFSET_ENABLE - TARGET_TYPE_SYSTEM - Used for to determine whether to apply an offset to VCS. Supplied by MRW. - uint8 - ENABLE = 1, DISABLE = 0 - - - - - - - ATTR_MSS_MRW_VPP_OFFSET_ENABLE - TARGET_TYPE_SYSTEM - Used for to determine whether to apply an offset to VCS. Supplied by MRW. - uint8 - ENABLE = 1, DISABLE = 0 - - - - - - - ATTR_MSS_MRW_VDDR_OFFSET_ENABLE - TARGET_TYPE_SYSTEM - Used for to determine whether to apply an offset to VDDR. Supplied by MRW. - uint8 - ENABLE = 1, DISABLE = 0 - - - - - - - ATTR_MSS_MRW_FINE_REFRESH_MODE - TARGET_TYPE_SYSTEM - - Fine refresh mode. - Sets DDR4 MRS3. - ZZ uses normal mode. - From JEDEC DDR4 Spec 1716.78C from 07-2016 - Page 47 Table 4.9.1 - - uint8 - - NORMAL = 0, - FIXED_2X = 1, - FIXED_4X = 2, - FLY_2X = 5, - FLY_4X = 6 - - - - NORMAL - mrw_fine_refresh_mode - - - - ATTR_MSS_MRW_TEMP_REFRESH_RANGE - TARGET_TYPE_SYSTEM - - Temperature refresh range. - Sets DDR4 MRS4. - Should be defaulted to extended range. - NORMAL for running at 85 degrees C or less, EXTENDED for 95 or less degrees C - Used for calculating periodic refresh intervals - JEDEC DDR4 spec 1716.78C from 07-2016 - page 46 4.8.1 - - uint8 - NORMAL = 0, EXTEND = 1 - - - EXTEND - mrw_temp_refresh_range - - - - ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL - TARGET_TYPE_SYSTEM - For resetting the phy delay values at the beginning of calling mss_draminit_training. YES means the vaules will be reset. - uint8 - YES = 0, NO = 1 - YES - - - - mrw_reset_delay_before_cal - - - - ATTR_MSS_MRW_PREFETCH_ENABLE - TARGET_TYPE_SYSTEM - Value of on or off. Determines if prefetching enabled or not. - uint8 - ON = 1, OFF = 0 - - - ON - - - - - - ATTR_MSS_MRW_CLEANER_ENABLE - TARGET_TYPE_SYSTEM - - Value of on or off. - Determines if the cleaner of the L4 cache (write modified entries to memory on idle cycles) - enabled or not. See chapter 7 of the Centaur Workbook. - - uint8 - OFF = 0, ON = 1 - - - OFF - - - - - - ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS - TARGET_TYPE_SYSTEM - - Describes the settings for periodic calibration for all ports: - Reading left to right. (DEFAULT: 0xD90C -> Byte 0(11011001), Byte 1(00001100)) - For each bit: OFF = 0, ON = 1. Setting to 0 indicates to disable periodic memcal. - Byte 0: - 0: ZCAL - 1: SYSCK_ALIGN - 2: RDCENTERING - 3: RDLCK_ALIGN - 4: DQS_ALIGN - 5: RDCLK_UPDATE - 6: PER_DUTYCYCLE - 7: PERCAL_PWR_DIS - - Byte 1: - 0: PERCAL_REPEAT - 1: PERCAL_REPEAT - 2: PERCAL_REPEAT - 3: SINGLE_BIT_MPR - 4: MBA_CFG_0 - 5: MBA_CFG_1 - 6: SPARE - 7: SPARE - - uint16 - encoded settings for periodic calibration - - 0xD90C - - mrw_periodic_memcal_mode_options - - - - ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS - TARGET_TYPE_SYSTEM - - Describes the settings for periodic ZQ calibration for all ports: - Reading left to right. For each bit: OFF = 0, ON = 1. - Setting to 0 indicates to disable periodic zqcal. - Byte 0: - 0: ZQCAL - All others reserved for future use - - uint16 - encoded settings for periodic calibration - - 0x8000 - - mrw_periodic_zqcal_mode_options - - - - ATTR_MSS_MRW_DRAM_2N_MODE - TARGET_TYPE_SYSTEM - - Allows user to manually turn on and off 2N Mode. - AUTO indicates to use Signal Integrity generated setting (from VPD). - - uint8 - AUTO = 0, FORCE_TO_1N_MODE = 1, FORCE_TO_2N_MODE = 2 - encoded settings for 2N Mode - - - AUTO - - mrw_dram_2n_mode - - ATTR_MSS_MRW_UNSUPPORTED_RANK_CONFIG TARGET_TYPE_MCS @@ -545,94 +41,4 @@ mrw_unsupported_rank_config - - ATTR_MSS_MRW_DRAM_WRITE_CRC - TARGET_TYPE_SYSTEM - Enables DRAM Write CRC - uint8 - - DISABLE = 0, ENABLE = 1 - 0 - mrw_dram_write_crc - - - - ATTR_MSS_MRW_TEMP_REFRESH_MODE - TARGET_TYPE_SYSTEM - - Used in MR4 A3 - Temperature refresh mode - Should be defaulted to disable - - uint8 - - - DISABLE = 0, ENABLE = 1 - 0 - mrw_temp_refresh_mode - - - - ATTR_MSS_MRW_FORCE_BCMODE_OFF - TARGET_TYPE_SYSTEM - - An override switch to shut off broadcast mode - Enum values: - YES: broadcast mode is forced off - NO: broadcast mode uses the default value - - uint8 - - - NO = 0, YES = 1 - mrw_force_bcmode_off - - - - ATTR_MSS_MRW_NVDIMM_PLUG_RULES - TARGET_TYPE_SYSTEM - - A bitmap containing the plug rules for NVDIMM. - 1 if a DIMM supports an NVDIMM being plugged in, 0 if it does not - DIMM slot 0 is the left most bit - The index to the bitmap is the position of the DIMM target - As such, a bitmap of 0b10010000, would allow NVDIMM plugged into DIMM0 and DIMM3 - Note: this attribute is a 64 bit number to account for 16 DIMM per processor if there is ever a 4 processor system - - uint64 - - 0 - NO_NVDIMM = 0, NVDIMM_CAPABLE = 1 - mrw_nvdimm_plug_rules - - - - ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW - TARGET_TYPE_SYSTEM - - Switch that allows unsupported raw card references by providing a - default raw card setting. - - uint8 - - 1 - DISABLE = 0, ENABLE = 1 - mrw_allow_unsupported_rcw - - - - ATTR_MSS_MRW_SUPPORTED_DRAM_WIDTH - TARGET_TYPE_SYSTEM - - Bitmap of DRAM widths supported by a system. A 1 indicates that the system supports a density. - Enums below represent the the bit location in the attribute for a given DRAM width. - Default value is 0xC -> both x4/x8 supported - - uint8 - - 0xc0 - X4 = 0, X8 = 1 - mrw_supported_dram_width - - diff --git a/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml b/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml index f7f678657..31ac9b4c0 100644 --- a/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml +++ b/src/import/generic/procedures/xml/attribute_info/generic_memory_mrw_attributes.xml @@ -60,6 +60,202 @@ mem_mrw_is_planar + + ATTR_MSS_MRW_SAFEMODE_MEM_THROTTLED_N_COMMANDS_PER_PORT + TARGET_TYPE_SYSTEM + + Machine Readable Workbook safe mode throttle value for numerator cfg_nm_n_per_port + Set to below optimum value/ rate. + On a per port basis + Also used for emergency mode throttle FARB4Q_EMERGENCY_N + Used to thermally protect the system in all supported environmental conditions when OCC is not functional + Consumer: thermal_init, initfile + + uint16 + 32 + + + mrw_safemode_mem_throttled_n_commands_per_port + + + + ATTR_MSS_MRW_THERMAL_MEMORY_POWER_LIMIT + TARGET_TYPE_SYSTEM + + Machine Readable Workbook Thermal Memory Power Limit + Used to calculate throttles to be at or under the power limit + Per DIMM basis + KEY (0-19): In order + DIMM_SIZE = bits 0-3, + DIMM_GEN = 4-5, + DIMM_TYPE = 6-7, + DIMM_WIDTH = 8-10, + DIMM_DENSITY = 11-13, + DIMM_STACK_TYPE = 14-15, + DRAM_MFGID = 16-18, + DIMMS_PER_PORT = 19-20, + Bits 21-32: Not used + VALUE (bits 32-63) in cW: + VMEM+VPP thermal power limit per DIMM = 32-63 + Consumers: eff_config_thermal and bulk_pwr_throttles + + uint64 + cW + 0xfffff80000000794 + 10 + + + mrw_thermal_memory_power_limit + + + + ATTR_MSS_MRW_PWR_INTERCEPT + TARGET_TYPE_SYSTEM + + Machine Readable Workbook Power Curve Intercept for DIMM + Used to get the VDDR and VDDR+VPP power curve for each DIMM + Decoded and used to set ATTR_MSS_TOTAL_PWR_INTERCEPT + Key Value pair + KEY (0-19): In order + DIMM_SIZE = bits 0-3, + DIMM_GEN = 4-5, + DIMM_TYPE = 6-7, + DIMM_WIDTH = 8-10, + DIMM_DENSITY = 11-13, + DIMM_STACK_TYPE = 14-15, + DRAM_MFGID = 16-18, + DIMMS_PER_PORT = 19-20, + Bits 21-32: Not used + VALUE (bits 32-63) in cW: + VMEM power curve = 32-47 + VMEM+VPP power curve = 48-63 + Consumers: eff_config_thermal + + uint64 + + + 100 + 0xfffff8000384044C + mrw_pwr_intercept + + + + ATTR_MSS_MRW_PWR_SLOPE + TARGET_TYPE_SYSTEM + + Machine Readable Workbook Power Curve Slope for DIMM + Used to get the VDDR and VDDR+VPP power curve for each DIMM + Decoded and used to set ATTR_MSS_TOTAL_PWR_INTERCEPT + Key Value pair + KEY (0-19): In order + DIMM_SIZE = bits 0-3, + DIMM_GEN = 4-5, + DIMM_TYPE = 6-7, + DIMM_WIDTH = 8-10, + DIMM_DENSITY = 11-13, + DIMM_STACK_TYPE = 14-15, + DRAM_MFGID = 16-18, + DIMMS_PER_PORT = 19-20, + Bits 21-32: Not used + VALUE (bits 32-63) in cW: + VMEM power curve = 32-47 + VMEM+VPP power curve = 48-63 + Consumers: eff_config_thermal + + uint64 + + + 100 + 0xfffff800041A044C + mrw_pwr_slope + + + + ATTR_MSS_MRW_REFRESH_RATE_REQUEST + TARGET_TYPE_SYSTEM + + Machine Readable Workbook Refresh Rate + Desired refresh interval used in refresh register 0, MBAREF0Q_CFG_REFRESH_INTERVAL + 7.8 us (SINGLE) + 3.9 us (DOUBLE) + 7.02 us (SINGLE_10_PERCENT_FASTER) + 3.51 us (DOUBLE_10_PERCENT_FASTER) + + uint8 + + + DOUBLE=0, + SINGLE=1, + SINGLE_10_PERCENT_FASTER=2, + DOUBLE_10_PERCENT_FASTER=3 + + 0x0 + + mrw_refresh_rate_request + + + + ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT + TARGET_TYPE_SYSTEM + + Machine Readable Workbook DIMM power curve percent uplift + for this system at max utilization. + Value should be 0 for ISDIMMs + + uint8 + + 0x0 + + mrw_dimm_power_curve_percent_uplift + + + + ATTR_MSS_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE + TARGET_TYPE_SYSTEM + + Machine Readable Workbook DIMM power curve percent uplift + for this system at idle utilization. + Value should be 0 for ISDIMMs + + uint8 + + 0x0 + + mrw_dimm_power_curve_percent_uplift_idle + + + + ATTR_MSS_MRW_MEM_M_DRAM_CLOCKS + TARGET_TYPE_SYSTEM + + Machine Readable Workbook for the number of M DRAM clocks. + One approach to curbing DRAM power usage is by throttling + traffic through a programmable N commands over M window. + + uint32 + + 0x00000200 + + mrw_mem_m_dram_clocks + + + + ATTR_MSS_MRW_MAX_DRAM_DATABUS_UTIL + TARGET_TYPE_SYSTEM + + Machine Readable Workbook value for maximum dram data bus utilization in centi percent (c%). + Used to determine memory throttle values. + Max databus utilization on a per port basis + Default to 90% + + uint32 + + c% + 0x00002328 + + mrw_max_dram_databus_util + + ATTR_MSS_MRW_POWER_CONTROL_REQUESTED TARGET_TYPE_SYSTEM @@ -74,4 +270,340 @@ mrw_power_control_requested + + + ATTR_MSS_MRW_IDLE_POWER_CONTROL_REQUESTED + TARGET_TYPE_SYSTEM + + Memory power control settings for IDLE powersave mode + Used by OCC when entering idle power-save mode + + uint8 + OFF = 0x00, POWER_DOWN = 0x01, PD_AND_STR = 0x02, PD_AND_STR_CLK_STOP = 0x03 + + OFF + + mrw_idle_power_control_requested + + + + ATTR_MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE + TARGET_TYPE_SYSTEM + + Machine Readable Workbook enablement of the HWP code to adjust the + VMEM regulator power limit based on number of installed DIMMs. + + uint8 + FALSE = 0, TRUE = 1 + + + + + + ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR3 + TARGET_TYPE_SYSTEM + + Machine Readable Workbook VMEM regulator power limit per CDIMM assuming a full configuration. Units in cW + Used for Cumulus + Consumed in mss_eff_config_thermal + + uint32 + + cW + + + + + ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4 + TARGET_TYPE_SYSTEM + + Machine Readable Workbook VMEM regulator power limit per DIMM assuming a full configuration. Units in cW + Consumed in mss_eff_config_thermal + + uint32 + + cW + 0x000006A4 + + mrw_vmem_regulator_power_limit_per_dimm_ddr4 + + + + ATTR_MSS_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR + TARGET_TYPE_SYSTEM + + Machine Readable Workbook value for the maximum possible number + of dimms that can be installed under any of the VMEM regulators. + Consumed in eff_config_thermal to calculate mem_watt_target + + uint8 + + + mrw_max_number_dimms_possible_per_vmem_regulator + + + + ATTR_MSS_MRW_AVDD_OFFSET_ENABLE + TARGET_TYPE_SYSTEM + Used for to determine whether to apply an offset to AVDD. Supplied by MRW. + uint8 + ENABLE = 1, DISABLE = 0 + + + + + + ATTR_MSS_MRW_VDD_OFFSET_ENABLE + TARGET_TYPE_SYSTEM + Used for to determine whether to apply an offset to VDD. Supplied by MRW. + uint8 + ENABLE = 1, DISABLE = 0 + + + + + + ATTR_MSS_MRW_VCS_OFFSET_ENABLE + TARGET_TYPE_SYSTEM + Used for to determine whether to apply an offset to VCS. Supplied by MRW. + uint8 + ENABLE = 1, DISABLE = 0 + + + + + + ATTR_MSS_MRW_VPP_OFFSET_ENABLE + TARGET_TYPE_SYSTEM + Used for to determine whether to apply an offset to VCS. Supplied by MRW. + uint8 + ENABLE = 1, DISABLE = 0 + + + + + + ATTR_MSS_MRW_VDDR_OFFSET_ENABLE + TARGET_TYPE_SYSTEM + Used for to determine whether to apply an offset to VDDR. Supplied by MRW. + uint8 + ENABLE = 1, DISABLE = 0 + + + + + + ATTR_MSS_MRW_FINE_REFRESH_MODE + TARGET_TYPE_SYSTEM + + Fine refresh mode. + Sets DDR4 MRS3. + ZZ uses normal mode. + From JEDEC DDR4 Spec 1716.78C from 07-2016 + Page 47 Table 4.9.1 + + uint8 + + NORMAL = 0, + FIXED_2X = 1, + FIXED_4X = 2, + FLY_2X = 5, + FLY_4X = 6 + + + + NORMAL + mrw_fine_refresh_mode + + + + ATTR_MSS_MRW_TEMP_REFRESH_RANGE + TARGET_TYPE_SYSTEM + + Temperature refresh range. + Sets DDR4 MRS4. + Should be defaulted to extended range. + NORMAL for running at 85 degrees C or less, EXTENDED for 95 or less degrees C + Used for calculating periodic refresh intervals + JEDEC DDR4 spec 1716.78C from 07-2016 + page 46 4.8.1 + + uint8 + NORMAL = 0, EXTEND = 1 + + + EXTEND + mrw_temp_refresh_range + + + + ATTR_MSS_MRW_RESET_DELAY_BEFORE_CAL + TARGET_TYPE_SYSTEM + For resetting the phy delay values at the beginning of calling mss_draminit_training. YES means the vaules will be reset. + uint8 + YES = 0, NO = 1 + YES + + + mrw_reset_delay_before_cal + + + + ATTR_MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS + TARGET_TYPE_SYSTEM + + Describes the settings for periodic calibration for all ports: + Reading left to right. (DEFAULT: 0xD90C -> Byte 0(11011001), Byte 1(00001100)) + For each bit: OFF = 0, ON = 1. Setting to 0 indicates to disable periodic memcal. + Byte 0: + 0: ZCAL + 1: SYSCK_ALIGN + 2: RDCENTERING + 3: RDLCK_ALIGN + 4: DQS_ALIGN + 5: RDCLK_UPDATE + 6: PER_DUTYCYCLE + 7: PERCAL_PWR_DIS + + Byte 1: + 0: PERCAL_REPEAT + 1: PERCAL_REPEAT + 2: PERCAL_REPEAT + 3: SINGLE_BIT_MPR + 4: MBA_CFG_0 + 5: MBA_CFG_1 + 6: SPARE + 7: SPARE + + uint16 + encoded settings for periodic calibration + + 0xD90C + mrw_periodic_memcal_mode_options + + + + ATTR_MSS_MRW_PERIODIC_ZQCAL_MODE_OPTIONS + TARGET_TYPE_SYSTEM + + Describes the settings for periodic ZQ calibration for all ports: + Reading left to right. For each bit: OFF = 0, ON = 1. + Setting to 0 indicates to disable periodic zqcal. + Byte 0: + 0: ZQCAL + All others reserved for future use + + uint16 + encoded settings for periodic calibration + + 0x8000 + mrw_periodic_zqcal_mode_options + + + + ATTR_MSS_MRW_DRAM_2N_MODE + TARGET_TYPE_SYSTEM + + Allows user to manually turn on and off 2N Mode. + AUTO indicates to use Signal Integrity generated setting (from VPD). + + uint8 + AUTO = 0, FORCE_TO_1N_MODE = 1, FORCE_TO_2N_MODE = 2 + encoded settings for 2N Mode + + + AUTO + mrw_dram_2n_mode + + + + ATTR_MSS_MRW_DRAM_WRITE_CRC + TARGET_TYPE_SYSTEM + Enables DRAM Write CRC + uint8 + + DISABLE = 0, ENABLE = 1 + 0 + mrw_dram_write_crc + + + + ATTR_MSS_MRW_TEMP_REFRESH_MODE + TARGET_TYPE_SYSTEM + + Used in MR4 A3 + Temperature refresh mode + Should be defaulted to disable + + uint8 + + + DISABLE = 0, ENABLE = 1 + 0 + mrw_temp_refresh_mode + + + + ATTR_MSS_MRW_FORCE_BCMODE_OFF + TARGET_TYPE_SYSTEM + + An override switch to shut off broadcast mode + Enum values: + YES: broadcast mode is forced off + NO: broadcast mode uses the default value + + uint8 + + + NO = 0, YES = 1 + mrw_force_bcmode_off + + + + ATTR_MSS_MRW_NVDIMM_PLUG_RULES + TARGET_TYPE_SYSTEM + + A bitmap containing the plug rules for NVDIMM. + 1 if a DIMM supports an NVDIMM being plugged in, 0 if it does not + DIMM slot 0 is the left most bit + The index to the bitmap is the position of the DIMM target + As such, a bitmap of 0b10010000, would allow NVDIMM plugged into DIMM0 and DIMM3 + Note: this attribute is a 64 bit number to account for 16 DIMM per processor if there is ever a 4 processor system + + uint64 + + 0 + NO_NVDIMM = 0, NVDIMM_CAPABLE = 1 + mrw_nvdimm_plug_rules + + + + ATTR_MSS_MRW_ALLOW_UNSUPPORTED_RCW + TARGET_TYPE_SYSTEM + + Switch that allows unsupported raw card references by providing a + default raw card setting. + + uint8 + + 1 + DISABLE = 0, ENABLE = 1 + mrw_allow_unsupported_rcw + + + + ATTR_MSS_MRW_SUPPORTED_DRAM_WIDTH + TARGET_TYPE_SYSTEM + + Bitmap of DRAM widths supported by a system. A 1 indicates that the system supports a density. + Enums below represent the the bit location in the attribute for a given DRAM width. + Default value is 0xC -> both x4/x8 supported + + uint8 + + 0xc0 + X4 = 0, X8 = 1 + mrw_supported_dram_width + + diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl index adc8d179a..1632b1cfc 100755 --- a/src/usr/targeting/common/genHwsvMrwXml.pl +++ b/src/usr/targeting/common/genHwsvMrwXml.pl @@ -322,8 +322,6 @@ push @systemAttr, "MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR3", $reqPol->{'vmem_regulator_memory_power_limit_per_dimm'}, "MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM_DDR4", $reqPol->{'mss_mrw_vmem_regulator_memory_power_limit_per_dimm_ddr4'}, "MSS_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE", $reqPol->{'vmem_regulator_memory_power_limit_per_dimm_adjustment_enable'}, - "MSS_MRW_PREFETCH_ENABLE", $reqPol->{'mss_prefetch_enable'}, - "MSS_MRW_CLEANER_ENABLE", $reqPol->{'mss_cleaner_enable'}, #TODO RTC:161768 these need to come from MRW "MSS_MRW_MEM_M_DRAM_CLOCKS", $reqPol->{'mss_mrw_mem_m_dram_clocks'}, "MSS_MRW_PERIODIC_MEMCAL_MODE_OPTIONS", $reqPol->{'mss_mrw_periodic_memcal_mode_options'}, diff --git a/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml b/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml index bbbc47442..25daef3dc 100644 --- a/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml +++ b/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml @@ -382,11 +382,6 @@ 1 - - ATTR_MSS_MRW_PREFETCH_ENABLE - 1 - - ATTR_PROC_FSP_BAR_ENABLE 0 -- cgit v1.2.1