From 1d565299ec312208104cdaf80f63ab5a2e49eb98 Mon Sep 17 00:00:00 2001 From: Louis Stermole Date: Tue, 30 Jan 2018 08:47:48 -0600 Subject: Add plug rule for dual-drop DIMM configs that produce different xlate settings Change-Id: Ief41995350e46386ed592d4c03dfc1f05e942a5c CQ: SW416081 RTC: 186549 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52972 Tested-by: FSP CI Jenkins Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: ANDRE A. MARIN Reviewed-by: STEPHEN GLANCY Reviewed-by: Jennifer A. Stofer Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53194 Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell --- .../hwp/memory/lib/eff_config/plug_rules.C | 50 ++++++++++++++++++++++ .../hwp/memory/lib/eff_config/plug_rules.H | 11 +++++ .../xml/error_info/p9_memory_mss_plug_rules.xml | 40 +++++++++++++++++ 3 files changed, 101 insertions(+) diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C index f3230ef8b..c65d3a5e9 100644 --- a/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C +++ b/src/import/chips/p9/procedures/hwp/memory/lib/eff_config/plug_rules.C @@ -82,6 +82,53 @@ fapi_try_exit: return fapi2::current_err; } +/// +/// @brief Enforce equivalent rank and row configs +/// Enforces configurations which will produce equivalent xlate register settings +/// @param[in] i_target the port +/// @param[in] i_kinds a vector of DIMM +/// @return fapi2::FAPI2_RC_SUCCESS if okay +/// @note Expects the kind array to represent the DIMM on the port. +/// +fapi2::ReturnCode check_xlate_config(const fapi2::Target& i_target, + const std::vector& i_kinds) +{ + if (i_kinds.size() > 1) + { + FAPI_ASSERT( i_kinds[0].equal_config(i_kinds[1]) == true, + fapi2::MSS_PLUG_RULES_DIFFERENT_XLATE() + .set_MASTER_RANKS_ON_DIMM0(i_kinds[0].iv_master_ranks) + .set_MASTER_RANKS_ON_DIMM1(i_kinds[1].iv_master_ranks) + .set_TOTAL_RANKS_ON_DIMM0(i_kinds[0].iv_total_ranks) + .set_TOTAL_RANKS_ON_DIMM1(i_kinds[1].iv_total_ranks) + .set_DRAM_DENSITY_ON_DIMM0(i_kinds[0].iv_dram_density) + .set_DRAM_DENSITY_ON_DIMM1(i_kinds[1].iv_dram_density) + .set_DRAM_WIDTH_ON_DIMM0(i_kinds[0].iv_dram_width) + .set_DRAM_WIDTH_ON_DIMM1(i_kinds[1].iv_dram_width) + .set_DRAM_GEN_ON_DIMM0(i_kinds[0].iv_dram_generation) + .set_DRAM_GEN_ON_DIMM1(i_kinds[1].iv_dram_generation) + .set_DIMM_TYPE_ON_DIMM0(i_kinds[0].iv_dimm_type) + .set_DIMM_TYPE_ON_DIMM1(i_kinds[1].iv_dimm_type) + .set_ROWS_ON_DIMM0(i_kinds[0].iv_rows) + .set_ROWS_ON_DIMM1(i_kinds[1].iv_rows) + .set_SIZE_ON_DIMM0(i_kinds[0].iv_size) + .set_SIZE_ON_DIMM1(i_kinds[1].iv_size) + .set_MCA_TARGET(i_target), + "%s has two different configurations of DIMM installed. mranks=%d,%d ranks=%d,%d density=%d,%d width=%d,%d gen=%d,%d type=%d,%d rows=%d,%d size=%d,%d Cannot mix DIMM configurations on port", + mss::c_str(i_target), i_kinds[0].iv_master_ranks, i_kinds[1].iv_master_ranks, + i_kinds[0].iv_total_ranks, i_kinds[1].iv_total_ranks, + i_kinds[0].iv_dram_density, i_kinds[1].iv_dram_density, + i_kinds[0].iv_dram_width, i_kinds[1].iv_dram_width, + i_kinds[0].iv_dram_generation, i_kinds[1].iv_dram_generation, + i_kinds[0].iv_dimm_type, i_kinds[1].iv_dimm_type, + i_kinds[0].iv_rows, i_kinds[1].iv_rows, + i_kinds[0].iv_size, i_kinds[1].iv_size); + } + +fapi_try_exit: + return fapi2::current_err; +} + } // code /// @@ -721,6 +768,9 @@ fapi2::ReturnCode plug_rule::enforce_plug_rules(const fapi2::Target& i_kinds ); +/// +/// @brief Enforce equivalent rank and row configs +/// Enforces configurations which will produce equivalent xlate register settings +/// @param[in] i_target the port +/// @param[in] i_kinds a vector of DIMM +/// @return fapi2::FAPI2_RC_SUCCESS if okay +/// @note Expects the kind array to represent the DIMM on the port. +/// +fapi2::ReturnCode check_xlate_config(const fapi2::Target& i_target, + const std::vector& i_kinds); + } // code } // plug_rule diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_plug_rules.xml b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_plug_rules.xml index ca7c2fa8d..7220ef48e 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_plug_rules.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_memory_mss_plug_rules.xml @@ -373,4 +373,44 @@ + + RC_MSS_PLUG_RULES_DIFFERENT_XLATE + + Two DIMM with different translation (xlate) configurations are installed on port + + MASTER_RANKS_ON_DIMM0 + MASTER_RANKS_ON_DIMM1 + TOTAL_RANKS_ON_DIMM0 + TOTAL_RANKS_ON_DIMM1 + DRAM_DENSITY_ON_DIMM0 + DRAM_DENSITY_ON_DIMM1 + DRAM_WIDTH_ON_DIMM0 + DRAM_WIDTH_ON_DIMM1 + DRAM_GEN_ON_DIMM0 + DRAM_GEN_ON_DIMM1 + DIMM_TYPE_ON_DIMM0 + DIMM_TYPE_ON_DIMM1 + ROWS_ON_DIMM0 + ROWS_ON_DIMM1 + SIZE_ON_DIMM0 + SIZE_ON_DIMM1 + + MEMORY_PLUGGING_ERROR + HIGH + + + + MCA_TARGET + TARGET_TYPE_DIMM + + MEDIUM + + + + MCA_TARGET + TARGET_TYPE_DIMM + + + + -- cgit v1.2.1