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-rw-r--r--src/usr/vpd/spdDDR4.H2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/usr/vpd/spdDDR4.H b/src/usr/vpd/spdDDR4.H
index 7f165d85a..b4413efe9 100644
--- a/src/usr/vpd/spdDDR4.H
+++ b/src/usr/vpd/spdDDR4.H
@@ -108,7 +108,6 @@ const KeywordData ddr4Data[] =
{ MODULE_MANUFACTURING_DATE, 0x143, 0x02, 0x00, 0x00, false, false, NA },
{ MODULE_SERIAL_NUMBER, 0x145, 0x04, 0x00, 0x00, false, false, NA },
{ MODULE_PART_NUMBER, 0x149, 0x14, 0x00, 0x00, false, false, NA },
- { MODULE_REVISION_CODE, 0x15d, 0x01, 0x00, 0x00, true, false, NA },
{ DRAM_MANUFACTURER_ID, 0x15f, 0x02, 0x00, 0x00, true, false, NA },
{ MANUFACTURER_SPECIFIC_DATA, 0x161, 0x1d, 0x00, 0x00, false, false, NA },
{ DIMM_BAD_DQ_DATA, 0x180, 0x50, 0x00, 0x00, false, true, NA },
@@ -132,6 +131,7 @@ const KeywordData ddr4Data[] =
{ TRRDS_FINE_OFFSET, 0x77, 0x01, 0x00, 0x00, false, false, NA },
{ TCKMAX_FINE_OFFSET, 0x7c, 0x01, 0x00, 0x00, false, false, NA },
{ BASE_CONFIG_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, NA },
+ { MODULE_REVISION_CODE_DDR4, 0x15d, 0x01, 0x00, 0x00, false, false, NA },
{ DRAM_STEPPING, 0x160, 0x01, 0x00, 0x00, false, false, NA },
{ MANUFACTURING_SECTION_CRC, 0x17f, 0x02, 0x00, 0x00, true, false, NA },
// Module Specific fields supported on both DDR3 and DDR4
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