diff options
Diffstat (limited to 'src/usr/hwpf/hwp')
| -rw-r--r-- | src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C | 244 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C | 10 | ||||
| -rwxr-xr-x | src/usr/hwpf/hwp/ei_bus_attributes.xml | 52 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/edi.io.define | 4 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/ei4.io.define | 961 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile | 515 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile | 828 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C | 308 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/slave_sbe/slave_sbe.C | 3 |
9 files changed, 2773 insertions, 152 deletions
diff --git a/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C b/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C index 5180bf7e3..18da77659 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C +++ b/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.C @@ -71,7 +71,8 @@ using namespace EDI_EI_INITIALIZATION; using namespace fapi; //****************************************************************************** -// wrapper funciton to call step 9.01 - proc_build_smp +// Wrapper function to call 09.1 : +// proc_build_smp //****************************************************************************** void* call_proc_build_smp( void *io_pArgs ) { @@ -82,137 +83,158 @@ void* call_proc_build_smp( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_build_smp entry" ); - // Get all functional proc chip targets - TARGETING::TargetHandleList l_cpuTargetList; - getAllChips(l_cpuTargetList, TYPE_PROC); - - // Collect all valid abus connections and xbus connections - TargetPairs_t l_abusConnections; - TargetPairs_t l_xbusConnections; - l_errl = PbusLinkSvc::getTheInstance().getPbusConnections( - l_abusConnections, TYPE_ABUS, false ); - if (!l_errl) + do { + // Get all functional proc chip targets + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); + + // Collect all valid abus connections and xbus connections + TargetPairs_t l_abusConnections; + TargetPairs_t l_xbusConnections; l_errl = PbusLinkSvc::getTheInstance().getPbusConnections( - l_xbusConnections, TYPE_XBUS, false ); - } + l_abusConnections, TYPE_ABUS, false ); + if (l_errl) + { + l_StepError.addErrorDetails(ISTEP_ACTIVATE_POWER_BUS_FAILED, + ISTEP_PROC_BUILD_SMP, + l_errl); + break; + } - // Populate l_proc_Chips vector for each good processor chip - // if a A/X-bus endpoint has a valid connection, then - // obtain the proc chip target of the other endpoint of the - // connection, build the fapi target to update the corresponding - // chip object of this A/X-bus endpoint for the procEntry - std::vector<proc_build_smp_proc_chip> l_procChips; + // Get XBUS connections + l_errl = PbusLinkSvc::getTheInstance().getPbusConnections( + l_xbusConnections, TYPE_XBUS, false ); + + if (l_errl) + { + l_StepError.addErrorDetails(ISTEP_ACTIVATE_POWER_BUS_FAILED, + ISTEP_PROC_BUILD_SMP, + l_errl); + break; + } - for ( size_t i = 0; (!l_errl) && (i < l_cpuTargetList.size()); i++ ) - { - proc_build_smp_proc_chip l_procEntry; + // Populate l_proc_Chips vector for each good processor chip + // if a A/X-bus endpoint has a valid connection, then + // obtain the proc chip target of the other endpoint of the + // connection, build the fapi target to update the corresponding + // chip object of this A/X-bus endpoint for the procEntry + std::vector<proc_build_smp_proc_chip> l_procChips; - l_procEntry.enable_f0 = false; - l_procEntry.enable_f1 = false; - l_procEntry.f0_node_id = FBC_NODE_ID_0; - l_procEntry.f1_node_id = FBC_NODE_ID_0; + for (TARGETING::TargetHandleList::iterator l_cpuIter = + l_cpuTargetList.begin(); l_cpuIter != l_cpuTargetList.end(); + ++l_cpuIter) + { + proc_build_smp_proc_chip l_procEntry; + const TARGETING::Target* l_pTarget = *l_cpuIter; - const TARGETING::Target * l_pTarget = l_cpuTargetList[i]; - fapi::Target l_fapiproc_target( TARGET_TYPE_PROC_CHIP, - reinterpret_cast<void *> - (const_cast<TARGETING::Target*>(l_pTarget)) ); + fapi::Target l_fapiproc_target( TARGET_TYPE_PROC_CHIP, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>(l_pTarget)) ); - l_procEntry.this_chip = l_fapiproc_target; + l_procEntry.this_chip = l_fapiproc_target; + l_procEntry.enable_f0 = false; + l_procEntry.enable_f1 = false; - TARGETING::TargetHandleList l_abuses; - getChildChiplets( l_abuses, l_pTarget, TYPE_ABUS ); + TARGETING::TargetHandleList l_abuses; + getChildChiplets( l_abuses, l_pTarget, TYPE_ABUS ); - for (size_t j = 0; j < l_abuses.size(); j++) - { - TARGETING::Target * l_target = l_abuses[j]; - uint8_t l_srcID = l_target->getAttr<ATTR_CHIP_UNIT>(); - TargetPairs_t::iterator l_itr = l_abusConnections.find(l_target); - if ( l_itr == l_abusConnections.end() ) + for (TARGETING::TargetHandleList::iterator l_abusIter = + l_abuses.begin(); l_abusIter != l_abuses.end(); ++l_abusIter) { - continue; + TARGETING::Target * l_target = *l_abusIter; + uint8_t l_srcID = l_target->getAttr<ATTR_CHIP_UNIT>(); + TargetPairs_t::iterator l_itr = l_abusConnections.find(l_target); + if ( l_itr == l_abusConnections.end() ) + { + continue; + } + + const TARGETING::Target *l_pParent = NULL; + l_pParent = getParentChip( + (const_cast<TARGETING::Target*>(l_itr->second))); + fapi::Target l_fapiproc_parent( TARGET_TYPE_PROC_CHIP, + (void *)l_pParent ); + + switch (l_srcID) + { + case 0: l_procEntry.a0_chip = l_fapiproc_parent; break; + case 1: l_procEntry.a1_chip = l_fapiproc_parent; break; + case 2: l_procEntry.a2_chip = l_fapiproc_parent; break; + default: break; + } + + l_procEntry.f0_node_id = static_cast<proc_fab_smp_node_id>( + l_pTarget->getAttr<TARGETING::ATTR_FABRIC_NODE_ID>()); + l_procEntry.f1_node_id = static_cast<proc_fab_smp_node_id>( + l_pParent->getAttr<TARGETING::ATTR_FABRIC_NODE_ID>()); } - const TARGETING::Target *l_pParent = NULL; - l_pParent = getParentChip( - (const_cast<TARGETING::Target*>(l_itr->second))); - fapi::Target l_fapiproc_parent( TARGET_TYPE_PROC_CHIP, - (void *)l_pParent ); + TARGETING::TargetHandleList l_xbuses; + getChildChiplets( l_xbuses, l_pTarget, TYPE_XBUS ); - switch (l_srcID) + for (TARGETING::TargetHandleList::iterator l_xbusIter = + l_xbuses.begin(); l_xbusIter != l_xbuses.end(); ++l_xbusIter) { - case 0: l_procEntry.a0_chip = l_fapiproc_parent; break; - case 1: l_procEntry.a1_chip = l_fapiproc_parent; break; - case 2: l_procEntry.a2_chip = l_fapiproc_parent; break; - default: break; + TARGETING::Target * l_target = *l_xbusIter; + uint8_t l_srcID = l_target->getAttr<ATTR_CHIP_UNIT>(); + TargetPairs_t::iterator l_itr = l_xbusConnections.find(l_target); + if ( l_itr == l_xbusConnections.end() ) + { + continue; + } + + const TARGETING::Target *l_pParent = NULL; + l_pParent = getParentChip( + (const_cast<TARGETING::Target*>(l_itr->second))); + fapi::Target l_fapiproc_parent( TARGET_TYPE_PROC_CHIP, + (void *)l_pParent ); + + switch (l_srcID) + { + case 0: l_procEntry.x0_chip = l_fapiproc_parent; break; + case 1: l_procEntry.x1_chip = l_fapiproc_parent; break; + case 2: l_procEntry.x2_chip = l_fapiproc_parent; break; + case 3: l_procEntry.x3_chip = l_fapiproc_parent; break; + default: break; + } } + + l_procChips.push_back( l_procEntry ); } - TARGETING::TargetHandleList l_xbuses; - getChildChiplets( l_xbuses, l_pTarget, TYPE_XBUS ); + // call the HWP with each fapi::Target + FAPI_INVOKE_HWP( l_errl, proc_build_smp, l_procChips, + SMP_ACTIVATE_PHASE1 ); - for (size_t j = 0; j < l_xbuses.size(); j++) + if(l_errl) { - TARGETING::Target * l_target = l_xbuses[j]; - uint8_t l_srcID = l_target->getAttr<ATTR_CHIP_UNIT>(); - TargetPairs_t::iterator l_itr = l_xbusConnections.find(l_target); - if ( l_itr == l_xbusConnections.end() ) - { - continue; - } - - const TARGETING::Target *l_pParent = NULL; - l_pParent = getParentChip( - (const_cast<TARGETING::Target*>(l_itr->second))); - fapi::Target l_fapiproc_parent( TARGET_TYPE_PROC_CHIP, - (void *)l_pParent ); - - switch (l_srcID) - { - case 0: l_procEntry.x0_chip = l_fapiproc_parent; break; - case 1: l_procEntry.x1_chip = l_fapiproc_parent; break; - case 2: l_procEntry.x2_chip = l_fapiproc_parent; break; - case 3: l_procEntry.x3_chip = l_fapiproc_parent; break; - default: break; - } + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR : proc_build_smp" ); + /*@ + * @errortype + * @reasoncode ISTEP_ACTIVATE_POWER_BUS_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_PROC_BUILD_SMP + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs included + * bytes 2-3: N/A + * @devdesc call to proc_build_smp has failed + */ + l_StepError.addErrorDetails(ISTEP_ACTIVATE_POWER_BUS_FAILED, + ISTEP_PROC_BUILD_SMP, + l_errl); + errlCommit( l_errl, HWPF_COMP_ID ); + break; + } + else + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : proc_build_smp" ); } - l_procChips.push_back( l_procEntry ); - } - - if(!l_errl) - { - // call the HWP with each fapi::Target - FAPI_INVOKE_HWP( l_errl, proc_build_smp, - l_procChips, SMP_ACTIVATE_PHASE1 ); - } - - if(l_errl) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR : proc_build_smp" ); - /*@ - * @errortype - * @reasoncode ISTEP_ACTIVATE_POWER_BUS_FAILED - * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE - * @moduleid ISTEP_PROC_BUILD_SMP - * @userdata1 bytes 0-1: plid identifying first error - * bytes 2-3: reason code of first error - * @userdata2 bytes 0-1: total number of elogs included - * bytes 2-3: N/A - * @devdesc call to proc_build_smp has failed - */ - l_StepError.addErrorDetails(ISTEP_ACTIVATE_POWER_BUS_FAILED, - ISTEP_PROC_BUILD_SMP, - l_errl); - - errlCommit( l_errl, HWPF_COMP_ID ); - } - else - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : proc_build_smp" ); - } + } while (0); TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_build_smp exit" ); diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C b/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C index 1f5664656..f23233a57 100644 --- a/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C +++ b/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C @@ -259,7 +259,9 @@ void* call_fabric_io_run_training( void *io_pArgs ) TargetPairs_t l_PbusConnections; TargetPairs_t::iterator l_itr; const uint32_t MaxBusSet = 2; - TYPE busSet[MaxBusSet] = { TYPE_ABUS, TYPE_XBUS }; + + // Note: Run XBUS first to match with Cronus + TYPE busSet[MaxBusSet] = { TYPE_XBUS, TYPE_ABUS }; for (uint32_t i = 0; (!l_errl) && (i < MaxBusSet); i++) { @@ -270,11 +272,11 @@ void* call_fabric_io_run_training( void *io_pArgs ) (!l_errl) && (l_itr != l_PbusConnections.end()); ++l_itr) { const fapi::Target l_fapi_endp1_target( - (i ? TARGET_TYPE_XBUS_ENDPOINT : TARGET_TYPE_ABUS_ENDPOINT), + (i ? TARGET_TYPE_ABUS_ENDPOINT : TARGET_TYPE_XBUS_ENDPOINT), reinterpret_cast<void *> (const_cast<TARGETING::Target*>(l_itr->first))); const fapi::Target l_fapi_endp2_target( - (i ? TARGET_TYPE_XBUS_ENDPOINT : TARGET_TYPE_ABUS_ENDPOINT), + (i ? TARGET_TYPE_ABUS_ENDPOINT : TARGET_TYPE_XBUS_ENDPOINT), reinterpret_cast<void *> (const_cast<TARGETING::Target*>(l_itr->second))); @@ -291,7 +293,7 @@ void* call_fabric_io_run_training( void *io_pArgs ) TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "%s : %cbus connection io_run_training", (l_errl ? "ERROR" : "SUCCESS"), - (i ? 'X' : 'A') ); + (i ? 'A' : 'X') ); if ( l_errl ) { diff --git a/src/usr/hwpf/hwp/ei_bus_attributes.xml b/src/usr/hwpf/hwp/ei_bus_attributes.xml index 391a2d951..6824c67dd 100755 --- a/src/usr/hwpf/hwp/ei_bus_attributes.xml +++ b/src/usr/hwpf/hwp/ei_bus_attributes.xml @@ -1,25 +1,25 @@ -<!-- IBM_PROLOG_BEGIN_TAG - This is an automatically generated prolog. - - $Source: src/usr/hwpf/hwp/ei_bus_attributes.xml $ - - IBM CONFIDENTIAL - - COPYRIGHT International Business Machines Corp. 2012 - - p1 - - Object Code Only (OCO) source materials - Licensed Internal Code Source Materials - IBM HostBoot Licensed Internal Code - - The source code for this program is not published or other- - wise divested of its trade secrets, irrespective of what has - been deposited with the U.S. Copyright Office. - - Origin: 30 - - IBM_PROLOG_END_TAG --> +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/ei_bus_attributes.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> <!-- XML file specifying HWPF attributes. These are platInit attributes associated with chips. @@ -29,18 +29,18 @@ <!-- ********************************************************************* --> <attribute> <id>ATTR_EI_BUS_RX_MSB_LSB_SWAP</id> - <targetType>TARGET_TYPE_MCS_CHIPLET,TARGET_TYPE_MEMBUF_CHIP</targetType> + <targetType>TARGET_TYPE_MCS_CHIPLET,TARGET_TYPE_MEMBUF_CHIP,TARGET_TYPE_ABUS_ENDPOINT</targetType> <description> - PRBS scramble pattern per lane on DMI bus for p8 and centaur. + When = 1, indicates the bus is end-for-end flipped in the board wiring. </description> <valueType>uint8</valueType> <platInit/> </attribute> <attribute> <id>ATTR_EI_BUS_TX_MSB_LSB_SWAP</id> - <targetType>TARGET_TYPE_MCS_CHIPLET,TARGET_TYPE_MEMBUF_CHIP</targetType> + <targetType>TARGET_TYPE_MCS_CHIPLET,TARGET_TYPE_MEMBUF_CHIP,TARGET_TYPE_ABUS_ENDPOINT</targetType> <description> - PRBS scramble pattern per lane on DMI bus for p8 and centaur. + When = 1, indicates the bus is end-for-end flipped in the board wiring. </description> <valueType>uint8</valueType> <platInit/> diff --git a/src/usr/hwpf/hwp/initfiles/edi.io.define b/src/usr/hwpf/hwp/initfiles/edi.io.define index e15d8f421..05bfb2dd9 100644 --- a/src/usr/hwpf/hwp/initfiles/edi.io.define +++ b/src/usr/hwpf/hwp/initfiles/edi.io.define @@ -1,4 +1,4 @@ -#-- $Id: edi.io.define,v 1.2 2012/06/14 01:37:56 jmcgill Exp $ +#-- $Id: edi.io.define,v 1.3 2012/07/09 22:31:54 ttnguyen Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: @@ -8,7 +8,6 @@ #-------------------------------------------------------------------------------- # End of revision history #-------------------------------------------------------------------------------- - define tx_mode_pl=010000000; #080 define tx_cntl_stat_pl=010000001; #081 define tx_spare_mode_pl=010000010; #082 @@ -986,6 +985,7 @@ define rx_pb_fir_err_inj_gcrs_ld_sm2=54:54; #start_bit=54, number_of_bit=1 define rx_pb_fir_err_inj_gcrs_unld_sm0=55:55; #start_bit=55, number_of_bit=1 define rx_pb_fir_err_inj_gcrs_unld_sm1=56:56; #start_bit=56, number_of_bit=1 define rx_pb_fir_err_inj_gcrs_unld_sm2=57:57; #start_bit=57, number_of_bit=1 +define abus_gcr_addr=08010C3F; define dmi0_gcr_addr=02011A3F; define dmi1_gcr_addr=02011E3F; define cn_gcr_addr=0201043F; diff --git a/src/usr/hwpf/hwp/initfiles/ei4.io.define b/src/usr/hwpf/hwp/initfiles/ei4.io.define new file mode 100644 index 000000000..1a74e4180 --- /dev/null +++ b/src/usr/hwpf/hwp/initfiles/ei4.io.define @@ -0,0 +1,961 @@ +#-- $Id: ei4.io.define,v 1.2 2012/08/01 05:31:17 thomsen Exp $ +#-- CHANGE HISTORY: +#-------------------------------------------------------------------------------- +#-- Version:|Author: | Date: | Comment: +#-- --------|--------|--------|-------------------------------------------------- +#-- 1.1 |pmegan |07/10/12|Created initial version +#-- --------|--------|--------|-------------------------------------------------- +#-------------------------------------------------------------------------------- +# End of revision history +#-------------------------------------------------------------------------------- +define tx_mode_pl=010000000; #080 +define tx_cntl_stat_pl=010000001; #081 +define tx_spare_mode_pl=010000010; #082 +#define #tx_id_pl=010000100; #084 +define tx_bist_stat_pl=010000101; #085 +define tx_prbs_mode_pl=010000110; #086 +define tx_data_cntl_gcrmsg_pl=010000111; #087 +define tx_sync_pattern_gcrmsg_pl=010001000; #088 +define tx_fir_pl=010001010; #08A +define tx_fir_mask_pl=010001011; #08B +define tx_fir_error_inject_pl=010001100; #08C +define tx_mode_fast_pl=010001101; #08D +define tx_clk_mode_pg=110000000; #180 +define tx_spare_mode_pg=110000001; #181 +define tx_cntl_stat_pg=110000010; #182 +define tx_mode_pg=110000011; #183 +define tx_reset_act_pg=110001000; #188 +define tx_bist_stat_pg=110001001; #189 +define tx_fir_pg=110001010; #18A +define tx_fir_mask_pg=110001011; #18B +define tx_fir_error_inject_pg=110001100; #18C +define tx_id1_pg=110010010; #192 +define tx_id2_pg=110010011; #193 +define tx_id3_pg=110010100; #194 +define tx_clk_cntl_gcrmsg_pg=110011000; #198 +define tx_bad_lane_enc_gcrmsg_pg=110011101; #19D +define tx_ber_cntl_pg=110011110; #19E +define tx_sls_lane_enc_gcrmsg_pg=110011111; #19F +define tx_wt_seg_enable_pg=110100000; #1A0 +#define #tx_term_pg=110100000; #1A0 +define tx_pc_ffe_pg=110100001; #1A1 +define tx_misc_analog_pg=110100010; #1A2 +define tx_lane_disabled_vec_0_15_pg=110100011; #1A3 +define tx_lane_disabled_vec_16_31_pg=110100100; #1A4 +define tx_sls_lane_mux_gcrmsg_pg=110100101; #1A5 +define tx_dyn_rpr_pg=110100110; #1A6 +define tx_slv_mv_sls_ln_req_gcrmsg_pg=110100111; #1A7 +define tx_rdt_cntl_pg=110101000; #1A8 +define rx_dll_cal_cntl_pg=111000111; #1C7 +define rx_dll1_setpoint1_pg=111001000; #1C8 +define rx_dll1_setpoint2_pg=111001001; #1C9 +define rx_dll1_setpoint3_pg=111001010; #1CA +define rx_dll2_setpoint1_pg=111001011; #1CB +define rx_dll2_setpoint2_pg=111001100; #1CC +define rx_dll2_setpoint3_pg=111001101; #1CD +define rx_dll_filter_mode_pg=111001110; #1CE +define rx_dll_analog_tweaks_pg=111001111; #1CF +define tx_wiretest_pp=111010000; #1D0 +define tx_mode_pp=111010001; #1D1 +define tx_sls_gcrmsg_pp=111010010; #1D2 +define tx_ber_cntl_a_pp=111010011; #1D3 +define tx_ber_cntl_b_pp=111010100; #1D4 +define tx_bist_cntl_pp=111010110; #1D6 +define tx_ber_cntl_sls_pp=111010111; #1D7 +define tx_cntl_pp=111011000; #1D8 +define tx_reset_cfg_pp=111011001; #1D9 +define tx_tdr_cntl2_pp=111011011; #1DB +define tx_tdr_cntl3_pp=111011100; #1DC +define tx_init_version_pb=111101000; #1E8 +define tx_scratch_reg_pb=111101001; #1E9 +define rx_mode_pl=000000000; #000 +define rx_cntl_pl=000000001; #001 +define rx_spare_mode_pl=000000010; #002 +define rx_prot_edge_status_pl=000000011; #003 +#define #rx_prot_gb_status_pl=000000100; #004 +define rx_bist_stat_pl=000000101; #005 +#define ##rx_eyeopt_mode_pl=000000110; #006 +#define #rx_eyeopt_stat_pl=000000111; #007 +define rx_offset_even_pl=000001000; #008 +define rx_offset_odd_pl=000001001; #009 +define rx_amp_val_pl=000001010; #00A +define rx_prot_status_pl=000001100; #00C +define rx_prot_mode_pl=000001101; #00D +define rx_prot_cntl_pl=000001110; #00E +#define #rx_wiretest_stat_pl=000001110; #00E +define rx_fifo_stat_pl=000001111; #00F +define rx_prbs_mode_pl=000010110; #016 +define rx_vref_pl=000010111; #017 +define rx_stat_pl=000011000; #018 +define rx_deskew_stat_pl=000011001; #019 +define rx_fir_pl=000011010; #01A +define rx_fir_mask_pl=000011011; #01B +define rx_fir_error_inject_pl=000011100; #01C +define rx_sls_pl=000011101; #01D +define rx_wt_status_pl=000011110; #01E +define rx_fifo_cntl_pl=000011111; #01F +define rx_ber_status_pl=000100000; #020 +define rx_ber_timer_0_15_pl=000100001; #021 +define rx_ber_timer_16_31_pl=000100010; #022 +define rx_ber_timer_32_39_pl=000100011; #023 +define rx_servo_cntl_pl=000100100; #024 +define rx_fifo_diag_0_15_pl=000100101; #025 +define rx_fifo_diag_16_31_pl=000100110; #026 +define rx_fifo_diag_32_47_pl=000100111; #027 +define rx_eye_width_status_pl=000101000; #028 +define rx_eye_width_cntl_pl=000101001; #029 +define rx_trace_pl=000101011; #02B +define rx_servo_ber_count_pl=000101100; #02C +define rx_eye_opt_stat_pl=000101101; #02D +define rx_clk_mode_pg=100000000; #100 +define rx_spare_mode_pg=100000001; #101 +define rx_stop_cntl_stat_pg=100000010; #102 +define rx_mode_pg=100000011; #103 +define rx_stop_addr_lsb_pg=100000111; #107 +define rx_stop_mask_lsb_pg=100001000; #108 +define rx_reset_act_pg=100001001; #109 +define rx_id1_pg=100001010; #10A +define rx_id2_pg=100001011; #10B +define rx_id3_pg=100001100; #10C +define rx_dyn_rpr_debug2_pg=100001110; #10E +define rx_sls_mode_pg=100001111; #10F +define rx_training_start_pg=100010000; #110 +define rx_training_status_pg=100010001; #111 +define rx_recal_status_pg=100010010; #112 +define rx_timeout_sel_pg=100010011; #113 +define rx_fifo_mode_pg=100010100; #114 +#define #rx_state_debug_pg=100010101; #115 +#define #rx_state_val_pg=100010110; #116 +define rx_sls_status_pg=100010111; #117 +define rx_fir1_pg=100011010; #11A +define rx_fir2_pg=100011011; #11B +define rx_fir1_mask_pg=100011100; #11C +define rx_fir2_mask_pg=100011101; #11D +define rx_fir1_error_inject_pg=100011110; #11E +define rx_fir2_error_inject_pg=100011111; #11F +define rx_fir_training_pg=100100000; #120 +define rx_fir_training_mask_pg=100100001; #121 +define rx_timeout_sel1_pg=100100010; #122 +define rx_lane_bad_vec_0_15_pg=100100011; #123 +define rx_lane_bad_vec_16_31_pg=100100100; #124 +define rx_lane_disabled_vec_0_15_pg=100100101; #125 +define rx_lane_disabled_vec_16_31_pg=100100110; #126 +define rx_lane_swapped_vec_0_15_pg=100100111; #127 +define rx_lane_swapped_vec_16_31_pg=100101000; #128 +define rx_init_state_pg=100101001; #129 +define rx_wiretest_state_pg=100101010; #12A +define rx_wiretest_laneinfo_pg=100101011; #12B +define rx_wiretest_gcrmsgs_pg=100101100; #12C +define rx_deskew_gcrmsgs_pg=100101101; #12D +define rx_deskew_state_pg=100101110; #12E +define rx_deskew_mode_pg=100101111; #12F +define rx_deskew_status_pg=100110000; #130 +define rx_bad_lane_enc_gcrmsg_pg=100110001; #131 +define rx_static_repair_state_pg=100110010; #132 +define rx_tx_bus_info_pg=100110011; #133 +define rx_sls_lane_enc_gcrmsg_pg=100110100; #134 +define rx_fence_pg=100110101; #135 +define rx_term_pg=100110110; #136 +define rx_timeout_sel2_pg=100110111; #137 +define rx_misc_analog_pg=100111000; #138 +define rx_dyn_rpr_pg=100111001; #139 +define rx_dyn_rpr_gcrmsg_pg=100111010; #13A +define rx_dyn_rpr_err_tallying1_pg=100111011; #13B +define rx_eo_final_l2u_gcrmsgs_pg=100111100; #13C +define rx_gcr_msg_debug_dest_ids_pg=100111101; #13D +define rx_gcr_msg_debug_src_ids_pg=100111110; #13E +define rx_gcr_msg_debug_dest_addr_pg=100111111; #13F +define rx_gcr_msg_debug_write_data_pg=101000000; #140 +define rx_wt_clk_status_pg=101000010; #142 +define rx_wt_config_pg=101000100; #144 +define rx_wiretest_pll_cntl_pg=101000110; #146 +define rx_eo_step_cntl_pg=101000111; #147 +define rx_eo_step_stat_pg=101001000; #148 +define rx_eo_step_fail_pg=101001001; #149 +define rx_amp_val_pg=101001110; #14E +define rx_sls_rcvy_pg=101010001; #151 +define rx_sls_rcvy_gcrmsg_pg=101010010; #152 +define rx_tx_lane_info_gcrmsg_pg=101010011; #153 +define rx_err_tallying_gcrmsg_pg=101010100; #154 +define rx_trace_pg=101010101; #155 +define rx_rdt_cntl_pg=101010110; #156 +define rx_rc_step_cntl_pg=101010111; #157 +define rx_eo_recal_pg=101011000; #158 +define rx_servo_ber_count_pg=101011001; #159 +define rx_func_state_pg=101011010; #15A +define rx_dyn_rpr_debug_pg=101011011; #15B +define rx_dyn_rpr_err_tallying2_pg=101011100; #15C +define rx_result_chk_pg=101011101; #15D +define rx_sls_rcvy_fin_gcrmsg_pg=101011111; #15F +#define #rx_wiretest_pp=101100000; #160 +define rx_mode1_pp=101100001; #161 +define rx_cntl_fast_pp=101100010; #162 +define rx_ei4_cal_cntl_pp=101100011; #163 +define rx_ei4_cal_inc_a_d_pp=101100100; #164 +define rx_ei4_cal_inc_e_h_pp=101100101; #165 +define rx_ei4_cal_dec_a_d_pp=101100110; #166 +define rx_ei4_cal_dec_e_h_pp=101100111; #167 +define rx_ber_cntl_pp=101101010; #16A +define rx_ber_mode_pp=101101011; #16B +define rx_servo_to1_pp=101101100; #16C +define rx_servo_to2_pp=101101101; #16D +define rx_reset_cfg_pp=101110001; #171 +define rx_recal_to1_pp=101110010; #172 +define rx_recal_to2_pp=101110011; #173 +define rx_recal_cntl_pp=101110101; #175 +define rx_mode2_pp=101110110; #176 +define rx_bist_gcrmsg_pp=101110111; #177 +define rx_fir_reset_pb=111110000; #1F0 +define rx_fir_pb=111110001; #1F1 +define rx_fir_mask_pb=111110010; #1F2 +define rx_fir_error_inject_pb=111110011; #1F3 +define rx_fir_msg_pb=111111111; #1FF +define tx_mode_pl_full_reg=48:63; #start_bit=48, number_of_bit=16 +define tx_lane_pdwn=48:48; #start_bit=48, number_of_bit=1 +define tx_lane_invert=49:49; #start_bit=49, number_of_bit=1 +define tx_lane_quiesce=50:51; #start_bit=50, number_of_bit=2 +define tx_lane_scramble_disable=54:54; #start_bit=54, number_of_bit=1 +#define #tx_lane_error_inject_mode=58:63; #start_bit=58, number_of_bit=6 +define tx_fifo_err=48:48; #start_bit=48, number_of_bit=1 +define tx_pl_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 +define tx_pl_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 +define tx_pl_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 +define tx_pl_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 +define tx_pl_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 +define tx_pl_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 +define tx_pl_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 +define tx_pl_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 +#define #tx_lane_id=48:52; #start_bit=48, number_of_bit=5 +define tx_lane_bist_err=48:48; #start_bit=48, number_of_bit=1 +define tx_lane_bist_done=49:49; #start_bit=49, number_of_bit=1 +define tx_pl_fir_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 +define tx_pl_fir_errs=48:48; #start_bit=48, number_of_bit=1 +define tx_pl_fir_err_pl_regs=48:48; #start_bit=48, number_of_bit=1 +define tx_pl_fir_errs_mask_full_reg=48:63; #start_bit=48, number_of_bit=16 +define tx_pl_fir_errs_mask=48:48; #start_bit=48, number_of_bit=1 +define tx_pl_fir_err_mask_pl_regs=48:48; #start_bit=48, number_of_bit=1 +define tx_pl_fir_err_inj_full_reg=48:63; #start_bit=48, number_of_bit=16 +define tx_pl_fir_err_inj=48:48; #start_bit=48, number_of_bit=1 +define tx_pl_fir_err_inj_pl_regs=48:48; #start_bit=48, number_of_bit=1 +define tx_prbs_tap_id=48:50; #start_bit=48, number_of_bit=3 +define tx_drv_data_pattern_gcrmsg=48:51; #start_bit=48, number_of_bit=4 +define tx_drv_func_data_gcrmsg=52:52; #start_bit=52, number_of_bit=1 +define tx_sls_lane_sel_gcrmsg=53:53; #start_bit=53, number_of_bit=1 +define tx_drv_sync_patt_gcrmsg=49:49; #start_bit=49, number_of_bit=1 +define tx_err_inject=48:51; #start_bit=48, number_of_bit=4 +define tx_err_inj_A_enable=52:52; #start_bit=52, number_of_bit=1 +define tx_err_inj_B_enable=53:53; #start_bit=53, number_of_bit=1 +define tx_clk_pdwn=48:48; #start_bit=48, number_of_bit=1 +define tx_clk_invert=49:49; #start_bit=49, number_of_bit=1 +define tx_clk_quiesce_p=50:51; #start_bit=50, number_of_bit=2 +define tx_clk_quiesce_n=52:53; #start_bit=52, number_of_bit=2 +define tx_pg_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 +define tx_pg_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 +define tx_pg_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 +define tx_pg_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 +define tx_pg_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 +define tx_pg_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 +define tx_pg_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 +define tx_pg_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 +define tx_clk_bist_err=48:49; #start_bit=48, number_of_bit=2 +define tx_clk_bist_done=50:51; #start_bit=50, number_of_bit=2 +#define #tx_cntl_stat_pg_spare=48:48; #start_bit=48, number_of_bit=1 +define tx_fifo_init=49:49; #start_bit=49, number_of_bit=1 +define tx_max_bad_lanes=48:52; #start_bit=48, number_of_bit=5 +define tx_msbswap=53:53; #start_bit=53, number_of_bit=1 +define tx_reset_cfg_ena=48:48; #start_bit=48, number_of_bit=1 +define tx_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 +define tx_fir_reset=63:63; #start_bit=63, number_of_bit=1 +define tx_pg_fir_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 +define tx_pg_fir_errs=48:55; #start_bit=48, number_of_bit=8 +define tx_pg_fir_err_pg_regs=48:48; #start_bit=48, number_of_bit=1 +define tx_pg_fir_err_gcr_buff=49:49; #start_bit=49, number_of_bit=1 +define tx_pg_fir_err_stat_rpr_snd_msg_sm=51:51; #start_bit=51, number_of_bit=1 +define tx_pg_fir_err_gcrs_ld_sm=52:52; #start_bit=52, number_of_bit=1 +define tx_pg_fir_err_gcrs_unld_sm=53:53; #start_bit=53, number_of_bit=1 +define tx_pl_fir_err=63:63; #start_bit=63, number_of_bit=1 +define tx_pg_fir_err_mask_full_reg=48:63; #start_bit=48, number_of_bit=16 +define tx_pg_fir_errs_mask=48:55; #start_bit=48, number_of_bit=8 +define tx_pg_fir_err_mask_pg_regs=48:48; #start_bit=48, number_of_bit=1 +define tx_pg_fir_err_mask_gcr_buff=49:49; #start_bit=49, number_of_bit=1 +define tx_pg_fir_err_mask_stat_rpr_snd_msg_sm=51:51; #start_bit=51, number_of_bit=1 +define tx_pg_fir_err_mask_gcrs_ld_sm=52:52; #start_bit=52, number_of_bit=1 +define tx_pg_fir_err_mask_gcrs_unld_sm=53:53; #start_bit=53, number_of_bit=1 +define tx_pl_fir_err_mask=63:63; #start_bit=63, number_of_bit=1 +define tx_pg_fir_err_inj_full_reg=48:63; #start_bit=48, number_of_bit=16 +define tx_pg_fir_err_inj=48:55; #start_bit=48, number_of_bit=8 +define tx_pg_fir_err_inj_pg_regs=48:48; #start_bit=48, number_of_bit=1 +define tx_pg_fir_err_inj_gcr_buff=49:49; #start_bit=49, number_of_bit=1 +define tx_pg_fir_err_inj_stat_rpr_snd_msg_sm=51:51; #start_bit=51, number_of_bit=1 +define tx_pg_fir_err_inj_gcrs_ld_sm=52:52; #start_bit=52, number_of_bit=1 +define tx_pg_fir_err_inj_gcrs_unld_sm=53:53; #start_bit=53, number_of_bit=1 +define tx_bus_id=48:53; #start_bit=48, number_of_bit=6 +define tx_group_id=55:60; #start_bit=55, number_of_bit=6 +define tx_last_group_id=48:53; #start_bit=48, number_of_bit=6 +define tx_start_lane_id=49:55; #start_bit=49, number_of_bit=7 +define tx_end_lane_id=57:63; #start_bit=57, number_of_bit=7 +define tx_drv_clk_pattern_gcrmsg=48:49; #start_bit=48, number_of_bit=2 +define tx_wt_en_all_clk_segs_gcrmsg=48:48; #start_bit=48, number_of_bit=1 +define tx_wt_en_all_data_segs_gcrmsg=49:49; #start_bit=49, number_of_bit=1 +define tx_bad_lane1_gcrmsg=48:54; #start_bit=48, number_of_bit=7 +define tx_bad_lane2_gcrmsg=55:61; #start_bit=55, number_of_bit=7 +define tx_bad_lane_code_gcrmsg=62:63; #start_bit=62, number_of_bit=2 +define tx_sls_lane_gcrmsg=48:54; #start_bit=48, number_of_bit=7 +define tx_sls_lane_val_gcrmsg=55:55; #start_bit=55, number_of_bit=1 +#define #tx_term_n_mode_enc=48:51; #start_bit=48, number_of_bit=4 +#define #tx_term_p_mode_enc=52:55; #start_bit=52, number_of_bit=4 +#define #tx_term_test_mode=56:56; #start_bit=56, number_of_bit=1 +#define #tx_termffe_n_mode_enc=57:59; #start_bit=57, number_of_bit=3 +#define #tx_termffe_p_mode_enc=61:63; #start_bit=61, number_of_bit=3 +define tx_pc_test_mode=48:48; #start_bit=48, number_of_bit=1 +#define #tx_ffe_slice_en_enc=49:51; #start_bit=49, number_of_bit=3 +define tx_main_slice_en_enc=52:55; #start_bit=52, number_of_bit=4 +#define #tx_mt_slice_en_enc=57:59; #start_bit=57, number_of_bit=3 +define tx_pc_slice_en_enc=60:63; #start_bit=60, number_of_bit=4 +define tx_slewctl=48:51; #start_bit=48, number_of_bit=4 +#define #tx_pvtnb_enc=52:53; #start_bit=52, number_of_bit=2 +#define #tx_pvtpb_enc=54:55; #start_bit=54, number_of_bit=2 +define tx_pvtnl_enc=58:59; #start_bit=58, number_of_bit=2 +define tx_pvtpl_enc=62:63; #start_bit=62, number_of_bit=2 +define tx_lane_disabled_vec_0_15=48:63; #start_bit=48, number_of_bit=16 +define tx_lane_disabled_vec_16_31=48:63; #start_bit=48, number_of_bit=16 +define tx_sls_lane_shdw_gcrmsg=48:48; #start_bit=48, number_of_bit=1 +define tx_sls_hndshk_state=48:52; #start_bit=48, number_of_bit=5 +define tx_slv_mv_sls_shdw_req_gcrmsg=48:48; #start_bit=48, number_of_bit=1 +define tx_slv_mv_sls_shdw_rpr_req_gcrmsg=49:49; #start_bit=49, number_of_bit=1 +define tx_slv_mv_sls_unshdw_req_gcrmsg=50:50; #start_bit=50, number_of_bit=1 +define tx_slv_mv_sls_unshdw_rpr_req_gcrmsg=51:51; #start_bit=51, number_of_bit=1 +define tx_bus_width=52:58; #start_bit=52, number_of_bit=7 +define tx_slv_mv_sls_rpr_req_gcrmsg=59:59; #start_bit=59, number_of_bit=1 +define tx_sls_lane_sel_lg_gcrmsg=60:60; #start_bit=60, number_of_bit=1 +define tx_sls_lane_unsel_lg_gcrmsg=61:61; #start_bit=61, number_of_bit=1 +define tx_rdt_mode=48:48; #start_bit=48, number_of_bit=1 +define tx_run_rdt=49:49; #start_bit=49, number_of_bit=1 +define tx_wt_pattern_length=48:49; #start_bit=48, number_of_bit=2 +define tx_reduced_scramble_mode=48:49; #start_bit=48, number_of_bit=2 +define tx_prbs_scramble_mode=50:51; #start_bit=50, number_of_bit=2 +define tx_ei3_mode=63:63; #start_bit=63, number_of_bit=1 +define tx_bist_en=48:48; #start_bit=48, number_of_bit=1 +define tx_bist_clr=49:49; #start_bit=49, number_of_bit=1 +define tx_snd_sls_cmd_gcrmsg=48:48; #start_bit=48, number_of_bit=1 +define tx_dyn_recal_tsr_ignore_gcrmsg=49:49; #start_bit=49, number_of_bit=1 +define tx_sls_cmd_gcrmsg=50:55; #start_bit=50, number_of_bit=6 +define tx_snd_sls_cmd_prev_gcrmsg=56:56; #start_bit=56, number_of_bit=1 +define tx_snd_sls_using_reg_scramble=57:57; #start_bit=57, number_of_bit=1 +define tx_err_inj_a_rand_beat_dis=48:48; #start_bit=48, number_of_bit=1 +define tx_err_inj_a_fine_sel=49:51; #start_bit=49, number_of_bit=3 +define tx_err_inj_a_coarse_sel=52:55; #start_bit=52, number_of_bit=4 +define tx_err_inj_a_ber_sel=58:63; #start_bit=58, number_of_bit=6 +define tx_err_inj_b_rand_beat_dis=48:48; #start_bit=48, number_of_bit=1 +define tx_err_inj_b_fine_sel=49:51; #start_bit=49, number_of_bit=3 +define tx_err_inj_b_coarse_sel=52:55; #start_bit=52, number_of_bit=4 +define tx_err_inj_b_ber_sel=58:63; #start_bit=58, number_of_bit=6 +define tx_err_inj_sls_mode=48:48; #start_bit=48, number_of_bit=1 +define tx_err_inj_sls_all_cmd=49:49; #start_bit=49, number_of_bit=1 +define tx_err_inj_sls_recal=50:50; #start_bit=50, number_of_bit=1 +define tx_err_inj_sls_cmd=58:63; #start_bit=58, number_of_bit=6 +define tx_enable_reduced_scramble=48:48; #start_bit=48, number_of_bit=1 +define tx_reset_cfg_hld=48:63; #start_bit=48, number_of_bit=16 +define tx_tdr_pulse_offset=48:59; #start_bit=48, number_of_bit=12 +define tx_tdr_pulse_width=48:59; #start_bit=48, number_of_bit=12 +define rx_mode_pl_full_reg=48:63; #start_bit=48, number_of_bit=16 +define rx_lane_pdwn=48:48; #start_bit=48, number_of_bit=1 +#define #rx_lane_invert=49:49; #start_bit=49, number_of_bit=1 +#define #rx_lane_known_bad=50:50; #start_bit=50, number_of_bit=1 +define rx_lane_scramble_disable=54:54; #start_bit=54, number_of_bit=1 +define rx_block_lock_lane=48:48; #start_bit=48, number_of_bit=1 +define rx_check_skew_lane=49:49; #start_bit=49, number_of_bit=1 +define rx_offcal_mode=51:51; #start_bit=51, number_of_bit=1 +define rx_pl_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 +define rx_pl_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 +define rx_pl_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 +define rx_pl_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 +define rx_pl_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 +define rx_pl_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 +define rx_pl_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 +define rx_pl_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 +#define #rx_lane_id_pl=48:52; #start_bit=48, number_of_bit=5 +define rx_bist_err=48:48; #start_bit=48, number_of_bit=1 +define rx_bist_done=49:49; #start_bit=49, number_of_bit=1 +#define ##rx_ddc_disable=48:48; #start_bit=48, number_of_bit=1 +#define #rx_eyeopt_stat_tbd=48:48; #start_bit=48, number_of_bit=1 +define rx_offset_even_samp1=49:55; #start_bit=49, number_of_bit=7 +#define #rx_offset_even_samp1=50:55; #start_bit=50, number_of_bit=6 +define rx_offset_even_samp0=57:63; #start_bit=57, number_of_bit=7 +#define #rx_offset_even_samp0=58:63; #start_bit=58, number_of_bit=6 +define rx_offset_odd_samp1=49:55; #start_bit=49, number_of_bit=7 +#define #rx_offset_odd_samp1=50:55; #start_bit=50, number_of_bit=6 +define rx_offset_odd_samp0=57:63; #start_bit=57, number_of_bit=7 +#define #rx_offset_odd_samp0=58:63; #start_bit=58, number_of_bit=6 +#define #rx_amp_peak=48:51; #start_bit=48, number_of_bit=4 +define rx_amp_peak=48:53; #start_bit=48, number_of_bit=6 +#define #rx_wiretest_lane_bad=48:48; #start_bit=48, number_of_bit=1 +#define #rx_lane_inverted=49:49; #start_bit=49, number_of_bit=1 +#define #rx_lane_fault_details=52:54; #start_bit=52, number_of_bit=3 +define rx_fifo_l2u_dly=48:51; #start_bit=48, number_of_bit=4 +define rx_fifo_init=52:52; #start_bit=52, number_of_bit=1 +define rx_fifo_inc_l2u_dly=48:48; #start_bit=48, number_of_bit=1 +define rx_fifo_dec_l2u_dly=49:49; #start_bit=49, number_of_bit=1 +define rx_clr_skew_valid=50:50; #start_bit=50, number_of_bit=1 +#define #rx_fifo_cntl_spare=51:51; #start_bit=51, number_of_bit=1 +define rx_bad_block_lock=48:48; #start_bit=48, number_of_bit=1 +define rx_bad_skew=49:49; #start_bit=49, number_of_bit=1 +define rx_bad_deskew=50:50; #start_bit=50, number_of_bit=1 +define rx_bad_eye_opt_ber=48:48; #start_bit=48, number_of_bit=1 +define rx_bad_eye_opt_width=49:49; #start_bit=49, number_of_bit=1 +define rx_vref =48:55; #start_bit=48, number_of_bit=8 +define rx_pl_fir_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 +define rx_pl_fir_errs=48:48; #start_bit=48, number_of_bit=1 +define rx_pl_fir_err_pl_regs=48:48; #start_bit=48, number_of_bit=1 +define rx_pl_fir_errs_mask_full_reg=48:63; #start_bit=48, number_of_bit=16 +define rx_pl_fir_errs_mask=48:48; #start_bit=48, number_of_bit=1 +define rx_pl_fir_err_mask_pl_regs=48:48; #start_bit=48, number_of_bit=1 +define rx_pl_fir_err_inj_full_reg=48:63; #start_bit=48, number_of_bit=16 +define rx_pl_fir_err_inj=48:48; #start_bit=48, number_of_bit=1 +define rx_pl_fir_err_inj_pl_regs=48:48; #start_bit=48, number_of_bit=1 +define rx_prbs_tap_id=48:50; #start_bit=48, number_of_bit=3 +define rx_some_block_locked=48:48; #start_bit=48, number_of_bit=1 +define rx_all_block_locked_b=49:49; #start_bit=49, number_of_bit=1 +define rx_some_skew_valid=50:50; #start_bit=50, number_of_bit=1 +define rx_all_skew_valid_b=51:51; #start_bit=51, number_of_bit=1 +define rx_some_prbs_synced=52:52; #start_bit=52, number_of_bit=1 +define rx_prbs_synced_b=53:53; #start_bit=53, number_of_bit=1 +define rx_skew_value=54:59; #start_bit=54, number_of_bit=6 +define rx_sls_lane_sel=48:48; #start_bit=48, number_of_bit=1 +define rx_9th_pattern_en=49:49; #start_bit=49, number_of_bit=1 +define rx_wt_lane_disabled=48:48; #start_bit=48, number_of_bit=1 +define rx_wt_lane_inverted=49:49; #start_bit=49, number_of_bit=1 +define rx_wt_lane_bad_code=50:52; #start_bit=50, number_of_bit=3 +define rx_wt_lane_status_alias=49:52; #start_bit=49, number_of_bit=4 +#define #rx_prot_cntl_pl_dummy=48:48; #start_bit=48, number_of_bit=1 +define rx_ext_sr=52:52; #start_bit=52, number_of_bit=1 +define rx_ext_sl=53:53; #start_bit=53, number_of_bit=1 +define rx_phaserot_offset=49:55; #start_bit=49, number_of_bit=7 +define rx_phaserot_val=49:55; #start_bit=49, number_of_bit=7 +#define #rx_phaserot_left_edge=49:55; #start_bit=49, number_of_bit=7 +#define #rx_phaserot_gb_hist_valid=48:48; #start_bit=48, number_of_bit=1 +#define #rx_phaserot_gb_hist=51:55; #start_bit=51, number_of_bit=5 +define rx_eye_width=50:55; #start_bit=50, number_of_bit=6 +define rx_hist_min_eye_width_valid=56:56; #start_bit=56, number_of_bit=1 +define rx_hist_min_eye_width=58:63; #start_bit=58, number_of_bit=6 +define rx_reset_hist_eye_width_min=48:48; #start_bit=48, number_of_bit=1 +define rx_ber_count=48:55; #start_bit=48, number_of_bit=8 +define rx_ber_count_saturated=56:56; #start_bit=56, number_of_bit=1 +define rx_ber_count_frozen_by_lane=57:57; #start_bit=57, number_of_bit=1 +define rx_ber_count_frozen_by_timer=58:58; #start_bit=58, number_of_bit=1 +define rx_ber_timer_saturated=59:59; #start_bit=59, number_of_bit=1 +define rx_ber_timer_value_0_15=48:63; #start_bit=48, number_of_bit=16 +define rx_ber_timer_value_16_31=48:63; #start_bit=48, number_of_bit=16 +define rx_ber_timer_value_32_39=48:55; #start_bit=48, number_of_bit=8 +define rx_servo_op_done=48:48; #start_bit=48, number_of_bit=1 +define rx_servo_op_all_done_b=49:49; #start_bit=49, number_of_bit=1 +define rx_servo_op=50:54; #start_bit=50, number_of_bit=5 +define rx_fifo_out_0_15=48:63; #start_bit=48, number_of_bit=16 +define rx_fifo_out_16_31=48:63; #start_bit=48, number_of_bit=16 +define rx_fifo_out_32_47=48:63; #start_bit=48, number_of_bit=16 +define rx_ln_trc_en=48:48; #start_bit=48, number_of_bit=1 +define rx_servo_ber_count=48:59; #start_bit=48, number_of_bit=12 +define rx_clk_pdwn=48:48; #start_bit=48, number_of_bit=1 +define rx_clk_invert=49:49; #start_bit=49, number_of_bit=1 +define rx_pg_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 +define rx_pg_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 +define rx_pg_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 +define rx_pg_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 +define rx_pg_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 +define rx_pg_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 +define rx_pg_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 +define rx_pg_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 +define rx_master_mode=48:48; #start_bit=48, number_of_bit=1 +define rx_disable_fence_reset=49:49; #start_bit=49, number_of_bit=1 +define rx_reset_cfg_ena=48:48; #start_bit=48, number_of_bit=1 +define rx_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 +define rx_fir_reset=63:63; #start_bit=63, number_of_bit=1 +define rx_bus_id=48:53; #start_bit=48, number_of_bit=6 +define rx_group_id=55:60; #start_bit=55, number_of_bit=6 +define rx_last_group_id=48:53; #start_bit=48, number_of_bit=6 +define rx_start_lane_id=49:55; #start_bit=49, number_of_bit=7 +define rx_end_lane_id=57:63; #start_bit=57, number_of_bit=7 +define rx_sls_disable=48:48; #start_bit=48, number_of_bit=1 +define tx_sls_disable=49:49; #start_bit=49, number_of_bit=1 +define rx_sls_cntr_tap_pts=50:51; #start_bit=50, number_of_bit=2 +define rx_nonsls_cntr_tap_pts=52:53; #start_bit=52, number_of_bit=2 +define rx_sls_err_chk_run=54:54; #start_bit=54, number_of_bit=1 +define rx_start_wderf_alias=48:52; #start_bit=48, number_of_bit=5 +define rx_start_wiretest=48:48; #start_bit=48, number_of_bit=1 +define rx_start_deskew=49:49; #start_bit=49, number_of_bit=1 +define rx_start_eye_opt=50:50; #start_bit=50, number_of_bit=1 +define rx_start_repair=51:51; #start_bit=51, number_of_bit=1 +define rx_start_func_mode=52:52; #start_bit=52, number_of_bit=1 +define rx_start_bist=53:53; #start_bit=53, number_of_bit=1 +define rx_start_offset_cal=54:54; #start_bit=54, number_of_bit=1 +define rx_start_wt_bypass=55:55; #start_bit=55, number_of_bit=1 +define rx_wderf_done_alias=48:52; #start_bit=48, number_of_bit=5 +define rx_wiretest_done=48:48; #start_bit=48, number_of_bit=1 +define rx_deskew_done=49:49; #start_bit=49, number_of_bit=1 +define rx_eye_opt_done=50:50; #start_bit=50, number_of_bit=1 +define rx_repair_done=51:51; #start_bit=51, number_of_bit=1 +define rx_func_mode_done=52:52; #start_bit=52, number_of_bit=1 +define rx_bist_started=53:53; #start_bit=53, number_of_bit=1 +define rx_offset_cal_done=54:54; #start_bit=54, number_of_bit=1 +define rx_wt_bypass_done=55:55; #start_bit=55, number_of_bit=1 +define rx_wderf_failed_alias=56:60; #start_bit=56, number_of_bit=5 +define rx_wiretest_failed=56:56; #start_bit=56, number_of_bit=1 +define rx_deskew_failed=57:57; #start_bit=57, number_of_bit=1 +define rx_eye_opt_failed=58:58; #start_bit=58, number_of_bit=1 +define rx_repair_failed=59:59; #start_bit=59, number_of_bit=1 +define rx_func_mode_failed=60:60; #start_bit=60, number_of_bit=1 +define rx_start_bist_failed=61:61; #start_bit=61, number_of_bit=1 +define rx_offset_cal_failed=62:62; #start_bit=62, number_of_bit=1 +define rx_wt_bypass_failed=63:63; #start_bit=63, number_of_bit=1 +define rx_recal_status=48:63; #start_bit=48, number_of_bit=16 +define rx_wt_check_count=48:52; #start_bit=48, number_of_bit=5 +define rx_wt_check_lanes=53:54; #start_bit=53, number_of_bit=2 +define rx_wt_enable_term_mode=55:55; #start_bit=55, number_of_bit=1 +define rx_wt_term_phase=56:56; #start_bit=56, number_of_bit=1 +define rx_wt_term_mode_enc=57:61; #start_bit=57, number_of_bit=5 +define rx_sls_timeout_sel=48:50; #start_bit=48, number_of_bit=3 +define rx_ds_bl_timeout_sel=51:53; #start_bit=51, number_of_bit=3 +define rx_cl_timeout_sel=54:56; #start_bit=54, number_of_bit=3 +define rx_wt_timeout_sel=57:59; #start_bit=57, number_of_bit=3 +define rx_ds_timeout_sel=60:62; #start_bit=60, number_of_bit=3 +define rx_eo_offset_timeout_sel=48:50; #start_bit=48, number_of_bit=3 +define rx_eo_vref_timeout_sel=51:53; #start_bit=51, number_of_bit=3 +define rx_eo_ctle_timeout_sel=54:56; #start_bit=54, number_of_bit=3 +define rx_eo_et_timeout_sel=60:62; #start_bit=60, number_of_bit=3 +define rx_eo_final_l2u_timeout_sel=63:63; #start_bit=63, number_of_bit=1 +define rx_func_mode_timeout_sel=48:50; #start_bit=48, number_of_bit=3 +define rx_rc_slowdown_timeout_sel=51:53; #start_bit=51, number_of_bit=3 +define rx_pup_lite_wait_sel=54:55; #start_bit=54, number_of_bit=2 +define rx_fifo_initial_l2u_dly=48:51; #start_bit=48, number_of_bit=4 +define rx_fifo_final_l2u_dly=52:55; #start_bit=52, number_of_bit=4 +define rx_fifo_max_deskew=56:59; #start_bit=56, number_of_bit=4 +define rx_fifo_final_l2u_min_err_thresh=60:61; #start_bit=60, number_of_bit=2 +#define #rx_start_at_state_en=48:48; #start_bit=48, number_of_bit=1 +#define #rx_stop_at_state_en=49:49; #start_bit=49, number_of_bit=1 +#define #rx_state_stopped=50:50; #start_bit=50, number_of_bit=1 +#define #rx_cur_state=51:58; #start_bit=51, number_of_bit=8 +#define #rx_start_state=48:55; #start_bit=48, number_of_bit=8 +#define #rx_stop_state=56:63; #start_bit=56, number_of_bit=8 +define rx_sls_cmd_val=48:48; #start_bit=48, number_of_bit=1 +define rx_sls_cmd_encode=50:55; #start_bit=50, number_of_bit=6 +define rx_sls_err_chk_cnt=56:63; #start_bit=56, number_of_bit=8 +define rx_pg_fir_training_error=48:48; #start_bit=48, number_of_bit=1 +define rx_pg_fir_static_spare_deployed=49:49; #start_bit=49, number_of_bit=1 +define rx_pg_fir_static_max_spares_exceeded=50:50; #start_bit=50, number_of_bit=1 +define rx_pg_fir_dynamic_repair_error=51:51; #start_bit=51, number_of_bit=1 +define rx_pg_fir_dynamic_spare_deployed=52:52; #start_bit=52, number_of_bit=1 +define rx_pg_fir_dynamic_max_spares_exceeded=53:53; #start_bit=53, number_of_bit=1 +define rx_pg_fir_recal_error=54:54; #start_bit=54, number_of_bit=1 +define rx_pg_fir_recal_spare_deployed=55:55; #start_bit=55, number_of_bit=1 +define rx_pg_fir_recal_max_spares_exceeded=56:56; #start_bit=56, number_of_bit=1 +define rx_pg_fir_too_many_bus_errors=57:57; #start_bit=57, number_of_bit=1 +define rx_pg_fir_training_error_mask=48:48; #start_bit=48, number_of_bit=1 +define rx_pg_fir_static_spare_deployed_mask=49:49; #start_bit=49, number_of_bit=1 +define rx_pg_fir_static_max_spares_exceeded_mask=50:50; #start_bit=50, number_of_bit=1 +define rx_pg_fir_dynamic_repair_error_mask=51:51; #start_bit=51, number_of_bit=1 +define rx_pg_fir_dynamic_spare_deployed_mask=52:52; #start_bit=52, number_of_bit=1 +define rx_pg_fir_dynamic_max_spares_exceeded_mask=53:53; #start_bit=53, number_of_bit=1 +define rx_pg_fir_recal_error_mask=54:54; #start_bit=54, number_of_bit=1 +define rx_pg_fir_recal_spare_deployed_mask=55:55; #start_bit=55, number_of_bit=1 +define rx_pg_fir_recal_max_spares_exceeded_mask=56:56; #start_bit=56, number_of_bit=1 +define rx_pg_fir_too_many_bus_errors_mask=57:57; #start_bit=57, number_of_bit=1 +define rx_pg_fir1_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 +define rx_pg_fir1_errs=48:61; #start_bit=48, number_of_bit=14 +define rx_pg_fir_err_pg_regs=48:48; #start_bit=48, number_of_bit=1 +define rx_pg_fir_err_gcr_buff=49:49; #start_bit=49, number_of_bit=1 +define rx_pg_fir_err_gcrs_ld_sm=51:51; #start_bit=51, number_of_bit=1 +define rx_pg_fir_err_gcrs_unld_sm=52:52; #start_bit=52, number_of_bit=1 +define rx_pg_fir_err_glb_init_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 +define rx_pg_fir_err_main_init_sm=54:54; #start_bit=54, number_of_bit=1 +define rx_pg_fir_err_wtm_sm=55:55; #start_bit=55, number_of_bit=1 +define rx_pg_fir_err_wtr_sm=56:56; #start_bit=56, number_of_bit=1 +define rx_pg_fir_err_wtl_sm=57:57; #start_bit=57, number_of_bit=1 +define rx_pg_fir_err_rpr_sm=58:58; #start_bit=58, number_of_bit=1 +define rx_pg_fir_err_eyeopt_sm=59:59; #start_bit=59, number_of_bit=1 +define rx_pg_fir_err_dsm_sm=60:60; #start_bit=60, number_of_bit=1 +define rx_pg_fir_err_rxdsm_sm=61:61; #start_bit=61, number_of_bit=1 +define rx_pg_chan_fail_rsvd=62:62; #start_bit=62, number_of_bit=1 +define rx_pl_fir_err=63:63; #start_bit=63, number_of_bit=1 +define rx_pg_fir2_errs_full_reg=48:54; #start_bit=48, number_of_bit=7 +define rx_pg_fir2_errs=48:54; #start_bit=48, number_of_bit=7 +define rx_pg_fir_err_dyn_rpr_sm=48:48; #start_bit=48, number_of_bit=1 +define rx_pg_fir_err_sls_hndshk_sm=49:49; #start_bit=49, number_of_bit=1 +define rx_pg_fir_err_dyn_rpr_snd_msg_sm=50:50; #start_bit=50, number_of_bit=1 +define rx_pg_fir_err_recal_sm=51:51; #start_bit=51, number_of_bit=1 +define rx_pg_fir_err_sls_enc_snd_msg_sm=52:52; #start_bit=52, number_of_bit=1 +define rx_pg_fir_err_glb_cal_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 +define rx_pg_fir_err_stat_rpr_snd_msg_sm=54:54; #start_bit=54, number_of_bit=1 +define rx_pg_fir1_errs_mask_full_reg=48:63; #start_bit=48, number_of_bit=16 +define rx_pg_fir1_errs_mask=48:61; #start_bit=48, number_of_bit=14 +define rx_pg_fir_err_mask_pg_regs=48:48; #start_bit=48, number_of_bit=1 +define rx_pg_fir_err_mask_gcr_buff=49:49; #start_bit=49, number_of_bit=1 +define rx_pg_fir_err_mask_gcrs_ld_sm=51:51; #start_bit=51, number_of_bit=1 +define rx_pg_fir_err_mask_gcrs_unld_sm=52:52; #start_bit=52, number_of_bit=1 +define rx_pg_fir_err_mask_glb_init_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 +define rx_pg_fir_err_mask_main_init_sm=54:54; #start_bit=54, number_of_bit=1 +define rx_pg_fir_err_mask_wtm_sm=55:55; #start_bit=55, number_of_bit=1 +define rx_pg_fir_err_mask_wtr_sm=56:56; #start_bit=56, number_of_bit=1 +define rx_pg_fir_err_mask_wtl_sm=57:57; #start_bit=57, number_of_bit=1 +define rx_pg_fir_err_mask_rpr_sm=58:58; #start_bit=58, number_of_bit=1 +define rx_pg_fir_err_mask_eyeopt_sm=59:59; #start_bit=59, number_of_bit=1 +define rx_pg_fir_err_mask_dsm_sm=60:60; #start_bit=60, number_of_bit=1 +define rx_pg_fir_err_mask_rxdsm_sm=61:61; #start_bit=61, number_of_bit=1 +define rx_pl_fir_err_mask=63:63; #start_bit=63, number_of_bit=1 +define rx_pg_fir2_errs_mask_full_reg=48:54; #start_bit=48, number_of_bit=7 +define rx_pg_fir2_errs_mask=48:54; #start_bit=48, number_of_bit=7 +define rx_pg_fir_err_mask_dyn_rpr_sm=48:48; #start_bit=48, number_of_bit=1 +define rx_pg_fir_err_mask_sls_hndshk_sm=49:49; #start_bit=49, number_of_bit=1 +define rx_pg_fir_err_mask_dyn_rpr_snd_msg_sm=50:50; #start_bit=50, number_of_bit=1 +define rx_pg_fir_err_mask_recal_sm=51:51; #start_bit=51, number_of_bit=1 +define rx_pg_fir_err_mask_sls_enc_snd_msg_sm=52:52; #start_bit=52, number_of_bit=1 +define rx_pg_fir_err_mask_glb_cal_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 +define rx_pg_fir_err_mask_stat_rpr_snd_msg_sm=54:54; #start_bit=54, number_of_bit=1 +define rx_pg_fir1_err_inj_full_reg=48:63; #start_bit=48, number_of_bit=16 +define rx_pg_fir1_err_inj=48:61; #start_bit=48, number_of_bit=14 +define rx_pg_fir_err_inj_pg_regs=48:48; #start_bit=48, number_of_bit=1 +define rx_pg_fir_err_inj_gcr_buff=49:49; #start_bit=49, number_of_bit=1 +define rx_pg_fir_err_inj_gcrs_ld_sm=51:51; #start_bit=51, number_of_bit=1 +define rx_pg_fir_err_inj_gcrs_unld_sm=52:52; #start_bit=52, number_of_bit=1 +define rx_pg_fir_err_inj_glb_init_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 +define rx_pg_fir_err_inj_main_init_sm=54:54; #start_bit=54, number_of_bit=1 +define rx_pg_fir_err_inj_wtm_sm=55:55; #start_bit=55, number_of_bit=1 +define rx_pg_fir_err_inj_wtr_sm=56:56; #start_bit=56, number_of_bit=1 +define rx_pg_fir_err_inj_wtl_sm=57:57; #start_bit=57, number_of_bit=1 +define rx_pg_fir_err_inj_rpr_sm=58:58; #start_bit=58, number_of_bit=1 +define rx_pg_fir_err_inj_eyeopt_sm=59:59; #start_bit=59, number_of_bit=1 +define rx_pg_fir_err_inj_dsm_sm=60:60; #start_bit=60, number_of_bit=1 +define rx_pg_fir_err_inj_rxdsm_sm=61:61; #start_bit=61, number_of_bit=1 +define rx_pg_fir2_err_inj_full_reg=48:54; #start_bit=48, number_of_bit=7 +define rx_pg_fir2_err_inj=48:54; #start_bit=48, number_of_bit=7 +define rx_pg_fir_err_inj_dyn_rpr_sm=48:48; #start_bit=48, number_of_bit=1 +define rx_pg_fir_err_inj_sls_hndshk_sm=49:49; #start_bit=49, number_of_bit=1 +define rx_pg_fir_err_inj_dyn_rpr_snd_msg_sm=50:50; #start_bit=50, number_of_bit=1 +define rx_pg_fir_err_inj_recal_sm=51:51; #start_bit=51, number_of_bit=1 +define rx_pg_fir_err_inj_sls_enc_snd_msg_sm=52:52; #start_bit=52, number_of_bit=1 +define rx_pg_fir_err_inj_glb_cal_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 +define rx_pg_fir_err_inj_stat_rpr_snd_msg_sm=54:54; #start_bit=54, number_of_bit=1 +define rx_lane_bad_vec_0_15=48:63; #start_bit=48, number_of_bit=16 +define rx_lane_bad_vec_16_31=48:63; #start_bit=48, number_of_bit=16 +define rx_lane_disabled_vec_0_15=48:63; #start_bit=48, number_of_bit=16 +define rx_lane_disabled_vec_16_31=48:63; #start_bit=48, number_of_bit=16 +define rx_lane_swapped_vec_0_15=48:63; #start_bit=48, number_of_bit=16 +define rx_lane_swapped_vec_16_31=48:63; #start_bit=48, number_of_bit=16 +define rx_main_init_state=48:51; #start_bit=48, number_of_bit=4 +define rx_wtm_state=48:52; #start_bit=48, number_of_bit=5 +define rx_wtr_state=53:56; #start_bit=53, number_of_bit=4 +define rx_wtl_state=59:63; #start_bit=59, number_of_bit=5 +define rx_wtl_done_alias=59:59; #start_bit=59, number_of_bit=1 +define rx_wtl_p_n_swap_alias=60:60; #start_bit=60, number_of_bit=1 +define rx_wtl_fault_code_alias=61:63; #start_bit=61, number_of_bit=3 +define rx_wtr_cur_lane=48:52; #start_bit=48, number_of_bit=5 +define rx_wtr_max_bad_lanes=53:57; #start_bit=53, number_of_bit=5 +define rx_wtr_bad_lane_count=59:63; #start_bit=59, number_of_bit=5 +define rx_wt_prev_done_gcrmsg=48:48; #start_bit=48, number_of_bit=1 +define rx_wt_all_done_gcrmsg=49:49; #start_bit=49, number_of_bit=1 +define rx_wt_cu_pll_pgood=48:48; #start_bit=48, number_of_bit=1 +define rx_wt_cu_pll_reset=49:49; #start_bit=49, number_of_bit=1 +define rx_wt_cu_pll_pgooddly=50:52; #start_bit=50, number_of_bit=3 +define rx_wt_cu_pll_lock=53:53; #start_bit=53, number_of_bit=1 +define rx_wt_pll_refclksel=54:54; #start_bit=54, number_of_bit=1 +define rx_dll1_cal_good=48:48; #start_bit=48, number_of_bit=1 +define rx_dll1_cal_error=49:49; #start_bit=49, number_of_bit=1 +define rx_dll1_cal_error_fine=50:50; #start_bit=50, number_of_bit=1 +define rx_dll1_cal_skip=51:52; #start_bit=51, number_of_bit=2 +define rx_dll1_coarse_adj_by2=53:53; #start_bit=53, number_of_bit=1 +define rx_dll2_cal_good=56:56; #start_bit=56, number_of_bit=1 +define rx_dll2_cal_error=57:57; #start_bit=57, number_of_bit=1 +define rx_dll2_cal_error_fine=58:58; #start_bit=58, number_of_bit=1 +define rx_dll2_cal_skip=59:60; #start_bit=59, number_of_bit=2 +define rx_dll2_coarse_adj_by2=61:61; #start_bit=61, number_of_bit=1 +define rx_dll1_coarse_en=48:53; #start_bit=48, number_of_bit=6 +define rx_dll1_vreg_dac_coarse=55:61; #start_bit=55, number_of_bit=7 +define rx_dll1_vreg_dac_lower=48:62; #start_bit=48, number_of_bit=15 +define rx_dll1_vreg_dac_upper=48:62; #start_bit=48, number_of_bit=15 +define rx_dll2_coarse_en=48:53; #start_bit=48, number_of_bit=6 +define rx_dll2_vreg_dac_coarse=55:61; #start_bit=55, number_of_bit=7 +define rx_dll2_vreg_dac_lower=48:62; #start_bit=48, number_of_bit=15 +define rx_dll2_vreg_dac_upper=48:62; #start_bit=48, number_of_bit=15 +define rx_dll_dll_filter_length=48:50; #start_bit=48, number_of_bit=3 +define rx_dll_dll_lead_lag_separation=52:54; #start_bit=52, number_of_bit=3 +define rx_dll_vreg_con=48:48; #start_bit=48, number_of_bit=1 +define rx_dll_vreg_compcon=49:51; #start_bit=49, number_of_bit=3 +define rx_dll_vreg_ref_sel=52:54; #start_bit=52, number_of_bit=3 +define rx_dll1_vreg_drvcon=55:57; #start_bit=55, number_of_bit=3 +define rx_dll2_vreg_drvcon=58:60; #start_bit=58, number_of_bit=3 +define rx_dll_vreg_dac_pullup=61:61; #start_bit=61, number_of_bit=1 +define rx_deskew_seq_gcrmsg=48:50; #start_bit=48, number_of_bit=3 +define rx_deskew_skmin_gcrmsg=52:57; #start_bit=52, number_of_bit=6 +define rx_deskew_skmax_gcrmsg=58:63; #start_bit=58, number_of_bit=6 +define rx_dsm_state=50:55; #start_bit=50, number_of_bit=6 +define rx_rxdsm_state=57:63; #start_bit=57, number_of_bit=7 +define rx_deskew_max_limit=48:53; #start_bit=48, number_of_bit=6 +define rx_deskew_minskew_grp=48:53; #start_bit=48, number_of_bit=6 +define rx_deskew_maxskew_grp=54:59; #start_bit=54, number_of_bit=6 +define rx_bad_lane1_gcrmsg=48:54; #start_bit=48, number_of_bit=7 +define rx_bad_lane2_gcrmsg=55:61; #start_bit=55, number_of_bit=7 +define rx_bad_lane_code_gcrmsg=62:63; #start_bit=62, number_of_bit=2 +define rx_rpr_state=48:53; #start_bit=48, number_of_bit=6 +define rx_func_mode_state=48:51; #start_bit=48, number_of_bit=4 +define rx_tx_bus_width=48:54; #start_bit=48, number_of_bit=7 +define rx_rx_bus_width=55:61; #start_bit=55, number_of_bit=7 +define rx_sls_lane_gcrmsg=48:54; #start_bit=48, number_of_bit=7 +define rx_sls_lane_val_gcrmsg=55:55; #start_bit=55, number_of_bit=1 +define rx_fence =48:48; #start_bit=48, number_of_bit=1 +define rx_term_test_mode=48:48; #start_bit=48, number_of_bit=1 +#define #rx_term_n_mode_enc=48:51; #start_bit=48, number_of_bit=4 +define rx_term_mode_enc=51:55; #start_bit=51, number_of_bit=5 +#define #rx_termffe_n_mode_enc=57:59; #start_bit=57, number_of_bit=3 +#define #rx_termffe_p_mode_enc=61:63; #start_bit=61, number_of_bit=3 +#define #rx_pc_test_mode=48:48; #start_bit=48, number_of_bit=1 +#define #rx_ffe_slice_en_enc=49:51; #start_bit=49, number_of_bit=3 +#define #rx_main_slice_en_enc=52:55; #start_bit=52, number_of_bit=4 +#define #rx_mt_slice_en_enc=57:59; #start_bit=57, number_of_bit=3 +#define #rx_pc_slice_en_enc=60:63; #start_bit=60, number_of_bit=4 +#define #rx_slewctl=48:51; #start_bit=48, number_of_bit=4 +define rx_iref_bc=52:54; #start_bit=52, number_of_bit=3 +define rx_iref_bypass=55:55; #start_bit=55, number_of_bit=1 +define rx_dyn_rpr_state=50:55; #start_bit=50, number_of_bit=6 +define rx_sls_hndshk_state=56:63; #start_bit=56, number_of_bit=8 +define rx_dyn_rpr_req_gcrmsg=48:48; #start_bit=48, number_of_bit=1 +define rx_dyn_rpr_lane2rpr_gcrmsg=49:55; #start_bit=49, number_of_bit=7 +define rx_dyn_rpr_ip_gcrmsg=56:56; #start_bit=56, number_of_bit=1 +define rx_dyn_rpr_complete_gcrmsg=57:57; #start_bit=57, number_of_bit=1 +define rx_dyn_rpr_bad_lane_max=48:54; #start_bit=48, number_of_bit=7 +define rx_dyn_rpr_err_cntr1_duration=55:58; #start_bit=55, number_of_bit=4 +define rx_dyn_rpr_clr_err_cntr1=59:59; #start_bit=59, number_of_bit=1 +define rx_dyn_rpr_disable=60:60; #start_bit=60, number_of_bit=1 +define rx_dyn_rpr_enc_bad_data_lane_width=61:63; #start_bit=61, number_of_bit=3 +define rx_gcr_msg_debug_dest_bus_id=48:53; #start_bit=48, number_of_bit=6 +define rx_gcr_msg_debug_dest_group_id=54:59; #start_bit=54, number_of_bit=6 +define rx_gcr_msg_debug_src_bus_id=48:53; #start_bit=48, number_of_bit=6 +define rx_gcr_msg_debug_src_group_id=54:59; #start_bit=54, number_of_bit=6 +define rx_gcr_msg_debug_dest_addr=48:56; #start_bit=48, number_of_bit=9 +define rx_gcr_msg_debug_send_msg=63:63; #start_bit=63, number_of_bit=1 +define rx_gcr_msg_debug_write_data=48:63; #start_bit=48, number_of_bit=16 +define rx_eye_opt_state=48:55; #start_bit=48, number_of_bit=8 +define rx_recal_state=56:63; #start_bit=56, number_of_bit=8 +define rx_wt_clk_lane_inverted=49:49; #start_bit=49, number_of_bit=1 +define rx_wt_clk_lane_bad_code=50:52; #start_bit=50, number_of_bit=3 +define rx_wt_clk_lane_status_alias=49:52; #start_bit=49, number_of_bit=4 +define rx_eo_enable_latch_offset_cal=48:48; #start_bit=48, number_of_bit=1 +define rx_eo_enable_ctle_cal=49:49; #start_bit=49, number_of_bit=1 +define rx_eo_enable_vref_cal=51:51; #start_bit=51, number_of_bit=1 +define rx_eo_enable_measure_eye_width=55:55; #start_bit=55, number_of_bit=1 +define rx_eo_enable_final_l2u_adj=56:56; #start_bit=56, number_of_bit=1 +define rx_eo_enable_ber_test=57:57; #start_bit=57, number_of_bit=1 +define rx_eo_enable_result_check=58:58; #start_bit=58, number_of_bit=1 +define rx_rc_enable_edge_track=51:51; #start_bit=51, number_of_bit=1 +define rx_rc_enable_measure_eye_width=55:55; #start_bit=55, number_of_bit=1 +define rx_rc_enable_result_check=57:57; #start_bit=57, number_of_bit=1 +define rx_rc_enable_dll_update=58:58; #start_bit=58, number_of_bit=1 +define rx_eo_latch_offset_done=48:48; #start_bit=48, number_of_bit=1 +define rx_eo_ctle_done=49:49; #start_bit=49, number_of_bit=1 +define rx_eo_vref_done=51:51; #start_bit=51, number_of_bit=1 +define rx_eo_measure_eye_width_done=55:55; #start_bit=55, number_of_bit=1 +define rx_eo_final_l2u_adj_done=56:56; #start_bit=56, number_of_bit=1 +define rx_eo_result_check_done=59:59; #start_bit=59, number_of_bit=1 +define rx_eo_latch_offset_failed=48:48; #start_bit=48, number_of_bit=1 +define rx_eo_ctle_failed=49:49; #start_bit=49, number_of_bit=1 +define rx_eo_vref_failed=51:51; #start_bit=51, number_of_bit=1 +define rx_eo_measure_eye_width_failed=55:55; #start_bit=55, number_of_bit=1 +define rx_eo_final_l2u_adj_failed=56:56; #start_bit=56, number_of_bit=1 +define rx_eo_result_check_failed=57:57; #start_bit=57, number_of_bit=1 +#define #rx_amp_peak_work=48:51; #start_bit=48, number_of_bit=4 +#define #rx_amp_peak_work=48:53; #start_bit=48, number_of_bit=6 +define rx_servo_ber_count_work=48:59; #start_bit=48, number_of_bit=12 +define rx_eo_final_l2u_dly_seq_gcrmsg=48:49; #start_bit=48, number_of_bit=2 +define rx_eo_final_l2u_dly_maxchg_gcrmsg=50:55; #start_bit=50, number_of_bit=6 +define rx_eo_final_l2u_dly_chg=58:63; #start_bit=58, number_of_bit=6 +define rx_sls_rcvy_disable=48:48; #start_bit=48, number_of_bit=1 +define rx_sls_rcvy_state=51:55; #start_bit=51, number_of_bit=5 +define rx_sls_rcvy_req_gcrmsg=48:48; #start_bit=48, number_of_bit=1 +define rx_sls_rcvy_ip_gcrmsg=49:49; #start_bit=49, number_of_bit=1 +define rx_sls_rcvy_done_gcrmsg=50:50; #start_bit=50, number_of_bit=1 +define rx_tx_bad_lane_cntr_gcrmsg=48:49; #start_bit=48, number_of_bit=2 +define rx_dis_synd_tallying_gcrmsg=48:48; #start_bit=48, number_of_bit=1 +define rx_run_rdt=48:48; #start_bit=48, number_of_bit=1 +define rx_rdt_check_mask=50:54; #start_bit=50, number_of_bit=5 +define rx_rdt_failed=55:55; #start_bit=55, number_of_bit=1 +define rx_trc_mode=48:51; #start_bit=48, number_of_bit=4 +define rx_trc_grp=54:59; #start_bit=54, number_of_bit=6 +define rx_dyn_rpr_bad_lane_valid_debug=48:48; #start_bit=48, number_of_bit=1 +define rx_dyn_rpr_enc_bad_data_lane_debug=49:55; #start_bit=49, number_of_bit=7 +define rx_bad_bus_err_cntr=57:63; #start_bit=57, number_of_bit=7 +define rx_bad_bus_lane_err_cntr_dis_clr=48:48; #start_bit=48, number_of_bit=1 +define rx_bad_bus_lane_err_cntr=49:55; #start_bit=49, number_of_bit=7 +define rx_last_bad_bus_lane=57:63; #start_bit=57, number_of_bit=7 +define rx_dyn_rpr_bad_bus_max=48:54; #start_bit=48, number_of_bit=7 +define rx_dyn_rpr_err_cntr2_duration=55:58; #start_bit=55, number_of_bit=4 +define rx_dyn_rpr_clr_err_cntr2=59:59; #start_bit=59, number_of_bit=1 +define rx_min_eye_width=50:55; #start_bit=50, number_of_bit=6 +define rx_stop_state_enable=48:48; #start_bit=48, number_of_bit=1 +define rx_state_stopped=49:49; #start_bit=49, number_of_bit=1 +define rx_resume_from_stop=50:50; #start_bit=50, number_of_bit=1 +define rx_stop_addr_msb=56:59; #start_bit=56, number_of_bit=4 +define rx_stop_mask_msb=60:63; #start_bit=60, number_of_bit=4 +define rx_stop_addr_lsb=48:63; #start_bit=48, number_of_bit=16 +define rx_stop_mask_lsb=48:63; #start_bit=48, number_of_bit=16 +define rx_slv_shdw_done_fin_gcrmsg=48:48; #start_bit=48, number_of_bit=1 +define rx_slv_shdw_nop_fin_gcrmsg=49:49; #start_bit=49, number_of_bit=1 +define rx_slv_shdw_rpr_done_fin_gcrmsg=50:50; #start_bit=50, number_of_bit=1 +define rx_slv_shdw_rpr_nop_fin_gcrmsg=51:51; #start_bit=51, number_of_bit=1 +define rx_slv_unshdw_done_fin_gcrmsg=52:52; #start_bit=52, number_of_bit=1 +define rx_slv_unshdw_nop_fin_gcrmsg=53:53; #start_bit=53, number_of_bit=1 +define rx_slv_unshdw_rpr_done_fin_gcrmsg=54:54; #start_bit=54, number_of_bit=1 +define rx_slv_unshdw_rpr_nop_fin_gcrmsg=55:55; #start_bit=55, number_of_bit=1 +define rx_slv_recal_done_nop_fin_gcrmsg=56:56; #start_bit=56, number_of_bit=1 +define rx_slv_recal_fail_nop_fin_gcrmsg=57:57; #start_bit=57, number_of_bit=1 +define rx_slv_recal_presults_fin_gcrmsg=58:58; #start_bit=58, number_of_bit=1 +define rx_slv_recal_fresults_fin_gcrmsg=59:59; #start_bit=59, number_of_bit=1 +define rx_slv_recal_abort_ack_fin_gcrmsg=60:60; #start_bit=60, number_of_bit=1 +define rx_slv_recal_abort_mnop_fin_gcrmsg=61:61; #start_bit=61, number_of_bit=1 +define rx_slv_recal_abort_snop_fin_gcrmsg=62:62; #start_bit=62, number_of_bit=1 +define rx_reduced_scramble_mode=48:49; #start_bit=48, number_of_bit=2 +define rx_prbs_scramble_mode=50:51; #start_bit=50, number_of_bit=2 +define rx_act_check_timeout_sel=52:54; #start_bit=52, number_of_bit=3 +define rx_block_lock_timeout_sel=55:57; #start_bit=55, number_of_bit=3 +define rx_bit_lock_timeout_sel=58:60; #start_bit=58, number_of_bit=3 +define rx_reverse_shift=62:62; #start_bit=62, number_of_bit=1 +define rx_ei3_mode=63:63; #start_bit=63, number_of_bit=1 +define rx_pp_trc_mode=48:50; #start_bit=48, number_of_bit=3 +define rx_bist_jitter_pulse_sel=51:52; #start_bit=51, number_of_bit=2 +define rx_bist_min_eye_width=53:59; #start_bit=53, number_of_bit=7 +define rx_dis_block_lock_vref=60:60; #start_bit=60, number_of_bit=1 +define rx_wt_pattern_length=61:62; #start_bit=61, number_of_bit=2 +define rx_servo_timeout_sel_A=48:51; #start_bit=48, number_of_bit=4 +define rx_servo_timeout_sel_B=52:55; #start_bit=52, number_of_bit=4 +define rx_servo_timeout_sel_C=56:59; #start_bit=56, number_of_bit=4 +define rx_servo_timeout_sel_D=60:63; #start_bit=60, number_of_bit=4 +define rx_servo_timeout_sel_E=48:51; #start_bit=48, number_of_bit=4 +define rx_servo_timeout_sel_F=52:55; #start_bit=52, number_of_bit=4 +define rx_servo_timeout_sel_G=56:59; #start_bit=56, number_of_bit=4 +define rx_servo_timeout_sel_H=60:63; #start_bit=60, number_of_bit=4 +define rx_recal_timeout_sel_A=48:51; #start_bit=48, number_of_bit=4 +define rx_recal_timeout_sel_E=48:51; #start_bit=48, number_of_bit=4 +define rx_recal_timeout_sel_F=52:55; #start_bit=52, number_of_bit=4 +#define #rx_block_lock=48:48; #start_bit=48, number_of_bit=1 +define rx_prbs_check_sync=49:49; #start_bit=49, number_of_bit=1 +define rx_enable_reduced_scramble=50:50; #start_bit=50, number_of_bit=1 +define rx_prbs_inc=51:51; #start_bit=51, number_of_bit=1 +define rx_prbs_dec=52:52; #start_bit=52, number_of_bit=1 +define rx_recal_in_progress=48:48; #start_bit=48, number_of_bit=1 +define rx_ddc_use_cyc_block_lock=48:48; #start_bit=48, number_of_bit=1 +define rx_cal_inc_val_A=48:51; #start_bit=48, number_of_bit=4 +define rx_cal_inc_val_B=52:55; #start_bit=52, number_of_bit=4 +define rx_cal_inc_val_C=56:59; #start_bit=56, number_of_bit=4 +define rx_cal_inc_val_D=60:63; #start_bit=60, number_of_bit=4 +define rx_cal_inc_val_E=48:51; #start_bit=48, number_of_bit=4 +define rx_cal_inc_val_F=52:55; #start_bit=52, number_of_bit=4 +define rx_cal_inc_val_G=56:59; #start_bit=56, number_of_bit=4 +define rx_cal_inc_val_H=60:63; #start_bit=60, number_of_bit=4 +define rx_cal_dec_val_A=48:51; #start_bit=48, number_of_bit=4 +define rx_cal_dec_val_B=52:55; #start_bit=52, number_of_bit=4 +define rx_cal_dec_val_C=56:59; #start_bit=56, number_of_bit=4 +define rx_cal_dec_val_D=60:63; #start_bit=60, number_of_bit=4 +define rx_cal_dec_val_E=48:51; #start_bit=48, number_of_bit=4 +define rx_cal_dec_val_F=52:55; #start_bit=52, number_of_bit=4 +define rx_cal_dec_val_G=56:59; #start_bit=56, number_of_bit=4 +define rx_cal_dec_val_H=60:63; #start_bit=60, number_of_bit=4 +define rx_reset_cfg_hld=48:63; #start_bit=48, number_of_bit=16 +define rx_bist_en=48:48; #start_bit=48, number_of_bit=1 +define rx_ber_en=48:48; #start_bit=48, number_of_bit=1 +define rx_ber_count_clr=49:49; #start_bit=49, number_of_bit=1 +define rx_ber_timer_clr=50:50; #start_bit=50, number_of_bit=1 +define rx_ber_timer_freeze_en=48:48; #start_bit=48, number_of_bit=1 +define rx_ber_count_freeze_en=49:49; #start_bit=49, number_of_bit=1 +define rx_ber_count_sel=51:53; #start_bit=51, number_of_bit=3 +define rx_ber_timer_sel=54:56; #start_bit=54, number_of_bit=3 +define rx_ber_clr_count_on_read_en=57:57; #start_bit=57, number_of_bit=1 +define rx_ber_clr_timer_on_read_en=58:58; #start_bit=58, number_of_bit=1 +define rx_fir_msg=48:55; #start_bit=48, number_of_bit=8 +define rx_pb_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 +define rx_pb_fir_reset=63:63; #start_bit=63, number_of_bit=1 +define rx_pb_fir_errs_full_reg=48:57; #start_bit=48, number_of_bit=10 +define rx_pb_fir_errs=48:57; #start_bit=48, number_of_bit=10 +define rx_pb_fir_err_pb_regs=48:48; #start_bit=48, number_of_bit=1 +define rx_pb_fir_err_gcr_buff0=49:49; #start_bit=49, number_of_bit=1 +define rx_pb_fir_err_gcr_buff1=50:50; #start_bit=50, number_of_bit=1 +define rx_pb_fir_err_gcr_buff2=51:51; #start_bit=51, number_of_bit=1 +define rx_pb_fir_err_gcrs_ld_sm0=52:52; #start_bit=52, number_of_bit=1 +define rx_pb_fir_err_gcrs_ld_sm1=53:53; #start_bit=53, number_of_bit=1 +define rx_pb_fir_err_gcrs_ld_sm2=54:54; #start_bit=54, number_of_bit=1 +define rx_pb_fir_err_gcrs_unld_sm0=55:55; #start_bit=55, number_of_bit=1 +define rx_pb_fir_err_gcrs_unld_sm1=56:56; #start_bit=56, number_of_bit=1 +define rx_pb_fir_err_gcrs_unld_sm2=57:57; #start_bit=57, number_of_bit=1 +define rx_pb_fir_errs_mask_full_reg=48:57; #start_bit=48, number_of_bit=10 +define rx_pb_fir_errs_mask=48:57; #start_bit=48, number_of_bit=10 +define rx_pb_fir_err_mask_pb_regs=48:48; #start_bit=48, number_of_bit=1 +define rx_pb_fir_err_mask_gcr_buff0=49:49; #start_bit=49, number_of_bit=1 +define rx_pb_fir_err_mask_gcr_buff1=50:50; #start_bit=50, number_of_bit=1 +define rx_pb_fir_err_mask_gcr_buff2=51:51; #start_bit=51, number_of_bit=1 +define rx_pb_fir_err_mask_gcrs_ld_sm0=52:52; #start_bit=52, number_of_bit=1 +define rx_pb_fir_err_mask_gcrs_ld_sm1=53:53; #start_bit=53, number_of_bit=1 +define rx_pb_fir_err_mask_gcrs_ld_sm2=54:54; #start_bit=54, number_of_bit=1 +define rx_pb_fir_err_mask_gcrs_unld_sm0=55:55; #start_bit=55, number_of_bit=1 +define rx_pb_fir_err_mask_gcrs_unld_sm1=56:56; #start_bit=56, number_of_bit=1 +define rx_pb_fir_err_mask_gcrs_unld_sm2=57:57; #start_bit=57, number_of_bit=1 +define rx_pb_fir_errs_inj_full_reg=48:57; #start_bit=48, number_of_bit=10 +define rx_pb_fir_errs_inj=48:57; #start_bit=48, number_of_bit=10 +define rx_pb_fir_err_inj_pb_regs=48:48; #start_bit=48, number_of_bit=1 +define rx_pb_fir_err_inj_gcr_buff0=49:49; #start_bit=49, number_of_bit=1 +define rx_pb_fir_err_inj_gcr_buff1=50:50; #start_bit=50, number_of_bit=1 +define rx_pb_fir_err_inj_gcr_buff2=51:51; #start_bit=51, number_of_bit=1 +define rx_pb_fir_err_inj_gcrs_ld_sm0=52:52; #start_bit=52, number_of_bit=1 +define rx_pb_fir_err_inj_gcrs_ld_sm1=53:53; #start_bit=53, number_of_bit=1 +define rx_pb_fir_err_inj_gcrs_ld_sm2=54:54; #start_bit=54, number_of_bit=1 +define rx_pb_fir_err_inj_gcrs_unld_sm0=55:55; #start_bit=55, number_of_bit=1 +define rx_pb_fir_err_inj_gcrs_unld_sm1=56:56; #start_bit=56, number_of_bit=1 +define rx_pb_fir_err_inj_gcrs_unld_sm2=57:57; #start_bit=57, number_of_bit=1 +define xbus0_gcr_addr=0401103F; +define xbus1_gcr_addr=0401143F; +define xbus2_gcr_addr=04011C3F; +define xbus3_gcr_addr=0401183F; +define rx_grp0=000000; # 0x00 +define rx_grp1=000001; # 0x01 +define rx_grp2=000010; # 0x02 +define rx_grp3=000011; # 0x03 +define tx_grp0=100000; # 0x20 +define tx_grp1=100001; # 0x21 +define tx_grp2=100010; # 0x22 +define tx_grp3=100011; # 0x23 +define lane_na=00000; # 0x00 +define lane_0=00000; +define lane_1=00001; +define lane_2=00010; +define lane_3=00011; +define lane_4=00100; +define lane_5=00101; +define lane_6=00110; +define lane_7=00111; +define lane_8=01000; +define lane_9=01001; +define lane_10=01010; +define lane_11=01011; +define lane_12=01100; +define lane_13=01101; +define lane_14=01110; +define lane_15=01111; +define lane_16=10000; +define lane_17=10001; +define lane_18=10010; +define lane_19=10011; +define lane_20=10100; +define lane_21=10101; +define lane_22=10110; +define lane_23=10111; +define rx_prbs_tap_id_pattern_a=0b0000000000000000; +define rx_prbs_tap_id_pattern_b=0b0010000000000000; +define rx_prbs_tap_id_pattern_c=0b0100000000000000; +define rx_prbs_tap_id_pattern_d=0b0110000000000000; +define rx_prbs_tap_id_pattern_e=0b1000000000000000; +define rx_prbs_tap_id_pattern_f=0b1010000000000000; +define rx_prbs_tap_id_pattern_g=0b1100000000000000; +define rx_prbs_tap_id_pattern_h=0b1110000000000000; +define tx_prbs_tap_id_pattern_a=0b0000000000000000; +define tx_prbs_tap_id_pattern_b=0b0010000000000000; +define tx_prbs_tap_id_pattern_c=0b0100000000000000; +define tx_prbs_tap_id_pattern_d=0b0110000000000000; +define tx_prbs_tap_id_pattern_e=0b1000000000000000; +define tx_prbs_tap_id_pattern_f=0b1010000000000000; +define tx_prbs_tap_id_pattern_g=0b1100000000000000; +define tx_prbs_tap_id_pattern_h=0b1110000000000000; diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile new file mode 100644 index 000000000..b923afda4 --- /dev/null +++ b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile @@ -0,0 +1,515 @@ +#-- $Id: p8.abus.scom.initfile,v 1.4 2012/07/28 03:43:16 jmcgill Exp $ +#-- CHANGE HISTORY: +#-------------------------------------------------------------------------------- +#-- Version:|Author: | Date: | Comment: +#-- --------|--------|--------|-------------------------------------------------- +#-- 1.4 |jmcgill |07/28/12|Simplify master/slave logic (node ID always unique) +#-- 1.3 |jmcgill |07/27/12|Edits to match scan initfle +#-- 1.2 |pmegan |07/11/12|Added ID in file header +#-- 1.1 |pmegan |07/09/12|Created initial version +#-- --------|--------|--------|-------------------------------------------------- +#-------------------------------------------------------------------------------- +# End of revision history +#-------------------------------------------------------------------------------- +#--Master list of variables that can be used in this file is at: +#--<Attribute Definition Location> +#-- ATTR_EI_BUS_RX_MSB_LSB_SWAP is 0 for setting RX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. +#-- ATTR_EI_BUS_TX_MSB_LSB_SWAP is 0 for setting TX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. + +SyntaxVersion = 1 + +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +#-- +#-- Includes +#-- Note: Must include the path to the .define file. +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +include edi.io.define +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +#-- +#-- Defines +#-- +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- + +define def_bus_id0 = (ATTR_CHIP_UNIT_POS == 0); +define def_bus_id1 = (ATTR_CHIP_UNIT_POS == 1); +define def_bus_id2 = (ATTR_CHIP_UNIT_POS == 2); + +define def_is_master = (TGT1.ATTR_FABRIC_NODE_ID < TGT2.ATTR_FABRIC_NODE_ID); +define def_is_slave = (TGT1.ATTR_FABRIC_NODE_ID > TGT2.ATTR_FABRIC_NODE_ID); +define def_rx_mirrored_mode = (ATTR_EI_BUS_RX_MSB_LSB_SWAP == 1); # Mirrored mode +define def_rx_non_mirrored_mode = (ATTR_EI_BUS_RX_MSB_LSB_SWAP == 0); # Non-Mirrored mode +define def_tx_mirrored_mode = (ATTR_EI_BUS_TX_MSB_LSB_SWAP == 1); # Mirrored mode +define def_tx_non_mirrored_mode = (ATTR_EI_BUS_TX_MSB_LSB_SWAP == 0); # Non-Mirrored mode + +# See p8.chipunit.scominfo file for details of how SCOM addresses are translated by Cronus and FW based on the target unit number +define def_rx_base_grp = rx_grp0; # +define def_tx_base_grp = tx_grp0; # + +#--****************************************************************************** +#------------------------------------------------------------------------------------- +# _____ __ ________ +# / ___/___ / /___ ______ / _/ __ \ +# \__ \/ _ \/ __/ / / / __ \ / // / / / +# ___/ / __/ /_/ /_/ / /_/ / _/ // /_/ / +# /____/\___/\__/\__,_/ .___/ /___/_____/ +# /_/ banner2 -fslant +#------------------------------------------------------------------------------------- +#--****************************************************************************** +#### X bus -> 4 CG's, 20 lanes, A bus -> 3 CG's, 23 lanes , DMI bus -> 4 CG's, 24 lanes +# +# Target unit number based address translation method - fAPI translates group address and lower scom address based on target unit num passed in +# - So the scom address group number must be 000011 for RX and 100011 for TX and lower 32-bits of scom address needs to be DMI0 address +#--******************************************************************************************** +#-- rx_bus_id, tx_bus_id +#--******************************************************************************************** +scom 0x800.0b(rx_id1_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_bus_id , 0b000000, (def_bus_id0); # + rx_bus_id , 0b000001, (def_bus_id1); # + rx_bus_id , 0b000010, (def_bus_id2); # + rx_group_id, 0b000000, any; # GroupID is always 000000 on all RX Abus clk groups +} +scom 0x800.0b(tx_id1_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_bus_id , 0b000000, (def_bus_id0); # + tx_bus_id , 0b000001, (def_bus_id1); # + tx_bus_id , 0b000010, (def_bus_id2); # + tx_group_id, 0b100000, any; # GroupID is always 100000 on all TX Abus channels +} +#--******************************************************************************************** +#-- rx_last_group_id, tx_last_group_id +#--******************************************************************************************** +scom 0x800.0b(rx_id2_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + rx_last_group_id , 0b000000; # Every clk group is 000000 for RX +} +scom 0x800.0b(tx_id2_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + tx_last_group_id , 0b100000; # Every clk group is 100000 for TX +} +#--********************************************************************************************* +#-- rx_start_lane_id, rx_end_lane_id +#--********************************************************************************************* +# 23-bits +scom 0x800.0b(rx_id3_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + rx_start_lane_id , 0b0000000; # Each RX CG on Abus starts with lane 0 + rx_end_lane_id, 0b0010110; # Each RX CG on ABus ends with lane 22 +} +scom 0x800.0b(tx_id3_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + tx_start_lane_id , 0b0000000; # Each TX CG on Abus starts with lane 0 + tx_end_lane_id, 0b0010110; # Each TX CG on Abus ends with lane 22 +} +#--********************************************************************************************* +#-- rx_tx_bus_width, rx_rx_bus_width +#--********************************************************************************************* +# 23-bits +scom 0x800.0b(rx_tx_bus_info_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + rx_tx_bus_width, 0b0010111; # Each TX CG on Abus is 23-bits + rx_rx_bus_width, 0b0010111; # Each RX CG on Abus is 23-bits +} +#----------------------------------------------------------------------------------------------- +# ______ +# / ____/__ ____ ________ #### TODO: This needs to be set in the scaninit file and io_hard_reset factored into all reinit scenarios +# / /_ / _ \/ __ \/ ___/ _ \ +# / __/ / __/ / / / /__/ __/ +# /_/ \___/_/ /_/\___/\___/ banner2 -fslant +#---------------------------------------------------------------------------------------------- +scom 0x800.0b(rx_fence_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits , scom_data; + rx_fence, 0b1; +} +#---------------------------------------------------------------------------------------------- +# __ ____ _ __ __ +# / / ____ _____ ___ / __ \(_)________ _/ /_ / /__ _____ +# / / / __ `/ __ \/ _ \ / / / / / ___/ __ `/ __ \/ / _ \/ ___/ +# / /___/ /_/ / / / / __/ / /_/ / (__ ) /_/ / /_/ / / __(__ ) +# /_____/\__,_/_/ /_/\___/ /_____/_/____/\__,_/_.___/_/\___/____/ banner2 -fslant +#---------------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_lane_disabled_vec_0_15, rx_lane_disabled_vec_16_31 +#--********************************************************************************************* +# RX = 23-bits +scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + rx_lane_disabled_vec_0_15, 0b0000000000000000; # Each RX CG on Abus has lanes 0-15 enabled (ie. disabled=0) +} +scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + rx_lane_disabled_vec_16_31, 0b0000000111111111; # Each RX CG on Abus has lanes 16-22 enabled (ie. disabled=0) +} +#--********************************************************************************************* +#-- tx_lane_disabled_vec_0_15, tx_lane_disabled_vec_16_31 +#--********************************************************************************************* +# TX = 23-bits +scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + tx_lane_disabled_vec_0_15, 0b0000000000000000; # Each RX CG on Abus has lanes 0-15 enabled (ie. disabled=0) +} +scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + tx_lane_disabled_vec_16_31, 0b0000000111111111; # Each RX CG on Abus has lanes 16-22 enabled (ie. disabled=0) +} +#------------------------------------------------------------------------------------- +# __ ___ ____ __ __ +# / |/ /___ __ __ / __ )____ _____/ / / / ____ _____ ___ _____ +# / /|_/ / __ `/ |/_/ / __ / __ `/ __ / / / / __ `/ __ \/ _ \/ ___/ +# / / / / /_/ /> < / /_/ / /_/ / /_/ / / /___/ /_/ / / / / __(__ ) +# /_/ /_/\__,_/_/|_| /_____/\__,_/\__,_/ /_____/\__,_/_/ /_/\___/____/ banner2 -fslant +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_wtr_max_bad_lanes, tx_max_bad_lanes +#--********************************************************************************************* +# RX = 1 spare +scom 0x800.0b(rx_wiretest_laneinfo_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + rx_wtr_max_bad_lanes, 0b00001; # Each RX CG on Abus has 1 spare lane +} +# TX = 1 spare +scom 0x800.0b(tx_mode_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + tx_max_bad_lanes, 0b00001; # Each TX CG on Abus has 1 spare lane +} +#------------------------------------------------------------------------------------- +# ____ ____ _ ______ ____ _ +# / __ \__ ______ / __ \___ ____ ____ _(_)____ /_ __/___ _/ / /_ __(_)___ ____ _ +# / / / / / / / __ \ / /_/ / _ \/ __ \/ __ `/ / ___/ / / / __ `/ / / / / / / __ \/ __ `/ +# / /_/ / /_/ / / / / / _, _/ __/ /_/ / /_/ / / / / / / /_/ / / / /_/ / / / / / /_/ / +# /_____/\__, /_/ /_/ /_/ |_|\___/ .___/\__,_/_/_/ /_/ \__,_/_/_/\__, /_/_/ /_/\__, / +# /____/ /_/ /____/ /____/ banner2 -fslant +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_dyn_rpr_err_tallying1_pg: rx_dyn_rpr_bad_lane_max, rx_dyn_rpr_err_cntr1_duration, rx_dyn_rpr_enc_bad_data_lane_width +#--********************************************************************************************* +scom 0x800.0b(rx_dyn_rpr_err_tallying1_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + rx_dyn_rpr_bad_lane_max, 0b0001111; # + rx_dyn_rpr_err_cntr1_duration, 0b1001; # tap 9 + rx_dyn_rpr_enc_bad_data_lane_width, 0b101; # +} +#--********************************************************************************************* +#-- rx_dyn_rpr_err_tallying2_pg: rx_dyn_rpr_bad_bus_max, rx_dyn_rpr_err_cntr2_duration +#--********************************************************************************************* +scom 0x800.0b(rx_dyn_rpr_err_tallying2_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + rx_dyn_rpr_bad_bus_max, 0b0011111; # + rx_dyn_rpr_err_cntr2_duration, 0b0110; # tap 6 +} +#------------------------------------------------------------------------------------- +# __ ___ __ __ ___ __ +# / |/ /___ ______/ /____ _____ / |/ /___ ____/ /__ +# / /|_/ / __ `/ ___/ __/ _ \/ ___/ / /|_/ / __ \/ __ / _ \ +# / / / / /_/ (__ ) /_/ __/ / / / / / /_/ / /_/ / __/ +# /_/ /_/\__,_/____/\__/\___/_/ /_/ /_/\____/\__,_/\___/ +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_mode_pg: rx_master_mode +#--********************************************************************************************* +scom 0x800.0b(rx_mode_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_master_mode, 0b1, (def_is_master); + rx_master_mode, 0b0, (def_is_slave); +} +#------------------------------------------------------------------------------------- +# ____ ____ ____ _____ ______ _____ __ __ +# / __ \/ __ \/ __ ) ___/ /_ __/___ _____ / ___/___ / /__ _____/ /______ +# / /_/ / /_/ / __ \__ \ / / / __ `/ __ \ \__ \/ _ \/ / _ \/ ___/ __/ ___/ +# / ____/ _, _/ /_/ /__/ / / / / /_/ / /_/ / ___/ / __/ / __/ /__/ /_(__ ) +# /_/ /_/ |_/_____/____/ /_/ \__,_/ .___/ /____/\___/_/\___/\___/\__/____/ banner2 -fslant +# /_/ +#------------------------------------------------------------------------------------- +# PER-LANE (RX) +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_prbs_mode_pl: rx_prbs_tap_id +#--********************************************************************************************* +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_0).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_1).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_2).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_3).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_4).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_5).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_6).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_7).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_8).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_9).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_10).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_11).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_12).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_13).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_14).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_15).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_16).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_h, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_17).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_g, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_18).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_f, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_19).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_e, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_20).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_d, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_21).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_c, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_22).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_b, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); +} +scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_23).0x(abus_gcr_addr){ + bits, scom_data, expr; + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_mirrored_mode); + rx_prbs_tap_id, rx_prbs_tap_id_pattern_a, (def_rx_non_mirrored_mode); +} +#------------------------------------------------------------------------------------- +# PER-LANE (TX) +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- tx_prbs_mode_pl: tx_prbs_tap_id +#--********************************************************************************************* +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_0).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_1).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_2).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_3).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_4).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_5).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_6).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_7).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_8).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_9).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_10).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_11).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_12).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_13).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_14).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_15).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_16).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_h, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_17).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_g, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_18).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_f, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_19).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_e, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_20).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_d, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_21).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_c, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_22).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_b, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); +} +scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_23).0x(abus_gcr_addr){ + bits, scom_data, expr; + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_mirrored_mode); + tx_prbs_tap_id, tx_prbs_tap_id_pattern_a, (def_tx_non_mirrored_mode); +} + +#------------------------------------------------------------------------------------- +# ____ __ __ +# / __ \/ / / / +# / /_/ / / / / +# / ____/ /___/ /___ +# /_/ /_____/_____/ banner2 -fslant +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- rx_wiretest_pll_cntl_pg: rx_wt_cu_pll_reset, rx_wt_cu_pll_pgooddly +#--********************************************************************************************* +scom 0x800.0b(rx_wiretest_pll_cntl_pg)(def_rx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + rx_wt_cu_pll_reset, 0b0; # Put PLL in disabled state until Wiretest is started. + rx_wt_cu_pll_pgooddly, 0b001; # 50ns delay +} +#------------------------------------------------------------------------------------- +# ____ _ __________ ____ __ __ +# / __ \_____(_) _____ / ____/ / /__ / __ \____ _/ /_/ /____ _________ +# / / / / ___/ / | / / _ \ / / / / //_/ / /_/ / __ `/ __/ __/ _ \/ ___/ __ \ +# / /_/ / / / /| |/ / __/ / /___/ / ,< / ____/ /_/ / /_/ /_/ __/ / / / / / +# /_____/_/ /_/ |___/\___/ \____/_/_/|_| /_/ \__,_/\__/\__/\___/_/ /_/ /_/ +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +#-- tx_clk_cntl_gcrmsg_pg: tx_drv_clk_pattern_gcrmsg +#--********************************************************************************************* +scom 0x800.0b(tx_clk_cntl_gcrmsg_pg)(def_tx_base_grp)(lane_na).0x(abus_gcr_addr){ + bits, scom_data; + tx_drv_clk_pattern_gcrmsg, 0b00; # Drive 0's to start out +} + +############################################################################################ +# END OF FILE +############################################################################################ diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile new file mode 100644 index 000000000..c6b4200e8 --- /dev/null +++ b/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile @@ -0,0 +1,828 @@ +#-- $Id: p8.xbus.scom.initfile,v 1.3 2012/08/01 05:31:13 thomsen Exp $ +#-- CHANGE HISTORY: +#-------------------------------------------------------------------------------- +#-- Version:|Author: | Date: | Comment: +#-- --------|--------|--------|-------------------------------------------------- +#-- 1.3 |thomsen |07/31/12|Removed mirrored PRBS tap entries since Xbus doesn't support end-for-end swapping +#-- | | |Changed per-group writes with the same data being written into all groups into group broadcast writes to save scom's +#-- 1.2 |jmcgill |07/27/12|Cleanup to run on VBU, edit to match scan initfile +#-- | | |Simplify master/slave logic (chip ID always unique) +#-- 1.1 |pmegan |07/10/12|Created initial version +#-- --------|--------|--------|-------------------------------------------------- +#-------------------------------------------------------------------------------- +# End of revision history +#-------------------------------------------------------------------------------- +#--Master list of variables that can be used in this file is at: +#--<Attribute Definition Location> +#-- ATTR_EI_BUS_RX_MSB_LSB_SWAP is 0 for setting RX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. +#-- ATTR_EI_BUS_TX_MSB_LSB_SWAP is 0 for setting TX PRBS TapID's to Non-Mirrored Mode and 1 for setting to Mirrored Mode. It comes from the MRW. + +SyntaxVersion = 1 + +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +#-- +#-- Includes +#-- Note: Must include the path to the .define file. +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +include ei4.io.define +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- +#-- +#-- Defines +#-- +#-- ----------------------------------------------------------------------------- +#--****************************************************************************** +#-- ----------------------------------------------------------------------------- + +define def_bus_id0 = (ATTR_CHIP_UNIT_POS == 0); +define def_bus_id1 = (ATTR_CHIP_UNIT_POS == 1); +define def_bus_id2 = (ATTR_CHIP_UNIT_POS == 2); +define def_bus_id3 = (ATTR_CHIP_UNIT_POS == 3); + +define def_is_master = (TGT1.ATTR_FABRIC_CHIP_ID < TGT2.ATTR_FABRIC_CHIP_ID); +define def_is_slave = (TGT1.ATTR_FABRIC_CHIP_ID > TGT2.ATTR_FABRIC_CHIP_ID); +define def_xbus_4byte_mode = (SYS.ATTR_PROC_X_BUS_WIDTH == ENUM_ATTR_PROC_X_BUS_WIDTH_W4BYTE); # xbus_4byte mode +define def_xbus_8byte_mode = (SYS.ATTR_PROC_X_BUS_WIDTH == ENUM_ATTR_PROC_X_BUS_WIDTH_W8BYTE); # xbus_8byte mode +# See p8.chipunit.scominfo file for details of how SCOM addresses are translated by Cronus and FW based on the target unit number +define rx_grp = rx_grp0; # +define tx_grp = tx_grp0; # +define rx_grp_broadcast = 001111; +define tx_grp_broadcast = 101111; + +#--****************************************************************************** +#------------------------------------------------------------------------------------- +# _____ __ ________ +# / ___/___ / /___ ______ / _/ __ \ +# \__ \/ _ \/ __/ / / / __ \ / // / / / +# ___/ / __/ /_/ /_/ / /_/ / _/ // /_/ / +# /____/\___/\__/\__,_/ .___/ /___/_____/ +# /_/ banner2 -fslant +#------------------------------------------------------------------------------------- +#--****************************************************************************** +#### X bus -> 4 CG's, 20 lanes, A bus -> 3 CG's, 23 lanes , DMI bus -> 4 CG's, 24 lanes +# +#--******************************************************************************************** +#-- rx_bus_id, tx_bus_id +#--******************************************************************************************** +scom 0x800.0b(rx_id1_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_bus_id , 0b000000, (def_xbus_8byte_mode); # BusID is 0x00 on RX0 when in 8-byte mode + rx_bus_id , 0b110000, (def_xbus_4byte_mode); # BusID is 0x30 on RX0 when in 4-byte mode since it isn't used and we don't want it decoding any GCR commands + rx_group_id, 0b000000, (def_xbus_8byte_mode); # GroupID is 0x00 on RX0 when in 8-byte mode + rx_group_id, 0b110000, (def_xbus_4byte_mode); # GroupID is 0x30 on RX0 when 4-byte mode since it isn't used +} +scom 0x800.0b(rx_id1_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_bus_id , 0b000000, any; # BusID is 0x00 for all clock groups in all X buses + rx_group_id, 0b000001, (def_xbus_8byte_mode); # GroupID is 0x01 on RX1 when in 8-byte mode + rx_group_id, 0b000000, (def_xbus_4byte_mode); # GroupID is 0x00 on RX1 when in 4-byte mode +} +scom 0x800.0b(rx_id1_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_bus_id , 0b000000, any; # BusID is 0x00 for all clock groups in all X buses + rx_group_id, 0b000010, (def_xbus_8byte_mode); # GroupID is 0x02 on RX2 when in 8-byte mode + rx_group_id, 0b000001, (def_xbus_4byte_mode); # GroupID is 0x01 on RX2 when in 4-byte mode +} +scom 0x800.0b(rx_id1_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_bus_id , 0b000000, any; # BusID is 0x00 for all clock groups in all X buses + rx_group_id, 0b000011, (def_xbus_8byte_mode); # GroupID is 0x03 on RX2 when in 8-byte mode + rx_group_id, 0b000001, (def_xbus_4byte_mode); # GroupID is 0x01 on RX2 when in 4-byte mode +} + +scom 0x800.0b(tx_id1_pg)(tx_grp0)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_bus_id , 0b000000, (def_xbus_8byte_mode); # BusID is 0x00 on TX0 when in 8-byte mode + tx_bus_id , 0b110000, (def_xbus_4byte_mode); # BusID is 0x30 on TX0 when in 4-byte mode since it isn't used and we don't want it decoding any GCR commands + tx_group_id, 0b100000, (def_xbus_8byte_mode); # GroupID is 0x20 on TX0 when in 8-byte mode + tx_group_id, 0b110001, (def_xbus_4byte_mode); # GroupID is 0x31 on TX0 when in 4-byte mode since it isn't used +} +scom 0x800.0b(tx_id1_pg)(tx_grp1)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_bus_id , 0b000000, any; # BusID is 0x00 for all clock groups in all X buses + tx_group_id, 0b100001, (def_xbus_8byte_mode); # GroupID is 0x21 on TX1 when in 8-byte mode + tx_group_id, 0b100000, (def_xbus_4byte_mode); # GroupID is 0x20 on TX1 when in 4-byte mode +} +scom 0x800.0b(tx_id1_pg)(tx_grp2)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_bus_id , 0b000000, any; # BusID is 0x00 for all clock groups in all X buses + tx_group_id, 0b100010, (def_xbus_8byte_mode); # GroupID is 0x22 on TX2 when in 8-byte mode + tx_group_id, 0b100001, (def_xbus_4byte_mode); # GroupID is 0x21 on TX2 when in 4-byte mode +} +scom 0x800.0b(tx_id1_pg)(tx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_bus_id , 0b000000, any; # BusID is 0x00 for all clock groups in all X buses + tx_group_id, 0b100011, (def_xbus_8byte_mode); # GroupID is 0x23 on TX3 when in 8-byte mode + tx_group_id, 0b100010, (def_xbus_4byte_mode); # GroupID is 0x22 on TX3 when in 4-byte mode +} + +#--******************************************************************************************** +#-- rx_last_group_id, tx_last_group_id +#--******************************************************************************************** +scom 0x800.0b(rx_id2_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_last_group_id , 0b000011, (def_xbus_8byte_mode); #Last group ID is 0x03 on RX0 when in 8-byte mode + rx_last_group_id , 0b110000, (def_xbus_4byte_mode); #Last group ID is 0x30 on RX0 when in 4-byte mode since it isn't used +} +scom 0x800.0b(rx_id2_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_last_group_id , 0b000011, (def_xbus_8byte_mode); #Last group ID is 0x03 on RX1 when in 8-byte mode + rx_last_group_id , 0b100000, (def_xbus_4byte_mode); #Last group ID is 0x20 on RX1 when in 4-byte mode +} +scom 0x800.0b(rx_id2_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_last_group_id , 0b000011, (def_xbus_8byte_mode); #Last group ID is 0x03 on RX2 when in 8-byte mode + rx_last_group_id , 0b100000, (def_xbus_4byte_mode); #Last group ID is 0x20 on RX2 when in 4-byte mode +} +scom 0x800.0b(rx_id2_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_last_group_id , 0b000011, (def_xbus_8byte_mode); #Last group ID is 0x03 on RX3 when in 8-byte mode + rx_last_group_id , 0b100000, (def_xbus_4byte_mode); #Last group ID is 0x20 on RX2 when in 4-byte mode +} +scom 0x800.0b(tx_id2_pg)(tx_grp0)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_last_group_id , 0b100011, (def_xbus_8byte_mode); #Last group ID is 0x23 on TX0 when in 8-byte mode + tx_last_group_id , 0b110001, (def_xbus_4byte_mode); #Last group ID is 0x31 on TX0 when in 4-byte mode since it isn't used +} +scom 0x800.0b(tx_id2_pg)(tx_grp1)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_last_group_id , 0b100011, (def_xbus_8byte_mode); #Last group ID is 0x23 on TX1 when in 8-byte mode + tx_last_group_id , 0b100010, (def_xbus_4byte_mode); #Last group ID is 0x22 on TX1 when in 4-byte mode +} +scom 0x800.0b(tx_id2_pg)(tx_grp2)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_last_group_id , 0b100011, (def_xbus_8byte_mode); #Last group ID is 0x23 on TX2 when in 8-byte mode + tx_last_group_id , 0b100010, (def_xbus_4byte_mode); #Last group ID is 0x22 on TX2 when in 4-byte mode +} +scom 0x800.0b(tx_id2_pg)(tx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_last_group_id , 0b100011, (def_xbus_8byte_mode); #Last group ID is 0x23 on TX3 when in 8-byte mode + tx_last_group_id , 0b100010, (def_xbus_4byte_mode); #Last group ID is 0x22 on TX3 when in 4-byte mode +} + +#--********************************************************************************************* +#-- rx_start_lane_id, rx_end_lane_id +#--********************************************************************************************* +#RX = 80-bits (8byte mode), 46-bits (4byte mode) +scom 0x800.0b(rx_id3_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_start_lane_id , 0b0000000, any; #Start lane ID starts with lane 0 on RX0 when in 8/4 byte mode + rx_end_lane_id, 0b0010011, (def_xbus_8byte_mode); #End lane ID ends with lane 19 on RX0 when in 8-byte mode + rx_end_lane_id, 0b0000000, (def_xbus_4byte_mode); #End lane ID ends with lane 0 on RX0 when in 4-byte mode +} +scom 0x800.0b(rx_id3_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_start_lane_id , 0b0010100, (def_xbus_8byte_mode); #Start lane ID starts with lane 20 on RX1 when in 8-byte mode + rx_start_lane_id , 0b0000000, (def_xbus_4byte_mode); #Start lane ID starts with lane 0 on RX1 when in 4-byte mode + rx_end_lane_id, 0b0100111, (def_xbus_8byte_mode); #End lane ID ends with lane 39 on RX1 when in 8-byte mode + rx_end_lane_id, 0b0000101, (def_xbus_4byte_mode); #End lane ID ends with lane 5 on RX1 when in 4-byte mode +} +scom 0x800.0b(rx_id3_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_start_lane_id , 0b0101000, (def_xbus_8byte_mode); #Start lane ID starts with lane 40 on RX2 when in 8-byte mode + rx_start_lane_id , 0b0000110, (def_xbus_4byte_mode); #Start lane ID starts with lane 6 on RX2 when in 4-byte mode + rx_end_lane_id, 0b0111011, (def_xbus_8byte_mode); #End lane ID ends with lane 59 on RX2 when in 8-byte mode + rx_end_lane_id, 0b0011001, (def_xbus_4byte_mode); #End lane ID ends with lane 25 on RX2 when in 4-byte mode +} +scom 0x800.0b(rx_id3_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_start_lane_id , 0b0111100, (def_xbus_8byte_mode); #Start lane ID starts with lane 60 on RX3 when in 8-byte mode + rx_start_lane_id , 0b0011010, (def_xbus_4byte_mode); #Start lane ID starts with lane 26 on RX3 when in 4-byte mode + rx_end_lane_id, 0b1001111, (def_xbus_8byte_mode); #End lane ID ends with lane 79 on RX3 when in 8-byte mode + rx_end_lane_id, 0b0101101, (def_xbus_4byte_mode); #End lane ID ends with lane 45 on RX3 when in 4-byte mode +} +# TX = 80-bits (8byte mode), 46-bits (4byte mode) +scom 0x800.0b(tx_id3_pg)(tx_grp0)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_start_lane_id , 0b0000000, any; #Start lane ID starts with lane 0 on TX0 when in 8/4-byte mode + tx_end_lane_id, 0b0010011, (def_xbus_8byte_mode); #End lane ID ends with lane 19 on TX0 when in 8-byte mode + tx_end_lane_id, 0b0000000, (def_xbus_4byte_mode); #End lane ID ends with lane 0 on TX0 when in 4-byte mode + } +scom 0x800.0b(tx_id3_pg)(tx_grp1)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_start_lane_id , 0b0010100, (def_xbus_8byte_mode); #Start lane ID starts with lane 20 on TX1 when in 8-byte mode + tx_start_lane_id , 0b0000000, (def_xbus_4byte_mode); #Start lane ID starts with lane 0 on TX1 when in 4-byte mode + tx_end_lane_id, 0b0100111, (def_xbus_8byte_mode); #End lane ID ends with lane 39 on TX1 when in 8-byte mode + tx_end_lane_id, 0b0000101, (def_xbus_4byte_mode); #End lane ID ends with lane 5 on TX1 when in 4-byte mode +} +scom 0x800.0b(tx_id3_pg)(tx_grp2)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_start_lane_id , 0b0101000, (def_xbus_8byte_mode); #Start lane ID starts with lane 40 on TX2 when in 8-byte mode + tx_start_lane_id , 0b0000110, (def_xbus_4byte_mode); #Start lane ID start with lane 6 on TX2 when in 4-byte mode + tx_end_lane_id, 0b0111011, (def_xbus_8byte_mode); #End lane ID ends with lane 59 on TX2 when in 8-byte mode + tx_end_lane_id, 0b0011001, (def_xbus_4byte_mode); #End lane ID ends with lane 25 on TX2 when in 4-byte mode +} +scom 0x800.0b(tx_id3_pg)(tx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_start_lane_id , 0b0111100, (def_xbus_8byte_mode); #Start lane ID starts with lane 60 on TX3 when in 8-byte mode + tx_start_lane_id , 0b0011010, (def_xbus_4byte_mode); #Start lane ID start with lane 26 on TX3 when in 4-byte mode + tx_end_lane_id, 0b1001111, (def_xbus_8byte_mode); #End lane ID ends with lane 79 on TX3 when in 8-byte mode + tx_end_lane_id, 0b0101101, (def_xbus_4byte_mode); #End lane ID ends with lane 45 on TX3 when in 4-byte mode +} +#--********************************************************************************************* +# rx_tx_bus_width ediei4 0 99 rx_tx_bus_info_pg 0 7 RWX n 0000000 +# rx_rx_bus_width ediei4 0 99 rx_tx_bus_info_pg 7 7 RWX n 0000000 +#--********************************************************************************************* +# +# TX = 80-bits (8byte mode), 46-bits (4byte mode) +scom 0x800.0b(rx_tx_bus_info_pg)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ + scom_data, expr; +# 0d80 0d80 + 0b1010000101000000, (def_xbus_8byte_mode); #Bus width is 80 bits for all clock groups in all X buses when in 8-byte mode +# 0d46 0d46 + 0b0101110001011100, (def_xbus_4byte_mode); #Bus width is 46 bits for all clock groups in all X buses when in 4-byte mode +#scom 0x800.0b(rx_tx_bus_info_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ +# bits, scom_data, expr; +# rx_tx_bus_width, 0b1010000, (def_xbus_8byte_mode); #Bus width is 80 bits for all clock groups in all X buses when in 8-byte mode +# rx_tx_bus_width, 0b0101110, (def_xbus_4byte_mode); #Bus width is 46 bits for all clock groups in all X buses when in 4-byte mode +# rx_rx_bus_width, 0b1010000, (def_xbus_8byte_mode); #Bus width is 80 bits for all clock groups in all X buses when in 8-byte mode +# rx_rx_bus_width, 0b0101110, (def_xbus_4byte_mode); #Bus width is 46 bits for all clock groups in all X buses when in 4-byte mode +} +#----------------------------------------------------------------------------------------------- +# ______ +# / ____/__ ____ ________ #### TODO: This needs to be set in the scaninit file and io_hard_reset factored into all reinit scenarios +# / /_ / _ \/ __ \/ ___/ _ \ +# / __/ / __/ / / / /__/ __/ +# /_/ \___/_/ /_/\___/\___/ banner2 -fslant +#---------------------------------------------------------------------------------------------- +#--********************************************************************************************* +# rx_fence ediei4 0 99 rx_fence_pg 0 1 RWX n 0 +#--********************************************************************************************* +scom 0x800.0b(rx_fence_pg)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ + scom_data; + 0x8000; +#scom 0x800.0b(rx_fence_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ +# bits , scom_data; +# rx_fence, 0b1; +} +#---------------------------------------------------------------------------------------------- +# __ ____ _ __ __ +# / / ____ _____ ___ / __ \(_)________ _/ /_ / /__ _____ +# / / / __ `/ __ \/ _ \ / / / / / ___/ __ `/ __ \/ / _ \/ ___/ +# / /___/ /_/ / / / / __/ / /_/ / (__ ) /_/ / /_/ / / __(__ ) +# /_____/\__,_/_/ /_/\___/ /_____/_/____/\__,_/_.___/_/\___/____/ banner2 -fslant +#---------------------------------------------------------------------------------------------- +#--********************************************************************************************* +# rx_lane_disabled_vec_0_15 ediei4 0 99 rx_lane_disabled_vec_0_15_pg 0 16 RWX n 0000000000000000 +#--********************************************************************************************* +# RX = 80-bits (8byte mode), 46-bits (4byte mode) +scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_lane_disabled_vec_0_15, 0b0000000000000000, (def_xbus_8byte_mode); # RX0 on X bus has all lanes (0x0000) enabled (ie. disabled=0)when in 8-byte mode + rx_lane_disabled_vec_0_15, 0b1111111111111111, (def_xbus_4byte_mode); # RX0 on X bus has lane 0:15 (0xFFFF) diabled when in 4-byte mode +} +scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_lane_disabled_vec_0_15, 0b0000000000000000, (def_xbus_8byte_mode); # RX1 on X bus has all laness (0x0000) enabled (ie. disabled=0)when in 8-byte mode + rx_lane_disabled_vec_0_15, 0b1111111111111100, (def_xbus_4byte_mode); # RX1 on X bus has lane 0:13(0xFFFC) diabled when in 4-byte mode +} +scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_lane_disabled_vec_0_15, 0b0000000000000000, any; # RX2 on X bus has all lanes (0x0000)enabled (ie. disabled=0) in 8/4-byte mode +} +scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_lane_disabled_vec_0_15, 0b0000000000000000, any; # RX3 on X bus has all lanes (0x0000) enabled (ie. disabled=0) in 8/4-byte mode +} +#--********************************************************************************************* +# rx_lane_disabled_vec_16_31 ediei4 0 99 rx_lane_disabled_vec_16_31_pg 0 16 RWX n 0000000000000000 +#--********************************************************************************************* +scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_lane_disabled_vec_16_31, 0b0000111111111111, (def_xbus_8byte_mode); # RX0 on X bus has lane 16:19 (0X0FFF) enabled (ie. disabled=0) when in 8-byte mode + rx_lane_disabled_vec_16_31, 0b1111111111111111, (def_xbus_4byte_mode); # RX0 on X bus has all lane 16:31(0xFFFF) diabled when in 4-byte mode +} +scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_lane_disabled_vec_16_31, 0b0000111111111111, any; # RX1 on X bus has lane 16:19 (0X0FFF) enabled (ie. disabled=0) in 8/4-byte mode +} +scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_lane_disabled_vec_16_31, 0b0000111111111111, any; # RX2 on X bus has lane 16:19 (0X0FFF) enabled (ie. disabled=0)when in 8/4-byte mode +} +scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_lane_disabled_vec_16_31, 0b0000111111111111, any; # RX3 on X bus has lane 16:19 (0X0FFF) enabled (ie. disabled=0)when in 8/4-byte mode +} + +#--********************************************************************************************* +# tx_lane_disabled_vec_0_15 ediei4 0 99 tx_lane_disabled_vec_0_15_pg 0 16 RWX n 0000000000000000 +#--********************************************************************************************* +# TX = 80-bits (8byte mode), 46-bits (4byte mode) +scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(tx_grp0)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_lane_disabled_vec_0_15, 0b0000000000000000, (def_xbus_8byte_mode); # TX0 on X bus has all lanes (0x0000)enabled(ie. disabled=0) when in 8-byte mode + tx_lane_disabled_vec_0_15, 0b1111111111111111, (def_xbus_4byte_mode); # TX0 on X bus has all lane 0:15 (0xFFFF)diabled when in 4-byte mode +} +scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(tx_grp1)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_lane_disabled_vec_0_15, 0b0000000000000000, (def_xbus_8byte_mode); # TX1 on X bus has all lanes (0x0000) enabled (ie. disabled=0)when in 8-byte mode + tx_lane_disabled_vec_0_15, 0b1111111111111100, (def_xbus_4byte_mode); # TX1 on X bus has lane 0:13(0xFFFC) diabled when in 4-byte mode +} +scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(tx_grp2)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_lane_disabled_vec_0_15, 0b0000000000000000, any; # TX2 on X bus has all lanes (0x0000) enabled (ie. disabled=0) in 8/4-byte mode +} +scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(tx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_lane_disabled_vec_0_15, 0b0000000000000000, any; # TX3 on X bus has all lanes enabled (0x0000) (ie. disabled=0) in 8/4-byte mode +} +#--********************************************************************************************* +# tx_lane_disabled_vec_16_31 ediei4 0 99 tx_lane_disabled_vec_16_31_pg 0 16 RWX n 0000000000000000 +#--********************************************************************************************* +scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(tx_grp0)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_lane_disabled_vec_16_31, 0b0000111111111111, (def_xbus_8byte_mode); # TX0 on X bus has lane 16:19 (0X0FFF) enabled when in 8-byte mode(ie. disabled=0) + tx_lane_disabled_vec_16_31, 0b1111111111111111, (def_xbus_4byte_mode); # TX0 on X bus has all lane 16:31(0xFFFF) diabled when in 4-byte mode +} +scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(tx_grp1)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_lane_disabled_vec_16_31, 0b0000111111111111, any; # TX1 on X bus has lane 16:19 (0X0FFF) enabled when in 8/4-byte mode(ie. disabled=0) +} +scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(tx_grp2)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_lane_disabled_vec_16_31, 0b0000111111111111, any; # TX2 on X bus has lane 16:19 (0X0FFF)enabled in 8/4-byte mode(ie. disabled=0) +} +scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(tx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + tx_lane_disabled_vec_16_31, 0b0000111111111111, any; # TX3 on X bus has lane 16:19 (0X0FFF) enabled in 8/4-byte mode(ie. disabled=0) +} +#------------------------------------------------------------------------------------- +# __ ___ ____ __ __ +# / |/ /___ __ __ / __ )____ _____/ / / / ____ _____ ___ _____ +# / /|_/ / __ `/ |/_/ / __ / __ `/ __ / / / / __ `/ __ \/ _ \/ ___/ +# / / / / /_/ /> < / /_/ / /_/ / /_/ / / /___/ /_/ / / / / __(__ ) +# /_/ /_/\__,_/_/|_| /_____/\__,_/\__,_/ /_____/\__,_/_/ /_/\___/____/ banner2 -fslant +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +# rx_wtr_cur_lane ediei4 0 99 rx_wiretest_laneinfo_pg 0 5 ROX n 00000 +# rx_wtr_max_bad_lanes ediei4 0 99 rx_wiretest_laneinfo_pg 5 5 RWX n 00000 +# rx_wtr_bad_lane_count ediei4 0 99 rx_wiretest_laneinfo_pg 11 5 ROX n 00000 +#--********************************************************************************************* +# Register has more than one possible non-zero field so can't use group broadcast write +# RX = 2 spares +#scom 0x800.0b(rx_wiretest_laneinfo_pg)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ +scom 0x800.0b(rx_wiretest_laneinfo_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data; + rx_wtr_max_bad_lanes, 0b00010; # Only 2 spare lanes on all clock groups of XBUS RX in both 8/4byte mode +} + + +#--********************************************************************************************* +# tx_max_bad_lanes ediei4 0 99 tx_mode_pg 0 5 RWX n 00000 +# tx_msbswap ediei4 0 99 tx_mode_pg 5 1 RWX n 0 +# tx_pdwn_lite_disable edi 0 99 tx_mode_pg 6 1 RWX n 0 +#--********************************************************************************************* +# Register has more than one possible non-zero field so can't use group broadcast write +# TX = 2 spares +#scom 0x800.0b(tx_mode_pg)(tx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ +scom 0x800.0b(tx_mode_pg)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data; + tx_max_bad_lanes, 0b00010; # Each TX CG on X bus has 2 spare lanes in 8/4byte mode +} +#------------------------------------------------------------------------------------- +# ____ ____ _ ______ ____ _ +# / __ \__ ______ / __ \___ ____ ____ _(_)____ /_ __/___ _/ / /_ __(_)___ ____ _ +# / / / / / / / __ \ / /_/ / _ \/ __ \/ __ `/ / ___/ / / / __ `/ / / / / / / __ \/ __ `/ +# / /_/ / /_/ / / / / / _, _/ __/ /_/ / /_/ / / / / / / /_/ / / / /_/ / / / / / /_/ / +# /_____/\__, /_/ /_/ /_/ |_|\___/ .___/\__,_/_/_/ /_/ \__,_/_/_/\__, /_/_/ /_/\__, / +# /____/ /_/ /____/ /____/ banner2 -fslant +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +# rx_dyn_rpr_bad_lane_max ediei4 0 99 rx_dyn_rpr_err_tallying1_pg 0 7 RWX n 0001111 +# rx_dyn_rpr_err_cntr1_duration ediei4 0 99 rx_dyn_rpr_err_tallying1_pg 7 4 RWX n 1010 +# rx_dyn_rpr_clr_err_cntr1 ediei4 0 99 rx_dyn_rpr_err_tallying1_pg 11 1 RWX n 0 +# rx_dyn_rpr_disable ediei4 0 99 rx_dyn_rpr_err_tallying1_pg 12 1 RWX n 0 +# rx_dyn_rpr_enc_bad_data_lane_width ediei4 0 99 rx_dyn_rpr_err_tallying1_pg 13 3 RWX n 111 +#--********************************************************************************************* +# Register has more than one possible non-zero field so can't use group broadcast write +#scom 0x800.0b(rx_dyn_rpr_err_tallying1_pg)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ +# scom_data; +# 0b0001111101000111; +scom 0x800.0b(rx_dyn_rpr_err_tallying1_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data; + rx_dyn_rpr_bad_lane_max, 0b0001111; # + rx_dyn_rpr_err_cntr1_duration, 0b1010; # tap 10 + rx_dyn_rpr_enc_bad_data_lane_width, 0b111; # +} +#--********************************************************************************************* +# rx_dyn_rpr_bad_bus_max ediei4 0 99 rx_dyn_rpr_err_tallying2_pg 0 7 RWX n 0011111 +# rx_dyn_rpr_err_cntr2_duration ediei4 0 99 rx_dyn_rpr_err_tallying2_pg 7 4 RWX n 0111 +# rx_dyn_rpr_clr_err_cntr2 ediei4 0 99 rx_dyn_rpr_err_tallying2_pg 11 1 RWX n 0 +#--********************************************************************************************* +scom 0x800.0b(rx_dyn_rpr_err_tallying2_pg)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ + scom_data; + 0b0011111011100000; +#scom 0x800.0b(rx_dyn_rpr_err_tallying2_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_dyn_rpr_bad_bus_max, 0b0011111; # +# rx_dyn_rpr_err_cntr2_duration, 0b0111; # tap 7 +} +#------------------------------------------------------------------------------------- +# __ ___ __ __ ___ __ +# / |/ /___ ______/ /____ _____ / |/ /___ ____/ /__ +# / /|_/ / __ `/ ___/ __/ _ \/ ___/ / /|_/ / __ \/ __ / _ \ +# / / / / /_/ (__ ) /_/ __/ / / / / / /_/ / /_/ / __/ +# /_/ /_/\__,_/____/\__/\___/_/ /_/ /_/\____/\__,_/\___/ +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +# rx_master_mode ediei4 0 99 rx_mode_pg 0 1 RWX n 0 +# rx_disable_fence_reset ediei4 0 99 rx_mode_pg 1 1 RWX n 0 +# rx_pdwn_lite_disable edi 0 99 rx_mode_pg 2 1 RWX n 0 +# rx_use_sls_as_spr edi 0 99 rx_mode_pg 3 1 RWX n 0 +#--********************************************************************************************* +# Register has more than one possible non-zero field so can't use group broadcast write +#scom 0x800.0b(rx_mode_pg)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ +# scom_data, expr; +# 0x8000, (def_is_master); +# 0x0000, (def_is_slave); +scom 0x800.0b(rx_mode_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data, expr; + rx_master_mode, 0b1, (def_is_master); # Node/chip currently running has + rx_master_mode, 0b0, (def_is_slave); # +} +#------------------------------------------------------------------------------------- +# ____ ____ ____ _____ ______ _____ __ __ +# / __ \/ __ \/ __ ) ___/ /_ __/___ _____ / ___/___ / /__ _____/ /______ +# / /_/ / /_/ / __ \__ \ / / / __ `/ __ \ \__ \/ _ \/ / _ \/ ___/ __/ ___/ +# / ____/ _, _/ /_/ /__/ / / / / /_/ / /_/ / ___/ / __/ / __/ /__/ /_(__ ) +# /_/ /_/ |_/_____/____/ /_/ \__,_/ .___/ /____/\___/_/\___/\___/\__/____/ banner2 -fslant +# /_/ +#------------------------------------------------------------------------------------- +# PER-LANE (RX) +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +# rx_prbs_tap_id ediei4 0 99 rx_prbs_mode_pl 0 3 RWX n 000 +#--********************************************************************************************* +# *_grp_broadcast uses clock group broadcast addresses 0b001111 (RX) and 0b101111 (TX) to cut down the number of scom operations needed during scominit +# 0x8000B0000401103F, 0x8000B0200401103F, 0x8000B0400401103F, 0x8000B0600401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_0).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_a; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_0).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; +} +# 0x8000B0010401103F, 0x8000B0210401103F, 0x8000B0410401103F, 0x8000B0610401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_1).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_b; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_1).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; +} +# 0x8000B0020401103F, 0x8000B0220401103F, 0x8000B0420401103F, 0x8000B0620401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_2).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_c; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_2).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; +} +# 0x8000B0030401103F, 0x8000B0230401103F, 0x8000B0430401103F, 0x8000B0630401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_3).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_d; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_3).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; +} +# 0x8000B0040401103F, 0x8000B0240401103F, 0x8000B0440401103F, 0x8000B0640401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_4).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_e; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_4).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_e; +} +# 0x8000B0050401103F, 0x8000B0250401103F, 0x8000B0450401103F, 0x8000B0650401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_5).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_f; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_5).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_f; +} +# 0x8000B0060401103F, 0x8000B0260401103F, 0x8000B0460401103F, 0x8000B0660401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_6).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_g; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_6).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_g; +} +# 0x8000B0070401103F, 0x8000B0270401103F, 0x8000B0470401103F, 0x8000B0670401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_7).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_h; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_7).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_h; +} +# 0x8000B0080401103F, 0x8000B0280401103F, 0x8000B0480401103F, 0x8000B0680401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_8).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_a; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_8).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; +} +# 0x8000B0090401103F, 0x8000B0290401103F, 0x8000B0490401103F, 0x8000B0690401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_9).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_b; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_9).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; +} +# 0x8000B00A0401103F, 0x8000B02A0401103F, 0x8000B04A0401103F, 0x8000B06A0401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_10).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_c; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_10).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; +} +# 0x8000B00B0401103F, 0x8000B02B0401103F, 0x8000B04B0401103F, 0x8000B06B0401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_11).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_d; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_11).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; +} +# 0x8000B00C0401103F, 0x8000B02C0401103F, 0x8000B04C0401103F, 0x8000B06C0401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_12).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_e; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_12).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_e; +} +# 0x8000B00D0401103F, 0x8000B02D0401103F, 0x8000B04D0401103F, 0x8000B06D0401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_13).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_f; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_13).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_f; +} +# 0x8000B00E0401103F, 0x8000B02E0401103F, 0x8000B04E0401103F, 0x8000B06E0401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_14).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_g; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_14).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_g; +} +# 0x8000B00F0401103F, 0x8000B02F0401103F, 0x8000B04F0401103F, 0x8000B06F0401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_15).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_h; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_15).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_h; +} +# 0x8000B0100401103F, 0x8000B0300401103F, 0x8000B0500401103F, 0x8000B0700401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_16).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_a; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_16).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_a; +} +# 0x8000B0110401103F, 0x8000B0310401103F, 0x8000B0510401103F, 0x8000B0710401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_17).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_b; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_17).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_b; +} +# 0x8000B0120401103F, 0x8000B0320401103F, 0x8000B0520401103F, 0x8000B0720401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_18).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_c; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_18).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_c; +} +# 0x8000B0130401103F, 0x8000B0330401103F, 0x8000B0530401103F, 0x8000B0730401103F +scom 0x800.0b(rx_prbs_mode_pl)(rx_grp_broadcast)(lane_19).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_d; +#scom 0x800.0b(rx_prbs_mode_pl)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_19).0x(xbus0_gcr_addr){ +# bits, scom_data; +# rx_prbs_tap_id, rx_prbs_tap_id_pattern_d; +} +#------------------------------------------------------------------------------------- +# PER-LANE (TX) +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +# tx_prbs_tap_id ediei4 0 99 tx_prbs_mode_pl 0 3 RWX n 000 +#--********************************************************************************************* +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_0).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_a; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_0).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_1).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_b; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_1).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_2).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_c; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_2).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_3).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_d; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_3).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_4).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_e; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_4).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_e; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_5).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_f; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_5).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_f; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_6).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_g; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_6).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_g; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_7).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_h; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_7).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_h; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_8).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_a; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_8).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_9).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_b; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_9).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_10).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_c; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_10).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_11).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_d; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_11).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_12).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_e; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_12).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_e; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_13).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_f; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_13).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_f; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_14).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_g; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_14).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_g; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_15).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_h; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_15).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_h; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_16).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_a; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_16).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_a; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_17).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_b; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_17).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_b; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_18).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_c; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_18).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_c; +} +scom 0x800.0b(tx_prbs_mode_pl)(tx_grp_broadcast)(lane_19).0x(xbus0_gcr_addr){ + scom_data; + rx_prbs_tap_id_pattern_d; +#scom 0x800.0b(tx_prbs_mode_pl)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_19).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_prbs_tap_id, tx_prbs_tap_id_pattern_d; + +} +#------------------------------------------------------------------------------------- +# ____ __ __ +# / __ \/ / / / +# / /_/ / / / / +# / ____/ /___/ /___ +# /_/ /_____/_____/ banner2 -fslant +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +# rx_wt_cu_pll_pgood ediei4 0 99 rx_wiretest_pll_cntl_pg 0 1 RWX n 0 +# rx_wt_cu_pll_reset ediei4 0 99 rx_wiretest_pll_cntl_pg 1 1 RWX n 1 +# rx_wt_cu_pll_pgooddly ediei4 0 99 rx_wiretest_pll_cntl_pg 2 3 RWX n 000 +# rx_wt_cu_pll_lock ediei4 0 99 rx_wiretest_pll_cntl_pg 5 1 ROX n 0 +# rx_wt_pll_refclksel ediei4 0 99 rx_wiretest_pll_cntl_pg 6 1 RWX n 0 +# rx_pll_refclksel_scom_en edi 0 99 rx_wiretest_pll_cntl_pg 7 1 RWX n 0 +#--********************************************************************************************* +# TODO: Double check if this is needed here or not +# Register has more than one possible non-zero field so can't use group broadcast write +scom 0x800.0b(rx_wiretest_pll_cntl_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data; + rx_wt_cu_pll_reset, 0b0; # Put PLL in disabled state until Wiretest is started. + rx_wt_cu_pll_pgooddly, 0b000; # 16UI delay +} +#------------------------------------------------------------------------------------- +# ____ _ __________ ____ __ __ +# / __ \_____(_) _____ / ____/ / /__ / __ \____ _/ /_/ /____ _________ +# / / / / ___/ / | / / _ \ / / / / //_/ / /_/ / __ `/ __/ __/ _ \/ ___/ __ \ +# / /_/ / / / /| |/ / __/ / /___/ / ,< / ____/ /_/ / /_/ /_/ __/ / / / / / +# /_____/_/ /_/ |___/\___/ \____/_/_/|_| /_/ \__,_/\__/\__/\___/_/ /_/ /_/ +#------------------------------------------------------------------------------------- +#--********************************************************************************************* +# tx_drv_clk_pattern_gcrmsg ediei4 0 99 tx_clk_cntl_gcrmsg_pg 0 2 RWX n 10 +#--********************************************************************************************* +scom 0x800.0b(tx_clk_cntl_gcrmsg_pg)(tx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ + scom_data; + 0x0000; +#scom 0x800.0b(tx_clk_cntl_gcrmsg_pg)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(xbus0_gcr_addr){ +# bits, scom_data; +# tx_drv_clk_pattern_gcrmsg, 0b00; # Drive 0's to start out +} + +#--********************************************************************************************* +# rx_block_lock_lane ediei4 0 99 rx_cntl_pl 0 1 RWX n 0 +# rx_check_skew_lane ediei4 0 99 rx_cntl_pl 1 1 RWX n 0 +# rx_pdwn_lite edi 0 99 rx_cntl_pl 2 1 RWX n 0 +# rx_offcal_mode ediei4 0 99 rx_cntl_pl 3 1 RWX n 0 +#--********************************************************************************************* +# Register has more than one possible non-zero field so can't use group broadcast write +#scom 0x800.0b(rx_ei4_cal_cntl_pp)(rx_grp_broadcast)(lane_na).0x(xbus0_gcr_addr){ +# scom_data; +# 0x8000; +scom 0x800.0b(rx_ei4_cal_cntl_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr){ + bits, scom_data; + rx_block_lock_lane, 0b1; +} + + +############################################################################################ +# END OF FILE +############################################################################################ diff --git a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C index 8a76dfef9..f6671c10c 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C +++ b/src/usr/hwpf/hwp/nest_chiplets/nest_chiplets.C @@ -69,6 +69,10 @@ #include "proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H" #include "proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H" #include "proc_pcie_scominit/proc_pcie_scominit.H" +#include "../bus_training/pbusLinkSvc.H" +#include <fapiHwpExecInitFile.H> +const char * const PROC_CHIPLET_ABUS_IF = "p8.abus.scom.if"; +const char * const PROC_CHIPLET_XBUS_IF = "p8.xbus.scom.if"; namespace NEST_CHIPLETS { @@ -197,10 +201,11 @@ void* call_proc_a_x_pci_dmi_pll_setup( void *io_pArgs ) TARGETING::TargetHandleList l_procTargetList; getAllChips(l_procTargetList, TYPE_PROC); - for ( TargetHandleList::iterator l_iter = l_procTargetList.begin(); - l_iter != l_procTargetList.end(); ++l_iter ) + for (TARGETING::TargetHandleList::iterator l_cpuIter = + l_procTargetList.begin(); l_cpuIter != l_procTargetList.end(); + ++l_cpuIter) { - const TARGETING::Target* l_proc_target = *l_iter; + const TARGETING::Target* l_proc_target = *l_cpuIter; const fapi::Target l_fapi_proc_target( TARGET_TYPE_PROC_CHIP, reinterpret_cast<void *> @@ -354,16 +359,301 @@ void* call_proc_startclock_chiplets( void *io_pArgs ) void* call_proc_chiplet_scominit( void *io_pArgs ) { errlHndl_t l_err = NULL; + fapi::ReturnCode rc; + IStepError l_StepError; - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "call_proc_chiplet_scominit entry" ); + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_chiplet_scominit entry" ); - // proc_chiplet_scominit will be called when there are initfiles to execute + uint8_t l_cpuNum = 0; + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "call_proc_chiplet_scominit exit" ); + do + { + // ---------------------------------------------- + // Execute PROC_CHIPLET_SCOMINIT_FBC_IF initfile + // ---------------------------------------------- - return l_err; + for (TARGETING::TargetHandleList::iterator l_cpuIter = + l_cpuTargetList.begin(); l_cpuIter != l_cpuTargetList.end(); + ++l_cpuIter) + { + const TARGETING::Target* l_cpu_target = *l_cpuIter; + const fapi::Target l_fapi_proc_target( + TARGET_TYPE_PROC_CHIP, + reinterpret_cast<void *> + ( const_cast<TARGETING::Target*>(l_cpu_target) ) ); + + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running proc_chiplet_scominit HWP on..." ); + // dump physical path to targets + EntityPath l_path; + l_path = l_cpu_target->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + + // call the HWP with each fapi::Target + FAPI_INVOKE_HWP(l_err, proc_chiplet_scominit, l_fapi_proc_target); + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X : " + "proc_chiplet_scominit HWP returns error. Target 0x%.8X", + l_err->reasonCode(), TARGETING::get_huid(l_cpu_target)); + ErrlUserDetailsTarget myDetails(l_cpu_target); + /*@ + * @errortype + * @reasoncode ISTEP_PROC_CHIPLET_SCOMINIT_FAILED + * @severity ERRORLOG::ERRL_SEV_UNRECOVERABLE + * @moduleid ISTEP_PROC_CHIPLET_SCOMINIT + * @userdata1 bytes 0-1: plid identifying first error + * bytes 2-3: reason code of first error + * @userdata2 bytes 0-1: total number of elogs included + * bytes 2-3: N/A + * @devdesc call to proc_chiplet_scominit has failed + */ + l_StepError.addErrorDetails(ISTEP_PROC_CHIPLET_SCOMINIT_FAILED, + ISTEP_PROC_CHIPLET_SCOMINIT, + l_err ); + // We want to continue to the next target instead of exiting, + // Commit the error log and move on + // Note: Error log should already be deleted and set to NULL + // after committing + errlCommit(l_err, HWPF_COMP_ID); + } + } + + // ---------------------------------------------- + // Execute PROC_CHIPLET_ABUS/XBUS initfiles + // Note: the order is intentional to make + // HB and Cronus trace in the same order. + // Please do not change + // ---------------------------------------------- + + // Do XBUS first, get all XBUS connections + EDI_EI_INITIALIZATION::TargetPairs_t l_XbusConnections; + l_err = + EDI_EI_INITIALIZATION::PbusLinkSvc::getTheInstance().getPbusConnections( + l_XbusConnections, TYPE_XBUS, false); + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X : getPbusConnections XBUS returns error", + l_err->reasonCode()); + + // TODO - RTC 57977 + // Need to discuss with Jamie on how to handle this: + // - An istep may fail in multiple locations. The failure + // may not be always from invoking the HW procedures. + // It may come from support functions in this case. + // - How do we set the error tags and use reason code for different + // fail scenarios? + l_StepError.addErrorDetails(ISTEP_PROC_CHIPLET_SCOMINIT_FAILED, + ISTEP_PROC_CHIPLET_SCOMINIT, + l_err); + + // Shouldn't continue on this fatal error (no XBUS), break out + break; + } + + + // Loop thru the proc + for ( l_cpuNum=0; l_cpuNum < l_cpuTargetList.size(); l_cpuNum++ ) + { + const TARGETING::Target* l_cpuTarget = l_cpuTargetList[l_cpuNum]; + + // ---------------------------------------------- + // Execute PROC_CHIPLET_XBUS initfiles + // ---------------------------------------------- + TARGETING::TargetHandleList l_xbusList; + getChildChiplets( l_xbusList, l_cpuTarget, TYPE_XBUS ); + + // For each XBUS unit in this proc + for (size_t jj = 0; jj < l_xbusList.size(); jj++) + { + TARGETING::Target * l_xbusTarget = l_xbusList[jj]; + EDI_EI_INITIALIZATION::TargetPairs_t::iterator l_itr = + l_XbusConnections.find(l_xbusTarget); + if ( l_itr == l_XbusConnections.end() ) + { + continue; + } + + const TARGETING::Target *l_pParent = + getParentChip( + (const_cast<TARGETING::Target*>(l_itr->second))); + + // Targets to pass in HW procedure + std::vector<fapi::Target> targets; + + const fapi::Target l_fapi_xbus_target( + TARGET_TYPE_XBUS_ENDPOINT, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>(l_xbusTarget))); + targets.push_back(l_fapi_xbus_target); + + const fapi::Target l_fapi_this_cpu_target( + TARGET_TYPE_PROC_CHIP, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>( + l_cpuTarget))); + targets.push_back(l_fapi_this_cpu_target); + + const fapi::Target l_fapi_other_cpu_target( + TARGET_TYPE_PROC_CHIP, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>( + l_pParent))); + targets.push_back(l_fapi_other_cpu_target); + + // execute PROC_CHIPLET_XBUS_IF initfile + FAPI_INF("proc_chiplet_scominit: Executing %s on...", + PROC_CHIPLET_XBUS_IF); + EntityPath l_path = l_xbusTarget->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + l_path = l_cpuTarget->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + l_path = l_pParent->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + + FAPI_EXEC_HWP(rc, + fapiHwpExecInitFile, + targets, + PROC_CHIPLET_XBUS_IF); + + l_err = fapi::fapiRcToErrl(rc); + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s", + PROC_CHIPLET_XBUS_IF); + + l_StepError.addErrorDetails( + ISTEP_PROC_XBUS_IF_EXECUTION_FAILED, + ISTEP_PROC_CHIPLET_SCOMINIT, + l_err); + + // We want to continue to the next link instead of exiting, + // Commit the error log and move on + // Log should be deleted and set to NULL in errlCommit. + errlCommit(l_err, HWPF_COMP_ID); + } + + } // End xbus loop + + + } // End cpunum loop + + // Note: all error logs exist above must have been committed. + // We want to move on to the ABUS training. The usage of l_err + // again below should not cause mem leakage. + + // Now do ABUS, get all ABUS connections + EDI_EI_INITIALIZATION::TargetPairs_t l_AbusConnections; + l_err = + EDI_EI_INITIALIZATION::PbusLinkSvc::getTheInstance().getPbusConnections( + l_AbusConnections, TYPE_ABUS, false); + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X : getPbusConnections ABUS returns error", + l_err->reasonCode()); + + // TODO - RTC 57977 + // Need to discuss with Jamie on how to handle this: + // - An istep may fail in multiple locations. The failure + // may not be always from invoking the HW procedures. + // It may come from support functions in this case. + // - How do we set the error tags and use reason code for different + // fail scenarios? + l_StepError.addErrorDetails(ISTEP_PROC_CHIPLET_SCOMINIT_FAILED, + ISTEP_PROC_CHIPLET_SCOMINIT, + l_err); + + // Shouldn't continue on this fatal error (no ABUS), break out + break; + } + + // Loop thru the proc + for ( l_cpuNum=0; l_cpuNum < l_cpuTargetList.size(); l_cpuNum++ ) + { + const TARGETING::Target* l_cpuTarget = l_cpuTargetList[l_cpuNum]; + // Get the ABUS under this proc + TARGETING::TargetHandleList l_abusList; + getChildChiplets( l_abusList, l_cpuTarget, TYPE_ABUS ); + + // For each ABUS unit in this proc + for (size_t ii = 0; ii < l_abusList.size(); ii++) + { + TARGETING::Target * l_abusTarget = l_abusList[ii]; + EDI_EI_INITIALIZATION::TargetPairs_t::iterator l_itr = + l_AbusConnections.find(l_abusTarget); + if ( l_itr == l_AbusConnections.end() ) + { + continue; + } + + const TARGETING::Target *l_pParent = + getParentChip( + (const_cast<TARGETING::Target*>(l_itr->second))); + + // Targets to pass in HW procedure + std::vector<fapi::Target> targets; + + const fapi::Target l_fapi_abus_target( + TARGET_TYPE_ABUS_ENDPOINT, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>(l_abusTarget))); + targets.push_back(l_fapi_abus_target); + + const fapi::Target l_fapi_this_cpu_target( + TARGET_TYPE_PROC_CHIP, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>( + l_cpuTarget))); + targets.push_back(l_fapi_this_cpu_target); + + const fapi::Target l_fapi_other_cpu_target( + TARGET_TYPE_PROC_CHIP, + reinterpret_cast<void *> + (const_cast<TARGETING::Target*>( + l_pParent))); + targets.push_back(l_fapi_other_cpu_target); + + // execute PROC_CHIPLET_ABUS_IF initfile + FAPI_INF("proc_chiplet_scominit: Executing %s on...", + PROC_CHIPLET_ABUS_IF); + EntityPath l_path = l_abusTarget->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + l_path = l_cpuTarget->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + l_path = l_pParent->getAttr<ATTR_PHYS_PATH>(); + l_path.dump(); + + FAPI_EXEC_HWP(rc, + fapiHwpExecInitFile, + targets, + PROC_CHIPLET_ABUS_IF); + l_err = fapi::fapiRcToErrl(rc); + if (l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s", + PROC_CHIPLET_ABUS_IF); + + l_StepError.addErrorDetails( + ISTEP_PROC_ABUS_IF_EXECUTION_FAILED, + ISTEP_PROC_CHIPLET_SCOMINIT, + l_err); + + // We want to continue to the next link instead of exiting, + // Commit the error log and move on + // Log should be deleted and set to NULL in errlCommit. + errlCommit(l_err, HWPF_COMP_ID); + } + } // End abus list loop + + } // End cpunum loop + + + } while (0); + + return l_StepError.getErrorHandle(); } //***************************************************************************** diff --git a/src/usr/hwpf/hwp/slave_sbe/slave_sbe.C b/src/usr/hwpf/hwp/slave_sbe/slave_sbe.C index 1142a51a7..f395f7894 100644 --- a/src/usr/hwpf/hwp/slave_sbe/slave_sbe.C +++ b/src/usr/hwpf/hwp/slave_sbe/slave_sbe.C @@ -76,6 +76,9 @@ void* call_proc_revert_sbe_mcs_setup(void *io_pArgs) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_revert_sbe_mcs_setup entry" ); + // Note: Even though Cronus trace shows this HWP runs on all proc, + // this should be done only for Master chip per Dean. + TARGETING::Target* l_pProcTarget = NULL; TARGETING::targetService().masterProcChipTargetHandle(l_pProcTarget); |
