diff options
Diffstat (limited to 'src/usr/hwpf/hwp/nest_chiplets')
11 files changed, 0 insertions, 4395 deletions
diff --git a/src/usr/hwpf/hwp/nest_chiplets/makefile b/src/usr/hwpf/hwp/nest_chiplets/makefile deleted file mode 100644 index c300c808e..000000000 --- a/src/usr/hwpf/hwp/nest_chiplets/makefile +++ /dev/null @@ -1,61 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/hwpf/hwp/nest_chiplets/makefile $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -ROOTPATH = ../../../../.. - -MODULE = nest_chiplets - -## support for Targeting and fapi -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp - -## pointer to common HWP files -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include - -## Include sub dirs -## NOTE: add a new EXTRAINCDIR when you add a new HWP -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/secure_boot - -## NOTE: add new object files when you add a new HWP -OBJS += proc_start_clocks_chiplets.o -OBJS += proc_a_x_pci_dmi_pll_initf.o -OBJS += proc_a_x_pci_dmi_pll_setup.o -OBJS += proc_a_x_pci_dmi_pll_utils.o -OBJS += proc_pcie_slot_power.o - - -## NOTE: add a new directory onto the vpaths when you add a new HWP -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power - -include ${ROOTPATH}/config.mk - diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C deleted file mode 100644 index b58d55429..000000000 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C +++ /dev/null @@ -1,422 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_initf.C,v 1.20 2015/05/14 21:03:40 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_initf.C,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_a_x_pci_dmi_pll_initf.C -// *! DESCRIPTION : Scan PLL settings for A/X/PCI/DMI PLLs -// *! -// *! OWNER NAME : Ralph Koester Email: rkoester@de.ibm.com -// *! -// *! The purpose of this procedure is to scan in runtime PLL settings -// *! for the X/A/PCIE/DMI PLLs -// *! -// *! - prerequisite is that the PLLs are in bypass mode -// *! - setup the PLLs by a ring load of PLL config bits -// *! -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <p8_scom_addresses.H> -#include <proc_a_x_pci_dmi_pll_initf.H> -#include <proc_a_x_pci_dmi_pll_utils.H> - - -//------------------------------------------------------------------------------ -// Constant definitons -//------------------------------------------------------------------------------ -const uint32_t DMI_PLL_VCO_WORKAROUND_THRESHOLD_FREQ = 4800; - - -//------------------------------------------------------------------------------ -// Function definition -//------------------------------------------------------------------------------ - -extern "C" -{ - - -//------------------------------------------------------------------------------ -// function: -// Scan PLL settings for A/X/PCI/DMI PLLs -// -// parameters: i_target => chip target -// i_startX => True to start X BUS PLL, else false -// i_startA => True to start A BUS PLL, else false -// i_startPCIE => True to start PCIE PLL, else false -// i_startDMI => True to start DMI PLL, else false -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_a_x_pci_dmi_pll_initf( - const fapi::Target & i_target, - const bool i_startX, - const bool i_startA, - const bool i_startPCIE, - const bool i_startDMI) -{ - // attribute data - uint8_t pcie_enable_attr; - uint8_t abus_enable_attr; - uint8_t is_simulation; - uint8_t lctank_pll_vco_workaround = 0; - - // return codes - fapi::ReturnCode rc; - - // mark function entry - FAPI_INF("\n Parameter1, start_XBUS=%s\n Parameter2, start_ABUS=%s\n Parameter3, start_PCIE=%s\n Parameter4, start_DMI=%s \n" , - i_startX ? "true":"false", - i_startA ? "true":"false", - i_startPCIE ? "true":"false", - i_startDMI ? "true":"false"); - do - { - //------------// - // Workaround // - //------------// - rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, - NULL, - is_simulation); - if (!rc.ok()) - { - FAPI_ERR("Error querying ATTR_IS_SIMULATION"); - break; - } - - if (!is_simulation) - { - rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_LCTANK_PLL_VCO_BUG, - &i_target, - lctank_pll_vco_workaround); - if (!rc.ok()) - { - FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_LCTANK_PLL_VCO_BUG"); - break; - } - } - - FAPI_DBG("lctank PLL VCO bug circumvention is %s", - (lctank_pll_vco_workaround ? "enabled" : "disabled")); - - - //------------// - // X Bus PLL // - //------------// - if (!i_startX) - { - FAPI_DBG("X BUS PLL not selected for setup in this routine."); - } - else - { - FAPI_INF("This routine does not do X-BUS PLL setup at this time!."); - FAPI_INF("It is assumed that the X-BUS PLL is already set up in synchronous mode for use with the NEST logic."); - } - // end X-bus PLL setup - - - //------------// - // A Bus PLL // - //------------// - - // query ABUS partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, - &i_target, - abus_enable_attr); - if (!rc.ok()) - { - FAPI_ERR("Error querying ATTR_PROC_A_ENABLE"); - break; - } - - if (!i_startA) - { - FAPI_DBG("A BUS PLL not selected for setup in this routine."); - } - else if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) - { - FAPI_DBG("A BUS PLL setup skipped (partial good)."); - } - else - { - // apply workaround for A PLL for all frequencies - bool a_lctank_pll_vco_workaround = (lctank_pll_vco_workaround != 0); - FAPI_DBG("A-Bus PLL VCO bug circumvention is %s", - (a_lctank_pll_vco_workaround ? "enabled" : "disabled")); - - // establish base ring state - rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target, - RING_ADDRESS_PROC_AB_BNDY_PLL, - RING_OP_BASE, - RING_BUS_ID_0, - false); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); - break; - } - - if (a_lctank_pll_vco_workaround) - { - rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target, - RING_ADDRESS_PROC_AB_BNDY_PLL, - RING_OP_MOD_VCO_S1, - RING_BUS_ID_0, - false); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); - break; - } - - // release PLL (skip lock check) & re-scan - rc = proc_a_x_pci_dmi_pll_release_pll(i_target, - A_BUS_CHIPLET_0x08000000, - false); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll"); - break; - } - - rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target, - RING_ADDRESS_PROC_AB_BNDY_PLL, - RING_OP_MOD_VCO_S2, - RING_BUS_ID_0, - false); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); - break; - } - } - FAPI_INF("Done setting up A-Bus PLL. "); - } // end A PLL - - - //----------// - // DMI PLL // - //----------// - if (!i_startDMI) - { - FAPI_DBG("DMI PLL not selected for setup in this routine."); - } - else - { - // only apply DMI workaround if needed when frequency < 4800 MHz, - bool dmi_lctank_pll_vco_workaround = (lctank_pll_vco_workaround != 0); - uint32_t dmi_freq; - if (dmi_lctank_pll_vco_workaround) - { - // frequency reported via X attribute should be equivalent to DMI freq - // given that we are running NEST off of X-bus PLL (NEST=X/2) and - // DMI=NEST*2 - rc = FAPI_ATTR_GET(ATTR_FREQ_X, NULL, dmi_freq); - if (!rc.ok()) - { - FAPI_ERR("Failed to get attribute: ATTR_FREQ_X"); - break; - } - - if (dmi_freq >= DMI_PLL_VCO_WORKAROUND_THRESHOLD_FREQ) - { - dmi_lctank_pll_vco_workaround = false; - } - } - FAPI_DBG("DMI PLL VCO bug circumvention is %s", - (dmi_lctank_pll_vco_workaround ? "enabled" : "disabled")); - - // establish base ring state - rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target, - RING_ADDRESS_PROC_PB_BNDY_DMIPLL, - RING_OP_BASE, - RING_BUS_ID_0, - true); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); - break; - } - - if (dmi_lctank_pll_vco_workaround) - { - rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target, - RING_ADDRESS_PROC_PB_BNDY_DMIPLL, - RING_OP_MOD_VCO_S1, - RING_BUS_ID_0, - true); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); - break; - } - - // release PLL (skip lock check) & re-scan - rc = proc_a_x_pci_dmi_pll_release_pll(i_target, - NEST_CHIPLET_0x02000000, - false); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll"); - break; - } - - rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target, - RING_ADDRESS_PROC_PB_BNDY_DMIPLL, - RING_OP_MOD_VCO_S2, - RING_BUS_ID_0, - true); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); - break; - } - } - - FAPI_INF("Done setting up DMI PLL. "); - } // end DMI PLL - - - //-----------// - // PCIE PLL // - //-----------// - - // query PCIE partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE, - &i_target, - pcie_enable_attr); - if (!rc.ok()) - { - FAPI_ERR("Error querying ATTR_PROC_PCIE_ENABLE"); - break; - } - - if (!i_startPCIE) - { - FAPI_DBG("PCIE PLL not selected for setup in this routine."); - } - else if (pcie_enable_attr != fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) - { - FAPI_DBG("PCIE PLL setup skipped (partial good)."); - } - else - { - // establish base ring state - rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target, - RING_ADDRESS_PROC_PCI_BNDY_PLL, - RING_OP_BASE, - RING_BUS_ID_0, - false); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy"); - break; - } - - FAPI_INF("Done setting up PCIE PLL."); - } // end PCIE PLL - - } while (0); // end do - - // mark function exit - FAPI_INF("Exit"); - return rc; -} // end FAPI procedure proc_a_x_pci_dmi_pll_initf - - -} // extern "C" - -/* -*************** Do not edit this area *************** -This section is automatically updated by CVS when you check in this file. -Be sure to create CVS comments when you commit so that they can be included here. -$Log: proc_a_x_pci_dmi_pll_initf.C,v $ -Revision 1.20 2015/05/14 21:03:40 jmcgill -Update to use modified proc_a_x_pci_dmi_pll_utils API - -Revision 1.19 2014/12/02 00:17:23 szhong -remove hardcoded bndy pll length in code - -Revision 1.18 2014/11/13 20:17:22 szhong -adjust pb_bndy_dmi_pll length to 240 - -Revision 1.17 2014/11/11 22:10:35 szhong -increased attribute data length to support Naples - -Revision 1.16 2014/01/07 14:43:23 mfred -Checking in updates from Andrea Ma: Include statements fixed and one fapi dbg statement changed. - -Revision 1.15 2013/09/30 16:09:56 jmcgill -fix HW268965 - -Revision 1.14 2013/04/29 16:38:51 jmcgill -add constants for Murano DD1 ccalload/ccalfmin ring offsets used in workaround - -Revision 1.13 2013/04/18 17:33:35 jmcgill -qualify workaround for DMI bus based on frequency - -Revision 1.12 2013/04/17 22:38:38 jmcgill -implement A/DMI PLL workaround for SW194943, reorganize code to use common subroutines for PLL scan/setup - -Revision 1.11 2013/01/24 16:34:45 jmcgill -fix comment as well... - -Revision 1.10 2013/01/24 16:33:40 jmcgill -adjust for DMI attribute change - -Revision 1.9 2013/01/20 19:21:03 jmcgill -update for A chiplet partial good support - -Revision 1.8 2013/01/10 14:42:53 jmcgill -add partial good support - -Revision 1.6 2012/12/07 17:09:39 mfred -fix to add DMI PLL settings for MC1 for Venice. - -Revision 1.5 2012/12/06 22:59:18 mfred -adjust DMI PLL settings based on chip type. - -Revision 1.4 2012/08/27 15:29:03 mfred -Fixed some findings from the latest FW code review. - -Revision 1.3 2012/08/20 16:00:09 jmcgill -adjust ring offsets for 39 model - -Revision 1.2 2012/08/14 18:32:42 mfred -Changed input parms from bool & to const bool. - -Revision 1.1 2012/08/14 14:18:02 mfred -Separating proc_a_x_pci_dmi_pll_setup into two hwp. And update code to use real scanning instead of sim cheats. - - -*/ - diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H deleted file mode 100644 index c7f14c671..000000000 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H +++ /dev/null @@ -1,87 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_initf.H,v 1.5 2015/05/14 21:03:42 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_initf.H,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_a_x_pci_dmi_pll_initf.H -// *! DESCRIPTION : Scan PLL settings for A/X/PCI/DMI PLLs -// *! -// *! OWNER NAME : Ralph Koester Email: rkoester@de.ibm.com -// *! -//------------------------------------------------------------------------------ - -#ifndef _PROC_A_X_PCI_DMI_PLL_INITF_H_ -#define _PROC_A_X_PCI_DMI_PLL_INITF_H_ - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <fapi.H> - - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*proc_a_x_pci_dmi_pll_initf_FP_t)(const fapi::Target &, - const bool, - const bool, - const bool, - const bool); - -//------------------------------------------------------------------------------ -// Function prototypes -//------------------------------------------------------------------------------ - -extern "C" -{ - -/** - * @brief Scan PLL settings for A/X/PCI/DMI PLLs - * - * @param[in] i_target Reference to target - * @param[in] i_startX True if X PLL should be initalized, else false - * @param[in] i_startA True if A PLL should be initalized, else false - * @param[in] i_startPCIE True if PCIE PLL should be initalized, else false - * @param[in] i_startDMI True if DMI PLL should be initalized, else false - * - * @return ReturnCode - */ -fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(const fapi::Target & i_target, - const bool i_startX, - const bool i_startA, - const bool i_startPCIE, - const bool i_startDMI); - -} // extern "C" - -#endif // _PROC_A_X_PCI_DMI_PLL_INITF_H_ diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C deleted file mode 100644 index 004ed3b44..000000000 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C +++ /dev/null @@ -1,383 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_setup.C,v 1.16 2014/08/27 14:53:40 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_setup.C,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_a_x_pci_dmi_pll_setup.C -// *! DESCRIPTION : Initialize and lock A/X/PCI/DMI PLLs -// *! -// *! OWNER NAME : Ralph Koester Email: rkoester@de.ibm.com -// *! -// *! The purpose of this procedure is to initialize (remove from reset/bypass) -// *! and lock the X/A/PCIE/DMI PLLs -// *! -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <p8_scom_addresses.H> -#include <proc_a_x_pci_dmi_pll_setup.H> -#include <proc_a_x_pci_dmi_pll_utils.H> - - - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -const uint64_t GENERIC_PCB_CONFIG_0x000F001E = 0x000F001EULL; - - -//------------------------------------------------------------------------------ -// Function definition -//------------------------------------------------------------------------------ - -extern "C" -{ - -//------------------------------------------------------------------------------ -// function: -// Clear and unmask chiplet PLL lock indication -// -// parameters: i_target => chip target -// i_chiplet_base_scom_addr => aligned base address of chiplet SCOM -// address space -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_a_x_pci_dmi_pll_setup_unmask_lock(const fapi::Target & i_target, - const uint32_t i_chiplet_base_scom_addr) -{ - // return codes - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - - // data buffer to hold register values - ecmdDataBufferBase data(64); - - do - { - rc = fapiGetScom(i_target, - i_chiplet_base_scom_addr | GENERIC_PCB_ERR_0x000F001F, - data); - if (!rc.ok()) - { - FAPI_ERR("Error reading PCB Slave PLL Lock Indication"); - break; - } - - rc_ecmd |= data.setBit(25); // set bit to clear previous lock errors - rc_ecmd |= data.setBit(26); // set bit to clear previous lock errors - rc_ecmd |= data.setBit(27); // set bit to clear previous lock errors - rc_ecmd |= data.setBit(28); // set bit to clear previous lock errors - - if (rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up PLL Lock Indication ecmdDataBufferBase", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - FAPI_INF("Clearing PCB Slave Lock Indication Bit 25,26,27,28"); - rc = fapiPutScom(i_target, - i_chiplet_base_scom_addr | GENERIC_PCB_ERR_0x000F001F, - data); - if (!rc.ok()) - { - FAPI_ERR("Error writing PCB Slave PLL Lock Indication"); - break; - } - - rc = fapiGetScom(i_target, - i_chiplet_base_scom_addr | GENERIC_PCB_CONFIG_0x000F001E, - data); - if (!rc.ok()) - { - FAPI_ERR("Error reading PCB Slave PLL Lock Mask"); - break; - } - - rc_ecmd |= data.clearBit(12); // set bit to clear PLL Lock Mask - - if (rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up PLL Lock Mask ecmdDataBufferBase", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - FAPI_INF("Clearing PCB Slave Lock Mask Bit 12"); - rc = fapiPutScom(i_target, - i_chiplet_base_scom_addr | GENERIC_PCB_CONFIG_0x000F001E, - data); - if (!rc.ok()) - { - FAPI_ERR("Error writing PCB Slave Lock Mask"); - break; - } - } while(0); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: -// Initialize and lock A/X/PCI/DMI PLLs -// -// parameters: i_target => chip target -// i_startX => True to start X BUS PLL, else false -// i_startA => True to start A BUS PLL, else false -// i_startPCIE => True to start PCIE PLL, else false -// i_startDMI => True to start DMI PLL, else false -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ - fapi::ReturnCode proc_a_x_pci_dmi_pll_setup(const fapi::Target & i_target, - const bool i_startX, - const bool i_startA, - const bool i_startPCIE, - const bool i_startDMI) - { - // data buffer to hold register values - ecmdDataBufferBase gp_data(64); - ecmdDataBufferBase scom_data(64); - - - // return codes - fapi::ReturnCode rc; - - // locals - uint8_t pcie_enable_attr; - uint8_t abus_enable_attr; - - // mark function entry - FAPI_INF("Entry1, start_XBUS=%s\n, Entry2, start_ABUS=%s\n, Entry3, start_PCIE=%s\n, Entry4, start_DMI=%s \n" , - i_startX? "true":"false", - i_startA? "true":"false", - i_startPCIE? "true":"false", - i_startDMI? "true":"false"); - - do - { - //------------// - // X Bus PLL // - //------------// - if (!i_startX) - { - FAPI_DBG("X BUS PLL not selected for setup in this routine."); - } - else - { - FAPI_INF("This routine does not do X-BUS PLL setup at this time!."); - FAPI_INF("It is assumed that the X-BUS PLL is already set up in synchronous mode for use with the NEST logic."); - - rc = proc_a_x_pci_dmi_pll_setup_unmask_lock( - i_target, - TP_CHIPLET_0x01000000); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_setup_unmask_lock"); - break; - } - } - // end X-bus PLL setup - - - - //------------// - // A Bus PLL // - //------------// - - // query ABUS partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, - &i_target, - abus_enable_attr); - if (!rc.ok()) - { - FAPI_ERR("Error querying ATTR_PROC_A_ENABLE"); - break; - } - - if (!i_startA) - { - FAPI_DBG("A BUS PLL not selected for setup in this routine."); - } - else if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) - { - FAPI_DBG("A BUS PLL setup skipped (partial good)."); - } - else - { - FAPI_DBG("Starting PLL setup for A BUS PLL ..."); - rc = proc_a_x_pci_dmi_pll_release_pll( - i_target, - A_BUS_CHIPLET_0x08000000, - true); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll"); - break; - } - - rc = proc_a_x_pci_dmi_pll_setup_unmask_lock( - i_target, - A_BUS_CHIPLET_0x08000000); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_setup_unmask_lock"); - break; - } - - FAPI_INF("Done setting up A-Bus PLL. "); - } // end A PLL - - - //----------// - // DMI PLL // - //----------// - if (!i_startDMI) - { - FAPI_DBG("DMI PLL not selected for setup in this routine."); - } - else - { - FAPI_DBG("Starting PLL setup for DMI PLL ..."); - rc = proc_a_x_pci_dmi_pll_release_pll( - i_target, - NEST_CHIPLET_0x02000000, - true); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll"); - break; - } - rc = proc_a_x_pci_dmi_pll_setup_unmask_lock( - i_target, - NEST_CHIPLET_0x02000000); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_setup_unmask_lock"); - break; - } - - FAPI_INF("Done setting up DMI PLL. "); - } // end DMI PLL - - - //-----------// - // PCIE PLL // - //-----------// - - // query PCIE partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE, - &i_target, - pcie_enable_attr); - if (!rc.ok()) - { - FAPI_ERR("Error querying ATTR_PROC_PCIE_ENABLE"); - break; - } - - if (!i_startPCIE) - { - FAPI_DBG("PCIE PLL not selected for setup in this routine."); - } - else if (pcie_enable_attr != fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) - { - FAPI_DBG("PCIE PLL setup skipped (partial good)."); - } - else - { - FAPI_DBG("Starting PLL setup for PCIE PLL ..."); - rc = proc_a_x_pci_dmi_pll_release_pll( - i_target, - PCIE_CHIPLET_0x09000000, - true); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll"); - break; - } - - FAPI_INF("Done setting up PCIE PLL. "); - - } // end PCIE PLL - - } while (0); // end do - - // mark function exit - FAPI_INF("Exit"); - return rc; - } // end FAPI procedure proc_a_x_pci_dmi_pll_setup - -} // extern "C" - -/* -*************** Do not edit this area *************** -This section is automatically updated by CVS when you check in this file. -Be sure to create CVS comments when you commit so that they can be included here. -$Log: proc_a_x_pci_dmi_pll_setup.C,v $ -Revision 1.16 2014/08/27 14:53:40 jmcgill -shift PCI PLL unlock reporting from istep 7 -> 14 (SW273877) - -Revision 1.15 2014/04/02 14:02:33 jmcgill -respect function input parameters/partial good in unlock error clear/unmask logic (SW252901) - -Revision 1.14 2014/03/28 15:25:39 bgeukes -updates for SW252901 after RAS review - -Revision 1.13 2014/03/27 17:58:08 bgeukes -fix for the scominit updates - -Revision 1.12 2014/01/07 14:43:34 mfred -Checking in updates from Andrea Ma: Include statements fixed and one fapi dbg statement changed. - -Revision 1.11 2013/04/17 22:38:42 jmcgill -implement A/DMI PLL workaround for SW194943, reorganize code to use common subroutines for PLL scan/setup - -Revision 1.10 2013/01/25 19:30:22 mfred -Release PLLs from bypass before checking for PLL lock. Also, check for two lock bits on DMI PLL to support Venice. - -Revision 1.9 2013/01/20 19:22:44 jmcgill -update for A chiplet partial good support - -Revision 1.8 2013/01/10 14:40:13 jmcgill -add partial good support - -Revision 1.7 2012/08/14 18:32:45 mfred -Changed input parms from bool & to const bool. - -Revision 1.6 2012/08/14 14:18:06 mfred -Separating proc_a_x_pci_dmi_pll_setup into two hwp. And update code to use real scanning instead of sim cheats. - - -*/ - diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H deleted file mode 100644 index ce3df4d2e..000000000 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H +++ /dev/null @@ -1,94 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_setup.H,v 1.8 2014/08/27 14:53:48 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_setup.H,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_a_x_pci_dmi_pll_setup.H -// *! DESCRIPTION : Initialize and lock A/X/PCI/DMI PLLs -// *! -// *! OWNER NAME : Ralph Koester Email: rkoester@de.ibm.com -// *! -//------------------------------------------------------------------------------ - -#ifndef _PROC_A_X_PCI_DMI_PLL_SETUP_H_ -#define _PROC_A_X_PCI_DMI_PLL_SETUP_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <fapi.H> - - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*proc_a_x_pci_dmi_pll_setup_FP_t)(const fapi::Target &, - const bool, const bool, const bool, const bool); - -//------------------------------------------------------------------------------ -// Function prototypes -//------------------------------------------------------------------------------ - -extern "C" -{ - -/* - * @brief Clear and unmask chiplet PLL lock indication - * @param[in] i_target Reference to target - * @param[in] i_chiplet_base_scom_addr Aligned base address of chiplet SCOM - * address space - * @return ReturnCode - */ - fapi::ReturnCode proc_a_x_pci_dmi_pll_setup_unmask_lock(const fapi::Target & i_target, - const uint32_t i_chiplet_base_scom_addr); - -/** - * @brief Initialize and lock A/X/PCI/DMI PLLs - * - * @param[in] i_target Reference to target - * @param[in] i_startX True if x_bus PLL should be started, else false - * @param[in] i_startA True if A PLL should be started, else false - * @param[in] i_startPCIE True if PCIE PLL should be started, else false - * @param[in] i_startDMI True if DMI PLL should be started, else false - * - * @return ReturnCode - */ - fapi::ReturnCode proc_a_x_pci_dmi_pll_setup(const fapi::Target & i_target, - const bool i_startX, - const bool i_startA, - const bool i_startPCIE, - const bool i_startDMI); - -} // extern "C" - -#endif // _PROC_A_X_PCI_DMI_PLL_SETUP_H_ diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C deleted file mode 100644 index de733a395..000000000 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C +++ /dev/null @@ -1,1432 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_utils.C,v 1.9 2015/08/14 16:31:17 thi Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_utils.C,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2015 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_a_x_pci_dmi_pll_utils.C -// *! DESCRIPTION : PLL configuration utility functions -// *! -// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -// *! -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <p8_scom_addresses.H> -#include <proc_a_x_pci_dmi_pll_utils.H> -#include <p8_istep_num.H> -#include <proc_sbe_scan_service.H> -#include <proc_use_sbe_scan_service.H> - - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// SBE polling constants -const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_SBE_MAX_POLLS = 100; -const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_SBE_POLL_DELAY_HW = 2000000; -const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_SBE_POLL_DELAY_SIM = 0; - -// SBE Control Register field/bit definitions -const uint32_t SBE_CONTROL_REG_CTL_NO_LB_BIT = 0; - -// SBE Mailbox0 Register scan request format constants -const uint32_t MBOX0_REQUEST_VALID_BIT = 0; -const uint32_t MBOX0_RING_SELECT_START_BIT = 6; -const uint32_t MBOX0_RING_SELECT_END_BIT = 7; -const uint32_t MBOX0_RING_OP_START_BIT = 9; -const uint32_t MBOX0_RING_OP_END_BIT = 11; -const uint32_t MBOX0_RING_BUS_ID_START_BIT = 13; -const uint32_t MBOX0_RING_BUS_ID_END_BIT = 15; - -// SBE MBOX1 Scratch Register scan reply format constants -const uint32_t MBOX1_SCAN_REPLY_SUCCESS_BIT = 0; - -// VCO PLL workaround ring offsets -const uint32_t PB_BNDY_DMIPLL_RING_CCALLOAD_OFFSET = 580; -const uint32_t PB_BNDY_DMIPLL_RING_CCALFMIN_OFFSET = 581; - -const uint32_t AB_BNDY_PLL_RING_CCALLOAD_OFFSET = 278; -const uint32_t AB_BNDY_PLL_RING_CCALFMIN_OFFSET = 279; - -// PLL lock polling constants -const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_MAX_LOCK_POLLS = 50; -const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_HW = 2000000; -const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_SIM = 1; - -// Pervasive LFIR Register field/bit definitions -const uint8_t PERV_LFIR_SCAN_COLLISION_BIT = 3; - -// OPCG/Clock Region Register values -const uint64_t OPCG_REG0_FOR_SETPULSE = 0x818C000000000000ull; -const uint64_t OPCG_REG2_FOR_SETPULSE = 0x0000000000002000ull; -const uint64_t OPCG_REG3_FOR_SETPULSE = 0x6000000000000000ull; -const uint64_t CLK_REGION_FOR_SETPULSE = 0x0010040000000000ull; - -// GP3 Register field/bit definitions -const uint8_t GP3_PLL_TEST_ENABLE_BIT = 3; -const uint8_t GP3_PLL_RESET_BIT = 4; -const uint8_t GP3_PLL_BYPASS_BIT = 5; - -// PLL Lock Register field/bit definitions -const uint8_t PLL_LOCK_REG_LOCK_START_BIT = 0; -const uint8_t PLL_LOCK_REG_LOCK_END_BIT = 3; - - -//------------------------------------------------------------------------------ -// Function definitions -//------------------------------------------------------------------------------ - -extern "C" -{ - -using namespace fapi; - -//------------------------------------------------------------------------------ -// function: -// Calculate state to apply to Centaur tp_bndy_pll ring -// -// parameters: i_target => chip target -// i_pll_ring_op => modification to be made to PLL content -// o_ring_data => data buffer containing ring state to apply -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode p8_pll_utils_calc_memb_tp_bndy_pll( - const fapi::Target & i_target, - const p8_pll_utils_ring_op i_pll_ring_op, - ecmdDataBufferBase & o_ring_data) -{ - // return codes - uint32_t rc_ecmd = 0; - fapi::ReturnCode rc; - - // mark function entry - FAPI_DBG("Start"); - - do - { - // determine ring length - fapi::ATTR_MEMB_TP_BNDY_PLL_LENGTH_Type ring_length; - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_LENGTH, &i_target, ring_length); - if (!rc.ok()) - { - FAPI_ERR("Failed to get attribute: ATTR_MEMB_TP_BNDY_PLL_LENGTH."); - break; - } - rc_ecmd |= o_ring_data.setBitLength(ring_length); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // determine starting ring state - if (i_pll_ring_op == RING_OP_BASE) - { - // start from attribute data - fapi::ATTR_MEMB_TP_BNDY_PLL_DATA_Type ring_data_attr = {0}; - rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_DATA, &i_target, ring_data_attr); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_MEMB_TP_BNDY_PLL_DATA."); - break; - } - rc_ecmd |= o_ring_data.insert(ring_data_attr, 0, ring_length, 0); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - else - { - // start from data currently in ring - rc = fapiGetRing(i_target, RING_ADDRESS_MEMB_TP_BNDY_PLL, o_ring_data, fapi::RING_MODE_SET_PULSE); - if (!rc.ok()) - { - FAPI_ERR("Error from fapiGetRing (ring ID: 0x08%x)", RING_ADDRESS_MEMB_TP_BNDY_PLL); - break; - } - } - - // modify ring data - if (i_pll_ring_op == RING_OP_MOD_REFCLK_SEL) - { - fapi::ATTR_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET_Type refclksel_offset; - rc = FAPI_ATTR_GET(ATTR_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET, &i_target, refclksel_offset); - if (!rc.ok()) - { - FAPI_ERR("Failed to get attribute: ATTR_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET"); - break; - } - - if (o_ring_data.isBitClear(refclksel_offset)) - { - rc_ecmd |= o_ring_data.setBit(refclksel_offset); - } - else - { - rc_ecmd |= o_ring_data.clearBit(refclksel_offset); - } - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading refclock select attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - else if (i_pll_ring_op == RING_OP_MOD_PFD360) - { - fapi::ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET_Type pfd360_offset; - rc = FAPI_ATTR_GET(ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET, &i_target, pfd360_offset); - if (!rc.ok()) - { - FAPI_ERR("Failed to get attribute: ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET"); - break; - } - - if (o_ring_data.isBitClear(pfd360_offset)) - { - rc_ecmd |= o_ring_data.setBit(pfd360_offset); - } - else - { - rc_ecmd |= o_ring_data.clearBit(pfd360_offset); - } - - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading pfd360 attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - } while(0); - - // mark function exit - FAPI_DBG("End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: -// Calculate state to apply to processor pci_bndy_pll ring -// -// parameters: i_target => chip target -// o_ring_data => data buffer containing ring state to apply -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode p8_pll_utils_calc_proc_pci_bndy_pll( - const fapi::Target & i_target, - ecmdDataBufferBase & o_ring_data) -{ - // return codes - uint32_t rc_ecmd = 0; - fapi::ReturnCode rc; - - // mark function entry - FAPI_DBG("Start"); - - do - { - // determine ring length - fapi::ATTR_PROC_PCI_BNDY_PLL_LENGTH_Type ring_length; - rc = FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_LENGTH, &i_target, ring_length); - if (!rc.ok()) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_PCI_BNDY_PLL_LENGTH."); - break; - } - rc_ecmd |= o_ring_data.setBitLength(ring_length); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // determine starting ring state - fapi::ATTR_PROC_PCI_BNDY_PLL_DATA_Type ring_data_attr = {0}; - rc = FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_DATA, &i_target, ring_data_attr); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_PCI_BNDY_PLL_DATA."); - break; - } - rc_ecmd |= o_ring_data.insert(ring_data_attr, 0, ring_length, 0); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } while(0); - - // mark function exit - FAPI_DBG("End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: -// Calculate state to apply to processor pb_bndy_dmipll ring -// -// parameters: i_target => chip target -// i_pll_ring_op => modification to be made to base PLL content -// i_pll_bus_id => bus instance to target for modification -// o_ring_data => data buffer containing ring state to apply -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode p8_pll_utils_calc_proc_pb_bndy_dmipll( - const fapi::Target & i_target, - const p8_pll_utils_ring_op i_pll_ring_op, - const p8_pll_utils_bus_id i_pll_bus_id, - ecmdDataBufferBase & o_ring_data) -{ - // return codes - uint32_t rc_ecmd = 0; - fapi::ReturnCode rc; - - // mark function entry - FAPI_DBG("Start"); - - do - { - // determine ring length - fapi::ATTR_PROC_PB_BNDY_DMIPLL_LENGTH_Type ring_length; - rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_LENGTH, &i_target, ring_length); - if (!rc.ok()) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_PB_BNDY_DMIPLL_LENGTH."); - break; - } - rc_ecmd |= o_ring_data.setBitLength(ring_length); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // determine starting ring state - if (i_pll_ring_op == RING_OP_BASE) - { - // start from attribute data - fapi::ATTR_PROC_PB_BNDY_DMIPLL_DATA_Type ring_data_attr = {0}; - rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_DATA, &i_target, ring_data_attr); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_PB_BNDY_DMIPLL_DATA."); - break; - } - rc_ecmd |= o_ring_data.insert(ring_data_attr, 0, ring_length, 0); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - else - { - // start from data currently in ring - rc = fapiGetRing(i_target, RING_ADDRESS_PROC_PB_BNDY_DMIPLL, o_ring_data, fapi::RING_MODE_SET_PULSE); - if (!rc.ok()) - { - FAPI_ERR("Error from fapiGetRing (ring ID: 0x08%x)", RING_ADDRESS_PROC_PB_BNDY_DMIPLL); - break; - } - } - - // modify ring data - if (i_pll_ring_op == RING_OP_MOD_VCO_S1) - { - rc_ecmd |= o_ring_data.setBit(PB_BNDY_DMIPLL_RING_CCALLOAD_OFFSET); - rc_ecmd |= o_ring_data.setBit(PB_BNDY_DMIPLL_RING_CCALFMIN_OFFSET); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to enable lctank PLL vco workaround (scan1)", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - else if (i_pll_ring_op == RING_OP_MOD_VCO_S2) - { - rc_ecmd |= o_ring_data.setBit(PB_BNDY_DMIPLL_RING_CCALLOAD_OFFSET); - rc_ecmd |= o_ring_data.clearBit(PB_BNDY_DMIPLL_RING_CCALFMIN_OFFSET); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to enable lctank PLL vco workaround (scan2)", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - else if (i_pll_ring_op == RING_OP_MOD_REFCLK_SEL) - { - fapi::ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET_Type refclksel_offset = {0}; - rc = FAPI_ATTR_GET(ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET, &i_target, refclksel_offset); - if (!rc.ok()) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET"); - break; - } - - if (o_ring_data.isBitSet(refclksel_offset[i_pll_bus_id])) - { - rc_ecmd |= o_ring_data.clearBit(refclksel_offset[i_pll_bus_id]); - } - else - { - rc_ecmd |= o_ring_data.setBit(refclksel_offset[i_pll_bus_id]); - } - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading refclock select attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - else if (i_pll_ring_op == RING_OP_MOD_PFD360) - { - fapi::ATTR_PROC_DMI_CUPLL_PFD360_OFFSET_Type pfd360_offset; - rc = FAPI_ATTR_GET(ATTR_PROC_DMI_CUPLL_PFD360_OFFSET, &i_target, pfd360_offset); - if (!rc.ok()) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_DMI_CUPLL_PFD360_OFFSET"); - break; - } - - if (o_ring_data.isBitSet(pfd360_offset[i_pll_bus_id])) - { - rc_ecmd |= o_ring_data.clearBit(pfd360_offset[i_pll_bus_id]); - } - else - { - rc_ecmd |= o_ring_data.setBit(pfd360_offset[i_pll_bus_id]); - } - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading pfd360 attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - } while(0); - - // mark function exit - FAPI_DBG("End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: -// Calculate state to apply to processor ab_bndy_pll ring -// -// parameters: i_target => chip target -// i_pll_ring_op => modification to be made to base PLL content -// i_pll_bus_id => bus instance to target for modification -// o_ring_data => data buffer containing ring state to apply -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode p8_pll_utils_calc_proc_ab_bndy_pll( - const fapi::Target & i_target, - const p8_pll_utils_ring_op i_pll_ring_op, - const p8_pll_utils_bus_id i_pll_bus_id, - ecmdDataBufferBase & o_ring_data) -{ - // return codes - uint32_t rc_ecmd = 0; - fapi::ReturnCode rc; - - // mark function entry - FAPI_DBG("Start"); - - do - { - // determine ring length - fapi::ATTR_PROC_AB_BNDY_PLL_LENGTH_Type ring_length; - rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_LENGTH, &i_target, ring_length); - if (!rc.ok()) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_AB_BNDY_PLL_LENGTH."); - break; - } - rc_ecmd |= o_ring_data.setBitLength(ring_length); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // determine starting ring state - if (i_pll_ring_op == RING_OP_BASE) - { - // start from attribute data - fapi::ATTR_PROC_AB_BNDY_PLL_DATA_Type ring_data_attr = {0}; - rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_DATA, &i_target, ring_data_attr); - if (rc) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_AB_BNDY_PLL_DATA."); - break; - } - rc_ecmd |= o_ring_data.insert(ring_data_attr, 0, ring_length, 0); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - else - { - // start from data currently in ring - rc = fapiGetRing(i_target, RING_ADDRESS_PROC_AB_BNDY_PLL, o_ring_data, fapi::RING_MODE_SET_PULSE); - if (!rc.ok()) - { - FAPI_ERR("Error from fapiGetRing (ring ID: 0x08%x)", RING_ADDRESS_PROC_AB_BNDY_PLL); - break; - } - } - - // modify ring data - if (i_pll_ring_op == RING_OP_MOD_VCO_S1) - { - rc_ecmd |= o_ring_data.setBit(AB_BNDY_PLL_RING_CCALLOAD_OFFSET); - rc_ecmd |= o_ring_data.setBit(AB_BNDY_PLL_RING_CCALFMIN_OFFSET); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to enable lctank PLL vco workaround (scan1)", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - else if (i_pll_ring_op == RING_OP_MOD_VCO_S2) - { - rc_ecmd |= o_ring_data.setBit(AB_BNDY_PLL_RING_CCALLOAD_OFFSET); - rc_ecmd |= o_ring_data.clearBit(AB_BNDY_PLL_RING_CCALFMIN_OFFSET); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to enable lctank PLL vco workaround (scan2)", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - else if (i_pll_ring_op == RING_OP_MOD_REFCLK_SEL) - { - fapi::ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET_Type refclksel_offset = {0}; - rc = FAPI_ATTR_GET(ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET, &i_target, refclksel_offset); - if (!rc.ok()) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET"); - break; - } - - if (o_ring_data.isBitSet(refclksel_offset[i_pll_bus_id])) - { - rc_ecmd |= o_ring_data.clearBit(refclksel_offset[i_pll_bus_id]); - } - else - { - rc_ecmd |= o_ring_data.setBit(refclksel_offset[i_pll_bus_id]); - } - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading refclock select attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - else if (i_pll_ring_op == RING_OP_MOD_PFD360) - { - fapi::ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET_Type pfd360_offset; - rc = FAPI_ATTR_GET(ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET, &i_target, pfd360_offset); - if (!rc.ok()) - { - FAPI_ERR("Failed to get attribute: ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET"); - break; - } - - if (o_ring_data.isBitSet(pfd360_offset[i_pll_bus_id])) - { - rc_ecmd |= o_ring_data.clearBit(pfd360_offset[i_pll_bus_id]); - } - else - { - rc_ecmd |= o_ring_data.setBit(pfd360_offset[i_pll_bus_id]); - } - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x loading pfd360 attribute data into buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - } while(0); - - // mark function exit - FAPI_DBG("End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: -// Poll for SBE to reach designated state (interlocked with scan requests) -// -// parameters: i_target => chip target -// i_poll_limit => number of polls permitted before timeout -// -// returns: FAPI_RC_SUCCESS if desired state was reached, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode p8_pll_utils_poll_sbe( - const fapi::Target & i_target, - const uint32_t i_num_polls) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - - uint32_t poll_num = 0; - bool poll_timeout = false; - bool sbe_running = true; - bool sbe_ready = false; - - ecmdDataBufferBase sbe_control_data(64); - ecmdDataBufferBase sbe_vital_data(64); - uint32_t istep_num; - uint8_t substep_num; - ecmdDataBufferBase mbox_data(64); - - // mark function entry - FAPI_DBG("Start"); - - do - { - do - { - // delay between poll attempts - if (poll_num) - { - FAPI_DBG("Pausing prior to next poll..."); - rc = fapiDelay(PROC_A_X_PCI_DMI_PLL_UTILS_SBE_POLL_DELAY_HW, - PROC_A_X_PCI_DMI_PLL_UTILS_SBE_POLL_DELAY_SIM); - if (!rc.ok()) - { - FAPI_ERR("Error from fapiDelay"); - break; - } - } - - // increment poll count, timeout if threshold exceeded - poll_num++; - if (poll_num > i_num_polls) - { - poll_timeout = true; - break; - } - - // determine SBE run state - FAPI_DBG("Reading SBE state (poll %d / %d)", poll_num, i_num_polls); - rc = fapiGetScom(i_target, PORE_SBE_CONTROL_0x000E0001, sbe_control_data); - if (!rc.ok()) - { - FAPI_ERR("Error reading SBE Control Register"); - break; - } - sbe_running = sbe_control_data.isBitClear(SBE_CONTROL_REG_CTL_NO_LB_BIT); - FAPI_DBG("Run state: %s", ((sbe_running)?("run"):("halted"))); - - // get SBE istep/substep information - rc = fapiGetScom(i_target, MBOX_SBEVITAL_0x0005001C, sbe_vital_data); - if (!rc.ok()) - { - FAPI_ERR("Error reading SBE Vital Register"); - break; - } - - rc_ecmd |= sbe_vital_data.extractToRight(&istep_num, - ISTEP_NUM_BIT_POSITION, - ISTEP_NUM_BIT_LENGTH); - rc_ecmd |= sbe_vital_data.extractToRight(&substep_num, - SUBSTEP_NUM_BIT_POSITION, - SUBSTEP_NUM_BIT_LENGTH); - if (rc_ecmd) - { - FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // get HB->SBE request mailbox, check that it is clear - rc = fapiGetScom(i_target, MBOX_SCRATCH_REG0_0x00050038, mbox_data); - if (!rc.ok()) - { - FAPI_ERR("Scom error reading SBE MBOX0 Register"); - break; - } - - sbe_ready = (istep_num == PROC_SBE_SCAN_SERVICE_ISTEP_NUM) && - (substep_num == SUBSTEP_SBE_READY) && - (mbox_data.getDoubleWord(0) == 0); - - FAPI_DBG("Istep: 0x%03X, Substep: %X, MBOX: %016llX", istep_num, substep_num, mbox_data.getDoubleWord(0)); - - } while (!poll_timeout && - sbe_running && - !sbe_ready); - - if (!rc.ok()) - { - break; - } - if (!sbe_running) - { - FAPI_ERR("SBE is NOT running!"); - const fapi::Target & TARGET = i_target; - ecmdDataBufferBase & SBE_CONTROL = sbe_control_data; - FAPI_SET_HWP_ERROR(rc, RC_P8_PLL_UTILS_SBE_STOPPED); - break; - } - if (poll_timeout || !sbe_ready) - { - FAPI_ERR("Poll limit reached waiting for SBE to attain expected state"); - FAPI_ERR("Expected istep 0x%03llX, substep 0x%X but found istep 0x%03X, substep 0x%X", - PROC_SBE_SCAN_SERVICE_ISTEP_NUM, SUBSTEP_SBE_READY, - istep_num, substep_num); - const fapi::Target & TARGET = i_target; - const uint32_t & POLL_COUNT = i_num_polls; - const ecmdDataBufferBase & SBE_VITAL = sbe_vital_data; - FAPI_SET_HWP_ERROR(rc, RC_P8_PLL_UTILS_SBE_TIMEOUT_ERROR); - break; - } - - FAPI_DBG("SBE reached expected state"); - - } while(0); - - // mark function entry - FAPI_DBG("End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: -// Scan PLL boundary ring with setpulse (scan executed by SBE) -// -// parameters: i_target => chip target -// i_pll_ring_addr => PLL ring address -// i_pll_ring_op => modification to be made to base PLL content -// i_pll_bus_id => bus instance to target for modification -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode p8_pll_utils_scan_bndy_sbe( - const fapi::Target & i_target, - const p8_pll_utils_ring_address i_pll_ring_addr, - const p8_pll_utils_ring_op i_pll_ring_op, - const p8_pll_utils_bus_id i_pll_bus_id) -{ - // return codes - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - - // mark function entry - FAPI_DBG("Start"); - - do - { - // check request content - p8_pll_utils_ring_id pll_ring_id; - if (i_pll_ring_addr == RING_ADDRESS_PROC_AB_BNDY_PLL) - { - pll_ring_id = RING_ID_ABUS; - } - else if (i_pll_ring_addr == RING_ADDRESS_PROC_PCI_BNDY_PLL) - { - pll_ring_id = RING_ID_PCI; - } - else if (i_pll_ring_addr == RING_ADDRESS_PROC_PB_BNDY_DMIPLL) - { - pll_ring_id = RING_ID_DMI; - } - else - { - FAPI_ERR("Invalid/unsupported SBE ring operation requested"); - const fapi::Target & TARGET = i_target; - const p8_pll_utils_ring_address & PLL_RING_ADDR = i_pll_ring_addr; - const p8_pll_utils_ring_op & PLL_RING_OP = i_pll_ring_op; - const p8_pll_utils_bus_id & PLL_BUS_ID = i_pll_bus_id; - const bool & INVALID_RING_ADDRESS = true; - const bool & INVALID_RING_OP = false; - const bool & INVALID_BUS_ID = false; - FAPI_SET_HWP_ERROR(rc, RC_P8_PLL_UTILS_INVALID_OPERATION); - break; - } - - // verify that SBE is ready to service scan operation - // (it should be waiting for our request) - FAPI_DBG("Checking SBE is ready to receive scan request"); - rc = p8_pll_utils_poll_sbe(i_target, 1); - if (!rc.ok()) - { - FAPI_ERR("Error from p8_pll_utils_poll_sbe"); - break; - } - - // construct scan request format - ecmdDataBufferBase mbox_data(64); - rc_ecmd |= mbox_data.setBit(MBOX0_REQUEST_VALID_BIT); - rc_ecmd |= mbox_data.insertFromRight(static_cast<uint32_t>(pll_ring_id), - MBOX0_RING_SELECT_START_BIT, - (MBOX0_RING_SELECT_END_BIT- - MBOX0_RING_SELECT_START_BIT+1)); - rc_ecmd |= mbox_data.insertFromRight(static_cast<uint32_t>(i_pll_ring_op), - MBOX0_RING_OP_START_BIT, - (MBOX0_RING_OP_END_BIT- - MBOX0_RING_OP_START_BIT+1)); - rc_ecmd |= mbox_data.insertFromRight(static_cast<uint32_t>(i_pll_bus_id), - MBOX0_RING_BUS_ID_START_BIT, - (MBOX0_RING_BUS_ID_END_BIT- - MBOX0_RING_BUS_ID_START_BIT+1)); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up SBE MBOX0 data buffer.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // submit request to SBE - FAPI_DBG("Submitting scan request to SBE"); - rc = fapiPutScom(i_target, MBOX_SCRATCH_REG0_0x00050038, mbox_data); - if (!rc.ok()) - { - FAPI_ERR("Error writing SBE MBOX0 Register"); - break; - } - - // poll until SBE drops response SBE indicates scan is finished (back to 'ready' state) - // or until maximum poll count is reached - FAPI_DBG("Polling for SBE completion..."); - rc = p8_pll_utils_poll_sbe(i_target, - PROC_A_X_PCI_DMI_PLL_UTILS_SBE_MAX_POLLS); - if (!rc.ok()) - { - FAPI_ERR("Error from p8_pll_utils_poll_sbe"); - break; - } - - // check result of scan operation - FAPI_DBG("SBE reached ready state, checking result of scan operation"); - rc = fapiGetScom(i_target, MBOX_SCRATCH_REG1_0x00050039, mbox_data); - if (!rc.ok()) - { - FAPI_ERR("Error reading SBE MBOX1 Register"); - break; - } - - if (mbox_data.isBitClear(MBOX1_SCAN_REPLY_SUCCESS_BIT)) - { - FAPI_ERR("SBE indicated scan operation failure!"); - const fapi::Target & TARGET = i_target; - const p8_pll_utils_ring_address & PLL_RING_ADDR = i_pll_ring_addr; - const p8_pll_utils_ring_op & PLL_RING_OP = i_pll_ring_op; - const p8_pll_utils_bus_id & PLL_BUS_ID = i_pll_bus_id; - const ecmdDataBufferBase & MBOX1_DATA = mbox_data; - FAPI_SET_HWP_ERROR(rc, RC_P8_PLL_UTILS_SBE_SCAN_ERROR); - break; - } - - FAPI_DBG("SBE reply indicates scan was successful!"); - - } while(0); - - // mark function exit - FAPI_DBG("End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: -// Scan PLL boundary ring with setpulse (scan executed by HB/FSP platform) -// -// parameters: i_target => chip target -// i_pll_ring_addr => PLL ring address -// i_pll_ring_op => modification to be made to base PLL content -// i_pll_bus_id => bus instance to target for modification -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode p8_pll_utils_scan_bndy_non_sbe( - const fapi::Target & i_target, - const p8_pll_utils_ring_address i_pll_ring_addr, - const p8_pll_utils_ring_op i_pll_ring_op, - const p8_pll_utils_bus_id i_pll_bus_id) -{ - // return codes - uint32_t rc_ecmd = 0; - fapi::ReturnCode rc; - - // mark function entry - FAPI_DBG("Start"); - - do - { - // form base chiplet ID / ring data to scan - uint32_t chiplet_base_scom_addr; - ecmdDataBufferBase ring_data; - if (i_pll_ring_addr == RING_ADDRESS_MEMB_TP_BNDY_PLL) - { - chiplet_base_scom_addr = TP_CHIPLET_0x01000000; - rc = p8_pll_utils_calc_memb_tp_bndy_pll(i_target, - i_pll_ring_op, - ring_data); - if (!rc.ok()) - { - FAPI_ERR("Error from p8_pll_utils_calc_memb_tp_bndy_pll"); - break; - } - } - else if (i_pll_ring_addr == RING_ADDRESS_PROC_PB_BNDY_DMIPLL) - { - chiplet_base_scom_addr = NEST_CHIPLET_0x02000000; - rc = p8_pll_utils_calc_proc_pb_bndy_dmipll(i_target, - i_pll_ring_op, - i_pll_bus_id, - ring_data); - if (!rc.ok()) - { - FAPI_ERR("Error from p8_pll_utils_calc_proc_pb_bndy_dmipll"); - break; - } - } - else if (i_pll_ring_addr == RING_ADDRESS_PROC_AB_BNDY_PLL) - { - chiplet_base_scom_addr = A_BUS_CHIPLET_0x08000000; - rc = p8_pll_utils_calc_proc_ab_bndy_pll(i_target, - i_pll_ring_op, - i_pll_bus_id, - ring_data); - if (!rc.ok()) - { - FAPI_ERR("Error from p8_pll_utils_calc_proc_ab_bndy_pll"); - break; - } - } - else - { - chiplet_base_scom_addr = PCIE_CHIPLET_0x09000000; - rc = p8_pll_utils_calc_proc_pci_bndy_pll(i_target, - ring_data); - if (!rc.ok()) - { - FAPI_ERR("Error from p8_pll_utils_calc_proc_pci_bndy_pll"); - break; - } - } - - // configure OPCG to generate setpulse - ecmdDataBufferBase scom_data(64); - FAPI_DBG("Writing OPCG Register 0 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG0_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write OPCG Register 0.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_OPCG_CNTL0_0x00030002, scom_data); - if (!rc.ok()) - { - FAPI_ERR("Error writing OPCG Register0 to generate setpulse."); - break; - } - - FAPI_DBG("Writing OPCG Register 2 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG2_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write OPCG Register 2.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_OPCG_CNTL2_0x00030004, scom_data); - if (rc) - { - FAPI_ERR("Error writing OPCG Register2 to generate setpulse."); - break; - } - - FAPI_DBG("Writing OPCG Register 3 to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG3_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write OPCG Register 3.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_OPCG_CNTL3_0x00030005, scom_data); - if (rc) - { - FAPI_ERR("Error writing OPCG Register3 to generate setpulse."); - break; - } - - FAPI_DBG("Writing OPCG Clock Region Register to generate setpulse ..."); - rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_FOR_SETPULSE); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to write Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_CLK_REGION_0x00030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing Clock Region Register to generate setpulse."); - break; - } - - // scan new ring data into PLL boundary scan ring - rc = fapiPutRing(i_target, i_pll_ring_addr, ring_data, fapi::RING_MODE_SET_PULSE); - if (rc) - { - FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t) rc); - break; - } - FAPI_DBG("Loading of the config bits for PLL is done."); - - - // set the OPCG back to a good state - FAPI_DBG("Writing OPCG Register 3 to clear setpulse ..."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear OPCG Register 3.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_OPCG_CNTL3_0x00030005, scom_data); - if (rc) - { - FAPI_ERR("Error writing OPCG Register3 to clear setpulse."); - break; - } - - FAPI_DBG("Writing OPCG Clock Region Register to clear setpulse ..."); - rc_ecmd |= scom_data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear Clock Region Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_CLK_REGION_0x00030006, scom_data); - if (rc) - { - FAPI_ERR("Error writing Clock Region Register to clear setpulse."); - break; - } - - } while(0); - - // mark function exit - FAPI_DBG("End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: -// Scan PLL boundary ring with setpulse -// -// parameters: i_target => chip target -// i_pll_ring_addr => PLL ring address -// i_pll_ring_op => modification to be made to base PLL content -// i_pll_bus_id => bus instance to target for modification -// i_mask_scan_collision => mask scan collision bit in chiplet -// pervasive LFIR -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_bndy( - const fapi::Target& i_target, - const p8_pll_utils_ring_address i_pll_ring_addr, - const p8_pll_utils_ring_op i_pll_ring_op, - const p8_pll_utils_bus_id i_pll_bus_id, - const bool i_mask_scan_collision) -{ - // return codes - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - - // mark function entry - FAPI_DBG("Start"); - - do - { - // check validity of arguments - bool invalid_ring_address = ((i_pll_ring_addr != RING_ADDRESS_MEMB_TP_BNDY_PLL) && - (i_pll_ring_addr != RING_ADDRESS_PROC_PB_BNDY_DMIPLL) && - (i_pll_ring_addr != RING_ADDRESS_PROC_AB_BNDY_PLL) && - (i_pll_ring_addr != RING_ADDRESS_PROC_PCI_BNDY_PLL)); - bool invalid_ring_op = (((i_pll_ring_op != RING_OP_BASE) && - (i_pll_ring_op != RING_OP_MOD_VCO_S1) && - (i_pll_ring_op != RING_OP_MOD_VCO_S2) && - (i_pll_ring_op != RING_OP_MOD_REFCLK_SEL) && - (i_pll_ring_op != RING_OP_MOD_PFD360)) || - ((i_pll_ring_addr == RING_ADDRESS_MEMB_TP_BNDY_PLL) && - ((i_pll_ring_op == RING_OP_MOD_VCO_S1) || - (i_pll_ring_op == RING_OP_MOD_VCO_S2))) || - ((i_pll_ring_addr == RING_ADDRESS_PROC_PCI_BNDY_PLL) && - (i_pll_ring_op != RING_OP_BASE))); - bool invalid_bus_id = ((((i_pll_ring_addr == RING_ADDRESS_MEMB_TP_BNDY_PLL) || - (i_pll_ring_addr == RING_ADDRESS_PROC_PCI_BNDY_PLL)) && - (i_pll_bus_id != RING_BUS_ID_0)) || - (((i_pll_ring_op == RING_OP_BASE) || - (i_pll_ring_op == RING_OP_MOD_VCO_S1) || - (i_pll_ring_op == RING_OP_MOD_VCO_S2)) && - (i_pll_bus_id != RING_BUS_ID_0)) || - ((i_pll_ring_addr == RING_ADDRESS_PROC_AB_BNDY_PLL) && - (i_pll_bus_id != RING_BUS_ID_0) && - (i_pll_bus_id != RING_BUS_ID_1) && - (i_pll_bus_id != RING_BUS_ID_2) && - (i_pll_bus_id != RING_BUS_ID_3)) || - ((i_pll_ring_addr == RING_ADDRESS_PROC_PB_BNDY_DMIPLL) && - (i_pll_bus_id != RING_BUS_ID_0) && - (i_pll_bus_id != RING_BUS_ID_1) && - (i_pll_bus_id != RING_BUS_ID_2) && - (i_pll_bus_id != RING_BUS_ID_3) && - (i_pll_bus_id != RING_BUS_ID_4) && - (i_pll_bus_id != RING_BUS_ID_5) && - (i_pll_bus_id != RING_BUS_ID_6) && - (i_pll_bus_id != RING_BUS_ID_7))); - - if (invalid_ring_address || - invalid_ring_op || - invalid_bus_id) - { - FAPI_ERR("Invalid/unsupported ring operation requested"); - FAPI_ERR(" ring address: %x (invalid = %d)", i_pll_ring_addr, invalid_ring_address); - FAPI_ERR(" ring op: %x (invalid = %d)", i_pll_ring_op, invalid_ring_op); - FAPI_ERR(" bus id: %x (invalid = %d)", i_pll_bus_id, invalid_bus_id); - - const fapi::Target & TARGET = i_target; - const p8_pll_utils_ring_address & PLL_RING_ADDR = i_pll_ring_addr; - const p8_pll_utils_ring_op & PLL_RING_OP = i_pll_ring_op; - const p8_pll_utils_bus_id & PLL_BUS_ID = i_pll_bus_id; - const bool & INVALID_RING_ADDRESS = invalid_ring_address; - const bool & INVALID_RING_OP = invalid_ring_op; - const bool & INVALID_BUS_ID = invalid_bus_id; - FAPI_SET_HWP_ERROR(rc, RC_P8_PLL_UTILS_INVALID_OPERATION); - break; - } - - // optionally mask pervasive LFIR prior to scan operation - bool unmask_scan_collision = false; - uint32_t chiplet_base_scom_addr; - ecmdDataBufferBase scom_data(64); - if (i_pll_ring_addr == RING_ADDRESS_MEMB_TP_BNDY_PLL) - { - chiplet_base_scom_addr = TP_CHIPLET_0x01000000; - } - else if (i_pll_ring_addr == RING_ADDRESS_PROC_PB_BNDY_DMIPLL) - { - chiplet_base_scom_addr = NEST_CHIPLET_0x02000000; - } - else if (i_pll_ring_addr == RING_ADDRESS_PROC_AB_BNDY_PLL) - { - chiplet_base_scom_addr = A_BUS_CHIPLET_0x08000000; - } - else - { - chiplet_base_scom_addr = PCIE_CHIPLET_0x09000000; - } - - if (i_mask_scan_collision) - { - FAPI_DBG("Reading value of Pervasive LFIR scan collision mask bit ..."); - rc = fapiGetScom(i_target, chiplet_base_scom_addr | GENERIC_PERV_LFIR_MASK_0x0004000D, scom_data); - if (!rc.ok()) - { - FAPI_ERR("Error reading Pervasive LFIR Mask OR Register."); - break; - } - unmask_scan_collision = scom_data.isBitClear(PERV_LFIR_SCAN_COLLISION_BIT); - - FAPI_DBG("Masking Pervasive LFIR scan collision bit ..."); - rc_ecmd |= scom_data.flushTo0(); - rc_ecmd |= scom_data.setBit(PERV_LFIR_SCAN_COLLISION_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to set Pervasive LFIR Mask Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_PERV_LFIR_MASK_OR_0x0004000F, scom_data); - if (!rc.ok()) - { - FAPI_ERR("Error writing Pervasive LFIR Mask OR Register."); - break; - } - } - - // make determination of scan path to use - bool use_sbe; - FAPI_EXEC_HWP(rc, proc_use_sbe_scan_service, i_target, use_sbe); - if (!rc.ok()) - { - FAPI_ERR("Error from proc_use_sbe_scan_service"); - break; - } - - // scan path determined - // request SCAN via SBE (SBE holds data) - if (use_sbe) - { - rc = p8_pll_utils_scan_bndy_sbe(i_target, - i_pll_ring_addr, - i_pll_ring_op, - i_pll_bus_id); - if (!rc.ok()) - { - FAPI_ERR("Error from p8_pll_utils_scan_bndy_sbe"); - break; - } - } - // construct ring content to scan via attributes, invoke FAPI API - else - { - rc = p8_pll_utils_scan_bndy_non_sbe(i_target, - i_pll_ring_addr, - i_pll_ring_op, - i_pll_bus_id); - if (!rc.ok()) - { - FAPI_ERR("Error from p8_pll_utils_scan_bndy_non_sbe"); - break; - } - } - - // clear & Unmask Pervasive LFIR - if (i_mask_scan_collision) - { - FAPI_DBG("Clearing Pervasive LFIR scan collision bit ..."); - rc_ecmd |= scom_data.flushTo1(); - rc_ecmd |= scom_data.clearBit(PERV_LFIR_SCAN_COLLISION_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear Pervasive LFIR Register.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_PERV_LFIR_AND_0x0004000B, scom_data); - if (!rc.ok()) - { - FAPI_ERR("Error writing Pervasive LFIR AND Register."); - break; - } - - if (unmask_scan_collision) - { - FAPI_DBG("Unmasking Pervasive LFIR scan collision bit ..."); - rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_PERV_LFIR_MASK_AND_0x0004000E, scom_data); - if (!rc.ok()) - { - FAPI_ERR("Error writing Pervasive LFIR Mask And Register."); - break; - } - } - } - - } while(0); - - // mark function exit - FAPI_DBG("End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: -// Release PLL from test mode/bypass/reset and optionally check for lock -// -// parameters: i_target => chip target -// i_chiplet_base_scom_addr => aligned base address of chiplet SCOM -// address space -// i_check_lock => check for PLL lock? -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_a_x_pci_dmi_pll_release_pll( - const fapi::Target& i_target, - const uint32_t i_chiplet_base_scom_addr, - const bool i_check_lock) -{ - // data buffer to hold SCOM data - ecmdDataBufferBase data(64); - - // return codes - uint32_t rc_ecmd = 0; - fapi::ReturnCode rc; - - // mark function entry - FAPI_DBG("Start"); - - do - { - FAPI_DBG("Release PLL test enable"); - rc_ecmd |= data.flushTo1(); - rc_ecmd |= data.clearBit(GP3_PLL_TEST_ENABLE_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to clear GP3 PLL test enable", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_GP3_AND_0x000F0013, data); - if (rc) - { - FAPI_ERR("Error writing GP3 to clear PLL test enable"); - break; - } - - FAPI_DBG("Release PLL reset"); - rc_ecmd |= data.flushTo1(); - rc_ecmd |= data.clearBit(GP3_PLL_RESET_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to clear GP3 PLL reset", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_GP3_AND_0x000F0013, data); - if (rc) - { - FAPI_ERR("Error writing GP3 to clear PLL reset"); - break; - } - - FAPI_DBG("Release PLL bypass"); - // 24july2012 mfred moved this before checking PLL lock as this is required for analog PLLs. - rc_ecmd |= data.flushTo1(); - rc_ecmd |= data.clearBit(GP3_PLL_BYPASS_BIT); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up data buffer to clear GP3 PLL bypass", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_GP3_AND_0x000F0013, data); - if (rc) - { - FAPI_ERR("Error writing GP3 to clear PLL bypass"); - break; - } - - if (i_check_lock) - { - FAPI_DBG("Checking for PLL lock..."); - uint32_t num = 0; - bool timeout = false; - - // poll until PLL is locked or max count is reached - do - { - num++; - if (num > PROC_A_X_PCI_DMI_PLL_UTILS_MAX_LOCK_POLLS) - { - timeout = 1; - break; - } - rc = fapiGetScom(i_target, i_chiplet_base_scom_addr | GENERIC_PLLLOCKREG_0x000F0019, data); - if (rc) - { - FAPI_ERR("Error reading PLL lock register"); - break; - } - rc = fapiDelay(PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_HW, - PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_SIM); - if (rc) - { - FAPI_ERR("Error from fapiDelay"); - break; - } - } while (!timeout && - !data.isBitSet(PLL_LOCK_REG_LOCK_START_BIT, - (PLL_LOCK_REG_LOCK_END_BIT- - PLL_LOCK_REG_LOCK_START_BIT+1))); - - if (rc) - { - break; - } - if (timeout) - { - FAPI_ERR("Timed out polling for PLL lock"); - const uint8_t LOCK_STATUS = data.getByte(0); - const fapi::Target & CHIP_IN_ERROR = i_target; - if (i_chiplet_base_scom_addr == NEST_CHIPLET_0x02000000) - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_DMI_PLL_NO_LOCK); - } - else if (i_chiplet_base_scom_addr == A_BUS_CHIPLET_0x08000000) - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_ABUS_PLL_NO_LOCK); - } - else if (i_chiplet_base_scom_addr == PCIE_CHIPLET_0x09000000) - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_PCIE_PLL_NO_LOCK); - } - break; - } - else - { - FAPI_DBG("PLL is locked."); - } - } - } while(0); - - // mark function entry - FAPI_DBG("End"); - return rc; -} - - -} // extern "C" diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H deleted file mode 100644 index c1a16c4de..000000000 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H +++ /dev/null @@ -1,136 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_utils.H,v 1.4 2015/05/14 21:18:32 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_utils.H,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2015 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_a_x_pci_dmi_pll_utils.H -// *! DESCRIPTION : PLL configuration utility functions -// *! -// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -// *! -//------------------------------------------------------------------------------ - -#ifndef _PROC_A_X_PCI_DMI_PLL_UTILS_H_ -#define _PROC_A_X_PCI_DMI_PLL_UTILS_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <fapi.H> - - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ -enum p8_pll_utils_ring_address -{ - RING_ADDRESS_MEMB_TP_BNDY_PLL = 0x01030088, - RING_ADDRESS_PROC_AB_BNDY_PLL = 0x08030088, - RING_ADDRESS_PROC_PCI_BNDY_PLL = 0x09030088, - RING_ADDRESS_PROC_PB_BNDY_DMIPLL = 0x02030088 -}; - -enum p8_pll_utils_ring_id -{ - RING_ID_ABUS = 1, - RING_ID_PCI = 2, - RING_ID_DMI = 3 -}; - -enum p8_pll_utils_ring_op -{ - RING_OP_BASE = 0, - RING_OP_MOD_VCO_S1 = 1, - RING_OP_MOD_VCO_S2 = 2, - RING_OP_MOD_REFCLK_SEL = 3, - RING_OP_MOD_PFD360 = 4 -}; - -enum p8_pll_utils_bus_id -{ - RING_BUS_ID_0 = 0, - RING_BUS_ID_1 = 1, - RING_BUS_ID_2 = 2, - RING_BUS_ID_3 = 3, - RING_BUS_ID_4 = 4, - RING_BUS_ID_5 = 5, - RING_BUS_ID_6 = 6, - RING_BUS_ID_7 = 7 -}; - - -//------------------------------------------------------------------------------ -// Function prototypes -//------------------------------------------------------------------------------ - -extern "C" -{ - -//------------------------------------------------------------------------------ -// function: -// Scan PLL boundary ring with setpulse -// -// parameters: i_target => chip target -// i_pll_ring_addr => PLL ring address -// i_pll_ring_op => modification to be made to base PLL content -// i_pll_bus_id => bus instance to target for modification -// i_mask_scan_collision => mask scan collision bit in chiplet -// pervasive LFIR -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_bndy( - const fapi::Target& i_target, - const p8_pll_utils_ring_address i_pll_ring_addr, - const p8_pll_utils_ring_op i_pll_ring_op, - const p8_pll_utils_bus_id i_pll_bus_id, - const bool i_mask_scan_collision); - - -//------------------------------------------------------------------------------ -// function: -// Release chiplet PLL from test mode/bypass/reset and optionally check -// for lock -// -// parameters: i_target => chip target -// -// i_chiplet_base_scom_addr => aligned base address of chiplet SCOM -// address space -// i_check_lock => check for PLL lock? -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_a_x_pci_dmi_pll_release_pll( - const fapi::Target& i_target, - const uint32_t i_chiplet_base_scom_addr, - const bool i_check_lock); - - -} // extern "C" - -#endif // _PROC_A_X_PCI_DMI_PLL_UTILS_H_ diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power/proc_pcie_slot_power.C b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power/proc_pcie_slot_power.C deleted file mode 100644 index 92069c833..000000000 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power/proc_pcie_slot_power.C +++ /dev/null @@ -1,685 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_pcie_slot_power/proc_pcie_slot_power.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_slot_power.C,v 1.3 2014/07/28 21:40:12 ricmata Exp $ -//$Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_slot_power.C,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -//------------------------------------------------------------------------------ -// *! TITLE : proc_pcie_slot_power.C -// *! DESCRIPTION : Disable/Enable slot power on hot-plug controlled slots. -// *! -// *! OWNER NAME : Rick Mata Email: ricmata@us.ibm.com -// *! BACKUP NAME : Rick Mata Email: ricmata@us.ibm.com -// *! -// *! ADDITIONAL COMMENTS : -// *! -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -// Version Date Owner Description -//------------------------------------------------------------------------------ -// 1.0 7/22/14 ricmata Initial release: Brazos support only. -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "proc_pcie_slot_power.H" - - -extern "C" -{ - - //---------------------------// - // Function protoptypes // - //---------------------------// - - /** - * @brief Issues i2c write command of 1-Byte length. - * - * @param[in] i_target Reference to chip target. - * @param[in] i_i2c_sel_dev The i2c slave address to the hotplug controller. - * @param[in] i_i2c_addr The Register offset to load into the FIFO. - * @param[in] i_i2c_data The Register data to load into the FIFO. - * - * @return ReturnCode - * - * - */ - fapi::ReturnCode proc_perv_i2cms_write(const fapi::Target &i_target, const uint8_t i_i2c_sel_dev, const uint8_t i_i2c_addr, const uint8_t i_i2c_data); - - - /** - * @brief Issues i2c read command of 1-Byte length. - * - * @param[in] i_target Reference to chip target. - * @param[in] i_i2c_sel_dev The i2c slave address to the hotplug controller. - * @param[in] i_i2c_addr The Register offset to load into the FIFO. - * @param[in] 0_i2c_data The Register data to read from the FIFO. - * - * @return ReturnCode - * - * - */ - fapi::ReturnCode proc_perv_i2cms_read(const fapi::Target &i_target, const uint8_t i_i2c_sel_dev, const uint8_t i_i2c_addr, uint8_t *o_i2c_data); - - - /** - * @brief Checks P8 I2C Master Status register for command complete and errors. - * - * @param[in] i_target Reference to chip target - * - * @return ReturnCode - * - * - */ - fapi::ReturnCode check_not_ready_bits(const fapi::Target &i_target); - - - /** - * @brief Checks P8 I2C Master Status register for the FIFO to be flushed. - * - * @param[in] i_target Reference to chip target - * - * @return ReturnCode - * - * - */ - fapi::ReturnCode check_fifo_entry_bits(const fapi::Target &i_target); - - -//------------------------------------------------------------------------------ -// -// Function definitions -//------------------------------------------------------------------------------ - - - //------------------------------------------------------------------------------ - // name: proc_pcie_slot_power - //------------------------------------------------------------------------------ - // purpose: - // Enables/Disables slot power to hot-plug controlled pcie slots. - // - // parameters: - // 'i_target' is reference to chip target. - // 'i_enable_slot_power' TRUE to enable slot power, else FALSE to disable slot power. - // - // - // returns: - // FAPI_RC_SUCCESS (success) - // - // getscom/putscom fapi errors - // fapi error assigned from eCMD function failure - // - // RC_UNKNOWN_PCIE_SLOT_POWER_RC - // ekb/eclipz/chips/p8/working/procedures/xml/error_info/proc_pcie_slot_power_errors.xml - //------------------------------------------------------------------------------ - fapi::ReturnCode proc_pcie_slot_power(const fapi::Target &i_target, const bool i_enable_slot_power) { - - fapi::ReturnCode rc; //fapi return code value - ecmdDataBufferBase fsi_data(64); - //const uint8_t led9551_reg_pgood = 0x00; // Register to read pgood state on LED9551 Controller. - const int MAX_PORTS = 2; // Max number of ports for LED9551 Controller. - const uint8_t ary_led9551_reg_en[MAX_PORTS] = {0x05, 0x06}; // Port target on LED9551 register to enable and disable power. - const uint8_t led9551_data_slot_off = 0x54; //Data to disable power on LED9551 controller. - const uint8_t led9551_data_slot_on = 0x55; //Data to enable power on LED9551 controller. - const uint8_t led9551_dev_addr = 0xC4; //I2C address to target i2c device. - //uint8_t pgood_data; //Data contents to store the read for the PGOOD register access. - //uint64_t nano_sec_delay = 250000000; //(250000000 ns = 250 ms) to wait - //uint64_t sim_cyc_delay = 2500000; //2,500,000 simulation cycles to wait - - // mark function entry - FAPI_INF("proc_pcie_slot_power: Start"); - - fapi::ATTR_NAME_Type chip_type; - rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME, &i_target, chip_type); - if (rc) { - FAPI_ERR("fapiGetAttribute (Privildged) of ATTR_NAME failed"); - return rc; - } - - if (chip_type == fapi::ENUM_ATTR_NAME_VENICE) { // This is a Venice-based system, Brazos. - FAPI_INF("%s: ATTR_NAME retrieve is %x", i_target.toEcmdString(), chip_type); - - for (int counter = 0; counter < MAX_PORTS; counter++) { - //DISABLE_SLOT_POWER - if(!i_enable_slot_power) { - rc = proc_perv_i2cms_write(i_target, led9551_dev_addr, ary_led9551_reg_en[counter], led9551_data_slot_off); - if (rc) { - FAPI_ERR("Error occurred while disabling slot power on I2C addr=%X, target=%s", led9551_dev_addr, i_target.toEcmdString()); - return rc; - } - FAPI_INF("Disabled slot power on I2C addr=%X, target=%s", led9551_dev_addr, i_target.toEcmdString()); - } - - //ENABLE_SLOT_POWER - else { // (i_enable_slot_power) - rc = proc_perv_i2cms_write(i_target, led9551_dev_addr, ary_led9551_reg_en[counter], led9551_data_slot_on); - if (rc) { - FAPI_ERR("Error occurred while enabling slot power on I2C addr=%X, target=%s", led9551_dev_addr, i_target.toEcmdString()); - return rc; - } - FAPI_INF("Enabled slot power on I2C addr=%X, target=%s", led9551_dev_addr, i_target.toEcmdString()); - } - } - - -/* //Removing this section as we decussed in a broader meeting that we don't need to check for PGOOD. We will let PHYP or Sapphire do the checking. - //Wait before checking PGOOD state. - rc = fapiDelay(nano_sec_delay, sim_cyc_delay); - if (rc) { - FAPI_ERR("%s: fapiDelay error"); - return rc; - } - - //Read PGOOD State - rc = proc_perv_i2cms_read(i_target, led9551_dev_addr, led9551_reg_pgood, &pgood_data); - if (rc) { - FAPI_ERR("Error occurred while reading pgood register on I2C addr=%X, target=%s", led9551_dev_addr, i_target.toEcmdString()); - return rc; - } - FAPI_INF("PGOOD register read on I2C addr=%X, value=%x, target=%s", led9551_dev_addr, pgood_data, i_target.toEcmdString()); -*/ - } - else { - FAPI_INF("%s: This chip type is not supported. ATTR_NAME retrieve is %x", i_target.toEcmdString(), chip_type); - } - - // mark function entry - FAPI_INF("proc_pcie_slot_power: End"); - return rc; - } - - - - //------------------------------------------------------------------------------ - // name: proc_perv_i2cms_write - //------------------------------------------------------------------------------ - // purpose: - // Set up of P8 I2C Master engine for I2C write operations. - // - // parameters: - // 'i_target' is reference to chip target - // 'i_i2c_sel_dev' is reference to i2c device target - // 'i_i2c_addr' is reference to the address entered into the FIFO - // 'i_i2c_data' is reference to data for write operation - // - // returns: - // - // (Note: refer to file eclipz/chips/p8/working/procedures/xml/error_info/proc_pcie_slot_power_errors.xml) - // - // getscom/putscom fapi errors - // fapi error assigned from eCMD function failure - // - //------------------------------------------------------------------------------ - fapi::ReturnCode proc_perv_i2cms_write(const fapi::Target &i_target, const uint8_t i_i2c_sel_dev, const uint8_t i_i2c_addr, const uint8_t i_i2c_data) { - - fapi::ReturnCode rc; //fapi return code value - uint32_t rc_ecmd; //ecmd return code value - const uint32_t data_size = 64; //Size of data buffer - ecmdDataBufferBase fsi_data(data_size); - - // mark function entry - FAPI_INF("proc_perv_i2cms_write: Start"); - - //1. Check I2C Status for I2C errors or complete bit not set - FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX) for at least 1 error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - rc = check_not_ready_bits(i_target); - if(rc) { - FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - return rc; - } - - //2. Initialize I2C Mode register - rc_ecmd = fsi_data.insertFromRight(I2C_MODE_DATA, 0, 32); - if(rc_ecmd) { - FAPI_ERR("Error (%u) setting first word on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - FAPI_DBG("Load I2C Mode register target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0)); - rc = fapiPutScom(i_target, I2CMS_MODE_0x000A0026, fsi_data); - if (rc) { - FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_MODE_0x000A0026, i_target.toEcmdString()); - return rc; - } - - //3. Initialize I2C Command register - rc_ecmd = fsi_data.setWord(0, I2C_CMD_DATA_2B); - if(rc_ecmd) { - FAPI_ERR("Error (%u) setting first word on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - rc_ecmd = fsi_data.insertFromRight(i_i2c_sel_dev, 8, 8); - if(rc_ecmd) { - FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - rc_ecmd = fsi_data.clearBit(15); - if(rc_ecmd) { - FAPI_ERR("Error (%u) setting bit on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - FAPI_DBG("Load I2C Command register target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0)); - rc = fapiPutScom(i_target, I2CMS_COMMAND_0x000A0025, fsi_data); - if (rc) { - FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_COMMAND_0x000A0025, i_target.toEcmdString()); - return rc; - } - - //4. Write address offset into the I2C FIFO - rc_ecmd = fsi_data.insertFromRight(i_i2c_addr, 0, 8); - if(rc_ecmd) { - FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - FAPI_DBG("Write the I2C FIFO with the address to slave device on target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0)); - rc = fapiPutScom(i_target, I2CMS_FIFO1_READ_0x000A0024, fsi_data ); - if (rc) { - FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_FIFO1_READ_0x000A0024, i_target.toEcmdString()); - return rc; - } - - //5. Poll for the FIFO Entry count in the status to ensure all data was checked in. - - FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX) for at least 1 error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - rc = check_fifo_entry_bits(i_target); - if(rc) { - FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - return rc; - } - - //6. Write data into the I2C FIFO - rc_ecmd = fsi_data.insertFromRight(i_i2c_data, 0, 8); - if(rc_ecmd) { - FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - FAPI_DBG("Write the I2C FIFO with data to slave device on target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0)); - rc = fapiPutScom(i_target, I2CMS_FIFO1_READ_0x000A0024, fsi_data); - if (rc) { - FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_FIFO1_READ_0x000A0024, i_target.toEcmdString()); - return rc; - } - - //TODO: Step 7. is not required for 1-byte length transfers. Instead, will go straight to check for complete bit and errors. Leaving it here for possible future enhancements. - //7. Repeat 5. and 6. above until all data is transferred. - - //8. Poll for complete bit to be set and check for errors. - FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX) for at least 1 error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - rc = check_not_ready_bits(i_target); - if(rc) { - FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - return rc; - } - - // mark function entry - FAPI_INF("proc_perv_i2cms_write: End"); - return rc; - } - - - //------------------------------------------------------------------------------ - // name: proc_perv_i2cms_read - //------------------------------------------------------------------------------ - // purpose: - // Set up of P8 I2C Master engine for I2C write operations. - // - // parameters: - // 'i_target' is reference to chip target - // 'i_i2c_sel_dev' is reference to i2c device target - // 'i_i2c_addr' is reference to the address entered into the FIFO - // 'o_i2c_data' is reference to the data read from the FIFO - // - // returns: - // - // (Note: refer to file eclipz/chips/p8/working/procedures/xml/error_info/proc_pcie_slot_power_errors.xml) - // - // getscom/putscom fapi errors - // fapi error assigned from eCMD function failure - // - //------------------------------------------------------------------------------ - fapi::ReturnCode proc_perv_i2cms_read(const fapi::Target &i_target, const uint8_t i_i2c_sel_dev, const uint8_t i_i2c_addr, uint8_t *o_i2c_data) { - - fapi::ReturnCode rc; //fapi return code value - uint32_t rc_ecmd; //ecmd return code value - const uint32_t data_size = 64; //Size of data buffer - ecmdDataBufferBase fsi_data(data_size); - - // mark function entry - FAPI_INF("proc_perv_i2cms_read: Start"); - - //1. Check I2C Status for I2C errors or complete bit not set - FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX) for at least 1 error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - rc = check_not_ready_bits(i_target); - if(rc) { - FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - return rc; - } - - //2. Initialize I2C Mode register - rc_ecmd = fsi_data.insertFromRight(I2C_MODE_DATA, 0, 32); - if(rc_ecmd) { - FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - FAPI_DBG("Load I2C Mode register target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0)); - rc = fapiPutScom(i_target, I2CMS_MODE_0x000A0026, fsi_data); - if (rc) { - FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_MODE_0x000A0026, i_target.toEcmdString()); - return rc; - } - - //3. Initialize I2C Command register - rc_ecmd = fsi_data.setWord(0, I2C_CMD_DATA_1B); - if(rc_ecmd) { - FAPI_ERR("Error (%u) setting first word on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - rc_ecmd = fsi_data.insertFromRight(i_i2c_sel_dev, 8, 8); - if(rc_ecmd) { - FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - rc_ecmd = fsi_data.clearBit(15); - if(rc_ecmd) { - FAPI_ERR("Error (%u) clearing bit on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - FAPI_DBG("Load I2C Command register target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0)); - rc = fapiPutScom(i_target, I2CMS_COMMAND_0x000A0025, fsi_data); - if (rc) { - FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_COMMAND_0x000A0025, i_target.toEcmdString()); - return rc; - } - - //4. Write address offset into the I2C FIFO - rc_ecmd = fsi_data.insertFromRight(i_i2c_addr, 0, 8); - if(rc_ecmd) { - FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - FAPI_DBG("Write the I2C FIFO with the address to slave device on target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0)); - rc = fapiPutScom(i_target, I2CMS_FIFO1_READ_0x000A0024, fsi_data ); - if (rc) { - FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_FIFO1_READ_0x000A0024, i_target.toEcmdString()); - return rc; - } - - //5. Poll for complete bit to be set and check for errors. - FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX) for at least 1 error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - rc = check_not_ready_bits(i_target); - if(rc) { - FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - return rc; - } - - //6. Initialize I2C Command register - rc_ecmd = fsi_data.setWord(0, I2C_CMD_DATA_1B); - if(rc_ecmd) { - FAPI_ERR("Error (%u) setting first word on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - rc_ecmd = fsi_data.insertFromRight(i_i2c_sel_dev, 8, 8); - if(rc_ecmd) { - FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - rc_ecmd = fsi_data.setBit(15); - if(rc_ecmd) { - FAPI_ERR("Error (%u) setting bit on %s", rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - return rc; - } - FAPI_DBG("Load I2C Command register target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0)); - rc = fapiPutScom(i_target, I2CMS_COMMAND_0x000A0025, fsi_data); - if (rc) { - FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_COMMAND_0x000A0025, i_target.toEcmdString()); - return rc; - } - - //7. Read data from the I2C FIFO - FAPI_DBG("Read I2C data from the FIFO"); - rc = fapiGetScom(i_target, I2CMS_FIFO1_READ_0x000A0024, fsi_data ); - if (rc) { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX), target=%s", I2CMS_FIFO1_READ_0x000A0024, i_target.toEcmdString()); - return rc; - } - FAPI_DBG("Read data from the I2C FIFO to slave device on target=%s, value=0x%X", i_target.toEcmdString(), fsi_data.getByte(0)); - *o_i2c_data = fsi_data.getByte(0); - - //8. Poll status register's FIFO_ENTRY_COUNT to know if entire FIFO has been read. - FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX)", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - rc = check_fifo_entry_bits(i_target); - if(rc) { - FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - return rc; - } - - //TODO: Step 9. is not required for 1-byte length transfers. Instead, will go straight to check for complete bit and errors. Leaving it here for possible future enhancements. - - //9. Repeat 7. and 8. above until all data is read from the FIFO. - - //10. Poll for complete bit and check for any errors. - FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX)", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - rc = check_not_ready_bits(i_target); - if(rc) { - FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - return rc; - } - - // mark function entry - FAPI_INF("proc_perv_i2cms_read: End"); - return rc; - } - - - //------------------------------------------------------------------------------ - //------------------------------------------------------------------------------ - // name: check_not_ready_bits - //------------------------------------------------------------------------------ - // purpose: - // Checks P8 I2C Status register for complete bit and errors. - // - // Bits that indicate P8 I2C Master engine is not ready for operation. - // bit 0 Invalid Command. - // bit 1 Local Bus Parity Error. - // bit 2 Back End Overrun Error. - // bit 3 Back End Access Error. - // bit 4 Arbitration Lost Error. - // bit 5 NACK Recieved Error. - // bit 6 Data Request. - // bit 8 Stop Error. - // - // parameters: - // 'i_target' is reference to chip target - // - // returns: - // - // (Note: refer to file eclipz/chips/p8/working/procedures/xml/error_info/proc_pcie_slot_power_errors.xml) - // - // getscom/putscom fapi errors - // fapi error assigned from eCMD function failure - // - //------------------------------------------------------------------------------ - fapi::ReturnCode check_not_ready_bits(const fapi::Target &i_target) { - - fapi::ReturnCode rc; - const uint32_t data_size = 64; //Size of data buffer - ecmdDataBufferBase fsi_data(data_size); - const int MAX_NUM_NOT_RDY_BITS = 8; //Maximum number of bits that indicate P8 I2C Master engine is not ready. - const uint32_t ARY_NOT_RDY_BITS[MAX_NUM_NOT_RDY_BITS] = {0, 1, 2, 3, 4, 5, 6, 8}; //Array of bits that indicate P8 I2C Master engine is not ready. - uint64_t nano_sec_delay = 1000000; //(1000000 ns = 1 ms ) to wait - uint64_t sim_cyc_delay = 10000; //10,000 simulation cycles to wait - int poll_counter; //Number of iterations while polling - const int MAX_NUM_POLLS = 100; //Maximum number of iterations (So, 1ms * 100 = 100ms before timeout) - - // mark function entry - FAPI_INF("check_not_ready_bits: Start"); - - //1. Read I2C Status register and poll for complete bit to be set then check for errors. - rc = fapiGetScom(i_target, I2CMS_STATUS_0x000A002B, fsi_data); - if (rc) { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", I2CMS_STATUS_0x000A002B); - return rc; - } - poll_counter = 0; - while (!fsi_data.isBitSet(7)) { - poll_counter++; - - //Exceed max number of polls - if(poll_counter > MAX_NUM_POLLS) { - FAPI_ERR("Exceeded max number of polls (%d) for target=%s", MAX_NUM_POLLS, i_target.toEcmdString()); - const fapi::Target & CHIP_TARGET = i_target; - const uint64_t & ADDRESS_VAL = I2CMS_STATUS_0x000A002B; - ecmdDataBufferBase & DATA_REG = fsi_data; - FAPI_SET_HWP_ERROR(rc, RC_I2C_COMPLETE_BIT_TIMEOUT_RC); - return rc; - } - FAPI_DBG("target=%s, Poll Iter: %d", i_target.toEcmdString(), poll_counter); - - //Wait before checking again - rc = fapiDelay(nano_sec_delay, sim_cyc_delay); - if (rc) { - FAPI_ERR("fapiDelay error"); - return rc; - } - - //Get data from I2C Status register - FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX) for at least 1 error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B); - rc = fapiGetScom(i_target, I2CMS_STATUS_0x000A002B, fsi_data); - if (rc) { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", I2CMS_STATUS_0x000A002B); - return rc; - } - } - - //2. Check P8 I2C Master engine is ready for new operation. - for(int counter = 0; counter < MAX_NUM_NOT_RDY_BITS; counter++) { - if( fsi_data.isBitSet(ARY_NOT_RDY_BITS[counter] )) { - FAPI_ERR("Error in bit pos %u of I2CMS_STATUS_0x000A002B, (addr: 0x%08llX) ",ARY_NOT_RDY_BITS[counter], I2CMS_STATUS_0x000A002B); - const fapi::Target & CHIP_TARGET = i_target; - const uint64_t & ADDRESS_VAL = I2CMS_STATUS_0x000A002B; - ecmdDataBufferBase & DATA_REG = fsi_data; - FAPI_SET_HWP_ERROR(rc, RC_I2C_ERROR_BIT_PRESENT_RC); - return rc; - } - } - - // mark function exit - FAPI_INF("check_not_ready_bits: End"); - return rc; - } - - - //------------------------------------------------------------------------------ - //------------------------------------------------------------------------------ - // name: check_fifo_entry_bits - //------------------------------------------------------------------------------ - // purpose: - // Checks P8 I2C Status register for FIFO entry to read 00 indicating FIFO has been flushed.. - // - // Bits that indicate P8 I2C Master engine is not ready for operation. - // bit[28:31] - FIFO Entry Count - // - // parameters: - // 'i_target' is reference to chip target - // - // returns: - // - // (Note: refer to file eclipz/chips/p8/working/procedures/xml/error_info/proc_pcie_slot_power_errors.xml) - // - // getscom/putscom fapi errors - // fapi error assigned from eCMD function failure - // - //------------------------------------------------------------------------------ - fapi::ReturnCode check_fifo_entry_bits(const fapi::Target &i_target) { - - fapi::ReturnCode rc; - const uint32_t data_size = 64; //Size of data buffer - ecmdDataBufferBase fsi_data(data_size); - uint64_t nano_sec_delay = 1000000; //(1000000 ns = 1 ms ) to wait - uint64_t sim_cyc_delay = 10000; //10,000 simulation cycles to wait - int poll_counter; //Number of iterations while polling - const int MAX_NUM_POLLS = 100; //Maximum number of iterations (So, 1ms * 100 = 100ms before timeout) - - // mark function entry - FAPI_INF("check_fifo_entry_bits: Start"); - - //Read I2C Status register and poll for FIFO entry count to reach 00. - rc = fapiGetScom(i_target, I2CMS_STATUS_0x000A002B, fsi_data); - if (rc) { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", I2CMS_STATUS_0x000A002B); - return rc; - } - poll_counter = 0; - while (!fsi_data.isBitClear(28, 4)) { - poll_counter++; - - //Exceed max number of polls - if(poll_counter > MAX_NUM_POLLS) { - FAPI_ERR("Exceeded max number of polls (%d) for target=%s", MAX_NUM_POLLS, i_target.toEcmdString()); - const fapi::Target & CHIP_TARGET = i_target; - const uint64_t & ADDRESS_VAL = I2CMS_STATUS_0x000A002B; - ecmdDataBufferBase & DATA_REG = fsi_data; - FAPI_SET_HWP_ERROR(rc, RC_I2C_FIFO_INCOMPLETE_RC); - return rc; - } - FAPI_DBG("target=%s, Poll Iter: %d", i_target.toEcmdString(), poll_counter); - - - //Wait before checking again - rc = fapiDelay(nano_sec_delay, sim_cyc_delay); - if (rc) { - FAPI_ERR("fapiDelay error"); - return rc; - } - - //Get data from I2C Status register - rc = fapiGetScom(i_target, I2CMS_STATUS_0x000A002B, fsi_data); - if (rc) { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", I2CMS_STATUS_0x000A002B); - return rc; - } - } - - // mark function exit - FAPI_INF("check_fifio_entry_bits: End"); - return rc; - } - -} // extern "C" diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power/proc_pcie_slot_power.H b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power/proc_pcie_slot_power.H deleted file mode 100644 index 6795dc883..000000000 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power/proc_pcie_slot_power.H +++ /dev/null @@ -1,90 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_pcie_slot_power/proc_pcie_slot_power.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_slot_power.H,v 1.3 2014/07/28 21:40:41 ricmata Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_slot_power.H,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -//------------------------------------------------------------------------------ -// *! TITLE : proc_pcie_slot_power.C -// *! DESCRIPTION : Disable/Enable slot power on hot-plug controlled slots. -// *! -// *! OWNER NAME : Rick Mata Email: ricmata@us.ibm.com -// */ BACKUP NAME : Rick Mata Email: ricmata@us.ibm.com -// *! -// *! ADDITIONAL COMMENTS : -// *! -//------------------------------------------------------------------------------ -//------------------------------------------------------------------------------ -// Version Date Owner Description -//------------------------------------------------------------------------------ -// 1.0 7/22/14 ricmata Initial release: Brazos support only. -//------------------------------------------------------------------------------ -#ifndef _PROC_PCIE_SLOT_POWER_H_ -#define _PROC_PCIE_SLOT_POWER_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "fapi.H" - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -const uint32_t I2C_MODE_DATA = 0x01760000; -const uint32_t I2C_CMD_DATA_2B = 0xD0000002; -const uint32_t I2C_CMD_DATA_1B = 0xD0000001; -const uint64_t I2CMS_FIFO1_READ_0x000A0024 = 0x00000000000A0024ULL; -const uint64_t I2CMS_COMMAND_0x000A0025 = 0x00000000000A0025ULL; -const uint64_t I2CMS_MODE_0x000A0026 = 0x00000000000A0026ULL; -const uint64_t I2CMS_STATUS_0x000A002B = 0x00000000000A002BULL; -const uint64_t I2CMS_EXT_STATUS_0x000A002C = 0x00000000000A002CULL; - -//------------------------------------------------------------------------------ -// Structure Definition(s) -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode -(*proc_pcie_slot_power_FP_t)(const fapi::Target &i_target, const bool); - -extern "C" -{ - /** - * @brief Disable/enable slot power to hot-plug controlled slots. - * - * @param[in] (1) 'i_target' is reference to chip target - * (2) 'i_enable_slot_power' is reference to boolean object: True = ON, False = OFF. - * - * @return ReturnCode - * - * - */ - fapi::ReturnCode proc_pcie_slot_power(const fapi::Target &i_target, const bool i_enable_slot_power); - -} //extern "C" - -#endif diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C deleted file mode 100644 index 025c3d0c9..000000000 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C +++ /dev/null @@ -1,890 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_start_clocks_chiplets.C,v 1.19 2015/05/14 21:21:34 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_start_clocks_chiplets.C,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** **** -// *| -// *! TITLE : proc_start_clocks_chiplets.H -// *! DESCRIPTION : Start X/A/PCIE chiplet clocks (FAPI) -// *! -// *! OWNER NAME : Ralph Koester Email: rkoester@de.ibm.com -// *! BACKUP NAME : Gebhard Weber Email: gweber@de.ibm.com -// *! -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "proc_start_clocks_chiplets.H" - -extern "C" -{ - - -//------------------------------------------------------------------------------ -// function: utility subroutine to clear chiplet fence in GP3 register -// parameters: i_target => chip target -// i_chiplet_base_addr => base SCOM address for chiplet -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_start_clocks_chiplet_clear_chiplet_fence( - const fapi::Target& i_target, - const uint32_t i_chiplet_base_addr) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase mask_data(64); - uint32_t scom_addr = i_chiplet_base_addr | - GENERIC_GP3_AND_0x000F0013; - - FAPI_DBG("proc_start_clocks_chiplet_clear_chiplet_fence: Start"); - - do - { - // form AND mask to clear chiplet fence bit - rc_ecmd |= mask_data.flushTo1(); - rc_ecmd |= mask_data.clearBit(GP3_FENCE_EN_BIT); - if (rc_ecmd) - { - FAPI_ERR("proc_start_clocks_chiplet_clear_chiplet_fence: Error 0x%x setting up data buffer to clear chiplet fence", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // write chiplet GP3 AND mask register to clear fence bit - rc = fapiPutScom(i_target, scom_addr, mask_data); - if (rc) - { - FAPI_ERR("proc_start_clocks_chiplet_clear_chiplet_fence: fapiPutScom error (GP3_AND_0x%08X)", - scom_addr); - break; - } - - } while(0); - - FAPI_DBG("proc_start_clocks_chiplet_clear_chiplet_fence: End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility subroutine to clear pervasive fence in GP0 register -// parameters: i_target => chip target -// i_chiplet_base_addr => base SCOM address for chiplet -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_start_clocks_chiplet_clear_perv_fence( - const fapi::Target& i_target, - const uint32_t i_chiplet_base_addr) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase mask_data(64); - uint32_t scom_addr = i_chiplet_base_addr | - GENERIC_GP0_AND_0x00000004; - - FAPI_DBG("proc_start_clocks_chiplet_clear_perv_fence: Start"); - - do - { - // form AND mask to clear pervasive fence bit - rc_ecmd |= mask_data.flushTo1(); - rc_ecmd |= mask_data.clearBit(GP0_PERV_FENCE_BIT); - if (rc_ecmd) - { - FAPI_ERR("proc_start_clocks_chiplet_clear_perv_fence: Error 0x%x setting up data buffer to clear pervasive fence", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // write chiplet GP0 AND mask register to clear pervasive fence bit - rc = fapiPutScom(i_target, scom_addr, mask_data); - if (rc) - { - FAPI_ERR("proc_start_clocks_chiplet_clear_perv_fence: fapiPutScom error (GP0_AND_0x%08X)", - scom_addr); - break; - } - - } while(0); - - FAPI_DBG("proc_start_clocks_chiplet_clear_perv_fence: End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility subroutine to set functional mode clock mux selects -// in GP0 register -// parameters: i_target => chip target -// i_chiplet_base_addr => base SCOM address for chiplet -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_start_clocks_chiplet_set_mux_selects( - const fapi::Target& i_target, - const uint32_t i_chiplet_base_addr) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase mask_data(64); - uint32_t scom_addr = i_chiplet_base_addr | - GENERIC_GP0_AND_0x00000004; - - FAPI_DBG("proc_start_clocks_chiplet_set_mux_selects: Start"); - - do - { - // form AND mask to clear mux selects - rc_ecmd |= mask_data.flushTo1(); - rc_ecmd |= mask_data.clearBit(GP0_ABSTCLK_MUXSEL_BIT); - rc_ecmd |= mask_data.clearBit(GP0_SYNCCLK_MUXSEL_BIT); - if (rc_ecmd) - { - FAPI_ERR("proc_start_clocks_chiplet_set_mux_selects: Error 0x%x setting up data buffer to clear chiplet mux selects", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // write chiplet GP0 AND mask register to clear mux selects - rc = fapiPutScom(i_target, scom_addr, mask_data); - if (rc) - { - FAPI_ERR("proc_start_clocks_chiplet_set_mux_selects: fapiPutScom error (GP0_AND_0x%08X)", - scom_addr); - break; - } - - } while(0); - - FAPI_DBG("proc_start_clocks_chiplet_set_mux_selects: End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility subroutine to get partial good vector from SEEPROM -// parameters: i_target => chip target -// i_chiplet_base_addr => base SCOM address for chiplet -// o_chiplet_reg_vec => output vector -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ - -// note: -// expected value out of SEEPROM (in case of "all good", the "Partial Good Region"-Pattern are: -// XBUS = 0xF00, ABUS = 0xE100, PCIE = 0xF700 - -fapi::ReturnCode proc_start_clocks_get_partial_good_vector( - const fapi::Target& i_target, - const uint32_t i_chiplet_base_addr, - uint64_t * o_chiplet_reg_vec - ) -{ - fapi::ReturnCode rc; - uint64_t partial_good_regions[32]; - - FAPI_DBG("proc_start_clocks_get_partial_good_vector: Start"); - - do - { - - FAPI_DBG("proc_start_clocks_get_partial_good_vector: Get attribute ATTR_CHIP_REGIONS_TO_ENABLE (partial good region data) " ); - rc = FAPI_ATTR_GET( ATTR_CHIP_REGIONS_TO_ENABLE, &i_target, partial_good_regions); - if (rc) { - FAPI_ERR("fapi_attr_get( ATTR_CHIP_REGIONS_TO_ENABLE ) failed. With rc = 0x%x", - (uint32_t) rc ); - break; - } - - - FAPI_DBG("proc_start_clocks_get_partial_good_vector: start assignment of the partial good vector per chiplet"); - - switch (i_chiplet_base_addr) - { - - case X_BUS_CHIPLET_0x04000000: - FAPI_DBG("proc_start_clocks_get_partial_good_vector: XBUS, attribute for XBUS (%016llX)", partial_good_regions[4]); - *o_chiplet_reg_vec = partial_good_regions[4]; - break; - - - case A_BUS_CHIPLET_0x08000000: - FAPI_DBG("proc_start_clocks_get_partial_good_vector: ABUS, attribute for ABUS (%016llX)", partial_good_regions[8]); - *o_chiplet_reg_vec = partial_good_regions[8]; - break; - - case PCIE_CHIPLET_0x09000000: - FAPI_DBG("proc_start_clocks_get_partial_good_vector: PCIE, attribute for PCIE (%016llX)", partial_good_regions[9]); - *o_chiplet_reg_vec = partial_good_regions[9]; - break; - - default: - - FAPI_ERR("proc_start_clocks_get_partial_good_vector: invalid chiplet base address selected when selecting par. good vector (0x%08X)", - i_chiplet_base_addr); - uint32_t CHIPLET_BASE_SCOM_ADDR = i_chiplet_base_addr; - FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_CHIPLETS_PARTIAL_GOOD_ERR); - break; - - } - - - } while(0); - - FAPI_DBG("proc_start_clocks_get_partial_good_vector: End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility subroutine to set clock region register (starts clocks) -// parameters: i_target => chip target -// i_chiplet_base_addr => base SCOM address for chiplet -// i_chiplet_reg_vec => vector from SEEPROM with partial good -// clock regions -// o_chiplet_clkreg_vec => output vector which contains -// the masked vector -> used to set the -// clock region register -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_start_clocks_chiplet_set_clk_region_reg( - const fapi::Target& i_target, - const uint32_t i_chiplet_base_addr, - const uint64_t i_chiplet_reg_vec, - uint64_t * o_chiplet_clkreg_vec - ) - - -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase data(64); - uint32_t scom_addr = i_chiplet_base_addr | - GENERIC_CLK_REGION_0x00030006; - uint64_t extracted_rec_vec; - uint64_t clk_region_start_nsl_ary_masked; - uint64_t clk_region_start_all_masked; - - FAPI_DBG("proc_start_clocks_chiplet_set_clk_region_reg: Start"); - - do - { - - - // bitwise ORing of input vector - extracted_rec_vec = PROC_START_CLOCKS_CHIPLETS_CLOCK_REGION_MANIPULATION | i_chiplet_reg_vec; - - // start NSL/array clocks - - clk_region_start_nsl_ary_masked = PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_NSL_ARY & extracted_rec_vec; - - rc_ecmd |= data.setDoubleWord(0, clk_region_start_nsl_ary_masked); - if (rc_ecmd) - { - FAPI_ERR("proc_start_clocks_chiplet_set_clk_region_reg: Error 0x%x setting up data buffer for NSL/ARY clock start", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - rc = fapiPutScom(i_target, scom_addr, data); - if (rc) - { - FAPI_ERR("proc_start_clocks_chiplet_set_clk_region_reg: fapiPutScom error (CLK_REGION_0x%08X)", - scom_addr); - break; - } - - // start all clocks - - clk_region_start_all_masked = PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_ALL & extracted_rec_vec; - - // output: value written into clk_region register, reused for status register checking - - *o_chiplet_clkreg_vec = clk_region_start_all_masked; - - rc_ecmd |= data.setDoubleWord(0, clk_region_start_all_masked); - if (rc_ecmd) - { - FAPI_ERR("proc_start_clocks_chiplet_set_clk_region_reg: Error 0x%x setting up data buffer for SL/NSL/ARY clock start", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - rc = fapiPutScom(i_target, scom_addr, data); - if (rc) - { - FAPI_ERR("proc_start_clocks_chiplet_set_clk_region_reg: fapiPutScom error (CLK_REGION_0x%08X)", - scom_addr); - break; - } - - } while(0); - - FAPI_DBG("proc_start_clocks_chiplet_set_clk_region_reg: End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility subroutine to check clock status register to ensure -// all desired clock domains have been started -// parameters: i_target => chip target -// i_chiplet_base_addr => base SCOM address for chiplet -// i_chiplet_clkreg_vec => region vector of SEEPROM for clock regions -// need to be turned on -// returns: FAPI_RC_SUCCESS if operation was successful, else -// RC_PROC_START_CLOCKS_CHIPLETS_CLK_STATUS_ERR if status register -// data does not match expected pattern -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_start_clocks_chiplet_check_clk_status_reg( - const fapi::Target& i_target, - const uint32_t i_chiplet_base_addr, - const uint64_t i_chiplet_clkreg_vec) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase vec_data(64); - ecmdDataBufferBase status_data(64); - ecmdDataBufferBase exp_data(64); - uint32_t scom_addr = i_chiplet_base_addr | - GENERIC_CLK_STATUS_0x00030008; - const uint32_t xbus = X_BUS_CHIPLET_0x04000000; - const uint32_t abus = A_BUS_CHIPLET_0x08000000; - const uint32_t pcie = PCIE_CHIPLET_0x09000000; - - FAPI_DBG("proc_start_clocks_chiplet_check_clk_status_reg: Start"); - - do - { - - // read clock status register - rc = fapiGetScom(i_target, scom_addr, status_data); - if (rc) - { - FAPI_ERR("proc_start_clocks_chiplet_check_clk_status_reg: fapiGetScom error (CLK_STATUS_0x%08X)", - scom_addr); - break; - } - - // load it with reference data - rc_ecmd |= vec_data.setDoubleWord(0, i_chiplet_clkreg_vec); - // generate expected value databuffer - rc_ecmd |= exp_data.flushTo1(); - - if ( i_chiplet_base_addr == xbus) - { - - if ( vec_data.isBitSet(4)) { rc_ecmd |= exp_data.clearBit(0,3); } - if ( vec_data.isBitSet(5)) { rc_ecmd |= exp_data.clearBit(3,6); } - if ( vec_data.isBitSet(6)) { rc_ecmd |= exp_data.clearBit(9,6); } - if ( vec_data.isBitSet(7)) { rc_ecmd |= exp_data.clearBit(15,3);} - - } - - else - { - - if ( vec_data.isBitSet(4)) { rc_ecmd |= exp_data.clearBit(0,3); } - if ( vec_data.isBitSet(5)) { rc_ecmd |= exp_data.clearBit(3,3); } - if ( vec_data.isBitSet(6)) { rc_ecmd |= exp_data.clearBit(6,3); } - if ( vec_data.isBitSet(7)) { rc_ecmd |= exp_data.clearBit(9,3); } - if ( vec_data.isBitSet(9)) { rc_ecmd |= exp_data.clearBit(15,3);} - if ( vec_data.isBitSet(10)) { rc_ecmd |= exp_data.clearBit(18,3);} - if ( vec_data.isBitSet(11)) { rc_ecmd |= exp_data.clearBit(21,3);} - - } - - - if (rc_ecmd) - { - FAPI_ERR("proc_start_clocks_chiplet_check_clk_status_reg: Error 0x%x setting up data buffer to set clock status", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - - // check that value matches expected pattern - // set a unique HWP_ERROR - if (status_data.getDoubleWord(0) != exp_data.getDoubleWord(0)) - { - FAPI_ERR("proc_start_clocks_chiplet_check_clk_status_reg: Clock status register actual value (%016llX) does not match expected value (%016llX)", - status_data.getDoubleWord(0), exp_data.getDoubleWord(0)); - ecmdDataBufferBase & STATUS_REG = status_data; - ecmdDataBufferBase & EXPECTED_REG = exp_data; - - if ( i_chiplet_base_addr == xbus) - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_XBUS_CHIPLET_CLK_STATUS_ERR); - break; - } - if ( i_chiplet_base_addr == abus) - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_ABUS_CHIPLET_CLK_STATUS_ERR); - break; - } - if ( i_chiplet_base_addr == pcie) - { - const fapi::Target & CHIP_IN_ERROR = i_target; - FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_PCIE_CHIPLET_CLK_STATUS_ERR); - break; - } - - } - - } while(0); - - FAPI_DBG("proc_start_clocks_chiplet_check_clk_status_reg: End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility subroutine to clear force align in GP0 register -// parameters: i_target => chip target -// i_chiplet_base_addr => base SCOM address for chiplet -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_start_clocks_chiplet_clear_force_align( - const fapi::Target& i_target, - const uint32_t i_chiplet_base_addr) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase mask_data(64); - uint32_t scom_addr = i_chiplet_base_addr | - GENERIC_GP0_AND_0x00000004; - - FAPI_DBG("proc_start_clocks_chiplet_clear_force_align: Start"); - - do - { - // form AND mask to clear force align bit - rc_ecmd |= mask_data.flushTo1(); - rc_ecmd |= mask_data.clearBit(GP0_FORCE_ALIGN_BIT); - if (rc_ecmd) - { - FAPI_ERR("proc_start_clocks_chiplet_clear_force_align: Error 0x%x setting up data buffer to clear force align", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // write chiplet GP0 AND mask register to clear force align bit - rc = fapiPutScom(i_target, scom_addr, mask_data); - if (rc) - { - FAPI_ERR("proc_start_clocks_chiplet_clear_force_align: fapiPutScom error (GP0_AND_0x%08X)", - scom_addr); - break; - } - - } while(0); - - FAPI_DBG("proc_start_clocks_chiplet_clear_force_align: End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility subroutine to clear flushmode inhibit in GP0 register -// parameters: i_target => chip target -// i_chiplet_base_addr => base SCOM address for chiplet -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_start_clocks_chiplet_clear_flushmode_inhibit( - const fapi::Target& i_target, - const uint32_t i_chiplet_base_addr) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase mask_data(64); - uint32_t scom_addr = i_chiplet_base_addr | - GENERIC_GP0_AND_0x00000004; - - FAPI_DBG("proc_start_clocks_chiplet_clear_flushmode_inhibit: Start"); - - do - { - // form AND mask to clear force align bit - rc_ecmd |= mask_data.flushTo1(); - rc_ecmd |= mask_data.clearBit(GP0_FLUSHMODE_INHIBIT_BIT); - if (rc_ecmd) - { - FAPI_ERR("proc_start_clocks_chiplet_clear_flushmode_inhibit: Error 0x%x setting up data buffer to clear flushmode inhibit", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // write chiplet GP0 AND mask register to clear force align bit - rc = fapiPutScom(i_target, scom_addr, mask_data); - if (rc) - { - FAPI_ERR("proc_start_clocks_chiplet_clear_flushmode_inhibit: fapiPutScom error (GP0_AND_0x%08X)", - scom_addr); - break; - } - - } while(0); - - FAPI_DBG("proc_start_clocks_chiplet_clear_flushmode_inhibit: End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility subroutine to check chiplet FIR register for errors -// after clocks have been started -// parameters: i_target => chip target -// i_chiplet_base_addr => base SCOM address for chiplet -// returns: FAPI_RC_SUCCESS if operation was successful, else -// RC_PROC_START_CLOCKS_CHIPLETS_FIR_ERR if FIR register data doesn't -// match expected pattern -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_start_clocks_chiplet_check_fir( - const fapi::Target& i_target, - const uint32_t i_chiplet_base_addr) -{ - fapi::ReturnCode rc; - ecmdDataBufferBase fir_data(64); - uint32_t scom_addr = i_chiplet_base_addr | - GENERIC_XSTOP_0x00040000; - const uint32_t xbus = X_BUS_CHIPLET_0x04000000; - const uint32_t abus = A_BUS_CHIPLET_0x08000000; - const uint32_t pcie = PCIE_CHIPLET_0x09000000; - - - FAPI_DBG("proc_start_clocks_chiplet_check_fir: Start"); - - do - { - // read chiplet FIR register - rc = fapiGetScom(i_target, scom_addr, fir_data); - if (rc) - { - FAPI_ERR("proc_start_clocks_chiplet_check_fir: fapiGetScom error (XSTOP_0x%08X)", - scom_addr); - break; - } - - // check that value matches expected pattern - // set a unique HWP_ERROR - if (fir_data.getDoubleWord(0) != - PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP) - { - FAPI_ERR("proc_start_clocks_chiplet_check_fir: FIR register actual value (%016llX) does not match expected value (%016llX)", - fir_data.getDoubleWord(0), PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP); - ecmdDataBufferBase & FIR_REG = fir_data; - const uint64_t & FIR_EXP_REG = PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP; - - - if ( i_chiplet_base_addr == xbus) - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_XBUS_CHIPLET_FIR_ERR); - break; - } - if ( i_chiplet_base_addr == abus) - { - FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_ABUS_CHIPLET_FIR_ERR); - break; - } - if ( i_chiplet_base_addr == pcie) - { - - const fapi::Target & CHIP_IN_ERROR = i_target; - FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_PCIE_CHIPLET_FIR_ERR); - break; - } - - } - - } while(0); - - FAPI_DBG("proc_start_clocks_chiplet_check_fir: End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility subroutine to run clock start sequence on a generic chiplet -// parameters: i_target => chip target -// i_chiplet_base_addr => base SCOM address for chiplet -// returns: FAPI_RC_SUCCESS if operation was successful, else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_start_clocks_generic_chiplet( - const fapi::Target& i_target, - const uint32_t i_chiplet_base_addr) - -{ - fapi::ReturnCode rc; - uint64_t chiplet_reg_vec; - uint64_t chiplet_clkreg_vec; - - FAPI_DBG("proc_start_clocks_generic_chiplet: Start"); - - do - { - - - // clear chiplet fence in GP3 register - FAPI_DBG("Writing GP3 AND mask to clear chiplet fence ..."); - rc = proc_start_clocks_chiplet_clear_chiplet_fence(i_target, - i_chiplet_base_addr); - if (rc) - { - FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing GP3 AND mask to clear chiplet fence"); - break; - } - - // clear pervasive fence in GP0 register - FAPI_DBG("Writing GP0 AND mask to clear pervasive fence ..."); - rc = proc_start_clocks_chiplet_clear_perv_fence(i_target, - i_chiplet_base_addr); - if (rc) - { - FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing GP0 AND mask to clear pervasive fence"); - break; - } - - // set functional clock mux selects in GP0 register - FAPI_DBG("Writing GP0 AND mask to set functional clock mux selects ..."); - rc = proc_start_clocks_chiplet_set_mux_selects(i_target, - i_chiplet_base_addr); - if (rc) - { - FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing GP0 AND mask to set functional clock mux selects"); - break; - } - - // pick partial good region vector from SEEPROM - FAPI_DBG("Get partial good region vector ..."); - rc = proc_start_clocks_get_partial_good_vector(i_target, - i_chiplet_base_addr, - & chiplet_reg_vec - ); - if (rc) - { - FAPI_ERR("proc_start_clocks_generic_chiplet: Error getting partial good region vector"); - break; - } - - - // write clock region register to start clocks - FAPI_DBG("Writing clock region register to start clocks ..."); - rc = proc_start_clocks_chiplet_set_clk_region_reg(i_target, - i_chiplet_base_addr, - chiplet_reg_vec, - & chiplet_clkreg_vec - ); - - - if (rc) - { - FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing clock region register"); - break; - } - - // check clock status register to ensure that all clocks are started - FAPI_DBG("Checking clock status register ..."); - rc = proc_start_clocks_chiplet_check_clk_status_reg(i_target, - i_chiplet_base_addr, - chiplet_clkreg_vec); - if (rc) - { - FAPI_ERR("proc_start_clocks_generic_chiplet: Error checking clock status register"); - break; - } - - // clear force align bit in GP0 register - FAPI_DBG("Writing GP0 AND mask to clear force align ..."); - rc = proc_start_clocks_chiplet_clear_force_align(i_target, - i_chiplet_base_addr); - if (rc) - { - FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing GP0 AND mask to clear force align"); - break; - } - - // clear flushmode inhibit bit in GP0 register - FAPI_DBG("Writing GP0 AND mask to clear flushmode inhibit ..."); - rc = proc_start_clocks_chiplet_clear_flushmode_inhibit(i_target, - i_chiplet_base_addr); - if (rc) - { - FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing GP0 AND mask to clear flushmode inhibit"); - break; - } - - // check chiplet FIR register - FAPI_DBG("Checking chiplet FIR register for errors after clock start ..."); - rc = proc_start_clocks_chiplet_check_fir(i_target, - i_chiplet_base_addr); - if (rc) - { - FAPI_ERR("proc_start_clocks_generic_chiplet: Error checking chiplet FIR register after clock start"); - break; - } - - } while(0); - - FAPI_DBG("proc_start_clocks_generic_chiplet: End"); - - return rc; -} - - -//------------------------------------------------------------------------------ -// Hardware Procedure -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_start_clocks_chiplets(const fapi::Target& i_target, - bool xbus, bool abus, bool pcie) -{ - fapi::ReturnCode rc; - uint8_t xbus_enable_attr; - uint8_t abus_enable_attr; - uint8_t pcie_enable_attr; - - // mark HWP entry - FAPI_IMP("proc_start_clocks_chiplets: Entering ..."); - - do - { - if (xbus) - { - // query XBUS partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE, - &i_target, - xbus_enable_attr); - if (!rc.ok()) - { - FAPI_ERR("proc_start_clocks_chiplets: Error querying ATTR_PROC_X_ENABLE"); - break; - } - - if (xbus_enable_attr == fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE) - { - FAPI_DBG("Starting X bus chiplet clocks ..."); - rc = proc_start_clocks_generic_chiplet( - i_target, - X_BUS_CHIPLET_0x04000000); - if (rc) - { - FAPI_ERR("proc_start_clocks_chiplets: Error from proc_start_clocks_generic_chiplet (X)"); - break; - } - } - else - { - FAPI_DBG("Skipping XBUS chiplet clock start (partial good)."); - } - } - - if (abus) - { - // query ABUS partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE, - &i_target, - abus_enable_attr); - if (!rc.ok()) - { - FAPI_ERR("proc_start_clocks_chiplets: Error querying ATTR_PROC_A_ENABLE"); - break; - } - - if (abus_enable_attr == fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) - { - FAPI_DBG("Starting A bus chiplet clocks ..."); - rc = proc_start_clocks_generic_chiplet( - i_target, - A_BUS_CHIPLET_0x08000000); - if (rc) - { - FAPI_ERR("proc_start_clocks_chiplets: Error from proc_start_clocks_generic_chiplet (A)"); - break; - } - } - else - { - FAPI_DBG("Skipping ABUS chiplet clock start (partial good)."); - } - } - - if (pcie) - { - // query PCIE partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE, - &i_target, - pcie_enable_attr); - if (!rc.ok()) - { - FAPI_ERR("proc_start_clocks_chiplets: Error querying ATTR_PROC_PCIE_ENABLE"); - break; - } - - if (pcie_enable_attr == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) - { - FAPI_DBG("Starting PCIE chiplet clocks ..."); - rc = proc_start_clocks_generic_chiplet( - i_target, - PCIE_CHIPLET_0x09000000); - if (rc) - { - FAPI_ERR("proc_start_clocks_chiplets: Error from proc_start_clocks_generic_chiplet (PCIE)"); - break; - } - } - else - { - FAPI_DBG("Skipping PCIE chiplet clock start (partial good)."); - } - } - - } while (0); - - // mark HWP exit - FAPI_IMP("proc_start_clocks_chiplets: Exiting ..."); - return rc; -} - - -} // extern "C" diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H deleted file mode 100644 index 3a0a52e47..000000000 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H +++ /dev/null @@ -1,115 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_start_clocks_chiplets.H,v 1.7 2014/09/26 19:01:22 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_start_clocks_chiplets.H,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** **** -// *| -// *! TITLE : proc_start_clocks_chiplets.H -// *! DESCRIPTION : Start X/A/PCIE chiplet clocks (FAPI) -// *! -// *! OWNER NAME : Ralph Koester Email: rkoester@de.ibm.com -// *! BACKUP NAME : Gebhard Weber Email: gweber@de.ibm.com -// *! -// *! ADDITIONAL COMMENTS : -// *! -// *! The purpose of this procedure is to start the clocks for X/A/PCIe chiplets -// *! Reference: FW specification: 7.3, PRV POR specification spreadsheet -// *! - Start Xbus, ABus, PCIe clocks -// *! - Drop fences -// *! -// *! Prerequisites: proc_a_x_pci_pll_setup -// *! -//------------------------------------------------------------------------------ - -#ifndef _PROC_START_CLOCKS_CHIPLETS_H_ -#define _PROC_START_CLOCKS_CHIPLETS_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <fapi.H> -#include "p8_scom_addresses.H" - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode -(*proc_start_clocks_chiplets_FP_t)(const fapi::Target&, bool, bool, bool); - -extern "C" { - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// GP3 register bit/field definitions -const uint8_t GP3_FENCE_EN_BIT = 18; - -// GP0 register bit/field definitions -const uint8_t GP0_ABSTCLK_MUXSEL_BIT = 0; -const uint8_t GP0_SYNCCLK_MUXSEL_BIT = 1; -const uint8_t GP0_FLUSHMODE_INHIBIT_BIT = 2; -const uint8_t GP0_FORCE_ALIGN_BIT = 3; -const uint8_t GP0_PERV_FENCE_BIT = 63; - -// Clock Region Register clock start data patterns -const uint64_t PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_NSL_ARY = 0x4FE0060000000000ull; -const uint64_t PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_ALL = 0x4FE00E0000000000ull; - -// Chiplet FIR register expected pattern -const uint64_t PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP = 0x0000000000000000ull; - - -// Input clock region vector mask (for bit manipulation of clock regions) -const uint64_t PROC_START_CLOCKS_CHIPLETS_CLOCK_REGION_MANIPULATION = 0xF0000FFFFFFFFFFFull; - - -//------------------------------------------------------------------------------ -// Function prototype -//------------------------------------------------------------------------------ - -// function: FAPI proc_start_clocks_chiplets HWP entry point -// start clocks for X/A/PCIE chiplets -// parameters: i_target => P8 chip target -// i_xbus => start X chiplet clocks? -// i_abus => start A chiplet clocks? -// i_pcie => start PCIE chiplet clocks? -// returns: FAPI_RC_SUCCESS if clock start sequence completes successfully -// else FAPI getscom/putscom return code for failing operation -fapi::ReturnCode proc_start_clocks_chiplets(const fapi::Target& i_target, - bool i_xbus, - bool i_abus, - bool i_pcie); - -} // extern "C" - -#endif // _PROC_START_CLOCKS_CHIPLETS_H_ |
