diff options
Diffstat (limited to 'src/usr/hwpf/hwp/memory_attributes.xml')
| -rw-r--r-- | src/usr/hwpf/hwp/memory_attributes.xml | 406 |
1 files changed, 399 insertions, 7 deletions
diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml index 80fa1fb8f..b4059a2ea 100644 --- a/src/usr/hwpf/hwp/memory_attributes.xml +++ b/src/usr/hwpf/hwp/memory_attributes.xml @@ -23,7 +23,7 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <attributes> -<!-- $Id: memory_attributes.xml,v 1.154 2015/08/26 03:14:17 eliner Exp $ --> +<!-- $Id: memory_attributes.xml,v 1.159 2015/09/09 18:10:53 thi Exp $ --> <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB --> <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP --> <!-- *********************************************************************** --> @@ -99,7 +99,7 @@ Set by: PLL settings written by Dave Cadigan</description> <id>ATTR_MSS_VREF_CAL_CNTL</id> <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType> <description>Training Control over IPL - ENUM - 0x00=DISABLE /Skip V-ref Train; 0x01=DRAM - Enable V-Ref Train DRAM Level; 0x02=RANK Level Training; 0x03=PORT Level Training; 0x04=MBA Level; 0x05=CENTAUR level; - Default Value = 0x01; + Default Value = 0x01; </description> <valueType>uint8</valueType> <platInit/> @@ -108,7 +108,7 @@ Set by: PLL settings written by Dave Cadigan</description> <odmChangeable/> <persistRuntime/> </attribute> - + <attribute> <id>ATTR_MSS_DIMM_MFG_ID_CODE</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> @@ -1174,6 +1174,401 @@ firmware notes: none</description> </attribute> <attribute> + <id>ATTR_EFF_DIMM_DDR4_RC00</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC00: Global Features Control Word.For normal operation, output inversion is always enabled. For DIMM vendor test purpose, output inversion can be disabled. +When disabled, register tPDM is not guaranteed to be met. NOTE: Default value - 0x00. Values Range from 0-8. +00 - Normal Operation; 01 - Output Inversion Disabled; 02 - Weak Drive Enabled; 04 - A outputs disabled; 08 - B outputs disabled; So on. +No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC01</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC01 - Clock Driver Enable Control Word.1. Output clocks may be individually turned on or off to conserve power. The system must read the module SPD to determine which clock outputs are used by the module. The PLL remains locked on CK_t/CK_c unless the system stops the clock inputs to the DDR4RCD02 to enter the lowest power mode. + Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC02</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC02: Timing and IBT Control Word; Default value - 0x00. Values Range from 0-8. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC03</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC03 - CA and CS Signals Driver Characteristics Control Word; Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 1st Nibble for CS and CA. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC04</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC04 - ODT and CKE Signals Driver Characteristics Control Word; Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 137, 2nd Nibble for ODT and CKE. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC05</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC05 - Clock Driver Characteristics Control Word; Default value - 0x05 (Moderate Drive). Values Range from 00 to 0F. Has to be picked up from SPD byte 138, 2nd Nibble for CK. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC06_07</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC06: Command Space Control Word definition; Default value - 0xF0 (NOP). Values Range from 00 to F0. F0RC07 not used. RDIMM +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC08</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC08: Input/Output Configuration Control Word; Default value - 0x03. Values Range from 00 to 08 decimal. Check the stack height and calculate dynamically; 00 = Stack height_8; 01 = Stack height_4; + 02 = Stack height_2; +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC09</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC09: Power Saving Settings Control Word; Default value - 0xF0 (NOP). Values Range from 00 to F0. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC10</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>RDIMM Operating Speed; Read from ATTR_MSS_FREQ; Default value - 00. Values Range from 00 to 09. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC11</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>Operating Voltage VDD and VrefCA Source Control Word; Read from ATTR_MSS_VOLT. Default value - 14. Values Range from 00 to 15 decimal. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC12</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC0C - Training Control Word; Default value - 00. Values Range from 00 to 07 decimal.No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC13</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC0D - DIMM Configuration Control Word; Default value - 0B. Values Range from 00 to 15 decimal. Dynamically calculated using 4 bits[0:3] Bit 0 - Address Mirroring; Bit 1 - Rdimm(1)/Lrdimm (0) ; Bit 2 - N/A ; Bit 3 - CS Mode (Direct / Quad CS mode etc); +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC14</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC0E - Parity Control Word; Default value - 00. Check from ATTR_EFF_CA_PARITY and assign; Values Range from 00 to 0F. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC15</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC0F - Command Latency Adder Control Word; Default value - 04. Values Range from 00 to 04. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_1x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC1x - Internal VrefCA Control Word; Default value - 00. Values Range from 00 to 3F.No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_2x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC2x: I2C Bus Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_3x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC3x - Fine Granularity RDIMM Operating Speed; Default value = (Operating Freq - 1250)/20. Values Range from 00 to 61 Hex. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_4x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC4x: CW Source Selection Control Word; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_5x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC5x: CW Destination Selection and Write/Read Additional QxODT[1:0] Signal High; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_6x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC6x: CW Data Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_7x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC7x: IBT Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_8x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC8x: ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_9x</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RC9x1: QxODT[1:0] Write Pattern Control Word; Default value - 00. Values Range from 00 to FF.No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_Ax</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RCAx1: QxODT[1:0] Read Pattern Control Word; Default value - 00. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> + <id>ATTR_EFF_DIMM_DDR4_RC_Bx</id> + <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> + <description>F0RCBx: IBT and MRS Snoop Control Word; Default value - 07. Values Range from 00 to FF. No need to calculate; User can override with desired experimental value. +creator: mss_eff_cnfg +consumer: mss_dram_init +firmware notes: none</description> + <valueType>uint8</valueType> + <writeable/> + <platInit/> + <odmVisable/> + <odmChangeable/> + <array> 2 2</array> +</attribute> + +<attribute> <id>ATTR_EFF_DIMM_RCD_IBT</id> <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> <description>RCD IBT. Used in mss_dram_init and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value. @@ -2478,7 +2873,7 @@ Firmware shares some code with the processor, so the attribute is named so they <writeable/> <odmVisable/> <odmChangeable/> - <array> 2 2</array> + <array> 2 2</array> </attribute> <attribute> @@ -2906,18 +3301,15 @@ Will be set at an MBA level with one policy to be used</description> <odmVisable/> </attribute> -<!-- TODO Thi <attribute> <id>ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description>Option to control MCS prefetch retry threshold, for performance optimization. This attribute controls the number of retries in the prefetch engine. Retry threshold available ranges from 16 to 30. Note: Values outside those ranges will default to 30. In MRW.</description> <valueType>uint8</valueType> <platInit/> - <writeable/> <odmVisable/> <odmChangeable/> </attribute> ---> <attribute> <id>ATTR_MRW_POWER_CONTROL_REQUESTED</id> |
