diff options
Diffstat (limited to 'src/build/citest')
| -rw-r--r-- | src/build/citest/etc/bbuild | 2 | ||||
| -rw-r--r-- | src/build/citest/etc/patches/centaur.act.patch | 20 | ||||
| -rw-r--r-- | src/build/citest/etc/patches/centaur.act.slew.patch | 53 | ||||
| -rw-r--r-- | src/build/citest/etc/patches/patchlist.txt | 23 | ||||
| -rw-r--r-- | src/build/citest/etc/patches/s1.act.io.patch | 223 | ||||
| -rwxr-xr-x | src/build/citest/etc/workarounds.postsimsetup | 38 |
6 files changed, 1 insertions, 358 deletions
diff --git a/src/build/citest/etc/bbuild b/src/build/citest/etc/bbuild index 204bafd54..e64a1a0f6 100644 --- a/src/build/citest/etc/bbuild +++ b/src/build/citest/etc/bbuild @@ -1 +1 @@ -/esw/fips810/Builds/b1207x_1251.810 +/esw/fips801/Builds/b1216c_1251.801 diff --git a/src/build/citest/etc/patches/centaur.act.patch b/src/build/citest/etc/patches/centaur.act.patch deleted file mode 100644 index 099132b85..000000000 --- a/src/build/citest/etc/patches/centaur.act.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- centaur.act.old 2012-11-29 13:26:32.062325973 -0500 -+++ centaur.act 2012-11-29 13:26:55.228400406 -0500 -@@ -187,7 +187,7 @@ CAUSE_EFFECT { - WATCH=[REG(0x0301060C)] #MBMSR=0301060C - CAUSE: TARGET=[REG(0x0301060C)] OP=[BIT,OFF] BIT=[0] # Maint Cmd Complete - CAUSE: TARGET=[REG(0x0301060F)] OP=[BIT,ON] BIT=[11] # Enable Special attn -- #EFFECT: TARGET=[REG(0x03010611)] OP=[BIT,ON] BIT=[0] # Set Special attn bit -+ EFFECT: TARGET=[REG(0x03010611)] OP=[BIT,ON] BIT=[0] # Set Special attn bit - } - - #Set command in progress -@@ -223,7 +223,7 @@ CAUSE_EFFECT { - WATCH=[REG(0x03010E0C)] #MBMSR=03010E0C - CAUSE: TARGET=[REG(0x03010E0C)] OP=[BIT,OFF] BIT=[0] # Maint Cmd Complete - CAUSE: TARGET=[REG(0x03010E0F)] OP=[BIT,ON] BIT=[11] # Enable Special attn -- #EFFECT: TARGET=[REG(0x03010E11)] OP=[BIT,ON] BIT=[0] # Set Special attn bit -+ EFFECT: TARGET=[REG(0x03010E11)] OP=[BIT,ON] BIT=[0] # Set Special attn bit - } - - #*************************************** diff --git a/src/build/citest/etc/patches/centaur.act.slew.patch b/src/build/citest/etc/patches/centaur.act.slew.patch deleted file mode 100644 index 089c52ecd..000000000 --- a/src/build/citest/etc/patches/centaur.act.slew.patch +++ /dev/null @@ -1,53 +0,0 @@ ---- /esw/fips810/Builds/b1207x_1251.810/src/simu/data/cec-chip/centaur.act 2012-09-18 09:23:16.000000000 -0500 -+++ ./centaur.act 2012-12-13 20:00:14.319266193 -0600 -@@ -29,6 +29,7 @@ - # ch139 F849719 ched 08/28/12 Apply Dean Sanner's fix for "OPCG SCAN0" - # action - # SW164340 bradleyb 09/18/12 temp back out mdia actions -+# SW178996 mjjones 12/13/12 Slew calibration actions - #******************************************************************** - # - -@@ -89,6 +90,42 @@ - } - - CAUSE_EFFECT { -+ LABEL=[Slew calibration for MBA0 Port0] -+ WATCH=[INDSCOM_0x0301143F(0x00008039)] # SLEW_CAL_CNTL_P0 -+ CAUSE: TARGET=[INDSCOM_0x0301143F(0x00008039)] OP=[BIT,ON] BIT=[48] # Set Start bit -+ EFFECT: TARGET=[INDSCOM_0x0301143F(0x00008034)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000031)] # SLEW_DONE_STAT -+ # 0x30 = Status Mask. 0x30 = Done with no errors -+ # 0x0F = Calibrated Data Mask. Anything other than all 0s or all 1s is good -+} -+ -+CAUSE_EFFECT { -+ LABEL=[Slew calibration for MBA0 Port1] -+ WATCH=[INDSCOM_0x0301143F(0x00018039)] # SLEW_CAL_CNTL_P1 -+ CAUSE: TARGET=[INDSCOM_0x0301143F(0x00018039)] OP=[BIT,ON] BIT=[48] # Set Start bit -+ EFFECT: TARGET=[INDSCOM_0x0301143F(0x00018034)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000031)] # SLEW_DONE_STAT -+ # 0x30 = Status Mask. 0x30 = Done with no errors -+ # 0x0F = Calibrated Data Mask. Anything other than all 0s or all 1s is good -+} -+ -+CAUSE_EFFECT { -+ LABEL=[Slew calibration for MBA1 Port0] -+ WATCH=[INDSCOM_0x0301183F(0x00008039)] # SLEW_CAL_CNTL_P0 -+ CAUSE: TARGET=[INDSCOM_0x0301183F(0x00008039)] OP=[BIT,ON] BIT=[48] # Set Start bit -+ EFFECT: TARGET=[INDSCOM_0x0301183F(0x00008034)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000031)] # SLEW_DONE_STAT -+ # 0x30 = Status Mask. 0x30 = Done with no errors -+ # 0x0F = Calibrated Data Mask. Anything other than all 0s or all 1s is good -+} -+ -+CAUSE_EFFECT { -+ LABEL=[Slew calibration for MBA0 Port1] -+ WATCH=[INDSCOM_0x0301183F(0x00018039)] # SLEW_CAL_CNTL_P1 -+ CAUSE: TARGET=[INDSCOM_0x0301183F(0x00018039)] OP=[BIT,ON] BIT=[48] # Set Start bit -+ EFFECT: TARGET=[INDSCOM_0x0301183F(0x00018034)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000031)] # SLEW_DONE_STAT -+ # 0x30 = Status Mask. 0x30 = Done with no errors -+ # 0x0F = Calibrated Data Mask. Anything other than all 0s or all 1s is good -+} -+ -+CAUSE_EFFECT { - # copy chip ID - LABEL=[DEVICE_ID_REG] # TPTOP.PIB.PCBMS.DEVICE_ID_REG - WATCH_READ=[REG(0x000F000F)] # if someone reads this diff --git a/src/build/citest/etc/patches/patchlist.txt b/src/build/citest/etc/patches/patchlist.txt index 281c4743d..18371bf8f 100644 --- a/src/build/citest/etc/patches/patchlist.txt +++ b/src/build/citest/etc/patches/patchlist.txt @@ -5,29 +5,6 @@ Brief description of the problem or reason for patch -Files: list of files -Coreq: list of associated changes, e.g. workarounds.presimsetup -New actions for Centaur maint command complete --RTC: Task 59218 will remove the patch --CMVC: D862701 is integrating the changes --Files: centaur.act.patch --Coreq: there are related changes in workarounds.postsimsetup - -Bus training does not set all 5 training bits at once, therefore the -Murano Action File must cope with any bit being set. -Proc-Cen Framelock now looks for a different status bit in a different -register, therefore the Murano Action File must cope --RTC: Task 60658 will remove this patch --CMVC: 864393 --Files: s1.act.io.patch --Coreq: None - -Centaur Slew calibration sets a start bit in a register and looks -for completion and calibration values in another register, therefore -the Centaur Action File must cope --RTC: Task 60658 will remove this patch --CMVC: 864393 --Files: centaur.act.slew.patch --Coreq: None - Additional actions for Centaur maint command complete -RTC: Task 60668 will remove the patch -CMVC: D864673 is integrating the changes diff --git a/src/build/citest/etc/patches/s1.act.io.patch b/src/build/citest/etc/patches/s1.act.io.patch deleted file mode 100644 index 57b42e25c..000000000 --- a/src/build/citest/etc/patches/s1.act.io.patch +++ /dev/null @@ -1,223 +0,0 @@ ---- /esw/fips810/Builds/b1207x_1251.810/src/simu/data/cec-chip/s1.act 2012-11-19 16:58:36.000000000 -0600 -+++ ./s1.act 2012-12-13 20:12:09.282244491 -0600 -@@ -15,6 +15,8 @@ - # SW170609 sankarkk 10/13/12 Added ramming support - # to99 SW170119 opiet 10/23/12 Set Core 1 functional bit - # dds129 SW175501 jlortiz 11/19/12 changes for SBEstart action -+# SW178996 mjjones 12/11/12 Breakout DMI run_training bits -+# Update framelock FRTL actions - - # ch110 send instruction start signal to phyp model for core 5, thread 0 - CAUSE_EFFECT { -@@ -95,7 +97,7 @@ - WATCH=[REG(0x02011C4A)] # MCI4_CFG_REG - CAUSE: TARGET=[REG(0x02011C4A)] OP=[BIT,ON] BIT=[8] # MCI4_CFG_REG[8] - Start Frame Lock Frtl - EFFECT: TARGET=[REG(0x02011C4B)] OP=[BIT,ON] BIT=[2] # MCI_STAT_REG - Frame Lock Frtl Pass -- EFFECT: TARGET=[ALIAS(mymcPort4)REG(0x0201080B)] OP=[BIT,ON] BIT=[2] # MBI_STAT_REG - Frame Lock Frtl Pass -+ EFFECT: TARGET=[REG(0x02011C4B)] OP=[BIT,ON] BIT=[12] # MCI_STAT_REG - Frame Lock Channel Interlock Pass - } - - CAUSE_EFFECT { -@@ -111,7 +113,7 @@ - WATCH=[REG(0x02011CCA)] # MCI5_CFG_REG - CAUSE: TARGET=[REG(0x02011CCA)] OP=[BIT,ON] BIT=[8] # MCI5_CFG_REG[8] - Start Frame Lock Frtl - EFFECT: TARGET=[REG(0x02011CCB)] OP=[BIT,ON] BIT=[2] # MCI_STAT_REG - Frame Lock Frtl Pass -- EFFECT: TARGET=[ALIAS(mymcPort5)REG(0x0201080B)] OP=[BIT,ON] BIT=[2] # MBI_STAT_REG - Frame Lock Frtl Pass -+ EFFECT: TARGET=[REG(0x02011CCB)] OP=[BIT,ON] BIT=[12] # MCI_STAT_REG - Frame Lock Channel Interlock Pass - } - - CAUSE_EFFECT { -@@ -127,7 +129,7 @@ - WATCH=[REG(0x02011D4A)] # MCI6_CFG_REG - CAUSE: TARGET=[REG(0x02011D4A)] OP=[BIT,ON] BIT=[8] # MCI6_CFG_REG[8] - Start Frame Lock Frtl - EFFECT: TARGET=[REG(0x02011D4B)] OP=[BIT,ON] BIT=[2] # MCI_STAT_REG - Frame Lock Frtl Pass -- EFFECT: TARGET=[ALIAS(mymcPort6)REG(0x0201080B)] OP=[BIT,ON] BIT=[2] # MBI_STAT_REG - Frame Lock Frtl Pass -+ EFFECT: TARGET=[REG(0x02011D4B)] OP=[BIT,ON] BIT=[12] # MCI_STAT_REG - Frame Lock Channel Interlock Pass - } - - CAUSE_EFFECT { -@@ -143,39 +145,167 @@ - WATCH=[REG(0x02011DCA)] # MCI7_CFG_REG - CAUSE: TARGET=[REG(0x02011DCA)] OP=[BIT,ON] BIT=[8] # MCI7_CFG_REG[8] - Start Frame Lock Frtl - EFFECT: TARGET=[REG(0x02011DCB)] OP=[BIT,ON] BIT=[2] # MCI_STAT_REG - Frame Lock Frtl Pass -- EFFECT: TARGET=[ALIAS(mymcPort7)REG(0x0201080B)] OP=[BIT,ON] BIT=[2] # MBI_STAT_REG - Frame Lock Frtl Pass -+ EFFECT: TARGET=[REG(0x02011DCB)] OP=[BIT,ON] BIT=[12] # MCI_STAT_REG - Frame Lock Channel Interlock Pass - } - - CAUSE_EFFECT { -- LABEL=[IO_run_training for MCS4] -+ LABEL=[IO_run_training wiretest for MCS4] - WATCH=[INDSCOM_0x02011E3F(0x00088060)] # start trigger register -- CAUSE: TARGET=[ALIAS(mymcPort4)INDSCOM_0x0201043F(0x00088000)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF0] -- CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088060)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF)] -- EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088860)] OP=[EQUALTO,BUFSTRING] DATA=[LITERAL(64,00000000 0000F800)] -+ CAUSE: TARGET=[ALIAS(mymcPort4)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[48] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088060)] OP=[BIT,ON] BIT=[48] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088860)] OP=[BIT,ON] BIT=[48] - } - - CAUSE_EFFECT { -- LABEL=[IO_run_training for MCS5] -+ LABEL=[IO_run_training deskew for MCS4] -+ WATCH=[INDSCOM_0x02011E3F(0x00088060)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort4)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[49] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088060)] OP=[BIT,ON] BIT=[49] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088860)] OP=[BIT,ON] BIT=[49] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training eye_opt for MCS4] -+ WATCH=[INDSCOM_0x02011E3F(0x00088060)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort4)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[50] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088060)] OP=[BIT,ON] BIT=[50] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088860)] OP=[BIT,ON] BIT=[50] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training repair for MCS4] -+ WATCH=[INDSCOM_0x02011E3F(0x00088060)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort4)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[51] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088060)] OP=[BIT,ON] BIT=[51] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088860)] OP=[BIT,ON] BIT=[51] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training func_mode for MCS4] -+ WATCH=[INDSCOM_0x02011E3F(0x00088060)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort4)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[52] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088060)] OP=[BIT,ON] BIT=[52] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088860)] OP=[BIT,ON] BIT=[52] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training wiretest for MCS5] -+ WATCH=[INDSCOM_0x02011E3F(0x00088040)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort5)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[48] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088040)] OP=[BIT,ON] BIT=[48] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088840)] OP=[BIT,ON] BIT=[48] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training deskew for MCS5] -+ WATCH=[INDSCOM_0x02011E3F(0x00088040)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort5)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[49] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088040)] OP=[BIT,ON] BIT=[49] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088840)] OP=[BIT,ON] BIT=[49] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training eye_opt for MCS5] -+ WATCH=[INDSCOM_0x02011E3F(0x00088040)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort5)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[50] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088040)] OP=[BIT,ON] BIT=[50] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088840)] OP=[BIT,ON] BIT=[50] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training repair for MCS5] -+ WATCH=[INDSCOM_0x02011E3F(0x00088040)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort5)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[51] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088040)] OP=[BIT,ON] BIT=[51] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088840)] OP=[BIT,ON] BIT=[51] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training func_mode for MCS5] - WATCH=[INDSCOM_0x02011E3F(0x00088040)] # start trigger register -- CAUSE: TARGET=[ALIAS(mymcPort5)INDSCOM_0x0201043F(0x00088000)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF0] -- CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088040)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF)] -- EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088840)] OP=[EQUALTO,BUFSTRING] DATA=[LITERAL(64,00000000 0000F800)] -+ CAUSE: TARGET=[ALIAS(mymcPort5)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[52] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088040)] OP=[BIT,ON] BIT=[52] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088840)] OP=[BIT,ON] BIT=[52] - } - - CAUSE_EFFECT { -- LABEL=[IO_run_training for MCS6] -+ LABEL=[IO_run_training wiretest for MCS6] - WATCH=[INDSCOM_0x02011E3F(0x00088020)] # start trigger register -- CAUSE: TARGET=[ALIAS(mymcPort6)INDSCOM_0x0201043F(0x00088000)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF0] -- CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088020)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF)] -- EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088820)] OP=[EQUALTO,BUFSTRING] DATA=[LITERAL(64,00000000 0000F800)] -+ CAUSE: TARGET=[ALIAS(mymcPort6)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[48] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088020)] OP=[BIT,ON] BIT=[48] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088820)] OP=[BIT,ON] BIT=[48] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training deskew for MCS6] -+ WATCH=[INDSCOM_0x02011E3F(0x00088020)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort6)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[49] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088020)] OP=[BIT,ON] BIT=[49] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088820)] OP=[BIT,ON] BIT=[49] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training eye_opt for MCS6] -+ WATCH=[INDSCOM_0x02011E3F(0x00088020)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort6)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[50] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088020)] OP=[BIT,ON] BIT=[50] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088820)] OP=[BIT,ON] BIT=[50] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training repair for MCS6] -+ WATCH=[INDSCOM_0x02011E3F(0x00088020)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort6)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[51] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088020)] OP=[BIT,ON] BIT=[51] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088820)] OP=[BIT,ON] BIT=[51] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training func_mode for MCS6] -+ WATCH=[INDSCOM_0x02011E3F(0x00088020)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort6)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[52] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088020)] OP=[BIT,ON] BIT=[52] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088820)] OP=[BIT,ON] BIT=[52] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training wiretest for MCS7] -+ WATCH=[INDSCOM_0x02011E3F(0x00088000)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort7)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[48] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088000)] OP=[BIT,ON] BIT=[48] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088800)] OP=[BIT,ON] BIT=[48] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training deskew for MCS7] -+ WATCH=[INDSCOM_0x02011E3F(0x00088000)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort7)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[49] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088000)] OP=[BIT,ON] BIT=[49] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088800)] OP=[BIT,ON] BIT=[49] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training eye_opt for MCS7] -+ WATCH=[INDSCOM_0x02011E3F(0x00088000)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort7)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[50] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088000)] OP=[BIT,ON] BIT=[50] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088800)] OP=[BIT,ON] BIT=[50] -+} -+ -+CAUSE_EFFECT { -+ LABEL=[IO_run_training repair for MCS7] -+ WATCH=[INDSCOM_0x02011E3F(0x00088000)] # start trigger register -+ CAUSE: TARGET=[ALIAS(mymcPort7)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[51] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088000)] OP=[BIT,ON] BIT=[51] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088800)] OP=[BIT,ON] BIT=[51] - } - - CAUSE_EFFECT { -- LABEL=[IO_run_training for MCS7] -+ LABEL=[IO_run_training func_mode for MCS7] - WATCH=[INDSCOM_0x02011E3F(0x00088000)] # start trigger register -- CAUSE: TARGET=[ALIAS(mymcPort7)INDSCOM_0x0201043F(0x00088000)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF0] -- CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088000)] OP=[EQUALTO,BUF,MASK] DATA=[LITERAL(64,00000000 0000F800)] MASK=[LITERAL(64,00000000 0000FFFF)] -- EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088800)] OP=[EQUALTO,BUFSTRING] DATA=[LITERAL(64,00000000 0000F800)] -+ CAUSE: TARGET=[ALIAS(mymcPort7)INDSCOM_0x0201043F(0x00088000)] OP=[BIT,ON] BIT=[52] -+ CAUSE: TARGET=[INDSCOM_0x02011E3F(0x00088000)] OP=[BIT,ON] BIT=[52] -+ EFFECT: TARGET=[INDSCOM_0x02011E3F(0x00088800)] OP=[BIT,ON] BIT=[52] - } - - CAUSE_EFFECT { diff --git a/src/build/citest/etc/workarounds.postsimsetup b/src/build/citest/etc/workarounds.postsimsetup index bc26ee2e6..7ff9800d4 100755 --- a/src/build/citest/etc/workarounds.postsimsetup +++ b/src/build/citest/etc/workarounds.postsimsetup @@ -26,49 +26,11 @@ ## to setup the sandbox ## -### Updates to handle maint command complete (Remove with RTC:59218) -echo "+++ Update cec-chip files for Centaur maint command complete." -mkdir -p $sb/simu/data/cec-chip/ -cp $bb/src/simu/data/cec-chip/centaur.act $sb/simu/data/cec-chip/centaur.act -patch -p0 $sb/simu/data/cec-chip/centaur.act $HOSTBOOTROOT/src/build/citest/etc/patches/centaur.act.patch - -### Update centaur.act to handle slew calibration (Remove with 60568) -echo "+++ Updating Centaur Action File to support slew calibration" -patch -p0 $sb/simu/data/cec-chip/centaur.act $HOSTBOOTROOT/src/build/citest/etc/patches/centaur.act.slew.patch - -#### Update config file with new variables (Remove with RTC: 59984) #### -#### Update config file with new GFW_P8_MURANO_CENTAUR_MODEL_EC separate RTC:60617) ### -#### Update config file with new GFW_P8_VENICE_CENTAUR_MODEL_EC separate RTC:60617) ### - -echo "+++ Forcing SBE header usage till Fips defaults to ON" -echo "+++ Forcing GFW_P8_MURANO_CENTAUR_MODEL_EC to 790 from 730 there currently" -mkdir -p $sb/simu/configs -mkdir -p $sb/simu/data/cec-chip -egrep -v "SETENV GFW_P8_MURANO_HB_BASE_IMG_USE_PNOR|SETENV GFW_P8_MURANO_HB_BASE_IMG_WITH_ECC|GFW_P8_MURANO_CENTAUR_MODEL_EC" $BACKING_BUILD/src/simu/configs/P8_MURANO.config> $sb/simu/configs/P8_MURANO.config -egrep -v "SETENV GFW_P8_VENICE_HB_BASE_IMG_USE_PNOR|SETENV GFW_P8_VENICE_HB_BASE_IMG_WITH_ECC|GFW_P8_VENICE_CENTAUR_MODEL_EC" $BACKING_BUILD/src/simu/configs/P8_VENICE.config> $sb/simu/configs/P8_VENICE.config -echo "SETENV GFW_P8_MURANO_HB_BASE_IMG_USE_PNOR yes" >> $sb/simu/configs/P8_MURANO.config -echo "SETENV GFW_P8_VENICE_HB_BASE_IMG_USE_PNOR yes" >> $sb/simu/configs/P8_VENICE.config -echo "SETENV GFW_P8_MURANO_HB_BASE_IMG_WITH_ECC yes" >> $sb/simu/configs/P8_MURANO.config -echo "SETENV GFW_P8_VENICE_HB_BASE_IMG_WITH_ECC yes" >> $sb/simu/configs/P8_VENICE.config -echo "SETENV GFW_P8_VENICE_CENTAUR_MODEL_EC 910790" >> $sb/simu/configs/P8_VENICE.config -echo "SETENV GFW_P8_MURANO_CENTAUR_MODEL_EC 910790" >> $sb/simu/configs/P8_MURANO.config echo "+++ Updating s1.act and p8_common.chip" mkdir -p $sb/simu/data/cec-chip cp $BACKING_BUILD/src/simu/data/cec-chip/s1.act $sb/simu/data/cec-chip cp $BACKING_BUILD/src/simu/data/cec-chip/p8.act $sb/simu/data/cec-chip -sed -i -e's/sbeStart, 0x03eca000,/sbeStart, FSIMBOX(0x3A),/' $sb/simu/data/cec-chip/s1.act -sed -i -e's/sbeStart, 0x03eca000,/sbeStart, FSIMBOX(0x3A),/' $sb/simu/data/cec-chip/p8.act - -### Update s1.act to handle bus training and framelock (Remove with 60568) -echo "+++ Updating Murano Action File to support bus training and framelock" -patch -p0 $sb/simu/data/cec-chip/s1.act $HOSTBOOTROOT/src/build/citest/etc/patches/s1.act.io.patch - -cp $BACKING_BUILD/src/simu/data/cec-chip/p8_common.chip $sb/simu/data/cec-chip -sed -i -e's/0xE0, 32 #MBOX_SCRATCH_0/0x38, 32 #MBOX_SCRATCH_0/' $sb/simu/data/cec-chip/p8_common.chip -sed -i -e's/0xE4, 32 #MBOX_SCRATCH_1/0x39, 32 #MBOX_SCRATCH_1/' $sb/simu/data/cec-chip/p8_common.chip -sed -i -e's/0xE8, 32 #MBOX_SCRATCH_2/0x3A, 32 #MBOX_SCRATCH_2/' $sb/simu/data/cec-chip/p8_common.chip -sed -i -e's/0xEC, 32 #MBOX_SCRATCH_3/0x3B, 32 #MBOX_SCRATCH_3/' $sb/simu/data/cec-chip/p8_common.chip #### Update actions files for proc_a_x_pci_dmi_pll_setup - #### Remove when F864674 under RTC 60617 |
