diff options
36 files changed, 1756 insertions, 805 deletions
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C index 80dc5a4aa..52f019a1b 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_cd.C,v 1.8 2013/05/07 22:10:20 jmcgill Exp $ +// $Id: proc_build_smp_fbc_cd.C,v 1.9 2013/06/20 21:19:02 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.C,v $ //------------------------------------------------------------------------------ // *| @@ -1266,19 +1266,44 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5( fapi::ReturnCode rc; uint32_t rc_ecmd = 0x0; ecmdDataBufferBase data(64); + uint8_t ver2 = 0x0; // mark function entry FAPI_DBG("proc_build_smp_set_sconfig_we5: Start"); do { + rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_CENT5_VER2, + &(i_smp_chip.chip->this_chip), + ver2); + if (!rc.ok()) + { + FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_CENT5_VER2"); + break; + } + // build register content // pb_cfg_lock_on_links + uint32_t PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT = + (ver2)? + (PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT_VER2): + (PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT_VER1); + rc_ecmd |= data.writeBit( PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT, PB_SCONFIG_WE5_LOCK_ON_LINKS?1:0); // pb_cfg_x_on_link_tok_agg_threshold + uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT = + (ver2)? + (PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2): + (PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1); + + uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT = + (ver2)? + (PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2): + (PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1); + rc_ecmd |= data.insertFromRight( PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD, PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT, @@ -1286,6 +1311,16 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5( PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT+1)); // pb_cfg_x_off_link_tok_agg_threshold + uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT = + (ver2)? + (PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2): + (PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1); + + uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT = + (ver2)? + (PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2): + (PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1); + rc_ecmd |= data.insertFromRight( PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD, PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT, @@ -1293,6 +1328,16 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5( PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT+1)); // pb_cfg_x_a_link_tok_agg_threshold + uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT = + (ver2)? + (PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2): + (PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1); + + uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT = + (ver2)? + (PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2): + (PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1); + rc_ecmd |= data.insertFromRight( PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD, PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT, @@ -1300,6 +1345,16 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5( PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT+1)); // pb_cfg_x_f_link_tok_agg_threshold + uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT = + (ver2)? + (PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2): + (PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1); + + uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT = + (ver2)? + (PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2): + (PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1); + rc_ecmd |= data.insertFromRight( PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD, PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT, @@ -1307,6 +1362,16 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5( PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT+1)); // pb_cfg_x_a_link_tok_ind_threshold + uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT = + (ver2)? + (PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT_VER2): + (PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT_VER1); + + uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT = + (ver2)? + (PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT_VER2): + (PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT_VER1); + rc_ecmd |= data.insertFromRight( PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD, PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT, @@ -1314,11 +1379,26 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5( PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT+1)); // pb_cfg_passthru_enable + uint32_t PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT = + (ver2)? + (PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT_VER2): + (PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT_VER1); + rc_ecmd |= data.writeBit( PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT, PB_SCONFIG_WE5_PASSTHRU_ENABLE?1:0); // pb_cfg_passthru_x_priority + uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT = + (ver2)? + (PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT_VER2): + (PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT_VER1); + + uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT = + (ver2)? + (PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT_VER2): + (PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT_VER1); + rc_ecmd |= data.insertFromRight( PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY, PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT, @@ -1326,6 +1406,16 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5( PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT+1)); // pb_cfg_passthru_a_priority + uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT = + (ver2)? + (PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT_VER2): + (PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT_VER1); + + uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT = + (ver2)? + (PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT_VER2): + (PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT_VER1); + rc_ecmd |= data.insertFromRight( PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY, PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT, @@ -1333,6 +1423,16 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5( PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT+1)); // pb_cfg_a_tok_init + uint32_t PB_SCONFIG_WE5_A_TOK_INIT_START_BIT = + (ver2)? + (PB_SCONFIG_WE5_A_TOK_INIT_START_BIT_VER2): + (PB_SCONFIG_WE5_A_TOK_INIT_START_BIT_VER1); + + uint32_t PB_SCONFIG_WE5_A_TOK_INIT_END_BIT = + (ver2)? + (PB_SCONFIG_WE5_A_TOK_INIT_END_BIT_VER2): + (PB_SCONFIG_WE5_A_TOK_INIT_END_BIT_VER1); + rc_ecmd |= data.insertFromRight( PB_SCONFIG_WE5_A_TOK_INIT, PB_SCONFIG_WE5_A_TOK_INIT_START_BIT, @@ -1340,6 +1440,15 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5( PB_SCONFIG_WE5_A_TOK_INIT_START_BIT+1)); // pb_cfg_f_tok_init + uint32_t PB_SCONFIG_WE5_F_TOK_INIT_START_BIT = + (ver2)? + (PB_SCONFIG_WE5_F_TOK_INIT_START_BIT_VER2): + (PB_SCONFIG_WE5_F_TOK_INIT_START_BIT_VER1); + + uint32_t PB_SCONFIG_WE5_F_TOK_INIT_END_BIT = + (ver2)? + (PB_SCONFIG_WE5_F_TOK_INIT_END_BIT_VER2): + (PB_SCONFIG_WE5_F_TOK_INIT_END_BIT_VER1); rc_ecmd |= data.insertFromRight( PB_SCONFIG_WE5_F_TOK_INIT, PB_SCONFIG_WE5_F_TOK_INIT_START_BIT, @@ -1347,24 +1456,65 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5( PB_SCONFIG_WE5_F_TOK_INIT_START_BIT+1)); // pb_cfg_em_fp_enable + uint32_t PB_SCONFIG_WE5_EM_FP_ENABLE_BIT = + (ver2)? + (PB_SCONFIG_WE5_EM_FP_ENABLE_BIT_VER2): + (PB_SCONFIG_WE5_EM_FP_ENABLE_BIT_VER1); + rc_ecmd |= data.writeBit( PB_SCONFIG_WE5_EM_FP_ENABLE_BIT, PB_SCONFIG_WE5_EM_FP_ENABLE?1:0); // spare + uint32_t PB_SCONFIG_WE5_SPARE_START_BIT = + (ver2)? + (PB_SCONFIG_WE5_SPARE_START_BIT_VER2): + (PB_SCONFIG_WE5_SPARE_START_BIT_VER1); + + uint32_t PB_SCONFIG_WE5_SPARE_END_BIT = + (ver2)? + (PB_SCONFIG_WE5_SPARE_END_BIT_VER2): + (PB_SCONFIG_WE5_SPARE_END_BIT_VER1); + rc_ecmd |= data.insertFromRight( PB_SCONFIG_WE5_SPARE, PB_SCONFIG_WE5_SPARE_START_BIT, (PB_SCONFIG_WE5_SPARE_END_BIT- PB_SCONFIG_WE5_SPARE_START_BIT+1)); + // pb_cfg_a_ind_threshold + if (ver2) + { + rc_ecmd |= data.writeBit( + PB_SCONFIG_WE5_A_IND_THRESHOLD_BIT_VER2, + PB_SCONFIG_WE5_A_IND_THRESHOLD?1:0); + } + // pb_cfg_mem_stv_priority + uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT = + (ver2)? + (PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT_VER2): + (PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT_VER1); + + uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT = + (ver2)? + (PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT_VER2): + (PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT_VER1); + rc_ecmd |= data.insertFromRight( PB_SCONFIG_WE5_MEM_STV_PRIORITY, PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT, (PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT- PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT+1)); + // pb_cfg_x_off_set + if (ver2) + { + rc_ecmd |= data.writeBit( + PB_SCONFIG_WE5_X_OFF_SEL_BIT_VER2, + PB_SCONFIG_WE5_X_OFF_SEL?1:0); + } + if (rc_ecmd) { FAPI_ERR("proc_build_smp_set_sconfig_we5: Error 0x%x setting up PB Serial Configuration load register data buffer", @@ -1374,7 +1524,10 @@ fapi::ReturnCode proc_build_smp_set_sconfig_we5( } // call common routine to program chain - rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_WE5_DEF, data); + rc = proc_build_smp_set_sconfig( + i_smp_chip, + (ver2)?(PB_SCONFIG_WE5_DEF_VER2):(PB_SCONFIG_WE5_DEF_VER1), + data); if (!rc.ok()) { FAPI_ERR("proc_build_smp_set_sconfig_we5: Error from proc_build_smp_set_sconfig"); diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H index 03299b2ba..940c05bb7 100644 --- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H +++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_build_smp_fbc_cd.H,v 1.6 2013/05/07 22:10:24 jmcgill Exp $ +// $Id: proc_build_smp_fbc_cd.H,v 1.8 2013/06/20 21:19:05 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.H,v $ //------------------------------------------------------------------------------ // *| @@ -232,7 +232,7 @@ const uint8_t PB_SCONFIG_C9_GP_STARVE_LIMIT = 0x80; const uint8_t PB_SCONFIG_C9_RGP_STARVE_LIMIT = 0x80; const uint8_t PB_SCONFIG_C9_SP_STARVE_LIMIT = 0x80; const uint8_t PB_SCONFIG_C9_FP_STARVE_LIMIT = 0x80; -const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE = 0x1; // RR_ONLY +const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE = 0x0; // LFSR_ONLY const uint8_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE = 0x2; // LFSR_ON_STARVATION_ELSE_RR @@ -410,33 +410,62 @@ const bool PB_SCONFIG_WE1_FP_C2I_SPARE_MODE = false; // spare // PBH_DAT_ARB_EM (east/west, chain #5) field/bit definitions // -const proc_build_smp_sconfig_def PB_SCONFIG_WE5_DEF = { 0x5, 51, false, { true, false, true } }; - -const uint32_t PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT = 13; -const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT = 14; -const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT = 17; -const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT = 18; -const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT = 21; -const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT = 22; -const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT = 25; -const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT = 26; -const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT = 29; -const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT = 30; -const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT = 33; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT = 34; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT = 35; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT = 42; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT = 43; -const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT = 50; -const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_START_BIT = 51; -const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_END_BIT = 54; -const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_START_BIT = 55; -const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_END_BIT = 58; -const uint32_t PB_SCONFIG_WE5_EM_FP_ENABLE_BIT = 59; -const uint32_t PB_SCONFIG_WE5_SPARE_START_BIT = 60; -const uint32_t PB_SCONFIG_WE5_SPARE_END_BIT = 61; -const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT = 62; -const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT = 63; +const proc_build_smp_sconfig_def PB_SCONFIG_WE5_DEF_VER1 = { 0x5, 51, false, { true, false, true } }; +const proc_build_smp_sconfig_def PB_SCONFIG_WE5_DEF_VER2 = { 0x5, 52, false, { true, false, true } }; + +const uint32_t PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT_VER1 = 13; +const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 14; +const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 17; +const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 18; +const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 21; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 22; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 25; +const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 26; +const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 29; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT_VER1 = 30; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT_VER1 = 33; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT_VER1 = 34; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT_VER1 = 35; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT_VER1 = 42; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT_VER1 = 43; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT_VER1 = 50; +const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_START_BIT_VER1 = 51; +const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_END_BIT_VER1 = 54; +const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_START_BIT_VER1 = 55; +const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_END_BIT_VER1 = 58; +const uint32_t PB_SCONFIG_WE5_EM_FP_ENABLE_BIT_VER1 = 59; +const uint32_t PB_SCONFIG_WE5_SPARE_START_BIT_VER1 = 60; +const uint32_t PB_SCONFIG_WE5_SPARE_END_BIT_VER1 = 61; +const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT_VER1 = 62; +const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT_VER1 = 63; + +const uint32_t PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT_VER2 = 12; +const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 13; +const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 16; +const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 17; +const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 20; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 21; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 24; +const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 25; +const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 28; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT_VER2 = 29; +const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT_VER2 = 32; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT_VER2 = 33; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT_VER2 = 34; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT_VER2 = 41; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT_VER2 = 42; +const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT_VER2 = 49; +const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_START_BIT_VER2 = 50; +const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_END_BIT_VER2 = 53; +const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_START_BIT_VER2 = 54; +const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_END_BIT_VER2 = 57; +const uint32_t PB_SCONFIG_WE5_EM_FP_ENABLE_BIT_VER2 = 58; +const uint32_t PB_SCONFIG_WE5_SPARE_START_BIT_VER2 = 59; +const uint32_t PB_SCONFIG_WE5_SPARE_END_BIT_VER2 = 59; +const uint32_t PB_SCONFIG_WE5_A_IND_THRESHOLD_BIT_VER2 = 60; +const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT_VER2 = 61; +const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT_VER2 = 62; +const uint32_t PB_SCONFIG_WE5_X_OFF_SEL_BIT_VER2 = 63; const bool PB_SCONFIG_WE5_LOCK_ON_LINKS = true; // lock const uint8_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD = 0x4; // cnt_4 @@ -453,6 +482,8 @@ const bool PB_SCONFIG_WE5_EM_FP_ENABLE = true; // enable const uint8_t PB_SCONFIG_WE5_SPARE = 0x0; // spare const uint8_t PB_SCONFIG_WE5_MEM_STV_PRIORITY = 0x2; // stv +const uint8_t PB_SCONFIG_WE5_A_IND_THRESHOLD = 0x0; // gt4 +const uint8_t PB_SCONFIG_WE5_X_OFF_SEL = 0x0; // disable extern "C" { diff --git a/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit_errors.xml b/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit_errors.xml index df6234576..162e7363d 100644 --- a/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit_errors.xml +++ b/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit_errors.xml @@ -20,9 +20,11 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: cen_dmi_scominit_errors.xml,v 1.3 2013/06/25 15:37:38 cswenson Exp $ --> <!-- Error definitions for cen_dmi_scominit procedure --> <hwpErrors> <!-- *********************************************************************** --> + <!-- $Id: cen_dmi_scominit_errors.xml,v 1.3 2013/06/25 15:37:38 cswenson Exp $ --> <hwpError> <rc>RC_CEN_DMI_SCOMINIT_INVALID_TARGET</rc> <description>Invalid target type presented to cen_dmi_scominit HWP (expects TARGET_TYPE_MEMBUF_CHIP).</description> diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock_errors.xml b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock_errors.xml index 39b4ce147..6d377ec69 100644 --- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock_errors.xml +++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock_errors.xml @@ -1,25 +1,26 @@ -<!-- IBM_PROLOG_BEGIN_TAG - This is an automatically generated prolog. - - $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock_errors.xml $ - - IBM CONFIDENTIAL - - COPYRIGHT International Business Machines Corp. 2012 - - p1 - - Object Code Only (OCO) source materials - Licensed Internal Code Source Materials - IBM HostBoot Licensed Internal Code - - The source code for this program is not published or other- - wise divested of its trade secrets, irrespective of what has - been deposited with the U.S. Copyright Office. - - Origin: 30 - - IBM_PROLOG_END --> +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_cen_framelock_errors.xml,v 1.4 2013/06/25 15:38:24 cswenson Exp $ --> <!-- Error definitions for proc_cen_framelock procedure --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit_errors.xml b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit_errors.xml index af4657ba6..d09cbac1f 100644 --- a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit_errors.xml +++ b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit_errors.xml @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_dmi_scominit_errors.xml,v 1.2 2013/06/25 15:38:26 cswenson Exp $ --> <!-- Error definitions for proc_dmi_scominit procedure --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config_errors.xml b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config_errors.xml index 53cb33dbc..c3508cb4e 100644 --- a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config_errors.xml +++ b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_pcie_config_errors.xml,v 1.2 2013/06/25 15:38:30 cswenson Exp $ --> <!-- Error definitions for proc_pcie_config --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/memory_mss_setup_bars.xml b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/memory_mss_setup_bars.xml new file mode 100644 index 000000000..cdfaa947d --- /dev/null +++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/memory_mss_setup_bars.xml @@ -0,0 +1,51 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/memory_mss_setup_bars.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_setup_bars.xml,v 1.1 2013/06/19 18:28:30 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_setup_bars.C --> +<!-- // *! OWNER NAME : Girisankar Paulraj Email: gpaulraj@in.ibm.com --> +<!-- // *! OWNER NAME : Mark Bellows Email: bellows@us.ibm.com --> + +<!-- Original Source for RC_MSS_SETUP_BARS_NM_ALT_BAR_ERR memory_errors.xml --> + <hwpError> + <rc>RC_MSS_SETUP_BARS_NM_ALT_BAR_ERR</rc> + <description>Invalid non-mirrored alternate BAR configuration.</description> + </hwpError> + +<!-- Original Source for RC_MSS_SETUP_BARS_M_ALT_BAR_ERR memory_errors.xml --> + <hwpError> + <rc>RC_MSS_SETUP_BARS_M_ALT_BAR_ERR</rc> + <description>Invalid mirrored alternate BAR configuration.</description> + </hwpError> + +<!-- Original Source for RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR memory_errors.xml --> + <hwpError> + <rc>RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR</rc> + <description>MCS is listed as a member in multiple groups.</description> + <ffdc>MCS_POS</ffdc> + <ffdc>GROUP_INDEX_A</ffdc> + <ffdc>GROUP_INDEX_B</ffdc> + </hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_training/mem_startclocks/memory_cen_stopclocks.xml b/src/usr/hwpf/hwp/dram_training/mem_startclocks/memory_cen_stopclocks.xml new file mode 100644 index 000000000..1e572252b --- /dev/null +++ b/src/usr/hwpf/hwp/dram_training/mem_startclocks/memory_cen_stopclocks.xml @@ -0,0 +1,37 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/dram_training/mem_startclocks/memory_cen_stopclocks.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_cen_stopclocks.xml,v 1.1 2013/06/19 18:27:32 bellows Exp $ --> +<!-- For file ../../ipl/fapi/cen_stopclocks.C --> +<!-- // *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com --> +<!-- // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com --> + +<!-- Original Source for RC_MSS_UNEXPECTED_CLOCK_STATUS memory_errors.xml --> + <hwpError> + <rc>RC_MSS_UNEXPECTED_CLOCK_STATUS</rc> + <description>Unexpected clock status! See previous error message for details.</description> +</hwpError> + +<!-- Add some header comments for BACKUP and SCREEN. --> + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_training/memory_errors.xml b/src/usr/hwpf/hwp/dram_training/memory_errors.xml index cf0704487..3b82da84b 100644 --- a/src/usr/hwpf/hwp/dram_training/memory_errors.xml +++ b/src/usr/hwpf/hwp/dram_training/memory_errors.xml @@ -21,46 +21,11 @@ <!-- --> <!-- IBM_PROLOG_END_TAG --> <hwpErrors> -<!-- $Id: memory_errors.xml,v 1.39 2013/05/20 16:51:14 gollub Exp $ --> +<!-- $Id: memory_errors.xml,v 1.41 2013/06/19 18:27:28 bellows Exp $ --> <!-- EDIT THIS FILE DIRECTLY. THE ODS FILE METHOD IS NO LONGER VALID --> <!-- *********************************************************************** --> <hwpError> - <rc>RC_MSS_RCD_PARITY_ERROR_PORT0</rc> - <description>An rcd parity error has been registered on port_0</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_RCD_PARITY_ERROR_PORT1</rc> - <description>An rcd parity error has been registered on port_1</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_RCD_PARITY_ERROR_LIMIT</rc> - <description>The number of rcd parity errors have exceeded the maximum allowable number</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_CCS_HUNG</rc> - <description>The ccs failed to return from in_progress status and failed to describe an error further.</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_CCS_READ_MISCOMPARE</rc> - <description>The ccs errors at runtime and registers a read miscompare.</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_CCS_UE_SUE</rc> - <description>The ccs errors at runtime and registers a UE or SUE</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_CCS_CAL_TIMEOUT</rc> - <description>The ccs errors at runtime and registers a calibration operation timeout</description> -</hwpError> - - <hwpError> <rc>RC_MSS_PLACE_HOLDER_ERROR</rc> <description>Not for production code. This return code is used for cases where the error code has not been approved yet. Eventually, no code should use this error code.</description> </hwpError> @@ -71,11 +36,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_EFF_CONFIG_RC_ERROR_001A</rc> - <description>Plug rule violation in EFF_CONFIG.</description> -</hwpError> - - <hwpError> <rc>RC_MSS_UNEXPECTED_MEM_CLK_STATUS</rc> <description>A read of the memory clock status register returned an unexpected value. </description> </hwpError> @@ -131,26 +91,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_DP18_0_PLL_FAILED_TO_LOCK</rc> - <description>DP18 0x0C000 PLL failed to lock! See lock status register at address: 0x8000C0000301143F</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_DP18_1_PLL_FAILED_TO_LOCK</rc> - <description>DP18 0x1C000 PLL failed to lock! See lock status register at address: 0x8001C0000301143F</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_AD32S_0_PLL_FAILED_TO_LOCK</rc> - <description>AD32S 0x0C001 PLL failed to lock! See lock status register at address: 0x8000C0010301143F</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_AD32S_1_PLL_FAILED_TO_LOCK</rc> - <description>AD32S 0x1C001 PLL failed to lock! See lock status register at address: 0x8001C0010301143F</description> -</hwpError> - - <hwpError> <rc>RC_MSS_GENERAL_PUTSCOM_ERROR</rc> <description>PutScom failed! See previous error message for details.</description> </hwpError> @@ -161,11 +101,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_UNEXPECTED_CLOCK_STATUS</rc> - <description>Unexpected clock status! See previous error message for details.</description> -</hwpError> - - <hwpError> <rc>RC_MSS_UNEXPECTED_FIR_STATUS</rc> <description>Unexpected FIR status! See previous error message for details.</description> </hwpError> @@ -176,22 +111,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE</rc> - <description>Unsupported DIMM type found. All dimms must be DDR3 or DDR4</description> - <ffdc>DEVICE_TYPE</ffdc> -</hwpError> - - <hwpError> - <rc>RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED</rc> - <description>Mixing of DDR3 and DDR4 not supported.</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE</rc> - <description>One or more DIMMs do not support required voltage for DDR type.</description> -</hwpError> - - <hwpError> <rc>RC_MSS_GENERAL_SIMSTKFAC_ERROR</rc> <description>simSTKFAC failed! See previous error message for details</description> </hwpError> @@ -206,148 +125,6 @@ <description>Failed to get simulation hierarchy from eCmd target.</description> </hwpError> - <hwpError> - <rc>RC_MSS_UNSUPPORTED_FREQ_CALCULATED</rc> - <description>The frequency calculated with spd data is not supported by the jedec standards.</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR</rc> - <description>MCS is listed as a member in multiple groups.</description> - <ffdc>MCS_POS</ffdc> - <ffdc>GROUP_INDEX_A</ffdc> - <ffdc>GROUP_INDEX_B</ffdc> - </hwpError> - - <hwpError> - <rc>RC_MSS_SETUP_BARS_NM_ALT_BAR_ERR</rc> - <description>Invalid non-mirrored alternate BAR configuration.</description> - </hwpError> - - <hwpError> - <rc>RC_MSS_SETUP_BARS_M_ALT_BAR_ERR</rc> - <description>Invalid mirrored alternate BAR configuration.</description> - </hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_START_NOT_RESET</rc> - <description>MBMCCQ[0]: maint_cmd_start not reset by hw.</description> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBMCC</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- FFDC: MBMCT[0:4] contains the cmd type set in hw --> - <ffdc>MBMCT</ffdc> - <!-- Callout MBA HIGH --> - <callout><target>MBA</target><priority>HIGH</priority></callout> - <!-- Deconfigure MBA --> - <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MBA --> - <gard><target>MBA</target></gard> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_STOP_NOT_RESET</rc> - <description>MBMCCQ[1]: maint_cmd_stop not reset by hw.</description> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBMCC</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- FFDC: MBMCT[0:4] contains the cmd type previously run --> - <ffdc>MBMCT</ffdc> - <!-- Callout MBA HIGH --> - <callout><target>MBA</target><priority>HIGH</priority></callout> - <!-- Deconfigure MBA --> - <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MBA --> - <gard><target>MBA</target></gard> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_CMD_IN_PROGRESS</rc> - <description>MBMSRQ[0]: Can't start new cmd if previous cmd still in progress.</description> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBMSR</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- FFDC: MBMCT[0:4] contains the cmd type previously run --> - <ffdc>MBMCT</ffdc> - <!-- TODO: Callout FW HIGH --> - <!-- Callout MBA LOW --> - <callout><target>MBA</target><priority>LOW</priority></callout> - <!-- Deconfigure MBA --> - <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MBA --> - <gard><target>MBA</target></gard> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_NO_MEM_CNFG</rc> - <description>MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBAXCR</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_CCS_MUX_NOT_MAINLINE</rc> - <description>CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>CCS_MODE</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_ECC_DISABLED</rc> - <description>MBSECC[0] non zero, meaning ECC check/correct disabled.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBSECC</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_INVALID_CMD</rc> - <description>MBAFIRQ[0], invalid_maint_cmd.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBAFIR</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- FFDC: MBMCT[0:4] contains the cmd type set in hw --> - <ffdc>MBMCT</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_INVALID_ADDR</rc> - <description>MBAFIRQ[1], cmd started with invalid_maint_address.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBAFIR</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- FFDC: MBMCT[0:4] contains the cmd type set in hw --> - <ffdc>MBMCT</ffdc> - <!-- Collect registers as FFDC --> - <collectRegisterFfdc> - <id>REG_FFDC_INVALID_ADDR</id> - <target>MBA</target> - </collectRegisterFfdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - <registerFfdc> <id>REG_FFDC_INVALID_ADDR</id> <scomRegister>MBA01_MBMACAQ_0x0301060D</scomRegister> @@ -355,31 +132,6 @@ <scomRegister>MBA01_MBA_MCBERRPTQ_0x030106e7</scomRegister> </registerFfdc> - - <hwpError> - <rc>RC_MSS_MAINT_CMD_TIMEOUT</rc> - <description>Maint cmd timeout.</description> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- Collect MBA registers as FFDC --> - <collectRegisterFfdc> - <id>REG_FFDC_CMD_TIMEOUT_MBA_REGS</id> - <target>MBA</target> - </collectRegisterFfdc> - <!-- Collect MBS registers as FFDC --> - <collectRegisterFfdc> - <id>REG_FFDC_CMD_TIMEOUT_MBS_REGS</id> - <target>CENTAUR</target> - </collectRegisterFfdc> - <!-- TODO: Callout FW HIGH --> - <!-- Callout MBA LOW --> - <callout><target>MBA</target><priority>LOW</priority></callout> - <!-- Deconfigure MBA --> - <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MBA --> - <gard><target>MBA</target></gard> -</hwpError> - <registerFfdc> <id>REG_FFDC_CMD_TIMEOUT_MBA_REGS</id> <!-- MBA Maintenance Command Type Register --> @@ -434,363 +186,11 @@ </registerFfdc> <hwpError> - <rc>RC_MSS_MAINT_ZERO_DDR_FREQ</rc> - <description>ATTR_MSS_FREQ set to zero so can't calculate scrub rate.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH</rc> - <description>Invalid dramSize or dramWidth in MBAXCRn.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBAXCR</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_INVALID_DIMM_CNFG</rc> - <description>MBAXCRn configured with invalid combination of configType, configSubType, slotConfig.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBAXCR</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_X4_SYMBOL_ON_READ</rc> - <description>Symbol mark not allowed in x4 mode.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width (should be x4) --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading markstore for --> - <ffdc>RANK</ffdc> - <!-- FFDC: Markstore with non-zero symbol entry --> - <ffdc>MARKSTORE</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_INVALID_MARKSTORE</rc> - <description>Invalid galois field in markstore.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading markstore for --> - <ffdc>RANK</ffdc> - <!-- FFDC: Markstore with invalid galois field --> - <ffdc>MARKSTORE</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_X4_SYMBOL_ON_WRITE</rc> - <description>Symbol mark not allowed in x4 mode.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width (should be x4) --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading markstore for --> - <ffdc>RANK</ffdc> - <!-- FFDC: Symbol mark we are trying to write to markstore --> - <ffdc>SYMBOL_MARK</ffdc> - <!-- FFDC: Chip mark we are trying to write to markstore --> - <ffdc>CHIP_MARK</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_INVALID_SYMBOL_INDEX</rc> - <description>Symbol index out of range.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading markstore for --> - <ffdc>RANK</ffdc> - <!-- FFDC: Symbol mark we are trying to write to markstore --> - <ffdc>SYMBOL_MARK</ffdc> - <!-- FFDC: Chip mark we are trying to write to markstore --> - <ffdc>CHIP_MARK</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_INVALID_CHIP_INDEX</rc> - <description>Not first symbol index of a chip.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading markstore for --> - <ffdc>RANK</ffdc> - <!-- FFDC: Symbol mark we are trying to write to markstore --> - <ffdc>SYMBOL_MARK</ffdc> - <!-- FFDC: Chip mark we are trying to write to markstore --> - <ffdc>CHIP_MARK</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED</rc> - <description>Markstore write may have been blocked due to MPE FIR set.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading markstore for --> - <ffdc>RANK</ffdc> - <!-- FFDC: Symbol mark we are trying to write to markstore --> - <ffdc>SYMBOL_MARK</ffdc> - <!-- FFDC: Chip mark we are trying to write to markstore --> - <ffdc>CHIP_MARK</ffdc> - <!-- FFDC: MBECCFIR showing MPE --> - <ffdc>MBECCFIR</ffdc> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_INVALID_STEER_MUX</rc> - <description>Steer mux index out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading steer mux for --> - <ffdc>RANK</ffdc> - <!-- FFDC: MUX_TYPE: read or write --> - <ffdc>MUX_TYPE</ffdc> - <!-- FFDC: Capture steer mux --> - <ffdc>STEER_MUX</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER</rc> - <description>Trying to steer invalid symbol.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading steer mux for --> - <ffdc>RANK</ffdc> - <!-- FFDC: MUX_TYPE: read or write --> - <ffdc>MUX_TYPE</ffdc> - <!-- FFDC: STEER_TYPE: port0, port1, or ecc spare --> - <ffdc>STEER_TYPE</ffdc> - <!-- FFDC: SYMBOL: Symbol we are trying to steer --> - <ffdc>SYMBOL</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_NO_X8_ECC_SPARE</rc> - <description>Invalid to use ECC spare in x8 mode.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading steer mux for --> - <ffdc>RANK</ffdc> - <!-- FFDC: MUX_TYPE: read or write --> - <ffdc>MUX_TYPE</ffdc> - <!-- FFDC: STEER_TYPE: port0, port1, or ecc spare --> - <ffdc>STEER_TYPE</ffdc> - <!-- FFDC: SYMBOL: Symbol we are trying to steer --> - <ffdc>SYMBOL</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_NO_UE_TRAP</rc> - <description>IPL UE trapping didn't work.</description> - <!-- FFDC: Capture UE trap contents --> - <ffdc>UE_TRAP0</ffdc> - <ffdc>UE_TRAP1</ffdc> - <!-- FFDC: MBMCT[0:4] contains the cmd type --> - <ffdc>MBMCT</ffdc> - <!-- FFDC: MBMMR[4:7] contains the pattern index --> - <ffdc>MBMMR</ffdc> - <!-- FFDC: MBSTR[59]: UE trap enable bit --> - <ffdc>MBSTR</ffdc> - <!-- Callout MBA HIGH --> - <callout><target>MBA</target><priority>HIGH</priority></callout> - <!-- Deconfigure MBA --> - <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MBA --> - <gard><target>MBA</target></gard> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_GET_ADDRESS_RANGE_BAD_INPUT</rc> - <description>i_rank input to mss_get_address_range out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: RANK we are trying to get address range for --> - <ffdc>RANK</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_GET_MARK_STORE_BAD_INPUT</rc> - <description>i_rank input to mss_get_mark_store out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: RANK we are trying read markstore for --> - <ffdc>RANK</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_PUT_MARK_STORE_BAD_INPUT</rc> - <description>i_rank input to mss_put_mark_store out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: RANK we are trying write markstore for --> - <ffdc>RANK</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_GET_STEER_MUX_BAD_INPUT</rc> - <description>i_rank or i_muxType input to mss_get_steer_mux out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: RANK we are reading steer mux for --> - <ffdc>RANK</ffdc> - <!-- FFDC: MUX_TYPE: read or write --> - <ffdc>MUX_TYPE</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_PUT_STEER_MUX_BAD_INPUT</rc> - <description>i_rank or i_muxType or i_steerType or i_symbol input to mss_put_steer_mux out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: RANK we are writing steer mux for --> - <ffdc>RANK</ffdc> - <!-- FFDC: MUX_TYPE: read or write --> - <ffdc>MUX_TYPE</ffdc> - <!-- FFDC: STEER_TYPE: port0 spare, port1 spare or ecc spare --> - <ffdc>STEER_TYPE</ffdc> - <!-- FFDC: SYMBOL: 0-71 --> - <ffdc>SYMBOL</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_DO_STEER_INPUT_OUT_OF_RANGE</rc> - <description>i_rank or i_symbol input to mss_do_steer out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: RANK we are writing steer mux for --> - <ffdc>RANK</ffdc> - <!-- FFDC: SYMBOL: 0-71 --> - <ffdc>SYMBOL</ffdc> - <!-- FFDC: X4ECCSPARE: true or false --> - <ffdc>X4ECCSPARE</ffdc> - <!-- TODO: Callout FW HIGH --> -</hwpError> - - <hwpError> - <rc>RC_MSS_MAINT_UNSUCCESSFUL_FORCED_MAINT_CMD_STOP</rc> - <description>MBMSRQ[0] = 1, unsuccessful forced maint cmd stop.</description> - <!-- FFDC: Capture register we used to stop cmd --> - <ffdc>MBMCC</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBMSR</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- Callout MBA HIGH --> - <callout><target>MBA</target><priority>HIGH</priority></callout> - <!-- Deconfigure MBA --> - <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MBA --> - <gard><target>MBA</target></gard> -</hwpError> - - - <hwpError> - <rc>RC_MSS_MEMDIAGS_RESTORE_REPAIRS_EXCEEDED</rc> - <description>FATAL: Memdiags exiting with error before running patterns, due to DRAM repairs exceeded.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> -</hwpError> - - <hwpError> - <rc>RC_MSS_MEMDIAGS_UE_OR_SUE_IN_LAST_PATTERN</rc> - <description>FATAL: Memdiags exiting with error due to UE, or SUE(in last pattern).</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> -</hwpError> - - - <hwpError> - <rc>RC_MSS_UNSUPPORTED_SPD_DATA</rc> - <description>Invalid SPD data returned.</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_NO_COMMON_SUPPORTED_CL</rc> - <description>Current Configuration has no common supported CL Values.</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_EXCEED_TAA_MAX_NO_CL</rc> - <description>Exceeded TAA MAX with Lowest frequency. No compatable CL.</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_MODULE_TYPE_MIX</rc> - <description>Differing DIMM types in the same configuration.</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_NUM_MBA_ERROR</rc> - <description>Less than 2 MBA's returned by fapiGetChildChiplets</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_SLEW_CAL_ERROR</rc> - <description>Slew calibration error occurred.</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_FREQ</rc> - <description>MSS_FREQ attribute equals 0.</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_INVALID_DRAM_GEN</rc> - <description>DRAM_GEN attribute is not valid; equals 0 for empty.</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_IMP_INPUT_ERROR</rc> - <description>Impedance is invalid for driver/receiver type.</description> -</hwpError> - - <hwpError> <rc>RC_MSS_INVALID_FN_INPUT_ERROR</rc> <description>An input to FN call is out of range.</description> </hwpError> <hwpError> - <rc>RC_MSS_MCBIST_TIMEOUT_ERROR</rc> - <description>Timeout on MCBIST configuration register polling.</description> -</hwpError> - - <hwpError> <rc>RC_MSS_MCBIST_ERROR</rc> <description>MCBIST operation failed</description> </hwpError> @@ -825,82 +225,12 @@ <description>TBD</description> </hwpError> - <hwpError> - <rc>RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION</rc> - <description>One or more DIMMs classified non-functional has a tolerated voltage below selected voltage.</description> - <!-- Deconfigure MASTER_CHIP --> - <deconfigure><target>MASTER_CHIP</target></deconfigure> -</hwpError> - - <hwpError> - <rc>RC_MSS_DRAMINIT_TRAINING_INIT_CAL_STALLED</rc> - <description>One or more Rank Pairs Stalled Init Cal within Draminit_training</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_DRAMINIT_TRAINING_INIT_CAL_FAILED</rc> - <description>One or more Rank Pairs Failed Init Cal within Draminit_training</description> -</hwpError> - - <hwpError> - <rc>RC_MSS_DIMM_POWER_CURVE_DATA_LAB</rc> - <description>DIMM power curve data is lab data not MSL</description> - <ffdc>FFDC_DATA_1</ffdc> - <ffdc>FFDC_DATA_2</ffdc> - <ffdc>FFDC_DATA_3</ffdc> - <ffdc>FFDC_DATA_4</ffdc> - <callout><target>MEM_CHIP</target><priority>HIGH</priority></callout> -</hwpError> - - <hwpError> - <rc>RC_MSS_DIMM_POWER_CURVE_DATA_INVALID</rc> - <description>DIMM power curve data is invalid</description> - <ffdc>FFDC_DATA_1</ffdc> - <ffdc>FFDC_DATA_2</ffdc> - <ffdc>FFDC_DATA_3</ffdc> - <ffdc>FFDC_DATA_4</ffdc> - <callout><target>MEM_CHIP</target><priority>HIGH</priority></callout> -</hwpError> - - <hwpError> - <rc>RC_MSS_DIMM_NOT_FOUND_IN_POWER_TABLE</rc> - <description>Unable to find matching entry in DIMM power table</description> - <ffdc>FFDC_DATA_1</ffdc> - <ffdc>FFDC_DATA_2</ffdc> - <ffdc>FFDC_DATA_3</ffdc> - <callout><target>MEM_DIMM</target><priority>HIGH</priority></callout> -</hwpError> - - <hwpError> - <rc>RC_MSS_NOT_ENOUGH_AVAILABLE_DIMM_POWER</rc> - <description>Unable to find throttle setting that has DIMM power underneath the limit. Callout Firmware.</description> - <ffdc>MEM_CHIP</ffdc> - <ffdc>FFDC_DATA_1</ffdc> - <ffdc>FFDC_DATA_2</ffdc> - <ffdc>FFDC_DATA_3</ffdc> - <ffdc>FFDC_DATA_4</ffdc> - <ffdc>FFDC_DATA_5</ffdc> - <!-- TODO: callout firmware --> -</hwpError> - <hwpError> <rc>RC_MSS_INPUT_ERROR</rc> <description>Invalid input </description> </hwpError> <hwpError> - <rc>RC_MSS_NON_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE</rc> - <description>FABRIC IS IN NON-CHECKER BOARD MODE. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '2MCS/GROUP, 4MCS/GROUP AND 8MCS/GROUP'. OR ENABLE CHECKER BOARD, TO SUPPORT '1MCS/GROUP'. MRW NEEDS TO BE UPDATED. </description> - <collectFfdc>hwpCollectMemGrouping, PROC_CHIP</collectFfdc> -</hwpError> - -<hwpError> - <rc>RC_MSS_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE</rc> - <description>FABRIC IS IN CHECKER BOARD MODE BUT IT DOES NOT SUPPORT 1MCS/GROUP. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '1MCS/GROUP'. OR DISABLE CHECKER BOARD, TO SUPPORT '2MCS/GROUP, 4MCS/GROUP AND 8MCS/GROUP'. MRW NEEDS TO BE UPDATED. </description> - <collectFfdc>hwpCollectMemGrouping, PROC_CHIP</collectFfdc> -</hwpError> - -<hwpError> <rc>RC_MSS_UNABLE_TO_GROUP_MCS</rc> <description>MCS COULD NOT BE GROUPED. EITHER SWITCH DIMMS SO GROUPING IS POSSIBLE OR CHANGE SYSTEM POLICY.</description> <gard><target>TARGET_MCS</target></gard> @@ -929,17 +259,6 @@ </hwpError> <hwpError> - <rc>RC_MSS_UNABLE_TO_GROUP_SUMMARY</rc> - <description>MCS COULD NOT BE GROUPED. SEE PREVIOUS ERROR MESSAGES FOR WHICH MCS HAS BEEN RC_MSS_UNABLE_TO_GROUP_MCS</description> -</hwpError> - -<hwpError> - <rc>RC_MSS_BASE_ADDRESS_OVERLAPS_MIRROR_ADDRESS</rc> - <description>MIRROR BASE ADDRESS OVERLAPS WITH MEMORY BASE ADDRESS.</description> - <collectFfdc>hwpCollectMemGrouping, PROC_CHIP</collectFfdc> -</hwpError> - -<hwpError> <rc>RC_ERROR_MSS_FIRS</rc> <description>MEM FIR REGISTERS</description> @@ -986,11 +305,9 @@ <target>CENCHIP_MBA</target> </collectRegisterFfdc> - </hwpError> - <registerFfdc> <id>REG_FFDC_MBA_FIR_REGS</id> @@ -1074,7 +391,6 @@ <scomRegister>PHY01_DDRPHY_FIR_WOF_REG_0x800200980301143fULL</scomRegister> </registerFfdc> - <registerFfdc> <id>REG_FFDC_DMI_FIR_REGS</id> <scomRegister>CEN_DMIFIR_0x02010400</scomRegister> diff --git a/src/usr/hwpf/hwp/dram_training/memory_mss_funcs.xml b/src/usr/hwpf/hwp/dram_training/memory_mss_funcs.xml new file mode 100644 index 000000000..7eb182b48 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_training/memory_mss_funcs.xml @@ -0,0 +1,72 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/dram_training/memory_mss_funcs.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_funcs.xml,v 1.1 2013/06/19 18:28:11 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_funcs.C --> +<!-- // *! OWNER NAME : jdsloat@us.ibm.com --> +<!-- // *! BACKUP NAME : --> + +<!-- Original Source for RC_MSS_CCS_READ_MISCOMPARE memory_errors.xml --> + <hwpError> + <rc>RC_MSS_CCS_READ_MISCOMPARE</rc> + <description>The ccs errors at runtime and registers a read miscompare.</description> +</hwpError> + +<!-- Original Source for RC_MSS_CCS_UE_SUE memory_errors.xml --> + <hwpError> + <rc>RC_MSS_CCS_UE_SUE</rc> + <description>The ccs errors at runtime and registers a UE or SUE</description> +</hwpError> + +<!-- Original Source for RC_MSS_CCS_CAL_TIMEOUT memory_errors.xml --> + <hwpError> + <rc>RC_MSS_CCS_CAL_TIMEOUT</rc> + <description>The ccs errors at runtime and registers a calibration operation timeout</description> +</hwpError> + +<!-- Original Source for RC_MSS_CCS_HUNG memory_errors.xml --> + <hwpError> + <rc>RC_MSS_CCS_HUNG</rc> + <description>The ccs failed to return from in_progress status and failed to describe an error further.</description> +</hwpError> + +<!-- Original Source for RC_MSS_RCD_PARITY_ERROR_LIMIT memory_errors.xml --> + <hwpError> + <rc>RC_MSS_RCD_PARITY_ERROR_LIMIT</rc> + <description>The number of rcd parity errors have exceeded the maximum allowable number</description> +</hwpError> + +<!-- Original Source for RC_MSS_RCD_PARITY_ERROR_PORT0 memory_errors.xml --> + <hwpError> + <rc>RC_MSS_RCD_PARITY_ERROR_PORT0</rc> + <description>An rcd parity error has been registered on port_0</description> +</hwpError> + +<!-- Original Source for RC_MSS_RCD_PARITY_ERROR_PORT1 memory_errors.xml --> + <hwpError> + <rc>RC_MSS_RCD_PARITY_ERROR_PORT1</rc> + <description>An rcd parity error has been registered on port_1</description> +</hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_training/memory_mss_termination_control.xml b/src/usr/hwpf/hwp/dram_training/memory_mss_termination_control.xml new file mode 100644 index 000000000..05b2091cc --- /dev/null +++ b/src/usr/hwpf/hwp/dram_training/memory_mss_termination_control.xml @@ -0,0 +1,54 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/dram_training/memory_mss_termination_control.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_termination_control.xml,v 1.1 2013/06/19 18:28:31 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_termination_control.C --> +<!-- // *! OWNER NAME : Saravanan Sethuraman email ID:saravanans@in.ibm.com --> +<!-- // *! BACKUP NAME: Menlo Wuu email ID:menlowuu@us.ibm.com --> + +<!-- Original Source for RC_MSS_IMP_INPUT_ERROR memory_errors.xml --> + <hwpError> + <rc>RC_MSS_IMP_INPUT_ERROR</rc> + <description>Impedance is invalid for driver/receiver type.</description> +</hwpError> + +<!-- Original Source for RC_MSS_INVALID_DRAM_GEN memory_errors.xml --> + <hwpError> + <rc>RC_MSS_INVALID_DRAM_GEN</rc> + <description>DRAM_GEN attribute is not valid; equals 0 for empty.</description> +</hwpError> + +<!-- Original Source for RC_MSS_INVALID_FREQ memory_errors.xml --> + <hwpError> + <rc>RC_MSS_INVALID_FREQ</rc> + <description>MSS_FREQ attribute equals 0.</description> +</hwpError> + +<!-- Original Source for RC_MSS_SLEW_CAL_ERROR memory_errors.xml --> + <hwpError> + <rc>RC_MSS_SLEW_CAL_ERROR</rc> + <description>Slew calibration error occurred.</description> +</hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/memory_mss_ddr_phy_reset.xml b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/memory_mss_ddr_phy_reset.xml new file mode 100644 index 000000000..9e1c7abfc --- /dev/null +++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/memory_mss_ddr_phy_reset.xml @@ -0,0 +1,54 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/memory_mss_ddr_phy_reset.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_ddr_phy_reset.xml,v 1.1 2013/06/19 18:27:43 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_ddr_phy_reset.C --> +<!-- // *! OWNER NAME : Mark Fredrickson Email: mfred@us.ibm.com --> +<!-- // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com --> + +<!-- Original Source for RC_MSS_DP18_0_PLL_FAILED_TO_LOCK memory_errors.xml --> + <hwpError> + <rc>RC_MSS_DP18_0_PLL_FAILED_TO_LOCK</rc> + <description>DP18 0x0C000 PLL failed to lock! See lock status register at address: 0x8000C0000301143F</description> +</hwpError> + +<!-- Original Source for RC_MSS_DP18_1_PLL_FAILED_TO_LOCK memory_errors.xml --> + <hwpError> + <rc>RC_MSS_DP18_1_PLL_FAILED_TO_LOCK</rc> + <description>DP18 0x1C000 PLL failed to lock! See lock status register at address: 0x8001C0000301143F</description> +</hwpError> + +<!-- Original Source for RC_MSS_AD32S_0_PLL_FAILED_TO_LOCK memory_errors.xml --> + <hwpError> + <rc>RC_MSS_AD32S_0_PLL_FAILED_TO_LOCK</rc> + <description>AD32S 0x0C001 PLL failed to lock! See lock status register at address: 0x8000C0010301143F</description> +</hwpError> + +<!-- Original Source for RC_MSS_AD32S_1_PLL_FAILED_TO_LOCK memory_errors.xml --> + <hwpError> + <rc>RC_MSS_AD32S_1_PLL_FAILED_TO_LOCK</rc> + <description>AD32S 0x1C001 PLL failed to lock! See lock status register at address: 0x8001C0010301143F</description> +</hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_mcbist_common.xml b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_mcbist_common.xml new file mode 100644 index 000000000..357a2ce77 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_mcbist_common.xml @@ -0,0 +1,36 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/memory_mss_mcbist_common.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_mcbist_common.xml,v 1.1 2013/06/19 18:28:22 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_mcbist_common.C --> +<!-- // *! OWNER NAME : Devashikamani, Aditya Email: adityamd@in.ibm.com --> +<!-- // *! BACKUP : Sethuraman, Saravanan Email: saravanans@in.ibm.com --> + +<!-- Original Source for RC_MSS_MCBIST_TIMEOUT_ERROR memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MCBIST_TIMEOUT_ERROR</rc> + <description>Timeout on MCBIST configuration register polling.</description> +</hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/memory_mss_draminit_training.xml b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/memory_mss_draminit_training.xml new file mode 100644 index 000000000..5b9bf15da --- /dev/null +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/memory_mss_draminit_training.xml @@ -0,0 +1,40 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/memory_mss_draminit_training.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_draminit_training.xml,v 1.1 2013/06/19 18:27:49 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_draminit_training.C --> + +<!-- Original Source for RC_MSS_DRAMINIT_TRAINING_INIT_CAL_STALLED memory_errors.xml --> + <hwpError> + <rc>RC_MSS_DRAMINIT_TRAINING_INIT_CAL_STALLED</rc> + <description>One or more Rank Pairs Stalled Init Cal within Draminit_training</description> +</hwpError> + +<!-- Original Source for RC_MSS_DRAMINIT_TRAINING_INIT_CAL_FAILED memory_errors.xml --> + <hwpError> + <rc>RC_MSS_DRAMINIT_TRAINING_INIT_CAL_FAILED</rc> + <description>One or more Rank Pairs Failed Init Cal within Draminit_training</description> +</hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/memory_mss_scominit.xml b/src/usr/hwpf/hwp/dram_training/mss_scominit/memory_mss_scominit.xml new file mode 100644 index 000000000..98d384bf9 --- /dev/null +++ b/src/usr/hwpf/hwp/dram_training/mss_scominit/memory_mss_scominit.xml @@ -0,0 +1,36 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/dram_training/mss_scominit/memory_mss_scominit.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_scominit.xml,v 1.1 2013/06/19 18:28:26 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_scominit.C --> +<!-- // *! OWNER NAME : Menlo Wuu Email: menlowuu@us.ibm.com --> +<!-- // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com --> + +<!-- Original Source for RC_MSS_NUM_MBA_ERROR memory_errors.xml --> + <hwpError> + <rc>RC_MSS_NUM_MBA_ERROR</rc> + <description>Less than 2 MBA's returned by fapiGetChildChiplets</description> +</hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C index b94b5fbdd..689dc7672 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C +++ b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012 */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_scominit.C,v 1.15 2012/11/12 03:08:50 mwuu Exp $ +// $Id: mss_scominit.C,v 1.17 2013/07/02 21:05:23 mwuu Exp $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -41,6 +41,8 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.17 | menlowuu |02-JUL-13| Fixed vector insert for L4 targets +// 1.16 | menlowuu |02-JUL-13| Added L4 targets for MBS initfile // 1.15 | menlowuu |11-NOV-12| Removed include of dimmBadDqBitmapFuncs.H> // 1.14 | menlowuu |09-NOV-12| Removed mss_set_bbm_regs FN since now handled // in draminit_training. @@ -91,7 +93,7 @@ extern "C" { ReturnCode mss_scominit(const Target & i_target) { ReturnCode rc; - std::vector<Target> vector_targets; + std::vector<Target> vector_targets, vector_l4_targets; const char* mbs_if[] = { "mbs_def.if", /* "mbs_mcbist.if" // moved into mbs_def file */ @@ -130,6 +132,28 @@ ReturnCode mss_scominit(const Target & i_target) { // insert centaur target at beginning of vector vector_targets.insert(vector_targets.begin(),i_target); + FAPI_INF("Getting L4 targets"); + // Get L4 vectors + rc = fapiGetChildChiplets(i_target, TARGET_TYPE_L4, + vector_l4_targets, TARGET_STATE_PRESENT); + + if (rc) + { + FAPI_ERR("Error from fapiGetChildChiplets getting L4 targets!"); + FAPI_ERR("RC = 0x%x", static_cast<uint32_t>(rc)); + return (rc); + } + + if (vector_l4_targets.size() != 1) + { + FAPI_ERR("Error target does not have L4!"); + FAPI_ERR("RC = 0x%x", static_cast<uint32_t>(rc)); + return (rc); + } + + // insert L4 targets at the end + vector_targets.insert(vector_targets.end(),vector_l4_targets.begin(), vector_l4_targets.end()); + // run mbs initfile... uint8_t num_mbs_files = sizeof(mbs_if)/sizeof(char*); for (uint8_t itr=0; itr < num_mbs_files; itr++) diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp_errors.xml b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp_errors.xml index 4893352c2..df96dc9f7 100644 --- a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp_errors.xml +++ b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_smp_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_fab_smp_errors.xml,v 1.5 2013/06/25 15:38:27 cswenson Exp $ --> <!-- Error definitions for proc_fab_smp --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H index 4a3e34ae3..b7cdba757 100755 --- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: p8_scom_addresses.H,v 1.158 2013/06/21 18:23:33 jeshua Exp $ +// $Id: p8_scom_addresses.H,v 1.159 2013/06/28 16:50:17 stillgs Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -760,10 +760,12 @@ CONST_UINT64_T( PBA_TRUSTMODE_0x02013F08 , ULL(0x02013F08) ); //------------------------------------------------------------------------------ // PBAX //------------------------------------------------------------------------------ -CONST_UINT64_T( PBAXSNDTX_00064020 , ULL(0x00064020) ); -CONST_UINT64_T( PBAXCFG_00064021 , ULL(0x00064021) ); -CONST_UINT64_T( PBAXSHBR0_00064026 , ULL(0x00064026) ); -CONST_UINT64_T( PBAXSHBR1_0006402A , ULL(0x0006402A) ); +CONST_UINT64_T( PBAXSNDTX_00064020 , ULL(0x00064020) ); +CONST_UINT64_T( PBAXCFG_00064021 , ULL(0x00064021) ); +CONST_UINT64_T( PBAXSHBR0_00064026 , ULL(0x00064026) ); +CONST_UINT64_T( PBAXSHCS0_00064027 , ULL(0x00064027) ); +CONST_UINT64_T( PBAXSHBR1_0006402A , ULL(0x0006402A) ); +CONST_UINT64_T( PBAXSHBR1_0006402B , ULL(0x0006402B) ); //------------------------------------------------------------------------------ // PSI @@ -1958,6 +1960,10 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: p8_scom_addresses.H,v $ +Revision 1.159 2013/06/28 16:50:17 stillgs + +Adde PBAX Push Control/Status 1 registers for pba_init -reset + Revision 1.158 2013/06/21 18:23:33 jeshua Added EX_PARTIAL_GOOD_0x520F0012 for FFDC diff --git a/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile index ea2e7277e..73a42d943 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.fbc.scom.initfile,v 1.11 2013/05/15 04:26:50 jmcgill Exp $ +#-- $Id: p8.fbc.scom.initfile,v 1.12 2013/06/19 18:58:32 jmcgill Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -138,7 +138,7 @@ scom 0x04010C0A { bits, scom_data, expr; x_avp_mode, 0b0, (xbus_enabled); #-- X AVP mode (TODO: link to attribute) x_4b_mode, 0b1, (xbus_enabled) && (def_x_is_4b); #-- X bus 4/8B switch - x_tod_wait_limit, 0b1000, (xbus_enabled); #-- X bus TOD wait limit + x_tod_wait_limit, 0b0100, (xbus_enabled); #-- X bus TOD wait limit } #-- PB A Link Mode Register (PB_IOA_MODE / 0x0801080A) diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_bulk_pwr_throttles.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_bulk_pwr_throttles.xml new file mode 100644 index 000000000..10edd59e7 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_bulk_pwr_throttles.xml @@ -0,0 +1,43 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_bulk_pwr_throttles.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_bulk_pwr_throttles.xml,v 1.1 2013/06/19 18:27:39 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_bulk_pwr_throttles.C --> +<!-- // *! OWNER NAME : Joab Henderson Email: joabhend@us.ibm.com --> +<!-- // *! BACKUP NAME : Michael Pardeik Email: pardeik@us.ibm.com --> + +<!-- Original Source for RC_MSS_NOT_ENOUGH_AVAILABLE_DIMM_POWER memory_errors.xml --> + <hwpError> + <rc>RC_MSS_NOT_ENOUGH_AVAILABLE_DIMM_POWER</rc> + <description>Unable to find throttle setting that has DIMM power underneath the limit. Callout Firmware.</description> + <ffdc>MEM_CHIP</ffdc> + <ffdc>FFDC_DATA_1</ffdc> + <ffdc>FFDC_DATA_2</ffdc> + <ffdc>FFDC_DATA_3</ffdc> + <ffdc>FFDC_DATA_4</ffdc> + <ffdc>FFDC_DATA_5</ffdc> + <!-- TODO: callout firmware --> +</hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_thermal.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_thermal.xml new file mode 100644 index 000000000..f4b4184fc --- /dev/null +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_thermal.xml @@ -0,0 +1,62 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_config_thermal.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_eff_config_thermal.xml,v 1.1 2013/06/19 18:28:01 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_eff_config_thermal.C --> +<!-- // *! OWNER NAME : Joab Henderson Email: joabhend@us.ibm.com --> +<!-- // *! BACKUP NAME : Michael Pardeik Email: pardeik@us.ibm.com --> + +<!-- Original Source for RC_MSS_DIMM_POWER_CURVE_DATA_LAB memory_errors.xml --> + <hwpError> + <rc>RC_MSS_DIMM_POWER_CURVE_DATA_LAB</rc> + <description>DIMM power curve data is lab data not MSL</description> + <ffdc>FFDC_DATA_1</ffdc> + <ffdc>FFDC_DATA_2</ffdc> + <ffdc>FFDC_DATA_3</ffdc> + <ffdc>FFDC_DATA_4</ffdc> + <callout><target>MEM_CHIP</target><priority>HIGH</priority></callout> +</hwpError> + +<!-- Original Source for RC_MSS_DIMM_POWER_CURVE_DATA_INVALID memory_errors.xml --> + <hwpError> + <rc>RC_MSS_DIMM_POWER_CURVE_DATA_INVALID</rc> + <description>DIMM power curve data is invalid</description> + <ffdc>FFDC_DATA_1</ffdc> + <ffdc>FFDC_DATA_2</ffdc> + <ffdc>FFDC_DATA_3</ffdc> + <ffdc>FFDC_DATA_4</ffdc> + <callout><target>MEM_CHIP</target><priority>HIGH</priority></callout> +</hwpError> + +<!-- Original Source for RC_MSS_DIMM_NOT_FOUND_IN_POWER_TABLE memory_errors.xml --> + <hwpError> + <rc>RC_MSS_DIMM_NOT_FOUND_IN_POWER_TABLE</rc> + <description>Unable to find matching entry in DIMM power table</description> + <ffdc>FFDC_DATA_1</ffdc> + <ffdc>FFDC_DATA_2</ffdc> + <ffdc>FFDC_DATA_3</ffdc> + <callout><target>MEM_DIMM</target><priority>HIGH</priority></callout> +</hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_grouping.xml b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_grouping.xml new file mode 100644 index 000000000..f56bf1d96 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_grouping.xml @@ -0,0 +1,55 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/memory_mss_eff_grouping.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_eff_grouping.xml,v 1.2 2013/06/19 21:33:10 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_eff_grouping.C --> + +<!-- Original Source for RC_MSS_NON_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE memory_errors.xml --> +<hwpError> + <rc>RC_MSS_NON_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE</rc> + <description>FABRIC IS IN NON-CHECKER BOARD MODE. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '2MCS/GROUP, 4MCS/GROUP AND 8MCS/GROUP'. OR ENABLE CHECKER BOARD, TO SUPPORT '1MCS/GROUP'. MRW NEEDS TO BE UPDATED. </description> + <collectFfdc>hwpCollectMemGrouping, PROC_CHIP</collectFfdc> +</hwpError> + +<!-- Original Source for RC_MSS_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE memory_errors.xml --> +<hwpError> + <rc>RC_MSS_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE</rc> + <description>FABRIC IS IN CHECKER BOARD MODE BUT IT DOES NOT SUPPORT 1MCS/GROUP. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '1MCS/GROUP'. OR DISABLE CHECKER BOARD, TO SUPPORT '2MCS/GROUP, 4MCS/GROUP AND 8MCS/GROUP'. MRW NEEDS TO BE UPDATED. </description> + <collectFfdc>hwpCollectMemGrouping, PROC_CHIP</collectFfdc> +</hwpError> + +<!-- Original Source for RC_MSS_UNABLE_TO_GROUP_SUMMARY memory_errors.xml --> +<hwpError> + <rc>RC_MSS_UNABLE_TO_GROUP_SUMMARY</rc> + <description>MCS COULD NOT BE GROUPED. SEE PREVIOUS ERROR MESSAGES FOR WHICH MCS HAS BEEN RC_MSS_UNABLE_TO_GROUP_MCS</description> +</hwpError> + +<!-- Original Source for RC_MSS_BASE_ADDRESS_OVERLAPS_MIRROR_ADDRESS memory_errors.xml --> +<hwpError> + <rc>RC_MSS_BASE_ADDRESS_OVERLAPS_MIRROR_ADDRESS</rc> + <description>MIRROR BASE ADDRESS OVERLAPS WITH MEMORY BASE ADDRESS.</description> + <collectFfdc>hwpCollectMemGrouping, PROC_CHIP</collectFfdc> +</hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/mc_config/mss_freq/memory_mss_freq.xml b/src/usr/hwpf/hwp/mc_config/mss_freq/memory_mss_freq.xml new file mode 100644 index 000000000..69e9f3cd3 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_config/mss_freq/memory_mss_freq.xml @@ -0,0 +1,60 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/mc_config/mss_freq/memory_mss_freq.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_freq.xml,v 1.1 2013/06/19 18:28:07 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_freq.C --> +<!-- // *! OWNER NAME : Jeff Sabrowski (jsabrow@us.ibm.com) --> +<!-- // *! BACKUP NAME : --> + +<!-- Original Source for RC_MSS_UNSUPPORTED_SPD_DATA memory_errors.xml --> + <hwpError> + <rc>RC_MSS_UNSUPPORTED_SPD_DATA</rc> + <description>Invalid SPD data returned.</description> +</hwpError> + +<!-- Original Source for RC_MSS_MODULE_TYPE_MIX memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MODULE_TYPE_MIX</rc> + <description>Differing DIMM types in the same configuration.</description> +</hwpError> + +<!-- Original Source for RC_MSS_NO_COMMON_SUPPORTED_CL memory_errors.xml --> + <hwpError> + <rc>RC_MSS_NO_COMMON_SUPPORTED_CL</rc> + <description>Current Configuration has no common supported CL Values.</description> +</hwpError> + +<!-- Original Source for RC_MSS_EXCEED_TAA_MAX_NO_CL memory_errors.xml --> + <hwpError> + <rc>RC_MSS_EXCEED_TAA_MAX_NO_CL</rc> + <description>Exceeded TAA MAX with Lowest frequency. No compatable CL.</description> +</hwpError> + +<!-- Original Source for RC_MSS_UNSUPPORTED_FREQ_CALCULATED memory_errors.xml --> + <hwpError> + <rc>RC_MSS_UNSUPPORTED_FREQ_CALCULATED</rc> + <description>The frequency calculated with spd data is not supported by the jedec standards.</description> +</hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C b/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C index 89e5e80f5..dda421f7e 100644 --- a/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C +++ b/src/usr/hwpf/hwp/mc_config/mss_freq/mss_freq.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_freq.C,v 1.21 2013/02/13 00:23:34 jdsloat Exp $ +// $Id: mss_freq.C,v 1.22 2013/06/27 20:51:49 jdsloat Exp $ /* File mss_volt.C created by JEFF SABROWSKI on Fri 21 Oct 2011. */ //------------------------------------------------------------------------------ @@ -61,6 +61,8 @@ // 1.19 | jdsloat | 01/30/13 | Added Check for l_spd_min_tck_max // 1.20 | jdsloat | 02/12/13 | Added path for freq_override // 1.21 | jdsloat | 02/12/13 | Added Debug messages +// 1.22 | jdsloat | 06/27/13 | Fixed overridng RC error that results in coredump on no centaur SPD info. + // // This procedure takes CENTAUR as argument. for each DIMM (under each MBA) // DIMM SPD attributes are read to determine optimal DRAM frequency @@ -382,36 +384,40 @@ fapi::ReturnCode mss_freq(const fapi::Target &i_target_memb) FAPI_SET_HWP_ERROR(l_rc, RC_MSS_UNSUPPORTED_SPD_DATA); } - l_rc = FAPI_ATTR_GET(ATTR_MSS_FREQ_OVERRIDE, &i_target_memb, l_freq_override); - if ( l_freq_override != 0) + if (!l_rc) { - // The relationship is as such - // l_dimm_freq_min = 2000000 / l_spd_min_tck_max - - if (l_freq_override == 1866) - { - l_dimm_freq_min = 1866; - l_spd_min_tck_max = 1072; - } - - if (l_freq_override == 1600) - { - l_dimm_freq_min = 1600; - l_spd_min_tck_max = 1250; - } + l_rc = FAPI_ATTR_GET(ATTR_MSS_FREQ_OVERRIDE, &i_target_memb, l_freq_override); + if ( l_freq_override != 0) + { + // The relationship is as such + // l_dimm_freq_min = 2000000 / l_spd_min_tck_max + + if (l_freq_override == 1866) + { + l_dimm_freq_min = 1866; + l_spd_min_tck_max = 1072; + } + + if (l_freq_override == 1600) + { + l_dimm_freq_min = 1600; + l_spd_min_tck_max = 1250; + } + + if (l_freq_override == 1333) + { + l_dimm_freq_min = 1333; + l_spd_min_tck_max = 1500; + } - if (l_freq_override == 1333) - { - l_dimm_freq_min = 1333; - l_spd_min_tck_max = 1500; - } + if (l_freq_override == 1066) + { + l_dimm_freq_min = 1066; + l_spd_min_tck_max = 1875; + } - if (l_freq_override == 1066) - { - l_dimm_freq_min = 1066; - l_spd_min_tck_max = 1875; - } - FAPI_INF( "Override Frequency Detected: %d", l_dimm_freq_min); + FAPI_INF( "Override Frequency Detected: %d", l_dimm_freq_min); + } } if ((l_spd_cas_lat_supported_all == 0) && (!l_rc)) diff --git a/src/usr/hwpf/hwp/mc_config/mss_volt/memory_mss_volt.xml b/src/usr/hwpf/hwp/mc_config/mss_volt/memory_mss_volt.xml new file mode 100644 index 000000000..5ba5b31f4 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_config/mss_volt/memory_mss_volt.xml @@ -0,0 +1,57 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/mc_config/mss_volt/memory_mss_volt.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_volt.xml,v 1.1 2013/06/19 18:28:37 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_volt.C --> +<!-- // *! OWNER NAME : Jeff Sabrowski (jsabrow@us.ibm.com) --> +<!-- // *! BACKUP NAME : --> + +<!-- Original Source for RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE memory_errors.xml --> + <hwpError> + <rc>RC_MSS_VOLT_UNRECOGNIZED_DRAM_DEVICE_TYPE</rc> + <description>Unsupported DIMM type found. All dimms must be DDR3 or DDR4</description> + <ffdc>DEVICE_TYPE</ffdc> +</hwpError> + +<!-- Original Source for RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED memory_errors.xml --> + <hwpError> + <rc>RC_MSS_VOLT_DDR_TYPE_MIXING_UNSUPPORTED</rc> + <description>Mixing of DDR3 and DDR4 not supported.</description> +</hwpError> + +<!-- Original Source for RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE memory_errors.xml --> + <hwpError> + <rc>RC_MSS_VOLT_DDR_TYPE_REQUIRED_VOLTAGE</rc> + <description>One or more DIMMs do not support required voltage for DDR type.</description> +</hwpError> + +<!-- Original Source for RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION memory_errors.xml --> + <hwpError> + <rc>RC_MSS_VOLT_TOLERATED_VOLTAGE_VIOLATION</rc> + <description>One or more DIMMs classified non-functional has a tolerated voltage below selected voltage.</description> + <!-- Deconfigure MASTER_CHIP --> + <deconfigure><target>MASTER_CHIP</target></deconfigure> +</hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup_errors.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup_errors.xml index f3edcf8ce..1c9b0a1dd 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup_errors.xml +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup_errors.xml @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_a_x_pci_dmi_pll_setup_errors.xml,v 1.4 2013/06/25 15:38:20 cswenson Exp $ --> <!-- Halt codes for proc_a_x_pci_dmi_pll_setup --> <hwpErrors> <!-- ******************************************************************** --> diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit_errors.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit_errors.xml index 9e61fd5ae..41c5107bc 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit_errors.xml +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit_errors.xml @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_abus_scominit_errors.xml,v 1.3 2013/06/25 15:38:21 cswenson Exp $ --> <!-- Error definitions for proc_abus_scominit procedure --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit_errors.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit_errors.xml index 5af51a27d..8a80cc5eb 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit_errors.xml +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_chiplet_scominit_errors.xml,v 1.2 2013/06/25 15:38:25 cswenson Exp $ --> <!-- Error definitions for proc_chiplet_scominit procedure --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit_errors.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit_errors.xml index bd2afb999..91960d3b8 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit_errors.xml +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit_errors.xml @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_xbus_scominit_errors.xml,v 1.3 2013/06/25 15:38:34 cswenson Exp $ --> <!-- Error definitions for proc_xbus_scominit procedure --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_errors.xml b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_errors.xml index e93077e64..dbc4a9e18 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_errors.xml +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_pcie_scominit_errors.xml,v 1.2 2013/06/25 15:38:31 cswenson Exp $ --> <!-- Error definitions for proc_pcie_scominit --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml index da135602a..03d35104e 100644 --- a/src/usr/hwpf/hwp/proc_chip_ec_feature.xml +++ b/src/usr/hwpf/hwp/proc_chip_ec_feature.xml @@ -20,10 +20,26 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_chip_ec_feature.xml,v 1.14 2013/05/01 22:08:25 jmcgill Exp $ --> +<!-- $Id: proc_chip_ec_feature.xml,v 1.22 2013/07/16 21:41:12 jmcgill Exp $ --> <!-- Defines the attributes that are based on EC level --> <attributes> <attribute> + <id>ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + For Venice specific inits. Returns true if Venice. + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> <id>ATTR_CHIP_EC_FEATURE_HW_BUG_PIBSLVRESET</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -47,8 +63,10 @@ <chip> <name>ENUM_ATTR_NAME_MURANO</name> <ec> - <value>0x11</value> - <test>LESS_THAN_OR_EQUAL</test> + <!-- WARNING: need to adjust to support true DD1.0 parts --> + <!-- this change ensures we test without workaround on DD1.01 --> + <value>0x10</value> + <test>LESS_THAN</test> </ec> </chip> </chipEcFeature> @@ -148,6 +166,56 @@ <chip> <name>ENUM_ATTR_NAME_VENICE</name> <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_NX_HANG_CONTROL_ON_SCOM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns if a chip contains SCOM configuration for NX unit PB hang recovrery controls. True if: + Murano EC 0x20 or greater + Venice EC 0x20 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_HCA_SPLIT_HANG_CONTROL</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns if a chip contains separate SCOM configuration for HCA oper/data hang PB hang recovrery controls. True if: + Murano EC 0x20 or greater + Venice EC 0x10 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> <value>0x10</value> <test>GREATER_THAN_OR_EQUAL</test> </ec> @@ -337,4 +405,79 @@ </chip> </chipEcFeature> </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_TRACE_CONTROL_ON_SCOM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True if: + Murano EC greater than or equal to 0x20 + Venice + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x10</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_MPIPL_AISS_WINKLE_ENTRY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True if: + Murano EC less than 0x20 + Venice EC less than 0x20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_CENT5_VER2</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + True if: + Murano EC greater than or equal to 0x20 + Venice EC greater than or equal to 0x20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_MURANO</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_VENICE</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> </attributes> diff --git a/src/usr/hwpf/hwp/runtime_errors/proc_force_vsafe_errors.xml b/src/usr/hwpf/hwp/runtime_errors/proc_force_vsafe_errors.xml index e2a54c135..243f745c0 100644 --- a/src/usr/hwpf/hwp/runtime_errors/proc_force_vsafe_errors.xml +++ b/src/usr/hwpf/hwp/runtime_errors/proc_force_vsafe_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: p8_force_vsafe_errors.xml,v 1.2 2013/06/25 15:38:19 cswenson Exp $ --> <!-- Error definitions for proc_pmc_force_vsage procedure --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/utility_procedures/memory_mss_maint_cmds.xml b/src/usr/hwpf/hwp/utility_procedures/memory_mss_maint_cmds.xml new file mode 100644 index 000000000..f8b8eb95d --- /dev/null +++ b/src/usr/hwpf/hwp/utility_procedures/memory_mss_maint_cmds.xml @@ -0,0 +1,488 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/utility_procedures/memory_mss_maint_cmds.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<hwpErrors> +<!-- $Id: memory_mss_maint_cmds.xml,v 1.1 2013/06/19 18:28:17 bellows Exp $ --> +<!-- For file ../../ipl/fapi/mss_maint_cmds.C --> + +<!-- Original Source for RC_MSS_MAINT_UNSUCCESSFUL_FORCED_MAINT_CMD_STOP memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_UNSUCCESSFUL_FORCED_MAINT_CMD_STOP</rc> + <description>MBMSRQ[0] = 1, unsuccessful forced maint cmd stop.</description> + <!-- FFDC: Capture register we used to stop cmd --> + <ffdc>MBMCC</ffdc> + <!-- FFDC: Capture register we are checking --> + <ffdc>MBMSR</ffdc> + <!-- FFDC: Capture command type we are trying to run --> + <ffdc>CMD_TYPE</ffdc> + <!-- Callout MBA HIGH --> + <callout><target>MBA</target><priority>HIGH</priority></callout> + <!-- Deconfigure MBA --> + <deconfigure><target>MBA</target></deconfigure> + <!-- Create GARD record for MBA --> + <gard><target>MBA</target></gard> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_START_NOT_RESET memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_START_NOT_RESET</rc> + <description>MBMCCQ[0]: maint_cmd_start not reset by hw.</description> + <!-- FFDC: Capture register we are checking --> + <ffdc>MBMCC</ffdc> + <!-- FFDC: Capture command type we are trying to run --> + <ffdc>CMD_TYPE</ffdc> + <!-- FFDC: MBMCT[0:4] contains the cmd type set in hw --> + <ffdc>MBMCT</ffdc> + <!-- Callout MBA HIGH --> + <callout><target>MBA</target><priority>HIGH</priority></callout> + <!-- Deconfigure MBA --> + <deconfigure><target>MBA</target></deconfigure> + <!-- Create GARD record for MBA --> + <gard><target>MBA</target></gard> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_STOP_NOT_RESET memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_STOP_NOT_RESET</rc> + <description>MBMCCQ[1]: maint_cmd_stop not reset by hw.</description> + <!-- FFDC: Capture register we are checking --> + <ffdc>MBMCC</ffdc> + <!-- FFDC: Capture command type we are trying to run --> + <ffdc>CMD_TYPE</ffdc> + <!-- FFDC: MBMCT[0:4] contains the cmd type previously run --> + <ffdc>MBMCT</ffdc> + <!-- Callout MBA HIGH --> + <callout><target>MBA</target><priority>HIGH</priority></callout> + <!-- Deconfigure MBA --> + <deconfigure><target>MBA</target></deconfigure> + <!-- Create GARD record for MBA --> + <gard><target>MBA</target></gard> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_CMD_IN_PROGRESS memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_CMD_IN_PROGRESS</rc> + <description>MBMSRQ[0]: Can't start new cmd if previous cmd still in progress.</description> + <!-- FFDC: Capture register we are checking --> + <ffdc>MBMSR</ffdc> + <!-- FFDC: Capture command type we are trying to run --> + <ffdc>CMD_TYPE</ffdc> + <!-- FFDC: MBMCT[0:4] contains the cmd type previously run --> + <ffdc>MBMCT</ffdc> + <!-- TODO: Callout FW HIGH --> + <!-- Callout MBA LOW --> + <callout><target>MBA</target><priority>LOW</priority></callout> + <!-- Deconfigure MBA --> + <deconfigure><target>MBA</target></deconfigure> + <!-- Create GARD record for MBA --> + <gard><target>MBA</target></gard> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_NO_MEM_CNFG memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_NO_MEM_CNFG</rc> + <description>MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: Capture register we are checking --> + <ffdc>MBAXCR</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_CCS_MUX_NOT_MAINLINE memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_CCS_MUX_NOT_MAINLINE</rc> + <description>CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: Capture register we are checking --> + <ffdc>CCS_MODE</ffdc> + <!-- FFDC: Capture command type we are trying to run --> + <ffdc>CMD_TYPE</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_ECC_DISABLED memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_ECC_DISABLED</rc> + <description>MBSECC[0] non zero, meaning ECC check/correct disabled.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: Capture register we are checking --> + <ffdc>MBSECC</ffdc> + <!-- FFDC: Capture command type we are trying to run --> + <ffdc>CMD_TYPE</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_INVALID_CMD memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_INVALID_CMD</rc> + <description>MBAFIRQ[0], invalid_maint_cmd.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: Capture register we are checking --> + <ffdc>MBAFIR</ffdc> + <!-- FFDC: Capture command type we are trying to run --> + <ffdc>CMD_TYPE</ffdc> + <!-- FFDC: MBMCT[0:4] contains the cmd type set in hw --> + <ffdc>MBMCT</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_INVALID_ADDR memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_INVALID_ADDR</rc> + <description>MBAFIRQ[1], cmd started with invalid_maint_address.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: Capture register we are checking --> + <ffdc>MBAFIR</ffdc> + <!-- FFDC: Capture command type we are trying to run --> + <ffdc>CMD_TYPE</ffdc> + <!-- FFDC: MBMCT[0:4] contains the cmd type set in hw --> + <ffdc>MBMCT</ffdc> + <!-- Collect registers as FFDC --> + <collectRegisterFfdc> + <id>REG_FFDC_INVALID_ADDR</id> + <target>MBA</target> + </collectRegisterFfdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_CMD_TIMEOUT memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_CMD_TIMEOUT</rc> + <description>Maint cmd timeout.</description> + <!-- FFDC: Capture command type we are trying to run --> + <ffdc>CMD_TYPE</ffdc> + <!-- Collect MBA registers as FFDC --> + <collectRegisterFfdc> + <id>REG_FFDC_CMD_TIMEOUT_MBA_REGS</id> + <target>MBA</target> + </collectRegisterFfdc> + <!-- Collect MBS registers as FFDC --> + <collectRegisterFfdc> + <id>REG_FFDC_CMD_TIMEOUT_MBS_REGS</id> + <target>CENTAUR</target> + </collectRegisterFfdc> + <!-- TODO: Callout FW HIGH --> + <!-- Callout MBA LOW --> + <callout><target>MBA</target><priority>LOW</priority></callout> + <!-- Deconfigure MBA --> + <deconfigure><target>MBA</target></deconfigure> + <!-- Create GARD record for MBA --> + <gard><target>MBA</target></gard> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_ZERO_DDR_FREQ memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_ZERO_DDR_FREQ</rc> + <description>ATTR_MSS_FREQ set to zero so can't calculate scrub rate.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: Capture command type we are trying to run --> + <ffdc>CMD_TYPE</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH</rc> + <description>Invalid dramSize or dramWidth in MBAXCRn.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: Capture register we are checking --> + <ffdc>MBAXCR</ffdc> + <!-- FFDC: DRAM width --> + <ffdc>DRAM_WIDTH</ffdc> + <!-- FFDC: DRAM gen: DDR3 or DDR4 --> + <ffdc>DRAM_GEN</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_INVALID_DIMM_CNFG memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_INVALID_DIMM_CNFG</rc> + <description>MBAXCRn configured with invalid combination of configType, configSubType, slotConfig.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: Capture register we are checking --> + <ffdc>MBAXCR</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_GET_ADDRESS_RANGE_BAD_INPUT memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_GET_ADDRESS_RANGE_BAD_INPUT</rc> + <description>i_rank input to mss_get_address_range out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: RANK we are trying to get address range for --> + <ffdc>RANK</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_GET_MARK_STORE_BAD_INPUT memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_GET_MARK_STORE_BAD_INPUT</rc> + <description>i_rank input to mss_get_mark_store out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: RANK we are trying read markstore for --> + <ffdc>RANK</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_X4_SYMBOL_ON_READ memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_X4_SYMBOL_ON_READ</rc> + <description>Symbol mark not allowed in x4 mode.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: DRAM width (should be x4) --> + <ffdc>DRAM_WIDTH</ffdc> + <!-- FFDC: RANK we are reading markstore for --> + <ffdc>RANK</ffdc> + <!-- FFDC: Markstore with non-zero symbol entry --> + <ffdc>MARKSTORE</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_INVALID_MARKSTORE memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_INVALID_MARKSTORE</rc> + <description>Invalid galois field in markstore.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: DRAM width --> + <ffdc>DRAM_WIDTH</ffdc> + <!-- FFDC: RANK we are reading markstore for --> + <ffdc>RANK</ffdc> + <!-- FFDC: Markstore with invalid galois field --> + <ffdc>MARKSTORE</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_PUT_MARK_STORE_BAD_INPUT memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_PUT_MARK_STORE_BAD_INPUT</rc> + <description>i_rank input to mss_put_mark_store out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: RANK we are trying write markstore for --> + <ffdc>RANK</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_X4_SYMBOL_ON_WRITE memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_X4_SYMBOL_ON_WRITE</rc> + <description>Symbol mark not allowed in x4 mode.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: DRAM width (should be x4) --> + <ffdc>DRAM_WIDTH</ffdc> + <!-- FFDC: RANK we are reading markstore for --> + <ffdc>RANK</ffdc> + <!-- FFDC: Symbol mark we are trying to write to markstore --> + <ffdc>SYMBOL_MARK</ffdc> + <!-- FFDC: Chip mark we are trying to write to markstore --> + <ffdc>CHIP_MARK</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_INVALID_SYMBOL_INDEX memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_INVALID_SYMBOL_INDEX</rc> + <description>Symbol index out of range.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: DRAM width --> + <ffdc>DRAM_WIDTH</ffdc> + <!-- FFDC: RANK we are reading markstore for --> + <ffdc>RANK</ffdc> + <!-- FFDC: Symbol mark we are trying to write to markstore --> + <ffdc>SYMBOL_MARK</ffdc> + <!-- FFDC: Chip mark we are trying to write to markstore --> + <ffdc>CHIP_MARK</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_INVALID_CHIP_INDEX memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_INVALID_CHIP_INDEX</rc> + <description>Not first symbol index of a chip.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: DRAM width --> + <ffdc>DRAM_WIDTH</ffdc> + <!-- FFDC: RANK we are reading markstore for --> + <ffdc>RANK</ffdc> + <!-- FFDC: Symbol mark we are trying to write to markstore --> + <ffdc>SYMBOL_MARK</ffdc> + <!-- FFDC: Chip mark we are trying to write to markstore --> + <ffdc>CHIP_MARK</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED</rc> + <description>Markstore write may have been blocked due to MPE FIR set.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: DRAM width --> + <ffdc>DRAM_WIDTH</ffdc> + <!-- FFDC: RANK we are reading markstore for --> + <ffdc>RANK</ffdc> + <!-- FFDC: Symbol mark we are trying to write to markstore --> + <ffdc>SYMBOL_MARK</ffdc> + <!-- FFDC: Chip mark we are trying to write to markstore --> + <ffdc>CHIP_MARK</ffdc> + <!-- FFDC: MBECCFIR showing MPE --> + <ffdc>MBECCFIR</ffdc> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_GET_STEER_MUX_BAD_INPUT memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_GET_STEER_MUX_BAD_INPUT</rc> + <description>i_rank or i_muxType input to mss_get_steer_mux out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: RANK we are reading steer mux for --> + <ffdc>RANK</ffdc> + <!-- FFDC: MUX_TYPE: read or write --> + <ffdc>MUX_TYPE</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_INVALID_STEER_MUX memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_INVALID_STEER_MUX</rc> + <description>Steer mux index out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: DRAM width --> + <ffdc>DRAM_WIDTH</ffdc> + <!-- FFDC: RANK we are reading steer mux for --> + <ffdc>RANK</ffdc> + <!-- FFDC: MUX_TYPE: read or write --> + <ffdc>MUX_TYPE</ffdc> + <!-- FFDC: Capture steer mux --> + <ffdc>STEER_MUX</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_PUT_STEER_MUX_BAD_INPUT memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_PUT_STEER_MUX_BAD_INPUT</rc> + <description>i_rank or i_muxType or i_steerType or i_symbol input to mss_put_steer_mux out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: RANK we are writing steer mux for --> + <ffdc>RANK</ffdc> + <!-- FFDC: MUX_TYPE: read or write --> + <ffdc>MUX_TYPE</ffdc> + <!-- FFDC: STEER_TYPE: port0 spare, port1 spare or ecc spare --> + <ffdc>STEER_TYPE</ffdc> + <!-- FFDC: SYMBOL: 0-71 --> + <ffdc>SYMBOL</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER</rc> + <description>Trying to steer invalid symbol.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: DRAM width --> + <ffdc>DRAM_WIDTH</ffdc> + <!-- FFDC: RANK we are reading steer mux for --> + <ffdc>RANK</ffdc> + <!-- FFDC: MUX_TYPE: read or write --> + <ffdc>MUX_TYPE</ffdc> + <!-- FFDC: STEER_TYPE: port0, port1, or ecc spare --> + <ffdc>STEER_TYPE</ffdc> + <!-- FFDC: SYMBOL: Symbol we are trying to steer --> + <ffdc>SYMBOL</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_NO_X8_ECC_SPARE memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_NO_X8_ECC_SPARE</rc> + <description>Invalid to use ECC spare in x8 mode.</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: DRAM width --> + <ffdc>DRAM_WIDTH</ffdc> + <!-- FFDC: RANK we are reading steer mux for --> + <ffdc>RANK</ffdc> + <!-- FFDC: MUX_TYPE: read or write --> + <ffdc>MUX_TYPE</ffdc> + <!-- FFDC: STEER_TYPE: port0, port1, or ecc spare --> + <ffdc>STEER_TYPE</ffdc> + <!-- FFDC: SYMBOL: Symbol we are trying to steer --> + <ffdc>SYMBOL</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_DO_STEER_INPUT_OUT_OF_RANGE memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_DO_STEER_INPUT_OUT_OF_RANGE</rc> + <description>i_rank or i_symbol input to mss_do_steer out of range</description> + <!-- FFDC: MBA target --> + <ffdc>MBA</ffdc> + <!-- FFDC: RANK we are writing steer mux for --> + <ffdc>RANK</ffdc> + <!-- FFDC: SYMBOL: 0-71 --> + <ffdc>SYMBOL</ffdc> + <!-- FFDC: X4ECCSPARE: true or false --> + <ffdc>X4ECCSPARE</ffdc> + <!-- TODO: Callout FW HIGH --> +</hwpError> + +<!-- Original Source for RC_MSS_MAINT_NO_UE_TRAP memory_errors.xml --> + <hwpError> + <rc>RC_MSS_MAINT_NO_UE_TRAP</rc> + <description>IPL UE trapping didn't work.</description> + <!-- FFDC: Capture UE trap contents --> + <ffdc>UE_TRAP0</ffdc> + <ffdc>UE_TRAP1</ffdc> + <!-- FFDC: MBMCT[0:4] contains the cmd type --> + <ffdc>MBMCT</ffdc> + <!-- FFDC: MBMMR[4:7] contains the pattern index --> + <ffdc>MBMMR</ffdc> + <!-- FFDC: MBSTR[59]: UE trap enable bit --> + <ffdc>MBSTR</ffdc> + <!-- Callout MBA HIGH --> + <callout><target>MBA</target><priority>HIGH</priority></callout> + <!-- Deconfigure MBA --> + <deconfigure><target>MBA</target></deconfigure> + <!-- Create GARD record for MBA --> + <gard><target>MBA</target></gard> +</hwpError> + + +</hwpErrors> diff --git a/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C b/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C index 72c464ee7..262a218bb 100644 --- a/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C +++ b/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_maint_cmds.C,v 1.24 2013/05/20 16:52:28 gollub Exp $ +// $Id: mss_maint_cmds.C,v 1.25 2013/05/24 19:39:02 gollub Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -71,6 +71,8 @@ // 1.22 | 04/30/13 | mjjones | Removed unused variable // 1.23 | 05/03/13 | gollub | Clear cmd complete attention in mss_stopCmd // 1.24 | 05/20/13 | gollub | Updates from review. +// 1.25 | 05/24/13 | gollub | Added DDR4 support to mss_get_address_range +// | | | Disabled superfast increment mode if DDR4 - due to DD1 bug //------------------------------------------------------------------------------ // Includes @@ -174,12 +176,15 @@ namespace mss_MemConfig */ enum MemOrg { + ROW_14 = 0x00003FFF, ROW_15 = 0x00007FFF, ROW_16 = 0x0000FFFF, + ROW_17 = 0x0001FFFF, COL_10 = 0x000003F8, // c2, c1, c0 always 0 COL_11 = 0x000007F8, // c2, c1, c0 always 0 COL_12 = 0x00000FF8, // c2, c1, c0 always 0 BANK_3 = 0x00000007, + BANK_4 = 0x0000000F, }; /** @@ -1058,21 +1063,36 @@ fapi::ReturnCode mss_MaintCmd::loadCmdType() fapi::ReturnCode l_rc; uint32_t l_ecmd_rc = 0; ecmdDataBufferBase l_data(64); + uint8_t l_dram_gen; FAPI_INF("ENTER mss_MaintCmd::loadCmdType()"); + // Get DDR3/DDR4: ATTR_EFF_DRAM_GEN + // 0x01 = ENUM_ATTR_EFF_DRAM_GEN_DDR3 + // 0x02 = ENUM_ATTR_EFF_DRAM_GEN_DDR4 + l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &iv_target, l_dram_gen); + if(l_rc) + { + FAPI_ERR("Error getting DDR3/DDR4 on %s.", iv_target.toEcmdString()); + return l_rc; + } + l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_data); if(l_rc) return l_rc; l_ecmd_rc |= l_data.insert( (uint32_t)iv_cmdType, 0, 5, 32-5 ); - // NOTE: Setting super fast address increment mode, where COL bits are LSB. - // Valid for all cmds. - l_ecmd_rc |= l_data.setBit(5); - if(l_ecmd_rc) + // Setting super fast address increment mode for DDR3, where COL bits are LSB. Valid for all cmds. + // NOTE: Super fast address increment mode is broken for DDR4 due to DD1 bug + if (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; + l_ecmd_rc |= l_data.setBit(5); + if(l_ecmd_rc) + { + l_rc.setEcmdError(l_ecmd_rc); + return l_rc; + } } + l_rc = fapiPutScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_data); if(l_rc) return l_rc; @@ -2962,6 +2982,7 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, uint8_t l_configSubType = 0; uint8_t l_end_master_rank = 0; uint8_t l_end_slave_rank = 0; + uint8_t l_dram_gen; // Get Centaur target for the given MBA l_rc = fapiGetParentChip(i_target, l_targetCentaur); @@ -2995,6 +3016,16 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, return l_rc; } + // Get DDR3/DDR4: ATTR_EFF_DRAM_GEN + // 0x01 = ENUM_ATTR_EFF_DRAM_GEN_DDR3 + // 0x02 = ENUM_ATTR_EFF_DRAM_GEN_DDR4 + l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, l_dram_gen); + if(l_rc) + { + FAPI_ERR("Error getting DDR3/DDR4 on %s.",i_target.toEcmdString()); + return l_rc; + } + // Check MBAXCRn, to show memory configured behind this MBA l_rc = fapiGetScom(l_targetCentaur, mss_mbaxcr[l_mbaPosition], l_data); if(l_rc) return l_rc; @@ -3025,57 +3056,120 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, return l_rc; } - if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_2)) + if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_2) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) { // For memory part Size = 256Mbx8 (2Gb), row/col/bank = 15/10/3 - FAPI_INF("For memory part Size = 256Mbx8 (2Gb), row/col/bank = 15/10/3"); + FAPI_INF("For memory part Size = 256Mbx8 (2Gb), row/col/bank = 15/10/3, DDR3"); l_row = mss_MemConfig::ROW_15; l_col = mss_MemConfig::COL_10; l_bank = mss_MemConfig::BANK_3; } - else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_2)) + + else if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_2) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)) + { + // For memory part Size = 256Mbx8 (2Gb), row/col/bank = 14/10/4 + FAPI_INF("For memory part Size = 256Mbx8 (2Gb), row/col/bank = 14/10/4, DDR4"); + l_row = mss_MemConfig::ROW_14; + l_col = mss_MemConfig::COL_10; + l_bank = mss_MemConfig::BANK_4; + } + + else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_2) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) { // For memory part Size = 512Mbx4 (2Gb), row/col/bank = 15/11/3 - FAPI_INF("For memory part Size = 512Mbx4 (2Gb), row/col/bank = 15/11/3"); + FAPI_INF("For memory part Size = 512Mbx4 (2Gb), row/col/bank = 15/11/3, DDR3"); l_row = mss_MemConfig::ROW_15; l_col = mss_MemConfig::COL_11; l_bank = mss_MemConfig::BANK_3; } - else if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_4)) + + else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_2) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)) + { + // For memory part Size = 512Mbx4 (2Gb), row/col/bank = 15/10/4 + FAPI_INF("For memory part Size = 512Mbx4 (2Gb), row/col/bank = 15/10/4, DDR4"); + l_row = mss_MemConfig::ROW_15; + l_col = mss_MemConfig::COL_10; + l_bank = mss_MemConfig::BANK_4; + } + + else if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_4) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) { // For memory part Size = 512Mbx8 (4Gb), row/col/bank = 16/10/3 - FAPI_INF("For memory part Size = 512Mbx8 (4Gb), row/col/bank = 16/10/3"); + FAPI_INF("For memory part Size = 512Mbx8 (4Gb), row/col/bank = 16/10/3, DDR3"); l_row = mss_MemConfig::ROW_16; l_col = mss_MemConfig::COL_10; l_bank = mss_MemConfig::BANK_3; } - else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_4)) + + else if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_4) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)) + { + // For memory part Size = 512Mbx8 (4Gb), row/col/bank = 14/10/4 + FAPI_INF("For memory part Size = 512Mbx8 (4Gb), row/col/bank = 14/10/4, DDR4"); + l_row = mss_MemConfig::ROW_15; + l_col = mss_MemConfig::COL_10; + l_bank = mss_MemConfig::BANK_4; + } + + + else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_4) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) { // For memory part Size = 1Gbx4 (4Gb), row/col/bank = 16/11/3 - FAPI_INF("For memory part Size = 1Gbx4 (4Gb), row/col/bank = 16/11/3"); + FAPI_INF("For memory part Size = 1Gbx4 (4Gb), row/col/bank = 16/11/3, DDR3"); l_row = mss_MemConfig::ROW_16; l_col = mss_MemConfig::COL_11; l_bank = mss_MemConfig::BANK_3; } - else if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_8)) + + else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_4) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)) + { + // For memory part Size = 1Gbx4 (4Gb), row/col/bank = 16/10/4 + FAPI_INF("For memory part Size = 1Gbx4 (4Gb), row/col/bank = 16/10/4, DDR4"); + l_row = mss_MemConfig::ROW_16; + l_col = mss_MemConfig::COL_10; + l_bank = mss_MemConfig::BANK_4; + } + + else if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_8) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) { // For memory part Size = 1Gbx8 (8Gb), row/col/bank = 16/11/3 - FAPI_INF("For memory part Size = 1Gbx8 (8Gb), row/col/bank = 16/11/3"); + FAPI_INF("For memory part Size = 1Gbx8 (8Gb), row/col/bank = 16/11/3, DDR3"); l_row = mss_MemConfig::ROW_16; l_col = mss_MemConfig::COL_11; l_bank = mss_MemConfig::BANK_3; } - else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_8)) + + else if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_8) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)) + { + // For memory part Size = 1Gbx8 (8Gb), row/col/bank = 16/10/4 + FAPI_INF("For memory part Size = 1Gbx8 (8Gb), row/col/bank = 16/10/4, DDR4"); + l_row = mss_MemConfig::ROW_16; + l_col = mss_MemConfig::COL_10; + l_bank = mss_MemConfig::BANK_4; + } + + + else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_8) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) { // For memory part Size = 2Gbx4 (8Gb), row/col/bank = 16/12/3 - FAPI_INF("For memory part Size = 2Gbx4 (8Gb), row/col/bank = 16/12/3"); + FAPI_INF("For memory part Size = 2Gbx4 (8Gb), row/col/bank = 16/12/3, DDR3"); l_row = mss_MemConfig::ROW_16; l_col = mss_MemConfig::COL_12; l_bank = mss_MemConfig::BANK_3; } + + else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_8) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)) + { + // For memory part Size = 2Gbx4 (8Gb), row/col/bank = 17/10/4 + FAPI_INF("Forosr memory part Size = 2Gbx4 (8Gb), row/col/bank = 17/10/4, DDR4"); + l_row = mss_MemConfig::ROW_17; + l_col = mss_MemConfig::COL_10; + l_bank = mss_MemConfig::BANK_4; + } else { - FAPI_ERR("Invalid l_dramSize = %d or l_dramWidth = %d in MBAXCRn on %s.", l_dramSize, l_dramWidth, i_target.toEcmdString()); + FAPI_ERR("Invalid l_dramSize = %d or l_dramWidth = %d in MBAXCRn, or l_dram_gen = %d on %s.", + l_dramSize, l_dramWidth, l_dram_gen, i_target.toEcmdString()); + // TODO: Calling out FW high // FFDC: MBA target @@ -3084,6 +3178,8 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, ecmdDataBufferBase & MBAXCR = l_data; // FFDC: DRAM width uint8_t DRAM_WIDTH = l_dramWidth; + // FFDC: DRAM width + uint8_t DRAM_GEN = l_dram_gen; // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH); return l_rc; diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index 2134126f6..f1352da1a 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -87,7 +87,21 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ hwp/pstates/pstates/proc_get_voltage_errors.xml \ hwp/proc_cfam_registers.xml \ hwp/proc_slw_registers.xml \ - hwp/proc_sbe_select_ex_errors.xml + hwp/proc_sbe_select_ex_errors.xml \ + hwp/utility_procedures/memory_mss_maint_cmds.xml \ + hwp/mc_config/mss_volt/memory_mss_volt.xml \ + hwp/mc_config/mss_freq/memory_mss_freq.xml \ + hwp/mc_config/mss_eff_config/memory_mss_eff_grouping.xml \ + hwp/mc_config/mss_eff_config/memory_mss_eff_config_thermal.xml \ + hwp/mc_config/mss_eff_config/memory_mss_bulk_pwr_throttles.xml \ + hwp/dram_training/memory_mss_funcs.xml \ + hwp/dram_training/mss_draminit_training/memory_mss_draminit_training.xml \ + hwp/dram_training/mss_ddr_phy_reset/memory_mss_ddr_phy_reset.xml \ + hwp/dram_training/memory_mss_termination_control.xml \ + hwp/dram_training/mem_startclocks/memory_cen_stopclocks.xml \ + hwp/dram_training/mss_scominit/memory_mss_scominit.xml \ + hwp/dram_training/mss_draminit_trainadv/memory_mss_mcbist_common.xml \ + hwp/dram_initialization/proc_setup_bars/memory_mss_setup_bars.xml ## these get generated into obj/genfiles/AttributeIds.H HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \ diff --git a/src/usr/hwpf/plat/fapiPlatSystemConfig.C b/src/usr/hwpf/plat/fapiPlatSystemConfig.C index a0eac794c..68a35b0e4 100644 --- a/src/usr/hwpf/plat/fapiPlatSystemConfig.C +++ b/src/usr/hwpf/plat/fapiPlatSystemConfig.C @@ -261,6 +261,11 @@ fapi::ReturnCode fapiGetChildChiplets( { l_type = TARGETING::TYPE_ABUS; } + else if (i_chipletType == fapi::TARGET_TYPE_L4) + { + l_type = TARGETING::TYPE_L4; + } + else { FAPI_ERR("fapiGetChildChiplets. Chiplet type 0x%08x not supported", |
