diff options
| author | Dan Crowell <dcrowell@us.ibm.com> | 2016-02-08 11:06:44 -0600 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2016-04-04 09:09:04 -0400 |
| commit | 4b4772ef8b18f2e9c80795c47b3a5f81b3521c1f (patch) | |
| tree | 82653a7d7cba5d1b4988fdefb2ef5d9f307b178c /src | |
| parent | feb51c34883347e80dd242266bd064a419cbdc88 (diff) | |
| download | blackbird-hostboot-4b4772ef8b18f2e9c80795c47b3a5f81b3521c1f.tar.gz blackbird-hostboot-4b4772ef8b18f2e9c80795c47b3a5f81b3521c1f.zip | |
Remove more old fapi1 stuff
Deleted src/include/usr/hwpf/hwp/ to ensure no old usage
Deleted a couple modules that have no P9 equivalent
Moved tod_init under istep18
Deleted old initfile related code
Deleted old pll related code
Change-Id: I9c1746609c7ca2a723241158b3958bb891b0629b
RTC: 146345
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21888
Tested-by: Jenkins Server
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: FSP CI Jenkins
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src')
155 files changed, 91 insertions, 89219 deletions
diff --git a/src/include/usr/hwpf/hwp/chip_accessors/getOscswitchCtlAttr.H b/src/include/usr/hwpf/hwp/chip_accessors/getOscswitchCtlAttr.H deleted file mode 100644 index 9be5173ec..000000000 --- a/src/include/usr/hwpf/hwp/chip_accessors/getOscswitchCtlAttr.H +++ /dev/null @@ -1,105 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/chip_accessors/getOscswitchCtlAttr.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getOscswitchCtlAttr.H,v 1.2 2014/06/19 14:35:43 whs Exp $ -/** - * @file getOscswitchCtlAttr.H - * - * @brief Accessor for providing the ATTR_OSCSWITCH_CTLx attributes - */ - -#ifndef _HWP_GETOSCSWITCHCNTL -#define _HWP_GETOSCSWITCHCNTL - -#include <fapi.H> - -namespace fapi -{ - namespace getOscswitchCtl - { - // Attributes supported - enum Attr - { - CTL0 = 0x00, // ATTR_OSCSWITCH_CTL0 - CTL1 = 0x01, // ATTR_OSCSWITCH_CTL1 - CTL2 = 0x02, // ATTR_OSCSWITCH_CTL2 - }; - - // Oscswitch control data - struct OSCSWITCH_CTL_DATA - { - ATTR_NAME_Enum l_CHIP_TYPE; -// uint8_t l_CHIP_EC; // can be added if needed - uint32_t l_CTL0; - uint8_t l_CTL1; - uint32_t l_CTL2; - }; - - // This structure could be generated from engineering data as - // there are more systems with redundant clocks or if values - // become EC specific - const OSCSWITCH_CTL_DATA OSCSWITCH_CTL_DATA_array []= - { - { // Entry if there are no redundant clocks - ENUM_ATTR_NAME_NONE, - 0x0080, - 0x00, - 0x00, - }, - { // Entry for Brazos - ENUM_ATTR_NAME_VENICE, - 0x0A02, - 0x2E, - 0x00400000, - } - }; - - } -} - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getOscswitchCtlAttr_FP_t) - (const fapi::Target &, - const fapi::getOscswitchCtl::Attr, - void *, - const size_t); - -extern "C" -{ -/** - * @brief This function is called by the FAPI_ATTR_GET macro when getting the - * ATTR_OSCSWITCH_CNTL0,1,2 attributes. It should not be called - * directly. - * - * @param[in] i_pProcTarget Processor Chip Target pointer - * @param[in] i_attr Attribute selection - * @param[out] o_pVal Pointer to output variable - * @param[in] i_len Size of o_pVal - */ -fapi::ReturnCode getOscswitchCtlAttr (const fapi::Target & i_pProcTarget, - const fapi::getOscswitchCtl::Attr i_attr, - void * o_pVal, - const size_t i_len); - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/chip_accessors/getPciOscswitchConfig.H b/src/include/usr/hwpf/hwp/chip_accessors/getPciOscswitchConfig.H deleted file mode 100644 index 06b7db9d2..000000000 --- a/src/include/usr/hwpf/hwp/chip_accessors/getPciOscswitchConfig.H +++ /dev/null @@ -1,64 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/chip_accessors/getPciOscswitchConfig.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getPciOscswitchConfig.H,v 1.2 2014/01/15 20:03:21 whs Exp $ -/** - * @file getPciOscswitchConfig.H - * - * @brief Accessor for providing the ATTR_PCI_OSCSWITCH_CONFIG attribute - */ - -#ifndef _HWP_GETPCIOSCSWITCHCONFIG_ -#define _HWP_GETPCIOSCSWITCHCONFIG_ - -#include <fapi.H> - -// configuration values -enum PciOscswitchConfigValues -{ - MURANO_DD1X = 0x03, - MURANO_DD2X = 0x0C, - VENICE_P0P2 = 0x09, // position 0 and 2 - VENICE_P1P3 = 0x06, // position 1 and 3 - NAPLES_DD1X = 0x0C, // TODO RTC: 109249, check; based on Murano DD2X -}; - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getPciOscswitchConfig_FP_t) - (const fapi::Target &, uint8_t &); - -extern "C" -{ -/** - * @brief Get the ATTR_PCI_OSCSWITCH_CONFIG FAPI attribute - * - * @param[in] i_procTarget - Reference to processor chip target - * @param[out] o_val - Filled in with pci oscswitch config - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ -fapi::ReturnCode getPciOscswitchConfig( - const fapi::Target & i_procTarget, - uint8_t & o_val); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/chip_accessors/getTdpRdpCurrentFactor.H b/src/include/usr/hwpf/hwp/chip_accessors/getTdpRdpCurrentFactor.H deleted file mode 100644 index 9d5aab46f..000000000 --- a/src/include/usr/hwpf/hwp/chip_accessors/getTdpRdpCurrentFactor.H +++ /dev/null @@ -1,56 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/chip_accessors/getTdpRdpCurrentFactor.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getTdpRdpCurrentFactor.H,v 1.1 2015/06/01 18:30:12 whs Exp $ -/** - * @file getTdpRdpCurrentFactor.H - * - * @brief Accessor for providing the ATTR_TDP_RDP_CURRENT_FACTOR attribute - */ - -#ifndef _HWP_GETTDPRDPCURRENTFACTOR_ -#define _HWP_GETTDPRDPCURRENTFACTOR_ - -#include <fapi.H> - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getTdpRdpCurrentFactor_FP_t) - (const fapi::Target &, uint32_t &); - -extern "C" -{ -/** - * @brief Get the ATTR_TDP_RDP_CURRENT_FACTOR FAPI attribute - * - * @param[in] i_procTarget - Reference to processor chip target - * @param[out] o_val - Filled in with TDP RDP Current Factor - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ -fapi::ReturnCode getTdpRdpCurrentFactor( - const fapi::Target & i_procTarget, - uint32_t & o_val); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/dimmBadDqBitmapAccessHwp.H b/src/include/usr/hwpf/hwp/dimmBadDqBitmapAccessHwp.H deleted file mode 100644 index ab6aa280e..000000000 --- a/src/include/usr/hwpf/hwp/dimmBadDqBitmapAccessHwp.H +++ /dev/null @@ -1,81 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/dimmBadDqBitmapAccessHwp.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: dimmBadDqBitmapAccessHwp.H,v 1.3 2013/10/03 20:40:52 dedahle Exp $ -/** - * @file dimmBadDqBitmapAccessHwp.H - * - * @brief FW Team HWP that accesses the Bad DQ Bitmap. - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * mjjones 02/17/2012 Created. - */ - -#ifndef DIMMBADDQBITMAPACCESSHWP_H_ -#define DIMMBADDQBITMAPACCESSHWP_H_ - -#include <fapi.H> -#include <dimmConsts.H> - -typedef fapi::ReturnCode (*dimmBadDqBitmapAccessHwp_FP_t)( - const fapi::Target &, - const fapi::Target &, - const uint8_t (&)[DIMM_DQ_MAX_DIMM_RANKS][DIMM_DQ_RANK_BITMAP_SIZE], - const bool); - -extern "C" -{ - -/** - * @brief FW Team HWP that accesses the Bad DQ Bitmap. It accesses the raw data - * from DIMM SPD and does any necessary processing to turn it into a - * bitmap from a Centaur DQ point of view. If the data in SPD is not - * valid then it has never been written and all zeroes are returned (no - * bad DQs). - * - * This HWP should be called by HWP/PLAT code to access the BAD DQ Bitmap - * - * Note that the MSB of each byte corresponds to the lowest DQ. - * if (data[1][0] == 0x80) then rank 1, Centaur DQ0 is bad - * if (data[1][0] == 0x40) then rank 1, Centaur DQ1 is bad - * if (data[1][1] == 0x20) then rank 1, Centaur DQ10 is bad - * - * @param[in] i_mba Reference to MBA Target - * @param[in] i_dimm Reference to DIMM Target - * @param[io] io_data Reference to bad DQ bitmap data for the DIMM. - * @param[in] i_get True if getting DQ Bitmap data. False if setting data. - * - * @return ReturnCode - */ -fapi::ReturnCode dimmBadDqBitmapAccessHwp( - const fapi::Target & i_mba, - const fapi::Target & i_dimm, - uint8_t (&io_data)[DIMM_DQ_MAX_DIMM_RANKS][DIMM_DQ_RANK_BITMAP_SIZE], - const bool i_get); - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/dimmBadDqBitmapFuncs.H b/src/include/usr/hwpf/hwp/dimmBadDqBitmapFuncs.H deleted file mode 100644 index f90e15925..000000000 --- a/src/include/usr/hwpf/hwp/dimmBadDqBitmapFuncs.H +++ /dev/null @@ -1,95 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/dimmBadDqBitmapFuncs.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: dimmBadDqBitmapFuncs.H,v 1.2 2013/08/13 20:30:25 mjjones Exp $ -/** - * @file dimmBadDqBitmapFuncs.H - * - * @brief FW Team Utility functions that accesses the Bad DQ Bitmap. - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * mjjones 02/17/2012 Created. - */ - -#ifndef DIMMBADDQBITMAPFUNCS_H_ -#define DIMMBADDQBITMAPFUNCS_H_ - -#include <fapi.H> -#include <dimmConsts.H> - -extern "C" -{ - -/** - * @brief FW Team Utility function that gets the Bad DQ Bitmap. - * - * This utility functon should be called by a HWP needing to get the Bad DQ - * bitmap for a particular mba, port, dimm and rank. - * - * This function finds the corresponding DIMM Target, calls - * dimmBadDqBitmapAccessHwp to get the DQ bitmap and returns the data - * for the specified rank. - * - * @param[in] i_mba Reference to MBA Chiplet - * @param[in] i_port MBA port number (0-(DIMM_DQ_MAX_MBA_PORTS - 1)) - * @param[in] i_dimm MBA port DIMM number (0-(DIMM_DQ_MAX_MBAPORT_DIMMS - 1)) - * @param[in] i_rank DIMM rank number (0-(DIMM_DQ_MAX_DIMM_RANKS -1)) - * @param[out] o_data Reference to data where Bad DQ bitmap is copied to - * - * @return ReturnCode - */ -fapi::ReturnCode dimmGetBadDqBitmap(const fapi::Target & i_mba, - const uint8_t i_port, - const uint8_t i_dimm, - const uint8_t i_rank, - uint8_t (&o_data)[DIMM_DQ_RANK_BITMAP_SIZE]); - -/** - * @brief FW Team Utility function that sets the Bad DQ Bitmap. - * - * This utility functon should be called by a HWP needing to set the Bad DQ - * bitmap for a particular mba, port, dimm and rank. - * - * This utility function finds the corresponding DIMM Target, calls - * dimmBadDqBitmapAccessHwp to get the DQ bitmap, fills in the data for the - * specified rank and calls dimmBadDqBitmapAccessHwp to set the DQ bitmap - * - * @param[in] i_mba Reference to MBA Chiplet - * @param[in] i_port MBA port number (0-(DIMM_DQ_MAX_MBA_PORTS - 1)) - * @param[in] i_dimm MBA port DIMM number (0-(DIMM_DQ_MAX_MBAPORT_DIMMS - 1)) - * @param[in] i_rank DIMM rank number (0-(DIMM_DQ_MAX_DIMM_RANKS -1)) - * @param[in] i_data Reference to data where Bad DQ bitmap is copied from - * - * @return ReturnCode - */ -fapi::ReturnCode dimmSetBadDqBitmap(const fapi::Target & i_mba, - const uint8_t i_port, - const uint8_t i_dimm, - const uint8_t i_rank, - const uint8_t (&i_data)[DIMM_DQ_RANK_BITMAP_SIZE]); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/dimmConsts.H b/src/include/usr/hwpf/hwp/dimmConsts.H deleted file mode 100644 index 8a049f312..000000000 --- a/src/include/usr/hwpf/hwp/dimmConsts.H +++ /dev/null @@ -1,70 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/dimmConsts.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -/** - * @file dimmConsts.H - * - * @brief DIMM Constants - */ -// $Id: dimmConsts.H,v 1.5 2014/11/03 17:16:17 eliner Exp $ -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * mjjones 02/17/2012 Created. - */ - -#ifndef DIMMCONSTS_H_ -#define DIMMCONSTS_H_ - -// Maximum number of ports on an MBA -const uint8_t DIMM_DQ_MAX_MBA_PORTS = 2; - -// Maximum number of DIMMs attached to an MBA PORT -const uint8_t DIMM_DQ_MAX_MBAPORT_DIMMS = 2; - -// Maximum number of ranks on a DIMM -const uint8_t DIMM_DQ_MAX_DIMM_RANKS = 4; - -// Size in bytes of the Bad DQ bitmap for a rank. -const uint8_t DIMM_DQ_RANK_BITMAP_SIZE = 10; - -// Number of DQs (data query pins). -// This is the number of bits in DIMM_DQ_RANK_BITMAP_SIZE. -const uint8_t DIMM_DQ_NUM_DQS = DIMM_DQ_RANK_BITMAP_SIZE * 8; - -// Size in bytes of Bad DQ Data in DIMM SPD -// This must be big enough to contain the bitmap for each rank -// (DIMM_DQ_MAX_DIMM_RANKS * DIMM_DQ_RANK_BITMAP_SIZE), plus the header -const uint8_t DIMM_DQ_SPD_DATA_SIZE = 80; - -//ISDIMM to C4 DQ and DQS constant -//Number of Ports needed in the array -const uint8_t DIMM_TO_C4_PORTS = 4; -//Number of entries in the DQ attribute -const uint8_t DIMM_TO_C4_DQ_ENTRIES = 80; -//Number of entries in the DQS attribute -const uint8_t DIMM_TO_C4_DQS_ENTRIES = 20; - -#endif diff --git a/src/include/usr/hwpf/hwp/erepairAccessorHwpFuncs.H b/src/include/usr/hwpf/hwp/erepairAccessorHwpFuncs.H deleted file mode 100644 index b0899683e..000000000 --- a/src/include/usr/hwpf/hwp/erepairAccessorHwpFuncs.H +++ /dev/null @@ -1,218 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/erepairAccessorHwpFuncs.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: erepairAccessorHwpFuncs.H,v 1.2 2014/04/29 11:59:25 bilicon Exp $ -/** - * @file erepairAccessorHwpFuncs.H - * - * @brief FW Team Utility functions that accesses fabric and memory eRepair - * data. - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * bilicon 10/24/2012 Created. - */ - -#ifndef EREPAIRACCESSORHWPFUNCS_H_ -#define EREPAIRACCESSORHWPFUNCS_H_ - -#include <fapi.H> -#include <algorithm> - -const uint8_t EREPAIR_MAX_CENTAUR_PER_MCS = 1; - -typedef fapi::ReturnCode (*getLanes_t)( - const fapi::Target &i_tgtHandle, - std::vector<uint8_t> &o_txFailLanes, - std::vector<uint8_t> &o_rxFailLanes); - -typedef fapi::ReturnCode (*setLanes_t)( - const fapi::Target &i_tgtHandle, - const std::vector<uint8_t> &i_txFailLanes, - const std::vector<uint8_t> &i_rxFailLanes); - -/** - * @brief FW Team Utility function that gets eRepair data from the VPD - * This function gets the eRepair data from both the Field VPD - * and the Manufacturing VPD. - * - * @param[in] i_endp_target Reference to X-Bus or A-Bus or MCS or memBuf Target - * @param[out] o_txFailLanes Reference to a Vector that will contain the fail - * lanes read from the VPD for Drive side - * @param[out] o_rxFailLanes Reference to a Vector that will contain the fail - * lanes read from the VPD for Receive side - * @return ReturnCode - * - */ -fapi::ReturnCode erepairGetFailedLanes(const fapi::Target &i_endp_target, - std::vector<uint8_t> &o_txFailLanes, - std::vector<uint8_t> &o_rxFailLanes); - -/** - * @brief FW Team Utility function that gets eRepair data - * - * This is a wrapper function for the Accessor HWP which reads failed lane - * numbers from the Field VPD - * - * @param[in] i_endp_target Reference to X-Bus or A-Bus or MCS or memBuf Target - * @param[out] o_txFailLanes Reference to a Vector that will contain the fail - * lanes read from the Field VPD for Drive side - * @param[out] o_rxFailLanes Reference to a Vector that will contain the fail - * lanes read from the Field VPD for Receive side - * @return ReturnCode - * - */ -fapi::ReturnCode erepairGetFieldFailedLanes(const fapi::Target &i_endp_target, - std::vector<uint8_t> &o_txFailLanes, - std::vector<uint8_t> &o_rxFailLanes); - -/** - * @brief FW Team Utility function that gets eRepair data - * - * This is a wrapper function for the Accessor HWP which reads failed lane - * numbers from the Manufacturing VPD - * - * @param[in] i_endp_target Reference to X-Bus or A-Bus or MCS or memBuf Target - * @param[out] o_txFailLanes Reference to a Vector that will contain the fail - * lanes read from the Mnfg VPD for Drive side - * @param[out] o_rxFailLanes Reference to a Vector that will contain the fail - * lanes read from the Mnfg VPD for Receive side - * @return ReturnCode - * - */ -fapi::ReturnCode erepairGetMnfgFailedLanes(const fapi::Target &i_endp_target, - std::vector<uint8_t> &o_txFailLanes, - std::vector<uint8_t> &o_rxFailLanes); - -/** - * @brief FW Team Utility function that sets eRepair data in the VPD. - * This functions sets the eRepair data to either the Field VPD - * or the Manufacturing VPD depending on whether the IPL was done - * in normal mode or Manufacturing mode. - * It writes eRepair data to the VPD of both the endpoint targets - * passed as arguments. - * - * @param[in] i_txEndp_target Reference to X-Bus or A-Bus or MCS or memBuf - * Target. This is the peer target of - * i_rxEndp_target - * @param[in] i_rxEndp_target Reference to X-Bus or A-Bus or MCS or memBuf - * Target. This is the target on which the - * badlanes were found - * @param[in] i_rxFailLanes Vector that will contain the fail lanes - * to be written to VPD for Receive side - * @param[out] o_thresholdExceed If TRUE, indicates that the eRepair threshold - * has exceeded, FALSE otherwise. - * - * @return ReturnCode - */ -fapi::ReturnCode erepairSetFailedLanes( - const fapi::Target &i_txEndp_target, - const fapi::Target &i_rxEndp_target, - const std::vector<uint8_t> &i_rxFailLanes, - bool &o_thresholdExceed); - -/** - * @brief FW Team Utility function that sets eRepair data in Field VPD - * - * This is a wrapper function for the Accessor HWP which writes failed lane - * numbers to the Field VPD - * - * @param[in] i_endp_target Reference to X-Bus or A-Bus or MCS or memBuf Target - * @param[in] i_txFailLanes Vector that will contain the fail lane - * to be written to Field VPD for Drive side - * @param[in] i_rxFailLanes Vector that will contain the fail lanes - * to be written to Field VPD for Receive side - * - * @return ReturnCode - */ -fapi::ReturnCode erepairSetFieldFailedLanes( - const fapi::Target &i_endp_target, - const std::vector<uint8_t> &i_txFailLanes, - const std::vector<uint8_t> &i_rxFailLanes); - -/** - * @brief FW Team Utility function that sets eRepair data in Manufacturing VPD - * - * This is a wrapper function for the Accessor HWP which writes failed lane - * numbers to the Manufacturing VPD - * - * @param[in] i_endp_target Reference to X-Bus or A-Bus or MCS or memBuf Target - * @param[in] i_txFailLanes Vector that will contain the fail lane - * to be written to Mnfg VPD for Drive side - * @param[in] i_rxFailLanes Vector that will contain the fail lanes - * to be written to Mnfg VPD for Receive side - * - * @return ReturnCode - */ -fapi::ReturnCode erepairSetMnfgFailedLanes( - const fapi::Target &i_endp_target, - const std::vector<uint8_t> &i_txFailLanes, - const std::vector<uint8_t> &i_rxFailLanes); - -/** - * @brief Function which retrieves the lanes that need to be restored for the - * given end point targets - * - * This function is called by the iStep dispatcher during the Restore Repair - * iStep for Fabric buses and DMI buses. The caller need to make sure that the - * first and fourth arguments are the endpoint targets of a Fabric bus or - * DMI bus. - * It calls the wrapper functions of Accessor HWP to read the fail lane data - * recorded in the VPD on both the ends and verifies that there are matching - * records on both the ends. If matching fail lanes are not found, the - * corresponding fail lane data is invalidated using the wrapper Accessor HWP - * that writes data to the VPD. - * - * @param [in] i_endp1_target Reference to X-Bus or A-Bus or MCS Target - * @param [out] o_endp1_txFaillanes Reference to vector that will have the - * fail lane numbers that need to be restored - * for the Tx side of the target passed - * as first param - * @param [out] o_endp1_rxFaillanes Reference to vector that will have the - * fail lane numbers that need to be restored - * for the Rx side of the target passed - * as first param - * @param [in] i_endp2_target Reference to X-Bus or A-Bus or MCS Target - * @param [out] o_endp2_txFaillanes Reference to vector that will have the - * fail lane numbers that need to be restored - * for the Tx side of the target passed - * as fourth param - * @param [out] o_endp2_rxFaillanes Reference to vector that will have the - * fail lane numbers that need to be restored - * for the Rx side of the target passed - * as fourth param - * - * @return ReturnCode - * - */ - -fapi::ReturnCode erepairGetRestoreLanes(const fapi::Target &i_endp1_target, - std::vector<uint8_t> &o_endp1_txFaillanes, - std::vector<uint8_t> &o_endp1_rxFaillanes, - const fapi::Target &i_endp2_target, - std::vector<uint8_t> &o_endp2_txFaillanes, - std::vector<uint8_t> &o_endp2_rxFaillanes); - -#endif diff --git a/src/include/usr/hwpf/hwp/erepairConsts.H b/src/include/usr/hwpf/hwp/erepairConsts.H deleted file mode 100644 index 0ad6684e9..000000000 --- a/src/include/usr/hwpf/hwp/erepairConsts.H +++ /dev/null @@ -1,184 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/erepairConsts.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: erepairConsts.H,v 1.3 2014/04/29 11:59:35 bilicon Exp $ -/** - * @file eRepairConsts.H - * - * @brief eRepair Constants - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * bilicon 09/14/2012 Created. - */ - -#ifndef EREPAIRCONSTS_H_ -#define EREPAIRCONSTS_H_ - - -/****************************************************************************** - * Erepair constants - *****************************************************************************/ - -namespace EREPAIR -{ - -const uint8_t INVALID_FAIL_LANE_NUMBER = 0xFF; - -// X-Bus is 78+2 lanes wide in 8 byte mode -// X-Bus is 44+2 lanes wide in 4 byte mode -// Data lanes numbering: 0 - 77 in 8 byte mode -// Spare lanes numbering: 78, 79 in 8 byte mode -// Data lanes numbering: 0 - 43 in 4 byte mode -// Spare lanes numbering: 44, 45 in 8 byte mode -const uint8_t XBUS_8_ACTIVE_LANE_START = 0; -const uint8_t XBUS_8_ACTIVE_LANE_END = 77; - -const uint8_t XBUS_4_ACTIVE_LANE_START = 0; -const uint8_t XBUS_4_ACTIVE_LANE_END = 43; - -const uint8_t XBUS_SPARE_DEPLOY_LANE_1 = 0; -const uint8_t XBUS_SPARE_DEPLOY_LANE_2 = 1; -const uint8_t XBUS_MAXSPARES_IN_HW = 2; - -// A-Bus is 21+1 lanes wide. -// Data lanes numbering: 0 - 20 -// Spare lane numbering: 21 -const uint8_t ABUS_ACTIVE_LANE_START = 0; -const uint8_t ABUS_ACTIVE_LANE_END = 20; - -const uint8_t ABUS_SPARE_DEPLOY_LANE_1 = 0; -const uint8_t ABUS_MAXSPARES_IN_HW = 1; - -// UpStream DMI-Bus is 21+2 lanes wide. -// Data lanes numbering: 0 - 20 -// Spare lanes numbering: 21, 22 -const uint8_t DMIBUS_UPSTREAM_ACTIVE_LANE_START = 0; -const uint8_t DMIBUS_UPSTREAM_ACTIVE_LANE_END = 20; - -// DownStream DMI-Bus is 14+2 lanes wide. -// Data lanes numbering: 0 - 13 -// Spare lanes numbering: 14, 15 -const uint8_t DMIBUS_DOWNSTREAM_ACTIVE_LANE_START = 0; -const uint8_t DMIBUS_DOWNSTREAM_ACTIVE_LANE_END = 13; - -const uint8_t DMIBUS_SPARE_DEPLOY_LANE_1 = 0; -const uint8_t DMIBUS_SPARE_DEPLOY_LANE_2 = 1; -const uint8_t DMIBUS_MAXSPARES_IN_HW = 2; - -const uint32_t EREPAIR_P8_MODULE_VPD_FIELD_SIZE = 0x154; // 340 bytes -const uint32_t EREPAIR_P8_MODULE_VPD_MNFG_SIZE = 0xC4; // 196 bytes -const uint32_t EREPAIR_MEM_FIELD_VPD_SIZE_PER_CENTAUR = 0x1C; // 28 bytes -const uint32_t EREPAIR_MEM_MNFG_VPD_SIZE_PER_CENTAUR = 0x14; // 20 bytes - -enum busType -{ - UNKNOWN_BUS_TYPE = 0, - PROCESSOR_EI4 = 1, - PROCESSOR_EDI = 2, - MEMORY_EDI = 3 -}; - -enum interfaceType -{ - UNKNOWN_INT_TYPE = 0, - PBUS_DRIVER = 1, // X-Bus, A-Bus transmit - PBUS_RECEIVER = 2, // X-Bus, A-Bus receive - DMI_MCS_RECEIVE = 3, // MCS receive - DMI_MCS_DRIVE = 4, // MCS transmit - DMI_MEMBUF_RECEIVE = 5, // Centaur receive - DMI_MEMBUF_DRIVE = 6, // Centaur transmit - DRIVE = 7, // Tx - RECEIVE = 8 // Rx -}; - -// VPD Type to read-write -enum erepairVpdType -{ - EREPAIR_VPD_UNKNOWN = 0, - EREPAIR_VPD_MNFG = 1, - EREPAIR_VPD_FIELD = 2, -}; - -}// end of EREPAIR namespace - -/****************************************************************************** - * VPD Structures. - *****************************************************************************/ - -// eRepair Header -struct eRepairHeader -{ - struct - { - uint8_t eye1; - uint8_t eye2; - uint8_t eye3; - }eyeCatcher; - - uint8_t numRecords; -}; - -// Device info structure of the P8 Processor -struct eRepairProcDevInfo -{ - uint8_t processor_id;// Range:0x00-0xFF. Value:Processor MRU IDs - uint8_t fabricBus; // Range:0x00-0xFF. Value: FabricBus(ATTR_CHIP_UNIT_POS) -}; - -// eRepair structure for failing lanes on Power Bus -struct eRepairPowerBus -{ - eRepairProcDevInfo device; // Device info of P8 - uint8_t type :4; // Range:0x0-0xF. Value:PROCESSOR_EI4, - // PROCESSOR_EDI - uint8_t interface :4; // Range:0x0-0xF. Value:PBUS_DRIVER, - // PBUS_RECEIVER - uint8_t failBit; // Range:0x00-0xFF. Value:Failing lane number -}; - - -// Device info structure of the endpoints of the Memory Channel -struct eRepairMemDevInfo -{ - uint8_t proc_centaur_id;// Range:0x00-0xFF.Value:Processor or Centaur MRU ID - uint8_t memChannel; // Range:0x00-0xFF.Value: MemoryBus(ATTR_CHIP_UNIT_POS) -}; - -// eRepair structure of failing lanes on Memory Channel -struct eRepairMemBus -{ - eRepairMemDevInfo device; // Device info of P8 and Centaur - uint8_t type :4;// Range:0x0-0xF. Value:MEMORY_EDI - uint8_t interface :4;// Range:0x0-0xF. Value:MCS_Receive, - // MCS_Drive, - // memBuf_Receive, - // memBuf_Drive - uint8_t failBit; // Range:0x00-0xFF. - // Value:Failing lane number:0-13 OR 0-20 - // depends on DownStream or UpStream -}; - -#endif diff --git a/src/include/usr/hwpf/hwp/erepairGetFailedLanesHwp.H b/src/include/usr/hwpf/hwp/erepairGetFailedLanesHwp.H deleted file mode 100644 index bcbc7b3a8..000000000 --- a/src/include/usr/hwpf/hwp/erepairGetFailedLanesHwp.H +++ /dev/null @@ -1,78 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/erepairGetFailedLanesHwp.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: erepairGetFailedLanesHwp.H,v 1.3 2014/04/29 11:59:55 bilicon Exp $ -/** - * @file erepairGetFailedLanesHwp.H - * - * @brief FW Team HWP that accesses the fail lanes of Fabric and Memory buses. - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * bilicon 09/14/2012 Created. - */ - -#ifndef EREPAIRGETFAILEDLANESHWP_H_ -#define EREPAIRGETFAILEDLANESHWP_H_ - -#include <fapi.H> -#include <erepairConsts.H> - - -typedef fapi::ReturnCode (*erepairGetFailedLanesHwp_FP_t)( - const fapi::Target &i_tgtHandle, - EREPAIR::erepairVpdType i_vpdType, - std::vector<uint8_t> &o_txFailLanes, - std::vector<uint8_t> &o_rxFailLanes); - -extern "C" -{ - -/** - * @brief FW Team HWP that retrieves the eRepair fail lanes. - * It retrieves the eRepair data from the P8 MVPD and the Centaur FRU - * VPD sections depending on the passed target type. It then parses the - * eRepair data to determine the fail lane numbers on the sub-interfaces - * (Tx and Rx) of the passed bus target. - * - * @param[in] i_tgtHandle Reference to X-Bus or A-Bus or MCS or memBuf Target - * @param[in] i_vpdType Specifies which VPD (MNFG or Field) to access. - * @param[o] o_txFailLanes Reference to a vector that will hold eRepair fail - * lane numbers of the Tx sub-interface. - * @param[o] o_rxFailLanes Reference to a vector that will hold eRepair fail - * lane numbers of the Rx sub-interface. - * - * @return ReturnCode - * - */ -fapi::ReturnCode erepairGetFailedLanesHwp( - const fapi::Target &i_tgtHandle, - EREPAIR::erepairVpdType i_vpdType, - std::vector<uint8_t> &o_txFailLanes, - std::vector<uint8_t> &o_rxFailLanes); - -}// end of extern C - -#endif diff --git a/src/include/usr/hwpf/hwp/erepairSetFailedLanesHwp.H b/src/include/usr/hwpf/hwp/erepairSetFailedLanesHwp.H deleted file mode 100755 index 52f58e77e..000000000 --- a/src/include/usr/hwpf/hwp/erepairSetFailedLanesHwp.H +++ /dev/null @@ -1,78 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/erepairSetFailedLanesHwp.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: erepairSetFailedLanesHwp.H,v 1.2 2014/04/30 09:45:10 bilicon Exp $ -/** - * @file erepairSetFailedLanesHwp.H - * - * @brief FW Team HWP that accesses the fail lanes of Fabric and Memory buses. - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * bilicon 10-Jan-2013 Created. - */ - -#ifndef EREPAIRSETFAILEDLANESHWP_H_ -#define EREPAIRSETFAILEDLANESHWP_H_ - -#include <fapi.H> -#include <erepairConsts.H> - - -typedef fapi::ReturnCode (*erepairSetFailedLanesHwp_FP_t)( - const fapi::Target &i_tgtHandle, - EREPAIR::erepairVpdType i_vpdType, - const std::vector<uint8_t> &i_txFailLanes, - const std::vector<uint8_t> &i_rxFailLanes); - -extern "C" -{ - -/** - * @brief FW Team HWP that writes the eRepair fail lanes to the VPD. - * The fail lanes will be written to either the P8 MVPD or the - * Centaur FRU VPD depending on the passed target type. - * - * @param[in] i_tgtHandle Reference to X-Bus or A-Bus or MCS or memBuf Target - * @param[in] i_vpdType Specifies which VPD (MNFG or Field) to access. - * @param[in] i_txFailLanes Reference to a vector that has the Tx side - * (of i_tgtHandle) fail lane numbers that need - * to be written to the VPD - * @param[in] i_rxFailLanes Reference to a vector that has the Rx side - * (of i_tgtHandle) fail lane numbers that need - * to be written to the VPD - * - * @return ReturnCode - * - */ -fapi::ReturnCode erepairSetFailedLanesHwp( - const fapi::Target &i_tgtHandle, - EREPAIR::erepairVpdType i_vpdType, - const std::vector<uint8_t> &i_txFailLanes, - const std::vector<uint8_t> &i_rxFailLanes); - -}// end of extern C - -#endif diff --git a/src/include/usr/hwpf/hwp/fapiHwpExecInitFile.H b/src/include/usr/hwpf/hwp/fapiHwpExecInitFile.H deleted file mode 100644 index 9e8f573ab..000000000 --- a/src/include/usr/hwpf/hwp/fapiHwpExecInitFile.H +++ /dev/null @@ -1,68 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/fapiHwpExecInitFile.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -/** - * @file fapiHwpExecInitFile.H - * - * @brief Defines for Hardware Procedure initfile execution - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * camvanng 09/29/2011 Created. - * andrewg 11/16/2011 Refactor includes with initfile compiler - * camvanng 11/16/2011 Define function pointer to HWP - * camvanng 05/07/2012 Support for associated target attributes - * - */ - -#ifndef FAPIHWPEXECINITFILE_H_ -#define FAPIHWPEXECINITFILE_H_ - -#include <fapi.H> -#include <fapiHwpInitFileInclude.H> - -// HWPs are defined as C functions because platforms may wish to package them -// in linux shared libraries which are DL-Opened -extern "C" -{ - -//Provided for platforms that need to cast a generic function pointer into a -//function pointer of the correct type to call the HWP. -typedef fapi::ReturnCode (*fapiHwpExecInitFile_FP_t)(const std::vector<fapi::Target> & i_target, - const char * i_file); -/** -* @brief HWP to execute an initfile. -* -* @param[in] i_target Reference to std::vector of targets -* @param[in] i_file filename of binary initfile -* -* @return ReturnCode -*/ -fapi::ReturnCode fapiHwpExecInitFile(const std::vector<fapi::Target> & i_target, - const char * i_file); - -} // extern "C" - -#endif // FAPIHWPEXECINITFILE_H_ diff --git a/src/include/usr/hwpf/hwp/fapiHwpInitFileInclude.H b/src/include/usr/hwpf/hwp/fapiHwpInitFileInclude.H deleted file mode 100644 index 93e41935e..000000000 --- a/src/include/usr/hwpf/hwp/fapiHwpInitFileInclude.H +++ /dev/null @@ -1,131 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/fapiHwpInitFileInclude.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2011,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -/** - * @file fapiHwpInitFileInclude.H - * - * @brief Common defines for Hardware Procedure initfile execution - */ -// $Id: fapiHwpInitFileInclude.H,v 1.4 2014/06/27 19:20:10 thi Exp $ -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * andrewg 11/09/2011 Created. - * camvanng 11/16/2011 Support for system & target - * attributes - * camvanng 05/07/2012 Support for associated - * target attributes - * camvanng 06/15/2012 Ability to do bitwise OR and - * AND operations - */ - -#ifndef FAPIHWPINITFILEINCLUDE_H_ -#define FAPIHWPINITFILEINCLUDE_H_ - -/** - * @brief Enumeration of RPN ops - */ -enum IfRpnOp -{ - AND = 0x00000001, - OR = 0x00000002, - NOT = 0x00000003, - EQ = 0x00000004, - NE = 0x00000005, - GT = 0x00000006, - GE = 0x00000007, - LT = 0x00000008, - LE = 0x00000009, - PLUS = 0x0000000A, - MINUS = 0x0000000B, - MULT = 0x0000000C, - DIVIDE = 0x0000000D, - MOD = 0x0000000E, - LIST = 0x0000000F, - SHIFTLEFT = 0x00000010, - SHIFTRIGHT = 0x00000011, - FALSE_OP = 0x00000012, - TRUE_OP = 0x00000013, - BITWISEAND = 0x00000014, - BITWISEOR = 0x00000015, - LAST_OP = 0x00000016, - PUSH_MASK = 0x000000C0, - OP_MASK = 0x000000FF -}; - -/** - * @brief Enumeration of Type Mask - */ -enum IfTypeMask -{ - IF_NUM_TYPE = 0x4000, - IF_ATTR_TYPE = 0x8000, - IF_SYS_ATTR_TYPE = 0xA000, - IF_ASSOC_TGT_ATTR_TYPE = 0xC000, - IF_TYPE_MASK = 0xE000, -}; - -// Id mask -const uint16_t IF_ID_MASK = static_cast<uint16_t>(~IF_TYPE_MASK); - -// Only support up to 4 dimensions for an array -const uint8_t MAX_ATTRIBUTE_ARRAY_DIMENSION = 4; - -// Used for array size parsing -const uint8_t ATTR_DIMENSION_MASK = 0xF0; - -// Most significant nibble in 1 byte attribute type will indicate array dimension -const uint8_t ATTR_DIMENSION_SIZE_MULT = 0x10; - -/** - * @brief Enumeration of Attribute types - * - * Note that the most significant nibble is used to determine dimension size - * by the procedure executing the initfile. - */ -enum IfAttrType -{ - SYM_ATTR_UINT8_TYPE = 0x00, - SYM_ATTR_UINT8_ARRAY1_TYPE = 0x11, - SYM_ATTR_UINT8_ARRAY2_TYPE = 0x22, - SYM_ATTR_UINT8_ARRAY3_TYPE = 0x33, - SYM_ATTR_UINT8_ARRAY4_TYPE = 0x44, - SYM_ATTR_UINT32_TYPE = 0x05, - SYM_ATTR_UINT32_ARRAY1_TYPE = 0x16, - SYM_ATTR_UINT32_ARRAY2_TYPE = 0x27, - SYM_ATTR_UINT32_ARRAY3_TYPE = 0x38, - SYM_ATTR_UINT32_ARRAY4_TYPE = 0x49, - SYM_ATTR_UINT64_TYPE = 0x0A, - SYM_ATTR_UINT64_ARRAY1_TYPE = 0x1B, - SYM_ATTR_UINT64_ARRAY2_TYPE = 0x2C, - SYM_ATTR_UINT64_ARRAY3_TYPE = 0x3D, - SYM_ATTR_UINT64_ARRAY4_TYPE = 0x4E, -}; - - - - -#endif /* FAPIHWPINITFILEINCLUDE_H_ */ - diff --git a/src/include/usr/hwpf/hwp/fapiTestHwp.H b/src/include/usr/hwpf/hwp/fapiTestHwp.H deleted file mode 100644 index 52f4c5745..000000000 --- a/src/include/usr/hwpf/hwp/fapiTestHwp.H +++ /dev/null @@ -1,63 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/fapiTestHwp.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -/** - * @file fapiTestHwp.H - * - * @brief Defines a simple test Hardware Procedure - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * mjjones 04/21/2011 Created. - * mjjones 06/28/2011 Updated comment - * mjjones 08/11/2011 Removed Clock HWP - * mjjones 10/17/2011 Added func pointer - * camvanng 05/07/2012 Support for associated - * attributes - */ - -#ifndef FAPITESTHW_H_ -#define FAPITESTHW_H_ - -#include <fapi.H> -#include <vector> - -typedef fapi::ReturnCode (*hwpInitialTest_FP_t)(const std::vector<fapi::Target> &); - -extern "C" -{ - -/** - * @brief A simple HWP. Can easily be modified by HW dev team for test - * - * @param[in] i_target Reference to std::vector of targets - * - * @return ReturnCode - */ -fapi::ReturnCode hwpInitialTest(const std::vector<fapi::Target> & i_target); - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/fapiTestHwpConfig.H b/src/include/usr/hwpf/hwp/fapiTestHwpConfig.H deleted file mode 100644 index d34006e98..000000000 --- a/src/include/usr/hwpf/hwp/fapiTestHwpConfig.H +++ /dev/null @@ -1,59 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/fapiTestHwpConfig.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -/** - * @file fapiTestHwpConfig.H - * - * @brief Defines a Hardware Procedure that exercises the FAPI System Config - * Query functions. - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * mjjones 09/12/2011 Created. - * mjjones 10/17/2011 Added func pointer - */ - -#ifndef FAPITESTHWCONFIG_H_ -#define FAPITESTHWCONFIG_H_ - -#include <fapi.H> - -typedef fapi::ReturnCode (*hwpTestConfig_FP_t)(const fapi::Target &); - -extern "C" -{ - -/** - * @brief A simple HWP that exercises the FAPI System Config Query functions. - * - * @param[in] i_chip Reference to target processor chip - * - * @return ReturnCode - */ -fapi::ReturnCode hwpTestConfig(const fapi::Target & i_chip); - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/fapiTestHwpDq.H b/src/include/usr/hwpf/hwp/fapiTestHwpDq.H deleted file mode 100644 index ee7115117..000000000 --- a/src/include/usr/hwpf/hwp/fapiTestHwpDq.H +++ /dev/null @@ -1,57 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/fapiTestHwpDq.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -/** - * @file fapiTestHwpDq.H - * - * @brief Test Hardware Procedure that exercises the bad DQ data - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * mjjones 02/21/2012 Created - */ - -#ifndef FAPITESTHWPDQ_H_ -#define FAPITESTHWPDQ_H_ - -#include <fapi.H> - -typedef fapi::ReturnCode (*fapiTestHwpDq_FP_t)(const fapi::Target &); - -extern "C" -{ - -/** - * @brief Test Hardware Procedure that exercises the bad DQ data - * - * @param[in] i_mba Reference to MBA chiplet - * - * @return ReturnCode - */ -fapi::ReturnCode fapiTestHwpDq(const fapi::Target & i_mba); - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/fapiTestHwpError.H b/src/include/usr/hwpf/hwp/fapiTestHwpError.H deleted file mode 100644 index a0324e3cf..000000000 --- a/src/include/usr/hwpf/hwp/fapiTestHwpError.H +++ /dev/null @@ -1,62 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/fapiTestHwpError.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -/** - * @file fapiTestHwpError.H - * - * @brief Defines a simple test Hardware Procedure that returns an error - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * mjjones 08/08/2011 Created. - * mjjones 10/17/2011 Added func pointer - * rjknight 09/30/2013 Add 2nd target to fctn ptr - */ - -#ifndef FAPITESTHWPERROR_H_ -#define FAPITESTHWPERROR_H_ - -#include <fapi.H> - -typedef fapi::ReturnCode (*hwpTestError_FP_t)(const fapi::Target &T1, - const fapi::Target &T2); - -extern "C" -{ - -/** - * @brief Simple HWP that returns an error (RC_TEST_ERROR_A) - * - * @param[in] i_procTarget Reference to a processor target type - * @param[in] i_mbaTarget Reference to an mba target type - * - * @return ReturnCode - */ - fapi::ReturnCode hwpTestError(const fapi::Target& i_procTarget, - const fapi::Target& i_mbaTarget); - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/fapiTestHwpFfdc.H b/src/include/usr/hwpf/hwp/fapiTestHwpFfdc.H deleted file mode 100644 index a0dd9ee77..000000000 --- a/src/include/usr/hwpf/hwp/fapiTestHwpFfdc.H +++ /dev/null @@ -1,60 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/fapiTestHwpFfdc.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2011,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -/** - * @file fapiTestHwpFfdc.H - * - * @brief Defines a simple test Hardware Procedure that collects FFDC data - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * mjjones 08/08/2011 Created. - * mjjones 10/17/2011 Added func pointer - */ - -#ifndef FAPITESTHWPFFDC_H_ -#define FAPITESTHWPFFDC_H_ - -#include <fapi.H> - -typedef fapi::ReturnCode (*hwpTestFfdc1_FP_t)(const fapi::Target &, fapi::ReturnCode &); - -extern "C" -{ - -/** - * @brief Simple FFDC HWP that collects TestFfdc1 data - * - * @param[in] i_target Reference to target (unused by this HWP) - * @param[out] o_rc Reference to ReturnCode that is updated with FFDC - * - * @return ReturnCode - */ -fapi::ReturnCode hwpTestFfdc1(const fapi::Target & i_target, - fapi::ReturnCode & o_rc); - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/DQCompressionLib.H b/src/include/usr/hwpf/hwp/mvpd_accessors/DQCompressionLib.H deleted file mode 100644 index 6b14c5081..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/DQCompressionLib.H +++ /dev/null @@ -1,72 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/DQCompressionLib.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -//$Id: DQCompressionLib.H,v 1.7 2014/11/12 20:03:25 pragupta Exp $ - -/* @file DQCompressionLib.H - * - * @brief Header file DQCompressionLib - * - */ - -#ifndef __DQCOMPRESSIONLIB_H -#define __DQCOMPRESSIONLIB_H - -#include <ecmdDataBufferBase.H> -#include <vector> -#include <algorithm> -#include <string.h> -#include <stdio.h> -#ifdef DQCOMPRESSION_TEST -#define DQ_TRAC(fmt,args...) FAPI_INF (fmt, ##args) -#else -#define DQ_TRAC(fmt,args...) printf(fmt, ##args) -#endif -namespace DQCompression -{ - //ERROR CODES - //Mapping of these error codes to error messages - //are in DQCompressionReasonCodes.H - enum ErrCodes - { - NO_ERR = 0, - ECMD_OPER_ERROR, - INVALID_INPUT, - INVALID_ARRAY_TYPE, - LAST_ERR, - }; -/** - * @brief Calculates the encoding for DQ or DQS arrays for one port - * to be stored in VPD - * @param i_data DQ or DQS array as a vector - * @param i_arrayType type of array being passed in (DQ/DQS) - * @param o_encodeData: 17 bytes of data for DQ and - * 2 bytes of data for DQS - * @retval ErrCodes Values - */ - int encodeDQ (std::vector<uint8_t>& i_data, - uint32_t i_arrayType, ecmdDataBufferBase& o_encodedData); -} -#endif - diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/accessMBvpdL4BankDelete.H b/src/include/usr/hwpf/hwp/mvpd_accessors/accessMBvpdL4BankDelete.H deleted file mode 100644 index 54ce1ff52..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/accessMBvpdL4BankDelete.H +++ /dev/null @@ -1,71 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/accessMBvpdL4BankDelete.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: accessMBvpdL4BankDelete.H,v 1.2 2013/11/21 17:17:30 whs Exp $ -/** - * @file accessMBvpdL4BankDelete.H - * - * @brief MBvpd accessor for the ATTR_L4_BANK_DELETE_VPD attribute - */ - -#ifndef _HWP_ACCESSMBVPDL4BANKDELETE_ -#define _HWP_ACCESSMBVPDL4BANKDELETE_ - -#include <fapi.H> - -namespace fapi -{ - -// mode - enum MBvpdL4BankDeleteMode - { - GET_L4_BANK_DELETE_MODE = 0, // retrieve value from vpd - SET_L4_BANK_DELETE_MODE = 1, // update value in vpd - }; -} - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*accessMBvpdL4BankDelete_FP_t) - (const fapi::Target &, - uint32_t &, - const fapi::MBvpdL4BankDeleteMode); - -extern "C" -{ -/** - * @brief MBvpd accessor for the ATTR_L4_BANK_DELETE_VPD attribute - * - * Access L4 Bank Delete value in MBvpd record VSPD keyword MX. - * - * @param[in] i_mbTarget - Reference to mb Target - * @param[in,out] io_val - retrived MX value or value to use to update MX vpd - * @param[in] i_mode - set or get mode - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ -fapi::ReturnCode accessMBvpdL4BankDelete( - const fapi::Target & i_mbTarget, - uint32_t & io_val, - const fapi::MBvpdL4BankDeleteMode i_mode ); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getControlCapableData.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getControlCapableData.H deleted file mode 100644 index 8e68566eb..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getControlCapableData.H +++ /dev/null @@ -1,51 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getControlCapableData.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $ID: getControlCapableData.H, v 1.1 2014/9/4 09:05:00 eliner Exp $ -/** - * @file getControlCapable.H - * - * @brief MBvpd accessor for the ATTR_VPD_POWER_CONTROL_CAPABLE attributes - */ - -#ifndef _HWP_MVPDCONTROLCAPABLEDATA_ -#define _HWP_MVPDCONTROLCAPABLEDATA_ - -extern "C" -{ -/** - * @brief MBvpd accessor for the ATTR_VPD_POWER_CONTROL_CAPABLE attribute - * - * Access Power control capable value in MBvpd record VSPD keyword MR - * - * @param[in] i_mbTarget - Reference to mb Target - * @param[out] o_val - retrieved MR value - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ -fapi::ReturnCode getControlCapableData(const fapi::Target &i_mbTarget, - uint8_t & o_val); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getDQAttrISDIMM.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getDQAttrISDIMM.H deleted file mode 100644 index 92ac0e59d..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getDQAttrISDIMM.H +++ /dev/null @@ -1,58 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getDQAttrISDIMM.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $ID: getDQAttrISDIMM.H, v 1.1 2014/9/25 04:38:00 eliner Exp $ -/* - * @file getDQAttrISDIMM.H - * - * @brief MBvpd accessor for the ATTR_VPD_ISDIMMTOC4DQ attribute - */ - -#ifndef _HWP_MVPDGETDQATTRISDIMM_ -#define _HWP_MVPDGETDQATTRISDIMM_ - -typedef fapi::ReturnCode (*getDQAttrISDIMM_FP_t) - (const fapi::Target &, - uint8_t (&)[4][80]); - -extern "C" -{ - -/* - * @brief MBvpd accessor for the ATTR_VPD_ISDIMMTOC4DQ attribute - * - * Access the compressed DQ data in the MBvpd record SPDX, keyword Q1-Q9 - * - * @param[in] i_mbTarget - Reference to mb Target - * @param[out] o_val[4][80] - Decoded Q data - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ - -fapi::ReturnCode getDQAttrISDIMM( - const fapi::Target &i_mbTarget, - uint8_t (&o_val)[4][80]); - -} -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getDQSAttrISDIMM.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getDQSAttrISDIMM.H deleted file mode 100644 index 593e669fd..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getDQSAttrISDIMM.H +++ /dev/null @@ -1,57 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getDQSAttrISDIMM.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $ID: getDQSAttrISDIMM.H, v 1.1 2014/9/25 04:38:00 eliner Exp $ -/* - * @file getDQSAttrISDIMM.H - * - * @brief MBvpd accessor for the ATTR_VPD_ISDIMMTOC4DQS attribute - */ - -#ifndef _HWP_MVPDGETDQSATTRISDIMM_ -#define _HWP_MVPDGETDQSATTRISDIMM_ - -typedef fapi::ReturnCode (*getDQSAttrISDIMM_FP_t) - (const fapi::Target &, - uint8_t (&)[4][20]); - -extern "C" -{ -/* - * @brief MBvpd accessor for the ATTR_VPD_ISDIMMTOC4DQS attribute - * - * Access the compressed DQS data in the MBvpd record, SPDX, keyword K1-K9 - * - * @param[in] i_mbTarget - Reference to mb Target - * @param[out] o_val[4][20] - Decoded K data - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ - -fapi::ReturnCode getDQSAttrISDIMM( - const fapi::Target &i_mbTarget, - uint8_t (&o_val)[4][20]); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getDecompressedISDIMMAttrs.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getDecompressedISDIMMAttrs.H deleted file mode 100644 index 8a46ac8a1..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getDecompressedISDIMMAttrs.H +++ /dev/null @@ -1,109 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getDecompressedISDIMMAttrs.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $ID: getDecompressedISDIMMAttrs.H, v 1.1 2014/9/26 09:22:00 eliner Exp $ -/** - * @file getDecompressedISDIMMAttrs.H - * - * @brief Decompresses the ISDIMMToC4DQ and DQS Attributes for proper use - */ -extern "C" -{ - -/** - * @brief Un-permeates the decimal input into an array of variable size - * - * @param[in] i_permNum - Decimal number to un-permeate - * @param[in] i_finalSize - Final Size of the variable array - * @param[out] o_array - Created Array of un-permeated numbers - */ -void antiPermutation(int i_permNum, int* o_array,int i_finalSize); - -/** - * @brief Translates the array from the condensed version to the - * actual information - * example: [1,0,0,5,1,1,1,1,0] -> [1,0,2,8,4,5,6,7,3] - * - * @param[in] i_array - condensed array of information - * @param[in] i_size - size of array - * @param[out] o_result - translated array of information - */ -void unPermeateToVector(int* i_array, int i_size, std::vector<int>& o_result); - -/** - * @brief Separates the input into the 4 needed parts; nibble swap, nibble - * to nibble relationship, DQS nibble swap, and the byte to - * byte relationship - * - * @param[in] i_toSeparateDQ - contains all the information for DQ - * @param[in] i_toSeparateDQS - contains all the information for DQS - * @param[out] o_nibSwap - DQ nibble swap information - * @param[out] o_nibToNib - nibble to nibble relationship - * @param[out[ o_nibSwapDQS - DQS nibble swap information - * - * @return int - byte to byte relationship information - */ -int getSeparatedInformation(ecmdDataBufferBase& i_toSeparateDQ, - ecmdDataBufferBase& i_separateDQS, - int* o_nibSwap,int* o_nibToNib,int* o_nibSwapDQS); - -/** - * @brief Converts all information into the final DQ 80-byte array - * - * @param[out] o_final80Array - completed decompressed array - * @param[in] i_byteNums - translated relationship between the bytes - * @param[in] i_nibbleSwap - translated DQ nibble swap information - * @param[in] i_nibbleToNibNums - translated relationship between the nibbles - */ -void convertToFinal80Array(int* o_final80Array, - std::vector<int>& i_byteNums,int* i_nibbleSwap, - std::vector<std::vector<int> >& i_nibbleToNibNums); - -/** - * @brief Converts all the information into the final dQS 20-byte array - * - * @param[out] o_final20Array - completed decompressed array - * @param[in] i_byteNums - translated relationship between the bytes - * @param[in] i_nibbleSwap - translated DQS nibble swap information - */ -void convertToFinal20Array(int* o_final20Array,std::vector<int>& i_byteNums, - int* i_nibbleSwap); - -/** - * @brief Controls the flow of data from the different functions - * - * @param[in] i_dataDQ - original DQ information before any processing - * @param[in] i_dataDQS - original DQS information before any processing - * @param[out] o_finalArray - completed DQ decompressed array - * @param[out] o_finalDQSArray - completed DQS decompressed array - */ -void decodeISDIMMAttrs(ecmdDataBufferBase& i_dataDQ, - ecmdDataBufferBase& i_dataDQS, - uint8_t* o_finalArray, uint8_t* o_finalDQSArray); - -} - - - - diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getISDIMMTOC4DAttrs.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getISDIMMTOC4DAttrs.H deleted file mode 100644 index 83bdd9db0..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getISDIMMTOC4DAttrs.H +++ /dev/null @@ -1,56 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getISDIMMTOC4DAttrs.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $ID: getISDIMMTOC4DAttrs.H, v 1.1 2014/9/25 04:38:00 eliner Exp $ -/* - * @file getISDIMMTOC4DAttrs.H - * - * @brief MBvpd accessor for the ATTR_VPD_ISDIMMTOC4DQ and DQS attributes - */ - -#ifndef _HWP_MVPDGETISDIMMTOC4DATTRS_ -#define _HWP_MVPDGETISDIMMTOC4DATTRS_ - -extern "C" -{ -const uint32_t DQ_KEYWORD_SIZE = 96; - -/* - * @brief Utility function for the ATTR_VPD_ISDIMMTOC4DQ attribute - * - * Given the D0 information, return the correct DQ copy. - * - * @param[in] i_mbTarget - Reference to mb Target - * @param[in] i_whichCopy - D0 information of which Q copy to get - * @param[out] o_DQKeyword - Correct DQ information - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ - -fapi::ReturnCode getDQAttribute(const fapi::Target &i_mbTarget, - uint32_t i_whichCopy, uint8_t (&o_DQKeyword)[DQ_KEYWORD_SIZE]); - -} -#endif - diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdAddrMirrorData.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdAddrMirrorData.H deleted file mode 100644 index 80d04c804..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdAddrMirrorData.H +++ /dev/null @@ -1,108 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdAddrMirrorData.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getMBvpdAddrMirrorData.H,v 1.1 2013/06/07 19:04:01 whs Exp $ - -/** - * @file getMBvpdAddrMirror.H - * - * @brief Prototype for getMBvpdAddrMirror() - - * get Address Mirroring Data from MBvpd - */ - -#ifndef _HWP_MBVPDADDRMIRRORDATA_ -#define _HWP_MBVPDADDRMIRRORDATA_ - -#include <fapi.H> - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getMBvpdAddrMirrorData_FP_t) - (const fapi::Target &, uint8_t (&) [2][2]); - -extern "C" -{ -/** - * @brief get Address Mirroring Data from cvpd record VSPD keyword AM - * - * The Address Mirroring Data attributes are retrieved from cvpd record VSPD - * keyword AM. - * There are two mba per memory buffer: position 0 and position 1. - * There are two ports for each mba and 2 DIMMs per port. - * - * cpvd record VSPD keyword AM - 4 bytes - * ----------------------------------- - * | mba position 0 | - * | ----------------------------- | - * | | port 0 (Port A) | | - * | | ------------------------ | | - * | | | DIMM 0 : 4 bits | | | - * | | ------------------------ | | - * | | | DIMM 1 : 4 bits | | | - * | | ------------------------ | | - * | |---------------------------| | - * | | port 1 (Port B) | | - * | | ------------------------ | | - * | | | DIMM 0 : 4 bits | | | - * | | ------------------------ | | - * | | | DIMM 1 : 4 bits | | | - * | | ------------------------ | | - * | ----------------------------- | - * |---------------------------------| - * | mba postion 1 | - * | ----------------------------- | - * | | port 0 (Port C) | | - * | | ------------------------ | | - * | | | DIMM 0 : 4 bits | | | - * | | ------------------------ | | - * | | | DIMM 1 : 4 bits | | | - * | | ------------------------ | | - * | |---------------------------| | - * | | port 1 (Port D) | | - * | | ------------------------ | | - * | | | DIMM 0 : 4 bits | | | - * | | ------------------------ | | - * | | | DIMM 1 : 4 bits | | | - * | | ------------------------ | | - * | ----------------------------- | - * ----------------------------------- - * - * Bit definition - * - * RANK0_MIRRORED = 0x08, - * RANK1_MIRRORED = 0x04, - * RANK2_MIRRORED = 0x02, - * RANK3_MIRRORED = 0x01, - * - * @param[in] i_mbaTarget - mba target - * @param[out] o_val - 2 x 2 array of bytes ([num ports] [num dimms]) - * Address Mirroring 4 bits per dimm returned - * in the lower nibble of the byte for the mba - * - * @return fapi::ReturnCode - FAPI_RC_SUCCESS if success, - * relevant error code for failure. - */ -fapi::ReturnCode getMBvpdAddrMirrorData( const fapi::Target &i_mbaTarget, - uint8_t (&o_val) [2][2]); - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.H deleted file mode 100644 index 591617411..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.H +++ /dev/null @@ -1,493 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getMBvpdAttr.H,v 1.7 2015/10/06 18:04:03 janssens Exp $ - -/** - * @file getMBvpdAttr.H - * - * @brief Prototype for getMBvpdAttr() - - * get Attribute Data from MBvpd - */ - -#ifndef _HWP_MBVPDATTR_ -#define _HWP_MBVPDATTR_ - -#include <fapi.H> -#include <fapiUtil.H> -#include <fapiMBvpdAccess.H> - -namespace fapi -{ -namespace getAttrData -{ - const uint32_t VM_00_MR_LAYOUT_KW_SIZE = 255; - const uint32_t VM_00_MR_LAYOUT_NON_PORT_HEAD_SIZE = 0; - const uint32_t VM_00_MR_LAYOUT_PORT_SEC_SIZE = 64; - const uint32_t VM_00_MT_LAYOUT_KW_SIZE = 255; - const uint32_t VM_00_MT_LAYOUT_NON_PORT_HEAD_SIZE = 0; - const uint32_t VM_00_MT_LAYOUT_PORT_SEC_SIZE = 64; - const uint32_t VM_01_MR_LAYOUT_KW_SIZE = 255; - const uint32_t VM_01_MR_LAYOUT_NON_PORT_HEAD_SIZE =2; - const uint32_t VM_01_MR_LAYOUT_PORT_SEC_SIZE = 64; - const uint32_t VM_01_MT_LAYOUT_KW_SIZE = 384; - const uint32_t VM_01_MT_LAYOUT_NON_PORT_HEAD_SIZE = 2; - const uint32_t VM_01_MT_LAYOUT_PORT_SEC_SIZE = 96; - - class keywordLayout - { - public: - virtual uint32_t getKeywordSize()=0; - virtual uint32_t getNonPortHeadSize()=0; - virtual uint32_t getPortSectionSize()=0; - virtual ~keywordLayout() {} - }; - class VM_00_MR_layout : public keywordLayout - { - public: - uint32_t getKeywordSize(){ return VM_00_MR_LAYOUT_KW_SIZE; } - uint32_t getNonPortHeadSize(){ return VM_00_MR_LAYOUT_NON_PORT_HEAD_SIZE; } - uint32_t getPortSectionSize(){ return VM_00_MR_LAYOUT_PORT_SEC_SIZE; } - ~VM_00_MR_layout() {} - }; - class VM_00_MT_layout : public keywordLayout - { - public: - uint32_t getKeywordSize(){ return VM_00_MT_LAYOUT_KW_SIZE; } - uint32_t getNonPortHeadSize(){ return VM_00_MT_LAYOUT_NON_PORT_HEAD_SIZE; } - uint32_t getPortSectionSize(){ return VM_00_MT_LAYOUT_PORT_SEC_SIZE; } - ~VM_00_MT_layout() {} - }; - class VM_01_MR_layout : public keywordLayout - { - public: - uint32_t getKeywordSize(){ return VM_01_MR_LAYOUT_KW_SIZE; } - uint32_t getNonPortHeadSize(){ return VM_01_MR_LAYOUT_NON_PORT_HEAD_SIZE; } - uint32_t getPortSectionSize(){ return VM_01_MR_LAYOUT_PORT_SEC_SIZE; } - ~VM_01_MR_layout() {} - }; - class VM_01_MT_layout : public keywordLayout - { - public: - uint32_t getKeywordSize(){ return VM_01_MT_LAYOUT_KW_SIZE; } - uint32_t getNonPortHeadSize(){ return VM_01_MT_LAYOUT_NON_PORT_HEAD_SIZE; } - uint32_t getPortSectionSize(){ return VM_01_MT_LAYOUT_PORT_SEC_SIZE; } - ~VM_01_MT_layout() {} - }; - class layoutFactory - { - public: - static keywordLayout* getLayout(const uint32_t &i_keyword ,const uint32_t &i_ver); - }; - - - //MT and MR keyword layout for VM ver 0. - const uint8_t NUM_MBA = 2; //There are 2 MBAs per Centaur memory buffer - const uint8_t NUM_PORTS = 2; //Each MBA has 2 ports - const uint8_t NUM_DIMMS = 2; //Each port has 2 DIMMs - const uint8_t NUM_RANKS = 4; //Number of ranks - - // DIMM types - enum DimmType - { - ALL_DIMM = 0, // Same for all Dimm types - CDIMM = 1, - ISDIMM = 2, - }; - - //Exceptions for MT keyword layout for VM ver 1. - - - // Versions to check for - enum VpdVersion - { - VD_VER = 0x010000, // Version came from VD keyword - VZ_VER = 0x020000, // Version came from VZ keyword - VM_VER = 0x040000, // Version came from VM keyword - ALL_VD = VD_VER, // Base value for VD keyword (version=0) - ALL_VZ = VZ_VER, // Base value for VZ keyword (version=0) - ALL_VM = VM_VER, // Base value for VM keyword (version=0) - ALL_VER = VD_VER|VZ_VER|VM_VER, // Base value for all versions - - // VZ values - VZ_10 = VZ_VER | 0x3130, // Version 6.0 is ascii "10" - VZ_13 = VZ_VER | 0x3133, // Version 6.3 is ascii "13" - - // VD values - VD_01 = VD_VER | 0x3031, // VD version "01" - - // VM values - VM_01 = VM_VER | 0x0001, // VM version "01" in hex - - // Supported VM version range - // As of now only VM_01 is supported - VM_SUPPORTED_HIGH_VER = 0x01, - VM_NOT_SUPPORTED = 0x00, - - VER_MASK= 0xffff, // Just version - INVALID_VER = 0, // Invalid initialization value - }; - -// Output data types - enum OutputType - { - UINT8_BY2 =0x0001, // uint8_t [2] - UINT8_BY2_BY2 =0x0002, // uint8_t [2][2] - UINT8_BY2_BY2_BY4 =0x0003, // uint8_t [2][2][4] - UINT32_BY2 =0x0004, // uint32_t [2] - UINT32_BY2_BY2 =0x0005, // uint32_t [2][2] - UINT64 =0x0006, // uint64_t - UINT8 =0x0007, // uint8_t - }; - const uint16_t OUTPUT_TYPE_MASK = 0x00FF; - - typedef uint8_t UINT8_BY2_t [2]; - typedef uint8_t UINT8_BY2_BY2_t [2][2]; - typedef uint8_t UINT8_BY2_BY2_BY4_t [2][2][4]; - typedef uint32_t UINT32_BY2_t [2]; - typedef uint32_t UINT32_BY2_BY2_t [2][2]; - typedef uint64_t UINT64_t; - typedef uint8_t UINT8_t; - - // Special processing - // Rules: - // Values for "All types" needs to be unquie for all output types - // Values for a particular type only need to be unique within that type - enum SpecialProcessing - { - // for All Types - DEFAULT_VALUE = 0x1000, - UINT8_DATA = 0x2000, // The vpd data size - UINT16_DATA = 0x3000, // The vpd data size - UINT32_DATA = 0x4000, // The vpd data size - // All the "all types" need to be within this mask - SPECIAL_DATA_MASK = 0xF000, - - // for UINT8_BY2 (all mutually exclusive) - XLATE_SLEW = 0x0100, - HIGH_NIBBLE = 0x0200, - LOW_NIBBLE = 0x0300, - PORT00 = 0x0400, - PORT11 = 0x0500, - - // for UINT8_BY2_BY2 (all mutually exclusive) - XLATE_DRAM_RON = 0x0100, - BOTH_DIMMS = 0x0200, - - // for UNIT8_BY2_BY2_BY4 (all mutually exclusive) - XLATE_RTT_NOM = 0x0100, - XLATE_RTT_WR = 0x0200, - - // for UINT32_BY2 (all mutually exclusive) - XLATE_RD_VREF = 0x0100, - XLATE_WR_VREF = 0x0200, - // UINT8_DATA supported - // UINT16_DATA supported - - // for UINT32_BY2_BY2 - // UINT8_DATA supported - // UINT16_DATA supported - - // for UINT64 - MERGE = 0x0100, - - // all of the "for output type" enums need to be within this mask - SPECIAL_XLATE_MASK = 0x0F00, - - // All enums need to be within this mask. The lower byte is the offset. - SPECIAL_PROCESSING_MASK = 0xFF00, - }; - -// VM keyword defination - struct MBvpdVMKeyword - { - uint8_t iv_version; - uint8_t iv_systemType; - uint8_t iv_systemType_ext; - uint8_t iv_dataVersion; - }; -// Attribute definition - struct MBvpdAttrDef - { - AttributeId iv_attrId; - DimmType iv_dimmType; - VpdVersion iv_version; - fapi::MBvpdKeyword iv_keyword; - uint8_t iv_offset; - uint16_t iv_outputType; - uint32_t iv_defaultValue; - }; - -// Declare global table and size -extern const MBvpdAttrDef g_MBVPD_ATTR_DEF_array []; -extern const uint32_t g_MBVPD_ATTR_DEF_array_size; - -} // getAttrData namespace -} // fapi namespace - -// Template class that is specialized for each attribute specifying it's type -template<const fapi::AttributeId A> - class MBvpdAttrDataType { }; - -// Term Data attribute specializations -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_DRAM_RON> - { public: typedef fapi::ATTR_VPD_DRAM_RON_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_DRAM_RTT_NOM> - { public: typedef fapi::ATTR_VPD_DRAM_RTT_NOM_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_DRAM_RTT_WR> - { public: typedef fapi::ATTR_VPD_DRAM_RTT_WR_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_ODT_RD> - { public: typedef fapi::ATTR_VPD_ODT_RD_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_ODT_WR> - { public: typedef fapi::ATTR_VPD_ODT_WR_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_DIMM_RCD_IBT> - { public: typedef fapi::ATTR_VPD_DIMM_RCD_IBT_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_DIMM_RCD_OUTPUT_TIMING> - { public: typedef fapi::ATTR_VPD_DIMM_RCD_OUTPUT_TIMING_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_RD_VREF> - { public: typedef fapi::ATTR_VPD_CEN_RD_VREF_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_DRAM_WR_VREF> - { public: typedef fapi::ATTR_VPD_DRAM_WR_VREF_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_DRAM_WRDDR4_VREF> - { public: typedef fapi::ATTR_VPD_DRAM_WRDDR4_VREF_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_RCV_IMP_DQ_DQS> - { public: typedef fapi::ATTR_VPD_CEN_RCV_IMP_DQ_DQS_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_DRV_IMP_DQ_DQS> - { public: typedef fapi::ATTR_VPD_CEN_DRV_IMP_DQ_DQS_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_DRV_IMP_CNTL> - { public: typedef fapi::ATTR_VPD_CEN_DRV_IMP_CNTL_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_DRV_IMP_ADDR> - { public: typedef fapi::ATTR_VPD_CEN_DRV_IMP_ADDR_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_DRV_IMP_CLK> - { public: typedef fapi::ATTR_VPD_CEN_DRV_IMP_CLK_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_DRV_IMP_SPCKE> - { public: typedef fapi::ATTR_VPD_CEN_DRV_IMP_SPCKE_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_SLEW_RATE_DQ_DQS> - { public: typedef fapi::ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_SLEW_RATE_CNTL> - { public: typedef fapi::ATTR_VPD_CEN_SLEW_RATE_CNTL_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_SLEW_RATE_ADDR> - { public: typedef fapi::ATTR_VPD_CEN_SLEW_RATE_ADDR_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_SLEW_RATE_CLK> - { public: typedef fapi::ATTR_VPD_CEN_SLEW_RATE_CLK_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_SLEW_RATE_SPCKE> - { public: typedef fapi::ATTR_VPD_CEN_SLEW_RATE_SPCKE_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CKE_PRI_MAP> - { public: typedef fapi::ATTR_VPD_CKE_PRI_MAP_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CKE_PWR_MAP> - { public: typedef fapi::ATTR_VPD_CKE_PWR_MAP_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_RLO> - { public: typedef fapi::ATTR_VPD_RLO_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_WLO> - { public: typedef fapi::ATTR_VPD_WLO_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_GPO> - { public: typedef fapi::ATTR_VPD_GPO_Type Type; }; - -// Phase Rotator attribute specializations -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_PAR> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_PAR_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M_ACTN> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M_ACTN_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1> - { public: typedef fapi::ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_MR_VERSION_BYTE> - { public: typedef fapi::ATTR_VPD_MR_VERSION_BYTE_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_MR_DATA_CONTROL_BYTE> - { public: typedef fapi::ATTR_VPD_MR_DATA_CONTROL_BYTE_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_PERIODIC_MEMCAL_MODE_OPTIONS> - { public: typedef fapi::ATTR_VPD_PERIODIC_MEMCAL_MODE_OPTIONS_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_MT_VERSION_BYTE> - { public: typedef fapi::ATTR_VPD_MT_VERSION_BYTE_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_MT_DATA_CONTROL_BYTE> - { public: typedef fapi::ATTR_VPD_MT_DATA_CONTROL_BYTE_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_DRAM_RTT_PARK> - { public: typedef fapi::ATTR_VPD_DRAM_RTT_PARK_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_RD_CTR_WINDAGE_OFFSET> - { public: typedef fapi::ATTR_VPD_RD_CTR_WINDAGE_OFFSET_Type Type; }; - - -// There is no ATTR_VPD_DRAM_2N_MODE attribute. getMBvpdAttr is called -// directly using ATTR_VPD_DRAM_2N_MODE_ENABLED as an ID. -//template<>class MBvpdAttrDataType<fapi::ATTR_VPD_DRAM_2N_MODE> -// { public: typedef fapi::ATTR_VPD_DRAM_2N_MODE Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_TSYS_ADR> - { public: typedef fapi::ATTR_VPD_TSYS_ADR_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_TSYS_DP18> - { public: typedef fapi::ATTR_VPD_TSYS_DP18_Type Type; }; -template<>class MBvpdAttrDataType<fapi::ATTR_VPD_POWER_CONTROL_CAPABLE> - { public: typedef fapi::ATTR_VPD_POWER_CONTROL_CAPABLE_Type Type; }; - - -// Template function that checks that the type is as expected. -// This can be optionally called before calling the main HWP in order -// to check for the expected type at compile-time. -template<const fapi::AttributeId ATTR> - inline void checkAttrDataType - (typename MBvpdAttrDataType<ATTR>::Type &) {} - -/* example -#define ATTR_VPD_DRAM_RON_GETMACRO(ID, PTARGET, VAL)\ - (checkAddrDataType<fapi::ATTR_VPD_DRAM_RON>(VAL), \ - fapi::platAttrSvc::fapiPlatGetAddrData\ - (PTARGET, fapi::ATTR_VPD_DRAM_RON , VAL, sizeof(VAL))) -*/ -// The complilation will fail unless the output variable matches the type -// in the per attribute template specialization. The error messages will -// include text related to template MBvpdAttrDataSize not be able to convert -// the incorrect output variable's type to the expected type. -// -// There will be an additonal error from the general attribute compliation -// checks related to fapiCheckIdType if the output type does not match -// any of the expected types -// -// The inline function checkTermData will be optimized out by the compiler. - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getMBvpdAttr_FP_t) - (const fapi::Target &, const fapi::AttributeId, - void *, const size_t); - - - -extern "C" -{ -/** - * @brief get Attribute Data from MBvpd - * - * @param[in] i_mbaTarget - mba target - * @param[in] i_attr - Attribute ID - * @param[out] o_pVal - pointer to variable typed output variable - * @param[in] i_valSize - size of output variable - * - * @return fapi::ReturnCode - FAPI_RC_SUCCESS if success, - * relevant error code for failure. - */ -fapi::ReturnCode getMBvpdAttr( - const fapi::Target &i_mbaTarget, - const fapi::AttributeId i_attr, - void * o_pVal, - const size_t i_valSize); - -/** - * @brief Find dimm info; parent, type, position - */ -fapi::ReturnCode findDimmInfo (const fapi::Target & i_mbaTarget, - fapi::Target & o_mbTarget, - uint8_t & o_pos, - fapi::getAttrData::DimmType & o_dimmType); - - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdDram2NModeEnabled.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdDram2NModeEnabled.H deleted file mode 100644 index 4fd9254c4..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdDram2NModeEnabled.H +++ /dev/null @@ -1,59 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdDram2NModeEnabled.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getMBvpdDram2NModeEnabled.H,v 1.1 2013/10/30 21:02:44 whs Exp $ -/** - * @file getMBvpdDram2NModeEnabled.H - * - * @brief MBVPD Accessor for providing the ATTR_VPD_DRAM_2N_MODE_ENABLED - * attribute - */ - -#ifndef _HWP_GETMBVPDDRAM2NMODEENABLED_ -#define _HWP_GETMBVPDDRAM2NMODEENABLED_ - -#include <fapi.H> - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getMBvpdDram2NModeEnabled_FP_t) - (const fapi::Target &, uint8_t &); - -extern "C" -{ -/** - * @brief Get the ATTR_DRAM_2N_MODE_ENABLED FAPI attribute - * - * Return whether Dram 2N Mode is enabled based on the MR keyword - * DRAM_2N_MODE value. The DRAM_2N_Mode values for both ports of the mba - * must be equal, otherwise an error is returned. - * - * @param[in] i_mbaTarget - Reference to mba Target - * @param[out] o_val - ATTR_VPD_DRAM_2N_MODE_ENABLED enumeration value - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ -fapi::ReturnCode getMBvpdDram2NModeEnabled( - const fapi::Target & i_mbaTarget, - uint8_t & o_val); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdMemoryDataVersion.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdMemoryDataVersion.H deleted file mode 100644 index f172508cb..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdMemoryDataVersion.H +++ /dev/null @@ -1,62 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdMemoryDataVersion.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getMBvpdMemoryDataVersion.H,v 1.2 2015/10/06 15:18:04 dcrowell Exp $ -/** - * @file getMBvpdMemoryDataVersion.H - * - * @brief MBVPD Accessor for providing the ATTR_VPD_VM_KEYWORD attribute - */ - -#ifndef _HWP_GETMBVPDMEMDATAVERSION_ -#define _HWP_GETMBVPDMEMDATAVERSION_ - -#include <fapi.H> -#define VM_KEYWORD_DEFAULT_VALUE 0x00000000 - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getMBvpdMemoryDataVersion_FP_t) - (const fapi::Target &, uint32_t &); - -extern "C" -{ -/** - * @brief Get the ATTR_VPD_VM_KEYWORD FAPI attribute - * - * Return the Memory Data version from MBvpd record SPDX keyword VM. - * - * The ATTR_VPD_VM_KEYWORD attribute is associated with a DIMM. The platfrom must - * get the associated Membuff chip to be passed to this hwp accessor. - * - * @param[in] i_mbTarget - Reference to membuf Target - * @param[out] o_val - Filled in with vpd version - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ -fapi::ReturnCode getMBvpdMemoryDataVersion( - const fapi::Target & i_mbTarget, - uint32_t & o_val); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSPDXRecordVersion.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSPDXRecordVersion.H deleted file mode 100644 index 647e68189..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSPDXRecordVersion.H +++ /dev/null @@ -1,62 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSPDXRecordVersion.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getMBvpdSPDXRecordVersion.H,v 1.1 2015/09/29 16:25:03 dcrowell Exp $ -/** - * @file getMBvpdSPDXRecordVersion.H - * - * @brief MBVPD Accessor for providing the ATTR_VPD_VD_KEYWORD attribute - */ - -#ifndef _HWP_GETMBVPDSPDXVERSION_ -#define _HWP_GETMBVPDSPDXVERSION_ - -#include <fapi.H> -#define VD_KEYWORD_DEFAULT_VALUE 0x0000 - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getMBvpdSPDXRecordVersion_FP_t) - (const fapi::Target &, uint32_t &); - -extern "C" -{ -/** - * @brief Get the ATTR_VPD_VD_KEYWORD FAPI attribute - * - * Return the SPDX version from MBvpd record SPDX keyword VD. - * - * The ATTR_VPD_VD_KEYWORD attribute is associated with a DIMM. The platfrom must - * get the associated MemBuff chip to be passed to this hwp accessor. - * - * @param[in] i_mbTarget - Reference to membuf Target - * @param[out] o_val - Filled in with vpd version - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ -fapi::ReturnCode getMBvpdSPDXRecordVersion( - const fapi::Target & i_mbTarget, - uint32_t & o_val); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSensorMap.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSensorMap.H deleted file mode 100644 index d376939f8..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSensorMap.H +++ /dev/null @@ -1,74 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSensorMap.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getMBvpdSensorMap.H,v 1.1 2013/11/20 22:36:54 whs Exp $ - -/** - * @file getMBvpdSensorMap.H - * - * @brief Prototype for getMBvpdSensorMap() - - * get primary and secondary sensor map - */ - -#ifndef _HWP_MBVPDSENSORMAP_ -#define _HWP_MBVPDSENSORMAP_ - -#include <fapi.H> - -namespace fapi -{ - - enum MBvpdSensorMap - { - SENSOR_MAP_PRIMARY = 0x00, - SENSOR_MAP_SECONDARY = 0x01, - }; -} - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getMBvpdSensorMap_FP_t) - (const fapi::Target &, const fapi::MBvpdSensorMap, uint8_t &); - -extern "C" -{ -/** - * @brief Return primary and secondary sensor map from cvpd record VSPD - * keyword MW for attributes: - * - * ATTR_VPD_CDIMM_SENSOR_MAP_PRIMARY - * ATTR_VPD_CDIMM_SENSOR_MAP_SECONDARY - * - * @param[in] i_mbTarget - Membuf chip target - * @param[in] i_attr - Enumerator to select requested value - * @param[out] o_val - Primary or secondary sensor map - * - * @return fapi::ReturnCode - FAPI_RC_SUCCESS if success, - * relevant error code for failure. - */ -fapi::ReturnCode getMBvpdSensorMap( - const fapi::Target &i_mbTarget, - const fapi::MBvpdSensorMap i_attr, - uint8_t &o_val); - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSlopeInterceptData.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSlopeInterceptData.H deleted file mode 100644 index d88a087a7..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSlopeInterceptData.H +++ /dev/null @@ -1,86 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSlopeInterceptData.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getMBvpdSlopeInterceptData.H,v 1.2 2015/09/29 15:59:42 dcrowell Exp $ - -/** - * @file getMBvpdSlopeInterceptData.H - * - * @brief Prototype for getMBvpdSlopeInterceptData() - - * get master and supplier power slope and intercept from MBvpd - */ - -#ifndef _HWP_MBVPDSLOPEINTERCEPTDATA_ -#define _HWP_MBVPDSLOPEINTERCEPTDATA_ - -#include <fapi.H> - -namespace fapi -{ - - enum MBvpdSlopeIntercept - { - MASTER_POWER_SLOPE = 0x00, - MASTER_POWER_INTERCEPT = 0x01, - SUPPLIER_POWER_SLOPE = 0x02, - SUPPLIER_POWER_INTERCEPT = 0x03, - MASTER_TOTAL_POWER_SLOPE = 0x04, - MASTER_TOTAL_POWER_INTERCEPT = 0x05, - SUPPLIER_TOTAL_POWER_SLOPE = 0x06, - SUPPLIER_TOTAL_POWER_INTERCEPT = 0x07, - }; -} - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getMBvpdSlopeInterceptData_FP_t) - (const fapi::Target &, const fapi::MBvpdSlopeIntercept, uint32_t &); - -extern "C" -{ -/** - * @brief Return power slope and intercept data from cvpd record VSPD - * keyword MW and MV - * - * The Master power slope and intercept data is in the MW keyword. - * The Supplier power slope and intercept data is in the MV keyword. - * The #I keyword has the Module ID for this CDIMM. The MV keyword - * has the supplier power slope and intercept for multiple vendors. - * The list in MV is searched for the Module ID in the #I keyword. - * Values for the matching vendor are returned. - * - * @param[in] i_mbTarget - membuf chip target - * @param[in] i_attr - enumerator to select requested value - * @param[out] o_val - master/supplier slope/intercept value - * - * @return fapi::ReturnCode - FAPI_RC_SUCCESS if success, - * relevant error code for failure. - */ -fapi::ReturnCode getMBvpdSlopeInterceptData( - const fapi::Target &i_mbTarget, - const fapi::MBvpdSlopeIntercept i_attr, - uint32_t &o_val); - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSpareDramData.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSpareDramData.H deleted file mode 100644 index 4a8bbea93..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSpareDramData.H +++ /dev/null @@ -1,54 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdSpareDramData.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getMBvpdSpareDramData.H,v 1.2 2013/10/03 20:40:52 dedahle Exp $ -#ifndef GETMBVPDSPAREDRAMDATA_H_ -#define GETMBVPDSPAREDRAMDATA_H_ - -#include <fapi.H> -#include <dimmConsts.H> - -typedef fapi::ReturnCode (*getMBvpdSpareDramData_FP_t)( - const fapi::Target &, - uint8_t (&)[DIMM_DQ_MAX_MBA_PORTS][DIMM_DQ_MAX_MBAPORT_DIMMS] - [DIMM_DQ_MAX_DIMM_RANKS]); -extern "C" -{ - -/** - * @brief FW Team HWP that handles the ATTR_VPD_DIMM_SPARE attribute - * by querying MBvpd to determine spare DRAM availability for C-DIMMs. - * - * This HWP should be called through the VPD_DIMM_SPARE attribute. - * - * @param[in] i_mba Reference to MBA Target. - * @param[out] o_data Reference to spare DRAM data. - * - * @return ReturnCode - */ -fapi::ReturnCode getMBvpdSpareDramData( - const fapi::Target & i_mba, - uint8_t (&o_data)[DIMM_DQ_MAX_MBA_PORTS][DIMM_DQ_MAX_MBAPORT_DIMMS] - [DIMM_DQ_MAX_DIMM_RANKS]); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdVersion.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdVersion.H deleted file mode 100644 index ec7770e01..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdVersion.H +++ /dev/null @@ -1,59 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdVersion.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getMBvpdVersion.H,v 1.1 2013/10/30 21:04:08 whs Exp $ -/** - * @file getMBvpdVersion.H - * - * @brief MBVPD Accessor for providing the ATTR_VPD_VERSION attribute - */ - -#ifndef _HWP_GETMBVPDVERSION_ -#define _HWP_GETMBVPDVERSION_ - -#include <fapi.H> - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getMBvpdVersion_FP_t) - (const fapi::Target &, uint32_t &); - -extern "C" -{ -/** - * @brief Get the ATTR_VPD_VERSION FAPI attribute - * - * Return the VPD version from MBvpd record VINI keyword VZ. - * - * The ATTR_VPD_VERSION attribute is associated with a DIMM. The platfrom must - * get the associated MBA chip to be passed to this hwp accessor. - * - * @param[in] i_mbaTarget - Reference to mba Target - * @param[out] o_val - Filled in with vpd version - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ -fapi::ReturnCode getMBvpdVersion( - const fapi::Target & i_mbaTarget, - uint32_t & o_val); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdVoltageSettingData.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdVoltageSettingData.H deleted file mode 100644 index 90f5a4d4e..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdVoltageSettingData.H +++ /dev/null @@ -1,61 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdVoltageSettingData.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getMBvpdVoltageSettingData.H,v 1.1 2015/09/29 16:25:05 dcrowell Exp $ -/** - * @file getMBvpdVoltageSettingData.H - * - * @brief MBVPD Accessor for providing the ATTR_VPD_DW_KEYWORD attribute - */ - -#ifndef _HWP_GETMBVPDDWDATA_ -#define _HWP_GETMBVPDDWDATA_ - -#include <fapi.H> -#define DW_KEYWORD_DEFAULT_VALUE 0x0109 -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getMBvpdVoltageSettingData_FP_t) - (const fapi::Target &, uint32_t &); - -extern "C" -{ -/** - * @brief Get the ATTR_VPD_DW_KEYWORD FAPI attribute - * - * Return the voltage setting data from MBvpd record SPDX keyword DW. - * - * The ATTR_VPD_DW_KEYWORD attribute is associated with a DIMM. The platfrom must - * get the associated MemBuff chip to be passed to this hwp accessor. - * - * @param[in] i_mbTarget - Reference to membuff Target - * @param[out] o_val - Filled in with vpd version - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ -fapi::ReturnCode getMBvpdVoltageSettingData( - const fapi::Target & i_mbTarget, - uint32_t & o_val); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getMvpdExL2SingleMemberEnable.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getMvpdExL2SingleMemberEnable.H deleted file mode 100644 index 4aa2aaf78..000000000 --- a/src/include/usr/hwpf/hwp/mvpd_accessors/getMvpdExL2SingleMemberEnable.H +++ /dev/null @@ -1,72 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/mvpd_accessors/getMvpdExL2SingleMemberEnable.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getMvpdExL2SingleMemberEnable.H,v 1.1 2013/04/10 22:02:29 mjjones Exp $ -/** - * @file getMvpdExL2SingleMemberEnable.H - * - * @brief MVPD Accessor for providing the ATTR_EX_L2_SINGLE_MEMBER_ENABLE - * attribute - */ - -/* - * Change Log ****************************************************************** - * Flag Defect/Feature User Date Description - * ------ -------------- ---------- ----------- ---------------------------- - * mjjones 04/10/2013 Created. - */ - -#ifndef _HWP_GETMVPDEXL2SINGLEMEMBERENABLE_ -#define _HWP_GETMVPDEXL2SINGLEMEMBERENABLE_ - -#include <fapi.H> - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getMvpdExL2SingleMemberEnable_FP_t) - (const fapi::Target &, uint32_t &); - -extern "C" -{ -/** - * @brief Get the ATTR_EX_L2_SINGLE_MEMBER_ENABLE FAPI attribute - * - * This data in MVPD indicates which EX chiplets must be configured with the L2 - * cache in single member mode. The data is used by the p8_xip_customize HWP. It - * is used by the FSP platform to build the IPL image, and the Hostboot platform - * to build the SLW image. The data is a bit-field. - * - * @param[in] i_procTarget - Reference to Processor Chip FAPI Target - * @param[out] o_val - Filled in with attribute value - * 0x00008000 - EX00 single member enable - * 0x00004000 - EX01 single member enable - * <snip> - * 0x00000002 - EX14 single member enable - * 0x00000001 - EX15 single member enable - * - * @return fapi::ReturnCode FAPI_RC_SUCCESS if success, else error code - */ -fapi::ReturnCode getMvpdExL2SingleMemberEnable( - const fapi::Target & i_procTarget, - uint32_t & o_val); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/occ/occ.H b/src/include/usr/hwpf/hwp/occ/occ.H index c4dba0996..f81d4f73b 100644 --- a/src/include/usr/hwpf/hwp/occ/occ.H +++ b/src/include/usr/hwpf/hwp/occ/occ.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ +/* Contributors Listed Below - COPYRIGHT 2013,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ diff --git a/src/include/usr/hwpf/hwp/occ/occAccess.H b/src/include/usr/hwpf/hwp/occ/occAccess.H index f5de96589..4846330d5 100644 --- a/src/include/usr/hwpf/hwp/occ/occAccess.H +++ b/src/include/usr/hwpf/hwp/occ/occAccess.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* Contributors Listed Below - COPYRIGHT 2014,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ diff --git a/src/include/usr/hwpf/hwp/occ/occ_common.H b/src/include/usr/hwpf/hwp/occ/occ_common.H index 2369c0fc2..48dbd1142 100644 --- a/src/include/usr/hwpf/hwp/occ/occ_common.H +++ b/src/include/usr/hwpf/hwp/occ/occ_common.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2015 */ +/* Contributors Listed Below - COPYRIGHT 2014,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ diff --git a/src/include/usr/hwpf/hwp/pll_accessors/getPllRingAttr.H b/src/include/usr/hwpf/hwp/pll_accessors/getPllRingAttr.H deleted file mode 100755 index 767dce42b..000000000 --- a/src/include/usr/hwpf/hwp/pll_accessors/getPllRingAttr.H +++ /dev/null @@ -1,66 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/pll_accessors/getPllRingAttr.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getPllRingAttr.H,v 1.1 2013/12/05 18:23:24 mjjones Exp $ -/** - * @file getPllRingAttr.H - * - * @brief Prototype for getPllRingAttr() - - * fetch PLL ring attributes based on chip EC and frequencies - * from data from static arrays (fapiPllRingAttr.H) - */ - - #ifndef _HWP_GETPLLRINGATTR_ - #define _HWP_GETPLLRINGATTR_ - -#include <fapi.H> -#define MAX_PLL_RING_SIZE_BYTES 256 - -//#include <fapiPllRingAttr.H> - - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getPllRingAttr_FP_t) - (const fapi::AttributeId, const fapi::Target &, uint32_t &, uint8_t *); - -extern "C" -{ -/** - * @brief get specified PLL ring attribute for the specified target CPU. - * - * @param i_attrId - fapi attribute requested by the caller. - * @param i_fapiTarget - cpu target - * @param o_ringLength - out: size of ring buffer that caller has - * allocated - * @param 0_data - out: PLL ring data. - * - * @return fapi::ReturnCode - FAPI_RC_SUCCESS if success, - * relevant error code for failure. - */ - fapi::ReturnCode getPllRingAttr( const fapi::AttributeId i_attrId, - const fapi::Target i_pChipTarget, - uint32_t & o_ringBitLength, - uint8_t *o_data); - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/pll_accessors/getPllRingInfoAttr.H b/src/include/usr/hwpf/hwp/pll_accessors/getPllRingInfoAttr.H deleted file mode 100644 index 4a77e7282..000000000 --- a/src/include/usr/hwpf/hwp/pll_accessors/getPllRingInfoAttr.H +++ /dev/null @@ -1,85 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/pll_accessors/getPllRingInfoAttr.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getPllRingInfoAttr.H,v 1.2 2014/01/17 23:50:25 whs Exp $ -/** - * @file getPllRingInfoAttr.H - * - * @brief Accessor HWP that gets attributes containing information about PLL - * Rings - */ - -#ifndef _GETPLLRINGINFOATTR_ -#define _GETPLLRINGINFOATTR_ - -#include <fapi.H> - -namespace fapi -{ - // Attributes supported - namespace getPllRingInfo - { - enum Attr - { - PROC_DMI_CUPLL_PFD360_OFFSET = 0x01, - PROC_DMI_CUPLL_REFCLKSEL_OFFSET = 0x02, - PROC_ABUS_CUPLL_PFD360_OFFSET = 0x03, - PROC_ABUS_CUPLL_REFCLKSEL_OFFSET = 0x04, - MEMB_DMI_CUPLL_PFD360_OFFSET = 0x05, - MEMB_DMI_CUPLL_REFCLKSEL_OFFSET = 0x06, - MEMB_MEM_PLL_CFG_UPDATE_OFFSET = 0x07, - }; - } -} - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getPllRingInfoAttr_FP_t) ( - const fapi::Target &, - const fapi::getPllRingInfo::Attr, - void *, const size_t); - -extern "C" -{ -/** - * @brief Accessor HWP that gets attributes containing information about PLL - * Rings - * - * FAPI_ATTR_GET checks at compile time that the user's attribute is the correct - * type. Assuming that the platform routes the access of the attribute to the - * corresponding attribute enum defined in this file then the size of o_pVal - * will be correct, in the unlikely event of a misroute where the buffer is too - * small, an error will be returned. - * - * @param[in] i_chip Reference to Processor/Membuf Chip fapi target - * @param[in] i_attr The Attribute to get - * @param[out] o_pVal Pointer to data buffer filled in with attribute data - * @param[in] i_len Size of o_pVal - * - * @return fapi::ReturnCode Indicating success or error - */ -fapi::ReturnCode getPllRingInfoAttr(const fapi::Target & i_chip, - const fapi::getPllRingInfo::Attr i_attr, - void * o_pVal, - const size_t i_len); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/procMemConsts.H b/src/include/usr/hwpf/hwp/procMemConsts.H deleted file mode 100644 index 5d343b0bd..000000000 --- a/src/include/usr/hwpf/hwp/procMemConsts.H +++ /dev/null @@ -1,74 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/procMemConsts.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -/** - * @file procMemConsts.H - * - * @brief Constants to implement support for proc_setup_bars and mss_setup_bars - * Taken from Shawn Lambeth's MMIOMap8.1.0 spreadsheet - */ - -#ifndef _HWP_PROCMEMCONSTS_H_ -#define _HWP_PROCMEMCONSTS_H_ - -// Lower FSP Bar Regions - line 226 Overall Map, line 72 service processor -// size is 4_GB -const uint64_t SP_BAR_SIZE = 0x0000000100000000ULL ; - -// FSP Bar Size, line 227 Overall Map -const uint64_t FSP_BAR_SIZE = 0x0000000100000000ULL ; - -// Fsp MMIO Mask Size -// @todo P7 had this at 4_GB, don't see it in the spreadsheet. -const uint64_t FSP_MMIO_MASK_SIZE = 0x0000000100000000 ; - -// Processor RNG Space, for NX_MMIO - line 46 Overall Map -// size is 4_KB -const uint64_t PROC_RNG_SIZE = 0x0000000000001000ULL; - -// PCIE Mem Address Space - line 236 Overall Map -// corresponds to the "unit number" in ATTR description -// size is 64_GB -const uint64_t PCI_MEM_SIZE = 0x0000001000000000ULL; - -// PCIE BAR size values -// Bar0 = 64_GB ( from spreadsheet) -// Bar1 = 2_GB ( from spreadsheet) -// Bar2 = 4_KB see NOTE above -const uint64_t PCIE_BAR0_SIZE = 0x0000001000000000ULL; -const uint64_t PCIE_BAR1_SIZE = 0x0000000080000000ULL; -const uint64_t PCIE_BAR2_SIZE = 0x0000000000001000ULL; - -// 4 PHB per chip, 4chips per node, max 4 nodes -const uint64_t PCIE_BAR0_OFFSET_MASK = ((PCIE_BAR0_SIZE*4*4*4)-1); -const uint64_t PCIE_BAR1_OFFSET_MASK = ((PCIE_BAR1_SIZE*4*4*4)-1); -const uint64_t SAPPHIRE_PCIE_BAR0_BASE = 0x00003B0000000000; -const uint64_t SAPPHIRE_PCIE_BAR1_BASE = 0x00003FE000000000; - - - -// PHB Register Address Space - line 90 Overall Map -// size is 1_MB -const uint64_t PHB_REGS_SIZE = 0x0000000000100000ULL; - - -#endif diff --git a/src/include/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.H b/src/include/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.H deleted file mode 100644 index ecc6048f5..000000000 --- a/src/include/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.H +++ /dev/null @@ -1,92 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getSpdAttrAccessor.H,v 1.2 2014/06/27 19:50:08 thi Exp $ -/** - * @file getSpdAttrAccessor.H - * - * @brief Accessor HWP that gets DDR neutral DIMM SPD FAPI Attributes - * - * Handles DDR neutral attributes where raw SPD data cannot be returned, - * either: - * - The raw data has a different meaning between DDR3 and DDR4. - * - The raw data has a different size between DDR3 and DDR4. - * - The attribute does not map to a single field in both DDR3 and DDR4. - * - * This Accessor HWP reads the DDR specific attribute and figures out the - * data to return for the DDR neutral attribute. - */ - -#ifndef _GETSPDDATAACCESSOR_ -#define _GETSPDDATAACCESSOR_ - -#include <fapi.H> - -namespace fapi -{ - // Attributes supported - namespace getSpdAttr - { - enum Attr - { - SPD_SDRAM_BANKS = 0x01, - SPD_MODULE_NOMINAL_VOLTAGE = 0x02, - SPD_CAS_LATENCIES_SUPPORTED = 0x03, - SPD_MODULE_REVISION_CODE = 0x04, - }; - } -} - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getSpdAttrAccessor_FP_t) ( - const fapi::Target &, - const fapi::getSpdAttr::Attr, - void *, - const size_t); - -extern "C" -{ -/** - * @brief Accessor HWP that gets DDR neutral DIMM SPD FAPI Attribute data - * - * FAPI_ATTR_GET checks at compile time that the user's attribute is the correct - * type. Assuming that the platform routes the access of the attribute to the - * corresponding attribute enum defined in this file (e.g. ATTR_SPD_SDRAM_BANKS - * -> SPD_SDRAM_BANKS) then the size of o_pVal will be correct, in the unlikely - * event of a misroute where the buffer is too small, an error will be returned. - * - * @param[in] i_dimm Reference to DIMM fapi target - * @param[in] i_attr The Attribute to get - * @param[out] o_pVal Pointer to data buffer filled in with attribute data - * @param[in] i_len Size of o_pVal - * - * @return fapi::ReturnCode Indicating success or error - */ -fapi::ReturnCode getSpdAttrAccessor(const fapi::Target & i_dimm, - const fapi::getSpdAttr::Attr i_attr, - void * o_pVal, - const size_t i_len); -} - -#endif diff --git a/src/include/usr/hwpf/hwp/tp_dbg_data_accessors/getTpDbgDataAttr.H b/src/include/usr/hwpf/hwp/tp_dbg_data_accessors/getTpDbgDataAttr.H deleted file mode 100644 index c4e25d8e8..000000000 --- a/src/include/usr/hwpf/hwp/tp_dbg_data_accessors/getTpDbgDataAttr.H +++ /dev/null @@ -1,93 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/tp_dbg_data_accessors/getTpDbgDataAttr.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getTpDbgDataAttr.H,v 1.1 2015/05/07 20:11:12 thi Exp $ -/** - * @file getTpDbgDataAttr.H - * - * @brief Prototype for getPervVitalAttr() - - * Fetch TP Debug data attributes based on chip EC - * from static arrays (fapiTpDbgDataAttr.H) - */ - -#ifndef _HWP_GETPERVVITALATTR_ -#define _HWP_GETPERVVITALATTR_ - -#include <fapi.H> -#include <fapiTpDbgDataAttr.H> - -// Function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getPervVitlRingLengthAttr_FP_t) - (const fapi::Target &, uint32_t &); - -typedef fapi::ReturnCode (*getTpVitlSpyLengthAttr_FP_t) - (const fapi::Target &, uint32_t &); - -typedef fapi::ReturnCode (*getTpVitlSpyOffsetAttr_FP_t) - (const fapi::Target &, uint32_t (&)[SPY_OFFSET_SIZE]); - -extern "C" -{ - -/** - * @brief Get processor TP VITL spy length for the specified target CPU. - * - * @param i_fapiTarget - cpu target - * @param o_ringLength - out: Length of decompressed data - * - * @return fapi::ReturnCode - FAPI_RC_SUCCESS if success, - * relevant error code for failure. - */ -fapi::ReturnCode getPervVitlRingLengthAttr(const fapi::Target &i_fapiTarget, - uint32_t (&o_ringLength)); - - -/** - * @brief Get processor PERV VITL ring length for the specified target CPU. - * - * @param i_fapiTarget - cpu target - * @param o_spyLength - out: Length of spy - * - * @return fapi::ReturnCode - FAPI_RC_SUCCESS if success, - * relevant error code for failure. - */ -fapi::ReturnCode getTpVitlSpyLengthAttr(const fapi::Target &i_fapiTarget, - uint32_t (&o_spyLength)); - - -/** - * @brief Get processor TP VITL spy offsets for the specified target CPU. - * - * @param i_fapiTarget - cpu target - * @param o_data - out: spy offset data - * - * @return fapi::ReturnCode - FAPI_RC_SUCCESS if success, - * relevant error code for failure. - */ -fapi::ReturnCode getTpVitlSpyOffsetAttr(const fapi::Target &i_fapiTarget, - uint32_t (&o_data)[SPY_OFFSET_SIZE]); - -} - -#endif diff --git a/src/include/usr/hwpf/hwp/utility_procedures/mss_count_active_centaurs.H b/src/include/usr/hwpf/hwp/utility_procedures/mss_count_active_centaurs.H deleted file mode 100644 index 6b3813a18..000000000 --- a/src/include/usr/hwpf/hwp/utility_procedures/mss_count_active_centaurs.H +++ /dev/null @@ -1,72 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/utility_procedures/mss_count_active_centaurs.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_count_active_centaurs.H,v 1.1 2014/06/16 16:06:27 dcadiga Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_volt_vpp_offset.H -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Stephen Glancy Email: sglancy@us.ibm.com -// *! BACKUP NAME : Jacob Sloat Email: jdsloat@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// Header file for mss_volt. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|----------|----------------------------------------------- -// 1.2 | sglancy | 06/04/14 | Updated to include output attribute -// 1.1 | sglancy | 05/20/14 | initial drop -#ifndef MSS_COUNT_ACTIVE_CENT_H_ -#define MSS_COUNT_ACTIVE_CENT_H_ - -#include <fapi.H> - -typedef fapi::ReturnCode (*mss_count_active_centaurs_FP_t)(std::vector<fapi::Target> & , uint32_t & , uint32_t &); - -extern "C" -{ - -/** - * @brief mss_count_active_centaurs procedure. Determines operating vpp voltage for dimms behind a voltage domain - * - * @param[in] std::vector<fapi::Target> l_targets Reference to vector of Centaur Targets - * uint32_t & var_num_active_centaur - number of active centaurs - to be returned out of the function - * uint32_t & var_num_inactive_centaur - number of inactive centaurs - to be returned out of the function - * - * @return ReturnCode - */ - - fapi::ReturnCode mss_count_active_centaurs(std::vector<fapi::Target> & i_targets, uint32_t & var_num_active_centaur, uint32_t &var_num_inactive_centaur); - -} // extern "C" - -#endif // MSS_COUNT_ACTIVE_CENT_H_ diff --git a/src/include/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.H b/src/include/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.H deleted file mode 100644 index 5f0fdd0a9..000000000 --- a/src/include/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.H +++ /dev/null @@ -1,1168 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_maint_cmds.H,v 1.23 2015/08/11 20:09:21 lwmulkey Exp $ -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Date: | Author: | Comment: -//---------|----------|---------|----------------------------------------------- -// | 11/02/11 | gollub | Created -// | 11/15/11 | gollub | Fixed some reg addresses -// | 03/30/12 | gollub | Made stop condition parm into a mask. -// | | | Added support for both MBAs -// | 04/25/12 | gollub | Added doxygen tags -// | 05/23/12 | gollub | Updates from review. -// | 07/13/12 | gollub | Updates from review. -// 1.7 | 07/16/12 | bellows | added in Id tag -// 1.8 | 07/18/12 | gollub | Updates for timebase scrub. -// 1.9 | 08/15/12 | gollub | Added stop condition enums -// | | | STOP_IMMEDIATE -// | | | ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR -// | | | Added iv_saved_MBA_WRD_MODE to allow -// | | | save/restore of setting for super fast read -// 1.10 | 09/07/12 | gollub | Updates from review. -// | | | Support for more patterns. -// 1.11 | 09/28/12 | gollub | Added mss_restore_DRAM_repairs -// 1.12 | 11/02/12 | gollub | Updates from review. -// 1.13 | 11/08/12 | gollub | Added timebase steer cleanup -// 1.14 | 11/21/12 | gollub | Updates from review. -// 1.15 | 12/19/12 | gollub | Added UE isolation -// 1.16 | 01/31/13 | gollub | Added mss_check_steering -// | | | Added mss_do_steering -// | | | Added mss_stopCmd -// | | | Changed setupAndExecuteCmd to pure virtual -// 1.17 | 08/23/13 | gollub | Added x4 ECC mode support: mss_x4_chip_mark_to_centaurDQ -// 1.18 | 10/31/13 | gollub | Removed support for stop condition enum -// | | | ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR -// 1.19 | 02/07/14 |adityamd | Added support to mss_restore_DRAM_repairs to be accessed at Standby -// 1.20 | 02/20/14 |bellows | RAS update from repairs at standby -// 1.21 | 03/07/14 | gollub | mss_restore_DRAM_repairs_asm: changed i_standby_flag to bool -// 1.22 | 03/11/14 | gollub | SW250519: More options for enum TimeBaseSpeed - - -#ifndef _MSS_MAINT_CMDS_H -#define _MSS_MAINT_CMDS_H - -/** @file mss_maint_cmds.H - * @brief General utility functions to for running maint cmds, - * accessing markstore, and accessing steer muxes. - */ - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <fapi.H> -#include <ecmdDataBufferBase.H> - - - -//------------------------------------------------------------------------------ -// Constants and enums -//------------------------------------------------------------------------------ - -//Structure to get count of repairs applied - -struct repair_count -{ - uint8_t symbolmark_count[8]; - uint8_t chipmark_count[8]; - uint8_t steer_count[8]; -}; - - - -/** - * @brief For index into this table, use 1st symbol index of x8 chip mark / 4. - */ - - - - -static const uint8_t mss_x8_chip_mark_to_centaurDQ[18][2]={ -// centaurDQ port 1st symbol index of chip mark - {64, 1}, // 0 - {64, 0}, // 4 - {56, 1}, // 8 - {48, 1}, // 12 - {40, 1}, // 16 - {32, 1}, // 20 - {24, 1}, // 24 - {16, 1}, // 28 - {8, 1}, // 32 - {0, 1}, // 36 - {56, 0}, // 40 - {48, 0}, // 44 - {40, 0}, // 48 - {32, 0}, // 52 - {24, 0}, // 56 - {16, 0}, // 60 - {8, 0}, // 64 - {0, 0}}; // 68 - -/** - * @brief For index into this table, use 1st symbol index of x4 chip mark / 2. - */ - static const uint8_t mss_x4_chip_mark_to_centaurDQ[36][2]={ -// centaurDQ port 1st symbol index of x4 chip mark - {68, 1}, // 0 - NOTE: not actually valid in x4 mode.... - {64, 1}, // 2 - {68, 0}, // 4 - {64, 0}, // 6 - {60, 1}, // 8 - {56, 1}, // 10 - {52, 1}, // 12 - {48, 1}, // 14 - {44, 1}, // 16 - {40, 1}, // 18 - {36, 1}, // 20 - {32, 1}, // 22 - {28, 1}, // 24 - {24, 1}, // 26 - {20, 1}, // 28 - {16, 1}, // 30 - {12, 1}, // 32 - {8, 1}, // 34 - {4, 1}, // 36 - {0, 1}, // 38 - {60, 0}, // 40 - {56, 0}, // 42 - {52, 0}, // 44 - {48, 0}, // 46 - {44, 0}, // 48 - {40, 0}, // 50 - {36, 0}, // 52 - {32, 0}, // 54 - {28, 0}, // 56 - {24, 0}, // 58 - {20, 0}, // 60 - {16, 0}, // 62 - {12, 0}, // 64 - {8, 0}, // 66 - {4, 0}, // 68 - {0, 0}}; // 70 - - - -/** - * @brief Used to get addess range of all ranks from get_address_range() - */ - const uint8_t MSS_ALL_RANKS = 0xff; - - -/** - * @brief Used to indicate invalid symbol - */ - const uint8_t MSS_INVALID_SYMBOL = 0xff; - - - - namespace mss_SteerMux - { - -/** - * @brief Used to specify read or write steer mux - */ - enum muxType - { - READ_MUX = 0, - WRITE_MUX = 1, - }; - -/** - * @brief Used to specify steer type - */ - enum steerType - { - DRAM_SPARE_PORT0 = 0, // Spare DRAM on port0 - DRAM_SPARE_PORT1 = 1, // Spare DRAM on port1 - ECC_SPARE = 2, // ECC spare (used in x4 mode only) - }; - }; - - - -//------------------------------------------------------------------------------ -// Parent class for all maintenance command types -//------------------------------------------------------------------------------ - -/** - * @brief Contains functions common to multiple maint cmd types. - */ - - class mss_MaintCmd - { - - public: // enums - -/** - * @brief Index into array containing data patterns to load into memory - */ - enum PatternIndex - { - PATTERN_0 = 0, //0x00 - PATTERN_1 = 1, //0xFF - PATTERN_2 = 2, //0xF0 - PATTERN_3 = 3, //0x0F - PATTERN_4 = 4, //0xAA - PATTERN_5 = 5, //0x55 - PATTERN_6 = 6, //0xCC - PATTERN_7 = 7, //0x33 - PATTERN_RANDOM = 8, // random seed - }; - -/** - * @brief Inject type used for atomic error inject maint cmd - */ - enum InjectType - { - ATOMIC_ALT_CE_INJ = 0, - ATOMIC_ALT_CHIPKILL_INJ = 1, - ATOMIC_ALT_UE_INJ = 2, - ATOMIC_ALT_SUE_INJ = 3, - }; - -/** - * @brief Stop conditions for maint cmds. - */ - enum StopCondition - { -// Turn off all stop conditions - NO_STOP_CONDITIONS = 0x0000, - -// Stop immediately if stop on error condition hit - STOP_IMMEDIATE = 0x8000, - -// Stop at end of rank if stop on error condition hit - STOP_END_OF_RANK = 0x4000, - -// Stop on hard new CE error threshlold equal - STOP_ON_HARD_NCE_ETE = 0x2000, - -// Stop on intermittent new CE error threshlold equal - STOP_ON_INT_NCE_ETE = 0x1000, - -// Stop on soft new CE error threshlold equal - STOP_ON_SOFT_NCE_ETE = 0x0800, - -// Stop on symbol corrected error (error on symbol already marked) - STOP_ON_SCE = 0x0400, - -// Stop on mark corrected error (error on chip already marked) - STOP_ON_MCE = 0x0200, - -// Stop on retry CE error threshold equal (UE that went away on retry) - STOP_ON_RETRY_CE_ETE = 0x0100, - -// Stop on mark placed error (hw placed a chip mark) - STOP_ON_MPE = 0x0080, - -// Stop on UE - STOP_ON_UE = 0x0040, - -// Stop on SUE - STOP_ON_SUE = 0x0020, - -// Stop when MBMACAQ = MBMEAQ - STOP_ON_END_ADDRESS = 0x0010, - -// Enable command complete attention - ENABLE_CMD_COMPLETE_ATTENTION = 0x0008, - - }; - -/** - * @brief speed options for time base commands. - */ - enum TimeBaseSpeed - { - /** Background scrubbing (field). */ - BG_SCRUB, - - /** Runtime DRAM repairs procedures (field) and the initial fast scrub - * of memory (field). */ - FAST_MIN_BW_IMPACT, - - /** Background scrubbing (mnfg) and the initial fast scrub of memory - * (mnfg). */ - FAST_MED_BW_IMPACT, - - /** IPL time DRAM repairs procedures (field/mnfg) and runtime DRAM - * repairs procedures (mnfg). */ - FAST_MAX_BW_IMPACT, - }; - - - protected: - -/** - * @brief Maintenance command types - */ - enum CmdType - { - TIMEBASE_READ = 0, - TIMEBASE_SCRUB = 1, - TIMEBASE_STEER_CLEANUP = 2, - TIMEBASE_INIT = 3, - TIMEBASE_RANDOM_INIT = 4, - - SUPERFAST_READ = 8, - SUPERFAST_INIT = 9, - SUPERFAST_RANDOM_INIT = 10, - - MEMORY_DISPLAY = 16, - MEMORY_ALTER = 17, - MEMORY_ALTER_WITH_ECC_OVERRIDE = 18, - ATOMIC_ALTER_ERROR_INJECT = 19, - INCREMENT_MBMACA_ADDRESS = 20, - }; - - - - public: - -/** - * @brief Constructor - * - * @param i_target MBA target - * @param i_startAddr Address cmd will start at - * @param i_endAddr, Address cmd will stop at - * @param i_stopCondition Mask of error conditions cmd should stop on - * @param i_poll Set to true if you wait for command to complete - * @param i_cmdType Command type - */ - mss_MaintCmd( const fapi::Target & i_target, - const ecmdDataBufferBase & i_startAddr, - const ecmdDataBufferBase & i_endAddr, - uint32_t i_stopCondition, - bool i_poll, - CmdType i_cmdType ); - - -/** - * @brief Destructor - */ - virtual ~mss_MaintCmd() {} - - -//---------------------------------------------------------------------- -// These are pure virtual functions that must be defined by every child -// class. -//---------------------------------------------------------------------- - - -/** - * @brief Gets the cmd type of a given object - * @return CmdType - */ - virtual CmdType getCmdType() const = 0; - -/** - * @brief Saves any settings that need to be restored when command is done. - * Loads the setup parameters into the hardware. Starts the command, - * then either polls for complete or exits with command running. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - virtual fapi::ReturnCode setupAndExecuteCmd() = 0; - - - -//---------------------------------------------------------------------- -// These are virtual functions that will have a default definition in this -// class but can be overriden by a child class. -//---------------------------------------------------------------------- - -/** - * @brief Stops running maint cmd, and saves the address it stopped at. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - virtual fapi::ReturnCode stopCmd(); - -/** - * @brief Called once a command is done if we need to restore settings that - * had to be modified to run a specific command type, or clear error - * data in the hw that is no longer relevant. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - * @note NOT YET IMPLEMENTED - */ - virtual fapi::ReturnCode cleanupCmd(); - - protected: -//---------------------------------------------------------------------- -// These are virtual functions that will have a default definition in this -// class but can be overriden by a child class. -//---------------------------------------------------------------------- - -/** - * @brief Checks for valid hw state and setup required before a cmd is run. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - virtual fapi::ReturnCode preConditionCheck(); - -/** - * @brief Loads command type into hw. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - virtual fapi::ReturnCode loadCmdType(); - -/** - * @brief Loads start address into hw. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - virtual fapi::ReturnCode loadStartAddress(); - -/** - * @brief Loads end address into hw. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - virtual fapi::ReturnCode loadEndAddress(); - -/** - * @brief Loads stop conditions into hw. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - virtual fapi::ReturnCode loadStopCondMask(); - -/** - * @brief Starts command. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - virtual fapi::ReturnCode startMaintCmd(); - -/** - * @brief Polls for command complete. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - virtual fapi::ReturnCode pollForMaintCmdComplete(); - -/** - * @brief FOR DEBUG ONLY: Reads hw regs for FFDC after command is done. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - virtual fapi::ReturnCode collectFFDC(); - -/** - * @brief Loads pattern into hw. - * @param i_initPattern Index into array containing patterns to load. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - * @note For now, no array of pattens, just hardcoded pattern of all 0's. - */ - virtual fapi::ReturnCode loadPattern(PatternIndex i_initPattern); - -/** - * @brief Loads timebase speed into hw. - * @param i_speed See enum TimeBaseSpeed - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - virtual fapi::ReturnCode loadSpeed(TimeBaseSpeed i_speed); - -/** - * @brief Checks for hw to be right state after cmd is started. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - * @note For now, no array of pattens, just hardcoded pattern of all 0's. - */ - virtual fapi::ReturnCode postConditionCheck(); - - protected: - - const fapi::Target iv_target; // MBA - fapi::Target iv_targetCentaur; // Centaur associated with this MBA - ecmdDataBufferBase iv_startAddr; // Start address - ecmdDataBufferBase iv_endAddr; // End address - uint32_t iv_stopCondition; // Mask of stop contitions - bool iv_poll; // Set true to wait for cmd complete - const CmdType iv_cmdType; // Command type - uint8_t iv_mbaPosition; // 0 = mba01, 1 = mba23 - - - - - }; - -//------------------------------------------------------------------------------ -// Child classes -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// mss_SuperFastInit -//------------------------------------------------------------------------------ - class mss_SuperFastInit : public mss_MaintCmd - { - public: - -// Constructor - mss_SuperFastInit( const fapi::Target & i_target, // MBA target - const ecmdDataBufferBase & i_startAddr, // Address cmd will start at - const ecmdDataBufferBase & i_endAddr, // Address cmd will stop at - PatternIndex i_initPattern, // Index into table containing patterns to load into memory - uint32_t i_stopCondition, // Mask of error conditions cmd should stop on - bool i_poll ); // Set to true if you wait for command to complete - - public: - - fapi::ReturnCode setupAndExecuteCmd(); - CmdType getCmdType() const { return cv_cmdType; } - -// This class's implementation of parent class functions that can be -// overridden. - - void setStartAddr(ecmdDataBufferBase i_startAddr) - { iv_startAddr = i_startAddr; } - - void setEndAddr( ecmdDataBufferBase i_endAddr ) - { iv_endAddr = i_endAddr; } - - ecmdDataBufferBase getStartAddr() const { return iv_startAddr; } - ecmdDataBufferBase getEndAddr() const { return iv_endAddr; } - - private: - - fapi::ReturnCode setSavedData( uint32_t i_savedData ) - {fapi::ReturnCode l_rc; iv_savedData = i_savedData; return l_rc;} - - uint32_t getSavedData() { return iv_savedData; } - - private: // Class variable(s) - - static const CmdType cv_cmdType; - - private: // Instance variable(s) - -// List of things to save may be cmd-specific, so keep it here for now - uint32_t iv_savedData; -// Index into table containing patterns to load into memory - PatternIndex iv_initPattern; - - }; - - -//------------------------------------------------------------------------------ -// SuperFastRandomInit -//------------------------------------------------------------------------------ - class mss_SuperFastRandomInit : public mss_MaintCmd - { - public: // Constructor(s) - -// Constructor - mss_SuperFastRandomInit( const fapi::Target & i_target, // MBA target - const ecmdDataBufferBase & i_startAddr, // Address cmd will start at - const ecmdDataBufferBase & i_endAddr, // Address cmd will stop at - PatternIndex i_initPattern, // Index into table containing pattern to use for random seed - uint32_t i_stopCondition, // Mask of error conditions cmd should stop on - bool i_poll ); // Set to true if you wait for command to complete - - public: - - fapi::ReturnCode setupAndExecuteCmd(); - CmdType getCmdType() const { return cv_cmdType; } - -// This class's implementation of parent class functions that can be -// overridden. - fapi::ReturnCode cleanupCmd(); - - void setStartAddr(ecmdDataBufferBase i_startAddr) - { iv_startAddr = i_startAddr; } - - void setEndAddr( ecmdDataBufferBase i_endAddr ) - { iv_endAddr = i_endAddr; } - - ecmdDataBufferBase getStartAddr() const { return iv_startAddr; } - ecmdDataBufferBase getEndAddr() const { return iv_endAddr; } - - private: - - fapi::ReturnCode setSavedData( uint32_t i_savedData ) - {fapi::ReturnCode l_rc; iv_savedData = i_savedData; return l_rc;} - - uint32_t getSavedData() { return iv_savedData; } - - private: // Class variable(s) - - static const CmdType cv_cmdType; - - private: // Instance variable(s) - -// List of things to save may be cmd-specific, so keep it here for now - uint32_t iv_savedData; -// Index into table containing patterns to load into memory - PatternIndex iv_initPattern; -// Setting that had to be restored when done - ecmdDataBufferBase iv_saved_MBA_WRD_MODE; - - }; - - - -//------------------------------------------------------------------------------ -// mss_SuperFastRead -//------------------------------------------------------------------------------ - class mss_SuperFastRead : public mss_MaintCmd - { - public: // Constructor(s) - - mss_SuperFastRead( const fapi::Target & i_target, // MBA target - const ecmdDataBufferBase & i_startAddr, // Address cmd will start at - const ecmdDataBufferBase & i_endAddr, // Address cmd will stop at - uint32_t i_stopCondition, // Mask of error conditions cmd should stop on - bool i_poll ); // Set to true if you wait for command to complete - - public: - - fapi::ReturnCode setupAndExecuteCmd(); - CmdType getCmdType() const { return cv_cmdType; } - -// This class's implementation of parent class functions that can be -// overridden. - fapi::ReturnCode cleanupCmd(); - - void setStartAddr(ecmdDataBufferBase i_startAddr) - { iv_startAddr = i_startAddr; } - - void setEndAddr( ecmdDataBufferBase i_endAddr ) - { iv_endAddr = i_endAddr; } - - ecmdDataBufferBase getStartAddr() const { return iv_startAddr; } - ecmdDataBufferBase getEndAddr() const { return iv_endAddr; } - - private: - - fapi::ReturnCode setSavedData( uint32_t i_savedData ) - {fapi::ReturnCode l_rc; iv_savedData = i_savedData; return l_rc; } - - uint32_t getSavedData() { return iv_savedData; } - - fapi::ReturnCode ueTrappingSetup(); - - private: // Class variable(s) - - static const CmdType cv_cmdType; - - private: // Instance variable(s) - -// List of things to save may be cmd-specific, so keep it here for now - uint32_t iv_savedData; -// Setting that had to be restored when done - ecmdDataBufferBase iv_saved_MBA_RRQ0; - - }; - - - -//------------------------------------------------------------------------------ -// mss_AtomicInject -//------------------------------------------------------------------------------ - class mss_AtomicInject : public mss_MaintCmd - { - public: // Constructor(s) - - mss_AtomicInject( const fapi::Target & i_target, // MBA target - const ecmdDataBufferBase & i_startAddr, // Address to inject on - InjectType i_injectType); // Inject type - - - - public: - - fapi::ReturnCode setupAndExecuteCmd(); - CmdType getCmdType() const { return cv_cmdType; } - - void setStartAddr(ecmdDataBufferBase i_startAddr) - { iv_startAddr = i_startAddr; } - - ecmdDataBufferBase getStartAddr() const { return iv_startAddr; } - - void setInjectType(InjectType i_injectType) - { iv_injectType = i_injectType; } - - - private: - - fapi::ReturnCode setSavedData( uint32_t i_savedData ) - {fapi::ReturnCode l_rc; iv_savedData = i_savedData; return l_rc; } - - uint32_t getSavedData() { return iv_savedData; } - - private: // Class variable(s) - - static const CmdType cv_cmdType; - - private: // Instance variable(s) - -// List of things to save may be cmd-specific, so keep it here for now - uint32_t iv_savedData; -// Inject type - InjectType iv_injectType; - }; - - -//------------------------------------------------------------------------------ -// Display -//------------------------------------------------------------------------------ - class mss_Display : public mss_MaintCmd - { - public: // Constructor(s) - - mss_Display( const fapi::Target & i_target, // MBA target - const ecmdDataBufferBase & i_startAddr ); // Address to display - - public: // Function declaration(s) - - fapi::ReturnCode setupAndExecuteCmd(); - CmdType getCmdType() const { return cv_cmdType; } - - void setStartAddr(const ecmdDataBufferBase & i_startAddr) - { iv_startAddr = i_startAddr; } - - ecmdDataBufferBase getStartAddr() const { return iv_startAddr; } - - - private: - - fapi::ReturnCode setSavedData( uint32_t i_savedData ) - {fapi::ReturnCode l_rc; iv_savedData = i_savedData; return l_rc; } - - uint32_t getSavedData() { return iv_savedData; } - - private: // Class variable(s) - - static const CmdType cv_cmdType; - - private: // Instance variable(s) - -// List of things to save may be cmd-specific, so keep it here for now - uint32_t iv_savedData; - }; - - - -//------------------------------------------------------------------------------ -// mss_IncrementAddress -//------------------------------------------------------------------------------ - class mss_IncrementAddress : public mss_MaintCmd - { - public: // Constructor(s) - - mss_IncrementAddress( const fapi::Target & i_target ); // MBA target - - public: - - fapi::ReturnCode setupAndExecuteCmd(); - CmdType getCmdType() const { return cv_cmdType; } - - private: - - static const CmdType cv_cmdType; - }; - - -//------------------------------------------------------------------------------ -// mss_TimeBaseScrub -//------------------------------------------------------------------------------ - class mss_TimeBaseScrub : public mss_MaintCmd - { - public: // Constructor(s) - - mss_TimeBaseScrub( const fapi::Target & i_target, // MBA target - const ecmdDataBufferBase & i_startAddr, // Address cmd will start at - const ecmdDataBufferBase & i_endAddr, // Address cmd will stop at - TimeBaseSpeed i_speed, // See enum TimeBaseSpeed - uint32_t i_stopCondition, // Mask of error conditions cmd should stop on - bool i_poll ); // Set to true if you wait for command to complete - - public: - - fapi::ReturnCode setupAndExecuteCmd(); - CmdType getCmdType() const { return cv_cmdType; } - -// This class's implementation of parent class functions that can be -// overridden. - - void setStartAddr(ecmdDataBufferBase i_startAddr) - { iv_startAddr = i_startAddr; } - - void setEndAddr( ecmdDataBufferBase i_endAddr ) - { iv_endAddr = i_endAddr; } - - ecmdDataBufferBase getStartAddr() const { return iv_startAddr; } - ecmdDataBufferBase getEndAddr() const { return iv_endAddr; } - - private: - - fapi::ReturnCode setSavedData( uint32_t i_savedData ) - {fapi::ReturnCode l_rc; iv_savedData = i_savedData; return l_rc; } - - uint32_t getSavedData() { return iv_savedData; } - - private: // Class variable(s) - - static const CmdType cv_cmdType; - - private: // Instance variable(s) - -// list of things to save may be specific to each cmd, so keep it -// here for now - uint32_t iv_savedData; - -// See enum TimeBaseSpeed - TimeBaseSpeed iv_speed; - }; - - -//------------------------------------------------------------------------------ -// mss_TimeBaseSteerCleanup -//------------------------------------------------------------------------------ - class mss_TimeBaseSteerCleanup : public mss_MaintCmd - { - public: // Constructor(s) - - mss_TimeBaseSteerCleanup( const fapi::Target & i_target, // MBA target - const ecmdDataBufferBase & i_startAddr, // Address cmd will start at - const ecmdDataBufferBase & i_endAddr, // Address cmd will stop at - TimeBaseSpeed i_speed, // See enum TimeBaseSpeed - uint32_t i_stopCondition, // Mask of error conditions cmd should stop on - bool i_poll ); // Set to true if you wait for command to complete - - public: - - fapi::ReturnCode setupAndExecuteCmd(); - CmdType getCmdType() const { return cv_cmdType; } - -// This class's implementation of parent class functions that can be -// overridden. - - void setStartAddr(ecmdDataBufferBase i_startAddr) - { iv_startAddr = i_startAddr; } - - void setEndAddr( ecmdDataBufferBase i_endAddr ) - { iv_endAddr = i_endAddr; } - - ecmdDataBufferBase getStartAddr() const { return iv_startAddr; } - ecmdDataBufferBase getEndAddr() const { return iv_endAddr; } - - private: - - fapi::ReturnCode setSavedData( uint32_t i_savedData ) - {fapi::ReturnCode l_rc; iv_savedData = i_savedData; return l_rc; } - - uint32_t getSavedData() { return iv_savedData; } - - private: // Class variable(s) - - static const CmdType cv_cmdType; - - private: // Instance variable(s) - -// list of things to save may be specific to each cmd, so keep it -// here for now - uint32_t iv_savedData; - -// See enum TimeBaseSpeed - TimeBaseSpeed iv_speed; - }; - - - -//------------------------------------------------------------------------------ -// Utility funcitons -//------------------------------------------------------------------------------ - - -/** - * @brief Calculates start and end address for a single rank, or all ranks - * behind the MBA. - * - * @param i_target MBA target - * @param i_rank Either single rank on the MBA to get start/end address - * for (0x00-0x07) - * Or MSS_ALL_RANKS = 0xff to get start/end address for - * all ranks behind the MBA. - * @param o_startAddr Address to start cmd at. - * @param o_endAddr Address to stop cmd at. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, - uint8_t i_rank, - ecmdDataBufferBase & o_startAddr, - ecmdDataBufferBase & o_endAddr ); - - -/** - * @brief Calculates start and end address for a single slave rank - * - * @param i_target MBA target - * @param i_master master rank corresponding to the desired slave rank on the MBA to get start/end address - * for (0x00-0x07) - * @param i_slave Slave rank to get the address range for - * @param o_startAddr Address to start cmd at. - * @param o_endAddr Address to stop cmd at. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - fapi::ReturnCode mss_get_slave_address_range( const fapi::Target & i_target, - uint8_t i_master, - uint8_t i_slave, - ecmdDataBufferBase & o_startAddr, - ecmdDataBufferBase & o_endAddr ); - - -/** - * @brief Mark store is implemented as one register per rank, so read register - * for the given rank. - * If MPE FIR for the given rank (scrub or fetch) is on after the read, - * we will read one more time to make sure we get latest. - * - * @param i_target MBA target - * @param i_rank Rank to get markstore for. - * @param o_symbolMark Symbol mark, converted from galois field to symbol - * index,(if no mark return 0xff) - * @param o_chipMark Chip mark, converted from galois field to first - * symbol index of the chip, (if no mark return 0xff) - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, - uint8_t i_rank, - uint8_t & o_symbolMark, - uint8_t & o_chipMark ); - - -/** - * @brief Mark store is implemented as one register per rank, so write register - * for the given rank. NOTE: Will be writing to both chip and symbol - * field at same time, so should use a read/modify/write approach to - * avoid unintentionally over-writing something. - * - * @param i_target MBA target - * @param i_rank Rank to write markstore for. - * @param i_symbolMark Symbol index, which will be converted to galois field - * (if input is 0xff, we write 0x00 for no symbol mark). - * @param i_chipMark First symbol index of the chip, which will be - * converted to galois field (if input is 0xff, we write - * 0x00 for no chip mark). - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, - uint8_t i_rank, - uint8_t i_symbolMark, - uint8_t i_chipMark ); - -/** - * @brief Gets either the read or write steer mux control register for the - * given rank, and converts from steer code to x8/x4 dram index to - * first symbol index for all DRAMs steered on that rank. - * - * @param i_target MBA target - * @param i_rank Rank we want to read steer mux for. - * @param i_muxType Select either the read mux or the write mux - * to get. - * @param o_dramSparePort0Symbol First symbol index of the DRAM fixed by the - * spare on port0 (if no steer, return 0xff) - * @param o_dramSparePort1Symbol First symbol index of the DRAM fixed by the - * spare on port1 (if no steer, return 0xff) - * @param o_eccSpareSymbol First symbol index of the DRAM fixed by the - * ECC spare, which can be used on either port0 - * or port1 (if no steer, return 0xff) - * @note The ECC spare is available only with x4 mode ECC. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, - uint8_t i_rank, - mss_SteerMux::muxType i_muxType, - uint8_t & o_dramSparePort0Symbol, - uint8_t & o_dramSparePort1Symbol, - uint8_t & o_eccSpareSymbol ); - -/** - * @brief Updates either the read or write steer mux control register with the - * selected steer type for the given rank. - * - * @param i_target MBA target - * @param i_rank Rank we want to write steer mux for. - * @param i_muxType Select either the read mux or the write mux - * to update. - * @param i_steerType 0 = DRAM_SPARE_PORT0, Spare DRAM on port0 - * 1 = DRAM_SPARE_PORT1, Spare DRAM on port1 - * 2 = ECC_SPARE, ECC spare (used in x4 mode only) - * @param i_symbol First symbol index of the DRAM to steer - * around. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, - uint8_t i_rank, - mss_SteerMux::muxType i_muxType, - uint8_t i_steerType, - uint8_t i_symbol ); - -/** - * @brief Reads the steer muxes for the given rank - * - * @param i_target MBA target - * @param i_rank Rank we want to read steer mux for. - * @param o_dramSparePort0Symbol First symbol index of the DRAM fixed by the - * spare on port0 (if no steer, return 0xff) - * @param o_dramSparePort1Symbol First symbol index of the DRAM fixed by the - * spare on port1 (if no steer, return 0xff) - * @param o_eccSpareSymbol First symbol index of the DRAM fixed by the - * ECC spare, which can be used on either port0 - * or port1 (if no steer, return 0xff) - * @note The ECC spare is available only with x4 mode ECC. - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - fapi::ReturnCode mss_check_steering(const fapi::Target & i_target, - uint8_t i_rank, - uint8_t & o_dramSparePort0Symbol, - uint8_t & o_dramSparePort1Symbol, - uint8_t & o_eccSpareSymbol ); - -/** - * @brief Set write mux, wait for periodic cal, set read mux, for the given rank. - * - * @param i_target MBA target - * @param i_rank Rank we want to write steer mux for. - * @param i_symbol First symbol index of the DRAM to steer - * around. - * @param i_x4EccSpare If true, writes the x4 ECC Spare. Otherwise, - * writes the DRAM spare (default). - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - fapi::ReturnCode mss_do_steering(const fapi::Target & i_target, - uint8_t i_rank, - uint8_t i_symbol, - bool i_x4EccSpare = false ); - - -/** - * @brief This procedure applies the maximum possible DRAM repairs - * (chip/symbol marks, DRAM steers) to known bad bits recorded in - * DIMM VPD. This operation is done on both valid logical DIMM pairs - * behind the given MBA. - * - * @param i_target MBA target - * @param o_repairs_applied 8-bit mask, where a bit set means the - * specified rank had any repairs applied. - * - * rank0 = 0x80 (maps to port0_dimm0, port1_dimm0) - * rank1 = 0x40 (maps to port0_dimm0, port1_dimm0) - * rank2 = 0x20 (maps to port0_dimm0, port1_dimm0) - * rank3 = 0x10 (maps to port0_dimm0, port1_dimm0) - * rank4 = 0x08 (maps to port0_dimm1, port1_dimm1) - * rank5 = 0x04 (maps to port0_dimm1, port1_dimm1) - * rank6 = 0x02 (maps to port0_dimm1, port1_dimm1) - * rank7 = 0x01 (maps to port0_dimm1, port1_dimm1) - * - * @param o_repairs_exceeded 4-bit mask, where a bit set means the - * specified DIMM-select on the specified port - * had more bad bits than could be repaired. - * - * port0_dimm0 = 0x8 - * port0_dimm1 = 0x4 - * port1_dimm0 = 0x2 - * port1_dimm1 = 0x1 - * - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, - uint8_t & o_repairs_applied, - uint8_t & o_repairs_exceeded); - - -/** - * @brief This procedure counts the maximum possible DRAM repairs - * (chip/symbol marks, DRAM steers) to known bad bits recorded in - * DIMM VPD. This operation is done on both valid logical DIMM pairs - * behind the given MBA. - * - * @param i_target MBA target - * @param o_repairs_applied 8-bit mask, where a bit set means the - * specified rank had any repairs applied. - * - * rank0 = 0x80 (maps to port0_dimm0, port1_dimm0) - * rank1 = 0x40 (maps to port0_dimm0, port1_dimm0) - * rank2 = 0x20 (maps to port0_dimm0, port1_dimm0) - * rank3 = 0x10 (maps to port0_dimm0, port1_dimm0) - * rank4 = 0x08 (maps to port0_dimm1, port1_dimm1) - * rank5 = 0x04 (maps to port0_dimm1, port1_dimm1) - * rank6 = 0x02 (maps to port0_dimm1, port1_dimm1) - * rank7 = 0x01 (maps to port0_dimm1, port1_dimm1) - * - * @param o_repairs_exceeded 4-bit mask, where a bit set means the - * specified DIMM-select on the specified port - * had more bad bits than could be repaired. - * - * port0_dimm0 = 0x8 - * port0_dimm1 = 0x4 - * port1_dimm0 = 0x2 - * port1_dimm1 = 0x1 - * - * @param i_strandby_flag Boolean if we are in standby at call time - * - * @param o_repair_count Repair counts - * - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - fapi::ReturnCode mss_restore_DRAM_repairs_asm( const fapi::Target & i_target, - uint8_t & o_repairs_applied, - uint8_t & o_repairs_exceeded, - bool i_standby_flag, - struct repair_count &o_repair_count); - - - - - -/** - * @brief This function takes converts from a Centaur DQ on a given port - * to a corresponding symbol index. - * - * @param i_dq Centaur DQ from 0-71 - * - * @param i_port port 0 or 1 - * - * @return Symbol index - */ - - uint8_t mss_centaurDQ_to_symbol( uint8_t i_dq, uint8_t i_port ); - - -/** - * @brief This function compares trapped actual UE data to an expected - * data pattern in order to identify the bits that contributed to - * a UE encountered during IPL memory diagnostics. - * - * @param i_target MBA target - * @param i_rank Rank containing the UE. - * @param o_bad_bits Map of bad bits (Centaur DQ format) - * 2 ports x 10 bytes - * - * @return Non-SUCCESS if an internal function fails, SUCCESS otherwise. - */ - fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, - uint8_t i_rank, - uint8_t (&o_bad_bits)[2][10]); - - -#endif/* _MSS_MAINT_CMDS_H */ diff --git a/src/include/usr/hwpf/hwp/utility_procedures/p8_cpu_special_wakeup.H b/src/include/usr/hwpf/hwp/utility_procedures/p8_cpu_special_wakeup.H deleted file mode 100644 index 231677691..000000000 --- a/src/include/usr/hwpf/hwp/utility_procedures/p8_cpu_special_wakeup.H +++ /dev/null @@ -1,115 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/utility_procedures/p8_cpu_special_wakeup.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: p8_cpu_special_wakeup.H,v 1.7 2013/12/11 20:39:04 stillgs Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_cpu_special_wakeup.H,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_cpu_special_wakeup.H -// *! DESCRIPTION : Set the EX chiplet into Special Wake-up via one of the -// *! entity bits provided -// *! -// *! OWNER NAME : Greg Still Email: stillgs@us.ibm.com -// *! BACKUP NAME : Pradeep CN Email: padeepcn@in.ibm.com -// *! -//------------------------------------------------------------------------------ - -#ifndef _PROC_CPUSPECWKUP_H_ -#define _PROC_CPUSPECWKUP_H_ - - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -#ifndef _PROC_SPCWKUP_ENTITY -#define _PROC_SPCWKUP_ENTITY - -#define NUM_SPCWKUP_ENTITIES 4 -enum PROC_SPCWKUP_ENTITY -{ - HOST, - FSP, - OCC, - PHYP = HOST, - SPW_ALL -}; - - - -#define NUM_SPCWKUP_OPS 3 -enum PROC_SPCWKUP_OPS -{ - SPCWKUP_DISABLE, - SPCWKUP_ENABLE, - SPCWKUP_INIT, - SPCWKUP_FORCE_DEASSERT -}; - - -#endif // _PROC_SPCWKUP_TGTS - - - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*p8_cpu_special_wakeup_FP_t) ( - const fapi::Target&, - PROC_SPCWKUP_OPS, - PROC_SPCWKUP_ENTITY ); - -extern "C" { - -//------------------------------------------------------------------------------ -// Parameter structure definitions -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Function prototype -//------------------------------------------------------------------------------ -/// \param[in] i_ex_target EX target -/// \param[in] i_entity Entity bit to use (OCC, PHYP, FSP) -/// \param[in] i_operation operation to use (SPCWKUP_ENABLE, SPCWKUP_DISABLE) - - -/// \retval ECMD_SUCCESS if something good happens, -/// \retval BAD_RETURN_CODE otherwise -fapi::ReturnCode -p8_cpu_special_wakeup( const fapi::Target& i_ex_target, - PROC_SPCWKUP_OPS i_operation , - PROC_SPCWKUP_ENTITY i_entity ); - -} // extern "C" - -#endif // _PROC_CPUSPECWKUP_H_ diff --git a/src/include/usr/hwpf/hwp/utility_procedures/p8_inst_pm_state.H b/src/include/usr/hwpf/hwp/utility_procedures/p8_inst_pm_state.H deleted file mode 100644 index 9a6989fda..000000000 --- a/src/include/usr/hwpf/hwp/utility_procedures/p8_inst_pm_state.H +++ /dev/null @@ -1,217 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/utility_procedures/p8_inst_pm_state.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: p8_inst_pm_state.H,v 1.7 2014/06/19 14:38:44 cmolsen Exp $ -//------------------------------------------------------------------------------ -// Title: p8_inst_pm_state.H -// Description: Contains definitions needed for calculating the -// Instantaneous PM State (IPMS). -//------------------------------------------------------------------------------ - -#ifndef _P8_INST_PM_STATE_H_ -#define _P8_INST_PM_STATE_H_ - -// ----------------------------------------------------------------------------- -// Includes -// ----------------------------------------------------------------------------- - -#include <fapi.H> -#include <vector> - -//------------------------------------------------------------------------------ -// Defines -//------------------------------------------------------------------------------ - -// The following enum list must start at 0x00 and must increment by 0x01. -// They are used as index to INST_PM_STATE_NAMES[INST_PM_STATE_xyz]. -enum INSTANTANEOUS_IDLE_STATES -{ - INST_PM_STATE_FS_ENTRY = 0x00, - INST_PM_STATE_DS_ENTRY = 0x01, - INST_PM_STATE_FS_EXIT = 0x02, - INST_PM_STATE_DS_EXIT = 0x03, - INST_PM_STATE_FW_ENTRY = 0x04, - INST_PM_STATE_DW_ENTRY = 0x05, - INST_PM_STATE_FW_EXIT = 0x06, - INST_PM_STATE_DW_EXIT = 0x07, - INST_PM_STATE_NAP_ENTRY = 0x08, - INST_PM_STATE_NAP_EXIT = 0x09, - INST_PM_STATE_RUN = 0x0a, - INST_PM_STATE_RUN_OHA_ENTRY = 0x0b, - INST_PM_STATE_PCBS_ANY_ENTRY = 0x0c, // Was not queued - INST_PM_STATE_PCBS_FS_EXIT = 0x0d, // Was not queued - INST_PM_STATE_PCBS_DS_EXIT = 0x0e, // Was not queued - INST_PM_STATE_PCBS_FW_EXIT = 0x0f, // Was not queued - INST_PM_STATE_PCBS_DW_EXIT = 0x10, // Was not queued - INST_PM_STATE_QUEUED_FS_ENTRY = 0x11, // Incl PMC-stuck state - INST_PM_STATE_QUEUED_DS_ENTRY = 0x12, // Incl PMC-stuck state - INST_PM_STATE_QUEUED_FS_EXIT = 0x13, // Incl PMC-stuck state - INST_PM_STATE_QUEUED_DS_EXIT = 0x14, // Incl PMC-stuck state - INST_PM_STATE_QUEUED_FW_ENTRY = 0x15, // Incl PMC-stuck state - INST_PM_STATE_QUEUED_DW_ENTRY = 0x16, // Incl PMC-stuck state - INST_PM_STATE_QUEUED_FW_EXIT = 0x17, // Incl PMC-stuck state - INST_PM_STATE_QUEUED_DW_EXIT = 0x18, // Incl PMC-stuck state - INST_PM_STATE_SPECIAL_WAKEUP = 0x19, - INST_PM_STATE_NAP_STATIC = 0x1a, - INST_PM_STATE_FS_STATIC = 0x1b, - INST_PM_STATE_DS_STATIC = 0x1c, - INST_PM_STATE_FW_STATIC = 0x1d, - INST_PM_STATE_DW_STATIC = 0x1e, - INST_PM_STATE_UNRESOLVED = 0x1f, // Final state, if no other valid state found - INST_PM_STATE_UNDEFINED = 0x20, // Initialized state - INST_PM_STATE_LAST_ENTRY = 0x21 -}; -// The following strings must precisely match the above enum INSTANTANEOUS_IDLE_STATES. -const char * const INST_PM_STATE_NAMES[INST_PM_STATE_LAST_ENTRY] = -{ - "FAST_SLEEP_ENTRY", - "DEEP_SLEEP_ENTRY", - "FAST_SLEEP_EXIT", - "DEEP_SLEEP_EXIT", - "FAST_WINKLE_ENTRY", - "DEEP_WINKLE_ENTRY", - "FAST_WINKLE_EXIT", - "DEEP_WINKLE_EXIT", - "NAP_ENTRY", - "NAP_EXIT", - "RUN", - "RUN_OHA_ENTRY", - "PCBS_ANY_ENTRY", - "PCBS_FAST_SLEEP_EXIT", - "PCBS_DEEP_SLEEP_EXIT", - "PCBS_FAST_WINKLE_EXIT", - "PCBS_DEEP_WINKLE_EXIT", - "QUEUED_FAST_SLEEP_ENTRY", - "QUEUED_DEEP_SLEEP_ENTRY", - "QUEUED_FAST_SLEEP_EXIT", - "QUEUED_DEEP_SLEEP_EXIT", - "QUEUED_FAST_WINKLE_ENTRY", - "QUEUED_DEEP_WINKLE_ENTRY", - "QUEUED_FAST_WINKLE_EXIT", - "QUEUED_DEEP_WINKLE_EXIT", - "SPECIAL_WAKEUP", - "NAP_STATIC", - "FAST_SLEEP_STATIC", - "DEEP_SLEEP_STATIC", - "FAST_WINKLE_STATIC", - "DEEP_WINKLE_STATIC", - "UNRESOLVED", - "UNDEFINED" -}; - - -enum PCBS_FSM_STATES -{ - PCBS_FSM_IDLE = 0x00, // "IDLE" means idling here. Not PM idle. - PCBS_FSM_ANY_IDLE_ENTRY = 0x2e, - PCBS_FSM_ANY_SLEEP_EXIT = 0x50, - PCBS_FSM_ANY_WINKLE_EXIT = 0x51, - PCBS_FSM_DEEP_WINKLE_EXIT = 0x57 -}; - -enum PORRR_START_VECTOR -{ - PORRR_SV_FS_ENTRY = 0x00, - PORRR_SV_DS_ENTRY = 0x01, - PORRR_SV_FS_EXIT = 0x02, - PORRR_SV_DS_EXIT = 0x03, - PORRR_SV_FW_ENTRY = 0x04, - PORRR_SV_DW_ENTRY = 0x05, - PORRR_SV_FW_EXIT = 0x06, - PORRR_SV_DW_EXIT = 0x07, - PORRR_SV_NAP_ENTRY = 0x08, - PORRR_SV_NAP_EXIT = 0x09 -}; - - -// The following enum list must start at 0x00 and must increment by 0x01. -// They are used as index to PMHIST_STATE_NAMES[PMHIST_STATE_xyz]. -enum PMHIST_STATES -{ - PMHIST_STATE_RUN = 0x0, - PMHIST_STATE_SPECIAL_WAKEUP = 0x1, - PMHIST_STATE_NAP = 0x2, - PMHIST_STATE_LEGACY_SLEEP = 0x3, - PMHIST_STATE_FAST_SLEEP = 0x4, - PMHIST_STATE_DEEP_SLEEP = 0x5, - PMHIST_STATE_FAST_WINKLE = 0x6, - PMHIST_STATE_DEEP_WINKLE = 0x7 -}; -// The following strings must precisely match the above enum PMHIST_STATES. -const char * const PMHIST_STATE_NAMES[8] = -{ - "RUN", - "SPECIAL_WAKEUP", - "NAP", - "LEGACY_SLEEP", - "FAST_SLEEP", - "DEEP_SLEEP", - "FAST_WINKLE", - "DEEP_WINKLE" -}; - -// PIRRx masks and meanings -const uint32_t PMC_QUEUE_PENDING_MASK = 0x00000080; -const uint32_t PMC_QUEUE_OP_TYPE_SCOPE_MASK = 0x00000078; -const uint32_t PMC_QUEUE_ASSIST_MASK = 0x00000004; -const uint32_t PMC_QUEUE_NAP_ENTRY = 0x00000020; -const uint32_t PMC_QUEUE_NAP_EXIT = 0x00000030; -const uint32_t PMC_QUEUE_FS_ENTRY = 0x00000040; -const uint32_t PMC_QUEUE_DS_ENTRY = 0x00000048; -const uint32_t PMC_QUEUE_FS_EXIT = 0x00000050; -const uint32_t PMC_QUEUE_DS_EXIT = 0x00000058; -const uint32_t PMC_QUEUE_FW_ENTRY = 0x00000060; -const uint32_t PMC_QUEUE_DW_ENTRY = 0x00000068; -const uint32_t PMC_QUEUE_FW_EXIT = 0x00000070; -const uint32_t PMC_QUEUE_DW_EXIT = 0x00000078; - - - -extern "C" -{ - -// ----------------------------------------------------------------------------- -// Function prototypes -// ----------------------------------------------------------------------------- - -// Determines Instantaneous PM State (IPMS). -fapi::ReturnCode ex_determine_inst_pm_state( const fapi::Target &i_ex_target, - uint32_t i_pm_settle_usec, - uint32_t i_pm_polls, - uint8_t &o_inst_pm_state); -// Determines IPMS from the PM HIST reg state. -fapi::ReturnCode ex_determine_ipms_from_pmhist( const fapi::Target &i_ex_target, - uint32_t i_pmhist_state, - uint8_t &o_inst_pm_state, - bool &o_bGoodState); -// Determines IPMS from the PMC PIRRx registers. -fapi::ReturnCode ex_determine_ipms_from_pirrx( const fapi::Target &i_ex_target, - uint32_t i_pcbs_fsm, - uint32_t i_pmc_queue_state, - uint8_t &o_inst_pm_state, - bool &o_bGoodState); -} - - -#endif diff --git a/src/include/usr/hwpf/hwp/utility_procedures/proc_cpu_special_wakeup.H b/src/include/usr/hwpf/hwp/utility_procedures/proc_cpu_special_wakeup.H deleted file mode 100644 index 1303c0cd3..000000000 --- a/src/include/usr/hwpf/hwp/utility_procedures/proc_cpu_special_wakeup.H +++ /dev/null @@ -1,107 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/utility_procedures/proc_cpu_special_wakeup.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_cpu_special_wakeup.H,v 1.8 2012/08/21 11:39:37 pchatnah Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cpu_special_wakeup.H,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_cpu_special_wakeup.H -// *! DESCRIPTION : Set the EX chiplet into Special Wake-up via one of the -// *! entity bits provided -// *! -// *! OWNER NAME : Greg Still Email: stillgs@us.ibm.com -// *! BACKUP NAME : Pradeep CN Email: padeepcn@in.ibm.com -// *! -//------------------------------------------------------------------------------ - -#ifndef _PROC_CPUSPECWKUP_H_ -#define _PROC_CPUSPECWKUP_H_ - - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -#ifndef _PROC_SPCWKUP_ENTITY -#define _PROC_SPCWKUP_ENTITY -enum PROC_SPCWKUP_ENTITY -{ - HOST = 0X1, - FSP = 0x2, - OCC = 0x3, - PHYP = HOST - -}; - - -enum PROC_SPCWKUP_OPS -{ - SPCWKUP_ENABLE = 0x1, - SPCWKUP_DISABLE = 0x2 -}; - -#endif // _PROC_SPCWKUP_TGTS - - - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*proc_cpu_special_wakeup_FP_t) (const fapi::Target&, PROC_SPCWKUP_OPS , PROC_SPCWKUP_ENTITY ); - -extern "C" { - - - -//------------------------------------------------------------------------------ -// Parameter structure definitions -//------------------------------------------------------------------------------ - - - -//------------------------------------------------------------------------------ -// Function prototype -//------------------------------------------------------------------------------ -/// \param[in] i_target EX target -/// \param[in] i_entity Entity bit to use (OCC, PHYP, FSP) -/// \param[in] i_operation operation to use (SPCWKUP_ENABLE, SPCWKUP_DISABLE) - - -/// \retval ECMD_SUCCESS if something good happens, -/// \retval BAD_RETURN_CODE otherwise -fapi::ReturnCode -proc_cpu_special_wakeup(const fapi::Target& i_target, PROC_SPCWKUP_OPS i_operation , PROC_SPCWKUP_ENTITY i_entity ); - - -} // extern "C" - -#endif // _PROC_CPUSPECWKUP_H_ diff --git a/src/include/usr/hwpf/hwp/winkle_ring_accessors/getL3DeltaDataAttr.H b/src/include/usr/hwpf/hwp/winkle_ring_accessors/getL3DeltaDataAttr.H deleted file mode 100755 index 6c9637669..000000000 --- a/src/include/usr/hwpf/hwp/winkle_ring_accessors/getL3DeltaDataAttr.H +++ /dev/null @@ -1,60 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/include/usr/hwpf/hwp/winkle_ring_accessors/getL3DeltaDataAttr.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getL3DeltaDataAttr.H,v 1.2 2014/03/20 16:24:43 whs Exp $ -/** - * @file getL3DeltaDataAttr.H - * - * @brief Prototype for getL3DeltaDataAttr() - - * fetch L3 delta data attribute based on chip EC and PROC_PBIEX_ASYNC_SEL from data from static arrays (fapiL3DeltaDataAttr.H) - */ - - #ifndef _HWP_GETL3DELTADATAATTR_ - #define _HWP_GETL3DELTADATAATTR_ - -#include <fapi.H> -#include <fapiL3DeltaDataAttr.H> - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*getL3DeltaDataAttr_FP_t) - (const fapi::Target &, uint32_t (&)[DELTA_DATA_SIZE], uint32_t &); - - -extern "C" -{ -/** - * @brief get processor ex func L3 delta data attribute for the specified target CPU. - * - * @param i_fapiTarget - cpu target - * @param o_data - out: L3 delta data data. - * @param o_ringLength - out: Length of decompressed data - * - * @return fapi::ReturnCode - FAPI_RC_SUCCESS if success, - * relevant error code for failure. - */ -fapi::ReturnCode getL3DeltaDataAttr( const fapi::Target &i_fapiTarget, - uint32_t (&o_data)[DELTA_DATA_SIZE], - uint32_t (&o_ringLength)); - -} - -#endif diff --git a/src/include/usr/isteps/istep18list.H b/src/include/usr/isteps/istep18list.H index b9112ce29..b1754ae86 100644 --- a/src/include/usr/isteps/istep18list.H +++ b/src/include/usr/isteps/istep18list.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ +/* Contributors Listed Below - COPYRIGHT 2012,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -40,8 +40,6 @@ #include <initservice/initsvcreasoncodes.H> #include <config.h> -// include prototypes file -#include "../../../usr/hwpf/hwp/tod_init/tod_init.H" namespace INITSERVICE { diff --git a/src/include/usr/hwpf/hwp/tod_init/tod_init_reasoncodes.H b/src/include/usr/isteps/tod_init_reasoncodes.H index c33e7cff6..abe3a9e0c 100644 --- a/src/include/usr/hwpf/hwp/tod_init/tod_init_reasoncodes.H +++ b/src/include/usr/isteps/tod_init_reasoncodes.H @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/include/usr/hwpf/hwp/tod_init/tod_init_reasoncodes.H $ */ +/* $Source: src/include/usr/isteps/tod_init_reasoncodes.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -23,6 +25,8 @@ #ifndef TOD_INIT_REASONCODES_H #define TOD_INIT_REASONCODES_H +//@todo-RTC:149253-Move these to a better place later + #include <hbotcompid.H> namespace TOD diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile deleted file mode 100644 index e2bbd4370..000000000 --- a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile +++ /dev/null @@ -1,432 +0,0 @@ -#-- $Id: cen.dmi.custom.scom.initfile,v 1.21 2014/02/20 15:19:02 garyp Exp $ -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -#-- 1.21|garyp |02/19/14|Added rx_min_eye_width and rx_min_eye_height for manufacturing and lab thresholding -#-- 1.20|jgrell |02/14/14|Corrected FIR_ACTION1 and FIR_MASK settings for SW245013 -#-- 1.19|jgrell |02/12/14|Added FIR_ACTION1 setting and changed FIR_MASK setting for SW245013 -#-- |Added rx_wt_lane_disabled=1 on lane 17 for SW244284 -#-- 1.18|jgrell |11/21/13|Added rx_trc_grp setting at the request of Yuen Tschang -#-- |Set rx_eo_ddc_timeout_sel to 110 for DD2 -#-- 1.17|jgrell |10/29/13|Changed rx_ds_timeout_sel setting to 111 -#-- 1.16|jgrell |10/28/13|Re-enabled recal bits for DD2+ hw -#-- 1.15|jgrell |09/24/13|Changed "1" expression to "any" -#-- 1.13|jgrell |09/17/13|Added DD2 specific inits -#-- 1.11|jgrell |09/12/13|Re-added "Override" scoms -#-- 1.10|jgrell |08/21/13|Removed "Override" scoms -#-- 1.9 |jgrell |06/27/13|Removed previous change and will debug -#-- 1.8 |jgrell |06/25/13|Added DFE override settings and updated sls and dyn_recal_overall timeout settings -#-- 1.7 |jgrell |04/18/13|Added EC level control of the Recal DFE, DDC, and CTLE enable bits. ('0' when EC < 20) -#-- 1.6 |jgrell |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab. -#-- 1.5 |thomsen |03/07/13|Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab. -#-- | | |Fixed address typo on tx_clk_invert entry -#-- 1.4 |thomsen |02/26/13|Fixed typo on lane 22 tx_lane_invert -#-- 1.3 |thomsen |02/18/13|Renamed HW_EXPRESS and VBU_EXPRESS to def_IS_HW & def_IS_VBU. Added target comments, changed to attribute method of setting tx_lane_invert's and added tx_clk_invert -#-- 1.2 |berger |02/01/13|Removed a handful of settings already in the base file, added sim attr for MSB swap and lane invert -#-- 1.1 |thomsen |01/23/13|Created initial version -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- -#-- TARGETS: -#-- SYS. Chiplet target -#-- TGT1. Proc target -#-- TGT2. Connected Chiplet target -#-- TGT3. Connected Proc target - -#--Master list of variables that can be used in this file is at: -#--<Attribute Definition Location> - -SyntaxVersion = 1 - -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Includes -#-- Note: Must include the path to the .define file. -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -include edi.io.define - -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Defines -#-- -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -define def_IS_HW = (SYS.ATTR_IS_SIMULATION == 0); -define def_IS_VBU = (SYS.ATTR_IS_SIMULATION == 1); - -define def_all_lanes=11111; - -#--***************** -#-- set rx_min_eye_width and rx_min_eye_height if in manufacturing mode -#--***************** -scom 0x800.0b(rx_result_chk_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { - bits, scom_data, expr; - rx_min_eye_width, SYS.ATTR_MNFG_DMI_MIN_EYE_WIDTH, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); - rx_min_eye_height, SYS.ATTR_MNFG_DMI_MIN_EYE_HEIGHT, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); -} - - - - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -# __ ____ __ __ -# / / ____ _____ ___ / __ \____ _ _____ _____ / / / /___ -# / / / __ `/ __ \/ _ \ / /_/ / __ \ | /| / / _ \/ ___/ / / / / __ \ -# / /___/ /_/ / / / / __/ / ____/ /_/ / |/ |/ / __/ / / /_/ / /_/ / -# /_____/\__,_/_/ /_/\___/ /_/ \____/|__/|__/\___/_/ \____/ .___/ -# /_/ -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -# rx_lane_pdwn -#scom 0x800.0b(rx_mode_pl)(rx_grp0)(def_all_lanes).0x(cn_gcr_addr){ -# bits, scom_data; -# rx_lane_pdwn, 0b0; -#} - -# tx_lane_pdwn -#scom 0x800.0b(tx_mode_pl)(tx_grp0)(def_all_lanes).0x(cn_gcr_addr){ -# bits, scom_data; -# tx_lane_pdwn, 0b0; -#} -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -# _______ __ __ ___ _ ________ _____ ___ ____________ ______ -# /_ __/ |/ / / / / | / | / / ____/ / _/ | / / | / / ____/ __ \/_ __/ -# / / | / / / / /| | / |/ / __/ / // |/ /| | / / __/ / /_/ / / / -# / / / | / /___/ ___ |/ /| / /___ _/ // /| / | |/ / /___/ _, _/ / / -# /_/ /_/|_| /_____/_/ |_/_/ |_/_____/ /___/_/ |_/ |___/_____/_/ |_| /_/ -# figlet -fslant -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -# These need to come as attributes from the MRW rather than be hardcoded here -#define def_EI_TX_LANE_INVERT_VEC_CEN4 = 0x60003500; # MSBSWAP=0 ON TULETA -#define def_EI_TX_LANE_INVERT_VEC_CEN5 = 0x7FE4FF00; # MSBSWAP=1 ON TULETA -#define def_EI_TX_LANE_INVERT_VEC_CEN6 = 0xED937F00; # MSBSWAP=1 ON TULETA -#define def_EI_TX_LANE_INVERT_VEC_CEN7 = 0xFFF4FF00; # MSBSWAP=1 ON TULETA - -# These only do a scom if the invert attribute is set (saves scom's). The default scanflush value of tx_lane_invert for each lane is '0'. -# Lane 0 -# scom 0x800404000201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_0).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x80000000) > 0; -} -# Lane 1 -# 0x800404010201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_1).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x40000000) > 0; -} -# Lane 2 -# 0x800404020201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_2).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x20000000) > 0; -} -# Lane 3 -# 0x800404030201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_3).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x10000000) > 0; -} -# Lane 4 -# 0x800404040201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_4).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x08000000) > 0; -} -# Lane 5 -# 0x800404050201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_5).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x04000000) > 0; -} -# Lane 6 -# 0x800404060201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_6).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x02000000) > 0; -} -# Lane 7 -# 0x800404070201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_7).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x01000000) > 0; -} -# Lane 8 -# 0x800404080201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_8).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00800000) > 0; -} -# Lane 9 -# 0x800404090201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_9).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00400000) > 0; -} -# Lane 10 -# 0x8004040A0201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_10).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00200000) > 0; -} -# Lane 11 -# 0x8004040B0201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_11).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00100000) > 0; -} -# Lane 12 -# 0x8004040C0201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_12).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00080000) > 0; -} -# Lane 13 -# 0x8004040D0201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_13).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00040000) > 0; -} -# Lane 14 -# 0x8004040E0201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_14).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00020000) > 0; -} -# Lane 15 -# 0x8004040F0201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_15).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00010000) > 0; -} -# Lane 16 -# 0x800404100201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_16).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00008000) > 0; -} -# Lane 17 -# 0x800404110201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_17).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00004000) > 0; -} -# Lane 18 -# 0x800404120201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_18).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00002000) > 0; -} -# Lane 19 -# 0x800404130201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_19).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00001000) > 0; -} -# Lane 20 -# 0x800404140201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_20).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000800) > 0; -} -# Lane 21 -# 0x800404150201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_21).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000400) > 0; -} -# Lane 22 -# 0x800404160201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_22).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000200) > 0; -} -# Lane 23 -# 0x800404170201043F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_23).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000100) > 0; -} - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -# _______ __ ________ __ __ ____ __ -# /_ __/ |/ / / ____/ / / //_/ / _/___ _ _____ _____/ /_ -# / / | / / / / / / ,< / // __ \ | / / _ \/ ___/ __/ -# / / / | / /___/ /___/ /| | _/ // / / / |/ / __/ / / /_ -# /_/ /_/|_| \____/_____/_/ |_| /___/_/ /_/|___/\___/_/ \__/ - -# figlet -fslant -#------------------------------------------------------------------------------------- -#--*********************************************************************************** -# CLK Lane (assigned to bit 31 of TX Lane Invert Attribute) -# 0x800???7008010C3F -scom 0x800.0b(tx_clk_mode_pg)(tx_grp0)(lane_22).0x(cn_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000001) > 0; -} - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -# __ ________ ____ _____ -# / |/ / ___// __ ) / ___/ ______ _____ -# / /|_/ /\__ \/ __ | \__ \ | /| / / __ `/ __ \ -# / / / /___/ / /_/ / ___/ / |/ |/ / /_/ / /_/ / -# /_/ /_//____/_____/ /____/|__/|__/\__,_/ .___/ -# /_/ -# figlet -fslant -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -# TX_MSBSWAP setting via manaual SCOM overrides -# ./iotk put tx_msbswap=1 (only when p# mod 4 = 3 for centaur or mcs mod 4 = 0, ie. grp0) -# 0x800C1C000201043F -scom 0x800.0b(tx_mode_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr) { -bits, scom_data; -tx_msbswap, (ATTR_EI_BUS_TX_MSBSWAP & 0x01); -} - -#--************************************************************************************************************** -#---------------------------------------------------------------------------------------------------------------- -# ________________ ____ ________ ____ _ __ __ ___ __ -# / ____/ ____/ __ \ / __ )__ __/ __/ __/__ _____ / __ \____ ______(_) /___ __ / |/ /___ ______/ /__ -# / / __/ / / /_/ / / __ / / / / /_/ /_/ _ \/ ___/ / /_/ / __ `/ ___/ / __/ / / / / /|_/ / __ `/ ___/ //_/ -# / /_/ / /___/ _, _/ / /_/ / /_/ / __/ __/ __/ / / ____/ /_/ / / / / /_/ /_/ / / / / / /_/ (__ ) ,< -# \____/\____/_/ |_| /_____/\__,_/_/ /_/ \___/_/ /_/ \__,_/_/ /_/\__/\__, / /_/ /_/\__,_/____/_/|_| -# /____/ -#---------------------------------------------------------------------------------------------------------------- -#--************************************************************************************************************** -# HW242564: Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab. -# 0x800???0002011E3F -# This is applied to all configured clkgrp's via chiplet targetting -scom 0x800.0b(rx_fir1_mask_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { -bits, scom_data; -rx_pg_fir_err_mask_gcr_buff, 0b1; -} -scom 0x800.0b(tx_fir_mask_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr) { -bits, scom_data; -tx_pg_fir_err_mask_gcr_buff, 0b1; -} -scom 0x800.0b(rx_fir_mask_pb)(rx_grp0)(lane_na).0x(cn_gcr_addr) { -bits, scom_data; -rx_pb_fir_err_mask_gcr_buff0, 0b1; -rx_pb_fir_err_mask_gcr_buff1, 0b1; -rx_pb_fir_err_mask_gcr_buff2, 0b1; -} - -# Mask off all rx and tx parity errors in the fir register -# SCOM_FIR_MASK_PB: setting from SW245013 -scom 0x02010403 { -scom_data; -0xDFFFFFFFFFFF0000; -} - -# SCOM_FIR_ACTION1_PB: setting from SW245013 -scom 0x02010407 { -scom_data; -0xFFDFFFFFFFFFC000; -} - -#--************************************************************************************************************** -#---------------------------------------------------------------------------------------------------------------- -# Recal (and part of DMI DFE Override) -#---------------------------------------------------------------------------------------------------------------- -#--************************************************************************************************************** -# HW235842 and HW244323 - -scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { -bits, scom_data, expr; -rx_rc_enable_dfe_h1_cal, 0b0, ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0 || ATTR_DMI_DFE_OVERRIDE==1; -rx_rc_enable_ddc, 0b0, ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0; -rx_rc_enable_ctle_cal, 0b0, ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0; -rx_rc_enable_h1ap_tweak, 0b0, ATTR_DMI_DFE_OVERRIDE==1; -} - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -# DMI DFE Override (HW244323) -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -#scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0)(lane_na).0x(dmi0_gcr_addr) { -#bits, scom_data, expr; -#rx_rc_enable_dfe_h1_cal, 0b0, ATTR_DMI_DFE_OVERRIDE==1; -#rx_rc_enable_h1ap_tweak, 0b0, ATTR_DMI_DFE_OVERRIDE==1; -#} - -scom 0x800.0b(rx_eo_step_cntl_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { -bits, scom_data, expr; -rx_eo_enable_dfe_h1_cal, 0b0, ATTR_DMI_DFE_OVERRIDE==1; -rx_eo_enable_h1ap_tweak, 0b0, ATTR_DMI_DFE_OVERRIDE==1; -} - -scom 0x800.0b(rx_amax_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { -bits, scom_data, expr; -rx_amax_high, 0b01101110, ATTR_DMI_DFE_OVERRIDE==1; -rx_amax_low, 0b01010000, ATTR_DMI_DFE_OVERRIDE==1; -} - -scom 0x800.0b(rx_amp_val_pl)(rx_grp0)(def_all_lanes).0x(cn_gcr_addr) { -bits, scom_data, expr; -rx_amp_gain, 0b1001, ATTR_DMI_DFE_OVERRIDE==1; -} - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -#-- DD2 Centaur -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { - bits, scom_data, expr; - rx_sls_timeout_sel_dd2, 0b1010, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; - rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; - rx_cl_timeout_sel_dd2, 0b010, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; - rx_wt_timeout_sel_dd2, 0b111, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; - rx_ds_timeout_sel_dd2, 0b111, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; -} - -scom 0x800.0b(rx_trace_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { - bits, scom_data, expr; - rx_trc_grp, 0b000000, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; -} - -scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { - bits, scom_data, expr; - rx_eo_ddc_timeout_sel, 0b110, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; -} - - -#--************************************************************************************************************** -#---------------------------------------------------------------------------------------------------------------- -# Power Down & Disable Unused Lanes -#---------------------------------------------------------------------------------------------------------------- -#--************************************************************************************************************** - -scom 0x800.0b(rx_mode_pl)(rx_grp0)(lane_17).0x(cn_gcr_addr) { -bits, scom_data; -rx_lane_pdwn, 0b1; -} - -scom 0x800.0b(rx_wt_status_pl)(rx_grp0)(lane_17).0x(cn_gcr_addr) { -bits, scom_data; -rx_wt_lane_disabled, 0b1; -} - -############################################################################################ -# END OF FILE -############################################################################################ diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile deleted file mode 100644 index ea1556a2b..000000000 --- a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile +++ /dev/null @@ -1,656 +0,0 @@ -#-- $Id: cen.dmi.scom.initfile,v 1.20 2013/12/04 17:43:33 jgrell Exp $ - - -#################################################################### -## -## Auto-genrated by fig2scominit.pl -## Based on SETUP_ID_MODE DMI_BUS_TR_HW -## from ../../logic/mesa_sim/fusion/run/IODNC_MB_TOP.IODNC_MB_TOP.figdb -## -## Created on Tue Nov 26 11:34:19 CST 2013, by jgrell -#################################################################### - -## -- CHANGE HISTORY: - ## -------------------------------------------------------------------------------- - ## -- VersionID: |Author: | Date: | Comment: - ## -- -----------|---------|--------|------------------------------------------------- - ## -- jgr13112600| jgr |11-26-13| CYC rx_ds_timeout_sel setting changed to 111 - ## -- jgr13102800| jgr |10-28-13| zcal address fix and rx_ds_timeout_sel change (110 -> 111) - ## -- jgr13082100| jgr |08-21-13| Added tx_zcal inits so they can be removed from scan - ## -- jfg13072400| jfg |07-24-13| HW253558: change pgooddly to MAX from lab feedback - ## -- mbs13071200| mbs |07-12-13| Disable recal adjustment for allv1 (DFE bug) - ## -- mbs13071100| mbs |07-11-13| Updates for HW239870 and HW258990 - ## -- jgr13041800| jgr |04-18-13| Added rx_max_ber_check_count setting to 0x03 - ## -- smr13032500| SMR |03-25-13| Changed rx_dyn_recal_overall_timeout_sel init to 0b100 & rx_sls_timeout_sel init to 0b110 - ## -- jgr13031300| jgr |03-13-13| Added missing entries from rel 0128 - ## -- mbs13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) - ## -- mbs13011000| mbs |01-10-13| Added rx_prot_speed_slct and rx_c4_sel - ## -- smr12112700| SMR |11-27-12| Added rx_dyn_recal_overall_timeout_sel init to 0b001 - ## -- jfg12112101| jfg |11-21-12| Added Zcal inits - ## -- jfg12112100| jfg |11-21-12| Added CU pll modes - ## -- 12111300| berger |11-13-12| Updated with HW eyeopt and recal settings - ## -- 12101900| berger |10-19-12| Updated Z DMI mirror pattern - ## -- 12062500| SMR |06-25-12| HW210654: Added rx_sls_timeout_sel default of 1 - ## -- 12041000| berger |04-10-12| Added Z specific settings (scramble tap points, start/end/width id's) - ## -- 12021601|mbs |02-16-12| Broke Centaur rx 6 pack into 4 and 2 - ## -- 11012500| mbs |01-25-12| Swizzle and typo fixes for HW191494, HW191518, HW188304 - ## -- 12011800| RJR |01-18-12| Added RX_CTL2_REGS FILE REFERENCES Issue HW164277 - ## -- 11121500| thomsen |12-15-11| Added Per-Pack GCR SCOM Addresses for Regchk (HW188381,HW182867) - ## -- | | | Removed 0x0000040000000000 from TX address definitions since it is in the lower level figtree files (HW187781,HW187893) - ## -- 11120700| mbs |12-07-11| Fixed RX mirror prbs swizzle for Centaur (HW187542) - ## -- 11120500| thomsen |12-05-11| Changed TX.TXCTL.TX_CTL_REGS.base_addr from all 0's to 0x000004.... to set group address to TX - ## -- 11111702| jg |11-17-11| HW184269: Changed swizzle for Centaur - ## -- 11102100| SMR |10-21-11| HW181193: Added rx_dyn_rpr_enc_bad_data_lane_width register - ## -- 11092900| SMR |09-29-11| HW171978: Added dyn rpr error tallying defaults - ## -- 11050300| SMR |05-02-11| Added tx_max_bad_lanes - ## -- 11032200| jg |02-17-11| Added RX PLLREG register offsets - ## -- 11022800| thomsen |02-28-11| Fixed RX/TX scramble tap pattern match problem between driver and receiver. Also fixed in iodpv_mc_wrap.fig. - ## -- 11021700| thomsen |02-17-11| Fixed RX_BUS_WIDTH from 24 to 17 - ## -- 11021600| thomsen |02-16-11| Added Per-Bus, Per-Lane and Per-Group GCR SCOM addresses so Regchk would pass - ## -- 11020200| thomsen |02-02-11| Added RX & TX scramble/descramble tap ID settings - ## -- 11012500| berger |01-25-11| added TX lane disable and rx_bus_width fields, added missing SETUP_ID fields - ## -- 11010600| berger |01-06-11| added lane disable and max bad lane - ## -- 11010400| thomsen |01-04-11| Changed TX_BUS_WIDTH from 17 to 24 - ## -- 10121600| thomsen |12-16-10| Added RX_FENCE - ## -- 10121300| thomsen |12-13-10| Swapped DMI_BUS END_LANE_ID values per HW133020 - ## -- 10120800| thomsen |12-08-10| Added TX_BUS_WIDTH and Z support - ## -- 10112900| thomsen |11-29-10| Fixed BUS_ID's and GROUP_ID's for TX - ## -- 10102600| thomsen |10-26-10| Initial version - ## -------------------------------------------------------------------------------- - - -SyntaxVersion = 1 - - - -#################################################################### -# Define File -#################################################################### -include edi.io.define - - define def_IS_HW = SYS.ATTR_IS_SIMULATION == 0; - define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1; - - - -#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_P_4X_PB -scom 0x800F1C000201043F { - bits, scom_data, expr; - tx_zcal_p_4x, 0b00100, any; -} - -#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_SWO2_PB -scom 0x800F2C000201043F { - bits, scom_data, expr; - tx_zcal_sm_max_val, 0b1000110, any; - tx_zcal_sm_min_val, 0b0010101 , def_IS_HW; - tx_zcal_sm_min_val, 0b0010110 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG -scom 0x800AF0000201043F { - bits, scom_data, expr; - rx_max_ber_check_count, 0b00000011 , def_IS_HW; - rx_max_ber_check_count, 0b00000000 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP -scom 0x800B78000201043F { - bits, scom_data, expr; - rx_amin_cfg, 0b111 , def_IS_HW; - rx_amin_cfg, 0b000 , def_IS_VBU; - rx_anap_cfg, 0b10 , def_IS_HW; - rx_anap_cfg, 0b00 , def_IS_VBU; - rx_h1_cfg, 0b01 , def_IS_HW; - rx_h1_cfg, 0b00 , def_IS_VBU; - rx_peak_cfg, 0b10 , def_IS_HW; - rx_peak_cfg, 0b00 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP -scom 0x800B80000201043F { - bits, scom_data, expr; - rx_ber_cfg, 0b100 , def_IS_HW; - rx_ber_cfg, 0b000 , def_IS_VBU; - rx_dac_bo_cfg, 0b101 , def_IS_HW; - rx_dac_bo_cfg, 0b000 , def_IS_VBU; - rx_ddc_cfg, 0b10 , def_IS_HW; - rx_ddc_cfg, 0b00 , def_IS_VBU; - rx_init_tmr_cfg, 0b111 , def_IS_HW; - rx_init_tmr_cfg, 0b000 , def_IS_VBU; - rx_prot_cfg, 0b10 , def_IS_HW; - rx_prot_cfg, 0b00 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG -scom 0x800A18000201043F { - bits, scom_data, expr; - rx_dyn_recal_overall_timeout_sel, 0b100, any; -} - -#RX.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_TIMEOUTS_PP -scom 0x800B40000201043F { - bits, scom_data, expr; - rx_dyn_recal_interval_timeout_sel, 0b101, any; -} - -#RX.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG -scom 0x8009D8000201043F { - bits, scom_data, expr; - rx_dyn_rpr_bad_lane_max, 0b0001111, any; - rx_dyn_rpr_enc_bad_data_lane_width, 0b101, any; - rx_dyn_rpr_err_cntr1_duration, 0b0111, any; -} - -#RX.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG -scom 0x800AE0000201043F { - bits, scom_data, expr; - rx_dyn_rpr_bad_bus_max, 0b0111111, any; - rx_dyn_rpr_err_cntr2_duration, 0b0111, any; -} - -#RX.RXCTL.RX_CTL_REGS.RX_EO_CONVERGENCE_PG -scom 0x800A80000201043F { - bits, scom_data, expr; - rx_eo_converged_end_count, 0b0111 , def_IS_HW; - rx_eo_converged_end_count, 0b0011 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG -scom 0x800A38000201043F { - bits, scom_data, expr; - rx_eo_enable_ber_test, 0b1 , def_IS_HW; - rx_eo_enable_ber_test, 0b0 , def_IS_VBU; - rx_eo_enable_ctle_cal, 0b1 , def_IS_HW; - rx_eo_enable_ctle_cal, 0b0 , def_IS_VBU; - rx_eo_enable_ddc, 0b1 , def_IS_HW; - rx_eo_enable_ddc, 0b0 , def_IS_VBU; - rx_eo_enable_dfe_h1_cal, 0b1 , def_IS_HW; - rx_eo_enable_dfe_h1_cal, 0b0 , def_IS_VBU; - rx_eo_enable_final_l2u_adj, 0b1, any; - rx_eo_enable_h1ap_tweak, 0b1 , def_IS_HW; - rx_eo_enable_h1ap_tweak, 0b0 , def_IS_VBU; - rx_eo_enable_latch_offset_cal, 0b1 , def_IS_HW; - rx_eo_enable_latch_offset_cal, 0b0 , def_IS_VBU; - rx_eo_enable_result_check, 0b1 , def_IS_HW; - rx_eo_enable_result_check, 0b0 , def_IS_VBU; - rx_eo_enable_vga_cal, 0b1 , def_IS_HW; - rx_eo_enable_vga_cal, 0b0 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_FENCE_PG -scom 0x8009A8000201043F { - bits, scom_data, expr; - rx_fence, 0b1, any; -} - -#RX.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x800850000201043F { - bits, scom_data, expr; - rx_bus_id, 0b000000, any; - rx_group_id, 0b000000, any; -} - -#RX.RXCTL.RX_CTL_REGS.RX_ID2_PG -scom 0x800858000201043F { - bits, scom_data, expr; - rx_last_group_id, 0b000000, any; -} - -#RX.RXCTL.RX_CTL_REGS.RX_ID3_PG -scom 0x800860000201043F { - bits, scom_data, expr; - rx_end_lane_id, 0b0010000, any; - rx_start_lane_id, 0b0000000, any; -} - -#RX.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG -scom 0x800928000201043F { - bits, scom_data, expr; - rx_lane_disabled_vec_0_15, 0b0000000000000000, any; -} - -#RX.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG -scom 0x800930000201043F { - bits, scom_data, expr; - rx_lane_disabled_vec_16_31, 0b0111111111111111, any; -} - -#RX.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG -scom 0x8009C0000201043F { - bits, scom_data, expr; - rx_c4_sel, 0b00 , def_IS_HW; - rx_c4_sel, 0b11 , def_IS_VBU; - rx_prot_speed_slct, 0b1 , def_IS_HW; - rx_prot_speed_slct, 0b0 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG -scom 0x800AB8000201043F { - bits, scom_data, expr; - rx_rc_enable_ber_test, 0b1 , def_IS_HW; - rx_rc_enable_ber_test, 0b0 , def_IS_VBU; - rx_rc_enable_ctle_cal, 0b1 , def_IS_HW; - rx_rc_enable_ctle_cal, 0b0 , def_IS_VBU; - rx_rc_enable_ddc, 0b1 , def_IS_HW; - rx_rc_enable_ddc, 0b0 , def_IS_VBU; - rx_rc_enable_dfe_h1_cal, 0b0, any; - rx_rc_enable_h1ap_tweak, 0b0, any; - rx_rc_enable_latch_offset_cal, 0b1 , def_IS_HW; - rx_rc_enable_latch_offset_cal, 0b0 , def_IS_VBU; - rx_rc_enable_result_check, 0b1 , def_IS_HW; - rx_rc_enable_result_check, 0b0 , def_IS_VBU; - rx_rc_enable_vga_cal, 0b1 , def_IS_HW; - rx_rc_enable_vga_cal, 0b0 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO1_PP -scom 0x800B90000201043F { - bits, scom_data, expr; - rx_recal_timeout_sel_b, 0b0110 , def_IS_HW; - rx_recal_timeout_sel_b, 0b1000 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP -scom 0x800B98000201043F { - bits, scom_data, expr; - rx_recal_timeout_sel_g, 0b0111 , def_IS_HW; - rx_recal_timeout_sel_g, 0b0100 , def_IS_VBU; - rx_recal_timeout_sel_h, 0b1011 , def_IS_HW; - rx_recal_timeout_sel_h, 0b1000 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP -scom 0x800BA0000201043F { - bits, scom_data, expr; - rx_recal_timeout_sel_i, 0b1011 , def_IS_HW; - rx_recal_timeout_sel_i, 0b1000 , def_IS_VBU; - rx_recal_timeout_sel_j, 0b1011 , def_IS_HW; - rx_recal_timeout_sel_j, 0b1000 , def_IS_VBU; - rx_recal_timeout_sel_k, 0b1011 , def_IS_HW; - rx_recal_timeout_sel_k, 0b1000 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP -scom 0x800B60000201043F { - bits, scom_data, expr; - rx_servo_timeout_sel_b, 0b1010 , def_IS_HW; - rx_servo_timeout_sel_b, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_d, 0b1010 , def_IS_HW; - rx_servo_timeout_sel_d, 0b1000 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP -scom 0x800B68000201043F { - bits, scom_data, expr; - rx_servo_timeout_sel_g, 0b0111 , def_IS_HW; - rx_servo_timeout_sel_g, 0b0100 , def_IS_VBU; - rx_servo_timeout_sel_h, 0b1011 , def_IS_HW; - rx_servo_timeout_sel_h, 0b1000 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP -scom 0x800B70000201043F { - bits, scom_data, expr; - rx_servo_timeout_sel_i, 0b1011 , def_IS_HW; - rx_servo_timeout_sel_i, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_j, 0b1101 , def_IS_HW; - rx_servo_timeout_sel_j, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_k, 0b1101 , def_IS_HW; - rx_servo_timeout_sel_k, 0b1000 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG -scom 0x800910000201043F { - bits, scom_data, expr; - rx_eo_amp_timeout_sel, 0b111 , def_IS_HW; - rx_eo_amp_timeout_sel, 0b110 , def_IS_VBU; - rx_eo_ctle_timeout_sel, 0b111 , def_IS_HW; - rx_eo_ctle_timeout_sel, 0b110 , def_IS_VBU; - rx_eo_ddc_timeout_sel, 0b111 , def_IS_HW; - rx_eo_ddc_timeout_sel, 0b110 , def_IS_VBU; - rx_eo_h1ap_timeout_sel, 0b111 , def_IS_HW; - rx_eo_h1ap_timeout_sel, 0b110 , def_IS_VBU; - rx_eo_offset_timeout_sel, 0b111 , def_IS_HW; - rx_eo_offset_timeout_sel, 0b110 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG -scom 0x800898000201043F { - bits, scom_data, expr; - rx_ds_bl_timeout_sel, 0b101 , def_IS_HW; - rx_ds_bl_timeout_sel, 0b001 , def_IS_VBU; - rx_ds_timeout_sel, 0b111, any; - rx_sls_timeout_sel, 0b110, any; - rx_wt_timeout_sel, 0b111 , def_IS_HW; - rx_wt_timeout_sel, 0b011 , def_IS_VBU; -} - -#RX.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG -scom 0x800998000201043F { - bits, scom_data, expr; - rx_rx_bus_width, 0b0010001, any; - rx_tx_bus_width, 0b0011000, any; -} - -#RX.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG -scom 0x800958000201043F { - bits, scom_data, expr; - rx_wtr_max_bad_lanes, 0b00010, any; -} - -#RX.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG -scom 0x800A30000201043F { - bits, scom_data, expr; - rx_wt_cu_pll_pgooddly, 0b110 , def_IS_HW; - rx_wt_cu_pll_pgooddly, 0b000 , def_IS_VBU; - rx_wt_cu_pll_reset, 0b0 , def_IS_HW; - rx_wt_cu_pll_reset, 0b1 , def_IS_VBU; -} - -#RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B0000201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B0010201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B0060201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, any; -} - -#RX.RXPACKS#0.RXPACK_DEFAULT.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B0050201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, any; -} - -#RX.RXPACKS#1.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B0040201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, any; -} - -#RX.RXPACKS#1.RXPACK_DEFAULT.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B0030201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, any; -} - -#RX.RXPACKS#1.RXPACK_DEFAULT.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B0020201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, any; -} - -#RX.RXPACKS#1.RXPACK_DEFAULT.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B0070201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, any; -} - -#RX.RXPACKS#2.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B0080201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX.RXPACKS#2.RXPACK_DEFAULT.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B0090201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, any; -} - -#RX.RXPACKS#2.RXPACK_DEFAULT.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00E0201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, any; -} - -#RX.RXPACKS#2.RXPACK_DEFAULT.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00A0201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, any; -} - -#RX.RXPACKS#3.RXPACK_DEFAULT.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00C0201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, any; -} - -#RX.RXPACKS#3.RXPACK_DEFAULT.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00D0201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, any; -} - -#RX.RXPACKS#3.RXPACK_DEFAULT.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00B0201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, any; -} - -#RX.RXPACKS#3.RXPACK_DEFAULT.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00F0201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX.RXPACKS#4.RXPACK_4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B0100201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX.RXPACKS#4.RXPACK_4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B0110201043F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#TX.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG -scom 0x800CC4000201043F { - bits, scom_data, expr; - tx_drv_clk_pattern_gcrmsg, 0b00, any; -} - -#TX.TXCTL.TX_CTL_REGS.TX_DYN_RECAL_TIMEOUTS_PP -scom 0x800EAC000201043F { - bits, scom_data, expr; - tx_dyn_recal_interval_timeout_sel, 0b101, any; -} - -#TX.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C94000201043F { - bits, scom_data, expr; - tx_bus_id, 0b000000, any; - tx_group_id, 0b100000, any; -} - -#TX.TXCTL.TX_CTL_REGS.TX_ID2_PG -scom 0x800C9C000201043F { - bits, scom_data, expr; - tx_last_group_id, 0b100000, any; -} - -#TX.TXCTL.TX_CTL_REGS.TX_ID3_PG -scom 0x800CA4000201043F { - bits, scom_data, expr; - tx_end_lane_id, 0b0010111, any; - tx_start_lane_id, 0b0000000, any; -} - -#TX.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG -scom 0x800D1C000201043F { - bits, scom_data, expr; - tx_lane_disabled_vec_0_15, 0b0000000000000000, any; -} - -#TX.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG -scom 0x800D24000201043F { - bits, scom_data, expr; - tx_lane_disabled_vec_16_31, 0b0000000011111111, any; -} - -#TX.TXCTL.TX_CTL_REGS.TX_MODE_PG -scom 0x800C1C000201043F { - bits, scom_data, expr; - tx_max_bad_lanes, 0b00010, any; -} - -#TX.TXPACKS#0.TXPACK_0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434000201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX.TXPACKS#0.TXPACK_0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434010201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX.TXPACKS#0.TXPACK_0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434020201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, any; -} - -#TX.TXPACKS#1.TXPACK_1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434040201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, any; -} - -#TX.TXPACKS#1.TXPACK_1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434030201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, any; -} - -#TX.TXPACKS#1.TXPACK_1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434050201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, any; -} - -#TX.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434060201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, any; -} - -#TX.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434070201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, any; -} - -#TX.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434080201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434090201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340A0201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, any; -} - -#TX.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340B0201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, any; -} - -#TX.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340C0201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, any; -} - -#TX.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340D0201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, any; -} - -#TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340E0201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340F0201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434100201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, any; -} - -#TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434110201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, any; -} - -#TX.TXPACKS#4.TXPACK_4.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434120201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, any; -} - -#TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434130201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, any; -} - -#TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434140201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, any; -} - -#TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434150201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, any; -} - -#TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434160201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x800434170201043F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - - -###################################### -## END OF FILE -####################################### diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile deleted file mode 100755 index b7b5e5beb..000000000 --- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile +++ /dev/null @@ -1,5478 +0,0 @@ -#-- $Id: cen_ddrphy.initfile,v 1.35 2014/05/28 14:46:21 asaetow Exp $ -#-- $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/ -#-- centaur/working/procedures/ec_ind/scoms/cen_ddrphy.initfile,v $ -# -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -# 1.35 |asaetow |05/28/14| Removed v1.34 from working since we will not be GAing with those settings. -# | | | NOTE: Re-evaluation in progress on PLL settings for SP1. -# 1.34 |asaetow |05/22/14| Changed ADR/DP18 PLL charge pump setting from 33x3=99uA to 66x2=132uA. Based on Qual FA sample data's potential DTMOAT leakage suspect Lot7DVBT. -# 1.33 |asaetow |05/14/14| Changed ADR/DP18 VCO bit61 from 0b1 to 0b0 and PLL_TUNEF bit54 from 0b1 to 0b0 to dampen noise. Based on Qual FA sample data. -# | | | Note bit61 is VCO low range from >700MHz to <700MHz. -# | | | Note bit54 is Cap from 2.5pF to 1.0pF. -# 1.32 |mwuu |03/25/14|Changed PERCAL_PWR_DIS -# in RD_DIA_CONFIG5, CONSEQ_PASS in RC_CONFIG2, BIG/SMALL_STEP in WC_CONFIG1, -# FW_RD_WR in WC_CONFIG2, 8 DQS_OFFSET, FW_WR_RD 32 -# NOTE: Backed off RD_DIA_CONFIG3, scom reg seems to get zeroed out when written, under investigation. -# 1.31|mwuu |03/11/14|Changed DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0 -# | | |VCO bits 60:63 to match the DP18 PLL of 700MHz, -# | | |Changed LRDIMM settings GPO, WLO to use attributes -# 1.30|mwuu |01/22/14|Changed DIMM_TYPE fix for DDR4 CDIMM -# 1.29|mwuu |01/14/14|Added VPD attributes for TSYS_ADR, TSYS_DP18, -# | | |changed DIMM_TYPE for obsolete CDIMM enum -# 1.28|mwuu |11/22/13|Update for VPD attributes -# 1.27|mwuu |11/01/13|Had a typo for ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8, -# |port A was getting the value of A9 phase rotator. -# |Using attribute settings for GPO,RLO,WLO for LRDIMM -# 1.27|mwuu |08/22/13|Changed RLO/GPO settings for LRDIMM to be picked up -# |by mss_eff_config_termination. -#-- 1.26|mwuu |07/17/13|Changed FAST_SIM_PC to use SIM attribute, changed -# | | |type1 define to use CUSTOM attribute as well. -# | | |Changed READ_CLOCK section to enable clocks for x4. -#-- 1.25|mwuu |05/08/13|Fixed change in DDR4/DDR3 DIMM type -#-- 1.24|mwuu |04/19/13|Changed to use ATTR_VPD_DIMM_SPARE instead of CDIMM -#-- 1.23|mwuu |04/09/13|Fixed typo ENUM for 2N mode. -#-- 1.22|mwuu |04/04/13|Updated tODTL definition when AL=0, added 2N support -# |changed for LRDIMM: RLO=6, WLO=-1; DDR4 UDIMM mem type -# |changed WC_CONFIG3 bit 48 drive dq on MRS -#-- 1.21|mwuu |02/07/13|Updated PC_CSID register to default CS to high -#-- 1.20|mwuu |01/16/13|Updated TWTR & TRTP define for FW_WR_RD field in -# | | |WC_CONFIG0 and FW_RD_WR in WC_CONFIG2 in 0W spec. -# | | |Thin Oxide hibernation disabled in ATEST & BIT_DIR1 -# | | |registers. -# | | |Changed Bang-Bang Margin in ADR32_SYSCLK_ROT_OVERRIDE -# | | |field of DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 -#-- 1.19|mwuu |12/12/12|Commented out settings for SIM, changed attribute -# | | |to CEN.ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE -#-- 1.18|mwuu |12/03/12|Changed DP18_PLL_CONFIG1 VCO setting -#-- 1.17|mwuu |11/30/12|Changed DP18_PLL_CONFIG0/1 registers & -# | | |DP18_IO_TX_CONFIG0 INTERP_SIG_SLEW field -#-- 1.16|mwuu |11/28/12|Changed ADR TSYS to 0x70 and DP18 TSYS to 0x6B. -# | | |Changed ADR_PLL_VREG_CONFIG0/1 registers. -#-- 1.15|mwuu |11/19/12|Updated TSYS_WR ADR+DP18 with slow process numbers -#-- 1.14|mwuu |11/13/12|Fixed define of Swizzle check, was wrong before. -#-- 1.13|mwuu |11/09/12|Updated SI settings from Paul, new attributes. -# Added dqs swizzle for Glacier0. Added TSYS settings based on freq. -# Changed FW_WR_RD to match DD0 setting. Changed ABORT_ON_CAL_ERR to be -# default. Divided up ADR blocks into ADDR, CNTL, CLK, SPCKE. Added FFE -# settings for drv_imp_dq_dqs. Changed PLL_TUNEMDIV to be same as DD0. -#-- 1.12|bwieman |10/08/12|attempt to restore -#-- 1.11|bellows |10/08/12|moved inifiles to scom sub directory -#-- 1.10|mwuu |08/15/12|Removed bit_disable settings, to be set in FN. -# Cleaned up the settings for sim. Added DIMM functional attribute, -# FIR unmask scom, PC_RESET register -#-- 1.9 |mwuu |06/27/12|Added SYS to IS_SIMULATION attribute -#-- 1.8 |mwuu |06/18/12|Changed to use spares based on DIMM_TYPE, also -# changed FW_RD_WR field to use AL, CL instead of hardcoded value -#-- changed RC_CONFIG3 cal_step_size to 10 from 6 for sim, and default to 0. -#-- 1.7 |mwuu |05/14/12|Fixed missing () in a couple of statements -# | | |changed is_sim in per_cal and zcal section to any -#-- 1.6 |mwuu |05/09/12|Added extra '()' due to compiler change -#-- 1.3 |bellows |05/03/12|Checking in working version -#-- 1.3 |bellows |04/09/12|Updates from menlo - The real VBU config supported -#-- 1.2 |bellows |04/09/12|Updates from menlo -#-- 1.1 |bellows |04/04/12|Created File In Proper Directory -#-- 0.04|bellows |04/04/12|Updates and checking for Judy -#-- 0.03|bellows |03/26/12|Updates -#-- 0.02|bellows |03/07/12|Initial drop from Menlo -#-- 0.01|andrewg |05/24/11|Created sample file -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- - -#--Master list of variables that can be used in this file is at: -#--<Attribute Definition Location> - -SyntaxVersion = 1 - -# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -# !! data fields are right aligned !! -# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -# -# SIM uses type 1B CDIMM, 2Rx8/drop, dual drop, 1600 -# -# 0 = false, anything else = true -# -# need to figure out GPO, WLO, RLO... - -#-- ----------------------------------------------------------------------------- -#-- ----------------------------------------------------------------------------- -#-- -#-- Defines -#-- -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- - -#!!!MW problem with (!def...) - -# defines for parent/child attributes -define CEN = TGT1; # parent Centaur - -# short test for simulation -define def_is_sim = (SYS.ATTR_IS_SIMULATION == 1) ; - -# FAST_SIM_PER_CNTR for periodic calibrations -define def_FAST_SIM_PC = (SYS.ATTR_IS_SIMULATION == 1) ; - -# for real HW uncomment, !!FIX once ATTR_VPD_DIMM_SPARE available [2][4][4] port, dimm, rank -define def_p0_has_spare_full = (ATTR_VPD_DIMM_SPARE[0][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE) ; # spare byte -define def_p0_has_spare_upper = (ATTR_VPD_DIMM_SPARE[0][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE) ; # upper nibble -define def_p0_has_spare_lower = (ATTR_VPD_DIMM_SPARE[0][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE) ; # lower nibble -define def_p0_no_spare = (ATTR_VPD_DIMM_SPARE[0][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE) ; # no spare - -define def_p1_has_spare_full = (ATTR_VPD_DIMM_SPARE[1][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE) ; # spare byte -define def_p1_has_spare_upper = (ATTR_VPD_DIMM_SPARE[1][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE) ; # upper nibble -define def_p1_has_spare_lower = (ATTR_VPD_DIMM_SPARE[1][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE) ; # lower nibble -define def_p1_no_spare = (ATTR_VPD_DIMM_SPARE[1][0][0] == ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE) ; # no spare - -# ports 0,1 must have functional dimms to be valid -define def_valid_p0 = (ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR >> 4); # ((def_is_mba01) || (def_is_mba23)) && -define def_valid_p1 = (ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR & 0x0F); - -# short test for MBA01 or MBA23 -define def_is_mba01 = (ATTR_CHIP_UNIT_POS == 0) ; # MBA01 -define def_is_mba23 = (ATTR_CHIP_UNIT_POS == 1) ; # MBA23 - -# Port 0 valid rank pair[0:3]_p0 -# PRIMARY RANK GROUP -define def_val_prg0_p0 = (ATTR_EFF_PRIMARY_RANK_GROUP0[0] != ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID) ; # valid rank group 0 port0 -define def_val_prg1_p0 = (ATTR_EFF_PRIMARY_RANK_GROUP1[0] != ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID) ; # valid rank group 1 port0 -define def_val_prg2_p0 = (ATTR_EFF_PRIMARY_RANK_GROUP2[0] != ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID) ; # valid rank group 2 port0 -define def_val_prg3_p0 = (ATTR_EFF_PRIMARY_RANK_GROUP3[0] != ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID) ; # valid rank group 3 port0 -# SECONDARY RANK GROUP -define def_val_srg0_p0 = (ATTR_EFF_SECONDARY_RANK_GROUP0[0] != ENUM_ATTR_EFF_SECONDARY_RANK_GROUP0_INVALID) ; # valid rank group 0 port0 -define def_val_srg1_p0 = (ATTR_EFF_SECONDARY_RANK_GROUP1[0] != ENUM_ATTR_EFF_SECONDARY_RANK_GROUP1_INVALID) ; # valid rank group 1 port0 -define def_val_srg2_p0 = (ATTR_EFF_SECONDARY_RANK_GROUP2[0] != ENUM_ATTR_EFF_SECONDARY_RANK_GROUP2_INVALID) ; # valid rank group 2 port0 -define def_val_srg3_p0 = (ATTR_EFF_SECONDARY_RANK_GROUP3[0] != ENUM_ATTR_EFF_SECONDARY_RANK_GROUP3_INVALID) ; # valid rank group 3 port0 -# TERTIARY RANK GROUP -define def_val_trg0_p0 = (ATTR_EFF_TERTIARY_RANK_GROUP0[0] != ENUM_ATTR_EFF_TERTIARY_RANK_GROUP0_INVALID) ; # valid rank group 0 port0 -define def_val_trg1_p0 = (ATTR_EFF_TERTIARY_RANK_GROUP1[0] != ENUM_ATTR_EFF_TERTIARY_RANK_GROUP1_INVALID) ; # valid rank group 1 port0 -define def_val_trg2_p0 = (ATTR_EFF_TERTIARY_RANK_GROUP2[0] != ENUM_ATTR_EFF_TERTIARY_RANK_GROUP2_INVALID) ; # valid rank group 2 port0 -define def_val_trg3_p0 = (ATTR_EFF_TERTIARY_RANK_GROUP3[0] != ENUM_ATTR_EFF_TERTIARY_RANK_GROUP3_INVALID) ; # valid rank group 3 port0 -# QUATERNARY RANK GROUP -define def_val_qrg0_p0 = (ATTR_EFF_QUATERNARY_RANK_GROUP0[0] != ENUM_ATTR_EFF_QUATERNARY_RANK_GROUP0_INVALID) ; # valid rank group 0 port0 -define def_val_qrg1_p0 = (ATTR_EFF_QUATERNARY_RANK_GROUP1[0] != ENUM_ATTR_EFF_QUATERNARY_RANK_GROUP1_INVALID) ; # valid rank group 1 port0 -define def_val_qrg2_p0 = (ATTR_EFF_QUATERNARY_RANK_GROUP2[0] != ENUM_ATTR_EFF_QUATERNARY_RANK_GROUP2_INVALID) ; # valid rank group 2 port0 -define def_val_qrg3_p0 = (ATTR_EFF_QUATERNARY_RANK_GROUP3[0] != ENUM_ATTR_EFF_QUATERNARY_RANK_GROUP3_INVALID) ; # valid rank group 3 port0 -# -# Port 1 valid rank group[0:3]_p1 -# PRIMARY RANK GROUP -define def_val_prg0_p1 = (ATTR_EFF_PRIMARY_RANK_GROUP0[1] != ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID) ; # valid rank group 0 port0 -define def_val_prg1_p1 = (ATTR_EFF_PRIMARY_RANK_GROUP1[1] != ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID) ; # valid rank group 1 port0 -define def_val_prg2_p1 = (ATTR_EFF_PRIMARY_RANK_GROUP2[1] != ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID) ; # valid rank group 2 port0 -define def_val_prg3_p1 = (ATTR_EFF_PRIMARY_RANK_GROUP3[1] != ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID) ; # valid rank group 3 port0 -# SECONDARY RANK GROUP -define def_val_srg0_p1 = (ATTR_EFF_SECONDARY_RANK_GROUP0[1] != ENUM_ATTR_EFF_SECONDARY_RANK_GROUP0_INVALID) ; # valid rank group 0 port0 -define def_val_srg1_p1 = (ATTR_EFF_SECONDARY_RANK_GROUP1[1] != ENUM_ATTR_EFF_SECONDARY_RANK_GROUP1_INVALID) ; # valid rank group 1 port0 -define def_val_srg2_p1 = (ATTR_EFF_SECONDARY_RANK_GROUP2[1] != ENUM_ATTR_EFF_SECONDARY_RANK_GROUP2_INVALID) ; # valid rank group 2 port0 -define def_val_srg3_p1 = (ATTR_EFF_SECONDARY_RANK_GROUP3[1] != ENUM_ATTR_EFF_SECONDARY_RANK_GROUP3_INVALID) ; # valid rank group 3 port0 -# TERTIARY RANK GROUP -define def_val_trg0_p1 = (ATTR_EFF_TERTIARY_RANK_GROUP0[1] != ENUM_ATTR_EFF_TERTIARY_RANK_GROUP0_INVALID) ; # valid rank group 0 port0 -define def_val_trg1_p1 = (ATTR_EFF_TERTIARY_RANK_GROUP1[1] != ENUM_ATTR_EFF_TERTIARY_RANK_GROUP1_INVALID) ; # valid rank group 1 port0 -define def_val_trg2_p1 = (ATTR_EFF_TERTIARY_RANK_GROUP2[1] != ENUM_ATTR_EFF_TERTIARY_RANK_GROUP2_INVALID) ; # valid rank group 2 port0 -define def_val_trg3_p1 = (ATTR_EFF_TERTIARY_RANK_GROUP3[1] != ENUM_ATTR_EFF_TERTIARY_RANK_GROUP3_INVALID) ; # valid rank group 3 port0 -# QUATERNARY RANK GROUP -define def_val_qrg0_p1 = (ATTR_EFF_QUATERNARY_RANK_GROUP0[1] != ENUM_ATTR_EFF_QUATERNARY_RANK_GROUP0_INVALID) ; # valid rank group 0 port0 -define def_val_qrg1_p1 = (ATTR_EFF_QUATERNARY_RANK_GROUP1[1] != ENUM_ATTR_EFF_QUATERNARY_RANK_GROUP1_INVALID) ; # valid rank group 1 port0 -define def_val_qrg2_p1 = (ATTR_EFF_QUATERNARY_RANK_GROUP2[1] != ENUM_ATTR_EFF_QUATERNARY_RANK_GROUP2_INVALID) ; # valid rank group 2 port0 -define def_val_qrg3_p1 = (ATTR_EFF_QUATERNARY_RANK_GROUP3[1] != ENUM_ATTR_EFF_QUATERNARY_RANK_GROUP3_INVALID) ; # valid rank group 3 port0 - -# shorter test for DRAM gen -#define def_is_empty = (ATTR_EFF_DRAM_GEN == ENUM_ATTR_EFF_DRAM_GEN_EMPTY) ; # EMPTY, no dram? -define def_is_ddr3 = (ATTR_EFF_DRAM_GEN == ENUM_ATTR_EFF_DRAM_GEN_DDR3) ; # DDR3 = 1 -define def_is_ddr4 = (ATTR_EFF_DRAM_GEN == ENUM_ATTR_EFF_DRAM_GEN_DDR4) ; # DDR4 = 2 -define def_not_ddr4 = (ATTR_EFF_DRAM_GEN != ENUM_ATTR_EFF_DRAM_GEN_DDR4) ; # not DDR4, (GEN != 2) - -# shorter test for DIMM type -define def_is_rdimm = (ATTR_EFF_DIMM_TYPE == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) ; # RDIMM = 1 -#define def_is_udimm = (ATTR_EFF_DIMM_TYPE == ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) ; # UDIMM = 2 -define def_is_lrdimm = (ATTR_EFF_DIMM_TYPE == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ; # LRDIMM = 3 - -# shorter test for DRAM width -define def_is_x4 = (ATTR_EFF_DRAM_WIDTH == ENUM_ATTR_EFF_DRAM_WIDTH_X4) ; # X4 = 0 -define def_is_x8 = (ATTR_EFF_DRAM_WIDTH == ENUM_ATTR_EFF_DRAM_WIDTH_X8) ; # X8 = 1 -#define def_is_x16 = (ATTR_EFF_DRAM_WIDTH == ENUM_ATTR_EFF_DRAM_WIDTH_X16) ; # X16 = 2 -#define def_is_x32 = (ATTR_EFF_DRAM_WIDTH == ENUM_ATTR_EFF_DRAM_WIDTH_X32) ; # X32 = 3 - -# shorter test for burst length -define def_is_bl8 = (ATTR_EFF_DRAM_BL == ENUM_ATTR_EFF_DRAM_BL8) ; # burst length 8 = (0) -#define def_is_bl_otf = (ATTR_EFF_DRAM_BL == ENUM_ATTR_EFF_DRAM_OTF) ; # burst length on the fly = (1) -#define def_is_bl4 = (ATTR_EFF_DRAM_BL == ENUM_ATTR_EFF_DRAM_BL4) ; # burst length 4 = (2) - -# shorter test for Centaur receiver impedance DQ / DQS -define def_cri_dqs_ohm15_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM15) ; # OHM15 = 0x0F (15) -define def_cri_dqs_ohm20_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM20) ; # OHM20 = 0x14 (20) -define def_cri_dqs_ohm30_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM30) ; # OHM30 = 0x1E (30) -define def_cri_dqs_ohm40_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM40) ; # OHM40 = 0x28 (40) -define def_cri_dqs_ohm48_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM48) ; # OHM48 = 0x30 (48) -define def_cri_dqs_ohm60_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60) ; # OHM60 = 0x3C (60) -define def_cri_dqs_ohm80_p0 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM80) ; # OHM80 = 0x50 (80) -define def_cri_dqs_ohm120_p0= (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM120) ; # OHM120 = 0x78 (120) -define def_cri_dqs_ohm160_p0= (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM160) ; # OHM160 = 0xA0 (160) -define def_cri_dqs_ohm240_p0= (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM240) ; # OHM240 = 0xF0 (240) - -define def_cri_dqs_ohm15_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM15) ; # OHM15 = 0x0F (15) -define def_cri_dqs_ohm20_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM20) ; # OHM20 = 0x14 (20) -define def_cri_dqs_ohm30_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM30) ; # OHM30 = 0x1E (30) -define def_cri_dqs_ohm40_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM40) ; # OHM40 = 0x28 (40) -define def_cri_dqs_ohm48_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM48) ; # OHM48 = 0x30 (48) -define def_cri_dqs_ohm60_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM60) ; # OHM60 = 0x3C (60) -define def_cri_dqs_ohm80_p1 = (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM80) ; # OHM80 = 0x50 (80) -define def_cri_dqs_ohm120_p1= (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM120) ; # OHM120 = 0x78 (120) -define def_cri_dqs_ohm160_p1= (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM160) ; # OHM160 = 0xA0 (160) -define def_cri_dqs_ohm240_p1= (ATTR_EFF_CEN_RCV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_RCV_IMP_DQ_DQS_OHM240) ; # OHM240 = 0xF0 (240) - -# shorter test for Centaur driver impedance DQ / DQS -define def_cdi_dqs_ohm24_p0 = (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0) ; # OHM24 = 0x18 (24) - -define def_cdi_dqs_ohm30_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120)) ; # OHM30 = 0x1E (30) - -define def_cdi_dqs_ohm34_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120)) ; # OHM34 = 0x22 (34) - -define def_cdi_dqs_ohm40_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120)) ; # OHM40 = 0x28 (40) - -define def_cdi_dqs_ohm24_p1 = (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0) ; # OHM24 = 0x18 (24) - -define def_cdi_dqs_ohm30_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120)) ; # OHM30 = 0x1E (30) - -define def_cdi_dqs_ohm34_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120)) ; # OHM34 = 0x22 (34) - -define def_cdi_dqs_ohm40_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120)) ; # OHM40 = 0x28 (40) - -# shorter test for number of FFE slices to enable in TX_CONFIG register -define def_ffe1_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480)) ; - -define def_ffe2_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240)) ; - -define def_ffe3_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160)) ; - -define def_ffe4_p0 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[0] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120)) ; - -define def_ffe1_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480)) ; - -define def_ffe2_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240)) ; - -define def_ffe3_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160)) ; - -define def_ffe4_p1 = ((ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120) || (ATTR_EFF_CEN_DRV_IMP_DQ_DQS[1] == ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120)) ; - -# shorter test for Centaur driver impedance command/address (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE) -define def_cdi_addr_ohm15_p0= (ATTR_VPD_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_addr_ohm20_p0= (ATTR_VPD_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_addr_ohm30_p0= (ATTR_VPD_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_addr_ohm40_p0= (ATTR_VPD_CEN_DRV_IMP_ADDR[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40) ; # OHM40 = 0x28 (40) - -define def_cdi_addr_ohm15_p1= (ATTR_VPD_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_addr_ohm20_p1= (ATTR_VPD_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_addr_ohm30_p1= (ATTR_VPD_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_addr_ohm40_p1= (ATTR_VPD_CEN_DRV_IMP_ADDR[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40) ; # OHM40 = 0x28 (40) - -# shorter test for Centaur driver impedance control (CKE0:1, CKE4:5, ODT0:3, CSN0:7) -define def_cdi_ctl_ohm15_p0 = (ATTR_VPD_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_ctl_ohm20_p0 = (ATTR_VPD_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_ctl_ohm30_p0 = (ATTR_VPD_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_ctl_ohm40_p0 = (ATTR_VPD_CEN_DRV_IMP_CNTL[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40) ; # OHM40 = 0x28 (40) - -define def_cdi_ctl_ohm15_p1 = (ATTR_VPD_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_ctl_ohm20_p1 = (ATTR_VPD_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_ctl_ohm30_p1 = (ATTR_VPD_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_ctl_ohm40_p1 = (ATTR_VPD_CEN_DRV_IMP_CNTL[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40) ; # OHM40 = 0x28 (40) - -# shorter test for Centaur driver impedance clocks (CLK0:3) -define def_cdi_clk_ohm15_p0 = (ATTR_VPD_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_clk_ohm20_p0 = (ATTR_VPD_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_clk_ohm30_p0 = (ATTR_VPD_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_clk_ohm40_p0 = (ATTR_VPD_CEN_DRV_IMP_CLK[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40) ; # OHM40 = 0x28 (40) - -define def_cdi_clk_ohm15_p1 = (ATTR_VPD_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_clk_ohm20_p1 = (ATTR_VPD_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_clk_ohm30_p1 = (ATTR_VPD_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_clk_ohm40_p1 = (ATTR_VPD_CEN_DRV_IMP_CLK[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40) ; # OHM40 = 0x28 (40) - -# shorter test for Centaur driver impedance spare clocks (CKE2:3, CKE6:7) -define def_cdi_spcke_ohm15_p0 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_spcke_ohm20_p0 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_spcke_ohm30_p0 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_spcke_ohm40_p0 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[0] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40) ; # OHM40 = 0x28 (40) - -define def_cdi_spcke_ohm15_p1 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM15) ; # OHM15 = 0x0F (15) -define def_cdi_spcke_ohm20_p1 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM20) ; # OHM20 = 0x14 (20) -define def_cdi_spcke_ohm30_p1 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM30) ; # OHM30 = 0x1E (30) -define def_cdi_spcke_ohm40_p1 = (ATTR_VPD_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40) ; # OHM40 = 0x28 (40) - -# define for glacier1(1), glacier2=normal(0) remove dimm_type != cdimm later -define def_is_type1 = ((ATTR_MSS_DQS_SWIZZLE_TYPE == 1) && (ATTR_EFF_CUSTOM_DIMM != ENUM_ATTR_EFF_CUSTOM_DIMM_YES)); - -# remove dimm_type == cdimm later -define def_is_custom = (ATTR_EFF_CUSTOM_DIMM == ENUM_ATTR_EFF_CUSTOM_DIMM_YES); - -# define for 2 cycle addressing mode (2N) -define def_2N_mode = (ATTR_VPD_DRAM_2N_MODE_ENABLED == ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE) ; - -# fix phase rotators due to NWELL issue -#define def_CL_adj = (CEN.ATTR_MSS_NWELL_MISPLACEMENT * 0x7F); -# 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0[0] | (def_CL_adj)) , (def_is_mba01) ; # P0 L1 , A_A0 centerlane -#define def_PR_adj = (CEN.ATTR_MSS_NWELL_MISPLACEMENT * 32); - -# SIMPLIFY -# ================================================================================ -# test if AL is disabled -define def_AL_ena = (ATTR_EFF_DRAM_AL != 0); -define def_AL_dis = (ATTR_EFF_DRAM_AL == 0); - -# for calculating FW_RD_WR delay... NOTE: AL could be disabled(=0) -#define def_TWTR_PLUS_OFF = (ATTR_EFF_DRAM_TWTR + 11) ; # change from +8 on reg spec -#define def_TRTP_PLUS_AL = (ATTR_EFF_DRAM_TRTP + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL + 3) ; -#define def_TRTP_PLUS_NOAL = (ATTR_EFF_DRAM_TRTP + 3) ; - -# AL={1,2}; max (TWTR + 8, TRTP + CL + AL + GPO) new formula from SWyatt -define def_TWTR_PLUS_OFF = (ATTR_EFF_DRAM_TWTR + 8) ; -define def_TRTP_PLUS_AL = (ATTR_EFF_DRAM_TRTP + ATTR_EFF_DRAM_CL + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL + ATTR_VPD_GPO[0]) ; -define def_TRTP_PLUS_NOAL = (ATTR_EFF_DRAM_TRTP + ATTR_EFF_DRAM_CL + ATTR_VPD_GPO[0]) ; - -# for ODT on/off time calculation during write calibration -# 2tCK = DDR4 feature for extended write preamble, should be defined by attribute if used. -# tODTLON/OFF DDR3=CWL+AL-2, DDR4=CWL+AL-3 if using 2tCK, otherwise same as DDR3 formula -#define def_AL = ((def_AL_ena)*(ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL)); -#define def_tODTL_DDR3 = (ATTR_EFF_DRAM_CWL + def_AL - 2) ; # DDR3 -# should not try to do the defines above... -define def_tODTL_DDR3 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL - 2) ; # DDR3 -define def_tODTL_DDR3_NOAL = (ATTR_EFF_DRAM_CWL - 2) ; # DDR3, no AL -define def_tODTL_DDR4 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL - 3) ; # DDR4 & 2tCK -define def_tODTL_DDR4_NOAL = (ATTR_EFF_DRAM_CWL - 3) ; # DDR4 & 2tCK, no AL - -# def_1PR = 1000*1000 / (FREQ / 2) -# def_dqs_offset = (10 + ((def_p2p_jitter / 2) / def_1PR) + 1) # +1 for ceiling FN -#define def_p2p_jitter = 240 ; # DQS peak to peak jitter in ps -define def_p2p_jitter = 2600 ; # DQS peak to peak jitter in ps -#define def_dqs_offset = (11 + (((def_p2p_jitter) * CEN.ATTR_MSS_FREQ) / 4000000)) ; -define def_dqs_offset = 8 ; # SWyatt - -#--------------------------------------------------------------------------------- - -# ===================================================================================================== -# PHY ADDRESSING -# -# 0x800Pyyyy03011M3F = base address, P=port [0:1], M=MBA {4=MBA01, 8=MBA23}, -# -# yyyy=16 bit PHY address { bits 0:1 = block (00=DP18, 01=ADR, 10=AD32S, 11=Control); -# bits 2:5 = instance select, '1111'=broadcast; -# bits 6:7 = rank pair if applicable (00,01,10,11); -# bit 8 = rank pair broadcast bit -# bits 9:15 = register address within block -# -# ===================================================================================================== -# ***************************************************************************************************** -# ===================================================================================================== -# !! following neo_databook_072911.pdf reset sequence section 3.11.2, pg 116 -# mainly done in /afs/awd/projects/eclipz/KnowledgeBase/eclipz/chips/ -# centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.C -# -# should be these values after running the procedure... -# PC_CONFIG0 = 0x0000 (DDR3) or 0x1202 (DDR4) -# ADR PLL/Vreg Config 0 = 0x0000 -# ADR PLL/Vreg Config 1 = 0x0040 -# DP18 PLL/Vreg Config 0 = 0x0000 -# DP18 PLL/Vreg Config 1 = 0x0040 -# DPHY01.DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 = 0x8020 -# DPHY01.DDRPHY_DP18_SYSCLK_PR_P0_0 = 0x8020 -# DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 = 0x0010 -# ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -# --------------------------------------------------------------------------------------- -# Pervasive FIR registers -# -# Error mask register where (Action0, Action1, Mask) = Action Select; -# -# (0,0,x) = No Error reported -# (0,1,0) = Recoverable Error -# (1,0,0) = Checkstop Error -# (1,1,0) = Local Core Checkstop -# (x,x,1) = MASKED -# -# PHY01_DDRPHY_FIR_REG default=0 0x800200900301143f -# PHY01_DDRPHY_FIR_MASK_REG default=0 0x800200930301143f -# PHY01_DDRPHY_FIR_ACTION0_REG default=0 0x800200960301143f -# PHY01_DDRPHY_FIR_ACTION1_REG default=0 0x800200970301143f -# PHY01_DDRPHY_FIR_WOF_REG default=0 0x800200980301143f -# -# PHY01_DDRPHY_FIR_MASK_REG default=0 0x800200930301143f -# scomx.fir0.fir_mask_lt -scom 0x800200930301143f { # covers both ports - # 48:52 = port0 { FSM, parity, cal, FSM recover, parity recover } - # 53 = port 0/1 FIR parity recover error - # 56:60 = port1 { FSM, parity, cal, FSM recover, parity recover } - scom_data , expr ; - # fix for DD1 mask all PHY FIR bits. - 0x000000000000FFFF , (CEN.ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE) ; - 0x0000000000000000 , any ; -} - -# --------------------------------------------------------------------------------------- -# PC Config0 -# -# ddr3=0x0000, ddr4=0x1202 # !! set in ddr_phy_reset -# -# DPHY01.DDRPHY_PC_CONFIG0_P[0:1] 0x00C 0x8000c00c0301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG12_L2 -scom 0x800(0,1)C00C0301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # Protocol, 0=DDR3, 1=DDR4, 2=RLDRAM2 CIO, 4=RLDRAM3 - 48:51 , 0b0001 , (def_is_ddr4) ; # ATTR_EFF_DRAM_GEN=2=DDR4 - 48:51 , 0b0000 , (def_not_ddr4) ; # ATTR_EFF_DRAM_GEN=1=DDR3 or 0=empty - 52 , 0b0 , any ; # 1=DATA_MUX4_1MODE, 0=2:1 data mux - 53 , 0b0 , any ; # Split access mode(on primary rank) enable - 54 , 0b1 , (def_is_ddr4) ; # DDR4 cmd/addr signal reduction enable - 54 , 0b0 , (def_not_ddr4) ; # disable for DDR3 - 55 , 0b0 , any ; # SysClK 2x Mem Internal CLK - 56 , 0b0 , any ; # Rank Override enable - 57:59 , 0b000 , any ; # Rank Override value -# DDR4_RD_PREAMBLE_TRAIN ? - 60 , 0b0 , any ; # low latency (ERS Mode), 1=force off, 0=auto -# DDR4_BANK_REFRESH ? -# 61 , 0b0 , any ; # reserved - 62 , 0b1 , (def_is_ddr4) ; # enable DDR4_VLEVEL_BANK_GROUP - 62 , 0b0 , (def_not_ddr4) ; # disable for DDR3 -# DDR4_DQ_LINK_TRAIN ? - 63 , 0b0 , any ; # ZCAL_NOT_CONT (set to continuously int zcal) -} - -# --------------------------------------------------------------------------------------- -# PC_CONFIG1 -# -# DPHY01.DDRPHY_PC_CONFIG1_P0 -scom 0x8000C00D0301143F { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# # WLO is normally 0 except for RDIMM (RCD) configurations in which case it's set to 1 -# DD0 = PORT_BUFFER_LATENCY -# 48:51 , 0xF , (def_is_lrdimm) ; # LRDIMM set WLO=-1 - 48:51 , (ATTR_VPD_WLO[0]), any ; # based on attribute now.. -# 48:51 , 0x1 , (def_is_rdimm) ; # RDIMM -# 48:51 , 0x0 , any ; # WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7) -# # 9.4.12.2 RLO = READ_LATENCY_OFFSET (2's complement -8 to 7) {0=CDIMM, 1=RDIMM, 2=LRDIMM} -# 52:55 , 0x1 , (def_is_rdimm) ; # RDIMM -# 52:55 , 0x0 , any ; # CDIMM/UDIMM -# 52:55 , 0x6 , (def_is_lrdimm) ; # LRDIMM # !! need to review LR settings !! -# 52:55 , (ATTR_VPD_RLO[0] + 1), (def_2N_mode) ; # based on attribute now.. - 52:55 , (ATTR_VPD_RLO[0]), any ; # based on attribute now.. - 56 , 0b0 , any ; # MEMCTL_CIC_FAST - 57 , 0b0 , any ; # MEMCTL_CTRN_IGNORE - 58 , 0b0 , any ; # DISABLE_MEMCTL_CAL -# Memory Type -# # 59:61 , 000=DDR3/DDR4 CDIMM, DDR3 (001=RDIMM, 011=LRDIMM), DDR4 (101=RDIMM, 111=LRDIMM) - 59 , 0b0 , (def_is_custom) ; # special for CDIMM - 59 , 0b1 , (def_is_ddr4) ; # DDR4 - 59 , 0b0 , any ; # DDR3 or custom - - 60 , 0b1 , (def_is_lrdimm) ; # LRDIMM - 60 , 0b0 , any ; # not LRDIMM - - 61 , 0b1 , ((def_is_lrdimm) || (def_is_rdimm)) ; # registered C/A - 61 , 0b0 , any ; # unbuffered C/A -# 59:61 , 0b000 , (def_is_cdimm) ; # CDIMM -# 59:61 , 0b001 , ((def_is_rdimm) && (def_is_ddr3)) ; # DDR3 RDIMM -# 59:61 , 0b011 , ((def_is_lrdimm) && (def_is_ddr3)) ; # DDR3 LRDIMM -# 59:61 , 0b101 , ((def_is_rdimm) && (def_is_ddr4)) ; # DDR4 RDIMM -# 59:61 , 0b111 , ((def_is_lrdimm) && (def_is_ddr4)) ; # DDR4 LRDIMM -# 62 , 0b1 , any ; # DDR4 Latency Chicken SW -# 63 , 0b0 , any ; # Retrain_Percal_SW -} - -# DPHY01.DDRPHY_PC_CONFIG1_P1 -scom 0x8001C00D0301143F { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# # WLO is normally 0 except for RDIMM (RCD) configurations in which case it's set to 1 -# DD0 = PORT_BUFFER_LATENCY -# 48:51 , 0xF , (def_is_lrdimm) ; # LRDIMM set WLO=-1 - 48:51 , (ATTR_VPD_WLO[1]), any ; # based on attribute now.. -# 48:51 , 0x1 , (def_is_rdimm) ; # RDIMM -# 48:51 , 0x0 , any ; # WLO=WRITE_LATENCY_OFFSET (2's complement -8 to 7) -# # 9.4.12.2 RLO = READ_LATENCY_OFFSET (2's complement -8 to 7) {0=CDIMM, 1=RDIMM, 2=LRDIMM} -# 52:55 , 0x6 , (def_is_lrdimm) ; # LRDIMM -# 52:55 , (ATTR_VPD_RLO[1] + 1), (def_2N_mode) ; # based on attribute now.. - 52:55 , (ATTR_VPD_RLO[1]), any ; # based on attribute now.. -# 52:55 , 0x1 , (def_is_rdimm) ; # RDIMM -# 52:55 , 0x0 , any ; # CDIMM/UDIMM - 56 , 0b0 , any ; # MEMCTL_CIC_FAST - 57 , 0b0 , any ; # MEMCTL_CTRN_IGNORE - 58 , 0b0 , any ; # DISABLE_MEMCTL_CAL -# Memory Type -# # 59:61 , 000=DDR3/DDR4 CDIMM, DDR3 (001=RDIMM, 011=LRDIMM), DDR4 (101=RDIMM, 111=LRDIMM) - 59 , 0b0 , (def_is_custom) ; # special for CDIMM - 59 , 0b1 , (def_is_ddr4) ; # DDR4 - 59 , 0b0 , any ; # DDR3 or custom - - 60 , 0b1 , (def_is_lrdimm) ; # LRDIMM - 60 , 0b0 , any ; # not LRDIMM - - 61 , 0b1 , ((def_is_lrdimm) || (def_is_rdimm)) ; # registered C/A - 61 , 0b0 , any ; # unbuffered C/A -# 62 , 0b1 , any ; # DDR4 Latency Chicken SW -# 63 , 0b0 , any ; # Retain_Percal_SW -} - -# --------------------------------------------------------------------------------------- -# PC Resets register default=0xC000 -# -# This register provides the capability to initiate resets in the hard cores. -# -# DPHY01_DDRPHY_PC_RESETS_P0 0x8000c00e0301143f -scom 0x800(0,1)C00E0301143F { # Port[0:1] - bits , scom_data ; -# 0:47 , 0x000000000000 ; # reserved - 48 , 0b1 ; # PLL_RESET (all PLL's) - 49 , 0b1 ; # SYSCLK_RESET (all logic in sysclk domain) -# 50:63 , 0x0000 ; # reserved -} - -# --------------------------------------------------------------------------------------- -# ADR PLL VREG Config0 default=0 !! register definition for TUNEF not correct for '111b'? -# -# 48:50 PLL_TUNE (000=66.6uA, 111=20uA), -# 51:53 PLL_TUNECP (000=gain 1, 111=gain 8) -# 54:59 PLL_TUNEF, RC for 2nd order filter -# 60:61 PLL_TUNEVCO -# 62:63 PLL_PLLXTR, extra bits for later expansion -# -# DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0 0x030 0x800080300301143f -# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.CONTROL.TWRAP.P_REG_30_L2 -#scom 0x8000(80,84)300301143F { # PHY01 Port0 ADR32S[0:1] -scom 0x800(0,1)BC300301143F { # PHY01 Port[0:1] broadcast ADR32S[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# # 0b110 100 101011 00 00 22.22uA, gain 5, SE(3pF, 24pF, 800 ohms), VCO=low, PLLXTR -# 48:59 , 0xD2B , (def_is_sim) ; # same as DD0 - -# # 0b111 000 111011 00 00 20uA, gain 1, SE(3pF, 24pF, 200 ohms), VCO=low -# 48:63 , 0xE3B0 , ((CEN.ATTR_MSS_FREQ/2) < 600) ; # 300-599.9 MHz, < 1200 MT/s - -# # 0b010 000 111000 00 00 40uA, gain 1, SE(2pF, 16pF, 200 ohms), VCO=low -# 48:63 , 0x4380 , ((CEN.ATTR_MSS_FREQ/2) < 1000) ; # 600-999.9 MHz, 1200-2000 MT/s - -# # 0b100 011 111011 01 00 28.57uA, gain 4, SE(3pF, 24pF, 200 ohms), VCO=high -# 48:63 , 0x8FB4 , ((CEN.ATTR_MSS_FREQ/2) >= 1000) ; # 1000-1066 MHz, >=2000 MT/s - -# new setting from Joe Iadanza 11/30 -# # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) -# Changed cap from 2.5pF to 1pF, per SteveW. - 48:59 , 0x689 , (CEN.ATTR_MSS_FREQ < 1200) ; # < 600 MHz, 1200 MT/s - -# # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) - 48:59 , 0x689 , (CEN.ATTR_MSS_FREQ < 1460) ; # < 730 MHz, < 1460 MT/s - -# # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) - 48:59 , 0x689 , (CEN.ATTR_MSS_FREQ > 1459) ; # >= 730 MHz, >=1460 MT/s - -# 60:63 , 0x4 , (def_is_ddr4) ; # VCO = high for DDR4 -# 60:63 , 0x0 , any ; # VCO = low for DDR3 -# changed from Qual FA32002 and SWyatt re-review... - 60:63 , 0x0 , (CEN.ATTR_MSS_FREQ > 1400) ; # Note, no longer valid --> "VCO = high for >= 700MHz or 1400 MT/s" - 60:63 , 0x0 , any ; # VCO = low for < 700MHz -} - -# --------------------------------------------------------------------------------------- -# ADR PLL VREG Config1 default=0 !! doc on section has some inconsistencies -# -# CEN.ATTR_MSS_VOLT [0:1] [0:1] -# DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0 0x031 0x800080310301143f -# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.CONTROL.TWRAP.P_REG_31_L2 -#scom 0x8000(80,84)310301143f { # PHY01 Port0 ADR32S[0:1] -scom 0x800(0,1)BC310301143f { # PHY01 Port[0:1] broadcast ADR32S[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # PLL_TUNETDIV(0:2) PLLTESTOUT (000=logic 1, 001=MDIVOUT div by 64, 01x=MDIVOUT div by 1, 1xx=dsabled, logic 0) -# 48:50 , 0b100 , (def_is_sim) ; # disabled, for SIM - 48:50 , 0b111 , any ; # disabled, was '100' - - # PLL_TUNEMDIV(0:1) Feedback divider (00=1, 01=2, 1x=reserved), "must be set to this value(00)" - 51:52 , 0b00 , any ; # same as DD0 -# 51:52 , 0b00 , ((CEN.ATTR_MSS_FREQ/2) < 800) ; # < 1600 MT/s -# 51:52 , 0b01 , ((CEN.ATTR_MSS_FREQ/2) >= 800) ; # >=1600 MT/s - - # PLL_TUNEATST (0=HiZ, 1=CMFB internal) - HiZ, "for all frequencies 0 is required" - 53 , 0b0 , any ; # HiZ - - # VREG_RANGE(0:1) (00=1.50V, 01=1.35V, 11=1.20V) -# 54:55 , 0b01 , (def_is_sim) ; # set to 1.35 for SIM - 54:55 , 0b11 , (CEN.ATTR_MSS_VOLT <= 1271) ; # set to 1.2V - 54:55 , 0b00 , any ; # set to 1.35V & 1.5V - - # VREG_VREGSPARE, Extra pins for later expansion. should be put to 0 - 56 , 0b0 , any ; - - # VREG_VCCTUNE(0:1) (00=850mV, 01=855mV, 10=860mV, 11=865mV) - 57:58 , 0b10 , any ; # standard operating point - - # INTERP_SIG_SLEW(0:3), Interpolated Signal Slew (PRSTCH pins on ADR16) clk freq -# 59:62 , 0b1010 , (def_is_sim) ; # for SIM -# new setting from Joe Iadanza 11/30 - 59:62 , 0b1000 , (CEN.ATTR_MSS_FREQ <= 1200) ; # -1066 - 59:62 , 0b0100 , ((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 - 59:62 , 0b0010 , ((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 - 59:62 , 0b1100 , (CEN.ATTR_MSS_FREQ > 1732) ; # 1866+ - -# 59:62 , 0b1001 , (CEN.ATTR_MSS_FREQ > 2260) ; # 2400 -# 59:62 , 0b1001 , ((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260)) ; # 2133 -# 59:62 , 0b0110 , ((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993)) ; # 1866 -# 59:62 , 0b1010 , ((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 -# 59:62 , 0b0010 , ((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 -# 59:62 , 0b1100 , ((CEN.ATTR_MSS_FREQ > 1013) && (CEN.ATTR_MSS_FREQ <= 1200)) ; # 1066 -# 59:62 , 0b0100 , ((CEN.ATTR_MSS_FREQ > 933) && (CEN.ATTR_MSS_FREQ <= 1113)) ; # 800 -# 59:62 , 0b1000 , (CEN.ATTR_MSS_FREQ <= 933) ; # 666 - - # ANALOG_WRAPON, Wrap Data control to attached ADR16(s)/ADR12(s) - 63 , 0b0 , any ; -} - -# --------------------------------------------------------------------------------------- -# DP18 PLL Config0 default=0 -# -# Needed? [0:1][0:1][0:4] -# DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_0 0x076 0x800000760301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_PLL_CONFIG0_L2 -# scom 0x8000(00,04,08,0C,10)760301143f { # CONFIG0_P0_[0:4] -scom 0x800(0,1)3C760301143F { # CONFIG0_P[0:1] broadcast [0:4] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# # 0b111 000 111011 00 00 20uA, gain 1, SE(200 ohms, 24pF, 3pF), VCO=low -# # 300-599.9 MHz, < 1200 MT/s -# 48:59 , 0xE3B , ((def_is_sim) && (CEN.ATTR_MSS_FREQ < 1200)) ; -# -# # 0b010 000 111000 00 00 40uA, gain 1, SE(200 ohms, 16pF, 2pF), VCO=low -# # 600-999.9 MHz, 1200-2000 MT/s -# 48:59 , 0x438 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ < 2000)) ; -# -# # 0b100 011 111011 01 00 28.57uA, gain 4, SE(200 ohms, 24pF, 3pF), VCO=high -# # 1000-1066 MHz, >=2000 MT/s -# 48:59 , 0x8FB , ((def_is_sim) && (CEN.ATTR_MSS_FREQ >= 2000)) ; - -# new setting from Joe Iadanza 11/30 -# # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) -# Changed cap from 2.5pF to 1pF, per SteveW. - 48:59 , 0x689 , (CEN.ATTR_MSS_FREQ < 1200) ; # < 600 MHz, 1200 MT/s - -# # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) - 48:59 , 0x689 , (CEN.ATTR_MSS_FREQ < 1460) ; # < 730 MHz, < 1460 MT/s - -# # 0b011 010 101 00 1 33.33uA, gain 3, SE(400 ohms, 16pF, 3pF) - 48:59 , 0x689 , (CEN.ATTR_MSS_FREQ > 1459) ; # >= 730 MHz, >=1460 MT/s - -# 60:63 , 0x0 , (def_is_sim) ; # for SIM -# changed from Qual FA32002 and SWyatt re-review... - 60:63 , 0x0 , (CEN.ATTR_MSS_FREQ > 1400) ; # VCO = high for >= 700MHz or 1400 MT/s - 60:63 , 0x0 , any ; # VCO = low for < 700MHz -} - -# --------------------------------------------------------------------------------------- -# DP18 PLL Config1 default=0 -# -# DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_0 0x077 0x800000770301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_PLL_CONFIG1_L2 -# scom 0x8000(00,04,08,0C,10)770301143f { # CONFIG1_P0_[0:4] -scom 0x800(0,1)3C770301143F { # CONFIG1_P[0:1] broadcast [0:4] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # PLL_TUNETDIV(0:2) PLLTESTOUT (all freq 1xx required) -# 48:50 , 0b100 , (def_is_sim) ; # disabled - 48:50 , 0b111 , any ; # disabled - - # PLL_TUNEMDIV(0:1) Feedback divider (00=1, 01=2, 1x=reserved), "must be set to this value" -# 51:52 , 0b01 , (def_is_sim) ; # 2 - 51:52 , 0b00 , any ; # 1 - - # PLL_TUNEATST (0=HiZ, 1=CMFB internal) - HiZ, "for all frequencies 0 is required" - 53 , 0b0 , any ; # HiZ - - # VREG_RANGE(0:1) (00=1.50V, 01=1.35V, 11=1.20V) - # !! Need to change if using 1.25V since overlap occurs! -# 54:55 , 0b01 , (def_is_sim) ; # set to 1.35V for sim - 54:55 , 0b11 , (CEN.ATTR_MSS_VOLT <= 1271) ; # set to 1.2V - 54:55 , 0b00 , any ; # set to 1.35V, & 1.5V - - # CE0DLTVCCA - 56 , 0b0 , any ; # must be 0 - - # VREG_VCCTUNE(0:1) (00=850mV, 01=855mV, 10=860mV, 11=865mV) - 57:58 , 0b10 , any ; # standard = 860 - - 59 , 0b0 , any ; # CE0DLTVCCD1, must be 0 - 60 , 0b0 , any ; # CE0DLTVCCD2, must be 0 - 61 , 0b0 , any ; # S0INSDLYTAP, must be 0 - 62 , 0b0 , any ; # S1INSDLYTAP, must be 0 -# 63 , 0b0 , any ; # reserved -} - -# freq ranges -# Low -5% Nom +5% High -# 0 633 666 700 730 # not used -# 731 760 800 840 933 # not used -# ------------------------------- -# 933 1013 1066 1120 1200 -# 1201 1266 1333 1400 1460 -# 1461 1520 1600 1680 1732 -# 1733 1773 1866 1960 1993 -# 1994 2026 2133 2240 2260 -# 2261 2280 2400 2520 ++++ -# freq ranges -# Low -5% Nom +5% High -# 933 1013 1066 1120 1199 -# 1200 1266 1333 1400 1459 -# 1460 1520 1600 1680 1731 -# 1732 1773 1866 1960 1992 -# 1993 2026 2133 2240 2259 -# 2260 2280 2400 2520 ++++ - -# --------------------------------------------------------------------------------------- -# DQ_DQS Slew rate setting -# -# CEN.ATTR_MSS_FREQ -# ATTR_EFF_CEN_SLEW_RATE_DQ_DQS [0:15] 0=slow, 15=fast -# -# FFE=feed forward equalization, DFE=decision feedback equalization -# -# [01:23] [0:1][0:4] -# DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0 0x075 0x800000750301143f -# PHYW.PHYX.GEN_DP#1.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_IO_TX_CONFIG0_L2 -#scom 0x8000(00,04,08,0C,10)750301143F { # CONFIG0_P0_[0:4] -scom 0x80003C750301143F { # CONFIG0_P0 broadcast [0:4] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # INTERP_SIG_SLEW for phase rotator -# 48:51 , 0b1100 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ <= 1200)) ; # 1066 -# 48:51 , 0b0010 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 -# 48:51 , 0b1010 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 -# 48:51 , 0b0110 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993)) ; # 1866 -# 48:51 , 0b1001 , ((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260)) ; # 2133 -# 48:51 , 0b1001 , (CEN.ATTR_MSS_FREQ > 2260) ; # 2400 - -# new setting from Joe Iadanza 11/30 - 48:51 , 0b1000 , (CEN.ATTR_MSS_FREQ <= 1200) ; # 1066 - 48:51 , 0b0100 , ((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 - 48:51 , 0b0010 , ((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 - 48:51 , 0b1100 , ((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993)) ; # 1866 - - # Post Cursor, tap coefficient for FFE, 0=no equalization - 52:55 , 0b0001 , (def_ffe1_p0) ; # enable 1 FFE slice - 52:55 , 0b0011 , (def_ffe2_p0) ; # enable 2 FFE slices - 52:55 , 0b0111 , (def_ffe3_p0) ; # enable 3 FFE slices - 52:55 , 0b1111 , (def_ffe4_p0) ; # enable 4 FFE slices - 52:55 , 0b0000 , any ; # enable 0 FFE slices - - # Slew rate set in ddrphy_reset procedure via slew FN call -# 56:59 , 0b0000 , (ATTR_EFF_CEN_SLEW_RATE_DQ_DQS == 0) ; # SLEW_CTL, slowest -# 60:63 , 0b0000 , any ; # reserved -} - -# DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0 0x075 0x800100750301143f -scom 0x80013C750301143F { # CONFIG0_P1 broadcast [0:4] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # INTERP_SIG_SLEW for phase rotator -# 48:51 , 0b1100 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ <= 1200)) ; # 1066 -# 48:51 , 0b0010 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 -# 48:51 , 0b1010 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 -# 48:51 , 0b0110 , ((def_is_sim) && (CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993)) ; # 1866 -# 48:51 , 0b1001 , ((CEN.ATTR_MSS_FREQ > 1993) && (CEN.ATTR_MSS_FREQ <= 2260)) ; # 2133 -# 48:51 , 0b1001 , (CEN.ATTR_MSS_FREQ > 2260) ; # 2400 - -# new setting from Joe Iadanza 11/30 - 48:51 , 0b1000 , (CEN.ATTR_MSS_FREQ <= 1200) ; # 1066 - 48:51 , 0b0100 , ((CEN.ATTR_MSS_FREQ > 1200) && (CEN.ATTR_MSS_FREQ <= 1460)) ; # 1333 - 48:51 , 0b0010 , ((CEN.ATTR_MSS_FREQ > 1460) && (CEN.ATTR_MSS_FREQ <= 1732)) ; # 1600 - 48:51 , 0b1100 , ((CEN.ATTR_MSS_FREQ > 1732) && (CEN.ATTR_MSS_FREQ <= 1993)) ; # 1866 - - # Post Cursor, tap coefficient for FFE, 0=no equalization - 52:55 , 0b0001 , (def_ffe1_p1) ; # enable 1 FFE slice - 52:55 , 0b0011 , (def_ffe2_p1) ; # enable 2 FFE slices - 52:55 , 0b0111 , (def_ffe3_p1) ; # enable 3 FFE slices - 52:55 , 0b1111 , (def_ffe4_p1) ; # enable 4 FFE slices - 52:55 , 0b0000 , any ; # enable 0 FFE slices - # Slew rate set in ddrphy_reset procedure via slew FN call -# 56:59 , 0b0000 , any ; -# 60:63 , 0b0000 , any ; # reserved -} - -# --------------------------------------------------------------------------------------- -# Input Termination impedance # pg 415 Cen_WB_1.13 -# -# ATTR_EFF_CEN_RCV_IMP_DQ_DQS 15,20,30,40,48,60,120 -# -# !! settings currently for 30, 40, 60, 80, 120, 160, 240 -# missing 15, 20, 48, added 160, 240 -# -# 48:55 = N/P FET slices (0-7), 56:59 = N/P FET FFE slices (0-4) -# 2 slices of 480 (FFE) = 1 slice of 240 (non-FFE) -# -# for DDR4 where VDDR (POD=Pseudo Open Drain) -# DDR4 ohms = 1 / ((1 / (total 240 slices / 240)) + (1 / (total 480 slices / 480))) -# -# for DDR3 VDDR/2 -# DDR3 ohms = (1 / ((1 / (total 240 slices / 240)) + (1 / (total 480 slices / 480)))) / 2 -# -# [01:23] [N:P] [0:1][0:4] -# DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0 0x07A 0x8000007a0301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_IO_TX_NFET_TERM_L2(0:11) -#scom 0x8000(00,04,08,0C,10)7A0301143f { # NFET_TERM_P0_[0:4] broadcast -scom 0x80003C7A0301143f { # NFET_TERM_P0_[0:4] broadcast - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # for DDR3 = 1 ohms # ohm/slices -# Joe Iadanza's spreadsheet (from Saravanan note 3/28/12 11:20A) has this... - 48:59 , 0xFF0 , ((def_is_ddr3) && (def_cri_dqs_ohm15_p0)) ; # 240/8, 480/0 - 48:59 , 0x7E0 , ((def_is_ddr3) && (def_cri_dqs_ohm20_p0)) ; # 240/6, 480/0 - 48:59 , 0x3C0 , ((def_is_ddr3) && (def_cri_dqs_ohm30_p0)) ; # 240/4, 480/0 -# 48:59 , 0x382 , ((def_is_ddr3) && (def_cri_dqs_ohm34_p0)) ; # 240/3, 480/1 - 48:59 , 0x186 , ((def_is_ddr3) && (def_cri_dqs_ohm40_p0)) ; # 240/2, 480/2 - 48:59 , 0x182 , ((def_is_ddr3) && (def_cri_dqs_ohm48_p0)) ; # 240/2, 480/1 - 48:59 , 0x180 , ((def_is_ddr3) && (def_cri_dqs_ohm60_p0)) ; # 240/2, 480/0 - 48:59 , 0x102 , ((def_is_ddr3) && (def_cri_dqs_ohm80_p0)) ; # 240/1, 480/1 - 48:59 , 0x100 , ((def_is_ddr3) && (def_cri_dqs_ohm120_p0)) ; # 240/1, 480/0 - 48:59 , 0x007 , ((def_is_ddr3) && (def_cri_dqs_ohm160_p0)) ; # 240/0, 480/3 - 48:59 , 0x003 , ((def_is_ddr3) && (def_cri_dqs_ohm240_p0)) ; # 240/0, 480/2 - 48:59 , 0x000 , any ; # 240/0, 480/0 -# 60:63 , 0b0000 , any ; # reserved -} -# DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0 0x07B 0x8000007B0301143f -#scom 0x8000(00,04,08,0C,10)7B0301143f { # PFET_TERM_P0_[0:4] -scom 0x80003C7B0301143f { # PFET_TERM_P0_[0:4] broadcast - bits , scom_data, expr ; -# 0:47 , 0x000000000000, any ; # reserved - # for DDR3 = 1 ohms # ohm/slices - 48:59 , 0xFF0 , ((def_is_ddr3) && (def_cri_dqs_ohm15_p0)) ; # 240/8, 480/0 - 48:59 , 0x7E0 , ((def_is_ddr3) && (def_cri_dqs_ohm20_p0)) ; # 240/6, 480/0 - 48:59 , 0x3C0 , ((def_is_ddr3) && (def_cri_dqs_ohm30_p0)) ; # 240/4, 480/0 - # 48:59 , 0x382 , ((def_is_ddr3) && (def_cri_dqs_ohm34_p0)) ; # 240/3, 480/1 - 48:59 , 0x186 , ((def_is_ddr3) && (def_cri_dqs_ohm40_p0)) ; # 240/2, 480/2 - 48:59 , 0x182 , ((def_is_ddr3) && (def_cri_dqs_ohm48_p0)) ; # 240/2, 480/1 - 48:59 , 0x180 , ((def_is_ddr3) && (def_cri_dqs_ohm60_p0)) ; # 240/2, 480/0 - 48:59 , 0x102 , ((def_is_ddr3) && (def_cri_dqs_ohm80_p0)) ; # 240/1, 480/1 - 48:59 , 0x100 , ((def_is_ddr3) && (def_cri_dqs_ohm120_p0)) ; # 240/1, 480/0 - 48:59 , 0x007 , ((def_is_ddr3) && (def_cri_dqs_ohm160_p0)) ; # 240/0, 480/3 - 48:59 , 0x003 , ((def_is_ddr3) && (def_cri_dqs_ohm240_p0)) ; # 240/0, 480/2 - # for DDR4 = 2 - # 48:59 , 0x7E6 , ((def_is_ddr4) && (def_cri_dqs_ohm34_p0)) ; # 240/8, 480/2 - 48:59 , 0x7E0 , ((def_is_ddr4) && (def_cri_dqs_ohm40_p0)) ; # 240/8, 480/0 - 48:59 , 0x3C6 , ((def_is_ddr4) && (def_cri_dqs_ohm48_p0)) ; # 240/4, 480/2 - 48:59 , 0x3C0 , ((def_is_ddr4) && (def_cri_dqs_ohm60_p0)) ; # 240/4, 480/0 - 48:59 , 0x186 , ((def_is_ddr4) && (def_cri_dqs_ohm80_p0)) ; # 240/2, 480/2 - 48:59 , 0x180 , ((def_is_ddr4) && (def_cri_dqs_ohm120_p0)) ; # 240/2, 480/0 -# 48:59 , 0x--- , ((def_is_ddr4) && (def_cri_dqs_ohm160_p0)) ; # 240/?, 480/? - 48:59 , 0x100 , ((def_is_ddr4) && (def_cri_dqs_ohm240_p0)) ; # 240/1, 480/0 -# 48:59 , 0x002 , ((def_is_ddr4) && (def_cri_dqs_ohm480_p0)) ; # 240/0, 480/1 - 48:59 , 0x000 , any ; # 240/0, 480/0 -# 60:63 , 0b0000 , any ; # reserved -} - -# DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0 0x07A 0x8001007a0301143f -#scom 0x8001(00,04,08,0C,10)7A0301143f { # NFET_TERM_P1_[0:4] broadcast -scom 0x80013C7A0301143f { # NFET_TERM_P1_[0:4] broadcast - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # for DDR3 = 1 ohms # ohm/slices - 48:59 , 0xFF0 , ((def_is_ddr3) && (def_cri_dqs_ohm15_p1)) ; # 240/8, 480/0 - 48:59 , 0x7E0 , ((def_is_ddr3) && (def_cri_dqs_ohm20_p1)) ; # 240/6, 480/0 - 48:59 , 0x3C0 , ((def_is_ddr3) && (def_cri_dqs_ohm30_p1)) ; # 240/4, 480/0 -# 48:59 , 0x382 , ((def_is_ddr3) && (def_cri_dqs_ohm34_p1)) ; # 240/3, 480/1 - 48:59 , 0x186 , ((def_is_ddr3) && (def_cri_dqs_ohm40_p1)) ; # 240/2, 480/2 - 48:59 , 0x182 , ((def_is_ddr3) && (def_cri_dqs_ohm48_p1)) ; # 240/2, 480/1 - 48:59 , 0x180 , ((def_is_ddr3) && (def_cri_dqs_ohm60_p1)) ; # 240/2, 480/0 - 48:59 , 0x102 , ((def_is_ddr3) && (def_cri_dqs_ohm80_p1)) ; # 240/1, 480/1 - 48:59 , 0x100 , ((def_is_ddr3) && (def_cri_dqs_ohm120_p1)) ; # 240/1, 480/0 - 48:59 , 0x007 , ((def_is_ddr3) && (def_cri_dqs_ohm160_p1)) ; # 240/0, 480/3 - 48:59 , 0x003 , ((def_is_ddr3) && (def_cri_dqs_ohm240_p1)) ; # 240/0, 480/2 - 48:59 , 0x000 , any ; # 240/0, 480/0 -# 60:63 , 0b0000 , any ; # reserved -} -# DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0 0x07B 0x8001007B0301143f -#scom 0x8001(00,04,08,0C,10)7B0301143f { # PFET_TERM_P1_[0:4] -scom 0x80013C7B0301143f { # PFET_TERM_P1_[0:4] broadcast - bits , scom_data, expr ; -# 0:47 , 0x000000000000, any ; # reserved - # for DDR3 = 1 ohms # ohm/slices - 48:59 , 0xFF0 , ((def_is_ddr3) && (def_cri_dqs_ohm15_p1)) ; # 240/8, 480/0 - 48:59 , 0x7E0 , ((def_is_ddr3) && (def_cri_dqs_ohm20_p1)) ; # 240/6, 480/0 - 48:59 , 0x3C0 , ((def_is_ddr3) && (def_cri_dqs_ohm30_p1)) ; # 240/4, 480/0 -# 48:59 , 0x382 , ((def_is_ddr3) && (def_cri_dqs_ohm34_p1)) ; # 240/3, 480/1 - 48:59 , 0x186 , ((def_is_ddr3) && (def_cri_dqs_ohm40_p1)) ; # 240/2, 480/2 - 48:59 , 0x182 , ((def_is_ddr3) && (def_cri_dqs_ohm48_p1)) ; # 240/2, 480/1 - 48:59 , 0x180 , ((def_is_ddr3) && (def_cri_dqs_ohm60_p1)) ; # 240/2, 480/0 - 48:59 , 0x102 , ((def_is_ddr3) && (def_cri_dqs_ohm80_p1)) ; # 240/1, 480/1 - 48:59 , 0x100 , ((def_is_ddr3) && (def_cri_dqs_ohm120_p1)) ; # 240/1, 480/0 - 48:59 , 0x007 , ((def_is_ddr3) && (def_cri_dqs_ohm160_p1)) ; # 240/0, 480/3 - 48:59 , 0x003 , ((def_is_ddr3) && (def_cri_dqs_ohm240_p1)) ; # 240/0, 480/2 - # for DDR4 = 2 -# 48:59 , 0x7E6 , ((def_is_ddr4) && (def_cri_dqs_ohm34_p1)) ; # 240/8, 480/2 - 48:59 , 0x7E0 , ((def_is_ddr4) && (def_cri_dqs_ohm40_p1)) ; # 240/8, 480/0 - 48:59 , 0x3C6 , ((def_is_ddr4) && (def_cri_dqs_ohm48_p1)) ; # 240/4, 480/2 - 48:59 , 0x3C0 , ((def_is_ddr4) && (def_cri_dqs_ohm60_p1)) ; # 240/4, 480/0 - 48:59 , 0x186 , ((def_is_ddr4) && (def_cri_dqs_ohm80_p1)) ; # 240/2, 480/2 - 48:59 , 0x180 , ((def_is_ddr4) && (def_cri_dqs_ohm120_p1)) ; # 240/2, 480/0 -# 48:59 , 0x--- , ((def_is_ddr4) && (def_cri_dqs_ohm160_p1)) ; # 240/?, 480/? - 48:59 , 0x100 , ((def_is_ddr4) && (def_cri_dqs_ohm240_p1)) ; # 240/1, 480/0 -# 48:59 , 0x002 , ((def_is_ddr4) && (def_cri_dqs_ohm480_p1)) ; # 240/0, 480/1 - 48:59 , 0x000 , any ; # 240/0, 480/0 -# 60:63 , 0b0000 , any ; # reserved -} -# --------------------------------------------------------------------------------------- -# Output(DQ/DQS) driver impedance settings -# -# ATTR_EFF_CEN_DRV_IMP_DQ_DQS 24, 30, 34, 40 + FFE differences... -# -# [01:23] [N:P] [0:1][0:4] -# DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0 0x078 0x800000780301143f -# DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0 0x079 0x800000790301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_IO_TX_NFET_SLICE_L2(0:11) -# (00,04,08,0C,10) -#scom 0x80003C780301143f { # NFET_SLICE_P0_[0:4] broadcast -scom 0x80003C7(8,9)0301143F { # [N:P]FET_SLICE_P0_[0:4] broadcast - bits , scom_data , expr ; # ohm/slices -# 0:47 , 0x000000000000, any ; # reserved - 48:59 , 0xFFF , (def_cdi_dqs_ohm24_p0) ; # 240/8, 480/4 - 48:59 , 0x7EF , (def_cdi_dqs_ohm30_p0) ; # 240/6, 480/4 - 48:59 , 0x3EF , (def_cdi_dqs_ohm34_p0) ; # 240/5, 480/4 - 48:59 , 0x3CF , (def_cdi_dqs_ohm40_p0) ; # 240/4, 480/4 - 48:59 , 0x000 , any ; # 240/0, 480/0 -# 60:63 , 0b0000 , any ; # reserved -} - -# DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0 0x078 0x800100780301143f -# DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_0 0x079 0x800100790301143f -scom 0x80013C7(8,9)0301143F { # [N:P]FET_SLICE_P1_[0:4] broadcast - bits , scom_data , expr ; # ohm/slices -# 0:47 , 0x000000000000, any ; # reserved - 48:59 , 0xFFF , (def_cdi_dqs_ohm24_p1) ; # 240/8, 480/4 - 48:59 , 0x7EF , (def_cdi_dqs_ohm30_p1) ; # 240/6, 480/4 - 48:59 , 0x3EF , (def_cdi_dqs_ohm34_p1) ; # 240/5, 480/4 - 48:59 , 0x3CF , (def_cdi_dqs_ohm40_p1) ; # 240/4, 480/4 - 48:59 , 0x000 , any ; # 240/0, 480/0 -# 60:63 , 0b0000 , any ; # reserved -} - -#********************************************************************************** -#!! DO NOT NEED to set for Centaur from Joe Iadanza. -# -# page 414 Centaur_WB_1.13.pdf -# -#!PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.CONTROL.TWRAP.REG_A_10_L2(0:15) -#!selects which values in one of these four registers are sent to each ADR output pin. -#! -#! [01:23] [P:N] [0:3][0:1][0:3] -#!DPHY01_DDRPHY_ADR_IO_NFET_SLICE_EN0_P0_ADR0 0x800040100301143f -#!DDRPHY_ADR_IO_NFET_SLICE_EN0_P0_ADR1 0x800044100301143f -#!DDRPHY_ADR_IO_NFET_SLICE_EN0_P0_ADR2 0x800048100301143f -#!DDRPHY_ADR_IO_NFET_SLICE_EN0_P0_ADR3 0x80004C100301143f -#! -#!DPHY01_DDRPHY_ADR_IO_PFET_SLICE_EN0_P0_ADR0 -#!DDRPHY_ADR_IO_PFET_SLICE_EN0 0x014 0x800040140301143f -#! -#! --------------------------------------------------------------------------------------- -#! --- PHY01 ADR IO NFET SLICE EN[0:3] P[0:1] ADR[0:3] --------------------------- -#! --------------------------------------------------------------------------------------- -#!DPHY01.DDRPHY_ADR_IO_NFET_SLICE_EN0_P0_ADR0 -#!scom 0x800(0,1)(40,44,48,4C)100301143F { -#!scom 0x800(0,1)(40,44,48,4C)(10,11,12,13)0301143F { # EN[0:3]_P[0:1]_ADR[0:3] -#!scom 0x800(0,1)7C(10,11,12,13)0301143F { # EN[0:3]_P[0:1]_ADR[0:3] via broadcast -#! bits , scom_data ; -## 0:47 , 0x000000000000 ; # reserved -#! 48:63 , 0b1111111111110000 ; -#!} -#! -#! --------------------------------------------------------------------------------------- -#! --- PHY01 ADR IO PFET SLICE EN[0:3] P[0:1] ADR[0:3] --------------------------- -#! --------------------------------------------------------------------------------------- -#!DPHY01.DDRPHY_ADR_IO_PFET_SLICE_EN0_P0_ADR0 -#!scom 0x800(0,1)(40,44,48,4C)140301143F { -#!scom 0x800(0,1)(40,44,48,4C)(14,15,16,17)0301143F { # EN[0:3]_P[0:1]_ADR[0:3] -#!scom 0x800(0,1)7C(14,15,16,17)0301143F { # EN[0:3]_P[0:1]_ADR[0:3] via broadcast -#! bits , scom_data ; -## 0:47 , 0x000000000000 ; # reserved -#! 48:63 , 0b1111111111110000 ; -#!} -#********************************************************************************** - -# --------------------------------------------------------------------------------------- -# Output Command / Control Impedance settings -# -# ADR I/O FET Slice Enable Map 0 -# Register 0(MAP0) contains lanes 0:7, Register 1(MAP1) contains lanes 8:13 -# CMD = address lines, ba, parity, ras, cas, we, act(DDR4) -# CNTL = cke, clk, cs, odt -# -# ATTR_EFF_CEN_DRV_IMP_CMD 15,20,30,40 -# ATTR_VPD_CEN_DRV_IMP_CNTL 15,20,30,40 -# -# SEL# impedance -# 00b = 15 ohm, -# 01b = 20 ohm, -# 10b = 30 ohm, -# 11b = 40 ohm -# -# --------------------------------------------------------------------------------- -# ----------------- Port 0 ADR 0 -------------------------- !! board wiring dependent !! -# --------------------------------------------------------------------------------- -# [01:23] [0:1][0:1][0:3] -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR0 0x020 0x800040200301143f -# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.CONTROL.TWRAP.REG_A_20_L2(0:15) -scom 0x800040200301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 0 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 0, A1_CKE1 - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 1, A0_CS3n - 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 2, A1_CKE0 - 52:53 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 3, A0_ODT0 - 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 4, A_A15 - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 5, A_PAR - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 60:61 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 6, A0_CKE1 - 60:61 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 60:61 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 60:61 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 7, A0_CS1n - 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; -# ------ PORT 2 ADR 0 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 0, C0_CS0n - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 1, C_A3 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 2, C1_CS3n - 52:53 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 3, C_RASn - 54:55 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 4, C_A12 - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 5, C_A7 - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 60:61 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 6, C0_CLK1_p - 60:61 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; - 60:61 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; - 60:61 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; - 62:63 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 7, C0_CLK1_n - 62:63 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; - 62:63 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; - 62:63 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; -# 48:63 , 0x0000 , any ; # SEL0-7 -} -# ADR I/O FET Slice Enable Map 1, register 1 containing lanes 8:15 -# [01:23] [0:1][0:1][0:3] -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR0 -scom 0x800040210301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 0 lanes 8:11 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 8, A0_CKE0 - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 9, A1_ODT0 - 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 10, A0_CLK0_p - 52:53 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 11, A0_CLK0_n - 54:55 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; -# ------ PORT 2 ADR 0 lanes 8:11 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 8, C1_CLK1_p - 48:49 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 9, C1_CLK1_n - 50:51 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba23)); # 10, C1_CKE2 - 52:53 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba23)); - 52:53 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba23)); - 52:53 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba23)); - 54:55 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba23)); # 11, C0_CKE2 - 54:55 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba23)); - 54:55 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba23)); - 54:55 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba23)); -# 56:63 , 0x00 , any ; # reserved -} -# ----------------- Port 0 ADR 1 ----------------------------------------------- -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR1 -scom 0x800044200301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 1 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 0, A0_CS0n - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba01)); # 1, A1_CKE3 - 50:51 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba01)); - 50:51 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba01)); - 50:51 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba01)); - 52:53 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 2, A1_ODT1 - 52:53 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 3, A_A2 - 54:55 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 4, A_A6 - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 5, A_A1 - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 60:61 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 6, A_A14 - 60:61 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 60:61 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 60:61 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 62:63 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba01)); # 7, A0_CKE2 - 62:63 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba01)); - 62:63 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba01)); - 62:63 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba01)); -# ------ PORT 2 ADR 1 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 0, C_BA2 - 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 1, C1_CKE1 - 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 2, C0_ODT1 - 52:53 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 3, C_WEn - 54:55 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 4, C0_CS1n - 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 5, C_A11 - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 60:61 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba23)); # 6, C0_CKE3 - 60:61 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba23)); - 60:61 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba23)); - 60:61 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba23)); - 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 7, C0_CS2n - 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; -} -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR1 -scom 0x800044210301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 1 lanes 8:11 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 8, A1_CS2n - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba01)); # 9, A1_CKE2 - 50:51 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba01)); - 50:51 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba01)); - 50:51 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba01)); - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 10, A_A4 - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 11, A_RASn - 54:55 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; -# ------ PORT 2 ADR 1 lanes 8:11 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 8, C0_ODT0 - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 9, C_A8 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 10, C_A5 - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 11, C1_CS0n - 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; -# 56:63 , 0x00 , any ; # reserved -} -# ----------------- Port 0 ADR 2 ----------------------------------------------- -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR2 -scom 0x800048200301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 2 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 0, A_A12 - 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 1, A_A0 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba01)); # 2, A0_CKE3 - 52:53 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba01)); - 52:53 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba01)); - 52:53 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba01)); - 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 3, A1_CS3n - 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 56:57 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 4, A1_CLK0_p - 56:57 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; - 56:57 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; - 56:57 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; - 58:59 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 5, A1_CLK0_n - 58:59 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; - 58:59 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; - 58:59 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; - 60:61 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 6, A0_ODT1 - 60:61 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 60:61 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 60:61 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 7, A1_CS0n - 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; -# ------ PORT 2 ADR 2 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 0, C_A1 - 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 1, C_A6 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 2, C_A13 - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 3, C0_CKE0 - 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; - 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 4, C1_ODT0 - 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; - 58:59 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 5, C1_CS1n - 58:59 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 58:59 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 58:59 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; - 60:61 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 6, C0_CKE1 - 60:61 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 60:61 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 60:61 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; - 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 7, C1_CKE0 - 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; -} -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR2 -scom 0x800048210301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 2 lanes 8:13 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 8, A1_CS1n - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 9, A_A10 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 10, A0_CLK1_n - 52:53 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 11, A0_CLK1_p - 54:55 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; - 56:57 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 12, A1_CLK1_n - 56:57 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; - 56:57 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; - 56:57 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; - 58:59 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba01)) ; # 13, A1_CLK1_p - 58:59 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba01)) ; - 58:59 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba01)) ; - 58:59 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba01)) ; -# ------ PORT 2 ADR 2 lanes 8:13 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 8, C_A0 - 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 9, C_BA1 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 10, C0_CLK0_n - 52:53 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 11, C0_CLK0_p - 54:55 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; - 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 12, C1_CS2n - 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 13, C_A10 - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; -# 60:63 , 0b0000 , any ; # reserved -} -# ----------------- Port 0 ADR 3 ----------------------------------------------- -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P0_ADR3 -scom 0x80004c200301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 3 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 0, A_A13 - 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 1, A_BA0 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 2, A_WEn - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba01)) ; # 3, A0_CS2n - 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba01)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 4, A_BA1 - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 5, A_CASn - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 60:61 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 6, A_A5 - 60:61 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 60:61 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 60:61 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 62:63 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 7, A_A3 - 62:63 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 62:63 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 62:63 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; -# ------ PORT 2 ADR 3 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 0, C_PAR - 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 1, C1_ODT1 - 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 2, C1_CLK0_p - 52:53 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_clk_ohm15_p0) && (def_is_mba23)) ; # 3, C1_CLK0_n - 54:55 , 0b01 , ((def_cdi_clk_ohm20_p0) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_clk_ohm30_p0) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_clk_ohm40_p0) && (def_is_mba23)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 4, C_A14 - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 5, C_A9 - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 60:61 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 6, C_ACTn - 60:61 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 60:61 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 60:61 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 62:63 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 7, C_A2 - 62:63 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 62:63 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 62:63 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; -} -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P0_ADR3 -scom 0x80004c210301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 3 lanes 8:13 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 8, A_BA2 - 48:49 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 9, A_A11 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 10, A_A7 - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 11, A_ACTn - 54:55 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 12, A_A9 - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba01)) ; # 13, A_A8 - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba01)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba01)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba01)) ; -# ------ PORT 2 ADR 3 lanes 8:13 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_spcke_ohm15_p0) && (def_is_mba23)); # 8, C1_CKE3 - 48:49 , 0b01 , ((def_cdi_spcke_ohm20_p0) && (def_is_mba23)); - 48:49 , 0b10 , ((def_cdi_spcke_ohm30_p0) && (def_is_mba23)); - 48:49 , 0b11 , ((def_cdi_spcke_ohm40_p0) && (def_is_mba23)); - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 9, C_A15 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 10, C_BA0 - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 11, C_CASn - 54:55 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p0) && (def_is_mba23)) ; # 12, C_A4 - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p0) && (def_is_mba23)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p0) && (def_is_mba23)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p0) && (def_is_mba23)) ; - 58:59 , 0b00 , ((def_cdi_ctl_ohm15_p0) && (def_is_mba23)) ; # 13, C0_CS3n - 58:59 , 0b01 , ((def_cdi_ctl_ohm20_p0) && (def_is_mba23)) ; - 58:59 , 0b10 , ((def_cdi_ctl_ohm30_p0) && (def_is_mba23)) ; - 58:59 , 0b11 , ((def_cdi_ctl_ohm40_p0) && (def_is_mba23)) ; -# 60:63 , 0b0000 , any ; # reserved -} -# ================================================================================= -# ----------------- Port 1 ADR 0 ----------------------------------------------- -# ================================================================================= -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR0 -scom 0x800140200301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 0 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 0, B1_CLK0_n - 48:49 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 1, B1_CLK0_p - 50:51 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 2, B1_CLK1_n - 52:53 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 3, B1_CLK1_p - 54:55 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; - 56:57 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba01)); # 4, B0_CKE3 - 56:57 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba01)); - 56:57 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba01)); - 56:57 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba01)); - 58:59 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 5, B0_CS3n - 58:59 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 58:59 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 58:59 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; - 60:61 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 6, B_BA0 - 60:61 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 60:61 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 60:61 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 7, B1_ODT1 - 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; -# ------ PORT 3 ADR 0 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 0, D1_CKE1 - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 1, D_BA2 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 2, D_A1 - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 3, D_A5 - 54:55 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 4, D_A12 - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 5, D_BA0 - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 60:61 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba23)); # 6, D1_CKE2 - 60:61 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba23)); - 60:61 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba23)); - 60:61 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba23)); - 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 7, D1_CS1n - 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; -} -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR0 -scom 0x800140210301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 0 lanes 8:11 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba01)); # 8, B1_CKE3 - 48:49 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba01)); - 48:49 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba01)); - 48:49 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba01)); - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 9, B_A15 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 10, B1_CS2n - 52:53 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 11, B0_CKE1 - 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; -# ------ PORT 3 ADR 0 lanes 8:11 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 8, D0_CKE0 - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 9, D0_CS2n - 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 10, D1_CLK0_p - 52:53 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 11, D1_CLK0_n - 54:55 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; -# 56:63 , 0x00 , any ; # reserved -} -# ----------------- Port 1 ADR 1 ----------------------------------------------- -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR1 -scom 0x800144200301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 1 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba01)); # 0, B0_CKE2 - 48:49 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba01)); - 48:49 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba01)); - 48:49 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba01)); - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 1, B_A7 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 2, B_A10 - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 3, B1_CKE1 - 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; - 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 4, B0_CS1n - 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 5, B_A8 - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 60:61 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 6, B_A6 - 60:61 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 60:61 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 60:61 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 7, B1_CS3n - 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; -# ------ PORT 3 ADR 1 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 0, D_A8 - 48:49 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 1, D_A13 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 2, D0_ODT1 - 52:53 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 3, D_PAR - 54:55 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 4, D1_CS0n - 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 5, D_A11 - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 60:61 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 6, D0_CKE1 - 60:61 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 60:61 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 60:61 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 62:63 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 7, D_WEn - 62:63 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 62:63 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 62:63 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; -} -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR1 -scom 0x800144210301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 1 lanes 8:11 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 8, B_A4 - 48:49 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 9, B1_CS1n - 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 10, B_A1 - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 11, B_BA1 - 54:55 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; -# ------ PORT 3 ADR 1 lanes 8:11 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba23)); # 8, D0_CKE3 - 48:49 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba23)); - 48:49 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba23)); - 48:49 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba23)); - 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 9, D1_ODT0 - 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 10, D_RASn - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 11, D0_CS1n - 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; -# 56:63 , 0x00 , any ; # reserved -} -# ----------------- Port 1 ADR 2 ----------------------------------------------- -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR2 -scom 0x800148200301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 2 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 0, B0_CS2n - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 1, B0_ODT0 - 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 2, B_WEn - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 3, B_A2 - 54:55 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 4, B0_ODT1 - 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; - 58:59 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 5, B0_CS0n - 58:59 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 58:59 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 58:59 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; - 60:61 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 6, B_A3 - 60:61 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 60:61 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 60:61 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 62:63 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 7, B_A0 - 62:63 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 62:63 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 62:63 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; -# ------ PORT 3 ADR 2 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 0, D0_CS0n - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 1, D_A10 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 2, D_A4 - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 3, D1_CS3n - 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 4, D_ACTn - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 5, D_A9 - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 60:61 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba23)); # 6, D1_CKE3 - 60:61 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba23)); - 60:61 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba23)); - 60:61 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba23)); - 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 7, D1_CKE0 - 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; -} -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR2 -scom 0x800148210301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 2 lanes 8:11 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 8, B0_CLK1_p - 48:49 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 9, B0_CLK1_n - 50:51 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 10, B_CASn - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 11, B1_CS0n - 54:55 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; - 56:57 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 12, B1_CKE0 - 56:57 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 56:57 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 56:57 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 13, B_A12 - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; -# ------ PORT 3 ADR 2 lanes 8:11 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 8, D0_CS3n - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 9, D_A2 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 10, D1_CLK1_n - 52:53 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 11, D1_CLK1_p - 54:55 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; - 56:57 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 12, D0_CLK1_n - 56:57 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; - 56:57 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; - 56:57 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; - 58:59 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 13, D0_CLK1_p - 58:59 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; - 58:59 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; - 58:59 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; -# 60:63 , 0b0000 , any ; # reserved -} -# ----------------- Port 1 ADR 3 ----------------------------------------------- -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0_P1_ADR3 -scom 0x80014c200301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 3 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 0, B_A11 - 48:49 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 1, B0_CKE0 - 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 2, B0_CLK0_n - 52:53 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba01)) ; # 3, B0_CLK0_p - 54:55 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba01)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 4, B_A13 - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 5, B_A14 - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 60:61 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba01)); # 6, B1_CKE2 - 60:61 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba01)); - 60:61 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba01)); - 60:61 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba01)); - 62:63 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba01)) ; # 7, B1_ODT0 - 62:63 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba01)) ; - 62:63 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba01)) ; - 62:63 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba01)) ; -# ------ PORT 3 ADR 3 lanes 0:7 --------------------------------------------- - 48:49 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 0, D1_CS2n - 48:49 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 1, D0_ODT0 - 50:51 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 2, D0_CLK0_n - 52:53 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_clk_ohm15_p1) && (def_is_mba23)) ; # 3, D0_CLK0_p - 54:55 , 0b01 , ((def_cdi_clk_ohm20_p1) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_clk_ohm30_p1) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_clk_ohm40_p1) && (def_is_mba23)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 4, D_A6 - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 58:59 , 0b00 , ((def_cdi_ctl_ohm15_p1) && (def_is_mba23)) ; # 5, D1_ODT1 - 58:59 , 0b01 , ((def_cdi_ctl_ohm20_p1) && (def_is_mba23)) ; - 58:59 , 0b10 , ((def_cdi_ctl_ohm30_p1) && (def_is_mba23)) ; - 58:59 , 0b11 , ((def_cdi_ctl_ohm40_p1) && (def_is_mba23)) ; - 60:61 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 6, D_A0 - 60:61 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 60:61 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 60:61 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 62:63 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 7, D_CASn - 62:63 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 62:63 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 62:63 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; -} -# DPHY01_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1_P1_ADR3 -scom 0x80014c210301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 3 lanes 8:11 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 8, B_A9 - 48:49 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 48:49 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 48:49 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 9, B_BA2 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 10, B_RASn - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 54:55 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 11, B_ACTn - 54:55 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 54:55 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 54:55 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 12, B_A5 - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; - 58:59 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba01)) ; # 13, B_PAR - 58:59 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba01)) ; - 58:59 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba01)) ; - 58:59 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba01)) ; -# ------ PORT 3 ADR 3 lanes 8:11 -------------------------------------------- - 48:49 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 8, D_A14 - 48:49 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 48:49 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 48:49 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 50:51 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 9, D_A3 - 50:51 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 50:51 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 50:51 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 52:53 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 10, D_A7 - 52:53 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 52:53 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 52:53 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 54:55 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 11, D_A15 - 54:55 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 54:55 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 54:55 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 56:57 , 0b00 , ((def_cdi_addr_ohm15_p1) && (def_is_mba23)) ; # 12, D_BA1 - 56:57 , 0b01 , ((def_cdi_addr_ohm20_p1) && (def_is_mba23)) ; - 56:57 , 0b10 , ((def_cdi_addr_ohm30_p1) && (def_is_mba23)) ; - 56:57 , 0b11 , ((def_cdi_addr_ohm40_p1) && (def_is_mba23)) ; - 58:59 , 0b00 , ((def_cdi_spcke_ohm15_p1) && (def_is_mba23)); # 13, D0_CKE2 - 58:59 , 0b01 , ((def_cdi_spcke_ohm20_p1) && (def_is_mba23)); - 58:59 , 0b10 , ((def_cdi_spcke_ohm30_p1) && (def_is_mba23)); - 58:59 , 0b11 , ((def_cdi_spcke_ohm40_p1) && (def_is_mba23)); -# 60:63 , 0b0000 , any ; # reserved -} - -#********************************************************************************** -# ADR Slew Calibration control default=0 -# DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0 0x039 0x800080390301143f -# -# --------------------------------------------------------------------------------- -# Configure slew rate mux(CTL) registers(4) slew mapping/slew mux -# set in ddrphy_reset procedure via FN call -# CTL0 = CMD, CTL1 = CNTL, CTL2 = CLK, CTL3 = SPCKE -# -# [01:23] [0:1][0:3] -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0 0x01A 0x8000401a0301143f -#scom 0x8000(40,44,48,4c)1A0301143f { # VALUE_P0_ADR[0:3] -#scom 0x800(0,1)7C1A0301143f { # VALUE_P[0:1]_ADR[0:3] broadcast -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved - # SLEW_CTL0, used for command (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE) -# 48:51 , 0b0000 , (ATTR_VPD_CEN_SLEW_RATE_ADDR[0]) ; - # SLEW_CTL1, used for control (CKE0:1, CKE4:5, ODT, CSN0:7) -# 52:55 , 0b0000 , (ATTR_VPD_CEN_SLEW_RATE_CNTL[0]) ; - # SLEW_CTL2, used for clocks (CLK0:3) -# 56:59 , 0b0000 , (ATTR_VPD_CEN_SLEW_RATE_CLK[0]) ; - # SLEW_CTL3, used for spare drams (CKE2:3, CKE6:7) -# 60:63 , 0b0000 , (ATTR_VPD_CEN_SLEW_RATE_SPCKE[0) ; -#} -#********************************************************************************** - -# --------------------------------------------------------------------------------- -# Set slew rate to select CMD(CTL0) or CNTL(CTL1) -# -# MAP0 = SLEW_CTL_SEL{0:7} MAP1 = SLEW_CTL_SEL{8:15} -# select between CTL0-3 slew rates in value register -# -# [01:23] [0:1][0:1][0:3] -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR0 0x02a 0x8000402a0301143f -# ----------------- Port 0 ADR 0 ----------------------------------------------- -scom 0x8000402a0301143f { # MAP0_P0_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 0 lanes 0:7 --------------------------------------------- -# A1_CKE1, A0_CS3n, A1_CKE0, A0_ODT0, A_A15, A_PAR, A0_CKE1, A0_CS1n -# 48:63 , 0x5505 , (def_is_mba01) ; -# ------ PORT 2 ADR 0 lanes 0:7 --------------------------------------------- -# C0_CS0n, C_A3, C1_CS3n, C_RASn, C_A12, C_A7, C0_CLK1_p, C0_CLK1_n -# 48:63 , 0x440A , (def_is_mba23) ; - 48:49 , 0b01 , (def_is_mba01) ; # 0 CNTL , A1_CKE1 - 50:51 , 0b01 , (def_is_mba01) ; # 1 CNTL , A0_CS3n - 52:53 , 0b01 , (def_is_mba01) ; # 2 CNTL , A1_CKE0 - 54:55 , 0b01 , (def_is_mba01) ; # 3 CNTL , A0_ODT0 - 56:57 , 0b00 , (def_is_mba01) ; # 4 ADDR , A_A15 - 58:59 , 0b00 , (def_is_mba01) ; # 5 ADDR , A_PAR - 60:61 , 0b01 , (def_is_mba01) ; # 6 CNTL , A0_CKE1 - 62:63 , 0b01 , (def_is_mba01) ; # 7 CNTL , A0_CS1n - # ----------------- Port 2 ADR 0 Map 0 ---------------------- - 48:49 , 0b01 , (def_is_mba23) ; # 0 CNTL , C0_CS0n - 50:51 , 0b00 , (def_is_mba23) ; # 1 ADDR , C_A3 - 52:53 , 0b01 , (def_is_mba23) ; # 2 CNTL , C1_CS3n - 54:55 , 0b00 , (def_is_mba23) ; # 3 ADDR , C_RASn - 56:57 , 0b00 , (def_is_mba23) ; # 4 ADDR , C_A12 - 58:59 , 0b00 , (def_is_mba23) ; # 5 ADDR , C_A7 - 60:61 , 0b10 , (def_is_mba23) ; # 6 CLK , C0_CLK1_p - 62:63 , 0b10 , (def_is_mba23) ; # 7 CLK , C0_CLK1_n -} -# ADR I/O FET Slice Enable Map 1 -# Register 1 containing lanes 8:15 -# [01:23] [0:1][0:1][0:3] -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR0 0x02b 0x8000402b0301143f -scom 0x8000402b0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 0 lanes 8:11 -------------------------------------------- -# A0_CKE0, A1_ODT0, A0_CLK0_p, A0_CLK0_n -# 48:55 , 0x5A , (def_is_mba01) ; -# ------ PORT 2 ADR 0 lanes 8:11 -------------------------------------------- -# C1_CLK1_p, C1_CLK1_n, C1_CKE2, C0_CKE2 -# 48:55 , 0xAF , (def_is_mba23) ; - 48:49 , 0b01 , (def_is_mba01) ; # 8 CNTL , A0_CKE0 - 50:51 , 0b01 , (def_is_mba01) ; # 9 CNTL , A1_ODT0 - 52:53 , 0b10 , (def_is_mba01) ; #10 CLK , A0_CLK0_p - 54:55 , 0b10 , (def_is_mba01) ; #11 CLK , A0_CLK0_n - # ----------------- Port 2 ADR 0 Map 1 ------------------------------------ - 48:49 , 0b10 , (def_is_mba23) ; # 8 CLK , C1_CLK1_p - 50:51 , 0b10 , (def_is_mba23) ; # 9 CLK , C1_CLK1_n - 52:53 , 0b11 , (def_is_mba23) ; #10 SPCKE , C1_CKE2 - 54:55 , 0b11 , (def_is_mba23) ; #11 SPCKE , C0_CKE2 -# 56:63 , 0b00000000 , any ; # reserved -} -# ----------------- Port 0 ADR 1 ----------------------------------------------- -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR1 -scom 0x8000442a0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 1 lanes 0:7 --------------------------------------------- -# A0_CS0n, A1_CKE3, A1_ODT1, A_A2, A_A6, A_A1, A_A14, A0_CKE2 -# 48:63 , 0x7403 , (def_is_mba01) ; -# ------ PORT 2 ADR 1 lanes 0:7 --------------------------------------------- -# C_BA2, C1_CKE1, C0_ODT1, C_WEn, C0_CS1n, C_A11, C0_CKE3, C0_CS2n -# 48:63 , 0x144D , (def_is_mba23) ; - 48:49 , 0b01 , (def_is_mba01) ; # 0 CNTL , A0_CS0n - 50:51 , 0b11 , (def_is_mba01) ; # 1 SPCKE , A1_CKE3 - 52:53 , 0b01 , (def_is_mba01) ; # 2 CNTL , A1_ODT1 - 54:55 , 0b00 , (def_is_mba01) ; # 3 ADDR , A_A2 - 56:57 , 0b00 , (def_is_mba01) ; # 4 ADDR , A_A6 - 58:59 , 0b00 , (def_is_mba01) ; # 5 ADDR , A_A1 - 60:61 , 0b00 , (def_is_mba01) ; # 6 ADDR , A_A14 - 62:63 , 0b11 , (def_is_mba01) ; # 7 SPCKE , A0_CKE2 - # ----------------- Port 2 ADR 1 Map 0 ------------------------------------ - 48:49 , 0b00 , (def_is_mba23) ; # 0 ADDR , C_BA2 - 50:51 , 0b01 , (def_is_mba23) ; # 1 CNTL , C1_CKE1 - 52:53 , 0b01 , (def_is_mba23) ; # 2 CNTL , C0_ODT1 - 54:55 , 0b00 , (def_is_mba23) ; # 3 ADDR , C_WEn - 56:57 , 0b01 , (def_is_mba23) ; # 4 CNTL , C0_CS1n - 58:59 , 0b00 , (def_is_mba23) ; # 5 ADDR , C_A11 - 60:61 , 0b11 , (def_is_mba23) ; # 6 SPCKE , C0_CKE3 - 62:63 , 0b01 , (def_is_mba23) ; # 7 CNTL , C0_CS2n -} -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR1 -scom 0x8000442b0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 1 lanes 8:11 -------------------------------------------- -# A1_CS2n, A1_CKE2, A_A4, A_RASn -# 48:55 , 0x70 , (def_is_mba01) ; -# ------ PORT 2 ADR 1 lanes 8:11 -------------------------------------------- -# C0_ODT0, C_A8, C_A5, C1_CS0n -# 48:55 , 0x41 , (def_is_mba23) ; - 48:49 , 0b01 , (def_is_mba01) ; # 8 CNTL , A1_CS2n - 50:51 , 0b11 , (def_is_mba01) ; # 9 SPCKE , A1_CKE2 - 52:53 , 0b00 , (def_is_mba01) ; #10 ADDR , A_A4 - 54:55 , 0b00 , (def_is_mba01) ; #11 ADDR , A_RASn - # ----------------- Port 2 ADR 1 Map 1 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # 8 CNTL , C0_ODT0 - 50:51 , 0b00 , (def_is_mba23) ; # 9 ADDR , C_A8 - 52:53 , 0b00 , (def_is_mba23) ; #10 ADDR , C_A5 - 54:55 , 0b01 , (def_is_mba23) ; #11 CNTL , C1_CS0n -# 56:63 , 0b00000000 , any ; # reserved -} -# ----------------- Port 0 ADR 2 ----------------------------------------------- -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR2 -scom 0x8000482a0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 2 lanes 0:7 --------------------------------------------- -# A_A12, A_A0, A0_CKE3, A1_CS3n, A1_CLK0_p, A1_CLK0_n, A0_ODT1, A1_CS0n -# 48:63 , 0x0DA5 , (def_is_mba01) ; -# ------ PORT 2 ADR 2 lanes 0:7 --------------------------------------------- -# C_A1, C_A6, C_A13, C0_CKE0, C1_ODT0, C1_CS1n, C0_CKE1, C1_CKE0 -# 48:63 , 0x0155 , (def_is_mba23) ; - 48:49 , 0b00 , (def_is_mba01) ; # 0 ADDR , A_A12 - 50:51 , 0b00 , (def_is_mba01) ; # 1 ADDR , A_A0 - 52:53 , 0b11 , (def_is_mba01) ; # 2 SPCKE , A0_CKE3 - 54:55 , 0b01 , (def_is_mba01) ; # 3 CNTL , A1_CS3n - 56:57 , 0b10 , (def_is_mba01) ; # 4 CLK , A1_CLK0_p - 58:59 , 0b10 , (def_is_mba01) ; # 5 CLK , A1_CLK0_n - 60:61 , 0b01 , (def_is_mba01) ; # 6 CNTL , A0_ODT1 - 62:63 , 0b01 , (def_is_mba01) ; # 7 CNTL , A1_CS0n - # ----------------- Port 2 ADR 2 Map 0 ------------------------------------ - 48:49 , 0b00 , (def_is_mba23) ; # 0 ADDR , C_A1 - 50:51 , 0b00 , (def_is_mba23) ; # 1 ADDR , C_A6 - 52:53 , 0b00 , (def_is_mba23) ; # 2 ADDR , C_A13 - 54:55 , 0b01 , (def_is_mba23) ; # 3 CNTL , C0_CKE0 - 56:57 , 0b01 , (def_is_mba23) ; # 4 CNTL , C1_ODT0 - 58:59 , 0b01 , (def_is_mba23) ; # 5 CNTL , C1_CS1n - 60:61 , 0b01 , (def_is_mba23) ; # 6 CNTL , C0_CKE1 - 62:63 , 0b01 , (def_is_mba23) ; # 7 CNTL , C1_CKE0 -} -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR2 -scom 0x8000482b0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 2 lanes 8:13 -------------------------------------------- -# A1_CS1n, A_A10, A0_CLK1_n, A0_CLK1_p, A1_CLK1_n, A1_CLK1_p -# 48:59 , 0x4AA , (def_is_mba01) ; -# ------ PORT 2 ADR 2 lanes 8:13 -------------------------------------------- -# C_A0, C_BA1, C0_CLK0_n, C0_CLK0_p, C1_CS2n, C_A10 -# 48:59 , 0x0A4 , (def_is_mba23) ; - 48:49 , 0b01 , (def_is_mba01) ; # 8 CNTL , A1_CS1n - 50:51 , 0b00 , (def_is_mba01) ; # 9 ADDR , A_A10 - 52:53 , 0b10 , (def_is_mba01) ; #10 CLK , A0_CLK1_n - 54:55 , 0b10 , (def_is_mba01) ; #11 CLK , A0_CLK1_p - 56:57 , 0b10 , (def_is_mba01) ; #12 CLK , A1_CLK1_n - 58:59 , 0b10 , (def_is_mba01) ; #13 CLK , A1_CLK1_p - # ----------------- Port 2 ADR 2 Map 1 ------------------------------------ - 48:49 , 0b00 , (def_is_mba23) ; # 8 ADDR , C_A0 - 50:51 , 0b00 , (def_is_mba23) ; # 9 ADDR , C_BA1 - 52:53 , 0b10 , (def_is_mba23) ; #10 CLK , C0_CLK0_n - 54:55 , 0b10 , (def_is_mba23) ; #11 CLK , C0_CLK0_p - 56:57 , 0b01 , (def_is_mba23) ; #12 CNTL , C1_CS2n - 58:59 , 0b00 , (def_is_mba23) ; #13 ADDR , C_A10 -# 60:63 , 0b0000 , any ; # reserved -} -# ----------------- Port 0 ADR 3 ----------------------------------------------- -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P0_ADR3 -scom 0x80004c2a0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 3 lanes 0:7 --------------------------------------------- -# A_A13, A_BA0, A_WEn, A0_CS2n, A_BA1, A_CASn, A_A5, A_A3 -# 48:63 , 0x0100 , (def_is_mba01) ; -# ------ PORT 2 ADR 3 lanes 0:7 --------------------------------------------- -# C_PAR, C1_ODT1, C1_CLK0_p, C1_CLK0_n, C_A14, C_A9, C_ACTn, C_A2 -# 48:63 , 0x1A00 , (def_is_mba23) ; - 48:49 , 0b00 , (def_is_mba01) ; # 0 ADDR , A_A13 - 50:51 , 0b00 , (def_is_mba01) ; # 1 ADDR , A_BA0 - 52:53 , 0b00 , (def_is_mba01) ; # 2 ADDR , A_WEn - 54:55 , 0b01 , (def_is_mba01) ; # 3 CNTL , A0_CS2n - 56:57 , 0b00 , (def_is_mba01) ; # 4 ADDR , A_BA1 - 58:59 , 0b00 , (def_is_mba01) ; # 5 ADDR , A_CASn - 60:61 , 0b00 , (def_is_mba01) ; # 6 ADDR , A_A5 - 62:63 , 0b00 , (def_is_mba01) ; # 7 ADDR , A_A3 - # ----------------- Port 2 ADR 3 Map 0 ------------------------------------ - 48:49 , 0b00 , (def_is_mba23) ; # 0 ADDR , C_PAR - 50:51 , 0b01 , (def_is_mba23) ; # 1 CNTL , C1_ODT1 - 52:53 , 0b10 , (def_is_mba23) ; # 2 CLK , C1_CLK0_p - 54:55 , 0b10 , (def_is_mba23) ; # 3 CLK , C1_CLK0_n - 56:57 , 0b00 , (def_is_mba23) ; # 4 ADDR , C_A14 - 58:59 , 0b00 , (def_is_mba23) ; # 5 ADDR , C_A9 - 60:61 , 0b00 , (def_is_mba23) ; # 6 ADDR , C_ACTn - 62:63 , 0b00 , (def_is_mba23) ; # 7 ADDR , C_A2 -} -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P0_ADR3 -scom 0x80004c2b0301143f { - bits , scom_data , expr ; # signal -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 0 ADR 3 lanes 8:13 -------------------------------------------- -# A_BA2, A_A11, A_A7, A_ACTn, A_A9, A_A8 -# 48:59 , 0x000 , (def_is_mba01) ; -# ------ PORT 2 ADR 3 lanes 8:13 -------------------------------------------- -# C1_CKE3, C_A15, C_BA0, C_CASn, C_A4, C0_CS3n -# 48:59 , 0xC01 , (def_is_mba23) ; - 48:49 , 0b00 , (def_is_mba01) ; # 8 ADDR , A_BA2 - 50:51 , 0b00 , (def_is_mba01) ; # 9 ADDR , A_A11 - 52:53 , 0b00 , (def_is_mba01) ; #10 ADDR , A_A7 - 54:55 , 0b00 , (def_is_mba01) ; #11 ADDR , A_ACTn - 56:57 , 0b00 , (def_is_mba01) ; #12 ADDR , A_A9 - 58:59 , 0b00 , (def_is_mba01) ; #13 ADDR , A_A8 - # ----------------- Port 2 ADR 3 Map 1 ------------------------------------ - 48:49 , 0b11 , (def_is_mba23) ; # 8 SPCKE , C1_CKE3 - 50:51 , 0b00 , (def_is_mba23) ; # 9 ADDR , C_A15 - 52:53 , 0b00 , (def_is_mba23) ; #10 ADDR , C_BA0 - 54:55 , 0b00 , (def_is_mba23) ; #11 ADDR , C_CASn - 56:57 , 0b00 , (def_is_mba23) ; #12 ADDR , C_A4 - 58:59 , 0b01 , (def_is_mba23) ; #13 CNTL , C0_CS3n -# 60:63 , 0b0000 , any ; # reserved -} -# ================================================================================= -# ----------------- Port 1 ADR 0 ----------------------------------------------- -# ================================================================================= -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR0 -scom 0x8001402a0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 0 lanes 0:7 --------------------------------------------- -# B1_CLK0_n, B1_CLK0_p, B1_CLK1_n, B1_CLK1_p, B0_CKE3, B0_CS3n, B_BA0, B1_ODT1 -# 48:63 , 0xAAD1 , (def_is_mba01) ; -# ------ PORT 3 ADR 0 lanes 0:7 --------------------------------------------- -# D1_CKE1, D_BA2, D_A1, D_A5, D_A12, D_BA0, D1_CKE2, D1_CS1n -# 48:63 , 0x400D , (def_is_mba23) ; - 48:49 , 0b10 , (def_is_mba01) ; # 0 CLK , B1_CLK0_n - 50:51 , 0b10 , (def_is_mba01) ; # 1 CLK , B1_CLK0_p - 52:53 , 0b10 , (def_is_mba01) ; # 2 CLK , B1_CLK1_n - 54:55 , 0b10 , (def_is_mba01) ; # 3 CLK , B1_CLK1_p - 56:57 , 0b11 , (def_is_mba01) ; # 4 SPCKE , B0_CKE3 - 58:59 , 0b01 , (def_is_mba01) ; # 5 CNTL , B0_CS3n - 60:61 , 0b00 , (def_is_mba01) ; # 6 ADDR , B_BA0 - 62:63 , 0b01 , (def_is_mba01) ; # 7 CNTL , B1_ODT1 - # ----------------- Port 3 ADR 0 Map 0 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # 0 CNTL , D1_CKE1 - 50:51 , 0b00 , (def_is_mba23) ; # 1 ADDR , D_BA2 - 52:53 , 0b00 , (def_is_mba23) ; # 2 ADDR , D_A1 - 54:55 , 0b00 , (def_is_mba23) ; # 3 ADDR , D_A5 - 56:57 , 0b00 , (def_is_mba23) ; # 4 ADDR , D_A12 - 58:59 , 0b00 , (def_is_mba23) ; # 5 ADDR , D_BA0 - 60:61 , 0b11 , (def_is_mba23) ; # 6 SPCKE , D1_CKE2 - 62:63 , 0b01 , (def_is_mba23) ; # 7 CNTL , D1_CS1n -} -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR0 -scom 0x8001402b0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 0 lanes 8:11 -------------------------------------------- -# B1_CKE3, B_A15, B1_CS2n, B0_CKE1 -# 48:55 , 0xC5 , (def_is_mba01) ; -# ------ PORT 3 ADR 0 lanes 8:11 -------------------------------------------- -# D0_CKE0, D0_CS2n, D1_CLK0_p, D1_CLK0_n -# 48:55 , 0x5A , (def_is_mba23) ; - 48:49 , 0b11 , (def_is_mba01) ; # 8 SPCKE , B1_CKE3 - 50:51 , 0b00 , (def_is_mba01) ; # 9 ADDR , B_A15 - 52:53 , 0b01 , (def_is_mba01) ; #10 CNTL , B1_CS2n - 54:55 , 0b01 , (def_is_mba01) ; #11 CNTL , B0_CKE1 - # ----------------- Port 3 ADR 0 Map 1 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # 8 CNTL , D0_CKE0 - 50:51 , 0b01 , (def_is_mba23) ; # 9 CNTL , D0_CS2n - 52:53 , 0b10 , (def_is_mba23) ; #10 CLK , D1_CLK0_p - 54:55 , 0b10 , (def_is_mba23) ; #11 CLK , D1_CLK0_n -# 56:63 , 0b00000000 , any ; # reserved -} -# ----------------- Port 1 ADR 1 ----------------------------------------------- -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR1 -scom 0x8001442a0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 1 lanes 0:7 --------------------------------------------- -# B0_CKE2, B_A7, B_A10, B1_CKE1, B0_CS1n, B_A8, B_A6, B1_CS3n -# 48:63 , 0xC141 , (def_is_mba01) ; -# ------ PORT 3 ADR 1 lanes 0:7 --------------------------------------------- -# D_A8, D_A13, D0_ODT1, D_PAR, D1_CS0n, D_A11, D0_CKE1, D_WEn -# 48:63 , 0x0444 , (def_is_mba23) ; - 48:49 , 0b11 , (def_is_mba01) ; # 0 SPCKE , B0_CKE2 - 50:51 , 0b00 , (def_is_mba01) ; # 1 ADDR , B_A7 - 52:53 , 0b00 , (def_is_mba01) ; # 2 ADDR , B_A10 - 54:55 , 0b01 , (def_is_mba01) ; # 3 CNTL , B1_CKE1 - 56:57 , 0b01 , (def_is_mba01) ; # 4 CNTL , B0_CS1n - 58:59 , 0b00 , (def_is_mba01) ; # 5 ADDR , B_A8 - 60:61 , 0b00 , (def_is_mba01) ; # 6 ADDR , B_A6 - 62:63 , 0b01 , (def_is_mba01) ; # 7 CNTL , B1_CS3n - # ----------------- Port 3 ADR 1 Map 0 ------------------------------------ - 48:49 , 0b00 , (def_is_mba23) ; # 0 ADDR , D_A8 - 50:51 , 0b00 , (def_is_mba23) ; # 1 ADDR , D_A13 - 52:53 , 0b01 , (def_is_mba23) ; # 2 CNTL , D0_ODT1 - 54:55 , 0b00 , (def_is_mba23) ; # 3 ADDR , D_PAR - 56:57 , 0b01 , (def_is_mba23) ; # 4 CNTL , D1_CS0n - 58:59 , 0b00 , (def_is_mba23) ; # 5 ADDR , D_A11 - 60:61 , 0b01 , (def_is_mba23) ; # 6 CNTL , D0_CKE1 - 62:63 , 0b00 , (def_is_mba23) ; # 7 ADDR , D_WEn -} -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR1 -scom 0x8001442b0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 1 lanes 8:11 -------------------------------------------- -# B_A4, B1_CS1n, B_A1, B_BA1 -# 48:55 , 0x10 , (def_is_mba01) ; -# ------ PORT 3 ADR 1 lanes 8:11 -------------------------------------------- -# D0_CKE3, D1_ODT0, D_RASn, D0_CS1n -# 48:55 , 0xD1 , (def_is_mba23) ; - 48:49 , 0b00 , (def_is_mba01) ; # 8 ADDR , B_A4 - 50:51 , 0b01 , (def_is_mba01) ; # 9 CNTL , B1_CS1n - 52:53 , 0b00 , (def_is_mba01) ; #10 ADDR , B_A1 - 54:55 , 0b00 , (def_is_mba01) ; #11 ADDR , B_BA1 - # ----------------- Port 3 ADR 1 Map 1 ------------------------------------ - 48:49 , 0b11 , (def_is_mba23) ; # 8 CNTL , D0_CKE3 - 50:51 , 0b01 , (def_is_mba23) ; # 9 CNTL , D1_ODT0 - 52:53 , 0b00 , (def_is_mba23) ; #10 ADDR , D_RASn - 54:55 , 0b01 , (def_is_mba23) ; #11 CNTL , D0_CS1n -# 56:63 , 0b00000000 , any ; # reserved -} -# ----------------- Port 1 ADR 2 ----------------------------------------------- -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR2 -scom 0x8001482a0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 2 lanes 0:7 --------------------------------------------- -# B0_CS2n, B0_ODT0, B_WEn, B_A2, B0_ODT1, B0_CS0n, B_A3, B_A0 -# 48:63 , 0x5050 , (def_is_mba01) ; -# ------ PORT 3 ADR 2 lanes 0:7 --------------------------------------------- -# D0_CS0n, D_A10, D_A4, D1_CS3n, D_ACTn, D_A9, D1_CKE3, D1_CKE0 -# 48:63 , 0x410D , (def_is_mba23) ; - 48:49 , 0b01 , (def_is_mba01) ; # 0 CNTL , B0_CS2n - 50:51 , 0b01 , (def_is_mba01) ; # 1 CNTL , B0_ODT0 - 52:53 , 0b00 , (def_is_mba01) ; # 2 ADDR , B_WEn - 54:55 , 0b00 , (def_is_mba01) ; # 3 ADDR , B_A2 - 56:57 , 0b01 , (def_is_mba01) ; # 4 CNTL , B0_ODT1 - 58:59 , 0b01 , (def_is_mba01) ; # 5 CNTL , B0_CS0n - 60:61 , 0b00 , (def_is_mba01) ; # 6 ADDR , B_A3 - 62:63 , 0b00 , (def_is_mba01) ; # 7 ADDR , B_A0 - # ----------------- Port 3 ADR 2 Map 0 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # 0 CNTL , D0_CS0n - 50:51 , 0b00 , (def_is_mba23) ; # 1 ADDR , D_A10 - 52:53 , 0b00 , (def_is_mba23) ; # 2 ADDR , D_A4 - 54:55 , 0b01 , (def_is_mba23) ; # 3 CNTL , D1_CS3n - 56:57 , 0b00 , (def_is_mba23) ; # 4 ADDR , D_ACTn - 58:59 , 0b00 , (def_is_mba23) ; # 5 ADDR , D_A9 - 60:61 , 0b11 , (def_is_mba23) ; # 6 SPCKE , D1_CKE3 - 62:63 , 0b01 , (def_is_mba23) ; # 7 CNTL , D1_CKE0 -} -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR2 -scom 0x8001482b0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 2 lanes 8:11 -------------------------------------------- -# B0_CLK1_p, B0_CLK1_n, B_CASn, B1_CS0n, B1_CKE0, B_A12 -# 48:59 , 0xA14 , (def_is_mba01) ; -# ------ PORT 3 ADR 2 lanes 8:11 -------------------------------------------- -# D0_CS3n, D_A2, D1_CLK1_n, D1_CLK1_p, D0_CLK1_n, D0_CLK1_p -# 48:59 , 0x4AA , (def_is_mba23) ; - 48:49 , 0b10 , (def_is_mba01) ; # 8 CLK , B0_CLK1_p - 50:51 , 0b10 , (def_is_mba01) ; # 9 CLK , B0_CLK1_n - 52:53 , 0b00 , (def_is_mba01) ; #10 ADDR , B_CASn - 54:55 , 0b01 , (def_is_mba01) ; #11 CNTL , B1_CS0n - 56:57 , 0b01 , (def_is_mba01) ; #12 CNTL , B1_CKE0 - 58:59 , 0b00 , (def_is_mba01) ; #13 ADDR , B_A12 - # ----------------- Port 3 ADR 2 Map 1 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # 8 CNTL , D0_CS3n - 50:51 , 0b00 , (def_is_mba23) ; # 9 ADDR , D_A2 - 52:53 , 0b10 , (def_is_mba23) ; #10 CLK , D1_CLK1_n - 54:55 , 0b10 , (def_is_mba23) ; #11 CLK , D1_CLK1_p - 56:57 , 0b10 , (def_is_mba23) ; #12 CLK , D0_CLK1_n - 58:59 , 0b10 , (def_is_mba23) ; #13 CLK , D0_CLK1_p -# 60:63 , 0b0000 , any ; # reserved -} -# ----------------- Port 1 ADR 3 ----------------------------------------------- -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0_P1_ADR3 -scom 0x80014c2a0301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 3 lanes 0:7 --------------------------------------------- -# B_A11, B0_CKE0, B0_CLK0_n, B0_CLK0_p, B_A13, B_A14, B1_CKE2, B1_ODT0 -# 48:63 , 0x1A0D , (def_is_mba01) ; -# ------ PORT 3 ADR 3 lanes 0:7 --------------------------------------------- -# D1_CS2n, D0_ODT0, D0_CLK0_n, D0_CLK0_p, D_A6, D1_ODT1, D_A0, D_CASn -# 48:63 , 0x5A10 , (def_is_mba23) ; - 48:49 , 0b00 , (def_is_mba01) ; # 0 ADDR , B_A11 - 50:51 , 0b01 , (def_is_mba01) ; # 1 CNTL , B0_CKE0 - 52:53 , 0b10 , (def_is_mba01) ; # 2 CLK , B0_CLK0_n - 54:55 , 0b10 , (def_is_mba01) ; # 3 CLK , B0_CLK0_p - 56:57 , 0b00 , (def_is_mba01) ; # 4 ADDR , B_A13 - 58:59 , 0b00 , (def_is_mba01) ; # 5 ADDR , B_A14 - 60:61 , 0b11 , (def_is_mba01) ; # 6 SPCKE , B1_CKE2 - 62:63 , 0b01 , (def_is_mba01) ; # 7 CNTL , B1_ODT0 - # ----------------- Port 3 ADR 3 Map 0 ------------------------------------ - 48:49 , 0b01 , (def_is_mba23) ; # 0 CNTL , D1_CS2n - 50:51 , 0b01 , (def_is_mba23) ; # 1 CNTL , D0_ODT0 - 52:53 , 0b10 , (def_is_mba23) ; # 2 CLK , D0_CLK0_n - 54:55 , 0b10 , (def_is_mba23) ; # 3 CLK , D0_CLK0_p - 56:57 , 0b00 , (def_is_mba23) ; # 4 ADDR , D_A6 - 58:59 , 0b01 , (def_is_mba23) ; # 5 CNTL , D1_ODT1 - 60:61 , 0b00 , (def_is_mba23) ; # 6 ADDR , D_A0 - 62:63 , 0b00 , (def_is_mba23) ; # 7 ADDR , D_CASn -} -# DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1_P1_ADR3 -scom 0x80014c2b0301143f { - bits , scom_data , expr ; # signal -# 0:47 , 0x000000000000, any ; # reserved -# ------ PORT 1 ADR 3 lanes 8:11 -------------------------------------------- -# B_A9, B_BA2, B_RASn, B_ACTn, B_A5, B_PAR -# 48:59 , 0x000 , (def_is_mba01) ; -# ------ PORT 3 ADR 3 lanes 8:11 -------------------------------------------- -# D_A14, D_A3, D_A7, D_A15, D_BA1, D0_CKE2 -# 48:59 , 0x003 , (def_is_mba23) ; - 48:49 , 0b00 , (def_is_mba01) ; # 8 ADDR , B_A9 - 50:51 , 0b00 , (def_is_mba01) ; # 9 ADDR , B_BA2 - 52:53 , 0b00 , (def_is_mba01) ; #10 ADDR , B_RASn - 54:55 , 0b00 , (def_is_mba01) ; #11 ADDR , B_ACTn - 56:57 , 0b00 , (def_is_mba01) ; #12 ADDR , B_A5 - 58:59 , 0b00 , (def_is_mba01) ; #13 ADDR , B_PAR - # ----------------- Port 3 ADR 3 Map 1 ------------------------------------ - 48:49 , 0b00 , (def_is_mba23) ; # 8 ADDR , D_A14 - 50:51 , 0b00 , (def_is_mba23) ; # 9 ADDR , D_A3 - 52:53 , 0b00 , (def_is_mba23) ; #10 ADDR , D_A7 - 54:55 , 0b00 , (def_is_mba23) ; #11 ADDR , D_A15 - 56:57 , 0b00 , (def_is_mba23) ; #12 ADDR , D_BA1 - 58:59 , 0b11 , (def_is_mba23) ; #13 SPCKE , D0_CKE2 -# 60:63 , 0b0000 , any ; # reserved -} - -# --------------------------------------------------------------------------------------- -# ADR I/O Post Cursor Value Register default=0 not needed anymore -# DPHY01_DDRPHY_ADR_IO_POST_CURSOR_VALUE_P0_ADR0 0x018 0x800040180301143f -# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_18_L2 -# -# --------------------------------------------------------------------------------------- -# ADR I/O Post Cursor Value Map {0-1} Register default=0 not needed anymore -# DPHY01_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0_P0_ADR0 0x028 0x800040280301143f -# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_28_L2 - -# --------------------------------------------------------------------------------------- -# Centaur Vref Trimmer Control & RCM default=0 !! need to set RCM for DDR3/4 -# -# Also sets RCM for DDR4 MPR mode setting(staggered, serial, parallel, custom) with -# SEQ Read/Write Data register for values (seq_rd_wr_data) -# -# ATTR_EFF_CEN_RD_VREF DDR3 = [40375, 41750, 43125, .... 61000] 1.37% -# DDR4 = [60375, 61750, 63125, ... 81000] 1.38% -# -# Vref trim for Centaur is in approximately 1.375% increments from 0.40375 to 0.575. -# Example: VDD = 1.5V(nom DDR3), ATTR_EFF_DRAM_WR_VREF = 500, -# Vref = VDD * ATTR_EFF_DRAM_WR_VREF/1000 = 0.750 V -# -# Vref Trim table bits=MCVREF[0:3] -# ________DDR3 (POD=0)__________|___________DDR4 (POD=1)_________ -# 0xF = 0.61000 0x0 = 0.50000 | 0xF = 0.81000 0x0 = 0.70000 -# 0xE = 0.59625 0x1 = 0.48625 | 0xE = 0.79625 0x1 = 0.68625 -# 0xD = 0.58250 0x2 = 0.47250 | 0xD = 0.78250 0x2 = 0.67250 -# 0xC = 0.56875 0x3 = 0.45875 | 0xC = 0.76875 0x3 = 0.65875 -# 0xB = 0.55500 0x4 = 0.44500 | 0xB = 0.75500 0x4 = 0.64500 -# 0xA = 0.54125 0x5 = 0.43125 | 0xA = 0.74125 0x5 = 0.63125 -# 0x9 = 0.52750 0x6 = 0.41750 | 0x9 = 0.72750 0x6 = 0.61750 -# 0x8 = 0.51375 0x7 = 0.40375 | 0x8 = 0.71375 0x7 = 0.60375 -# -# DP18_IO_RX_CONFIG0 -# [01:23] P[0:1]_[0:4] -# DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0 0x006 0x800000060301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.RCVRPEAK_L2 -#scom 0x800(0,1)(00,04,08,0C,10)060301143f { # _P[0:1]_[0:4] -scom 0x80003C060301143f { # _P0_[0:4] via broadcast - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:50 , 0b000 , any ; # PEAK_AMP_CTL_SIDE0, amp ctl bits -# 51 , 0b0 , any ; # reserved, 0=no peaking, [1:7]=0.3dB-0.9dB - 52:54 , 0b000 , any ; # PEAK_AMP_CTL_SIDE1, amp ctl bits -# 55 , 0b0 , any ; # reserved - # SxMCVREF_0_3, Vref trim ctl signals DDR3 DDR4 - 56:59 , 0xF , ((ATTR_EFF_CEN_RD_VREF[0] == 61000) || (ATTR_EFF_CEN_RD_VREF[0] == 81000)) ; - 56:59 , 0xE , ((ATTR_EFF_CEN_RD_VREF[0] == 59625) || (ATTR_EFF_CEN_RD_VREF[0] == 79625)) ; - 56:59 , 0xD , ((ATTR_EFF_CEN_RD_VREF[0] == 58250) || (ATTR_EFF_CEN_RD_VREF[0] == 78250)) ; - 56:59 , 0xC , ((ATTR_EFF_CEN_RD_VREF[0] == 56875) || (ATTR_EFF_CEN_RD_VREF[0] == 76875)) ; - 56:59 , 0xB , ((ATTR_EFF_CEN_RD_VREF[0] == 55500) || (ATTR_EFF_CEN_RD_VREF[0] == 75500)) ; - 56:59 , 0xA , ((ATTR_EFF_CEN_RD_VREF[0] == 54125) || (ATTR_EFF_CEN_RD_VREF[0] == 74125)) ; - 56:59 , 0x9 , ((ATTR_EFF_CEN_RD_VREF[0] == 52750) || (ATTR_EFF_CEN_RD_VREF[0] == 72750)) ; - 56:59 , 0x8 , ((ATTR_EFF_CEN_RD_VREF[0] == 51375) || (ATTR_EFF_CEN_RD_VREF[0] == 71375)) ; - 56:59 , 0x0 , ((ATTR_EFF_CEN_RD_VREF[0] == 50000) || (ATTR_EFF_CEN_RD_VREF[0] == 70000)) ; - 56:59 , 0x1 , ((ATTR_EFF_CEN_RD_VREF[0] == 48625) || (ATTR_EFF_CEN_RD_VREF[0] == 68625)) ; - 56:59 , 0x2 , ((ATTR_EFF_CEN_RD_VREF[0] == 47250) || (ATTR_EFF_CEN_RD_VREF[0] == 67250)) ; - 56:59 , 0x3 , ((ATTR_EFF_CEN_RD_VREF[0] == 45875) || (ATTR_EFF_CEN_RD_VREF[0] == 65875)) ; - 56:59 , 0x4 , ((ATTR_EFF_CEN_RD_VREF[0] == 44500) || (ATTR_EFF_CEN_RD_VREF[0] == 64500)) ; - 56:59 , 0x5 , ((ATTR_EFF_CEN_RD_VREF[0] == 43125) || (ATTR_EFF_CEN_RD_VREF[0] == 63125)) ; - 56:59 , 0x6 , ((ATTR_EFF_CEN_RD_VREF[0] == 41750) || (ATTR_EFF_CEN_RD_VREF[0] == 61750)) ; - 56:59 , 0x7 , ((ATTR_EFF_CEN_RD_VREF[0] == 40375) || (ATTR_EFF_CEN_RD_VREF[0] == 60375)) ; - 56:59 , 0x0 , any ; - 60 , 0b1 , (def_is_ddr4) ; # SxPODVREF, if DDR4, POD=0.7*VDD - 60 , 0b0 , any ; # else (DDR3), POD=0.5*VDD - 61 , 0b0 , any ; # 1=DISABLE_TERMINATION, for dq/dqs pins - # READ_CENTERING_MODE - # (00=MPR_PATTERN_BIT or staggered, custom [11=snooped, 00=custom] using SEQ rd/wr data - 62:63 , 0b11 , (def_is_ddr4) ; # for DDR4 - 62:63 , 0b00 , any ; # -} - -scom 0x80013C060301143f { # _P1_[0:4] via broadcast - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:50 , 0b000 , any ; # PEAK_AMP_CTL_SIDE0, amp ctl bits -# 51 , 0b0 , any ; # reserved, 0=no peaking, [1:7]=0.3dB-0.9dB - 52:54 , 0b000 , any ; # PEAK_AMP_CTL_SIDE1, amp ctl bits -# 55 , 0b0 , any ; # reserved - # SxMCVREF_0_3, Vref trim ctl signals DDR3 DDR4 - 56:59 , 0xF , ((ATTR_EFF_CEN_RD_VREF[1] == 61000) || (ATTR_EFF_CEN_RD_VREF[1] == 81000)) ; - 56:59 , 0xE , ((ATTR_EFF_CEN_RD_VREF[1] == 59625) || (ATTR_EFF_CEN_RD_VREF[1] == 79625)) ; - 56:59 , 0xD , ((ATTR_EFF_CEN_RD_VREF[1] == 58250) || (ATTR_EFF_CEN_RD_VREF[1] == 78250)) ; - 56:59 , 0xC , ((ATTR_EFF_CEN_RD_VREF[1] == 56875) || (ATTR_EFF_CEN_RD_VREF[1] == 76875)) ; - 56:59 , 0xB , ((ATTR_EFF_CEN_RD_VREF[1] == 55500) || (ATTR_EFF_CEN_RD_VREF[1] == 75500)) ; - 56:59 , 0xA , ((ATTR_EFF_CEN_RD_VREF[1] == 54125) || (ATTR_EFF_CEN_RD_VREF[1] == 74125)) ; - 56:59 , 0x9 , ((ATTR_EFF_CEN_RD_VREF[1] == 52750) || (ATTR_EFF_CEN_RD_VREF[1] == 72750)) ; - 56:59 , 0x8 , ((ATTR_EFF_CEN_RD_VREF[1] == 51375) || (ATTR_EFF_CEN_RD_VREF[1] == 71375)) ; - 56:59 , 0x0 , ((ATTR_EFF_CEN_RD_VREF[1] == 50000) || (ATTR_EFF_CEN_RD_VREF[1] == 70000)) ; - 56:59 , 0x1 , ((ATTR_EFF_CEN_RD_VREF[1] == 48625) || (ATTR_EFF_CEN_RD_VREF[1] == 68625)) ; - 56:59 , 0x2 , ((ATTR_EFF_CEN_RD_VREF[1] == 47250) || (ATTR_EFF_CEN_RD_VREF[1] == 67250)) ; - 56:59 , 0x3 , ((ATTR_EFF_CEN_RD_VREF[1] == 45875) || (ATTR_EFF_CEN_RD_VREF[1] == 65875)) ; - 56:59 , 0x4 , ((ATTR_EFF_CEN_RD_VREF[1] == 44500) || (ATTR_EFF_CEN_RD_VREF[1] == 64500)) ; - 56:59 , 0x5 , ((ATTR_EFF_CEN_RD_VREF[1] == 43125) || (ATTR_EFF_CEN_RD_VREF[1] == 63125)) ; - 56:59 , 0x6 , ((ATTR_EFF_CEN_RD_VREF[1] == 41750) || (ATTR_EFF_CEN_RD_VREF[1] == 61750)) ; - 56:59 , 0x7 , ((ATTR_EFF_CEN_RD_VREF[1] == 40375) || (ATTR_EFF_CEN_RD_VREF[1] == 60375)) ; - 56:59 , 0x0 , any ; - 60 , 0b1 , (def_is_ddr4) ; # SxPODVREF, if DDR4, POD=0.7*VDD - 60 , 0b0 , any ; # else (DDR3), POD=0.5*VDD - 61 , 0b0 , any ; # 1=DISABLE_TERMINATION, for dq/dqs pins - # READ_CENTERING_MODE - # (00=MPR_PATTERN_BIT or staggered, custom [11=snooped, 00=custom] using SEQ rd/wr data - 62:63 , 0b11 , (def_is_ddr4) ; # for DDR4 - 62:63 , 0b00 , any ; # -} - -#------------------------------------------------------------------------------- -# DDR Vref Output Driver Control register default=0, output to DIMM -# -# ATTR_EFF_DRAM_WR_VREF DDR3 = [420, 425, 430, ... 575] -# Note: NOT valid for DDR4. -# -# Vref driven to the DIMM(s) in 0.5% increments from 0.420 to 0.575. -# Example: VDD=1.5V(nom DDR3), ATTR_EFF_DRAM_WR_VREF = 500, -# Vref = VDD * ATTR_EFF_DRAM_WR_VREF/1000 = 0.750 V -# -# sign bit, VREFDQ[0:3]D -# 01111 = 575+ 01110 = 535 10000 = 495 10001 = 455 -# 00111 = 570 00110 = 530 11000 = 490 11001 = 450 -# 01011 = 565 01010 = 525 10100 = 485 10101 = 445 -# 00011 = 560 00010 = 520 11100 = 480 11101 = 440 -# 01101 = 555 01100 = 515 10010 = 475 10011 = 435 -# 00101 = 550 00100 = 510 11010 = 470 11011 = 430 -# 01001 = 545 01000 = 505 10110 = 465 10111 = 425 -# 00001 = 540 00000 = 500* 11110 = 460 11111 = 420- -# -# [01:23] [0:1] -# DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0 0x015 0x8000c0150301143f -scom 0x8000c0150301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48 , 0b1 , (ATTR_EFF_DRAM_WR_VREF[0] < 500) ; # VREF[0]DQ0 sign bit - 48 , 0b0 , (ATTR_EFF_DRAM_WR_VREF[0] >= 500) ; # VREF[0]DQ0 sign bit - # VREF[0]DQ0D bit enables - 49:52 , 0xF , ((ATTR_EFF_DRAM_WR_VREF[0] == 575) || (ATTR_EFF_DRAM_WR_VREF[0] == 420)) ; - 49:52 , 0x7 , ((ATTR_EFF_DRAM_WR_VREF[0] == 570) || (ATTR_EFF_DRAM_WR_VREF[0] == 425)) ; - 49:52 , 0xB , ((ATTR_EFF_DRAM_WR_VREF[0] == 565) || (ATTR_EFF_DRAM_WR_VREF[0] == 430)) ; - 49:52 , 0x3 , ((ATTR_EFF_DRAM_WR_VREF[0] == 560) || (ATTR_EFF_DRAM_WR_VREF[0] == 435)) ; - 49:52 , 0xD , ((ATTR_EFF_DRAM_WR_VREF[0] == 555) || (ATTR_EFF_DRAM_WR_VREF[0] == 440)) ; - 49:52 , 0x5 , ((ATTR_EFF_DRAM_WR_VREF[0] == 550) || (ATTR_EFF_DRAM_WR_VREF[0] == 445)) ; - 49:52 , 0x9 , ((ATTR_EFF_DRAM_WR_VREF[0] == 545) || (ATTR_EFF_DRAM_WR_VREF[0] == 450)) ; - 49:52 , 0x1 , ((ATTR_EFF_DRAM_WR_VREF[0] == 540) || (ATTR_EFF_DRAM_WR_VREF[0] == 455)) ; - 49:52 , 0xE , ((ATTR_EFF_DRAM_WR_VREF[0] == 535) || (ATTR_EFF_DRAM_WR_VREF[0] == 460)) ; - 49:52 , 0x6 , ((ATTR_EFF_DRAM_WR_VREF[0] == 530) || (ATTR_EFF_DRAM_WR_VREF[0] == 465)) ; - 49:52 , 0xA , ((ATTR_EFF_DRAM_WR_VREF[0] == 525) || (ATTR_EFF_DRAM_WR_VREF[0] == 470)) ; - 49:52 , 0x2 , ((ATTR_EFF_DRAM_WR_VREF[0] == 520) || (ATTR_EFF_DRAM_WR_VREF[0] == 475)) ; - 49:52 , 0xC , ((ATTR_EFF_DRAM_WR_VREF[0] == 515) || (ATTR_EFF_DRAM_WR_VREF[0] == 480)) ; - 49:52 , 0x4 , ((ATTR_EFF_DRAM_WR_VREF[0] == 510) || (ATTR_EFF_DRAM_WR_VREF[0] == 485)) ; - 49:52 , 0x8 , ((ATTR_EFF_DRAM_WR_VREF[0] == 505) || (ATTR_EFF_DRAM_WR_VREF[0] == 490)) ; - 49:52 , 0x0 , ((ATTR_EFF_DRAM_WR_VREF[0] == 500) || (ATTR_EFF_DRAM_WR_VREF[0] == 495)) ; - 49:52 , 0b0000 , any ; # VREF[0]DQ0D bit enables - 53 , 0b1 , (ATTR_EFF_DRAM_WR_VREF[0] < 500) ; # VREF[0]DQ1 sign bit - 53 , 0b0 , (ATTR_EFF_DRAM_WR_VREF[0] >= 500) ; # VREF[0]DQ1 sign bit - # VREF[0]DQ1D bit enables - 54:57 , 0xF , ((ATTR_EFF_DRAM_WR_VREF[0] == 575) || (ATTR_EFF_DRAM_WR_VREF[0] == 420)) ; - 54:57 , 0x7 , ((ATTR_EFF_DRAM_WR_VREF[0] == 570) || (ATTR_EFF_DRAM_WR_VREF[0] == 425)) ; - 54:57 , 0xB , ((ATTR_EFF_DRAM_WR_VREF[0] == 565) || (ATTR_EFF_DRAM_WR_VREF[0] == 430)) ; - 54:57 , 0x3 , ((ATTR_EFF_DRAM_WR_VREF[0] == 560) || (ATTR_EFF_DRAM_WR_VREF[0] == 435)) ; - 54:57 , 0xD , ((ATTR_EFF_DRAM_WR_VREF[0] == 555) || (ATTR_EFF_DRAM_WR_VREF[0] == 440)) ; - 54:57 , 0x5 , ((ATTR_EFF_DRAM_WR_VREF[0] == 550) || (ATTR_EFF_DRAM_WR_VREF[0] == 445)) ; - 54:57 , 0x9 , ((ATTR_EFF_DRAM_WR_VREF[0] == 545) || (ATTR_EFF_DRAM_WR_VREF[0] == 450)) ; - 54:57 , 0x1 , ((ATTR_EFF_DRAM_WR_VREF[0] == 540) || (ATTR_EFF_DRAM_WR_VREF[0] == 455)) ; - 54:57 , 0xE , ((ATTR_EFF_DRAM_WR_VREF[0] == 535) || (ATTR_EFF_DRAM_WR_VREF[0] == 460)) ; - 54:57 , 0x6 , ((ATTR_EFF_DRAM_WR_VREF[0] == 530) || (ATTR_EFF_DRAM_WR_VREF[0] == 465)) ; - 54:57 , 0xA , ((ATTR_EFF_DRAM_WR_VREF[0] == 525) || (ATTR_EFF_DRAM_WR_VREF[0] == 470)) ; - 54:57 , 0x2 , ((ATTR_EFF_DRAM_WR_VREF[0] == 520) || (ATTR_EFF_DRAM_WR_VREF[0] == 475)) ; - 54:57 , 0xC , ((ATTR_EFF_DRAM_WR_VREF[0] == 515) || (ATTR_EFF_DRAM_WR_VREF[0] == 480)) ; - 54:57 , 0x4 , ((ATTR_EFF_DRAM_WR_VREF[0] == 510) || (ATTR_EFF_DRAM_WR_VREF[0] == 485)) ; - 54:57 , 0x8 , ((ATTR_EFF_DRAM_WR_VREF[0] == 505) || (ATTR_EFF_DRAM_WR_VREF[0] == 490)) ; - 54:57 , 0x0 , ((ATTR_EFF_DRAM_WR_VREF[0] == 500) || (ATTR_EFF_DRAM_WR_VREF[0] == 495)) ; - 54:57 , 0b0000 , any ; -# 58:63 , 0b000000 , any ; # reserved - -# 48:57 , 0x1EF , (ATTR_EFF_DRAM_WR_VREF[0] == 575) ; # 0b 0 1111 0 1111 , 0b01 1110 1111 -# 48:57 , 0x0E7 , (ATTR_EFF_DRAM_WR_VREF[0] == 570) ; # 0b 0 0111 0 0111 , 0b00 1110 0111 -# 48:57 , 0x16B , (ATTR_EFF_DRAM_WR_VREF[0] == 565) ; # 0b 0 1011 0 1011 , 0b01 0110 1011 -# 48:57 , 0x063 , (ATTR_EFF_DRAM_WR_VREF[0] == 560) ; # 0b 0 0011 0 0011 , 0b00 0110 0011 -# 48:57 , 0x1AD , (ATTR_EFF_DRAM_WR_VREF[0] == 555) ; # 0b 0 1101 0 1101 , 0b01 1010 1101 -# 48:57 , 0x0A5 , (ATTR_EFF_DRAM_WR_VREF[0] == 550) ; # 0b 0 0101 0 0101 , 0b00 1010 0101 -# 48:57 , 0x129 , (ATTR_EFF_DRAM_WR_VREF[0] == 545) ; # 0b 0 1001 0 1001 , 0b01 0010 1001 -# 48:57 , 0x029 , (ATTR_EFF_DRAM_WR_VREF[0] == 540) ; # 0b 0 0001 0 0001 , 0b00 0010 0001 -# 48:57 , 0x1CE , (ATTR_EFF_DRAM_WR_VREF[0] == 535) ; # 0b 0 1110 0 1110 , 0b01 1100 1110 -# 48:57 , 0x0C6 , (ATTR_EFF_DRAM_WR_VREF[0] == 530) ; # 0b 0 0110 0 0110 , 0b00 1100 0110 -# 48:57 , 0x14A , (ATTR_EFF_DRAM_WR_VREF[0] == 525) ; # 0b 0 1010 0 1010 , 0b01 0100 1010 -# 48:57 , 0x042 , (ATTR_EFF_DRAM_WR_VREF[0] == 520) ; # 0b 0 0010 0 0010 , 0b00 0100 0010 -# 48:57 , 0x01C , (ATTR_EFF_DRAM_WR_VREF[0] == 515) ; # 0b 0 1100 0 1100 , 0b01 1000 1100 -# 48:57 , 0x004 , (ATTR_EFF_DRAM_WR_VREF[0] == 510) ; # 0b 0 0100 0 0100 , 0b00 1000 0100 -# 48:57 , 0x108 , (ATTR_EFF_DRAM_WR_VREF[0] == 505) ; # 0b 0 1000 0 1000 , 0b01 0000 1000 -# 48:57 , 0x000 , (ATTR_EFF_DRAM_WR_VREF[0] == 500) ; # 0b 0 0000 0 0000 , 0b00 0000 0000 -# 48:57 , 0x210 , (ATTR_EFF_DRAM_WR_VREF[0] == 495) ; # 0b 1 0000 1 0000 , 0b10 0001 0000 -# 48:57 , 0x318 , (ATTR_EFF_DRAM_WR_VREF[0] == 490) ; # 0b 1 1000 1 1000 , 0b11 0001 1000 -# 48:57 , 0x294 , (ATTR_EFF_DRAM_WR_VREF[0] == 485) ; # 0b 1 0100 1 0100 , 0b10 1001 0100 -# 48:57 , 0x39C , (ATTR_EFF_DRAM_WR_VREF[0] == 480) ; # 0b 1 1100 1 1100 , 0b11 1001 1100 -# 48:57 , 0x252 , (ATTR_EFF_DRAM_WR_VREF[0] == 475) ; # 0b 1 0010 1 0010 , 0b10 0101 0010 -# 48:57 , 0x35A , (ATTR_EFF_DRAM_WR_VREF[0] == 470) ; # 0b 1 1010 1 1010 , 0b11 0101 1010 -# 48:57 , 0x2D6 , (ATTR_EFF_DRAM_WR_VREF[0] == 465) ; # 0b 1 0110 1 0110 , 0b10 1101 0110 -# 48:57 , 0x3DE , (ATTR_EFF_DRAM_WR_VREF[0] == 460) ; # 0b 1 1110 1 1110 , 0b11 1101 1110 -# 48:57 , 0x231 , (ATTR_EFF_DRAM_WR_VREF[0] == 455) ; # 0b 1 0001 1 0001 , 0b10 0011 0001 -# 48:57 , 0x339 , (ATTR_EFF_DRAM_WR_VREF[0] == 450) ; # 0b 1 1001 1 1001 , 0b11 0011 1001 -# 48:57 , 0x2B5 , (ATTR_EFF_DRAM_WR_VREF[0] == 445) ; # 0b 1 0101 1 0101 , 0b10 1011 0101 -# 48:57 , 0x3BD , (ATTR_EFF_DRAM_WR_VREF[0] == 440) ; # 0b 1 1101 1 1101 , 0b11 1011 1101 -# 48:57 , 0x273 , (ATTR_EFF_DRAM_WR_VREF[0] == 435) ; # 0b 1 0011 1 0011 , 0b10 0111 0011 -# 48:57 , 0x37B , (ATTR_EFF_DRAM_WR_VREF[0] == 430) ; # 0b 1 1011 1 1011 , 0b11 0111 1011 -# 48:57 , 0x2F7 , (ATTR_EFF_DRAM_WR_VREF[0] == 425) ; # 0b 1 0111 1 0111 , 0b10 1111 0111 -# 48:57 , 0x3FF , (ATTR_EFF_DRAM_WR_VREF[0] == 420) ; # 0b 1 1111 1 1111 , 0b11 1111 1111 -# 58:63 , 0b000000 , any ; # reserved -} -# DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P1 0x015 0x8001c0150301143f -scom 0x8001c0150301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48 , 0b1 , (ATTR_EFF_DRAM_WR_VREF[1] < 500) ; # VREF[1]DQ0 sign bit - 48 , 0b0 , (ATTR_EFF_DRAM_WR_VREF[1] >= 500) ; # VREF[1]DQ0 sign bit - # VREF[1]DQ0D bit enables - 49:52 , 0xF , ((ATTR_EFF_DRAM_WR_VREF[1] == 575) || (ATTR_EFF_DRAM_WR_VREF[1] == 420)) ; - 49:52 , 0x7 , ((ATTR_EFF_DRAM_WR_VREF[1] == 570) || (ATTR_EFF_DRAM_WR_VREF[1] == 425)) ; - 49:52 , 0xB , ((ATTR_EFF_DRAM_WR_VREF[1] == 565) || (ATTR_EFF_DRAM_WR_VREF[1] == 430)) ; - 49:52 , 0x3 , ((ATTR_EFF_DRAM_WR_VREF[1] == 560) || (ATTR_EFF_DRAM_WR_VREF[1] == 435)) ; - 49:52 , 0xD , ((ATTR_EFF_DRAM_WR_VREF[1] == 555) || (ATTR_EFF_DRAM_WR_VREF[1] == 440)) ; - 49:52 , 0x5 , ((ATTR_EFF_DRAM_WR_VREF[1] == 550) || (ATTR_EFF_DRAM_WR_VREF[1] == 445)) ; - 49:52 , 0x9 , ((ATTR_EFF_DRAM_WR_VREF[1] == 545) || (ATTR_EFF_DRAM_WR_VREF[1] == 450)) ; - 49:52 , 0x1 , ((ATTR_EFF_DRAM_WR_VREF[1] == 540) || (ATTR_EFF_DRAM_WR_VREF[1] == 455)) ; - 49:52 , 0xE , ((ATTR_EFF_DRAM_WR_VREF[1] == 535) || (ATTR_EFF_DRAM_WR_VREF[1] == 460)) ; - 49:52 , 0x6 , ((ATTR_EFF_DRAM_WR_VREF[1] == 530) || (ATTR_EFF_DRAM_WR_VREF[1] == 465)) ; - 49:52 , 0xA , ((ATTR_EFF_DRAM_WR_VREF[1] == 525) || (ATTR_EFF_DRAM_WR_VREF[1] == 470)) ; - 49:52 , 0x2 , ((ATTR_EFF_DRAM_WR_VREF[1] == 520) || (ATTR_EFF_DRAM_WR_VREF[1] == 475)) ; - 49:52 , 0xC , ((ATTR_EFF_DRAM_WR_VREF[1] == 515) || (ATTR_EFF_DRAM_WR_VREF[1] == 480)) ; - 49:52 , 0x4 , ((ATTR_EFF_DRAM_WR_VREF[1] == 510) || (ATTR_EFF_DRAM_WR_VREF[1] == 485)) ; - 49:52 , 0x8 , ((ATTR_EFF_DRAM_WR_VREF[1] == 505) || (ATTR_EFF_DRAM_WR_VREF[1] == 490)) ; - 49:52 , 0x0 , ((ATTR_EFF_DRAM_WR_VREF[1] == 500) || (ATTR_EFF_DRAM_WR_VREF[1] == 495)) ; - 49:52 , 0b0000 , any ; # VREF[1]DQ0D bit enables - 53 , 0b1 , (ATTR_EFF_DRAM_WR_VREF[1] < 500) ; # VREF[1]DQ1 sign bit - 53 , 0b0 , (ATTR_EFF_DRAM_WR_VREF[1] >= 500) ; # VREF[1]DQ1 sign bit - # VREF[1]DQ1D bit enables - 54:57 , 0xF , ((ATTR_EFF_DRAM_WR_VREF[1] == 575) || (ATTR_EFF_DRAM_WR_VREF[1] == 420)) ; - 54:57 , 0x7 , ((ATTR_EFF_DRAM_WR_VREF[1] == 570) || (ATTR_EFF_DRAM_WR_VREF[1] == 425)) ; - 54:57 , 0xB , ((ATTR_EFF_DRAM_WR_VREF[1] == 565) || (ATTR_EFF_DRAM_WR_VREF[1] == 430)) ; - 54:57 , 0x3 , ((ATTR_EFF_DRAM_WR_VREF[1] == 560) || (ATTR_EFF_DRAM_WR_VREF[1] == 435)) ; - 54:57 , 0xD , ((ATTR_EFF_DRAM_WR_VREF[1] == 555) || (ATTR_EFF_DRAM_WR_VREF[1] == 440)) ; - 54:57 , 0x5 , ((ATTR_EFF_DRAM_WR_VREF[1] == 550) || (ATTR_EFF_DRAM_WR_VREF[1] == 445)) ; - 54:57 , 0x9 , ((ATTR_EFF_DRAM_WR_VREF[1] == 545) || (ATTR_EFF_DRAM_WR_VREF[1] == 450)) ; - 54:57 , 0x1 , ((ATTR_EFF_DRAM_WR_VREF[1] == 540) || (ATTR_EFF_DRAM_WR_VREF[1] == 455)) ; - 54:57 , 0xE , ((ATTR_EFF_DRAM_WR_VREF[1] == 535) || (ATTR_EFF_DRAM_WR_VREF[1] == 460)) ; - 54:57 , 0x6 , ((ATTR_EFF_DRAM_WR_VREF[1] == 530) || (ATTR_EFF_DRAM_WR_VREF[1] == 465)) ; - 54:57 , 0xA , ((ATTR_EFF_DRAM_WR_VREF[1] == 525) || (ATTR_EFF_DRAM_WR_VREF[1] == 470)) ; - 54:57 , 0x2 , ((ATTR_EFF_DRAM_WR_VREF[1] == 520) || (ATTR_EFF_DRAM_WR_VREF[1] == 475)) ; - 54:57 , 0xC , ((ATTR_EFF_DRAM_WR_VREF[1] == 515) || (ATTR_EFF_DRAM_WR_VREF[1] == 480)) ; - 54:57 , 0x4 , ((ATTR_EFF_DRAM_WR_VREF[1] == 510) || (ATTR_EFF_DRAM_WR_VREF[1] == 485)) ; - 54:57 , 0x8 , ((ATTR_EFF_DRAM_WR_VREF[1] == 505) || (ATTR_EFF_DRAM_WR_VREF[1] == 490)) ; - 54:57 , 0x0 , ((ATTR_EFF_DRAM_WR_VREF[1] == 500) || (ATTR_EFF_DRAM_WR_VREF[1] == 495)) ; - 54:57 , 0b0000 , any ; -# 58:63 , 0b000000 , any ; # reserved -} - -# --------------------------------------------------------------------------------------- -# SEQ Read/Write Data {0-1} Register default=0x5555 !! need to set to custom mode -# for DDR3 -# Attributes -# Read/Write via programming interface. Two registers. These two registers are used to -# create eight beats of data by repeating every fourth bit of data within a beat. -# -# Description -# The data in these registers are used to write the custom training pattern into a specified -# memory location during calibration operations which use reserved memory locations in the -# memory devices. The data in these registers is also used as comparison data during calibration -# operations that perform a read operation from a reserved memory location which requires the -# incoming read data to be compared. This register must be programmed to the pre-defined pattern -# for protocols which provide a pre-defined pattern for read calibrations. For the most robust -# centering solution, custom patterns for DQS Centering should have data transitions at all -# beats. Each bit lane can have a different pattern, but the composite pattern should have -# transitions at each beat. -# -# 48:63 , 0x0000 , (def_is_sim) ; # to match dials -# -# in DDR3 only bits 48:55 are used as pattern, and 56:63 must match 48:55. -# [0:1] -# DPHY01_DDRPHY_SEQ_RD_WR_DATA0_P0 0x000-0x001 0x8000c4000301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.RD_WR_DATA0_L2 -scom 0x8000c4000301143f { - bits , scom_data , expr ; # beat 12345678 -# 0:47 , 0x000000000000, any ; # reserved -# if DDR4 = 0:7 (MPR0), 8:15 (MPR1) - 48:63 , 0x5555 , any ; # MPR_PATTERN_BIT of 0F0F0F0F pattern -# 48:63 , 0xD896 , any ; # 1st half-nibble of EA0CA653 pattern -} -# DPHY01_DDRPHY_SEQ_RD_WR_DATA1_P0 -scom 0x8000c4010301143f { - bits , scom_data , expr ; # beat 12345678 -# 0:47 , 0x000000000000, any ; # reserved -# if DDR4 = 0:7 (MPR2), 8:15 (MPR3) - 48:63 , 0x5555 , any ; # MPR_PATTERN_BIT of 0F0F0F0F pattern -# 48:63 , 0xD896 , any ; # 1st half-nibble of EA0CA653 pattern -} - -# DPHY01_DDRPHY_SEQ_RD_WR_DATA0_P1 -scom 0x8001c4000301143f { - bits , scom_data , expr ; # beat 12345678 -# 0:47 , 0x000000000000, any ; # reserved -# if DDR4 = 0:7 (MPR0), 8:15 (MPR1) - 48:63 , 0x5555 , any ; # MPR_PATTERN_BIT of 0F0F0F0F pattern -# 48:63 , 0xCD03 , any ; # 2st half-nibble of EA0CA653 pattern -} -# DPHY01_DDRPHY_SEQ_RD_WR_DATA1_P1 -scom 0x8001c4010301143f { - bits , scom_data , expr ; # beat 12345678 -# 0:47 , 0x000000000000, any ; # reserved -# if DDR4 = 0:7 (MPR2), 8:15 (MPR3) - 48:63 , 0x5555 , any ; # MPR_PATTERN_BIT of 0F0F0F0F pattern -# 48:63 , 0xCD03 , any ; # 2st half-nibble of EA0CA653 pattern -} - -# --------------------------------------------------------------------------------------- -# DP18 Pattern Position 0 Register default=0 -# needed for DDR4 staggered pattern, not setting in initfile since needs to be sequenced. -# -# SYSTEM Dependent due to wiring on data bus. -# Volt = planar. all ISDIMMs (LRDIMM, UDIMM, RDIMM) should have same wiring. Ken requirement. -# -# Bare minimum to support DDR4 parallel/staggered pattern on single rank or all ranks if wired -# exactly the same per port, or if this register is written to each time a calibration of a rank -# is performed. -# -# use CDIMM to identify, need short vs tall? -# -# Need to check with layout people(Brian Connolly[CDIMM] and Cindy Armstrong[ISDIMMs on Volt]) -# in order to confirm C4 to DQ mappings. -# -# No need to set POS_2 since lanes 16-23 always DQS -# POS_0_P0_0 = DP0, lanes 0-7 -# POS_1_P0_0 = DP0, lanes 8-15 -# POS_0_P0_1 = DP1, lanes 0-7 -# POS_1_P0_1 = DP1, lanes 8-15 -# POS_0_P0_2 = DP2, lanes 0-7 -# POS_1_P0_2 = DP2, lanes 8-15 -# POS_0_P0_3 = DP3, lanes 0-7 -# POS_1_P0_3 = DP3, lanes 8-15 -# POS_0_P0_4 = DP4, lanes 0-7 -# POS_1_P0_4 = DP4, lanes 8-15 -# -# [01:23] [0:2]_P[0:1]_[0:4] -# DPHY01_DDRPHY_DP18_PATTERN_POS_0_P0_0 0x032 0x800000320301143f -# DPHY01_DDRPHY_DP18_PATTERN_POS_1_P0_0 0x033 0x800000330301143f -# DPHY01_DDRPHY_DP18_PATTERN_POS_2_P0_0 0x034 0x800000340301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.DQMAP0_7_L2 -# - -#------------------------------------------------------------------------------- -# ODT Default Configuration Register -# -# Determines the ODT values sent to all ranks during MRS commands -# basically used when ODT pins used as CID (chip ID) for TSV DIMMs... -# -# DDRPHY_SEQ_ODT_DEFAULT_CONFIG SEQ 0x024 0x... -# -# 48:55 = ODT[0:7] - -#------------------------------------------------------------------------------- -# ODT Read Registers default=0 -# -# Determines the ODT values sent to all ranks when the given rank in read -# operation during calibration. -# 48:55 are ODT pins 0-7 (bit0-7) during read of rank {0-3}*2 -# 56:63 are ODT pins 0-7 (bit8-15) during read of rank {0-3}*2+1 -# -# bit#=odt# 0..1 0..1 0..3 ODT0:1 ODT2:3 ODT4:5 ODT6:7 -# ATTR_VPD_ODT_RD[port][dimm][rank] = dimm0 dimm1 dimm2 unused; -# bits 0:1 2:3 4:5 6:7 -# -# DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG0_P0 0x00E 0x8000c40e0301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.ODT_RD_CONFIG0_L2 -scom 0x8000C40E0301143F { -# ODT 01234567 - bits , scom_data ; # DIMM0, Port0 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_RD[0][0][0] ; # when Read of Rank0 - 56:63 , ATTR_VPD_ODT_RD[0][0][1] ; # when Read of Rank1 -} -# DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG1_P0 -scom 0x8000C40F0301143F { - bits , scom_data ; # DIMM0, Port0 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_RD[0][0][2] ; # when Read of Rank2 - 56:63 , ATTR_VPD_ODT_RD[0][0][3] ; # when Read of Rank3 -} -# DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG2_P0 -scom 0x8000C4100301143F { - bits , scom_data ; # DIMM1, Port0 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_RD[0][1][0] ; # when Read of Rank4 - 56:63 , ATTR_VPD_ODT_RD[0][1][1] ; # when Read of Rank5 -} -# DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG3_P0 -scom 0x8000C4110301143F { - bits , scom_data ; # DIMM1, Port0 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_RD[0][1][2] ; # when Read of Rank6 - 56:63 , ATTR_VPD_ODT_RD[0][1][3] ; # when Read of Rank7 -} -# ------- Read ODT Port 1 (DIMM2 & DIMM3) ---------------------------------- -# DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG0_P1 -scom 0x8001C40E0301143F { - bits , scom_data ; # DIMM2, Port1 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_RD[1][0][0] ; # when Read of Rank0 - 56:63 , ATTR_VPD_ODT_RD[1][0][1] ; # when Read of Rank1 -} -# DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG1_P1 -scom 0x8001C40F0301143F { - bits , scom_data ; # DIMM2, Port1 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_RD[1][0][2] ; # when Read of Rank2 - 56:63 , ATTR_VPD_ODT_RD[1][0][3] ; # when Read of Rank3 -} -# DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG2_P1 -scom 0x8001C4100301143F { - bits , scom_data ; # DIMM3, Port1 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_RD[1][1][0] ; # when Read of Rank4 - 56:63 , ATTR_VPD_ODT_RD[1][1][1] ; # when Read of Rank5 -} -# DPHY01_DDRPHY_SEQ_ODT_RD_CONFIG3_P1 -scom 0x8001C4110301143F { - bits , scom_data ; # DIMM3, Port1 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_RD[1][1][2] ; # when Read of Rank6 - 56:63 , ATTR_VPD_ODT_RD[1][1][3] ; # when Read of Rank7 -} -#================================================================================ -# ODT write registers default=0 -# -# bit#=odt# 0..1 0..1 0..3 ODT0:1 ODT2:3 ODT4:5 ODT6:7 -# ATTR_VPD_ODT_WR[port][dimm][rank] = dimm0 dimm1 dimm2 unused ; -# -# DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG0_P0 0x000A 0x8000c40a0301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.ODT_WR_CONFIG0_L2 -scom 0x8000C40A0301143F { - bits , scom_data ; # DIMM0, Port0 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_WR[0][0][0] ; # when write of Rank0 - 56:63 , ATTR_VPD_ODT_WR[0][0][1] ; # when write of Rank1 -} -# DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG1_P0 -scom 0x8000C40B0301143F { - bits , scom_data ; # DIMM0, Port0 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_WR[0][0][2] ; # when write of Rank2 - 56:63 , ATTR_VPD_ODT_WR[0][0][3] ; # when write of Rank3 -} -# DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG2_P0 -scom 0x8000C40C0301143F { - bits , scom_data ; # DIMM1, Port0 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_WR[0][1][0] ; # when write of Rank4 - 56:63 , ATTR_VPD_ODT_WR[0][1][1] ; # when write of Rank5 -} -# DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG3_P0 -scom 0x8000C40D0301143F { - bits , scom_data ; # DIMM1, Port0 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_WR[0][1][2] ; # when write of Rank6 - 56:63 , ATTR_VPD_ODT_WR[0][1][3] ; # when write of Rank7 -} -# ------- Write ODT Port 1 (DIMM2 & DIMM3) ---------------------------------- -# DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG0_P1 -scom 0x8001C40A0301143F { - bits , scom_data ; # DIMM2, Port1 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_WR[1][0][0] ; # when write of Rank0 - 56:63 , ATTR_VPD_ODT_WR[1][0][1] ; # when write of Rank1 -} -# DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG1_P1 -scom 0x8001C40B0301143F { - bits , scom_data ; # DIMM2, Port1 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_WR[1][0][2] ; # when write of Rank2 - 56:63 , ATTR_VPD_ODT_WR[1][0][3] ; # when write of Rank3 -} -# DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG2_P1 -scom 0x8001C40C0301143F { - bits , scom_data ; # DIMM3, Port1 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_WR[1][1][0] ; # when write of Rank4 - 56:63 , ATTR_VPD_ODT_WR[1][1][1] ; # when write of Rank5 -} -# DPHY01_DDRPHY_SEQ_ODT_WR_CONFIG3_P1 -scom 0x8001C40D0301143F { - bits , scom_data ; # DIMM3, Port1 -# 0:47 , 0x000000000000 ; # reserved - 48:55 , ATTR_VPD_ODT_WR[1][1][2] ; # when write of Rank6 - 56:63 , ATTR_VPD_ODT_WR[1][1][3] ; # when write of Rank7 -} - -# --------------------------------------------------------------------------------------- -# PC MODE registers default=0 done in mss_draminit.C -# -# DPHY01_DDRPHY_PC_MR0_PRI_RP0_P0 0x01C 0x8000c01c0301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG28_RP0_L2 - -# --------------------------------------------------------------------------------------- -# PC Chip select ID configuration register default=0 NEED to be programmed for DDR4/TSV dimms. -# HERE MW -# -# This register controls the value of Chip Select (CS) signals not selected -# by any of the PC Rank Pair registers during initial calibration for DDR4 / TSV dimms. -# -# DPHY01_DDRPHY_PC_CSID_CFG_P0 0x033 0x8000c0330301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG51_L2 -scom 0x800(0,1)c0330301143f { - bits , scom_data ; -# 0:47 , 0x000000000000 ; # reserved - 48:55 , 0xFF ; # CS[0:7] level - 56:63 , 0x00 ; # reserved -} - -# --------------------------------------------------------------------------------------- -# DP18 DQSCLK offset default=0x0200 needed for SIM -# -# Used to pervent switching to the live DQS too early in RLDRAM or DDR4 modes or during -# calibration routines of all protocols. -# -# DQS_OFFSET = 10 + ceiling(peak_to_peak_jitter_magnitude_in_ticks / 2) -# or more specifically: -# DQS_OFFSET = 2 + ceiling(peak_to_peak_jitter_magnitude_in_ticks / 2) + -# (peak_to_peak_periodic_drift_in_ticks/2) -# Where peak_to_peak_jitter_magnitude_in_ticks is a whole number equal to the read clock -# strobe (DQS) peak to peak jitter rounded up to the nearest 128th memory clock. And, -# peak_to_peak_periodic_drift_in_ticks is the peak to peak drift of the read clock strobe -# (DQS) rounded up to the nearest 128th memory clock. -# The + 2 term in the equation accounts for the jitter sources within the DDR PHY. -# -# Setup margin time... would cause read errors if set incorrectly. -# James Mossman for more details. -# -# DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_0 0x037 0x800000370301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.DQSOFFSET_L2(0:6) -#scom 0x8000(00,04,08,0C,10)370301143f { # _P0_[0:4], all instances -scom 0x800(0,1)3C370301143f { # _P[0:1]_[0:4] - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved -# 48 , 0b0 , any ; # reserved -# 49:55 , 0b0010000 , (def_is_sim) ; # DQS_OFFSET - 49:55 , def_dqs_offset , any ; # DQS_OFFSET, 7 bits -# 56:63 , 0b0 , any ; # reserved -} - -# --------------------------------------------------------------------------------------- -# DP18 Write DQ offset value register default=0 -# -# Used to shift(left/right) the Write Eye after Write centering calibration. -# The value is 2's complement and can only move it in 2 tick increments. -# NOTE: Does NOT affect the data bit delay values if Write centering calibration is not run! -# -# 200 ps offset / # steps based on freq? -# -# [01:23] _RP[0:3]_P[0:1]_[0:4] -# DPHY01_DDRPHY_DP18_DQ_WR_OFFSET_RP0_P0_0 0x07E 0x8000007e0301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DQS_WR_OFFSET_RP0_L2 -# -#scom 0x8000007e0301143f { # _RP0_P0_0 -#scom 0x8000(00,04,08,0C,10)7E0301143f { # _RP0_P0_[0:4], all instances -#scom 0x80003C7E0301143f { # _RP0_P0_[0:4], all instances via broadcast -#scom 0x80003(C,D,E,F)7E0301143f { # _RP[0:3]_P0_[0:4], all instances(broadcast), all rank pairs -#scom 0x80003CFE0301143f { # _RP[0:3]_P0_[0:4], all instances and rank pairs via broadcast -# -# _RP[0:3]_P[0:1]_[0:4], all instances and rank pairs via broadcast, both ports -# scom 0x800(0,1)3CFE0301143f { # _RP[0:3]_P[0:1]_[0:4] -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved -# 48:51 , 0x0 , any ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , any ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , any ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , any ; # DQ_WR_OFFSET_N3 -# } -# -# scom 0x80003C7E0301143f { # _RP0_P0_[0:4], rank pair 0, all instances via broadcast -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved -# ~~~~~~~~~~~~~~~ Port 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N3 -# ~~~~~~~~~~~~~~~ Port 2 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N3 -# } -# scom 0x80003D7E0301143f { # _RP1_P0_[0:4], rank pair 1, all instances via broadcast -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved -# ~~~~~~~~~~~~~~~ Port 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N3 -# ~~~~~~~~~~~~~~~ Port 2 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N3 -# } -# scom 0x80003E7E0301143f { # _RP2_P0_[0:4], rank pair 2, all instances via broadcast -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved -# ~~~~~~~~~~~~~~~ Port 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N3 -# ~~~~~~~~~~~~~~~ Port 2 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N3 -# } -# scom 0x80003F7E0301143f { # _RP3_P0_[0:4], rank pair 3, all instances via broadcast -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved -# ~~~~~~~~~~~~~~~ Port 0 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N3 -# ~~~~~~~~~~~~~~~ Port 2 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N3 -# } -# =============================================================================== -# scom 0x80013C7E0301143f { # _RP0_P1_[0:4], rank pair 0, all instances via broadcast -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved -# ~~~~~~~~~~~~~~~ Port 1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N3 -# ~~~~~~~~~~~~~~~ Port 3 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N3 -# } -# scom 0x80013D7E0301143f { # _RP1_P1_[0:4], rank pair 1, all instances via broadcast -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved -# ~~~~~~~~~~~~~~~ Port 1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N3 -# ~~~~~~~~~~~~~~~ Port 3 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N3 -# } -# scom 0x80013E7E0301143f { # _RP2_P1_[0:4], rank pair 2, all instances via broadcast -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved -# ~~~~~~~~~~~~~~~ Port 1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N3 -# ~~~~~~~~~~~~~~~ Port 3 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N3 -# } -# scom 0x80013F7E0301143f { # _RP3_P1_[0:4], rank pair 3, all instances via broadcast -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved -# ~~~~~~~~~~~~~~~ Port 1 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba01) ; # DQ_WR_OFFSET_N3 -# ~~~~~~~~~~~~~~~ Port 3 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -# 48:51 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N0 -# 52:55 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N1 -# 56:59 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N2 -# 60:63 , 0x0 , (def_is_mba23) ; # DQ_WR_OFFSET_N3 -# } - -# --------------------------------------------------------------------------------------- -# DP18 Write Delay Value {0-23} Register default=0x0008 !! set after characterization -# -# Attributes -# Read/Write via programming interface. Write via hardware. -# 20 registers hold the delay values for the twenty-four MEMINTDnnB pins for a given -# rank pair. DP18 lanes 16-23 can only be used as DQS. As such, registers for lanes 17, 19, -# 21, 23 exist, yet serve no purpose. Lane 16 register controls both DQS lanes 16 and 17, etc. -# A 24 register set exists for each rank pair. 96 total registers. -# -# Description -# This register holds the write delay values for one of the MEMINTDnnB pins for one Rank Pair -# within the DP18. The write leveling calibration algorithms write this register. The write -# leveling algorithm does not reset this register. The write eye centering algorithm uses this -# register value as a starting point for the algorithm. -# -# Note: This register must be reset prior to re-running initial calibration. -# -# DPHY01_DP18_WR_DELAY_VALUE_0_RP0_REG_P0_0 0x038-0x04F 0x800000380301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DP18_WR_DELAY_VALUE_0_RP0_REG_L2 -# - -# --------------------------------------------------------------------------------------- -# DP18 Read Delay Value {0-11} Register default=0x4040 !! characterization req'd -# -# Attributes -# Read/Write via programming interface. Write via hardware. Each register holds the delay value -# for two of the twenty-four MEMINTDnnB pins on the DP18. -# An 8 register set exists for each rank pair: DP18 Read Delay Value {0-7}. 32 total registers. -# -# Description -# This register holds the read delay values for two of the MEMINTDnnB pins for one Rank Pair -# within the DP18. The read centering calibration algorithms writes this register. The read -# centering algorithm does not reset this register. The read centering algorithm uses this -# register value as a starting point for the algorithm. -# -# DPHY01_DDRPHY_DP18_READ_DELAY0_RANK_PAIR0_P0_0 0x050-0x05B 0x800000500301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.SL#0.DL#1.RDDP18FIFO_MAC.R0RDCLKDLY_L2 -# - -# --------------------------------------------------------------------------------------- -# DP18 Drift Limits Register default=0 !! set after characterization -# -# Description -# This register holds the limits for periodic drift of the data eye and the received strobe. -# -# DPHY01_DDRPHY_DP18_DRIFT_LIMITS_P0_0 0x00A 0x8000000a0301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.LIMITS_L2 -# -# min_rd_eye_size, max_dqs_drift -# 0 disables check - -# --------------------------------------------------------------------------------------- -# DP18 DQS Gate Delay Register default=0 !! need to set this? -# -# This register contains the DQS gate delay settings for each incoming read clock. One -# register exists for each rank pair. -# -# From Centaur Chip Spec, section 9.4.12.3, -# The PHY can only auto-calibrate within a 4-memory clock cycle delay window as -# determined by the Gate Delay equation. If more than 4 cycles of delay exist on the -# memory interface, the RLO must be increased by a sufficient amount until the resulting -# Gate Delay falls within the 4 cycle window. Since the RLO applies to all bits on the -# interface, it has the effect of directly adding latency to the overall data return time -# and effectively sliding the entire calibration window in time. -# -# gateDelay = -# ((staticDQSgateDelay + cmdDelayMax + dqsDelayMax - (RLO * clkPeriod)) * 0x80 / clkPeriod) >> 7 -# -# DPHY01_DDRPHY_DP18_DQS_GATE_DELAY_RP0_P0_0 0x013 0x800000130301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.SL#3.RDDP18DQS_MAC.DQSLOGIC.R0DQSCDLY_L2 -# - -## --------------------------------------------------------------------------------------- -## DP18 Read Diagnostic Configuration 3 Register default=0x0806 !! need to set this? -## -## DDRPHY_DP18_RD_DIA_CONFIG3 0x06D 0x8000006d0301143f -#scom 0x800(0,1)0C6D0301143F { # broadcast all instances -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved -## 48:55 , 0x08 , any ; # DP18_0_DESIRED_EDGE_CNTR_TARGET_HIGH(0:7) default -# 48:55 , 0x0C , any ; # DP18_0_DESIRED_EDGE_CNTR_TARGET_HIGH(0:7) SWyatt -## 56:63 , 0x06 , any ; # DP18_0_DESIRED_EDGE_CNTR_TARGET_HIGH(0:7) default -# 56:63 , 0x08 , any ; # DP18_0_DESIRED_EDGE_CNTR_TARGET_HIGH(0:7) SWyatt -#} - -# --------------------------------------------------------------------------------------- -# DP18 Read Diagnostic Configuration 5 Register default=0x0000 -# -# DDRPHY_DP18_RD_DIA_CONFIG5 0x012 0x800000120301143f -scom 0x800(0,1)3C120301143F { # broadcast all instances - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# 48 , 0b0 , any ; #0 DYN_POWER_CNTL_EN -# 49 , 0b0 , (def_is_sim) ; #1 DYN_MCTERM_CNTL_EN -# 50 , 0b0 , (def_is_sim) ; #2 DYN_RX_GATE_CNTL_EN -# 51 , 0b0 , (def_is_sim) ; #3 CALGATE_ON -# 52 , 0b0 , (def_is_sim) ; #4 PER_RDCLK_UPDATE_DISABLE -# 53:54 , 0b00 , (def_is_sim) ; #5 DQS_PIPE_FIX_DIS -# 55 , 0b0 , (def_is_sim) ; #6 DD2_DQS_FIX_DIS -# 56 , 0b0 , any ; #7 DL_FORCE_ON -# 57 , 0b0 , any ; #8 BLFIFO_DIS -# 58 , 0b0 , any ; #9 WTRFL_AVE_DIS -# 59 , 0b0 , any ; #A PERCAL_PWR_DIS default - 59 , 0b1 , any ; #B PERCAL_PWR_DIS SWyatt -# 60 , 0b0 , any ; #C LOOPBACK_FIX_EN -# 61 , 0b0 , any ; #D LOOPBACK_DLY12 -# 62 , 0b0 , any ; #E DD2_WTRFL_SYNC_DIS -# 63 , 0b0 , any ; #F FORCE_FIFO_CAPTURE -} - -# --------------------------------------------------------------------------------------- -# Initial calibration sequence Config0 register default=0 sim = 0xBF2? -# -# !! Needed? Which procedure does this?? -# !! need to check if needed to be set in the initfile or not. -# -# DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0 0x016 0x8000c0160301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG22_L2 -scom 0x8000C0160301143F { # Port 0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# 48 , 0b1 , (def_is_sim) ; # ENA_WR_LEVEL -# 49 , 0b0 , (def_is_sim) ; # ENA_INITIAL_PAT_WR, for custom pattern -# 50 , 0b1 , (def_is_sim) ; # ENA_DQS_ALIGN -# 51 , 0b1 , (def_is_sim) ; # ENA_RDCLK_ALIGN -# 52 , 0b1 , (def_is_sim) ; # ENA_READ_CTR -# 53 , 0b1 , (def_is_sim) ; # ENA_WRITE_CTR -# 54 , 0b1 , (def_is_sim) ; # ENA_INITIAL_COARSE_WR -# 55 , 0b1 , (def_is_sim) ; # ENA_COARSE_RD - 56 , 0b0 , any ; # ENA_CUSTOM_RD - 57 , 0b0 , any ; # ENA_CUSTOM_WR -# 58 , 0b1 , (def_is_sim) ; # ABORT_ON_CAL_ERROR - 59 , 0b0 , any ; # ENA_DIGITAL_EYE - - # ENA_RANK_GROUP[0:3], 4 bits - 60 , 0b1 , (def_val_prg0_p0) ; # enable primary rank group 0 - 60 , 0b0 , any ; # disable primary rank group 0 - 61 , 0b1 , (def_val_prg1_p0) ; # enable primary rank group 1 - 61 , 0b0 , any ; # disable primary rank group 1 - 62 , 0b1 , (def_val_prg2_p0) ; # enable primary rank group 2 - 62 , 0b0 , any ; # disable primary rank group 2 - 63 , 0b1 , (def_val_prg3_p0) ; # enable primary rank group 3 - 63 , 0b0 , any ; # disable primary rank group 3 -} - -# DPHY01.DDRPHY_PC_INIT_CAL_CONFIG0_P1 -scom 0x8001C0160301143F { # Port 1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# 48 , 0b1 , (def_is_sim) ; # ENA_WR_LEVEL -# 49 , 0b0 , (def_is_sim) ; # ENA_INITIAL_PAT_WR, for custom pattern -# 50 , 0b1 , (def_is_sim) ; # ENA_DQS_ALIGN -# 51 , 0b1 , (def_is_sim) ; # ENA_RDCLK_ALIGN -# 52 , 0b1 , (def_is_sim) ; # ENA_READ_CTR -# 53 , 0b1 , (def_is_sim) ; # ENA_WRITE_CTR -# 54 , 0b1 , (def_is_sim) ; # ENA_INITIAL_COARSE_WR -# 55 , 0b1 , (def_is_sim) ; # ENA_COARSE_RD - 56 , 0b0 , any ; # ENA_CUSTOM_RD - 57 , 0b0 , any ; # ENA_CUSTOM_WR -# 58 , 0b1 , (def_is_sim) ; # ABORT_ON_CAL_ERROR - 59 , 0b0 , any ; # ENA_DIGITAL_EYE - # ENA_RANK_GROUP[0:3], 4 bits - 60 , 0b1 , (def_val_prg0_p1) ; # enable primary rank group 0 - 60 , 0b0 , any ; # disable primary rank group 0 - 61 , 0b1 , (def_val_prg1_p1) ; # enable primary rank group 1 - 61 , 0b0 , any ; # disable primary rank group 1 - 62 , 0b1 , (def_val_prg2_p1) ; # enable primary rank group 2 - 62 , 0b0 , any ; # disable primary rank group 2 - 63 , 0b1 , (def_val_prg3_p1) ; # enable primary rank group 3 - 63 , 0b0 , any ; # disable primary rank group 3 -} - -# --------------------------------------------------------------------------------------- -# Initial calibration sequence Config1 register default=0 -# EFF_DRAM_TRFI -# -# Controls refreshes during calibration, and regular refresh interval. -# if DDR3/4 with custom pattern then need refresh since pattern written into memory -# -# REFRESH_CONTROL { 00 = Refresh commands are only sent at start of initial calibration, -# based on the value in the .REFRESH_COUNT. field. Disables if count=0 -# 01 = Use the internal Refresh Interval timer to determine when refresh -# commands are sent; allow refreshes to occur between calibration routines. -# 10 = Reserved -# 11 = Use the internal Refresh Interval timer to determine when refresh -# commands should be sent; in addition to allowing refreshes commands to be -# issued between calibration routines, also allow refreshes to interrupt each -# calibration routine (as required). This is the recommended setting when -# refreshes are required during initial calibration. -# } -# -# DPHY01_DDRPHY_PC_INIT_CAL_CONFIG1_P0 0x017 0x8000c0170301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG23_L2 -scom 0x800(0,1)C0170301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:51 , 0b0000 , any ; # REFRESH_COUNT, num of refreshes before cal - 52:53 , 0b00 , any ; # REFRESH_CONTROL during initial calibration - 54 , 0b0 , any ; # REFRESH_ALL_RANKS, 1 issued to each rank seq. -# 55:56 , 0b00 , any ; # reserved - # REFRESH_INTERVAL, defaults to 6 if value < 6, value*256=num clks between refreshes - # ATTR_EFF_DRAM_TRFI = refresh interval in clocks -# 57:63 , 0b0000000 , (def_is_sim) ; # match dials - 57:63 , (ATTR_EFF_DRAM_TRFI >> 8) , any ; # field needs refresh/256 -} - -# --------------------------------------------------------------------------------------- -# Peroidic calibration configuration register default=0 -# -# !! Setup in mss_draminit_mc.C ?? -# -# DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0 0x00B 0x8000c00b0301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG11_L2 -scom 0x8000C00B0301143F { # Port 0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # PER_ENA_RANK_GROUP[0:3], 4 bits - 48 , 0b1 , (def_val_prg0_p0) ; # enable primary rank group 0 - 48 , 0b0 , any ; # disable primary rank group 0 - 49 , 0b1 , (def_val_prg1_p0) ; # enable primary rank group 1 - 49 , 0b0 , any ; # disable primary rank group 1 - 50 , 0b1 , (def_val_prg2_p0) ; # enable primary rank group 2 - 50 , 0b0 , any ; # disable primary rank group 2 - 51 , 0b1 , (def_val_prg3_p0) ; # enable primary rank group 3 - 51 , 0b0 , any ; # disable primary rank group 3 - - 52 , 0b1 , any ; # PER_ENA_ZCAL - 53 , 0b1 , any ; # PER_ENA_SYSCLK_ALIGN - 54 , 0b1 , any ; # ENA_PER_READ_CTR - 55 , 0b1 , any ; # ENA_PER_RDCLK_ALIGN - 56 , 0b1 , any ; # ENA_PER_DQS_ALIGN - 57:58 , 0b00 , any ; # PER_NEXT_RANK_PAIR - 59 , 0b1 , (def_FAST_SIM_PC==1) ; # FAST_SIM_PER_CNTR - 59 , 0b0 , (def_FAST_SIM_PC==0) ; # FAST_SIM_PER_CNTR - 60 , 0b0 , any ; # START_INIT_CAL - 61 , 0b0 , any ; # START_PER_CAL - 62 , 0b0 , any ; # ABORT_ON_ERR_EN - 63 , 0b0 , any ; # DD2_FIX_DIS -#63 , 0b0 , any ; # ZCAL_UPDATE_MODE -} -# DPHY01.DDRPHY_PC_PER_CAL_CONFIG_P1 -scom 0x8001C00B0301143F { # Port 1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # PER_ENA_RANK_GROUP[0:3], 4 bits - 48 , 0b1 , (def_val_prg0_p1) ; # enable primary rank group 0 - 48 , 0b0 , any ; # disable primary rank group 0 - 49 , 0b1 , (def_val_prg1_p1) ; # enable primary rank group 1 - 49 , 0b0 , any ; # disable primary rank group 1 - 50 , 0b1 , (def_val_prg2_p1) ; # enable primary rank group 2 - 50 , 0b0 , any ; # disable primary rank group 2 - 51 , 0b1 , (def_val_prg3_p1) ; # enable primary rank group 3 - 51 , 0b0 , any ; # disable primary rank group 3 - - 52 , 0b1 , any ; # PER_ENA_ZCAL - 53 , 0b1 , any ; # PER_ENA_SYSCLK_ALIGN - 54 , 0b1 , any ; # ENA_PER_RDCLK_ALIGN - 55 , 0b1 , any ; # ENA_PER_DQS_ALIGN - 56 , 0b1 , any ; # ENA_PER_READ_CTR - 57:58 , 0b00 , any ; # PER_NEXT_RANK_PAIR - 59 , 0b1 , (def_FAST_SIM_PC==1) ; # FAST_SIM_PER_CNTR - 59 , 0b0 , (def_FAST_SIM_PC==0) ; # FAST_SIM_PER_CNTR - 60 , 0b0 , any ; # START_INIT_CAL - 61 , 0b0 , any ; # START_PER_CAL - 62 , 0b0 , any ; # ABORT_ON_ERR_EN - 63 , 0b0 , any ; # ZCAL_UPDATE_MODE -} - -# --------------------------------------------------------------------------------------- -# Peroidic calibration reload value register default=0 -# -# Periodic calibration request enable is also in this register. -# The value in this register is loaded into the PC Periodic Base Counter 0(PBC0) when it -# rolls over. Periodic Base Counter[1:0] together form a 32-bit timer where periodic -# base counter 1 is the most significant 16 bits and periodic base counter 0 is the least -# significant 16 bits. The memcal interval is 48 bits formed by concatenating the -# periodic calibration timer(PCT) with the periodic base counter[1:0] where the PCT is -# the most significant 16 bits and the PBC[1:0] is the least significant 32 bits. -# -# Interval = { PCT, PBC1, PBC0 } = -# (periodic_timer_reload_value -1) * (2^16 -1) * ((periodic_reload_value0 * 2) + 1) -# -# Note if FAST_SIM_PER_CNTR = 1, 2^16 becomes 2^8 -# -# DPHY01_DDRPHY_PC_RELOAD_VALUE0_P0 0x005 0x8000c0050301143f -scom 0x800(0,1)C0050301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48 , 0b0 , any ; # PERIODIC_CAL_REQ_EN - 49:63 , 0x0001 , any ; # PERIODIC_RELOAD_VALUE0 -} - -# --------------------------------------------------------------------------------------- -# DPHY01 PC Periodic Calibration Timer Reload Value default=0 -# -# Loaded into PC Periodic Calibration Timer register. -# -# memcal interval = ATTR_EFF_MEMCAL_INTERVAL # u32 value in clocks -# periodic_reload_value0 = 1; -# -# Anuwat says should be ~114ms = 91200000 clks @ 1600MHz -# -# if FAST_SIM_PER_CNTR = 0, -# memcal interval = (periodic_timer_reload_value -1) * (2^16 -1) * ((periodic_reload_value0 * 2) + 1) -# periodic_timer_reload_value = ((ATTR_EFF_MEMCAL_INTERVAL / ((2^16 -1) * ((periodic_reload_value0 * 2) + 1))) + 1) -# periodic_timer_reload_value = ((ATTR_EFF_MEMCAL_INTERVAL / (65535 * ((1 * 2) + 1))) + 1) -# periodic_timer_reload_value = ((ATTR_EFF_MEMCAL_INTERVAL / (65535 * 3)) + 1) -# periodic_timer_reload_value = ((ATTR_EFF_MEMCAL_INTERVAL / 196605) + 1) -# -# FAST_SIM_PER_CNTR=1, periodic_timer_reload_value = ATTR_EFF_MEMCAL_INTERVAL / 765 -# -# DPHY01_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE_P0 0x008 0x8000c0080301143f -# PHYE.PHYX.SYNTHX.D3SIDEA.PCX.REG08_L2 -scom 0x800(0,1)c0080301143f { # _P[0:1] - bits , scom_data , expr ; # must be >= 2... -# 0:47 , 0x000000000000 , any ; # reserved -# 48:63 , 0x0000 , (def_is_sim) ; # match dials - 48:63 , ((ATTR_EFF_MEMCAL_INTERVAL/196605)+1) , (def_FAST_SIM_PC==0) ; # FAST_SIM_PER_CNTR=0 - 48:63 , ((ATTR_EFF_MEMCAL_INTERVAL/765)+1) , (def_FAST_SIM_PC==1) ; # FAST_SIM_PER_CNTR=1 -# 48:63 , 0x01D1 , any ; # 464 = 114ms @ 1600MHz -} - - -# --------------------------------------------------------------------------------------- -# Periodic ZQcal configuration register default=0 -# -# DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P0 0x00F 0x8000c00f0301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG15_L2 -scom 0x8000C00F0301143F { # Port0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # PER_ZCAL_ENA_RANK for ranks [0:7] - 48:51 , 0b1000 , (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] == 1) ; # dimm0 = 1 rank - 48:51 , 0b1100 , (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] == 2) ; # dimm0 = 2 rank - 48:51 , 0b1111 , (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] >= 4) ; # dimm0 >= 4 rank dimm - 48:51 , 0b0000 , any ; # dimm0 = no valid ranks - # DIMM1 - 52:55 , 0b1000 , (ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] == 1) ; # dimm1 = 1 rank - 52:55 , 0b1100 , (ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] == 2) ; # dimm1 = 2 rank - # dimm1 = 4 rank or dimm0 > 4 ranks - 52:55 , 0b1111 , ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] == 4) || (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] > 4)) ; - 52:55 , 0b0000 , any ; # no valid ranks - # PER_ZCAL_NEXT_RANK, indicates next rank to be cal'd - 56:58 , 0b000 , any ; - # START_PER_ZCAL - 59 , 0b0 , any ; -# 60:63 , 0x0 , any ; reserved -} -scom 0x8001C00F0301143F { # Port1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # PER_ZCAL_ENA_RANK for ranks [0:7] - 48:51 , 0b1000 , (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] == 1) ; # dimm0 = 1 rank - 48:51 , 0b1100 , (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] == 2) ; # dimm0 = 2 rank - 48:51 , 0b1111 , (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] >= 4) ; # dimm0 >= 4 rank dimm - 48:51 , 0b0000 , any ; # dimm0 = no valid ranks - # DIMM1 - 52:55 , 0b1000 , (ATTR_EFF_NUM_RANKS_PER_DIMM[1][1] == 1) ; # dimm1 = 1 rank - 52:55 , 0b1100 , (ATTR_EFF_NUM_RANKS_PER_DIMM[1][1] == 2) ; # dimm1 = 2 rank - # dimm1 = 4 rank or dimm0 > 4 ranks - 52:55 , 0b1111 , ((ATTR_EFF_NUM_RANKS_PER_DIMM[1][1] == 4) || (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] > 4)) ; - 52:55 , 0b0000 , any ; # no valid ranks - # PER_ZCAL_NEXT_RANK, indicates next rank to be cal'd - 56:58 , 0b000 , any ; - # START_PER_ZCAL - 59 , 0b0 , any ; -# 60:63 , 0x0 , any ; reserved -} - -# --------------------------------------------------------------------------------------- -# Peroidic ZQcal reload value register default=0 -# -# Value from this register is loaded into the PERIODIC_ZCAL_TIMER. -# (2^16 - 1) * ((PERIODIC_RELOAD_VALUE0 * 2) + 1) * (PERIODIC_ZCAL_TIMER_RELOAD_VALUE - 1) -# if FAST_SIM_PER_CNTR is set, it becomes 2^8 instead of 2^16. -# -# Note: calibration is performed on a single rank per request. -# -# Anuwat says should be ~11ms = 8800000 clks @ 1600MHz -# -# 65535 * ((PERIODIC_RELOAD_VALUE0*2)+1) * (zcal_timer_reload_val - 1) -# (ATTR_EFF_ZQCAL_INTERVAL/(65535*(2prv+1)))+1 -# zcq_int=88000000 -# -# DPHY01_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE_P0 0x00A 0x8000c0090301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG09_L2 -scom 0x8000c0090301143f { - bits , scom_data , expr ; # must be >= 2... -# 0:47 , 0x000000000000 , any ; # reserved - 48:63 , ((ATTR_EFF_ZQCAL_INTERVAL/196605)+1) , (def_FAST_SIM_PC==0) ; # FAST_SIM_PER_CNTR=0 - 48:63 , ((ATTR_EFF_ZQCAL_INTERVAL/765)+1) , (def_FAST_SIM_PC==1) ; # FAST_SIM_PER_CNTR=1 -# 48:63 , 0x002E , any ; # 46 = 11ms @ 1600MHz -} - -# --------------------------------------------------------------------------------------- -# DPHY01 PC Power Down 1 default=0 !! need to set this? -# -# This register provides control of the power down modes of the DDR PHY. -# -# DPHY01_DDRPHY_PC_POWERDOWN_1_P0 0x010 0x8000c0100301143f -# -# asking Ken... - -# --------------------------------------------------------------------------------------- -# PC Rank Group Register set in the mss_draminit procedure -# -# This register provides control of mirrored address bits. -# -# DPHY01_DDRPHY_PC_RANK_GROUP_P0 0x11 0x8000c0110301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG17_L2 -#scom 0x8000c0110301143f { -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved -# 48 , 0b0 , any ; # ADDR_MIRROR_RP0_PRI -# 49 , 0b0 , any ; # ADDR_MIRROR_RP0_SEC -# 50 , 0b0 , any ; # ADDR_MIRROR_RP1_PRI -# 51 , 0b0 , any ; # ADDR_MIRROR_RP1_SEC -# 52 , 0b0 , any ; # ADDR_MIRROR_RP2_PRI -# 53 , 0b0 , any ; # ADDR_MIRROR_RP2_SEC -# 54 , 0b0 , any ; # ADDR_MIRROR_RP3_PRI -# 55 , 0b0 , any ; # ADDR_MIRROR_RP3_SEC -# 56:57 , 0b0 , any ; # RANK_GROUPING # reserved -# 58 , 0b0 , any ; # ADDR_MIRROR_A3_A4 -# 59 , 0b0 , any ; # ADDR_MIRROR_A5_A6 -# 60 , 0b0 , any ; # ADDR_MIRROR_A7_A8 -# 61 , 0b0 , any ; # ADDR_MIRROR_A11_A13 -# 62 , 0b0 , any ; # ADDR_MIRROR_BA0_BA1 -# 63 , 0b0 , any ; # ADDR_MIRROR_BG0_BG1 -#} -# --------------------------------------------------------------------------------------- -# PC Rank Group Extension Register -# -# DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0 0x035 0x8000c0350301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG53_L2 -#scom 0x8000c0350301143f { -# bits , scom_data , expr ; -## 0:47 , 0x000000000000, any ; # reserved -# 48 , 0b0 , any ; # ADDR_MIRROR_RP0_TER -# 49 , 0b0 , any ; # ADDR_MIRROR_RP0_QUA -# 50 , 0b0 , any ; # ADDR_MIRROR_RP1_TER -# 51 , 0b0 , any ; # ADDR_MIRROR_RP1_QUA -# 52 , 0b0 , any ; # ADDR_MIRROR_RP2_TER -# 53 , 0b0 , any ; # ADDR_MIRROR_RP2_QUA -# 54 , 0b0 , any ; # ADDR_MIRROR_RP3_TER -# 55 , 0b0 , any ; # ADDR_MIRROR_RP3_QUA -# 56:63 , 0x00 , any ; # reserved -#} - -# --------------------------------------------------------------------------------------- -# Rank pair 0 configuration register default=0 -# -# Configures rank pairing for primary & secondary ranks [0:1]. -# -# !! need to zero out 3 bits when invalid? shouldn't invalid bit take care of it? -# -# reg port -# ATTR_EFF_PRIMARY_RANK_GROUP{0:3}[0:1] CS, 255=invalid -# ATTR_EFF_SECONDARY_RANK_GROUP{0:3}[0:1] CS, 255=invalid -# -# DPHY01_DDRPHY_PC_RANK_PAIR0_P0 0x002 0x8000c0020301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG02_L2 -scom 0x8000C0020301143F { - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved -# possible way to simplify... -# 48:51 , ((ATTR_EFF_PRIMARY_RANK_GROUP0[0]<<1) | 0x1) , (def_val_prg1_p1) ; # P1_RP1_PRI = 9 -# 48:51 , 0b0000 , any ; # P1_RP1_PRI invalid - 48:50 , (ATTR_EFF_PRIMARY_RANK_GROUP0[0]) , (def_val_prg0_p0) ; # P0_RP0_PRI - 48:50 , 0b000 , any ; # P0_RP0_PRI - 51 , 0b1 , (def_val_prg0_p0) ; # P0_RP0_PRI_V - 51 , 0b0 , any ; # P0_RP0_PRI_V invalid - 52:54 , (ATTR_EFF_SECONDARY_RANK_GROUP0[0]) , (def_val_srg0_p0) ; # P0_RP0_SEC - 52:54 , 0b000 , any ; # P0_RP0_SEC invalid - 55 , 0b1 , (def_val_srg0_p0) ; # P0_RP0_SEC_V - 55 , 0b0 , any ; # P0_RP0_SEC_V invalid - 56:58 , (ATTR_EFF_PRIMARY_RANK_GROUP1[0]) , (def_val_prg1_p0) ; # P0_RP1_PRI - 56:58 , 0b000 , any ; # P0_RP1_PRI invalid - 59 , 0b1 , (def_val_prg1_p0) ; # P0_RP1_PRI_V - 59 , 0b0 , any ; # P0_RP1_PRI_V invalid - 60:62 , (ATTR_EFF_SECONDARY_RANK_GROUP1[0]) , (def_val_srg1_p0) ; # P0_RP1_SEC - 60:62 , 0b000 , any ; # P0_RP1_SEC invalid - 63 , 0b1 , (def_val_srg1_p0) ; # P0_RP1_SEC_V - 63 , 0b0 , any ; # P0_RP1_SEC_V invalid -} - -# -=-=-=-=-=-=-=- PC_RANK_PAIR0 Port 1 -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= -# DPHY01.DDRPHY_PC_RANK_PAIR0_P1 -scom 0x8001C0020301143F { - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:50 , (ATTR_EFF_PRIMARY_RANK_GROUP0[1]) , (def_val_prg0_p1) ; # P1_RP0_PRI - 48:50 , 0b000 , any ; # P1_RP0_PRI invalid - 51 , 0b1 , (def_val_prg0_p1) ; # P1_RP0_PRI_V - 51 , 0b0 , any ; # P1_RP0_PRI_V invalid - 52:54 , (ATTR_EFF_SECONDARY_RANK_GROUP0[1]) , (def_val_srg0_p1) ; # P1_RP0_SEC - 52:54 , 0b000 , any ; # P1_RP0_SEC invalid - 55 , 0b1 , (def_val_srg0_p1) ; # P1_RP0_SEC_V - 55 , 0b0 , any ; # P1_RP0_SEC_V invalid - 56:58 , (ATTR_EFF_PRIMARY_RANK_GROUP1[1]) , (def_val_prg1_p1) ; # P1_RP1_PRI - 56:58 , 0b000 , any ; # P1_RP1_PRI invalid - 59 , 0b1 , (def_val_prg1_p1) ; # P1_RP1_PRI_V - 59 , 0b0 , any ; # P1_RP1_PRI_V invalid - 60:62 , (ATTR_EFF_SECONDARY_RANK_GROUP1[1]) , (def_val_srg1_p1) ; # P1_RP1_SEC - 60:62 , 0b000 , any ; # P1_RP1_SEC invalid - 63 , 0b1 , (def_val_srg1_p1) ; # P1_RP1_SEC_V - 63 , 0b0 , any ; # P1_RP1_SEC_V invalid -} - -# --------------------------------------------------------------------------------------- -# Rank pair 1 configuration register default=0 -# -# Configures rank pairing for primary & secondary ranks [2:3]. -# -# reg port -# ATTR_EFF_PRIMARY_RANK_GROUP{0:3}[0:1] CS, 255=invalid -# ATTR_EFF_SECONDARY_RANK_GROUP{0:3}[0:1] CS, 255=invalid -# -# DPHY01.DDRPHY_PC_RANK_PAIR1_P0 -scom 0x8000C0030301143F { - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:50 , (ATTR_EFF_PRIMARY_RANK_GROUP2[0]) , (def_val_prg2_p0) ; # P0_RP2_PRI - 48:50 , 0b000 , any ; # P0_RP2_PRI invalid - 51 , 0b1 , (def_val_prg2_p0) ; # P0_RP2_PRI_V - 51 , 0b0 , any ; # P0_RP2_PRI_V invalid - 52:54 , (ATTR_EFF_SECONDARY_RANK_GROUP2[0]) , (def_val_srg2_p0) ; # P0_RP2_SEC - 52:54 , 0b000 , any ; # P0_RP2_SEC invalid - 55 , 0b1 , (def_val_srg2_p0) ; # P0_RP2_SEC_V - 55 , 0b0 , any ; # P0_RP2_SEC_V invalid - 56:58 , (ATTR_EFF_PRIMARY_RANK_GROUP3[0]) , (def_val_prg3_p0) ; # P0_RP3_PRI - 56:58 , 0b000 , any ; # P0_RP3_PRI invalid - 59 , 0b1 , (def_val_prg3_p0) ; # P0_RP3_PRI_V - 59 , 0b0 , any ; # P0_RP3_PRI_V invalid - 60:62 , (ATTR_EFF_SECONDARY_RANK_GROUP3[0]) , (def_val_srg3_p0) ; # P0_RP3_SEC - 60:62 , 0b000 , any ; # P0_RP3_SEC invalid - 63 , 0b1 , (def_val_srg3_p0) ; # P0_RP3_SEC_V - 63 , 0b0 , any ; # P0_RP3_SEC_V invalid -} - -# -=-=-=-=-=-=-=- PC_RANK_PAIR1 Port 1 -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= -# DPHY01.DDRPHY_PC_RANK_PAIR1_P1 -scom 0x8001C0030301143F { - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:50 , (ATTR_EFF_PRIMARY_RANK_GROUP2[1]) , (def_val_prg2_p1) ; # P1_RP2_PRI - 48:50 , 0b000 , any ; # P1_RP2_PRI invalid - 51 , 0b1 , (def_val_prg2_p1) ; # P1_RP2_PRI_V - 51 , 0b0 , any ; # P1_RP2_PRI_V invalid - 52:54 , (ATTR_EFF_SECONDARY_RANK_GROUP2[1]) , (def_val_srg2_p1) ; # P1_RP2_SEC - 52:54 , 0b000 , any ; # P1_RP2_SEC invalid - 55 , 0b1 , (def_val_srg2_p1) ; # P1_RP2_SEC_V - 55 , 0b0 , any ; # P1_RP2_SEC_V invalid - 56:58 , (ATTR_EFF_PRIMARY_RANK_GROUP3[1]) , (def_val_prg3_p1) ; # P1_RP3_PRI - 56:58 , 0b000 , any ; # P1_RP3_PRI invalid - 59 , 0b1 , (def_val_prg3_p1) ; # P1_RP3_PRI_V - 59 , 0b0 , any ; # P1_RP3_PRI_V invalid - 60:62 , (ATTR_EFF_SECONDARY_RANK_GROUP3[1]) , (def_val_srg3_p1) ; # P1_RP3_SEC - 60:62 , 0b000 , any ; # P1_RP3_SEC invalid - 63 , 0b1 , (def_val_srg3_p1) ; # P1_RP3_SEC_V - 63 , 0b0 , any ; # P1_RP3_SEC_V invalid -} - -# --------------------------------------------------------------------------------------- -# Rank pair 2 configuration register default=0 -# -# Configures rank pairing for tertiary & quaternary ranks [0:1]. -# -# reg port -# ATTR_EFF_TERTIARY_RANK_GROUP{0:3}[0:1] CS, 255=invalid -# ATTR_EFF_QUATERNARY_RANK_GROUP{0:3}[0:1] CS, 255=invalid -# -# DPHY01_DDRPHY_PC_RANK_PAIR2_P0 0x030 0x8000c0300301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG48_L2 -scom 0x8000c0300301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:50 , (ATTR_EFF_TERTIARY_RANK_GROUP0[0]) , (def_val_trg0_p0) ; # P0_RP0_TER - 48:50 , 0b000 , any ; # P0_RP0_TER invalid - 51 , 0b1 , (def_val_trg0_p0) ; # P0_RP0_TER_V - 51 , 0b0 , any ; # P0_RP0_TER_V invalid - 52:54 , (ATTR_EFF_QUATERNARY_RANK_GROUP0[0]), (def_val_qrg0_p0) ; # P0_RP0_QUA - 52:54 , 0b000 , any ; # P0_RP0_SEC invalid - 55 , 0b1 , (def_val_qrg0_p0) ; # P0_RP0_QUA_V - 55 , 0b0 , any ; # P0_RP0_QUA_V invalid - 56:58 , (ATTR_EFF_TERTIARY_RANK_GROUP1[0]) , (def_val_trg1_p0) ; # P0_RP1_TER - 56:58 , 0b000 , any ; # P0_RP1_TER invalid - 59 , 0b1 , (def_val_trg1_p0) ; # P0_RP1_TER_V - 59 , 0b0 , any ; # P0_RP1_TER_V invalid - 60:62 , (ATTR_EFF_QUATERNARY_RANK_GROUP1[0]), (def_val_qrg1_p0) ; # P0_RP1_QUA - 60:62 , 0b000 , any ; # P0_RP1_QUA invalid - 63 , 0b1 , (def_val_qrg1_p0) ; # P0_RP1_QUA_V - 63 , 0b0 , any ; # P0_RP1_QUA_V invalid -} -# -# -=-=-=-=-=-=-=- PC_RANK_PAIR2 Port 1 -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= -# DPHY01.DDRPHY_PC_RANK_PAIR2_P1 -scom 0x8001c0300301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:50 , (ATTR_EFF_TERTIARY_RANK_GROUP0[1]) , (def_val_trg0_p1) ; # P1_RP0_TER - 48:50 , 0b000 , any ; # P1_RP0_TER invalid - 51 , 0b1 , (def_val_trg0_p1) ; # P1_RP0_TER_V - 51 , 0b0 , any ; # P1_RP0_TER_V invalid - 52:54 , (ATTR_EFF_QUATERNARY_RANK_GROUP0[1]), (def_val_qrg0_p1) ; # P1_RP0_QUA - 52:54 , 0b000 , any ; # P1_RP0_SEC invalid - 55 , 0b1 , (def_val_qrg0_p1) ; # P1_RP0_QUA_V - 55 , 0b0 , any ; # P1_RP0_QUA_V invalid - 56:58 , (ATTR_EFF_TERTIARY_RANK_GROUP1[1]) , (def_val_trg1_p1) ; # P1_RP1_TER - 56:58 , 0b000 , any ; # P1_RP1_TER invalid - 59 , 0b1 , (def_val_trg1_p1) ; # P1_RP1_TER_V - 59 , 0b0 , any ; # P1_RP1_TER_V invalid - 60:62 , (ATTR_EFF_QUATERNARY_RANK_GROUP1[1]), (def_val_qrg1_p1) ; # P1_RP1_QUA - 60:62 , 0b000 , any ; # P1_RP1_QUA invalid - 63 , 0b1 , (def_val_qrg1_p1) ; # P1_RP1_QUA_V - 63 , 0b0 , any ; # P1_RP1_QUA_V invalid -} -# -# --------------------------------------------------------------------------------------- -# Rank pair 3 configuration register default=0 -# -# Configures rank pairing for tertiary & quaternary ranks [2:3]. -# -# reg port -# ATTR_EFF_TERTIARY_RANK_GROUP{0:3}[0:1] CS, 255=invalid -# ATTR_EFF_QUATERNARY_RANK_GROUP{0:3}[0:1] CS, 255=invalid -# -# DPHY01_DDRPHY_PC_RANK_PAIR3_P0 0x031 0x8000c0310301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.PCX.REG49_L2 -scom 0x8000c0310301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:50 , (ATTR_EFF_TERTIARY_RANK_GROUP2[0]) , (def_val_trg2_p0) ; # P0_RP2_TER - 48:50 , 0b000 , any ; # P0_RP2_TER invalid - 51 , 0b1 , (def_val_trg2_p0) ; # P0_RP2_TER_V - 51 , 0b0 , any ; # P0_RP2_TER_V invalid - 52:54 , (ATTR_EFF_QUATERNARY_RANK_GROUP2[0]), (def_val_qrg2_p0) ; # P0_RP2_QUA - 52:54 , 0b000 , any ; # P0_RP0_QUA invalid - 55 , 0b1 , (def_val_qrg2_p0) ; # P0_RP2_QUA_V - 55 , 0b0 , any ; # P0_RP2_QUA_V invalid - 56:58 , (ATTR_EFF_TERTIARY_RANK_GROUP3[0]) , (def_val_trg3_p0) ; # P0_RP3_TER - 56:58 , 0b000 , any ; # P0_RP3_TER invalid - 59 , 0b1 , (def_val_trg3_p0) ; # P0_RP3_TER_V - 59 , 0b0 , any ; # P0_RP3_TER_V invalid - 60:62 , (ATTR_EFF_QUATERNARY_RANK_GROUP3[0]), (def_val_qrg3_p0) ; # P0_RP3_QUA - 60:62 , 0b000 , any ; # P0_RP3_QUA invalid - 63 , 0b1 , (def_val_qrg3_p0) ; # P0_RP3_QUA_V - 63 , 0b0 , any ; # P0_RP3_QUA_V invalid -} -# -# -=-=-=-=-=-=-=- PC_RANK_PAIR3 Port 1 -=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= -# DPHY01.DDRPHY_PC_RANK_PAIR3_P1 -scom 0x8001c0310301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:50 , (ATTR_EFF_TERTIARY_RANK_GROUP2[1]) , (def_val_trg2_p1) ; # P1_RP2_TER - 48:50 , 0b000 , any ; # P1_RP2_TER invalid - 51 , 0b1 , (def_val_trg2_p1) ; # P1_RP2_TER_V - 51 , 0b0 , any ; # P1_RP2_TER_V invalid - 52:54 , (ATTR_EFF_QUATERNARY_RANK_GROUP2[1]), (def_val_qrg2_p1) ; # P1_RP2_QUA - 52:54 , 0b000 , any ; # P1_RP2_QUA invalid - 55 , 0b1 , (def_val_qrg2_p1) ; # P1_RP2_QUA_V - 55 , 0b0 , any ; # P1_RP2_QUA_V invalid - 56:58 , (ATTR_EFF_TERTIARY_RANK_GROUP3[1]) , (def_val_trg3_p1) ; # P1_RP3_TER - 56:58 , 0b000 , any ; # P1_RP3_TER invalid - 59 , 0b1 , (def_val_trg3_p1) ; # P1_RP3_TER_V - 59 , 0b0 , any ; # P1_RP3_TER_V invalid - 60:62 , (ATTR_EFF_QUATERNARY_RANK_GROUP3[1]), (def_val_qrg3_p1) ; # P1_RP3_QUA - 60:62 , 0b000 , any ; # P1_RP3_QUA invalid - 63 , 0b1 , (def_val_qrg3_p1) ; # P1_RP3_QUA_V - 63 , 0b0 , any ; # P1_RP3_QUA_V invalid -} - -# --------------------------------------------------------------------------------------- -# Read Control Configuration 0 default=0x0002 -# -# DPHY01.DDRPHY_RC_CONFIG0_P0 -# DPHY01.DDRPHY_RC_CONFIG0_P1 -# -# num of tCK cycles = 300 + [(PER_REPEAT_COUNT + 1) * 600] -# -# DPHY01_DDRPHY_RC_CONFIG0_P0 0x000 0x8000c8000301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.RCX.RC_CONFIG0_L2 -scom 0x8000C8000301143F { # _P0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # - # System_Delay = ( ( (ADR_DELAY - 64) + - # {wire delay from the PHY memory clock output to the DRAM module converted to units of 1/128th of a MEMINTCLKO clock cycle} + - # {delay of DQS at the memory module pin relative to memory clock at the memory module pin introduced by the memory module - # (that is, tDQSCK) converted to units of 1/128th of a MEMINTCLKO clock cycle} + - # {wire delay from the DRAM DQS output to the PHY converted to units of 1/128th of a MEMINTCLKO clock cycle}) / 128) + - # {number of pipeline stages in the addr/cmd path} + - # {number of pipeline stages in the read data path} - # - # min GPO = 5 + max(rndUp(System_delay)) - RLO + ADVANCE_RD_VALID + SPAM_EN - # max GPO = 11 if in 2:1, 13 if in 4:1 -# 48:51 , 0b0111 , (def_is_lrdimm) ; # GLOBAL_PHY_OFFSET LRDIMM set to 7 # need to review LR settings - 48:51 , (ATTR_VPD_GPO[0]), any ; # GLOBAL_PHY_OFFSET (GPO), based on attribute now -# 48:51 , 0b0101 , any ; # GLOBAL_PHY_OFFSET (GPO), ideally 2:1 max=11, 4:1 max=13 - 52 , 0b0 , any ; # ADVANCE_RD_VALID ask Yuen - 53 , 0b0 , any ; # PER_DUTY_CYCLE_SW, 0=rd cmds 50% duty cycle during per.cal, 1=continuously - 54:56 , 0b000 , any ; # NUM_PERIODIC_CAL, (value+1)=num bits per peridic cal - 57 , 0b0 , any ; # SINGLE_BIT_MPR_RP0 - 58 , 0b0 , any ; # SINGLE_BIT_MPR_RP1 - 59 , 0b0 , any ; # SINGLE_BIT_MPR_RP2 - 60 , 0b0 , any ; # SINGLE_BIT_MPR_RP3 - 61 , 0b0 , any ; # ALIGN_ON_EVEN_CYCLES -# !! switched to '1' to match SIM - 62 , 0b1 , any ; # PERFORM_RDCLK_ALIGN - 63 , 0b0 , any ; # STAGGERED_PATTERN # for DDR4, 0=serial, 1=staggered -} -scom 0x8001C8000301143F { # _P1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # - # System_Delay = ( ( (ADR_DELAY - 64) + - # {wire delay from the PHY memory clock output to the DRAM module converted to units of 1/128th of a MEMINTCLKO clock cycle} + - # {delay of DQS at the memory module pin relative to memory clock at the memory module pin introduced by the memory module - # (that is, tDQSCK) converted to units of 1/128th of a MEMINTCLKO clock cycle} + - # {wire delay from the DRAM DQS output to the PHY converted to units of 1/128th of a MEMINTCLKO clock cycle}) / 128) + - # {number of pipeline stages in the addr/cmd path} + - # {number of pipeline stages in the read data path} - # - # min GPO = 5 + max(rndUp(System_delay)) - RLO + ADVANCE_RD_VALID + SPAM_EN - # max GPO = 11 if in 2:1, 13 if in 4:1 -# 48:51 , 0b0111 , (def_is_lrdimm) ; # GLOBAL_PHY_OFFSET LRDIMM set to 7 - 48:51 , (ATTR_VPD_GPO[1]), any ; # GLOBAL_PHY_OFFSET (GPO), based on attribute now -# 48:51 , 0b0101 , any ; # GLOBAL_PHY_OFFSET (GPO), ideally 2:1 max=11, 4:1 max=13 - 52 , 0b0 , any ; # ADVANCE_RD_VALID ask Yuen - 53 , 0b0 , any ; # PER_DUTY_CYCLE_SW, 0=rd cmds 50% duty cycle during per.cal, 1=continuously - 54:56 , 0b000 , any ; # NUM_PERIODIC_CAL, (value+1)=num bits per peridic cal - 57 , 0b0 , any ; # SINGLE_BIT_MPR_RP0 - 58 , 0b0 , any ; # SINGLE_BIT_MPR_RP1 - 59 , 0b0 , any ; # SINGLE_BIT_MPR_RP2 - 60 , 0b0 , any ; # SINGLE_BIT_MPR_RP3 - 61 , 0b0 , any ; # ALIGN_ON_EVEN_CYCLES -# !! switched to '1' to match SIM - 62 , 0b1 , any ; # PERFORM_RDCLK_ALIGN - 63 , 0b0 , any ; # STAGGERED_PATTERN # for DDR4, 0=serial, 1=staggered -} - -# --------------------------------------------------------------------------------------- -# Read Control Configuration 1 default=0x0000 -# -# DPHY01.DDRPHY_RC_CONFIG1_P0 -# DPHY01.DDRPHY_RC_CONFIG1_P1 -# -# DPHY01_DDRPHY_RC_CONFIG1_P0 0x001 0x8000c8010301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.RCX.ITERATION_COUNT_L2 -scom 0x800(0,1)C8010301143F { # _P[0:1] - bits , scom_data ; -# 0:47 , 0x000000000000 ; # reserved - 48:61 , 0b00000000000000 ; # OUTER_LOOP_CNT -# 62:63 , 0b00 ; # reserved -} - -# --------------------------------------------------------------------------------------- -# Read Control Configuration 2 default=0x4008 -# -# DPHY01.DDRPHY_RC_CONFIG2_P0 -# DPHY01.DDRPHY_RC_CONFIG2_P1 -# -# DPHY01_DDRPHY_RC_CONFIG2_P0 0x002 0x8000c8020301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.RCX.RC_CONFIG2_L2 -scom 0x800(0,1)C8020301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# 48:52 , 0b00000 , (def_is_sim) ; # CONSEQ_PASS sim value - 48:52 , 0b01000 , (def_is_bl8) ; # CONSEQ_PASS 8 from SWyatt -# 48:52 , 0b00110 , (def_is_bl8) ; # CONSEQ_PASS 6 min for BL8 -# 48:52 , 0b01100 , any ; # CONSEQ_PASS 12 min for BL4, or OTF - 48:52 , 0b01111 , any ; # CONSEQ_PASS 16 min for BL4, or OTF -# 53:56 , 0b0000 , any ; # reserved - # 00 = compare beats 1:4, 01 = compare beats 3:6, 10 = compare beats 5:8, 11 = compare all 8 beats -# 57:58 , 0b00 , (def_is_sim) ; # BURST_WINDOW, compare beats 1-4 (legacy, if SIM) - 57:58 , 0b11 , any ; # BURST_WINDOW, compare all 8 beats (AS recommended) - 59 , 0b0 , any ; # ALLOW_RD_FIFO_AUTO_RESET -# 60:63 , 0b0000 , any ; # reserved -} - -# --------------------------------------------------------------------------------------- -# Read Control Configuration 3 default=0x0800 -# -# DPHY01.DDRPHY_RC_CONFIG3_P0 -# DPHY01.DDRPHY_RC_CONFIG3_P1 -# -# DPHY01_DDRPHY_RC_CONFIG3_P0 0x007 0x8000c8070301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.RCX.RC_CONFIG3_L2(0:6),PHYW.PHYX.SYNTHX.D3SIDEA.RCX.DQSDQ_ENUM_COUNT_L2 -scom 0x800(0,1)C8070301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # FINE_CAL_STEP_SIZE (000=1/128, 001=1/64, 010=3/128, 011=1/32...) - 48:50 , 0b000 , any ; # 1/128 - - # COARSE_CAL_STEP_SIZE same as above but 8-16 reserved, but when DIGITAL_EYE_EN=1 - # in DFT_DIG_EYE register, 51:52 reserved, 53=DIGEYE_16_NOT_1, 54= DIGEYE_REFRESH - 51:54 , 0b1010 , (def_is_sim) ; # COARSE_CAL_STEP_SIZE # old=4=5/128 (5/18) - 51:54 , 0b0000 , any ; # COARSE_CAL_STEP_SIZE = 1/128 - 55:56 , 0b00 , any ; # DQ_SEL_QUAD - 57:59 , 0b000 , any ; # DQ_SEL_LANE -# 60:63 , 0b0000 , any ; # reserved -} - -# --------------------------------------------------------------------------------------- -# RC Periodic Register default=???? !! need to set? -# -# !! can't find address in db. -# - -# --------------------------------------------------------------------------------------- -# SEQ Configuration 0 Register default=0 -# -# DPHY01.DDRPHY_SEQ_CONFIG0_P0 -# DPHY01.DDRPHY_SEQ_CONFIG0_P1 -# -# DPHY01_DDRPHY_SEQ_CONFIG0_P0 CTL 0x002 0x8000c4020301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MPR_PATTERN_DATA_L2 -scom 0x800(0,1)C4020301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48 , 0b0 , any ; # MPR_PATTERN_BIT -# # TWO_CYCLE_ADDR_EN - 49 , 0b1 , (def_2N_mode) ; # enable 2 cycle addr mode - 49 , 0b0 , any ; # disable 2 cycle addr mode - - 50:53 , 0b0000 , any ; # MR_MASK_EN (mode register[0:3] mask during calibration) - 54 , 0b0 , any ; # DELAYED_PARITY (only for DDR4, DDR3 don't care) - 55 , 0b0 , any ; # LRDIMM_CONTEXT - 56 , 0b0 , any ; # FORCE_RESERVED # for DDR4 - 57 , 0b0 , any ; # HALT_ROTATION, for DDR4 staggered pattern - 58 , 0b0 , any ; # FORCE_MPR -# 59:63 , 0b00000 , any ; # reserved -} - -# --------------------------------------------------------------------------------------- -# SEQ Reserved Address 0 default=0 !! need to set for DDR3 init due to custom -# pattern during initialization. -# -# Attributes Read/Write via programming interface. Row address Lower -# -# Description -# This register contains the reserved address to be used during calibration algorithms in the -# memory devices. This address is used within all primary ranks of rank pairs. The exact mapping -# of these register bits to physical ADR pins is protocol dependant. -# -# Each read/write access by the DDR PHY during calibration algorithms receives/sends eight beats -# of data starting at the address defined by the SEQ Reserved Address registers. Since RLDRAM2 and -# RLDRAM3 support a burst length of 4, the DDR PHY sends multiple back to back commands to receive -# and send eight beats of data. That is, for BL = 4 the DDR PHY sends two commands back to back. -# -# Row/Column addressing: -# RLDRAM2/3 Addressing with BL = 4: The first command is to address as in SEQ Reserved Address -# Registers. The second command is to the row and column address increments by 4. Some calibration -# algorithms require multiple reads with burst length 8 to be performed back to back to generate read -# data bursts greater than 8 beats. To achieve this in RLDRAM2 and RLDRAM3 the consecutive reads must -# be to different banks. Therefore, in RLDRAM2 and RLDRAM3 the reserved address defined in the SEQ -# Reserved Address Registers is used in every bank. -# -# Bank Addressing: -# Single read or write command: The bank address is defined by the SEQ Reserved Address Registers. -# Series of multiple back to back read or write commands: The first read/write is to the bank address -# defined by the SEQ Reserved Address Registers and the bank address is incremented by 1 for each -# subsequent read or write command. -# -# DPHY01_DDRPHY_SEQ_RESERVED_ADDR0_P0 CTL 0x003 0x8000c4030301143f -# DPHY01_DDRPHY_SEQ_RESERVED_ADDR1_P0 CTL 0x004 0x8000c4040301143f -# DPHY01_DDRPHY_SEQ_RESERVED_ADDR2_P0 CTL 0x005 0x8000c4050301143f -# DPHY01_DDRPHY_SEQ_RESERVED_ADDR3_P0 CTL 0x006 0x8000c4060301143f -# DPHY01_DDRPHY_SEQ_RESERVED_ADDR4_P0 CTL 0x007 0x8000c4070301143f -# -# DPHY01_DDRPHY_SEQ_RESERVED_ADDR0_P0 CTL 0x003 0x8000c4030301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.RSVD_ADDR0_L2 - - -# --------------------------------------------------------------------------------------- -# SEQ Memory Timing Parameter 0 default=0x7777 -# -# Memory Timing Parameters to be used during calibration. Each nibble is used as -# exponent of 2, to calculate # of clock cycles. Ex: TMOD_CYCLES=5, 2^5 clocks -# -# clk 12*clks 16*clks 15ns/clk 24*clk -# 800 = 2.5ns 30 ns 40 ns -# 1066 = 1.876ns 22.512 ns 30 ns -# 1333 = 1.5ns 18 ns 24 ns -# 1460 - 1.370ns 16.439 ns 22 ns 32.88 ns* -# 1600 = 1.25ns 15 ns 20 ns 12 30 ns* -# 1731 = 1.155ns 13.865 ns 18.49 ns 13 27.72 ns* -# 1866 = 1.072ns 12.862 ns 17.15 ns 14 25.73 ns* -# 2133 = .9376ns 11.25 ns 15 ns 16 22.50 ns* -# 2259 = .8853ns 10.624 ns 14.16 ns 17 21.25 ns* -# 3200 0.625ns -# -# [01:23] [0:2] [0:1] -# DPHY01_DDRPHY_SEQ_MEM_TIMING_PARAM0_P0 CTL 0x012 0x8000c4120301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MEM_TIMING_PARAM0_L2 -scom 0x800(0,1)C4120301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # TMOD_CYCLES, DDR3=max(12nCK, 15ns), DDR4=max(24nCK, 15ns) - 48:51 , 0x4 , ((CEN.ATTR_MSS_FREQ <= 2133) && (def_is_ddr3)) ; # DDR3 && < 2133, 2^4 = 16clks - 48:51 , 0x5 , ((CEN.ATTR_MSS_FREQ > 2133) && (def_is_ddr3)) ; # DDR3 && > 2133, 2^5 = 32clks - 48:51 , 0x5 , ((CEN.ATTR_MSS_FREQ < 3200) && (def_is_ddr4)) ; # DDR4 && < 3200, 2^5 = 32clks - # TRCD_CYCLES - 52:55 , 0x4 , ((ATTR_EFF_DRAM_TRCD > 8) && (ATTR_EFF_DRAM_TRCD <= 16)) ; # 2^4 = 16 clks - 52:55 , 0x3 , (ATTR_EFF_DRAM_TRCD <= 8) ; # 2^3 = 8 clks - 52:55 , 0x5 , (ATTR_EFF_DRAM_TRCD > 16) ; # 2^5 = 32 clks - # TRP_CYCLES - 56:59 , 0x3 , (ATTR_EFF_DRAM_TRP < 8) ; # 2^3 = 8 clks - 56:59 , 0x4 , ((ATTR_EFF_DRAM_TRP > 8) && (ATTR_EFF_DRAM_TRP <= 16)) ; # 2^4 = 16 clks - 56:59 , 0x5 , (ATTR_EFF_DRAM_TRP > 16) ; # 2^5 = 32 clks - # TRFC_CYCLES, based on Gb density (512=90ns 1Gb=110ns 2Gb=160ns 4Gb=300ns 8Gb=350ns) - # ATTR_EFF_DRAM_TRFC in clocks = tRFC / clock - 60:63 , 0x6 , ((ATTR_EFF_DRAM_TRFC <= 64) && (ATTR_EFF_DRAM_TRFC > 32)) ; # 2^6 = 64 clks - 60:63 , 0x7 , ((ATTR_EFF_DRAM_TRFC <= 128) && (ATTR_EFF_DRAM_TRFC > 64)) ; # 2^7 = 128 clks - 60:63 , 0x8 , ((ATTR_EFF_DRAM_TRFC <= 256) && (ATTR_EFF_DRAM_TRFC > 128)) ; # 2^8 = 256 clks - 60:63 , 0x9 , (ATTR_EFF_DRAM_TRFC > 256) ; # 2^9 = 512 clks -} - -# --------------------------------------------------------------------------------------- -# SEQ Memory Timing Parameter 1 default=0x7777 -# -# Memory Timing Parameters to be used during calibration. Each nibble is used as -# exponent of 2, to calculate # of clock cycles. Ex: TZQCS_CYCLES=6, 2^6 clocks -# -# [01:23] [0:2] [0:1] -# DPHY01_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0 CTL 0x013 0x8000c4130301143f -# PHYW.PHYX.SYNHX.D3SIDEA.SEQX.U_SEQ_APB.MEM_TIMING_PARAM1_L2T -scom 0x800(0,1)C4130301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # TZQINIT_CYCLES max(tZQINIT,tZQOPER) DDR3=max(512nCK, 640ns) DDR4=1024nCK - 48:51 , 0x9 , ((def_is_ddr3) && (CEN.ATTR_MSS_FREQ <= 1600)) ; # DDR3 & freq <= 1600, 512 clks - 48:51 , 0xA , ((def_is_ddr4) || (CEN.ATTR_MSS_FREQ > 1600)) ; # DDR4 || freq > 1600, 1024 clks - # TZQCS_CYCLES DDR3=max(64nCK, 80ns) DDR4=128nCK - 52:55 , 0x6 , ((def_is_ddr3) && (CEN.ATTR_MSS_FREQ <= 1600)) ; # DDR3 & freq <= 1600, 64 clks - 52:55 , 0xA , ((def_is_ddr4) || (CEN.ATTR_MSS_FREQ > 1600)) ; # DDR4 || freq > 1600, 128 clks -# *Note: max values system dependent - # TWLDQSEN_CYCLES DDR3/4=min(25nCK)* - 56:59 , 0x5 , any ; # 2^5 = 32 clks - # TWLMRD_CYCLES DDR3/4=min(40nCK)* - 60:63 , 0x6 , any ; # 2^6 = 64 clks -} - -# --------------------------------------------------------------------------------------- -# SEQ Memory Timing Parameter 2 default=0x7777 -# -# Memory Timing Parameters to be used during calibration. Each nibble is used as -# exponent of 2, to calculate # of clock cycles. Ex: TRCS_CYCLES=0, 2^0 clocks -# -# [01:23] [0:2] [0:1] -# DPHY01_DDRPHY_SEQ_MEM_TIMING_PARAM2_P0 CTL 0x014 0x8000c4140301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MEM_TIMING_PARAM2_L2 -# -# TODTLON_OFF_CYCLES DDR3=CWL+AL-2 DDR4 if 2tCK, CWL+AL-3 -# -scom 0x800(0,1)C4140301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - # TODTLON_OFF_CYCLES DDR3=CWL+AL-2 DDR4 if 2tCK, CWL+AL-3 - #--------------- DDR3 ------------------------------------------------------------------------- - 48:51 , 0x3 , ((def_is_ddr3) && (def_AL_ena) && (def_tODTL_DDR3 <= 8)) ; # 8 clks - 48:51 , 0x4 , ((def_is_ddr3) && (def_AL_ena) && (def_tODTL_DDR3 <= 16) && (def_tODTL_DDR3 > 8)) ; # 16 clks - 48:51 , 0x5 , ((def_is_ddr3) && (def_AL_ena) && (def_tODTL_DDR3 <= 32) && (def_tODTL_DDR3 > 16)) ; # 32 clks - 48:51 , 0x6 , ((def_is_ddr3) && (def_AL_ena) && (def_tODTL_DDR3 <= 64) && (def_tODTL_DDR3 > 32)) ; # 64 clks - #--------------- DDR3 and no AL --------------------------------------------------------------- - 48:51 , 0x3 , ((def_is_ddr3) && (def_AL_dis) && (def_tODTL_DDR3_NOAL <= 8)) ; # 8 clks - 48:51 , 0x4 , ((def_is_ddr3) && (def_AL_dis) && (def_tODTL_DDR3_NOAL <= 16) && (def_tODTL_DDR3_NOAL > 8)) ; # 16 clks - 48:51 , 0x5 , ((def_is_ddr3) && (def_AL_dis) && (def_tODTL_DDR3_NOAL <= 32) && (def_tODTL_DDR3_NOAL > 16)) ; # 32 clks - 48:51 , 0x6 , ((def_is_ddr3) && (def_AL_dis) && (def_tODTL_DDR3_NOAL <= 64) && (def_tODTL_DDR3_NOAL > 32)) ; # 64 clks - #--------------- DDR4 ------------------------------------------------------------------------- - 48:51 , 0x3 , ((def_is_ddr4) && (def_AL_ena) && (def_tODTL_DDR4 <= 8)) ; # 8 clks - 48:51 , 0x4 , ((def_is_ddr4) && (def_AL_ena) && (def_tODTL_DDR4 <= 16) && (def_tODTL_DDR4 > 8)) ; # 16 clks - 48:51 , 0x5 , ((def_is_ddr4) && (def_AL_ena) && (def_tODTL_DDR4 <= 32) && (def_tODTL_DDR4 > 16)) ; # 32 clks - 48:51 , 0x6 , ((def_is_ddr4) && (def_AL_ena) && (def_tODTL_DDR4 <= 64) && (def_tODTL_DDR4 > 32)) ; # 64 clks - #--------------- DDR4 and no AL --------------------------------------------------------------- - 48:51 , 0x3 , ((def_is_ddr4) && (def_AL_dis) && (def_tODTL_DDR4_NOAL <= 8)) ; # 8 clks - 48:51 , 0x4 , ((def_is_ddr4) && (def_AL_dis) && (def_tODTL_DDR4_NOAL <= 16) && (def_tODTL_DDR4_NOAL > 8)) ; # 16 clks - 48:51 , 0x5 , ((def_is_ddr4) && (def_AL_dis) && (def_tODTL_DDR4_NOAL <= 32) && (def_tODTL_DDR4_NOAL > 16)) ; # 32 clks - 48:51 , 0x6 , ((def_is_ddr4) && (def_AL_dis) && (def_tODTL_DDR4_NOAL <= 64) && (def_tODTL_DDR4_NOAL > 32)) ; # 64 clks - 48:51 , 0x0 , any ; # 0 clks - # TRC_CYCLES -# 52:55 , 0x7 , (def_is_sim) ; # match dials - 52:55 , 0x7 , ((ATTR_EFF_DRAM_TRC > 64) && (ATTR_EFF_DRAM_TRC <= 128)) ; # 2^7 = 128 clks - 52:55 , 0x6 , ((ATTR_EFF_DRAM_TRC > 32) && (ATTR_EFF_DRAM_TRC <= 64)) ; # 2^6 = 64 clks - 52:55 , 0x5 , ((ATTR_EFF_DRAM_TRC > 16) && (ATTR_EFF_DRAM_TRC <= 32)) ; # 2^5 = 32 clks - 52:55 , 0x4 , ((ATTR_EFF_DRAM_TRC > 8) && (ATTR_EFF_DRAM_TRC <= 16)) ; # 2^4 = 16 clks - 52:55 , 0x3 , (ATTR_EFF_DRAM_TRC <= 8) ; # 2^3 = 8 clks - # TMRSC_CYCLES for RLDRAMs, set to 0 for everything else -# 56:59 , 0x7 , (def_is_sim) ; # match dials - 56:59 , 0x0 , any ; -# 60:63 , 0x0 , any ; # reserved -} -# --------------------------------------------------------------------------------------- -# SEQ Low Power Termination Address default=0xFFFF -# -# bit positions and mapping of the Address/BA/BG pins in DDR3/DDR4 of the low power -# termination address{2-4} -# -# for DDR3: -# A(0:9) = LPT_ADDR2(0:9) -# A(11) = LPT_ADDR2(11) -# A(13:15) = LPT_ADDR2(13:15) -# BA(0:2) = LPT_ADDR4(0:2) -# -# for DDR4: -# A(0:9) = LPT_ADDR2(0:9) -# A(11) = LPT_ADDR2(11) -# A(13) = LPT_ADDR2(13) -# A(17) = LPT_ADDR3(1) -# BA(0:1) = LPT_ADDR4(0:1) -# BG(0:1) = LPT_ADDR4(2:3) -# -#DPHY01_DDRPHY_SEQ_LPT_ADDR2_P0 0x017 0x8000c4170301143f -#scom 0x8000c4170301143f { -# bits , scom_data ; -## 0:47 , 0x000000000000 ; # reserved -# 48:63 , 0xFFFF ; # LPT_ADDR2 -#} - -# --------------------------------------------------------------------------------------- -# Write control logic configuration 0 default=0 -# -# tWLO = write leveling output delay; freq < 1600, max=9 otherwise max=7.5 ns -# tWLOE= write leveling output error; max=2 ns -# -# DPHY01_DDRPHY_WC_CONFIG0_P0 0x000 0x8000cc000301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG0_L2 -scom 0x800(0,1)CC000301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved -# !! need to review - # = 12 + max(tWLDQSEN-tMOD,tWLO+tWLOE) + (longest DQS wire delay in CKs) + (longest DQ wire delay in CKs) - 48:55 , 0x10 , (def_is_sim) ; # TWLO_TWLOE = 16 (same as DD0) - # @ 1600, = 12 + max(13,8) + ldqs + ldq = 25 + ldqs + ldq - # @ 1866, = 12 + max(13,9) + ldqs + ldq = 25 + ldqs + ldq - 48:55 , 0x1B , any ; # TWLO_TWLOE = 27 - #48:55 , (25+ldqs+ldq) , (CEN.ATTR_MSS_FREQ > 1460) ; # TWLO_TWLOE (> 1333) - - 56 , 0b1 , any ; # WL_ONE_DQS_PULSE = enable (one pulse) -# 56 , 0b0 , any ; # WL_ONE_DQS_PULSE = disable (many pulses) - - # FW_WR_RD [same formula as RD_WR? max(tWTR+11,AL+tRTP+3), ATTR_EFF_DRAM_AL(0,1,2)] - 57:62 , 0b000000 , (def_is_sim) ; # is this max? - 57:62 , 0b100000 , any ; # dd0 = 17 clocks, now 32 from SWyatt - - # AL={1,2}; max (TWTR + 11, TRTP + AL + 3) -# 57:62 , (def_TWTR_PLUS_OFF) , (def_AL_ena && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_AL) ) ; # TWTR + 11 -# 57:62 , (def_TRTP_PLUS_AL) , (def_AL_ena && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_AL) ) ; # TRTP + AL + 3 - - # AL=0, max (TWTR + 11, TRTP + 3) -# 57:62 , (def_TWTR_PLUS_OFF) , (def_AL_dis && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_NOAL) ) ; # TWTR + 11 -# 57:62 , (def_TRTP_PLUS_NOAL), (def_AL_dis && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_NOAL) ) ; # TRTP + 3 - - 63 , 0b0 , any ; # CUSTOM_INIT_WRITE -} -# --------------------------------------------------------------------------------------- -# Write control logic configuration 1 default=0x2350 addr=0xCC01 -# -# DPHY01_DDRPHY_WC_CONFIG1_P0 0x001 0x8000cc010301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG1_L2 -scom 0x800(0,1)CC010301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# !! need to review - 48:51 , 0b1100 , (def_is_sim) ; # BIG_STEP = 12 (changed from default for SIM) - 48:51 , 0b0000 , any ; # BIG_STEP = 0 SWyatt -# 48:51 , 0b0010 , any ; # BIG_STEP = 2 (default) - 52:54 , 0b000 , any ; # SMALL_STEP = 0 (default) SWyatt -# 52:54 , 0b001 , any ; # SMALL_STEP = 1 (!! recommend setting to 0) - 55:60 , 0b101010 , any ; # WR_PRE_DLY = 42 -# 61:63 , 0b000 , any ; # reserved -} - -# --------------------------------------------------------------------------------------- -# Write control logic configuration 2 default=0x5440 -# -# DPHY01_DDRPHY_WC_CONFIG2_P0 0x002 0x8000cc020301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG2_L2 -scom 0x800(0,1)CC020301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:51 , 0x3 , (def_is_sim) ; # NUM_VALID_SAMPLES = 3 (changed from defaults) - 48:51 , 0x5 , any ; # NUM_VALID_SAMPLES = 5 (defaults) -# -------------------------- - # FW_RD_WR = max(tWTR+8,CL+AL+GPO+tRTP), AL=ATTR_EFF_DRAM_CL-ATTR_EFF_DRAM_AL when ATTR_EFF_DRAM_AL != 0 SWyatt - # AL={1,2}; max (TWTR + 8, TRTP + CL + AL + GPO) - 52:57 , (def_TWTR_PLUS_OFF) , (def_AL_ena && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_AL) ) ; # TWTR + 8 - 52:57 , (def_TRTP_PLUS_AL) , (def_AL_ena && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_AL) ) ; # TRTP + CL + CL-AL + GPO - - # AL=0, max (TWTR + 8, TRTP + CL + GPO) - 52:57 , (def_TWTR_PLUS_OFF) , (def_AL_dis && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_NOAL) ) ; # TWTR + 8 - 52:57 , (def_TRTP_PLUS_NOAL), (def_AL_dis && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_NOAL) ) ; # TRTP + CL + GPO -# -------------------------- - # FW_RD_WR = max(tWTR+11,AL+tRTP+3), AL=ATTR_EFF_DRAM_CL-ATTR_EFF_DRAM_AL when ATTR_EFF_DRAM_AL != 0 - # AL={1,2}; max (TWTR + 11, TRTP + AL + 3) -# 52:57 , (def_TWTR_PLUS_OFF) , (def_AL_ena && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_AL) ) ; # TWTR + 11 -# 52:57 , (def_TRTP_PLUS_AL) , (def_AL_ena && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_AL) ) ; # TRTP + AL + 3 - - # AL=0, max (TWTR + 11, TRTP + 3) -# 52:57 , (def_TWTR_PLUS_OFF) , (def_AL_dis && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_NOAL) ) ; # TWTR + 11 -# 52:57 , (def_TRTP_PLUS_NOAL), (def_AL_dis && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_NOAL) ) ; # TRTP + 3 - -# 58:61 , 0b00000 , any ; # reserved - # DD2_FIX_DIS - 62 , 0b0 , any ; # 0=disable 1=enable DD2 fixes in WC logic - # DP18_WR_DELAY_VALUE_{0-23}_RP{0-3}_REG are reset to 0 at the start of WL cal for rank pair 0 when '1' - 63 , 0b0 , any ; # EN_RESET_WR_DELAY_WL = disabled -} - -# --------------------------------------------------------------------------------------- -# Write control logic configuration 3 default=0x01F8 DDR4 PDA register -# -# DPHY01_DDRPHY_WC_CONFIG3_P0 0x005 0x8000cc050301143f -# PHYW.PHYX.SYNTHX.D3SIDEA.WCX.DDRPHY_WC_CONFIG3_L2 -scom 0x800(0,1)CC050301143F { # _P[0:1] - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48 , 0b0 , any ; # DDR4 ballot, drive DQ pins on MRS -# !! need to review - # MRS_CMD_DQ_ON determines the WL_per_DRAM_addr time. - # WL_per_DRAM_addr = 10 + MRS_CMD_DQ_ON in 2:1 mode - # WL_per_DRAM_addr = 18 + 2 * MRS_CMD_DQ_ON in 4:1 mode - 49:54 , 0b000000 , any ; # MRS_CMD_DQ_ON !! - 55:60 , 0b000000 , (def_is_sim) ; # MRS_CMD_DQ_OFF !! - 55:60 , 0b111111 , any ; # MRS_CMD_DQ_OFF !! -# 61:63 , 0b000 , any ; # reserved -} - -# --------------------------------------------------------------------------------------- -# DP18 Data Bit Direction 0 defaults to 0's no longer need to set this. -# -# 1 indicates output only -# -# DPHY01_DDRPHY_DP18_DATA_BIT_DIR0_P0_0 0x002 0x800000020301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_DIR0_L2 - -# --------------------------------------------------------------------------------------- -# DP18 Data Bit Direction 1 defaults to 0's -# -# '1'b indicates DP18 bit is an output and continously drives out a signal -# -# DPHY01_DDRPHY_DP18_DATA_BIT_DIR1_P0_0 0x003 0x800000030301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_DIR1_L2 -#scom 0x800(0,1)(00,04,08,0C,10)030301143f { # DIR1_P[0:1]_[0:4] -scom 0x800(0,1)3C030301143f { # DIR1_P[0:1]_[0:4] via broadcast - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# 48:52 , 0b00000 , any ; # reserved... used to be DATA_BIT_DIR_16_23 - 53 , 0b0 , any ; # DD2_FIX_DIS, disable fixes for DP18 write logic - 54 , 0b1 , any ; # TOXDRV_HIBERNATE # Thin oxide driver hibernation disable. - 55 , 0b0 , any ; # ATEST_MUX_CTL_EN - 56 , 0b0 , any ; # WL_ADVANCE_DISABLE - 57 , 0b0 , any ; # DISABLE_PING_PONG - 58 , 0b1 , any ; # DELAY_PING_PONG_HALF, must be 1 from definition - 59 , 0b1 , any ; # ADVANCE_PING_PONG. must be 1 from definition - 60:63 , 0b0000 , any ; # ATEST_MUX_CTL[0:3] -} - -# --------------------------------------------------------------------------------------- -# ADR Output Driver Force and ATEST Control Register -# -# DPHY01_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0 0x035 0x800080350301143f -#scom 0x800(0,1)(80,84)350301143f { # P[0:1]_ADR32S[0:1] -scom 0x800(0,1)BC350301143f { # DIR1_P[0:1]_[0:4] via broadcast - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# 48 , 0b0 , any ; # FLUSH control to ANALOG during Manufacturing Macro Test - reserved. -# 49 , 0b0 , any ; # FORCE_EN output Force Enable Bit. - 50 , 0b1 , any ; # TOXDRV_HIBERNATE thin oxide driver hibernation disable. -# 51 , 0b0 , any ; # ATEST1CTL_EN Enable ATEST1 output. -# 52:55 , 0b0000 , any ; # HS_PROBE_A_SEL High Speed Probe A Select - reserved. -# 56:59 , 0b0000 , any ; # HS_PROBE_B_SEL High Speed Probe B Select - reserved. -# 60 , 0b0 , any ; # ATEST1CTL0 bit 0 of ATEST1CTL value - reserved -# 61 , 0b0 , any ; # ATEST1CTL1 bit 1 of ATEST1CTL value - reserved -# 62 , 0b0 , any ; # ATEST1CTL2 bit 2 of ATEST1CTL value - reserved. -# 63 , 0b0 , any ; # ATEST1CTL3 bit 3 of ATEST1CTL value - reserved. -} - -# -# -# --------------------------------------------------------------------------------------- -# DP18 Data Bit Enable 0 (defaults to 0's) Affects ALL Ranks -# -# DP18 24 single ended data (tx/rx) pins enable(1)/disable(0). -# When set to disable, it turns off the bit(lane) for ALL ranks -# -# Byte spares on P0_1, P1_2, P2_4, P3_1, DQ in lanes 8:15, DQS in lanes 20:23 -# -# P0_1{56:63}, P1_2{56:63} = 0xFF if spares enabled else 0x00 -# all others (P0_0, P0_[2:4], P1_[0:1], P1_[3:4]) = 0xFFFF -# -# P2_4{56:63}, P3_1{56:63} = 0xFF if spares enabled else 0x00 -# all others (P2_[0:3], P3_0, P3_[2:4]) = 0xFFFF -# -# [01:23] [0:1]_[0:1]_[0:4] -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0 0x000 0x800000000301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_ENABLE0_L2 -# -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0 0x800000000301143f -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2 0x800008000301143f -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3 0x80000C000301143f -# DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_0 0x800000000301183f -# DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_2 0x800008000301183f -# DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_3 0x80000C000301183f -scom 0x800(000,008,00C)000301143f { # P0_0, P0_2, P0_3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0xFFFF , (def_valid_p0) ; # enable DATA_BIT_ENABLE_0_15 - 48:63 , 0x0000 , any ; -} - -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0 0x800100000301143f -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3 0x80010C000301143f -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4 0x800110000301143f -# DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_0 0x800100000301183f -# DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_3 0x80010C000301183f -# DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_4 0x800110000301183f -scom 0x800(100,10C,110)000301143f { # P1_0, P1_2, P1_3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0xFFFF , (def_valid_p1) ; # enable DATA_BIT_ENABLE_0_15 - 48:63 , 0x0000 , any ; -} - -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_4 0x800010000301143f -scom 0x800010000301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0xFFFF , ((def_is_mba01) && (def_valid_p0)) ; # enable DATA_BIT_ENABLE_0_15 -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_4 0x800010000301183f - 48:63 , 0xFFFF , ((def_is_mba23) && (def_valid_p0) && (def_p0_has_spare_full)) ; # PortC DATA_BIT_ENABLE_0_15 - 48:63 , 0xFF0F , ((def_is_mba23) && (def_valid_p0) && (def_p0_has_spare_upper)) ; # PortC disable lower dq0:3 - 48:63 , 0xFFF0 , ((def_is_mba23) && (def_valid_p0) && (def_p0_has_spare_lower)) ; # PortC disable upper dq4:7 - 48:63 , 0xFF00 , ((def_is_mba23) && (def_valid_p0) && (def_p0_no_spare)) ; # PortC disable spare byte - 48:63 , 0x0000 , any ; -} - -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_1 0x800104000301143f -scom 0x800104000301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0xFFFF , ((def_is_mba01) && (def_valid_p1)) ; # enable DATA_BIT_ENABLE_0_15 -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_1 0x800104000301183f - 48:63 , 0xFFFF , ((def_is_mba23) && (def_valid_p1) && (def_p1_has_spare_full)) ; # PortD DATA_BIT_ENABLE_0_15 - 48:63 , 0xFF0F , ((def_is_mba23) && (def_valid_p1) && (def_p1_has_spare_upper)) ; # PortD disable lower dq0:3 - 48:63 , 0xFFF0 , ((def_is_mba23) && (def_valid_p1) && (def_p1_has_spare_lower)) ; # PortD disable upper dq4:7 - 48:63 , 0xFF00 , ((def_is_mba23) && (def_valid_p1) && (def_p1_no_spare)) ; # PortD disable spare byte - 48:63 , 0x0000 , any ; -} - -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P0_1 0x800004000301143f -scom 0x800004000301143f { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0xFFFF , ((def_is_mba01) && (def_valid_p0) && (def_p0_has_spare_full)) ; # PortA DATA_BIT_ENABLE_0_15 - 48:63 , 0xFF0F , ((def_is_mba01) && (def_valid_p0) && (def_p0_has_spare_upper)) ; # PortA disable lower dq0:3 - 48:63 , 0xFFF0 , ((def_is_mba01) && (def_valid_p0) && (def_p0_has_spare_lower)) ; # PortA disable upper dq4:7 - 48:63 , 0xFF00 , ((def_is_mba01) && (def_valid_p0) && (def_p0_no_spare)) ; # PortA disable spare byte -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P2_1 0x800004000301183f - 48:63 , 0xFFFF , ((def_is_mba23) && (def_valid_p0)) ; # enable DATA_BIT_ENABLE_0_15 - 48:63 , 0x0000 , any ; -} - -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P1_2 0x800108000301143f -scom 0x800108000301143f { - bits , scom_data , expr ; # spare = 8_15 -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0xFFFF , ((def_is_mba01) && (def_valid_p1) && (def_p1_has_spare_full)) ; # PortB DATA_BIT_ENABLE_0_15 - 48:63 , 0xFFF0 , ((def_is_mba01) && (def_valid_p1) && (def_p1_has_spare_upper)) ; # PortB disable lower dq0:3 - 48:63 , 0xFF0F , ((def_is_mba01) && (def_valid_p1) && (def_p1_has_spare_lower)) ; # PortB disable upper dq4:7 - 48:63 , 0xFF00 , ((def_is_mba01) && (def_valid_p1) && (def_p1_no_spare)) ; # PortB disable spare byte -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE0_P3_2 0x800108000301183f - 48:63 , 0xFFFF , ((def_is_mba23) && (def_valid_p1)) ; # P3_2 - 48:63 , 0x0000 , any ; -} - -# --------------------------------------------------------------------------------------- -# DP18 Data Bit Enable 1 (defaults to 0's) -# -# Centaur has mapped DP18 data bits 16:23 to be DQS, but this register bits 48:55 are for -# changing these lanes to be dq bits, so we should leave them at 0's. (per Dave Stauffer) -# -# DPHY01_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0 0x001 0x800000010301143f -#PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_ENABLE1_L2 -#scom 0x800(0,1)(00,04,08,0C,10)010301143f { # ENABLE1_P[0:1]_[0:4] -# scom 0x800(0,1)3C010301143f { # ENABLE1_P[0:1]_[0:4] via broadcast -# bits , scom_data ; -## 0:47 , 0x000000000000 ; # reserved -# 48:55 , 0b00000000 ; # data_bit_enable_16_23 -# 56 , 0b0 ; # DFT_FORCE_OUTPUTS -# 57 , 0b0 ; # DFT_PRBS7_GEN_EN -# 58 , 0b0 ; # WRAPSEL -# 59 , 0b0 ; # HW_VALUE -# 60 , 0b0 ; # MRS_CMD_DATA_N0 -# 61 , 0b0 ; # MRS_CMD_DATA_N1 -# 62 , 0b0 ; # MRS_CMD_DATA_N2 -# 63 , 0b0 ; # MRS_CMD_DATA_N3 -# } - -#--------------------------------------------------------------------------- -# DP18 Data Bit Disable 0 default=0 per Rank Group/Pair -# -# Procedure function to set this register, pulling data from the SPD. -# 1 = disable dq bit -# !! Note only affects calibrations. -# -# DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0 0x07C 0x8000007c0301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_L2 -# -#--------------------------------------------------------------------------- -# DP18 Data Bit Disable 1 default=0 -# -# bits 16:23, used for DQS, no need to set, legacy logic (Dave) -# -# DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_P0_0 0x07D 0x8000007d0301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_DATA_BIT_DISABLE1_RP0_L2 - -#--------------------------------------------------------------------------- -# ADR BIT ENABLE P[0:1] ADR[0:3] default=0 -# -# Turn off of deconfigured the ports handled in a clean up procedure -# -# DPHY01_DDRPHY_ADR_BIT_ENABLE_P0_ADR0 0x000 0x800040000301143f -# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.P_REG_A_00_L2 -scom 0x800(040,044,140,144)000301143F { # _P[0:1]_ADR[0:1] - bits , scom_data ; -# 0:47 , 0x000000000000 ; # reserved - 48:63 , 0xFFF0 ; # bits 12:15 not used in ADR[0:1] -} -scom 0x800(048,04C,148,14C)000301143F { # _P[0:1]_ADR[2:3] - bits , scom_data ; -# 0:47 , 0x000000000000 ; # reserved - 48:63 , 0xFFFC ; # 14:15 not used in ADR[2:3] -} - -#--------------------------------------------------------------------------- -# ADR DELAYs defaults to 0's -# -# Adjustment in the ADR to center clock signals with address/cmd -# Settings for differential clocks for all ports and ADR blocks based -# on how Centaur maps the clocks to ADR lanes. reference: centaur_pins_xref.xls -# -# ADR {0:3} = address {0x400, 0x440, 0x480, 0x4C0} -# -# DELAY Address offset lane(ADR) -# ----------------------------------- -# 0 4 0:1 -# 1 5 2:3 -# 2 6 4:5 -# 3 7 6:7 -# 4 8 8:9 -# 5 9 10:11 -# 6 A 12:13 -# 7 B 14:15 (not used in our design) -# -# dimm0 = clk[0:1], dimm1 = clk[2:3] -# 49:55 = value0, 57:63 = value1, -# 0x40 = 64 (for single data rate), 0x20 = 32 (for double data rate) -# -# [01:23] [0:7] [0:1] [0:3] -# DPHY01_DDRPHY_ADR_DELAY0_P0_ADR0 0x004-00B 0x800040040301143f -# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_09_L2 -#==================================================================================== -# PORT 0 / 2 -#==================================================================================== -#-- Port 0/2 ADR 0 ------------------------------------------------------------ -scom 0x800040040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1[0]) , (def_is_mba01) ; # P0 L0 , A1_CKE1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3[0]) , (def_is_mba01) ; # P0 L1 , A0_CS3n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0[0]) , (def_is_mba23) ; # P2 L0 , C0_CS0n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3[0]) , (def_is_mba23) ; # P2 L1 , C_A3 -} -scom 0x800040050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P0_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0[0]) , (def_is_mba01) ; # P0 L2 , A1_CKE0 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0[0]) , (def_is_mba01) ; # P0 L3 , A0_ODT0 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3[0]) , (def_is_mba23) ; # P2 L2 , C1_CS3n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN[0]) , (def_is_mba23) ; # P2 L3 , C_RASn -} -scom 0x800040060301143F { # DPHY01_DDRPHY_ADR_DELAY2_P0_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15[0]) , (def_is_mba01) ; # P0 L4 , A_A15 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_PAR[0]) , (def_is_mba01) ; # P0 L5 , A_PAR - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12[0]) , (def_is_mba23) ; # P2 L4 , C_A12 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7[0]) , (def_is_mba23) ; # P2 L5 , C_A7 -} -scom 0x800040070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P0_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1[0]) , (def_is_mba01) ; # P0 L6 , A0_CKE1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1[0]) , (def_is_mba01) ; # P0 L7 , A0_CS1n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba23) ; # P2 L6 , C0_CLK1_p - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba23) ; # P2 L7 , C0_CLK1_n -} -scom 0x800040080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P0_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0[0]) , (def_is_mba01) ; # P0 L8 , A0_CKE0 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0[0]) , (def_is_mba01) ; # P0 L9 , A1_ODT0 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba23) ; # P2 L8 , C1_CLK1_p - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba23) ; # P2 L9 , C1_CLK1_n -} -scom 0x800040090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P0_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba01) ; # P0 L10, A0_CLK0_p - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba01) ; # P0 L11, A0_CLK0_n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2[0]) , (def_is_mba23) ; # P2 L10, C1_CKE2 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2[0]) , (def_is_mba23) ; # P2 L11, C0_CKE2 -} -#-- Port 0/2 ADR 1 ------------------------------------------------------------ -scom 0x800044040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0[0]) , (def_is_mba01) ; # P0 L0 , A0_CS0n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3[0]) , (def_is_mba01) ; # P0 L1 , A1_CKE3 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2[0]) , (def_is_mba23) ; # P2 L0 , C_BA2 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1[0]) , (def_is_mba23) ; # P2 L1 , C1_CKE1 -} -scom 0x800044050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P0_ADR1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1[0]) , (def_is_mba01) ; # P0 L2 , A1_ODT1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2[0]) , (def_is_mba01) ; # P0 L3 , A_A2 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1[0]) , (def_is_mba23) ; # P2 L2 , C0_ODT1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN[0]) , (def_is_mba23) ; # P2 L3 , C_WEn -} -scom 0x800044060301143F { # DPHY01_DDRPHY_ADR_DELAY2_P0_ADR1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6[0]) , (def_is_mba01) ; # P0 L4 , A_A6 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1[0]) , (def_is_mba01) ; # P0 L5 , A_A1 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1[0]) , (def_is_mba23) ; # P2 L4 , C0_CS1n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11[0]) , (def_is_mba23) ; # P2 L5 , C_A11 -} -scom 0x800044070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P0_ADR1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14[0]) , (def_is_mba01) ; # P0 L6 , A_A14 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2[0]) , (def_is_mba01) ; # P0 L7 , A0_CKE2 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3[0]) , (def_is_mba23) ; # P2 L6 , C0_CKE3 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2[0]) , (def_is_mba23) ; # P2 L7 , C0_CS2n -} -scom 0x800044080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P0_ADR1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2[0]) , (def_is_mba01) ; # P0 L8 , A1_CS2n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2[0]) , (def_is_mba01) ; # P0 L9 , A1_CKE2 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0[0]) , (def_is_mba23) ; # P2 L8 , C0_ODT0 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8[0]) , (def_is_mba23) ; # P2 L9 , C_A8 -} -scom 0x800044090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P0_ADR1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4[0]) , (def_is_mba01) ; # P0 L10, A_A4 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN[0]) , (def_is_mba01) ; # P0 L11, A_RASn - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5[0]) , (def_is_mba23) ; # P2 L10, C_A5 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0[0]) , (def_is_mba23) ; # P2 L11, C1_CS0n -} -#-- Port 0/2 ADR 2 ------------------------------------------------------------ -scom 0x800048040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12[0]) , (def_is_mba01) ; # P0 L0 , A_A12 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0[0]) , (def_is_mba01) ; # P0 L1 , A_A0 centerlane - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1[0]) , (def_is_mba23) ; # P2 L0 , C_A1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6[0]) , (def_is_mba23) ; # P2 L1 , C_A6 -} -scom 0x800048050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P0_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3[0]) , (def_is_mba01) ; # P0 L2 , A0_CKE3 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3[0]) , (def_is_mba01) ; # P0 L3 , A1_CS3n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13[0]) , (def_is_mba23) ; # P2 L2 , C_A13 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0[0]) , (def_is_mba23) ; # P2 L3 , C0_CKE0 -} -scom 0x800048060301143F { # DPHY01.DDRPHY_ADR_DELAY2_P0_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba01) ; # P0 L4 , A1_CLK0_p - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba01) ; # P0 L5 , A1_CLK0_n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0[0]) , (def_is_mba23) ; # P2 L4 , C1_ODT0 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1[0]) , (def_is_mba23) ; # P2 L5 , C1_CS1n -} -scom 0x800048070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P0_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1[0]) , (def_is_mba01) ; # P0 L6 , A0_ODT1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0[0]) , (def_is_mba01) ; # P0 L7 , A1_CS0n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1[0]) , (def_is_mba23) ; # P2 L6 , C0_CKE1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0[0]) , (def_is_mba23) ; # P2 L7 , C1_CKE0 -} -scom 0x800048080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P0_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1[0]) , (def_is_mba01) ; # P0 L8 , A1_CS1n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10[0]) , (def_is_mba01) ; # P0 L9 , A_A10 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0[0]) , (def_is_mba23) ; # P2 L8 , C_A0 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1[0]) , (def_is_mba23) ; # P2 L9 , C_BA1 -} -scom 0x800048090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P0_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba01) ; # P0 L10, A0_CLK1_n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[0]) , (def_is_mba01) ; # P0 L11, A0_CLK1_p - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba23) ; # P2 L10, C0_CLK0_n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[0]) , (def_is_mba23) ; # P2 L11, C0_CLK0_p -} -scom 0x8000480A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P0_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba01) ; # P0 L12, A1_CLK1_n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[0]) , (def_is_mba01) ; # P0 L13, A1_CLK1_p - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2[0]) , (def_is_mba23) ; # P2 L12, C1_CS2n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10[0]) , (def_is_mba23) ; # P2 L13, C_A10 -} -#-- Port 0/2 ADR 3 ------------------------------------------------------------ -scom 0x80004C040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P0_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13[0]) , (def_is_mba01) ; # P0 L0 , A_A13 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0[0]) , (def_is_mba01) ; # P0 L1 , A_BA0 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_PAR[0]) , (def_is_mba23) ; # P2 L0 , C_PAR - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1[0]) , (def_is_mba23) ; # P2 L1 , C1_ODT1 -} -scom 0x80004C050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P0_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN[0]) , (def_is_mba01) ; # P0 L2 , A_WEn - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2[0]) , (def_is_mba01) ; # P0 L3 , A0_CS2n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba23) ; # P2 L2 , C1_CLK0_p - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[0]) , (def_is_mba23) ; # P2 L3 , C1_CLK0_n -} -scom 0x80004C060301143F { # DPHY01.DDRPHY_ADR_DELAY2_P0_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1[0]) , (def_is_mba01) ; # P0 L4 , A_BA1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN[0]) , (def_is_mba01) ; # P0 L5 , A_CASn - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14[0]) , (def_is_mba23) ; # P2 L4 , C_A14 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9[0]) , (def_is_mba23) ; # P2 L5 , C_A9 -} -scom 0x80004C070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P0_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5[0]) , (def_is_mba01) ; # P0 L6 , A_A5 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3[0]) , (def_is_mba01) ; # P0 L7 , A_A3 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_ACTN[0]) , (def_is_mba23) ; # P2 L6 , C_ACTn - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2[0]) , (def_is_mba23) ; # P2 L7 , C_A2 -} -scom 0x80004C080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P0_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2[0]) , (def_is_mba01) ; # P0 L8 , A_BA2 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11[0]) , (def_is_mba01) ; # P0 L9 , A_A11 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3[0]) , (def_is_mba23) ; # P2 L8 , C1_CKE3 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15[0]) , (def_is_mba23) ; # P2 L9 , C_A15 -} -scom 0x80004C090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P0_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7[0]) , (def_is_mba01) ; # P0 L10, A_A7 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_ACTN[0]) , (def_is_mba01) ; # P0 L11, A_ACTn - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0[0]) , (def_is_mba23) ; # P2 L10, C_BA0 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN[0]) , (def_is_mba23) ; # P2 L11, C_CASn -} -scom 0x80004C0A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P0_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9[0]) , (def_is_mba01) ; # P0 L12, A_A9 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8[0]) , (def_is_mba01) ; # P0 L13, A_A8 # fixed typo - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4[0]) , (def_is_mba23) ; # P2 L12, C_A4 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3[0]) , (def_is_mba23) ; # P2 L13, C0_CS3n -} -#==================================================================================== -# PORT 1 / 3 -#==================================================================================== -#-- Port 1/3 ADR 0------------------------------------------------------------ -scom 0x800140040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P1_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba01) ; # P1 L0 , B1_CLK0_n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba01) ; # P1 L1 , B1_CLK0_p - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1[1]) , (def_is_mba23) ; # P3 L0 , D1_CKE1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2[1]) , (def_is_mba23) ; # P3 L1 , D_BA2 -} -scom 0x800140050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P1_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba01) ; # P1 L2 , B1_CLK1_n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba01) ; # P1 L3 , B1_CLK1_p - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1[1]) , (def_is_mba23) ; # P3 L2 , D_A1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5[1]) , (def_is_mba23) ; # P3 L3 , D_A5 -} -scom 0x800140060301143F { # DPHY01_DDRPHY_ADR_DELAY2_P1_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3[1]) , (def_is_mba01) ; # P1 L4 , B0_CKE3 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3[1]) , (def_is_mba01) ; # P1 L5 , B0_CS3n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12[1]) , (def_is_mba23) ; # P3 L4 , D_A12 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0[1]) , (def_is_mba23) ; # P3 L5 , D_BA0 -} -scom 0x800140070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P1_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0[1]) , (def_is_mba01) ; # P1 L6 , B_BA0 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1[1]) , (def_is_mba01) ; # P1 L7 , B1_ODT1 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2[1]) , (def_is_mba23) ; # P3 L6 , D1_CKE2 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1[1]) , (def_is_mba23) ; # P3 L7 , D1_CS1n -} -scom 0x800140080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P1_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3[1]) , (def_is_mba01) ; # P1 L8 , B1_CKE3 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15[1]) , (def_is_mba01) ; # P1 L9 , B_A15 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0[1]) , (def_is_mba23) ; # P3 L8 , D0_CKE0 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2[1]) , (def_is_mba23) ; # P3 L9 , D0_CS2n -} -scom 0x800140090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P1_ADR0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2[1]) , (def_is_mba01) ; # P1 L10, B1_CS2n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1[1]) , (def_is_mba01) ; # P1 L11, B0_CKE1 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba23) ; # P3 L10, D1_CLK0_p - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0[1]) , (def_is_mba23) ; # P3 L11, D1_CLK0_n -} -#-- Port 1/3 ADR 1 ------------------------------------------------------------ -scom 0x800144040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P1_ADR1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2[1]) , (def_is_mba01) ; # P1 L0 , B0_CKE2 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7[1]) , (def_is_mba01) ; # P1 L1 , B_A7 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8[1]) , (def_is_mba23) ; # P3 L0 , D_A8 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13[1]) , (def_is_mba23) ; # P3 L1 , D_A13 -} -scom 0x800144050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P1_ADR1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10[1]) , (def_is_mba01) ; # P1 L2 , B_A10 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1[1]) , (def_is_mba01) ; # P1 L3 , B1_CKE1 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1[1]) , (def_is_mba23) ; # P3 L2 , D0_ODT1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_PAR[1]) , (def_is_mba23) ; # P3 L3 , D_PAR -} -scom 0x800144060301143F { # DPHY01_DDRPHY_ADR_DELAY2_P1_ADR1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1[1]) , (def_is_mba01) ; # P1 L4 , B0_CS1n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8[1]) , (def_is_mba01) ; # P1 L5 , B_A8 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0[1]) , (def_is_mba23) ; # P3 L4 , D1_CS0n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11[1]) , (def_is_mba23) ; # P3 L5 , D_A11 -} -scom 0x800144070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P1_ADR1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6[1]) , (def_is_mba01) ; # P1 L6 , B_A6 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3[1]) , (def_is_mba01) ; # P1 L7 , B1_CS3n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1[1]) , (def_is_mba23) ; # P3 L6 , D0_CKE1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN[1]) , (def_is_mba23) ; # P3 L7 , D_WEn -} -scom 0x800144080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P1_ADR1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4[1]) , (def_is_mba01) ; # P1 L8 , B_A4 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1[1]) , (def_is_mba01) ; # P1 L9 , B1_CS1n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3[1]) , (def_is_mba23) ; # P3 L8 , D0_CKE3 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0[1]) , (def_is_mba23) ; # P3 L9 , D1_ODT0 -} -scom 0x800144090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P1_ADR1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1[1]) , (def_is_mba01) ; # P1 L10, B_A1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1[1]) , (def_is_mba01) ; # P1 L11, B_BA1 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN[1]) , (def_is_mba23) ; # P3 L10, D_RASn - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1[1]) , (def_is_mba23) ; # P3 L11, D0_CS1n -} -#-- Port 1/3 ADR 2 ------------------------------------------------------------ -scom 0x800148040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P1_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2[1]) , (def_is_mba01) ; # P1 L0 , B0_CS2n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0[1]) , (def_is_mba01) ; # P1 L1 , B0_ODT0 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0[1]) , (def_is_mba23) ; # P3 L0 , D0_CS0n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10[1]) , (def_is_mba23) ; # P3 L1 , D_A10 -} -scom 0x800148050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P1_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN[1]) , (def_is_mba01) ; # P1 L2 , B_WEn - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2[1]) , (def_is_mba01) ; # P1 L3 , B_A2 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4[1]) , (def_is_mba23) ; # P3 L2 , D_A4 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3[1]) , (def_is_mba23) ; # P3 L3 , D1_CS3n -} -scom 0x800148060301143F { # DPHY01.DDRPHY_ADR_DELAY2_P1_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1[1]) , (def_is_mba01) ; # P1 L4 , B0_ODT1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0[1]) , (def_is_mba01) ; # P1 L5 , B0_CS0n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_ACTN[1]) , (def_is_mba23) ; # P3 L4 , D_ACTn - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9[1]) , (def_is_mba23) ; # P3 L5 , D_A9 -} -scom 0x800148070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P1_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3[1]) , (def_is_mba01) ; # P1 L6 , B_A3 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0[1]) , (def_is_mba01) ; # P1 L7 , B_A0 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3[1]) , (def_is_mba23) ; # P3 L6 , D1_CKE3 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0[1]) , (def_is_mba23) ; # P3 L7 , D1_CKE0 -} -scom 0x800148080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P1_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba01) ; # P1 L8 , B0_CLK1_p - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba01) ; # P1 L9 , B0_CLK1_n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3[1]) , (def_is_mba23) ; # P3 L8 , D0_CS3n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2[1]) , (def_is_mba23) ; # P3 L9 , D_A2 -} -scom 0x800148090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P1_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN[1]) , (def_is_mba01) ; # P1 L10, B_CASn - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0[1]) , (def_is_mba01) ; # P1 L11, B1_CS0n - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba23) ; # P3 L10, D1_CLK1_n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1[1]) , (def_is_mba23) ; # P3 L11, D1_CLK1_p -} -scom 0x8001480A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P1_ADR2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0[1]) , (def_is_mba01) ; # P1 L12, B1_CKE0 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12[1]) , (def_is_mba01) ; # P1 L13, B_A12 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba23) ; # P3 L12, D0_CLK1_n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1[1]) , (def_is_mba23) ; # P3 L13, D0_CLK1_p -} -#-- Port 1/3 ADR 3 ------------------------------------------------------------ -scom 0x80014C040301143F { # DPHY01_DDRPHY_ADR_DELAY0_P1_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11[1]) , (def_is_mba01) ; # P1 L0 , B_A11 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0[1]) , (def_is_mba01) ; # P1 L1 , B0_CKE0 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2[1]) , (def_is_mba23) ; # P3 L0 , D1_CS2n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0[1]) , (def_is_mba23) ; # P3 L1 , D0_ODT0 -} -scom 0x80014C050301143F { # DPHY01_DDRPHY_ADR_DELAY1_P1_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba01) ; # P1 L2 , B0_CLK0_n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba01) ; # P1 L3 , B0_CLK0_p - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba23) ; # P3 L2 , D0_CLK0_n - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0[1]) , (def_is_mba23) ; # P3 L3 , D0_CLK0_p -} -scom 0x80014C060301143F { # DPHY01.DDRPHY_ADR_DELAY2_P1_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13[1]) , (def_is_mba01) ; # P1 L4 , B_A13 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14[1]) , (def_is_mba01) ; # P1 L5 , B_A14 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6[1]) , (def_is_mba23) ; # P3 L4 , D_A6 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1[1]) , (def_is_mba23) ; # P3 L5 , D1_ODT1 -} -scom 0x80014C070301143F { # DPHY01_DDRPHY_ADR_DELAY3_P1_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2[1]) , (def_is_mba01) ; # P1 L6 , B1_CKE2 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0[1]) , (def_is_mba01) ; # P1 L7 , B1_ODT0 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0[1]) , (def_is_mba23) ; # P3 L6 , D_A0 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN[1]) , (def_is_mba23) ; # P3 L7 , D_CASn -} -scom 0x80014C080301143F { # DPHY01_DDRPHY_ADR_DELAY4_P1_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9[1]) , (def_is_mba01) ; # P1 L8 , B_A9 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2[1]) , (def_is_mba01) ; # P1 L9 , B_BA2 - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14[1]) , (def_is_mba23) ; # P3 L8 , D_A14 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3[1]) , (def_is_mba23) ; # P3 L9 , D_A3 -} -scom 0x80014C090301143F { # DPHY01_DDRPHY_ADR_DELAY5_P1_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN[1]) , (def_is_mba01) ; # P1 L10, B_RASn - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_ACTN[1]) , (def_is_mba01) ; # P1 L11, B_ACTn - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7[1]) , (def_is_mba23) ; # P3 L10, D_A7 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15[1]) , (def_is_mba23) ; # P3 L11, D_A15 -} -scom 0x80014C0A0301143F { # DPHY01.DDRPHY_ADR_DELAY6_P1_ADR3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000 , any ; # reserved - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5[1]) , (def_is_mba01) ; # P1 L12, B_A5 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M_PAR[1]) , (def_is_mba01) ; # P1 L13, B_PAR - 48:55 , (ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1[1]) , (def_is_mba23) ; # P3 L12, D_BA1 - 56:63 , (ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2[1]) , (def_is_mba23) ; # P3 L13, D0_CKE2 -} - -#================================================================================ -# ADR Differential Pair Enable -# -# Settings for differential clocks for all ports and ADR blocks based -# on how Centaur maps the clocks to ADR lanes. reference: centaur_pins_xref.xls -# -# bits 48:55 correspond to ADR lane pairs. ex. bit 0 = ADR lane 0 & 1 -# -# ------------- Port 0 --------------------------------------------- -# DPHY01_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0 0x001 0x800040010301143f -# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_A_01_L2 -scom 0x800040010301143F { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:55 , 0x04 , (def_is_mba01) ; # lane 10:11(clk0) - # ------------- Port 2 ------------------------------------- - # DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR0 - 48:55 , 0x18 , (def_is_mba23) ; # lane 6:7(clk1), 8:9(clk3) -# 56:63 , 0x00 , any ; # reserved -} -# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2 -scom 0x800048010301143F { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:55 , 0x26 , (def_is_mba01) ; # lane 4:5(clk2), 10:11(clk1), 12:13(clk3) - # ------------- Port 2 ------------------------------------- - # DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR2 - 48:55 , 0x04 , (def_is_mba23) ; # lane 10:11(clk0) -# 56:63 , 0x00 , any ; # reserved -} - -# ------------- Port 2 --------------------------------------------- -# DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P0_ADR3 -scom 0x80004C010301143F { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:55 , 0x40 , (def_is_mba23) ; # lane 2:3(clk2) - 48:55 , 0x00 , any ; # for mba01 -# 56:63 , 0x00 , any ; # reserved -} - -# ------------- Port 1 --------------------------------------------- -# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0 -scom 0x800140010301143F { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:55 , 0xC0 , (def_is_mba01) ; # lane 0:1(clk2), 2:3(clk3) - # ------------- Port 3 ------------------------------------- - # DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR0 - 48:55 , 0x04 , (def_is_mba23) ; # lane 10:11(clk2) -# 56:63 , 0x00 , any ; # reserved -} -# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2 -scom 0x800148010301143F { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:55 , 0x08 , (def_is_mba01) ; # lane 8:9(clk1) - # ------------- Port 3 ------------------------------------- - # DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR2 - 48:55 , 0x06 , (def_is_mba23) ; # lane 10:11(clk3), 12:13(clk1) -# 56:63 , 0x00 , any ; # reserved -} -# DPHY01.DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3 -scom 0x80014C010301143F { - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:55 , 0x40 , (def_is_mba01) ; # lane 2:3(clk0) - # ------------- Port 3 ------------------------------------- - # DPHY23_DDRPHY_ADR_DIFFPAIR_ENABLE_P1_ADR3 - 48:55 , 0x40 , (def_is_mba23) ; # lane 2:3(clk0) -# 56:63 , 0x00 , any ; # reserved -} - -# !! need updates to these clock registers from PHY / SIM team -# set to 0x8070, reset seq sets it to 0x8024 -#--------------------------------------------------------------------------------------- -# ADR SYSCLK settings default=0x8074 -# -# Controls the circuit which aligns the internal SysClk to the incoming dphy_nclk clock. -# -# DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 0x032 0x800080320301143F -# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_32_L2 -#scom 0x800(0,1)(80,84)320301143F { # _P[0:1]_ADR32S[0:1] -scom 0x800(0,1)BC320301143F { # _P[0:1]_ADR32S[0:1] via broadcast - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# old dials value = 0x0080 - 48 , 0b1 , any ; # ADR32_SYSCLK_ENABLE - - 49:55 , 0b0000010 , any ; # ADR32_SYSCLK_ROT_OVERRIDE - - 56 , 0b0 , any ; # ADR32_SYSCLK_ROT_OVERRIDE_EN - - 57 , 0b1 , any ; # ADR32_SYSCLK_PHASE_ALIGN_RESET - - 58 , 0b1 , any ; # ADR32_SYSCLK_PHASE_CNTL_EN - - 59 , 0b1 , any ; # ADR32_SYSCLK_PHASE_DEFAULT_EN - - 60 , 0b0 , any ; # ADR32_SYSCLK_POS_EDGE_ALIGN -# recent 7/3 - 61 , 0b1 , any ; # ADR32_CONTINUOUS_UPDATE - 62:63 , 0b00 , any ; # CE0DLTVCC, must be '00'b -} - -# --------------------------------------------------------------------------------------- -# ADR WRClk Phase Rotator Offset Value default=0 -# -# !! NOTE different depending on EC level -# -# ADR Phase Rotator Static Offset value used to determine the -# Phase of the WrClk with respect to SysClk. Adjusts for race -# condition between combinatorial logic for WrClk to SysClk. -# -# [01:23] [0:1] [0:1] -# DPHY01_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET_P0_ADR32S0 0x033 0x800080330301143f -# PHYW.PHYX.ADRNEST.ADR32X0.HC.ADRLOGM.ADRLOGX.CONTROL.TWRAP.REG_33_L2 -# 0x800080330301143F 0x800084330301143F 0x800180330301143F 0x800184330301143F -#scom 0x800(0,1)(80,84)330301143F { # _P[0:1]_ADR32S[0:1] -scom 0x800(0,1)BC330301143F { # _P[0:1]_ADR32S[0:1] via broadcast - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# 48 , 0b0 , any ; # reserved - # !! NOTE different depending on EC level, system voltage too? - # value in the scom_data field is right aligned - 48:55 , 0x60 , (def_is_sim) ; # ADR32_TSYS_WRCLK sim set to 0x60 - 48:55 , 0x70 , (ATTR_MSS_EFF_VPD_VERSION < 0x10); # if lower than v6.0 / VZ 0x10, use hardcode - 48:55 , (ATTR_VPD_TSYS_ADR[0]), any ; -# below is for fast process parts -# 48:55 , 0x15 , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (21) -# 48:55 , 0x19 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (25) -# 48:55 , 0x1E , any ; # 1866 Mbps (30) -# group below is for most parts process... -## 48:55 , 0x22 , (CEN.ATTR_MSS_FREQ < 1191) ; # 1066 Mbps, 120 -# 48:55 , 0x22 , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (34) -# 48:55 , 0x28 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (40) -# 48:55 , 0x2F , any ; # 1866 Mbps (47) -# below is for slow process parts -# 48:55 , 0x2D , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (45) -# 48:55 , 0x35 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (53) -# 48:55 , 0x3E , any ; # 1866 Mbps (62) -#-------- debug ----------------------------- -# 48:55 , 0x70 , any ; -# 56:63 , 0x00 , any ; # reserved -} - -# --------------------------------------------------------------------------------------- -# --- DP18 WRCLK_PR P[0:1]_[0:4] Phase Rotator --------------------------- -# --------------------------------------------------------------------------------------- -# DPHY01.DDRPHY_DP18_WRCLK_PR_P0_0 default=0 -# -# !! NOTE different depending on EC level -# -# DP18 Phase Rotator Static Offset value used to -# determine the Phase of the WrClk with respect to SysClk. -# -# [01:23] [0:1]_[0:4] -# DPHY01_DDRPHY_DP18_WRCLK_PR_P0_0 0x074 0x800000740301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_WRCLK_PR_L2 -#scom 0x800(0,1)(00,04,08,0C,10)740301143F { #_P[0:1]_[0:4] -scom 0x800(0,1)3C740301143F { #_P[0:1]_[0:4] via broadcast - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved -# 48 , 0b0 , any ; # reserved - # !! NOTE different depending on EC level - # value in the scom_data field is right aligned - 48:55 , 0x60 , (def_is_sim) ; # DP18_TSYS_WRCLK sim set to 0x60 - 48:55 , 0x6B , (ATTR_MSS_EFF_VPD_VERSION < 0x10); # if lower than v6.0 / VZ 0x10, use hardcode - 48:55 , (ATTR_VPD_TSYS_DP18[0]), any ; -# below is for fast process parts -# 48:55 , 0x14 , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (20) -# 48:55 , 0x18 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (24) -# 48:55 , 0x1C , any ; # 1866 Mbps (28) -# group below is for most parts process... -## 48:55 , 0x78 , (CEN.ATTR_MSS_FREQ < 1191) ; # 1066 Mbps -# 48:55 , 0x20 , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (32) -# 48:55 , 0x27 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (39) -# 48:55 , 0x2D , any ; # 1866 Mbps (45) -# below is for slow process parts -# 48:55 , 0x2C , (CEN.ATTR_MSS_FREQ < 1458) ; # 1333 Mbps, and 1066 (44) -# 48:55 , 0x35 , (CEN.ATTR_MSS_FREQ < 1724) ; # 1600 Mbps (53) -# 48:55 , 0x3E , any ; # 1866 Mbps (62) -#-------- debug ----------------------------- -# 48:55 , 0x6B , any ; -# 56:63 , 0x00 , any ; # reserved -} - -# --------------------------------------------------------------------------------------- -# --- DP18 SYSCLK_PR P[0:1]_[0:4] Phase Rotator --------------------------- -# --------------------------------------------------------------------------------------- -# DPHY01.DDRPHY_DP18_SYSCLK_PR_P0_0 default=0x8070 -# -# to Align bang-bang -# -# !! set to 0x8020 at the end of ddr_phy_reset procedure, should not setting in initfile? -# -# DPHY01 DP18 SysClk Phase Rotator Control -# This register controls the circuit which aligns the internal -# SysClk to the incoming dphy_nclk clock. -# -# [01:23] [0:1]_[0:4] -# DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 0x007 0x0x800000070301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_SYSCLK_PR_L2 -#scom 0x800(0,1)(00,04,08,0C,10)070301143F { #_P[0:1]_[0:4] -scom 0x800(0,1)3C070301143F { #_P[0:1]_[0:4] via broadcast - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48 , 0b1 , any ; # DP18_SYSCLK_ENABLE - 49:55 , 0b0000000 , any ; # DP18_SYSCLK_ROT_OVERRIDE - - 56 , 0b1 , (def_is_sim) ; # DP18_SYSCLK_ROT_OVERRIDE_EN - 56 , 0b0 , any ; # DP18_SYSCLK_ROT_OVERRIDE_EN - - 57 , 0b0 , (def_is_sim) ; # DP18_SYSCLK_PHASE_ALIGN_RESET - 57 , 0b1 , any ; # DP18_SYSCLK_PHASE_ALIGN_RESET - - 58 , 0b0 , (def_is_sim) ; # DP18_SYSCLK_PHASE_CNTL_EN - 58 , 0b1 , any ; # DP18_SYSCLK_PHASE_CNTL_EN - - 59 , 0b0 , (def_is_sim) ; # DP18_SYSCLK_PHASE_DEFAULT_EN - 59 , 0b1 , any ; # DP18_SYSCLK_PHASE_DEFAULT_EN - - 60 , 0b0 , any ; # DP18_SYSCLK_POS_EDGE_ALIGN - 61 , 0b0 , any ; # DP18_CONTINUOUS_UPDATE -# 62:63 , 0b00 , any ; # reserved -} - -# ======================================================================================= -# --- Read clock / WRCLK ENABLE Rank pair P[0:1]_[0:4] -------------------------------- -# ======================================================================================= -# -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0 default=0 -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_0 default=0 -# -# Set according to table in chapter 14.3 of the Centaur_Chip_Spec.pdf -# These are settings for the read and write clock enables of the rank pair for -# x4 & x8 DRAM devices with and without spare DRAMs. -# -# Configuration Requirements: -# 1) If bit 49, 50, or 51 are set, either bit 48 or 52 must also be set. -# 2) If bit 52 is set, then bit 49 or 53 must also be set unless bit 52 was only set to satisfy requirement 1. -# 3) If bit 55 is set, then bit 50, 54, or 56 must also be set. -# 4) If bit 56 is set, then bit 51, 55, or 57 must also be set unless bit 56 was only set to satisfy requirement 3. -# -# [X:Y] represent DP18 lanes(24) -# lanes 0:15 used for dq bits -# lanes 16:23 used for dqs signal pairs (16:17, 18:19, 20:21, 22:23) -# -# if x4 & no swizzle if x8 and no swizzle -# quad0 = dq[0:3] clk16 = dqs[16:17] clk16 = dqs[16:17] -# quad1 = dq[4:7] clk18 = dqs[18:19] clk16 = dqs[16:17] -# quad2 = dq[8:11] clk20 = dqs[20:21] clk20 = dqs[20:21] -# quad3 = dq[12:15] clk22 = dqs[22:23] clk20 = dqs[20:21] -# -# or another way to look at it... -# -# for x4: -# dqs lane pairs 16/17 18/19 20/21 22/23 -# dq quad nibbles 0 1 2 3 // no swizzle -# 1 0 2 3 // swizzle lane pairs 16/17 with 18/19 -# 0 1 3 2 // swizzle lane pairs 20/21 with 22/23 -# 1 0 3 2 // swizzle lane pairs 16/17 with 18/19 & 20/21 with 22/23 -# -# for x8: -# dqs lane pairs 16/17 18/19 20/21 22/23 -# dq quad nibbles 0:1 n/a 2:3 n/a // no swizzle -# n/a 0:1 2:3 n/a // swizzle lane pairs 16/17 with 18/19 -# 0:1 n/a n/a 2:3 // swizzle lane pairs 20/21 with 22/23 -# n/a 0:1 n/a 2:3 // swizzle lane pairs 16/17 with 18/19 & 20/21 with 22/23 -# -# quadx_clk# 16 18 20 22 -# quad# 0 1 2 3 0 1 2 3 2 3 -# ---------------------------------- -# bits 0 1 2 3 4 5 6 7 8 9 10 11 (10:15 unused) -# ============================================================== -# possible spare (x4) Full[both nibbles] -# 0x8640 1 0 0 0 0 1 1 0 0 1 0 0 = x4 no-swizzle, q0=16, q1=18, q2=20, q3=22 -# 0x4A40 0 1 0 0 1 0 1 0 0 1 0 0 = x4 swizzle quad0/1, q0=18, q1=16, q2=20, q3=22 -# 0x8580 1 0 0 0 0 1 0 1 1 0 0 0 = x4 swizzle quad2/3, q0=16, q1=18, q2=22, q3=20 -# 0x4980 0 1 0 0 1 0 0 1 1 0 0 0 = x4 swizzle quad0/1 & 2/3, q0=18, q1=16, q2=22, q3=20 -# -# 0x8600 1 0 0 0 0 1 1 0 0 0 0 0 = x4 no swizzle, disable upper nibble -# 0x8440 1 0 0 0 0 1 0 0 0 1 0 0 = x4 no swizzle, disable lower nibble -# 0x8480 1 0 0 0 0 1 0 0 1 0 0 0 = x4 swizzle quad2/3, disable upper nibble -# 0x8500 1 0 0 0 0 1 0 1 0 0 0 0 = x4 swizzle quad2/3, disable lower nibble -# -# no spare (x4) -# 0x8400 1 0 0 0 0 1 0 0 0 0 0 0 = x4 no-swizzle, q0=16, q1=18, q2=n/a, q3=n/a -# 0x4800 0 1 0 0 1 0 0 0 0 0 0 0 = x4 swizzle quad0/1, q0=18, q1=16, q2=n/a, q3=n/a -# -# possible spare (x8) -# 0xC300 1 1 0 0 0 0 1 1 0 0 0 0 = x8 no-swizzle, q0:1=16, q2:3=20 -# 0x0F00 0 0 0 0 1 1 1 1 0 0 0 0 = x8 swizzle quad0/1, q0:1=18, q2:3=20 -# 0xC0C0 1 1 0 0 0 0 0 0 1 1 0 0 = x8 swizzle quad2/3, q0:1=16, q2:3=22 -# 0x0CC0 0 0 0 0 1 1 0 0 1 1 0 0 = x8 swizzle quad0/1 & 2/3, q0:1=18, q2:3=22 -# -# no spare (x8) -# 0xC000 1 1 0 0 0 0 0 0 0 0 0 0 = x8 no swizzle -# 0x0C00 0 0 0 0 1 1 0 0 0 0 0 0 = x8 swizzle quad0/1 -# -# -# For Centaur: -# Spares on P0_1, P1_2, P2_4, P3_1, DQ in lanes 0:15, DQS in lanes 16:23 -# -# DP18 Read Clock Enable & Selection RP0 -# [01:23] PAIR[0:3]_P[0:1]_[0:4] -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0 0x004 0x800000040301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.RDDP18WRAP.RDDP18CNTL_MAC.R0RDCLKEN_L2 -# 48:51 , 0b1100 ; # Quad[0:3]_CLK16, MEMINTD[0:15,18:23]B(n) -# 52:53 , 0b00 ; # Quad[0:1]_CLK18, MEMINTD[0:7,16,17]B(n) -# 54:55 , 0b11 ; # Quad[2:3]_CLK20, MEMINTD[8:15,22,23]B(n) -# 56:57 , 0b00 ; # Quad[2:3]_CLK22, MEMINTD[8:15,20,21]B(n) -# 58:61 , 0b0000 ; # CLK[16,18,20,22]_SINGLE_ENDED -# 62:63 , 0b00 ; # Reserved -# -# DP18 Write Clock Enable & Selection Register -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_0 0x005 0x800000050301143f -# PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DDRPHY_DP18_WRCLK_EN_RP0_L2 -# same as above, except -# 62:63 , 0b00 ; # Quad[2:3]_CLK18 -# -# instance _0=00, _1=04, _2=08, _3=0C, _4=10 -# RANK_PAIR[0:3], RP[0:3] _P0_0 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_0 (4) 0x800000040301143F -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1 (4) 0x800004040301143F -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2 (4) 0x800008040301143F -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3 (4) 0x80000C040301143F -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4 (4) 0x800010040301143F -# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_0 (5) 0x800000050301143F -# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_1 (5) 0x800004050301143F -# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_2 (5) 0x800008050301143F -# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_3 (5) 0x80000C050301143F -# DPHY01_DRPHY_DP18_WRCLK_EN_RP0_P0_4 (5) 0x800010050301143F -scom 0x8000008(4,5)0301143F { # _RP[0:3] via broadcast bit -# P0_0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0x8580 , ((def_is_mba01) && (def_is_x4)) ; # x4 swizzle quad2/3 - 48:63 , 0xC0C0 , ((def_is_mba01) && (def_is_x8) && (def_is_type1)) ; # x8 swizzle quad 2/3 - 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 no swizzle -# P2_0 - 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 no swizzle - 48:63 , 0x0F00 , ((def_is_mba23) && (def_is_x8)) ; # x8 swizzle quad0/1 - 48:63 , 0x0000 , any ; -} - -# RANK_PAIR[0:3], RP[0:3] _P0_1 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_1 0x800004040301143F -scom 0x800004840301143F { # _RP[0:3] via broadcast bit -# P0_1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved PORT A - 48:63 , 0x8400 , ((def_is_mba01) && (def_p0_no_spare) && (def_is_x4)) ; # x4 no-spare no swizzle -# 48:63 , 0x8580 , ((def_is_mba01) && (def_is_x4)) ; # x4 any spare swizzle quad2/3 - 48:63 , 0x8580 , ((def_is_mba01) && (def_is_x4) && ((def_p0_has_spare_upper) || (def_p0_has_spare_lower))); # x4 spare set - 48:63 , 0x0CC0 , ((def_is_mba01) && (def_p0_has_spare_full) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 - 48:63 , 0x0C00 , ((def_is_mba01) && (def_p0_no_spare) && (def_is_x8)) ; # x8 swizzle quad0/1 -# P2_1 - 48:63 , 0x8580 , ((def_is_mba23) && (def_is_x4)) ; # x4 swizzle quad2/3 - 48:63 , 0xC300 , ((def_is_mba23) && (def_is_x8)) ; # x8 no swizzle - 48:63 , 0x0000 , any ; -} -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_1 0x800004050301143F -scom 0x800004850301143F { # _RP[0:3] via broadcast bit -# P0_1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved PORT A - 48:63 , 0x8580 , ((def_is_mba01) && (def_p0_has_spare_full) && (def_is_x4)) ; # x4 spare swizzle quad2/3 - 48:63 , 0x8500 , ((def_is_mba01) && (def_p0_has_spare_upper) && (def_is_x4)) ; # disable lower dqs - 48:63 , 0x8480 , ((def_is_mba01) && (def_p0_has_spare_lower) && (def_is_x4)) ; # disable upper dqs - 48:63 , 0x8400 , ((def_is_mba01) && (def_p0_no_spare) && (def_is_x4)) ; # x4 no-spare no swizzle - 48:63 , 0x0CC0 , ((def_is_mba01) && (def_p0_has_spare_full) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 - 48:63 , 0x0C00 , ((def_is_mba01) && (def_p0_no_spare) && (def_is_x8)) ; # x8 swizzle quad0/1 -# P2_1 - 48:63 , 0x8580 , ((def_is_mba23) && (def_is_x4)) ; # x4 swizzle quad2/3 - 48:63 , 0xC300 , ((def_is_mba23) && (def_is_x8)) ; # x8 no swizzle - 48:63 , 0x0000 , any ; -} - -# RANK_PAIR[0:3], RP[0:3] _P0_2 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_2 0x800008040301143F -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_2 0x800008050301143F -scom 0x8000088(4,5)0301143F { # _RP[0:3] via broadcast bit -# P0_2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 no swizzle - 48:63 , 0x0CC0 , ((def_is_mba01) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 -# P2_2 - 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 no swizzle - 48:63 , 0x0CC0 , ((def_is_mba23) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 - 48:63 , 0x0000 , any ; -} - -# RANK_PAIR[0:3], RP[0:3] _P0_3 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_3 0x80000C040301143F -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_3 0x80000C050301143F -scom 0x80000C8(4,5)0301143F { # _RP[0:3] via broadcast bit -# P0_3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 no swizzle - 48:63 , 0x0F00 , ((def_is_mba01) && (def_is_x8) && (def_is_type1)) ; # x8 swizzle quad0/1 - 48:63 , 0x0CC0 , ((def_is_mba01) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 -# P2_3 - 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 no swizzle - 48:63 , 0xC0C0 , ((def_is_mba23) && (def_is_x8)) ; # x8 swizzle quad2/3 - 48:63 , 0x0000 , any ; -} - -# RANK_PAIR[0:3], RP[0:3] _P0_4 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P0_4 0x800010040301143F -scom 0x800010840301143F { # _RP[0:3] via broadcast bit -# P0_4 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 no swizzle - 48:63 , 0x0F00 , ((def_is_mba01) && (def_is_x8)) ; # x8 swizzle quad0/1 -# P2_4 - 48:63 , 0x8400 , ((def_is_mba23) && (def_p0_no_spare) && (def_is_x4)) ; # x4 no-spare no swizzle - 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4) && ((def_p0_has_spare_upper) || (def_p0_has_spare_lower))); # x4 spare no swizzle PORT C - 48:63 , 0x0F00 , ((def_is_mba23) && (def_p0_has_spare_full) && (def_is_x8)) ; # x8 swizzle quad0/1 - 48:63 , 0x0C00 , ((def_is_mba23) && (def_p0_no_spare) && (def_is_x8)) ; # x8 swizzle quad0/1 - 48:63 , 0x0000 , any ; -} -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P0_4 0x800010050301143F -scom 0x800010850301143F { # _RP[0:3] via broadcast bit -# P0_4 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 no swizzle - 48:63 , 0x0F00 , ((def_is_mba01) && (def_is_x8)) ; # x8 swizzle quad0/1 -# P2_4 - 48:63 , 0x8640 , ((def_is_mba23) && (def_p0_has_spare_full) && (def_is_x4)) ; # x4 spare no swizzle PORT C - 48:63 , 0x8440 , ((def_is_mba23) && (def_p0_has_spare_upper) && (def_is_x4)) ; # disable lower dqs - 48:63 , 0x8600 , ((def_is_mba23) && (def_p0_has_spare_lower) && (def_is_x4)) ; # disable upper dqs - 48:63 , 0x8400 , ((def_is_mba23) && (def_p0_no_spare) && (def_is_x4)) ; # x4 no-spare no swizzle - 48:63 , 0x0F00 , ((def_is_mba23) && (def_p0_has_spare_full) && (def_is_x8)) ; # x8 swizzle quad0/1 - 48:63 , 0x0C00 , ((def_is_mba23) && (def_p0_no_spare) && (def_is_x8)) ; # x8 swizzle quad0/1 - 48:63 , 0x0000 , any ; -} - -# RANK_PAIR[0:3], RP[0:3] _P1_0 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_0 0x800100840301143F -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_0 0x800100850301143F -scom 0x8001008(4,5)0301143F { # _RP[0:3] via broadcast bit -# P1_0 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0x4A40 , ((def_is_mba01) && (def_is_x4)) ; # x4 swizzle quad0/1 - 48:63 , 0xC0C0 , ((def_is_mba01) && (def_is_x8) && (def_is_type1)) ; # x8 swizzle quad2/3 - 48:63 , 0x0F00 , ((def_is_mba01) && (def_is_x8)) ; # x8 swizzle quad0/1 -# P3_0 - 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 no swizzle - 48:63 , 0xC300 , ((def_is_mba23) && (def_is_x8)) ; # x8 no swizzle - 48:63 , 0x0000 , any ; -} - -# RANK_PAIR[0:3]_, P1_1 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_1 0x800104040301143F -scom 0x800104840301143F { # _RP[0:3] via broadcast bit -# P1_1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4) && (def_is_type1)) ; # x4 no swizzle - 48:63 , 0x4A40 , ((def_is_mba01) && (def_is_x4)) ; # x4 swizzle quad0/1 - 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 no swizzle -# P3_1 - 48:63 , 0x8400 , ((def_is_mba23) && (def_p1_no_spare) && (def_is_x4)) ; # x4 no-spare no swizzle - 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4) && ((def_p1_has_spare_upper) || (def_p1_has_spare_lower))); # x4 spare no swizzle PORT D - 48:63 , 0xC300 , ((def_is_mba23) && (def_p1_has_spare_full) && (def_is_x8)) ; # x8 no swizzle - 48:63 , 0xC000 , ((def_is_mba23) && (def_p1_no_spare) && (def_is_x8)) ; # x8 no swizzle - 48:63 , 0x0000 , any ; -} -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_1 0x800104050301143F -scom 0x800104850301143F { # _RP[0:3] via broadcast bit -# P1_1 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4) && (def_is_type1)) ; # x4 no swizzle - 48:63 , 0x4A40 , ((def_is_mba01) && (def_is_x4)) ; # x4 swizzle quad0/1 - 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 no swizzle -# P3_1 - 48:63 , 0x8640 , ((def_is_mba23) && (def_p1_has_spare_full) && (def_is_x4)) ; # x4 spare no swizzle PORT D - 48:63 , 0x8440 , ((def_is_mba23) && (def_p1_has_spare_upper) && (def_is_x4)) ; # disable lower dqs - 48:63 , 0x8600 , ((def_is_mba23) && (def_p1_has_spare_lower) && (def_is_x4)) ; # disable upper dqs - 48:63 , 0x8400 , ((def_is_mba23) && (def_p1_no_spare) && (def_is_x4)) ; # x4 no-spare no swizzle - 48:63 , 0xC300 , ((def_is_mba23) && (def_p1_has_spare_full) && (def_is_x8)) ; # x8 no swizzle - 48:63 , 0xC000 , ((def_is_mba23) && (def_p1_no_spare) && (def_is_x8)) ; # x8 no swizzle - 48:63 , 0x0000 , any ; -} - -# RANK_PAIR[0:3], RP[0:3] _P1_2 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_2 0x800108040301143F -scom 0x800108840301143F { # _RP[0:3] via broadcast bit -# P1_2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0x8400 , ((def_is_mba01) && (def_p1_no_spare) && (def_is_x4)) ; # x4 no-spare no swizzle - 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4) && ((def_p1_has_spare_upper) || (def_p1_has_spare_lower))); # x4 spare no swizzle - 48:63 , 0x0CC0 , ((def_is_mba01) && (def_p1_has_spare_full) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 - 48:63 , 0x0C00 , ((def_is_mba01) && (def_p1_no_spare) && (def_is_x8)) ; # x8 swizzle quad0/1 -# P3_2 - 48:63 , 0x8580 , ((def_is_mba23) && (def_is_x4)) ; # x4 swizzle quad2/3 - 48:63 , 0x0F00 , ((def_is_mba23) && (def_is_x8)) ; # x8 swizzle quad0/1 - 48:63 , 0x0000 , any ; -} -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_2 0x800108050301143F -scom 0x800108850301143F { # _RP[0:3] via broadcast bit -# P1_2 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0x8640 , ((def_is_mba01) && (def_p1_has_spare_full) && (def_is_x4)) ; # x4 spare no swizzle - 48:63 , 0x8600 , ((def_is_mba01) && (def_p1_has_spare_upper) && (def_is_x4)) ; # disable lower dqs - 48:63 , 0x8440 , ((def_is_mba01) && (def_p1_has_spare_lower) && (def_is_x4)) ; # disable upper dqs - 48:63 , 0x8400 , ((def_is_mba01) && (def_p1_no_spare) && (def_is_x4)) ; # x4 no-spare no swizzle - 48:63 , 0x0CC0 , ((def_is_mba01) && (def_p1_has_spare_full) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 - 48:63 , 0x0C00 , ((def_is_mba01) && (def_p1_no_spare) && (def_is_x8)) ; # x8 swizzle quad0/1 -# P3_2 - 48:63 , 0x8580 , ((def_is_mba23) && (def_is_x4)) ; # x4 swizzle quad2/3 - 48:63 , 0x0F00 , ((def_is_mba23) && (def_is_x8)) ; # x8 swizzle quad0/1 - 48:63 , 0x0000 , any ; -} - -# RANK_PAIR[0:3], RP[0:3] _P1_3 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_3 0x80010C040301143F -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_3 0x80010C050301143F -scom 0x80010C8(4,5)0301143F { # _RP[0:3] via broadcast bit -# P1_3 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0x8640 , ((def_is_mba01) && (def_is_x4)) ; # x4 no swizzle - 48:63 , 0xC0C0 , ((def_is_mba01) && (def_is_x8) && (def_is_type1)) ; # x8 swizzle quad2/3 - 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 no swizzle -# P3_3 - 48:63 , 0x4A40 , ((def_is_mba23) && (def_is_x4)) ; # x4 swizzle quad0/1 - 48:63 , 0xC300 , ((def_is_mba23) && (def_is_x8)) ; # x8 no swizzle - 48:63 , 0x0000 , any ; -} - -# RANK_PAIR[0:3], RP[0:3] _P1_4 -# DPHY01_DDRPHY_DP18_READ_CLOCK_RANK_PAIR0_P1_4 0x800110040301143F -# DPHY01_DDRPHY_DP18_WRCLK_EN_RP0_P1_4 0x800110050301143F -scom 0x8001108(4,5)0301143F { # _RP[0:3] via broadcast bit -# P1_4 - bits , scom_data , expr ; -# 0:47 , 0x000000000000, any ; # reserved - 48:63 , 0x8580 , ((def_is_mba01) && (def_is_x4)) ; # x4 swizzle quad2/3 - 48:63 , 0xC300 , ((def_is_mba01) && (def_is_x8)) ; # x8 no swizzle -# P3_4 - 48:63 , 0x8640 , ((def_is_mba23) && (def_is_x4)) ; # x4 no swizzle - 48:63 , 0x0CC0 , ((def_is_mba23) && (def_is_x8)) ; # x8 swizzle quad0/1 & 2/3 - 48:63 , 0x0000 , any ; -} diff --git a/src/usr/hwpf/hwp/initfiles/edi.io.define b/src/usr/hwpf/hwp/initfiles/edi.io.define deleted file mode 100644 index 01069c598..000000000 --- a/src/usr/hwpf/hwp/initfiles/edi.io.define +++ /dev/null @@ -1,1014 +0,0 @@ -define tx_mode_pl_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_lane_pdwn=48:48; #start_bit=48, number_of_bit=1 -define tx_lane_invert=49:49; #start_bit=49, number_of_bit=1 -define tx_lane_quiesce_p=50:51; #start_bit=50, number_of_bit=2 -define tx_lane_quiesce_n=52:53; #start_bit=52, number_of_bit=2 -define tx_lane_scramble_disable=54:54; #start_bit=54, number_of_bit=1 -#define #tx_lane_error_inject_mode=58:63; #start_bit=58, number_of_bit=6 -define tx_fifo_err=48:48; #start_bit=48, number_of_bit=1 -define tx_pdwn_lite_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 -define tx_pl_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 -define tx_pl_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 -define tx_pl_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 -define tx_pl_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 -define tx_pl_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 -define tx_pl_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 -#define #tx_lane_id=48:52; #start_bit=48, number_of_bit=5 -define tx_lane_bist_err=48:48; #start_bit=48, number_of_bit=1 -define tx_lane_bist_done=49:49; #start_bit=49, number_of_bit=1 -define tx_pl_fir_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_pl_fir_errs=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_fir_err_pl_regs=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_fir_errs_mask_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_pl_fir_errs_mask=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_fir_err_mask_pl_regs=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_fir_err_inj_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_pl_fir_err_inj=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_fir_err_inj_pl_regs=48:48; #start_bit=48, number_of_bit=1 -define tx_prbs_tap_id=48:50; #start_bit=48, number_of_bit=3 -define tx_drv_data_pattern_gcrmsg=48:51; #start_bit=48, number_of_bit=4 -define tx_drv_func_data_gcrmsg=52:52; #start_bit=52, number_of_bit=1 -define tx_sls_lane_sel_gcrmsg=53:53; #start_bit=53, number_of_bit=1 -define tx_err_inj_a_enable=52:52; #start_bit=52, number_of_bit=1 -define tx_err_inj_b_enable=53:53; #start_bit=53, number_of_bit=1 -define tx_tdr_capt_val=48:48; #start_bit=48, number_of_bit=1 -define tx_clk_pdwn=48:48; #start_bit=48, number_of_bit=1 -define tx_clk_invert=49:49; #start_bit=49, number_of_bit=1 -define tx_clk_quiesce_p=50:51; #start_bit=50, number_of_bit=2 -define tx_clk_quiesce_n=52:53; #start_bit=52, number_of_bit=2 -define tx_clk_ddr_mode=54:54; #start_bit=54, number_of_bit=1 -define tx_pg_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 -define tx_pg_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 -define tx_pg_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 -define tx_pg_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 -define tx_pg_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 -define tx_pg_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 -define tx_pg_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 -define tx_pg_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 -define tx_clk_bist_err=49:49; #start_bit=49, number_of_bit=1 -define tx_clk_bist_done=51:51; #start_bit=51, number_of_bit=1 -#define #tx_cntl_stat_pg_spare=48:48; #start_bit=48, number_of_bit=1 -define tx_max_bad_lanes=48:52; #start_bit=48, number_of_bit=5 -define tx_msbswap=53:53; #start_bit=53, number_of_bit=1 -define tx_pdwn_lite_disable=54:54; #start_bit=54, number_of_bit=1 -define tx_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 -define tx_fir_reset=63:63; #start_bit=63, number_of_bit=1 -define tx_pg_fir_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_pg_fir_errs=48:55; #start_bit=48, number_of_bit=8 -define tx_pg_fir_err_pg_regs=48:48; #start_bit=48, number_of_bit=1 -define tx_pg_fir_err_gcr_buff=49:49; #start_bit=49, number_of_bit=1 -define tx_pg_fir_err_stat_rpr_snd_msg_sm=51:51; #start_bit=51, number_of_bit=1 -define tx_pg_fir_err_gcrs_ld_sm=52:52; #start_bit=52, number_of_bit=1 -define tx_pg_fir_err_gcrs_unld_sm=53:53; #start_bit=53, number_of_bit=1 -define tx_pl_fir_err=63:63; #start_bit=63, number_of_bit=1 -define tx_pg_fir_err_mask_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_pg_fir_errs_mask=48:55; #start_bit=48, number_of_bit=8 -define tx_pg_fir_err_mask_pg_regs=48:48; #start_bit=48, number_of_bit=1 -define tx_pg_fir_err_mask_gcr_buff=49:49; #start_bit=49, number_of_bit=1 -define tx_pg_fir_err_mask_stat_rpr_snd_msg_sm=51:51; #start_bit=51, number_of_bit=1 -define tx_pg_fir_err_mask_gcrs_ld_sm=52:52; #start_bit=52, number_of_bit=1 -define tx_pg_fir_err_mask_gcrs_unld_sm=53:53; #start_bit=53, number_of_bit=1 -define tx_pl_fir_err_mask=63:63; #start_bit=63, number_of_bit=1 -define tx_pg_fir_err_inj_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_pg_fir_err_inj=48:55; #start_bit=48, number_of_bit=8 -define tx_pg_fir_err_inj_pg_regs=48:48; #start_bit=48, number_of_bit=1 -define tx_pg_fir_err_inj_gcr_buff=49:49; #start_bit=49, number_of_bit=1 -define tx_pg_fir_err_inj_stat_rpr_snd_msg_sm=51:51; #start_bit=51, number_of_bit=1 -define tx_pg_fir_err_inj_gcrs_ld_sm=52:52; #start_bit=52, number_of_bit=1 -define tx_pg_fir_err_inj_gcrs_unld_sm=53:53; #start_bit=53, number_of_bit=1 -define tx_bus_id=48:53; #start_bit=48, number_of_bit=6 -define tx_group_id=55:60; #start_bit=55, number_of_bit=6 -define tx_last_group_id=48:53; #start_bit=48, number_of_bit=6 -define tx_start_lane_id=49:55; #start_bit=49, number_of_bit=7 -define tx_end_lane_id=57:63; #start_bit=57, number_of_bit=7 -define tx_drv_clk_pattern_gcrmsg=48:49; #start_bit=48, number_of_bit=2 -define tx_wt_en_all_clk_segs_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define tx_wt_en_all_data_segs_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define tx_ffe_test_mode=50:51; #start_bit=50, number_of_bit=2 -define tx_ffe_test_override1r=54:54; #start_bit=54, number_of_bit=1 -define tx_ffe_test_override2r=55:55; #start_bit=55, number_of_bit=1 -define tx_ffe_main_p_enc=49:55; #start_bit=49, number_of_bit=7 -define tx_ffe_main_n_enc=57:63; #start_bit=57, number_of_bit=7 -define tx_ffe_post_p_enc=51:55; #start_bit=51, number_of_bit=5 -define tx_ffe_post_n_enc=59:63; #start_bit=59, number_of_bit=5 -define tx_ffe_margin_p_enc=51:55; #start_bit=51, number_of_bit=5 -define tx_ffe_margin_n_enc=59:63; #start_bit=59, number_of_bit=5 -define tx_bad_lane1_gcrmsg=48:54; #start_bit=48, number_of_bit=7 -define tx_bad_lane2_gcrmsg=55:61; #start_bit=55, number_of_bit=7 -define tx_bad_lane_code_gcrmsg=62:63; #start_bit=62, number_of_bit=2 -define tx_sls_lane_gcrmsg=48:54; #start_bit=48, number_of_bit=7 -define tx_sls_lane_val_gcrmsg=55:55; #start_bit=55, number_of_bit=1 -define tx_lane_disabled_vec_0_15=48:63; #start_bit=48, number_of_bit=16 -define tx_lane_disabled_vec_16_31=48:63; #start_bit=48, number_of_bit=16 -define tx_sls_lane_shdw_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define tx_sls_hndshk_state=48:52; #start_bit=48, number_of_bit=5 -define tx_slv_mv_sls_shdw_req_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define tx_slv_mv_sls_shdw_rpr_req_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define tx_slv_mv_sls_unshdw_req_gcrmsg=50:50; #start_bit=50, number_of_bit=1 -define tx_slv_mv_sls_unshdw_rpr_req_gcrmsg=51:51; #start_bit=51, number_of_bit=1 -define tx_bus_width=52:58; #start_bit=52, number_of_bit=7 -define tx_slv_mv_sls_rpr_req_gcrmsg=59:59; #start_bit=59, number_of_bit=1 -define tx_sls_lane_sel_lg_gcrmsg=60:60; #start_bit=60, number_of_bit=1 -define tx_sls_lane_unsel_lg_gcrmsg=61:61; #start_bit=61, number_of_bit=1 -define tx_spr_lns_pdwn_lite_gcrmsg=62:62; #start_bit=62, number_of_bit=1 -define tx_wt_pattern_length=48:49; #start_bit=48, number_of_bit=2 -define tx_reduced_scramble_mode=48:49; #start_bit=48, number_of_bit=2 -define tx_prbs_scramble_mode=50:51; #start_bit=50, number_of_bit=2 -define tx_fifo_l2u_dly=52:54; #start_bit=52, number_of_bit=3 -define tx_bist_en=48:48; #start_bit=48, number_of_bit=1 -define tx_bist_clr=49:49; #start_bit=49, number_of_bit=1 -define tx_snd_sls_cmd_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define tx_dyn_recal_tsr_ignore_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define tx_sls_cmd_gcrmsg=50:55; #start_bit=50, number_of_bit=6 -define tx_snd_sls_cmd_prev_gcrmsg=56:56; #start_bit=56, number_of_bit=1 -define tx_snd_sls_using_reg_scramble=57:57; #start_bit=57, number_of_bit=1 -define tx_err_inj_a_rand_beat_dis=48:48; #start_bit=48, number_of_bit=1 -define tx_err_inj_a_fine_sel=49:51; #start_bit=49, number_of_bit=3 -define tx_err_inj_a_coarse_sel=52:55; #start_bit=52, number_of_bit=4 -define tx_err_inj_a_ber_sel=58:63; #start_bit=58, number_of_bit=6 -define tx_err_inj_b_rand_beat_dis=48:48; #start_bit=48, number_of_bit=1 -define tx_err_inj_b_fine_sel=49:51; #start_bit=49, number_of_bit=3 -define tx_err_inj_b_coarse_sel=52:55; #start_bit=52, number_of_bit=4 -define tx_err_inj_b_ber_sel=58:63; #start_bit=58, number_of_bit=6 -define tx_err_inj_sls_mode=48:48; #start_bit=48, number_of_bit=1 -define tx_err_inj_sls_all_cmd=49:49; #start_bit=49, number_of_bit=1 -define tx_err_inj_sls_recal=50:50; #start_bit=50, number_of_bit=1 -define tx_err_inj_sls_cmd=58:63; #start_bit=58, number_of_bit=6 -define tx_dyn_recal_interval_timeout_sel=49:51; #start_bit=49, number_of_bit=3 -define tx_dyn_recal_status_rpt_timeout_sel=52:53; #start_bit=52, number_of_bit=2 -define tx_enable_reduced_scramble=48:48; #start_bit=48, number_of_bit=1 -define tx_reset_cfg_hld=48:63; #start_bit=48, number_of_bit=16 -define tx_tdr_dac_cntl=48:55; #start_bit=48, number_of_bit=8 -define tx_tdr_phase_sel=57:57; #start_bit=57, number_of_bit=1 -define tx_tdr_pulse_offset=48:59; #start_bit=48, number_of_bit=12 -define tx_tdr_pulse_width=48:59; #start_bit=48, number_of_bit=12 -#define #tx_zcal_spare=48:48; #start_bit=48, number_of_bit=1 -define tx_zcal_done=50:50; #start_bit=50, number_of_bit=1 -define tx_zcal_error=51:51; #start_bit=51, number_of_bit=1 -define tx_zcal_busy=52:52; #start_bit=52, number_of_bit=1 -define tx_zcal_cmp_out=54:54; #start_bit=54, number_of_bit=1 -define tx_zcal_sample_cnt=55:63; #start_bit=55, number_of_bit=9 -define tx_zcal_n=48:56; #start_bit=48, number_of_bit=9 -define tx_zcal_p=48:56; #start_bit=48, number_of_bit=9 -define tx_zcal_p_4x=48:52; #start_bit=48, number_of_bit=5 -define tx_zcal_swo_en=48:48; #start_bit=48, number_of_bit=1 -define tx_zcal_swo_cal_segs=49:49; #start_bit=49, number_of_bit=1 -define tx_zcal_swo_cmp_inv=50:50; #start_bit=50, number_of_bit=1 -define tx_zcal_swo_cmp_offset=51:51; #start_bit=51, number_of_bit=1 -define tx_zcal_swo_cmp_reset=52:52; #start_bit=52, number_of_bit=1 -define tx_zcal_swo_powerdown=53:53; #start_bit=53, number_of_bit=1 -define tx_zcal_cya_data_inv=54:54; #start_bit=54, number_of_bit=1 -define tx_zcal_test_ovr_2r=55:55; #start_bit=55, number_of_bit=1 -define tx_zcal_debug_mode=62:63; #start_bit=62, number_of_bit=2 -define tx_zcal_sm_min_val=48:54; #start_bit=48, number_of_bit=7 -define tx_zcal_sm_max_val=55:61; #start_bit=55, number_of_bit=7 -define tx_iref_bc=48:50; #start_bit=48, number_of_bit=3 -define tx_minikerf=48:63; #start_bit=48, number_of_bit=16 -define tx_init_version=48:63; #start_bit=48, number_of_bit=16 -define tx_scratch_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_mode_pl_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_lane_pdwn=48:48; #start_bit=48, number_of_bit=1 -#define #rx_lane_invert=49:49; #start_bit=49, number_of_bit=1 -#define #rx_lane_known_bad=50:50; #start_bit=50, number_of_bit=1 -define rx_lane_scramble_disable=54:54; #start_bit=54, number_of_bit=1 -define rx_block_lock_lane=48:48; #start_bit=48, number_of_bit=1 -define rx_check_skew_lane=49:49; #start_bit=49, number_of_bit=1 -define rx_pdwn_lite=50:50; #start_bit=50, number_of_bit=1 -define rx_offcal_mode=51:51; #start_bit=51, number_of_bit=1 -define rx_pl_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 -define rx_pl_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 -define rx_pl_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 -define rx_pl_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 -define rx_pl_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 -define rx_pl_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 -define rx_pl_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 -define rx_pl_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 -#define #rx_lane_id_pl=48:52; #start_bit=48, number_of_bit=5 -define rx_bist_err=48:48; #start_bit=48, number_of_bit=1 -define rx_bist_done=49:49; #start_bit=49, number_of_bit=1 -#define #rx_eyeopt_stat_tbd=48:48; #start_bit=48, number_of_bit=1 -define rx_offset_even_samp1=49:55; #start_bit=49, number_of_bit=7 -define rx_offset_even_samp0=57:63; #start_bit=57, number_of_bit=7 -define rx_offset_odd_samp1=49:55; #start_bit=49, number_of_bit=7 -define rx_offset_odd_samp0=57:63; #start_bit=57, number_of_bit=7 -#define #rx_amp_peak=48:51; #start_bit=48, number_of_bit=4 -define rx_amp_peak=48:51; #start_bit=48, number_of_bit=4 -define rx_amp_gain=52:55; #start_bit=52, number_of_bit=4 -define rx_amp_offset=58:63; #start_bit=58, number_of_bit=6 -define rx_amp_adj_done=48:48; #start_bit=48, number_of_bit=1 -define rx_amp_adj_all_done_b=49:49; #start_bit=49, number_of_bit=1 -#define #rx_wiretest_lane_bad=48:48; #start_bit=48, number_of_bit=1 -#define #rx_lane_inverted=49:49; #start_bit=49, number_of_bit=1 -#define #rx_lane_fault_details=52:54; #start_bit=52, number_of_bit=3 -define rx_fifo_l2u_dly=48:51; #start_bit=48, number_of_bit=4 -#define #rx_fifo_cntl_spare=51:51; #start_bit=51, number_of_bit=1 -define rx_bad_block_lock=48:48; #start_bit=48, number_of_bit=1 -define rx_bad_skew=49:49; #start_bit=49, number_of_bit=1 -define rx_bad_deskew=50:50; #start_bit=50, number_of_bit=1 -define rx_bad_eye_opt_ber=48:48; #start_bit=48, number_of_bit=1 -define rx_bad_eye_opt_width=49:49; #start_bit=49, number_of_bit=1 -define rx_bad_eye_opt_height=50:50; #start_bit=50, number_of_bit=1 -define rx_bad_eye_opt_ddc=51:51; #start_bit=51, number_of_bit=1 -define rx_ap_even_samp=48:55; #start_bit=48, number_of_bit=8 -define rx_ap_odd_samp=56:63; #start_bit=56, number_of_bit=8 -define rx_an_even_samp=48:55; #start_bit=48, number_of_bit=8 -define rx_an_odd_samp=56:63; #start_bit=56, number_of_bit=8 -define rx_dfe_clkadj=48:51; #start_bit=48, number_of_bit=4 -define rx_amin_even=48:55; #start_bit=48, number_of_bit=8 -define rx_amin_odd=56:63; #start_bit=56, number_of_bit=8 -define rx_h1_even_samp1=49:55; #start_bit=49, number_of_bit=7 -define rx_h1_even_samp0=57:63; #start_bit=57, number_of_bit=7 -define rx_h1_odd_samp1=49:55; #start_bit=49, number_of_bit=7 -define rx_h1_odd_samp0=57:63; #start_bit=57, number_of_bit=7 -define rx_pl_fir_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_pl_fir_errs=48:49; #start_bit=48, number_of_bit=2 -define rx_pl_fir_err_pl_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pl_fir_err_ddc_sm=49:49; #start_bit=49, number_of_bit=1 -define rx_pl_fir_errs_mask_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_pl_fir_errs_mask=48:49; #start_bit=48, number_of_bit=2 -define rx_pl_fir_err_mask_pl_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pl_fir_err_mask_ddc_sm=49:49; #start_bit=49, number_of_bit=1 -define rx_pl_fir_err_inj_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_pl_fir_err_inj=48:49; #start_bit=48, number_of_bit=2 -define rx_pl_fir_err_inj_pl_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pl_fir_err_inj_ddc_sm=49:49; #start_bit=49, number_of_bit=1 -define rx_prbs_tap_id=48:50; #start_bit=48, number_of_bit=3 -define rx_some_block_locked=48:48; #start_bit=48, number_of_bit=1 -define rx_all_block_locked_b=49:49; #start_bit=49, number_of_bit=1 -define rx_some_skew_valid=50:50; #start_bit=50, number_of_bit=1 -define rx_all_skew_valid_b=51:51; #start_bit=51, number_of_bit=1 -define rx_some_prbs_synced=52:52; #start_bit=52, number_of_bit=1 -define rx_prbs_synced_b=53:53; #start_bit=53, number_of_bit=1 -define rx_skew_value=54:59; #start_bit=54, number_of_bit=6 -define rx_sls_lane_sel=48:48; #start_bit=48, number_of_bit=1 -define rx_9th_pattern_en=49:49; #start_bit=49, number_of_bit=1 -define rx_wt_lane_disabled=48:48; #start_bit=48, number_of_bit=1 -define rx_wt_lane_inverted=49:49; #start_bit=49, number_of_bit=1 -define rx_wt_lane_bad_code=50:52; #start_bit=50, number_of_bit=3 -define rx_wt_lane_status_alias=49:52; #start_bit=49, number_of_bit=4 -define rx_bump_left_half_ui=48:48; #start_bit=48, number_of_bit=1 -define rx_bump_right_half_ui=49:49; #start_bit=49, number_of_bit=1 -define rx_bump_one_ui=50:50; #start_bit=50, number_of_bit=1 -define rx_bump_two_ui=51:51; #start_bit=51, number_of_bit=1 -define rx_phaserot_offset=50:55; #start_bit=50, number_of_bit=6 -define rx_phaserot_val=50:55; #start_bit=50, number_of_bit=6 -define rx_phaserot_ddc_complete=56:56; #start_bit=56, number_of_bit=1 -define rx_phaserot_block_lock_err=57:57; #start_bit=57, number_of_bit=1 -define rx_phaserot_left_edge=50:55; #start_bit=50, number_of_bit=6 -define rx_phaserot_right_edge=56:61; #start_bit=56, number_of_bit=6 -#define #rx_phaserot_gb_hist_valid=48:48; #start_bit=48, number_of_bit=1 -#define #rx_phaserot_gb_hist=52:55; #start_bit=52, number_of_bit=4 -define rx_eye_width=50:55; #start_bit=50, number_of_bit=6 -define rx_hist_min_eye_width_valid=56:56; #start_bit=56, number_of_bit=1 -define rx_hist_min_eye_width=58:63; #start_bit=58, number_of_bit=6 -define rx_ber_count=48:55; #start_bit=48, number_of_bit=8 -define rx_ber_count_saturated=56:56; #start_bit=56, number_of_bit=1 -define rx_ber_count_frozen_by_lane=57:57; #start_bit=57, number_of_bit=1 -define rx_ber_count_frozen_by_timer=58:58; #start_bit=58, number_of_bit=1 -define rx_ber_timer_saturated=59:59; #start_bit=59, number_of_bit=1 -define rx_ber_timer_value_0_15=48:63; #start_bit=48, number_of_bit=16 -define rx_ber_timer_value_16_31=48:63; #start_bit=48, number_of_bit=16 -define rx_ber_timer_value_32_39=48:55; #start_bit=48, number_of_bit=8 -define rx_servo_op_done=48:48; #start_bit=48, number_of_bit=1 -define rx_servo_op_all_done_b=49:49; #start_bit=49, number_of_bit=1 -define rx_servo_op=50:54; #start_bit=50, number_of_bit=5 -define rx_scope_en=55:55; #start_bit=55, number_of_bit=1 -define rx_fifo_out_0_15=48:63; #start_bit=48, number_of_bit=16 -define rx_fifo_out_16_31=48:63; #start_bit=48, number_of_bit=16 -define rx_fifo_out_32_47=48:63; #start_bit=48, number_of_bit=16 -define rx_ln_trc_en=48:48; #start_bit=48, number_of_bit=1 -define rx_servo_ber_count=48:59; #start_bit=48, number_of_bit=12 -define rx_clk_pdwn=48:48; #start_bit=48, number_of_bit=1 -define rx_clk_invert=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 -define rx_pg_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 -#define #rx_pg_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 -#define #rx_pg_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 -#define #rx_pg_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 -define rx_sls_extend_sel=53:55; #start_bit=53, number_of_bit=3 -define rx_master_mode=48:48; #start_bit=48, number_of_bit=1 -define rx_disable_fence_reset=49:49; #start_bit=49, number_of_bit=1 -define rx_pdwn_lite_disable=50:50; #start_bit=50, number_of_bit=1 -define rx_use_sls_as_spr=51:51; #start_bit=51, number_of_bit=1 -define rx_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 -define rx_fir_reset=63:63; #start_bit=63, number_of_bit=1 -define rx_bus_id=48:53; #start_bit=48, number_of_bit=6 -define rx_group_id=55:60; #start_bit=55, number_of_bit=6 -define rx_last_group_id=48:53; #start_bit=48, number_of_bit=6 -define rx_start_lane_id=49:55; #start_bit=49, number_of_bit=7 -define rx_end_lane_id=57:63; #start_bit=57, number_of_bit=7 -define rx_minikerf=48:63; #start_bit=48, number_of_bit=16 -define rx_sls_disable=48:48; #start_bit=48, number_of_bit=1 -define tx_sls_disable=49:49; #start_bit=49, number_of_bit=1 -define rx_sls_cntr_tap_pts=50:51; #start_bit=50, number_of_bit=2 -define rx_nonsls_cntr_tap_pts=52:53; #start_bit=52, number_of_bit=2 -define rx_sls_err_chk_run=54:54; #start_bit=54, number_of_bit=1 -define rx_start_wderf_alias=48:52; #start_bit=48, number_of_bit=5 -define rx_start_wiretest=48:48; #start_bit=48, number_of_bit=1 -define rx_start_deskew=49:49; #start_bit=49, number_of_bit=1 -define rx_start_eye_opt=50:50; #start_bit=50, number_of_bit=1 -define rx_start_repair=51:51; #start_bit=51, number_of_bit=1 -define rx_start_func_mode=52:52; #start_bit=52, number_of_bit=1 -define rx_start_bist=53:53; #start_bit=53, number_of_bit=1 -define rx_start_offset_cal=54:54; #start_bit=54, number_of_bit=1 -define rx_start_wt_bypass=55:55; #start_bit=55, number_of_bit=1 -define rx_wderf_done_alias=48:52; #start_bit=48, number_of_bit=5 -define rx_wiretest_done=48:48; #start_bit=48, number_of_bit=1 -define rx_deskew_done=49:49; #start_bit=49, number_of_bit=1 -define rx_eye_opt_done=50:50; #start_bit=50, number_of_bit=1 -define rx_repair_done=51:51; #start_bit=51, number_of_bit=1 -define rx_func_mode_done=52:52; #start_bit=52, number_of_bit=1 -define rx_bist_started=53:53; #start_bit=53, number_of_bit=1 -define rx_offset_cal_done=54:54; #start_bit=54, number_of_bit=1 -define rx_wt_bypass_done=55:55; #start_bit=55, number_of_bit=1 -define rx_wderf_failed_alias=56:60; #start_bit=56, number_of_bit=5 -define rx_wiretest_failed=56:56; #start_bit=56, number_of_bit=1 -define rx_deskew_failed=57:57; #start_bit=57, number_of_bit=1 -define rx_eye_opt_failed=58:58; #start_bit=58, number_of_bit=1 -define rx_repair_failed=59:59; #start_bit=59, number_of_bit=1 -define rx_func_mode_failed=60:60; #start_bit=60, number_of_bit=1 -define rx_start_bist_failed=61:61; #start_bit=61, number_of_bit=1 -define rx_offset_cal_failed=62:62; #start_bit=62, number_of_bit=1 -define rx_wt_bypass_failed=63:63; #start_bit=63, number_of_bit=1 -define rx_recal_status=48:63; #start_bit=48, number_of_bit=16 -define rx_wt_check_count=48:52; #start_bit=48, number_of_bit=5 -define rx_wt_check_lanes=53:54; #start_bit=53, number_of_bit=2 -define rx_sls_timeout_sel=48:50; #start_bit=48, number_of_bit=3 -define rx_sls_timeout_sel_dd2=48:51; #start_bit=49, number_of_bit=4 -define rx_ds_bl_timeout_sel=51:53; #start_bit=51, number_of_bit=3 -define rx_ds_bl_timeout_sel_dd2=52:54; #start_bit=52, number_of_bit=3 -define rx_cl_timeout_sel=54:56; #start_bit=54, number_of_bit=3 -define rx_cl_timeout_sel_dd2=55:57; #start_bit=55, number_of_bit=3 -define rx_wt_timeout_sel=57:59; #start_bit=57, number_of_bit=3 -define rx_wt_timeout_sel_dd2=58:60; #start_bit=58, number_of_bit=3 -define rx_ds_timeout_sel=60:62; #start_bit=60, number_of_bit=3 -define rx_ds_timeout_sel_dd2=61:63; #start_bit=61, number_of_bit=3 -define rx_eo_offset_timeout_sel=48:50; #start_bit=48, number_of_bit=3 -define rx_eo_amp_timeout_sel=51:53; #start_bit=51, number_of_bit=3 -define rx_eo_ctle_timeout_sel=54:56; #start_bit=54, number_of_bit=3 -define rx_eo_h1ap_timeout_sel=57:59; #start_bit=57, number_of_bit=3 -define rx_eo_ddc_timeout_sel=60:62; #start_bit=60, number_of_bit=3 -define rx_eo_final_l2u_timeout_sel=63:63; #start_bit=63, number_of_bit=1 -define rx_func_mode_timeout_sel=48:50; #start_bit=48, number_of_bit=3 -define rx_rc_slowdown_timeout_sel=51:53; #start_bit=51, number_of_bit=3 -define rx_pup_lite_wait_sel=54:55; #start_bit=54, number_of_bit=2 -define rx_fifo_initial_l2u_dly=48:51; #start_bit=48, number_of_bit=4 -define rx_fifo_final_l2u_dly=52:55; #start_bit=52, number_of_bit=4 -define rx_fifo_max_deskew=56:59; #start_bit=56, number_of_bit=4 -define rx_fifo_final_l2u_min_err_thresh=60:61; #start_bit=60, number_of_bit=2 -#define #rx_start_at_state_en=48:48; #start_bit=48, number_of_bit=1 -#define #rx_stop_at_state_en=49:49; #start_bit=49, number_of_bit=1 -#define #rx_state_stopped=50:50; #start_bit=50, number_of_bit=1 -#define #rx_cur_state=51:58; #start_bit=51, number_of_bit=8 -#define #rx_start_state=48:55; #start_bit=48, number_of_bit=8 -#define #rx_stop_state=56:63; #start_bit=56, number_of_bit=8 -define rx_sls_cmd_val=48:48; #start_bit=48, number_of_bit=1 -define rx_sls_cmd_encode=50:55; #start_bit=50, number_of_bit=6 -define rx_sls_err_chk_cnt=56:63; #start_bit=56, number_of_bit=8 -define rx_pg_fir_training_error=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_static_spare_deployed=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_static_max_spares_exceeded=50:50; #start_bit=50, number_of_bit=1 -define rx_pg_fir_dynamic_repair_error=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_dynamic_spare_deployed=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_dynamic_max_spares_exceeded=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_recal_error=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir_recal_spare_deployed=55:55; #start_bit=55, number_of_bit=1 -define rx_pg_fir_recal_max_spares_exceeded=56:56; #start_bit=56, number_of_bit=1 -define rx_pg_fir_too_many_bus_errors=57:57; #start_bit=57, number_of_bit=1 -define rx_pg_fir_training_error_mask=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_static_spare_deployed_mask=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_static_max_spares_exceeded_mask=50:50; #start_bit=50, number_of_bit=1 -define rx_pg_fir_dynamic_repair_error_mask=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_dynamic_spare_deployed_mask=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_dynamic_max_spares_exceeded_mask=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_recal_error_mask=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir_recal_spare_deployed_mask=55:55; #start_bit=55, number_of_bit=1 -define rx_pg_fir_recal_max_spares_exceeded_mask=56:56; #start_bit=56, number_of_bit=1 -define rx_pg_fir_too_many_bus_errors_mask=57:57; #start_bit=57, number_of_bit=1 -define rx_pg_fir1_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_pg_fir1_errs=48:61; #start_bit=48, number_of_bit=14 -define rx_pg_fir_err_pg_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_err_gcr_buff=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_err_gcrs_ld_sm=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_err_gcrs_unld_sm=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_err_glb_init_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_err_main_init_sm=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir_err_wtm_sm=55:55; #start_bit=55, number_of_bit=1 -define rx_pg_fir_err_wtr_sm=56:56; #start_bit=56, number_of_bit=1 -define rx_pg_fir_err_wtl_sm=57:57; #start_bit=57, number_of_bit=1 -define rx_pg_fir_err_rpr_sm=58:58; #start_bit=58, number_of_bit=1 -define rx_pg_fir_err_eyeopt_sm=59:59; #start_bit=59, number_of_bit=1 -define rx_pg_fir_err_dsm_sm=60:60; #start_bit=60, number_of_bit=1 -define rx_pg_fir_err_rxdsm_sm=61:61; #start_bit=61, number_of_bit=1 -define rx_pg_chan_fail_rsvd=62:62; #start_bit=62, number_of_bit=1 -define rx_pl_fir_err=63:63; #start_bit=63, number_of_bit=1 -define rx_pg_fir2_errs_full_reg=48:54; #start_bit=48, number_of_bit=7 -define rx_pg_fir2_errs=48:54; #start_bit=48, number_of_bit=7 -define rx_pg_fir_err_dyn_rpr_sm=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_err_sls_hndshk_sm=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_err_dyn_rpr_snd_msg_sm=50:50; #start_bit=50, number_of_bit=1 -define rx_pg_fir_err_recal_sm=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_err_sls_enc_snd_msg_sm=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_err_glb_cal_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_err_stat_rpr_snd_msg_sm=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir1_errs_mask_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_pg_fir1_errs_mask=48:61; #start_bit=48, number_of_bit=14 -define rx_pg_fir_err_mask_pg_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_err_mask_gcr_buff=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_err_mask_gcrs_ld_sm=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_err_mask_gcrs_unld_sm=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_err_mask_glb_init_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_err_mask_main_init_sm=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir_err_mask_wtm_sm=55:55; #start_bit=55, number_of_bit=1 -define rx_pg_fir_err_mask_wtr_sm=56:56; #start_bit=56, number_of_bit=1 -define rx_pg_fir_err_mask_wtl_sm=57:57; #start_bit=57, number_of_bit=1 -define rx_pg_fir_err_mask_rpr_sm=58:58; #start_bit=58, number_of_bit=1 -define rx_pg_fir_err_mask_eyeopt_sm=59:59; #start_bit=59, number_of_bit=1 -define rx_pg_fir_err_mask_dsm_sm=60:60; #start_bit=60, number_of_bit=1 -define rx_pg_fir_err_mask_rxdsm_sm=61:61; #start_bit=61, number_of_bit=1 -define rx_pl_fir_err_mask=63:63; #start_bit=63, number_of_bit=1 -define rx_pg_fir2_errs_mask_full_reg=48:54; #start_bit=48, number_of_bit=7 -define rx_pg_fir2_errs_mask=48:54; #start_bit=48, number_of_bit=7 -define rx_pg_fir_err_mask_dyn_rpr_sm=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_err_mask_sls_hndshk_sm=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_err_mask_dyn_rpr_snd_msg_sm=50:50; #start_bit=50, number_of_bit=1 -define rx_pg_fir_err_mask_recal_sm=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_err_mask_sls_enc_snd_msg_sm=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_err_mask_glb_cal_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_err_mask_stat_rpr_snd_msg_sm=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir1_err_inj_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_pg_fir1_err_inj=48:61; #start_bit=48, number_of_bit=14 -define rx_pg_fir_err_inj_pg_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_err_inj_gcr_buff=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_err_inj_gcrs_ld_sm=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_err_inj_gcrs_unld_sm=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_err_inj_glb_init_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_err_inj_main_init_sm=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir_err_inj_wtm_sm=55:55; #start_bit=55, number_of_bit=1 -define rx_pg_fir_err_inj_wtr_sm=56:56; #start_bit=56, number_of_bit=1 -define rx_pg_fir_err_inj_wtl_sm=57:57; #start_bit=57, number_of_bit=1 -define rx_pg_fir_err_inj_rpr_sm=58:58; #start_bit=58, number_of_bit=1 -define rx_pg_fir_err_inj_eyeopt_sm=59:59; #start_bit=59, number_of_bit=1 -define rx_pg_fir_err_inj_dsm_sm=60:60; #start_bit=60, number_of_bit=1 -define rx_pg_fir_err_inj_rxdsm_sm=61:61; #start_bit=61, number_of_bit=1 -define rx_pg_fir2_err_inj_full_reg=48:54; #start_bit=48, number_of_bit=7 -define rx_pg_fir2_err_inj=48:54; #start_bit=48, number_of_bit=7 -define rx_pg_fir_err_inj_dyn_rpr_sm=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_err_inj_sls_hndshk_sm=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_err_inj_dyn_rpr_snd_msg_sm=50:50; #start_bit=50, number_of_bit=1 -define rx_pg_fir_err_inj_recal_sm=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_err_inj_sls_enc_snd_msg_sm=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_err_inj_glb_cal_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_err_inj_stat_rpr_snd_msg_sm=54:54; #start_bit=54, number_of_bit=1 -define rx_lane_bad_vec_0_15=48:63; #start_bit=48, number_of_bit=16 -define rx_lane_bad_vec_16_31=48:63; #start_bit=48, number_of_bit=16 -define rx_lane_disabled_vec_0_15=48:63; #start_bit=48, number_of_bit=16 -define rx_lane_disabled_vec_16_31=48:63; #start_bit=48, number_of_bit=16 -define rx_lane_swapped_vec_0_15=48:63; #start_bit=48, number_of_bit=16 -define rx_lane_swapped_vec_16_31=48:63; #start_bit=48, number_of_bit=16 -define rx_main_init_state=48:51; #start_bit=48, number_of_bit=4 -define rx_wtm_state=48:52; #start_bit=48, number_of_bit=5 -define rx_wtr_state=53:56; #start_bit=53, number_of_bit=4 -define rx_wtl_state=59:63; #start_bit=59, number_of_bit=5 -define rx_wtl_done_alias=59:59; #start_bit=59, number_of_bit=1 -define rx_wtl_p_n_swap_alias=60:60; #start_bit=60, number_of_bit=1 -define rx_wtl_fault_code_alias=61:63; #start_bit=61, number_of_bit=3 -define rx_wtr_cur_lane=48:52; #start_bit=48, number_of_bit=5 -define rx_wtr_max_bad_lanes=53:57; #start_bit=53, number_of_bit=5 -define rx_wtr_bad_lane_count=59:63; #start_bit=59, number_of_bit=5 -define rx_wt_prev_done_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define rx_wt_all_done_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define rx_wt_cu_pll_pgood=48:48; #start_bit=48, number_of_bit=1 -define rx_wt_cu_pll_reset=49:49; #start_bit=49, number_of_bit=1 -define rx_wt_cu_pll_pgooddly=50:52; #start_bit=50, number_of_bit=3 -define rx_wt_cu_pll_lock=53:53; #start_bit=53, number_of_bit=1 -define rx_wt_pll_refclksel=54:54; #start_bit=54, number_of_bit=1 -define rx_pll_refclksel_scom_en=55:55; #start_bit=55, number_of_bit=1 -define rx_deskew_seq_gcrmsg=48:50; #start_bit=48, number_of_bit=3 -define rx_deskew_skmin_gcrmsg=52:57; #start_bit=52, number_of_bit=6 -define rx_deskew_skmax_gcrmsg=58:63; #start_bit=58, number_of_bit=6 -define rx_dsm_state=50:55; #start_bit=50, number_of_bit=6 -define rx_rxdsm_state=57:63; #start_bit=57, number_of_bit=7 -define rx_deskew_max_limit=48:53; #start_bit=48, number_of_bit=6 -define rx_deskew_minskew_grp=48:53; #start_bit=48, number_of_bit=6 -define rx_deskew_maxskew_grp=54:59; #start_bit=54, number_of_bit=6 -define rx_bad_lane1_gcrmsg=48:54; #start_bit=48, number_of_bit=7 -define rx_bad_lane2_gcrmsg=55:61; #start_bit=55, number_of_bit=7 -define rx_bad_lane_code_gcrmsg=62:63; #start_bit=62, number_of_bit=2 -define rx_rpr_state=48:53; #start_bit=48, number_of_bit=6 -define rx_func_mode_state=48:51; #start_bit=48, number_of_bit=4 -define rx_tx_bus_width=48:54; #start_bit=48, number_of_bit=7 -define rx_rx_bus_width=55:61; #start_bit=55, number_of_bit=7 -define rx_sls_lane_gcrmsg=48:54; #start_bit=48, number_of_bit=7 -define rx_sls_lane_val_gcrmsg=55:55; #start_bit=55, number_of_bit=1 -define rx_fence =48:48; #start_bit=48, number_of_bit=1 -define rx_c4_sel=48:49; #start_bit=48, number_of_bit=2 -define rx_negz_en=50:50; #start_bit=50, number_of_bit=1 -define rx_prot_speed_slct=51:51; #start_bit=51, number_of_bit=1 -define rx_iref_bc=52:54; #start_bit=52, number_of_bit=3 -define rx_dyn_rpr_state=50:55; #start_bit=50, number_of_bit=6 -define rx_sls_hndshk_state=56:63; #start_bit=56, number_of_bit=8 -define rx_dyn_rpr_req_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define rx_dyn_rpr_lane2rpr_gcrmsg=49:55; #start_bit=49, number_of_bit=7 -define rx_dyn_rpr_ip_gcrmsg=56:56; #start_bit=56, number_of_bit=1 -define rx_dyn_rpr_complete_gcrmsg=57:57; #start_bit=57, number_of_bit=1 -define rx_dyn_rpr_bad_lane_max=48:54; #start_bit=48, number_of_bit=7 -define rx_dyn_rpr_err_cntr1_duration=55:58; #start_bit=55, number_of_bit=4 -define rx_dyn_rpr_clr_err_cntr1=59:59; #start_bit=59, number_of_bit=1 -define rx_dyn_rpr_disable=60:60; #start_bit=60, number_of_bit=1 -define rx_dyn_rpr_enc_bad_data_lane_width=61:63; #start_bit=61, number_of_bit=3 -define rx_gcr_msg_debug_dest_bus_id=48:53; #start_bit=48, number_of_bit=6 -define rx_gcr_msg_debug_dest_group_id=54:59; #start_bit=54, number_of_bit=6 -define rx_gcr_msg_debug_src_bus_id=48:53; #start_bit=48, number_of_bit=6 -define rx_gcr_msg_debug_src_group_id=54:59; #start_bit=54, number_of_bit=6 -define rx_gcr_msg_debug_dest_addr=48:56; #start_bit=48, number_of_bit=9 -define rx_gcr_msg_debug_send_msg=63:63; #start_bit=63, number_of_bit=1 -define rx_gcr_msg_debug_write_data=48:63; #start_bit=48, number_of_bit=16 -define rx_servo_recal_ip=48:48; #start_bit=48, number_of_bit=1 -define rx_dyn_recal_main_state=50:55; #start_bit=50, number_of_bit=6 -define rx_dyn_recal_hndshk_state=57:63; #start_bit=57, number_of_bit=7 -#define #rx_eye_opt_state=48:55; #start_bit=48, number_of_bit=8 -define rx_eye_opt_state=48:55; #start_bit=48, number_of_bit=8 -define rx_recal_state=56:63; #start_bit=56, number_of_bit=8 -define rx_wt_clk_lane_inverted=49:49; #start_bit=49, number_of_bit=1 -define rx_wt_clk_lane_bad_code=50:52; #start_bit=50, number_of_bit=3 -define rx_wt_clk_lane_status_alias=49:52; #start_bit=49, number_of_bit=4 -define rx_dyn_recal_overall_timeout_sel=48:50; #start_bit=48, number_of_bit=3 -define rx_dyn_recal_suspend=51:51; #start_bit=51, number_of_bit=1 -#define #rx_dyn_recal_ber_test_timeout=61:63; #start_bit=61, number_of_bit=3 -define rx_dyn_recal_ip_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define rx_dyn_recal_failed_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define rx_dyn_recal_ripple_gcrmsg=50:50; #start_bit=50, number_of_bit=1 -define rx_dyn_recal_timeout_gcrmsg=51:51; #start_bit=51, number_of_bit=1 -define rx_eo_enable_latch_offset_cal=48:48; #start_bit=48, number_of_bit=1 -define rx_eo_enable_ctle_cal=49:49; #start_bit=49, number_of_bit=1 -define rx_eo_enable_vga_cal=50:50; #start_bit=50, number_of_bit=1 -define rx_eo_enable_dfe_h1_cal=52:52; #start_bit=52, number_of_bit=1 -define rx_eo_enable_h1ap_tweak=53:53; #start_bit=53, number_of_bit=1 -define rx_eo_enable_ddc=54:54; #start_bit=54, number_of_bit=1 -define rx_eo_enable_final_l2u_adj=56:56; #start_bit=56, number_of_bit=1 -define rx_eo_enable_ber_test=57:57; #start_bit=57, number_of_bit=1 -define rx_eo_enable_result_check=58:58; #start_bit=58, number_of_bit=1 -define rx_eo_enable_ctle_edge_track_only=59:59; #start_bit=59, number_of_bit=1 -define rx_rc_enable_latch_offset_cal=48:48; #start_bit=48, number_of_bit=1 -define rx_rc_enable_ctle_cal=49:49; #start_bit=49, number_of_bit=1 -define rx_rc_enable_vga_cal=50:50; #start_bit=50, number_of_bit=1 -define rx_rc_enable_dfe_h1_cal=52:52; #start_bit=52, number_of_bit=1 -define rx_rc_enable_h1ap_tweak=53:53; #start_bit=53, number_of_bit=1 -define rx_rc_enable_ddc=54:54; #start_bit=54, number_of_bit=1 -define rx_rc_enable_ber_test=56:56; #start_bit=56, number_of_bit=1 -define rx_rc_enable_result_check=57:57; #start_bit=57, number_of_bit=1 -define rx_rc_enable_ctle_edge_track_only=59:59; #start_bit=59, number_of_bit=1 -define rx_eo_latch_offset_done=48:48; #start_bit=48, number_of_bit=1 -define rx_eo_ctle_done=49:49; #start_bit=49, number_of_bit=1 -define rx_eo_vga_done=50:50; #start_bit=50, number_of_bit=1 -define rx_eo_dfe_h1_done=52:52; #start_bit=52, number_of_bit=1 -define rx_eo_h1ap_tweak_done=53:53; #start_bit=53, number_of_bit=1 -define rx_eo_ddc_done=54:54; #start_bit=54, number_of_bit=1 -define rx_eo_final_l2u_adj_done=56:56; #start_bit=56, number_of_bit=1 -define rx_eo_dfe_flag=57:57; #start_bit=57, number_of_bit=1 -define rx_eo_ber_test_done=58:58; #start_bit=58, number_of_bit=1 -define rx_eo_result_check_done=59:59; #start_bit=59, number_of_bit=1 -define rx_eo_latch_offset_failed=48:48; #start_bit=48, number_of_bit=1 -define rx_eo_ctle_failed=49:49; #start_bit=49, number_of_bit=1 -define rx_eo_vga_failed=50:50; #start_bit=50, number_of_bit=1 -define rx_eo_dfe_h1_failed=52:52; #start_bit=52, number_of_bit=1 -define rx_eo_h1ap_tweak_failed=53:53; #start_bit=53, number_of_bit=1 -define rx_eo_ddc_failed=54:54; #start_bit=54, number_of_bit=1 -define rx_eo_final_l2u_adj_failed=56:56; #start_bit=56, number_of_bit=1 -define rx_eo_result_check_failed=57:57; #start_bit=57, number_of_bit=1 -define rx_eo_converged_count=48:51; #start_bit=48, number_of_bit=4 -define rx_eo_converged_end_count=52:55; #start_bit=52, number_of_bit=4 -define rx_ap_even_work=48:55; #start_bit=48, number_of_bit=8 -define rx_ap_odd_work=56:63; #start_bit=56, number_of_bit=8 -define rx_an_even_work=48:55; #start_bit=48, number_of_bit=8 -define rx_an_odd_work=56:63; #start_bit=56, number_of_bit=8 -define rx_amin_even_work=48:55; #start_bit=48, number_of_bit=8 -define rx_amin_odd_work=56:63; #start_bit=56, number_of_bit=8 -define rx_amax_high=48:55; #start_bit=48, number_of_bit=8 -define rx_amax_low=56:63; #start_bit=56, number_of_bit=8 -#define #rx_amp_peak_work=48:51; #start_bit=48, number_of_bit=4 -define rx_amp_peak_work=48:51; #start_bit=48, number_of_bit=4 -define rx_amp_gain_work=52:55; #start_bit=52, number_of_bit=4 -define rx_amp_offset_work=58:63; #start_bit=58, number_of_bit=6 -define rx_amp_offset_max=48:53; #start_bit=48, number_of_bit=6 -define rx_amp_offset_min=54:59; #start_bit=54, number_of_bit=6 -define rx_servo_ber_count_work=48:59; #start_bit=48, number_of_bit=12 -define rx_eo_final_l2u_dly_seq_gcrmsg=48:49; #start_bit=48, number_of_bit=2 -define rx_eo_final_l2u_dly_maxchg_gcrmsg=50:55; #start_bit=50, number_of_bit=6 -define rx_eo_final_l2u_dly_chg=58:63; #start_bit=58, number_of_bit=6 -define rx_sls_rcvy_disable=48:48; #start_bit=48, number_of_bit=1 -define rx_sls_rcvy_state=51:55; #start_bit=51, number_of_bit=5 -define rx_sls_rcvy_req_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define rx_sls_rcvy_ip_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define rx_sls_rcvy_done_gcrmsg=50:50; #start_bit=50, number_of_bit=1 -define rx_tx_bad_lane_cntr_gcrmsg=48:49; #start_bit=48, number_of_bit=2 -define rx_dis_synd_tallying_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define rx_trc_mode=48:51; #start_bit=48, number_of_bit=4 -define rx_trc_grp=54:59; #start_bit=54, number_of_bit=6 -define rx_dyn_rpr_enc_bad_data_lane_debug=49:55; #start_bit=49, number_of_bit=7 -define rx_bad_bus_err_cntr=57:63; #start_bit=57, number_of_bit=7 -define rx_bad_bus_lane_err_cntr_dis_clr=48:48; #start_bit=48, number_of_bit=1 -define rx_bad_bus_lane_err_cntr=49:55; #start_bit=49, number_of_bit=7 -define rx_last_bad_bus_lane=57:63; #start_bit=57, number_of_bit=7 -define rx_dyn_rpr_bad_bus_max=48:54; #start_bit=48, number_of_bit=7 -define rx_dyn_rpr_err_cntr2_duration=55:58; #start_bit=55, number_of_bit=4 -define rx_dyn_rpr_clr_err_cntr2=59:59; #start_bit=59, number_of_bit=1 -define rx_min_eye_width=50:55; #start_bit=50, number_of_bit=6 -define rx_min_eye_height=56:63; #start_bit=56, number_of_bit=8 -define rx_max_ber_check_count=56:63; #start_bit=56, number_of_bit=8 -define rx_stop_state_enable=48:48; #start_bit=48, number_of_bit=1 -define rx_state_stopped=49:49; #start_bit=49, number_of_bit=1 -define rx_stop_addr_msb=56:59; #start_bit=56, number_of_bit=4 -define rx_stop_mask_msb=60:63; #start_bit=60, number_of_bit=4 -define rx_stop_addr_lsb=48:63; #start_bit=48, number_of_bit=16 -define rx_stop_mask_lsb=48:63; #start_bit=48, number_of_bit=16 -define rx_slv_shdw_done_fin_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define rx_slv_shdw_nop_fin_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define rx_slv_shdw_rpr_done_fin_gcrmsg=50:50; #start_bit=50, number_of_bit=1 -define rx_slv_shdw_rpr_nop_fin_gcrmsg=51:51; #start_bit=51, number_of_bit=1 -define rx_slv_unshdw_done_fin_gcrmsg=52:52; #start_bit=52, number_of_bit=1 -define rx_slv_unshdw_nop_fin_gcrmsg=53:53; #start_bit=53, number_of_bit=1 -define rx_slv_unshdw_rpr_done_fin_gcrmsg=54:54; #start_bit=54, number_of_bit=1 -define rx_slv_unshdw_rpr_nop_fin_gcrmsg=55:55; #start_bit=55, number_of_bit=1 -define rx_slv_recal_done_nop_fin_gcrmsg=56:56; #start_bit=56, number_of_bit=1 -define rx_slv_recal_fail_nop_fin_gcrmsg=57:57; #start_bit=57, number_of_bit=1 -define rx_slv_recal_presults_fin_gcrmsg=58:58; #start_bit=58, number_of_bit=1 -define rx_slv_recal_fresults_fin_gcrmsg=59:59; #start_bit=59, number_of_bit=1 -define rx_slv_recal_abort_ack_fin_gcrmsg=60:60; #start_bit=60, number_of_bit=1 -define rx_slv_recal_abort_mnop_fin_gcrmsg=61:61; #start_bit=61, number_of_bit=1 -define rx_slv_recal_abort_snop_fin_gcrmsg=62:62; #start_bit=62, number_of_bit=1 -define rx_reduced_scramble_mode=48:49; #start_bit=48, number_of_bit=2 -define rx_prbs_scramble_mode=50:51; #start_bit=50, number_of_bit=2 -define rx_act_check_timeout_sel=52:54; #start_bit=52, number_of_bit=3 -define rx_block_lock_timeout_sel=55:57; #start_bit=55, number_of_bit=3 -define rx_bit_lock_timeout_sel=58:60; #start_bit=58, number_of_bit=3 -define rx_pp_trc_mode=48:50; #start_bit=48, number_of_bit=3 -define rx_bist_jitter_pulse_sel=51:52; #start_bit=51, number_of_bit=2 -define rx_bist_min_eye_width=54:59; #start_bit=54, number_of_bit=6 -define rx_wt_pattern_length=61:62; #start_bit=61, number_of_bit=2 -define rx_servo_timeout_sel_a=48:51; #start_bit=48, number_of_bit=4 -define rx_servo_timeout_sel_b=52:55; #start_bit=52, number_of_bit=4 -define rx_servo_timeout_sel_c=56:59; #start_bit=56, number_of_bit=4 -define rx_servo_timeout_sel_d=60:63; #start_bit=60, number_of_bit=4 -define rx_servo_timeout_sel_e=48:51; #start_bit=48, number_of_bit=4 -define rx_servo_timeout_sel_f=52:55; #start_bit=52, number_of_bit=4 -define rx_servo_timeout_sel_g=56:59; #start_bit=56, number_of_bit=4 -define rx_servo_timeout_sel_h=60:63; #start_bit=60, number_of_bit=4 -define rx_servo_timeout_sel_i=48:51; #start_bit=48, number_of_bit=4 -define rx_servo_timeout_sel_j=52:55; #start_bit=52, number_of_bit=4 -define rx_servo_timeout_sel_k=56:59; #start_bit=56, number_of_bit=4 -define rx_servo_timeout_sel_l=60:63; #start_bit=60, number_of_bit=4 -define rx_recal_timeout_sel_a=48:51; #start_bit=48, number_of_bit=4 -define rx_recal_timeout_sel_b=52:55; #start_bit=52, number_of_bit=4 -define rx_recal_timeout_sel_g=56:59; #start_bit=56, number_of_bit=4 -define rx_recal_timeout_sel_h=60:63; #start_bit=60, number_of_bit=4 -define rx_recal_timeout_sel_i=48:51; #start_bit=48, number_of_bit=4 -define rx_recal_timeout_sel_j=52:55; #start_bit=52, number_of_bit=4 -define rx_recal_timeout_sel_k=56:59; #start_bit=56, number_of_bit=4 -define rx_recal_timeout_sel_l=60:63; #start_bit=60, number_of_bit=4 -#define #rx_block_lock=48:48; #start_bit=48, number_of_bit=1 -define rx_prbs_check_sync=49:49; #start_bit=49, number_of_bit=1 -define rx_enable_reduced_scramble=50:50; #start_bit=50, number_of_bit=1 -define rx_recal_in_progress=48:48; #start_bit=48, number_of_bit=1 -define rx_dyn_recal_interval_timeout_sel=49:51; #start_bit=49, number_of_bit=3 -define rx_dyn_recal_status_rpt_timeout_sel=52:53; #start_bit=52, number_of_bit=2 -define rx_peak_cfg=48:49; #start_bit=48, number_of_bit=2 -define rx_amin_cfg=50:52; #start_bit=50, number_of_bit=3 -define rx_anap_cfg=53:54; #start_bit=53, number_of_bit=2 -define rx_h1_cfg=55:56; #start_bit=55, number_of_bit=2 -define rx_h1ap_cfg=57:59; #start_bit=57, number_of_bit=3 -define rx_dfe_ca_cfg=60:61; #start_bit=60, number_of_bit=2 -define rx_spmux_cfg=62:63; #start_bit=62, number_of_bit=2 -define rx_init_tmr_cfg=48:50; #start_bit=48, number_of_bit=3 -define rx_ber_cfg=51:53; #start_bit=51, number_of_bit=3 -define rx_fifo_dly_cfg=54:55; #start_bit=54, number_of_bit=2 -define rx_ddc_cfg=56:57; #start_bit=56, number_of_bit=2 -define rx_dac_bo_cfg=58:60; #start_bit=58, number_of_bit=3 -define rx_prot_cfg=61:62; #start_bit=61, number_of_bit=2 -define rx_reset_cfg_hld=48:63; #start_bit=48, number_of_bit=16 -define rx_scope_control=48:49; #start_bit=48, number_of_bit=2 -define rx_bist_en=48:48; #start_bit=48, number_of_bit=1 -define rx_ber_en=48:48; #start_bit=48, number_of_bit=1 -define rx_ber_timer_freeze_en=48:48; #start_bit=48, number_of_bit=1 -define rx_ber_count_freeze_en=49:49; #start_bit=49, number_of_bit=1 -define rx_ber_count_sel=51:53; #start_bit=51, number_of_bit=3 -define rx_ber_timer_sel=54:56; #start_bit=54, number_of_bit=3 -define rx_ber_clr_count_on_read_en=57:57; #start_bit=57, number_of_bit=1 -define rx_ber_clr_timer_on_read_en=58:58; #start_bit=58, number_of_bit=1 -define rx_pb_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 -define rx_pb_fir_reset=63:63; #start_bit=63, number_of_bit=1 -define rx_pb_fir_errs_full_reg=48:57; #start_bit=48, number_of_bit=10 -define rx_pb_fir_errs=48:57; #start_bit=48, number_of_bit=10 -define rx_pb_fir_err_pb_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pb_fir_err_gcr_buff0=49:49; #start_bit=49, number_of_bit=1 -define rx_pb_fir_err_gcr_buff1=50:50; #start_bit=50, number_of_bit=1 -define rx_pb_fir_err_gcr_buff2=51:51; #start_bit=51, number_of_bit=1 -define rx_pb_fir_err_gcrs_ld_sm0=52:52; #start_bit=52, number_of_bit=1 -define rx_pb_fir_err_gcrs_ld_sm1=53:53; #start_bit=53, number_of_bit=1 -define rx_pb_fir_err_gcrs_ld_sm2=54:54; #start_bit=54, number_of_bit=1 -define rx_pb_fir_err_gcrs_unld_sm0=55:55; #start_bit=55, number_of_bit=1 -define rx_pb_fir_err_gcrs_unld_sm1=56:56; #start_bit=56, number_of_bit=1 -define rx_pb_fir_err_gcrs_unld_sm2=57:57; #start_bit=57, number_of_bit=1 -define rx_pb_fir_errs_mask_full_reg=48:57; #start_bit=48, number_of_bit=10 -define rx_pb_fir_errs_mask=48:57; #start_bit=48, number_of_bit=10 -define rx_pb_fir_err_mask_pb_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pb_fir_err_mask_gcr_buff0=49:49; #start_bit=49, number_of_bit=1 -define rx_pb_fir_err_mask_gcr_buff1=50:50; #start_bit=50, number_of_bit=1 -define rx_pb_fir_err_mask_gcr_buff2=51:51; #start_bit=51, number_of_bit=1 -define rx_pb_fir_err_mask_gcrs_ld_sm0=52:52; #start_bit=52, number_of_bit=1 -define rx_pb_fir_err_mask_gcrs_ld_sm1=53:53; #start_bit=53, number_of_bit=1 -define rx_pb_fir_err_mask_gcrs_ld_sm2=54:54; #start_bit=54, number_of_bit=1 -define rx_pb_fir_err_mask_gcrs_unld_sm0=55:55; #start_bit=55, number_of_bit=1 -define rx_pb_fir_err_mask_gcrs_unld_sm1=56:56; #start_bit=56, number_of_bit=1 -define rx_pb_fir_err_mask_gcrs_unld_sm2=57:57; #start_bit=57, number_of_bit=1 -define rx_pb_fir_errs_inj_full_reg=48:57; #start_bit=48, number_of_bit=10 -define rx_pb_fir_errs_inj=48:57; #start_bit=48, number_of_bit=10 -define rx_pb_fir_err_inj_pb_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pb_fir_err_inj_gcr_buff0=49:49; #start_bit=49, number_of_bit=1 -define rx_pb_fir_err_inj_gcr_buff1=50:50; #start_bit=50, number_of_bit=1 -define rx_pb_fir_err_inj_gcr_buff2=51:51; #start_bit=51, number_of_bit=1 -define rx_pb_fir_err_inj_gcrs_ld_sm0=52:52; #start_bit=52, number_of_bit=1 -define rx_pb_fir_err_inj_gcrs_ld_sm1=53:53; #start_bit=53, number_of_bit=1 -define rx_pb_fir_err_inj_gcrs_ld_sm2=54:54; #start_bit=54, number_of_bit=1 -define rx_pb_fir_err_inj_gcrs_unld_sm0=55:55; #start_bit=55, number_of_bit=1 -define rx_pb_fir_err_inj_gcrs_unld_sm1=56:56; #start_bit=56, number_of_bit=1 -define rx_pb_fir_err_inj_gcrs_unld_sm2=57:57; #start_bit=57, number_of_bit=1 -define tx_mode_pl=010000000; #080 -define tx_cntl_stat_pl=010000001; #081 -define tx_spare_mode_pl=010000010; #082 -#define #tx_id_pl=010000100; #084 -define tx_bist_stat_pl=010000101; #085 -define tx_prbs_mode_pl=010000110; #086 -define tx_data_cntl_gcrmsg_pl=010000111; #087 -define tx_sync_pattern_gcrmsg_pl=010001000; #088 -define tx_fir_pl=010001010; #08A -define tx_fir_mask_pl=010001011; #08B -define tx_fir_error_inject_pl=010001100; #08C -define tx_mode_fast_pl=010001101; #08D -define tx_tdr_stat_pl=010001110; #08E -define tx_cntl_gcrmsg_pl=010001111; #08F -define tx_clk_mode_pg=110000000; #180 -define tx_spare_mode_pg=110000001; #181 -define tx_cntl_stat_pg=110000010; #182 -define tx_mode_pg=110000011; #183 -define tx_reset_act_pg=110001000; #188 -define tx_bist_stat_pg=110001001; #189 -define tx_fir_pg=110001010; #18A -define tx_fir_mask_pg=110001011; #18B -define tx_fir_error_inject_pg=110001100; #18C -define tx_id1_pg=110010010; #192 -define tx_id2_pg=110010011; #193 -define tx_id3_pg=110010100; #194 -define tx_clk_cntl_gcrmsg_pg=110011000; #198 -define tx_ffe_mode_pg=110011001; #199 -define tx_ffe_main_pg=110011010; #19A -define tx_ffe_post_pg=110011011; #19B -define tx_ffe_margin_pg=110011100; #19C -define tx_bad_lane_enc_gcrmsg_pg=110011101; #19D -define tx_ber_cntl_pg=110011110; #19E -define tx_sls_lane_enc_gcrmsg_pg=110011111; #19F -define tx_wt_seg_enable_pg=110100000; #1A0 -define tx_lane_disabled_vec_0_15_pg=110100011; #1A3 -define tx_lane_disabled_vec_16_31_pg=110100100; #1A4 -define tx_sls_lane_mux_gcrmsg_pg=110100101; #1A5 -define tx_dyn_rpr_pg=110100110; #1A6 -define tx_slv_mv_sls_ln_req_gcrmsg_pg=110100111; #1A7 -define tx_wiretest_pp=111010000; #1D0 -define tx_mode_pp=111010001; #1D1 -define tx_sls_gcrmsg_pp=111010010; #1D2 -define tx_ber_cntl_a_pp=111010011; #1D3 -define tx_ber_cntl_b_pp=111010100; #1D4 -define tx_dyn_recal_timeouts_pp=111010101; #1D5 -define tx_bist_cntl_pp=111010110; #1D6 -define tx_ber_cntl_sls_pp=111010111; #1D7 -define tx_cntl_pp=111011000; #1D8 -define tx_reset_cfg_pp=111011001; #1D9 -define tx_tdr_cntl1_pp=111011010; #1DA -define tx_tdr_cntl2_pp=111011011; #1DB -define tx_tdr_cntl3_pp=111011100; #1DC -define tx_impcal_pb=111100000; #1E0 -define tx_impcal_nval_pb=111100001; #1E1 -define tx_impcal_pval_pb=111100010; #1E2 -define tx_impcal_p_4x_pb=111100011; #1E3 -define tx_impcal_swo1_pb=111100100; #1E4 -define tx_impcal_swo2_pb=111100101; #1E5 -define tx_analog_iref_pb=111100110; #1E6 -define tx_minikerf_pb=111100111; #1E7 -define tx_init_version_pb=111101000; #1E8 -define tx_scratch_reg_pb=111101001; #1E9 -define rx_mode_pl=000000000; #000 -define rx_cntl_pl=000000001; #001 -define rx_spare_mode_pl=000000010; #002 -define rx_prot_edge_status_pl=000000011; #003 -#define #rx_prot_gb_status_pl=000000100; #004 -define rx_bist_stat_pl=000000101; #005 -#define #rx_eyeopt_stat_pl=000000111; #007 -define rx_offset_even_pl=000001000; #008 -define rx_offset_odd_pl=000001001; #009 -define rx_amp_val_pl=000001010; #00A -define rx_amp_cntl_pl=000001011; #00B -define rx_prot_status_pl=000001100; #00C -define rx_prot_mode_pl=000001101; #00D -define rx_prot_cntl_pl=000001110; #00E -#define #rx_wiretest_stat_pl=000001110; #00E -define rx_fifo_stat_pl=000001111; #00F -define rx_ap_pl =000010000; #010 -define rx_an_pl =000010001; #011 -define rx_amin_pl=000010010; #012 -define rx_h1_even_pl=000010011; #013 -define rx_h1_odd_pl=000010100; #014 -define rx_prbs_mode_pl=000010110; #016 -define rx_stat_pl=000011000; #018 -define rx_deskew_stat_pl=000011001; #019 -define rx_fir_pl=000011010; #01A -define rx_fir_mask_pl=000011011; #01B -define rx_fir_error_inject_pl=000011100; #01C -define rx_sls_pl=000011101; #01D -define rx_wt_status_pl=000011110; #01E -define rx_fifo_cntl_pl=000011111; #01F -define rx_ber_status_pl=000100000; #020 -define rx_ber_timer_0_15_pl=000100001; #021 -define rx_ber_timer_16_31_pl=000100010; #022 -define rx_ber_timer_32_39_pl=000100011; #023 -define rx_servo_cntl_pl=000100100; #024 -define rx_fifo_diag_0_15_pl=000100101; #025 -define rx_fifo_diag_16_31_pl=000100110; #026 -define rx_fifo_diag_32_47_pl=000100111; #027 -define rx_eye_width_status_pl=000101000; #028 -define rx_eye_width_cntl_pl=000101001; #029 -define rx_dfe_clkadj_pl=000101010; #02A -define rx_trace_pl=000101011; #02B -define rx_servo_ber_count_pl=000101100; #02C -define rx_eye_opt_stat_pl=000101101; #02D -define rx_clk_mode_pg=100000000; #100 -define rx_spare_mode_pg=100000001; #101 -define rx_stop_cntl_stat_pg=100000010; #102 -define rx_mode_pg=100000011; #103 -define rx_stop_addr_lsb_pg=100000111; #107 -define rx_stop_mask_lsb_pg=100001000; #108 -define rx_reset_act_pg=100001001; #109 -define rx_id1_pg=100001010; #10A -define rx_id2_pg=100001011; #10B -define rx_id3_pg=100001100; #10C -define rx_minikerf_pg=100001101; #10D -define rx_dyn_rpr_debug2_pg=100001110; #10E -define rx_sls_mode_pg=100001111; #10F -define rx_training_start_pg=100010000; #110 -define rx_training_status_pg=100010001; #111 -define rx_recal_status_pg=100010010; #112 -define rx_timeout_sel_pg=100010011; #113 -define rx_fifo_mode_pg=100010100; #114 -#define #rx_state_debug_pg=100010101; #115 -#define #rx_state_val_pg=100010110; #116 -define rx_sls_status_pg=100010111; #117 -define rx_fir1_pg=100011010; #11A -define rx_fir2_pg=100011011; #11B -define rx_fir1_mask_pg=100011100; #11C -define rx_fir2_mask_pg=100011101; #11D -define rx_fir1_error_inject_pg=100011110; #11E -define rx_fir2_error_inject_pg=100011111; #11F -define rx_fir_training_pg=100100000; #120 -define rx_fir_training_mask_pg=100100001; #121 -define rx_timeout_sel1_pg=100100010; #122 -define rx_lane_bad_vec_0_15_pg=100100011; #123 -define rx_lane_bad_vec_16_31_pg=100100100; #124 -define rx_lane_disabled_vec_0_15_pg=100100101; #125 -define rx_lane_disabled_vec_16_31_pg=100100110; #126 -define rx_lane_swapped_vec_0_15_pg=100100111; #127 -define rx_lane_swapped_vec_16_31_pg=100101000; #128 -define rx_init_state_pg=100101001; #129 -define rx_wiretest_state_pg=100101010; #12A -define rx_wiretest_laneinfo_pg=100101011; #12B -define rx_wiretest_gcrmsgs_pg=100101100; #12C -define rx_deskew_gcrmsgs_pg=100101101; #12D -define rx_deskew_state_pg=100101110; #12E -define rx_deskew_mode_pg=100101111; #12F -define rx_deskew_status_pg=100110000; #130 -define rx_bad_lane_enc_gcrmsg_pg=100110001; #131 -define rx_static_repair_state_pg=100110010; #132 -define rx_tx_bus_info_pg=100110011; #133 -define rx_sls_lane_enc_gcrmsg_pg=100110100; #134 -define rx_fence_pg=100110101; #135 -define rx_timeout_sel2_pg=100110111; #137 -define rx_misc_analog_pg=100111000; #138 -define rx_dyn_rpr_pg=100111001; #139 -define rx_dyn_rpr_gcrmsg_pg=100111010; #13A -define rx_dyn_rpr_err_tallying1_pg=100111011; #13B -define rx_eo_final_l2u_gcrmsgs_pg=100111100; #13C -define rx_gcr_msg_debug_dest_ids_pg=100111101; #13D -define rx_gcr_msg_debug_src_ids_pg=100111110; #13E -define rx_gcr_msg_debug_dest_addr_pg=100111111; #13F -define rx_gcr_msg_debug_write_data_pg=101000000; #140 -define rx_dyn_recal_pg=101000001; #141 -define rx_wt_clk_status_pg=101000010; #142 -define rx_dyn_recal_config_pg=101000011; #143 -define rx_wt_config_pg=101000100; #144 -define rx_dyn_recal_gcrmsg_pg=101000101; #145 -define rx_wiretest_pll_cntl_pg=101000110; #146 -define rx_eo_step_cntl_pg=101000111; #147 -define rx_eo_step_stat_pg=101001000; #148 -define rx_eo_step_fail_pg=101001001; #149 -define rx_ap_pg =101001010; #14A -define rx_an_pg =101001011; #14B -define rx_amin_pg=101001100; #14C -define rx_amax_pg=101001101; #14D -define rx_amp_val_pg=101001110; #14E -define rx_amp_offset_pg=101001111; #14F -define rx_eo_convergence_pg=101010000; #150 -define rx_sls_rcvy_pg=101010001; #151 -define rx_sls_rcvy_gcrmsg_pg=101010010; #152 -define rx_tx_lane_info_gcrmsg_pg=101010011; #153 -define rx_err_tallying_gcrmsg_pg=101010100; #154 -define rx_trace_pg=101010101; #155 -define rx_rc_step_cntl_pg=101010111; #157 -define rx_eo_recal_pg=101011000; #158 -define rx_servo_ber_count_pg=101011001; #159 -define rx_func_state_pg=101011010; #15A -define rx_dyn_rpr_debug_pg=101011011; #15B -define rx_dyn_rpr_err_tallying2_pg=101011100; #15C -define rx_result_chk_pg=101011101; #15D -define rx_ber_chk_pg=101011110; #15E -define rx_sls_rcvy_fin_gcrmsg_pg=101011111; #15F -#define #rx_wiretest_pp=101100000; #160 -define rx_mode1_pp=101100001; #161 -define rx_cntl_fast_pp=101100010; #162 -define rx_dyn_recal_timeouts_pp=101101000; #168 -define rx_ber_cntl_pp=101101010; #16A -define rx_ber_mode_pp=101101011; #16B -define rx_servo_to1_pp=101101100; #16C -define rx_servo_to2_pp=101101101; #16D -define rx_servo_to3_pp=101101110; #16E -define rx_dfe_config_pp=101101111; #16F -define rx_dfe_timers_pp=101110000; #170 -define rx_reset_cfg_pp=101110001; #171 -define rx_recal_to1_pp=101110010; #172 -define rx_recal_to2_pp=101110011; #173 -define rx_recal_to3_pp=101110100; #174 -define rx_recal_cntl_pp=101110101; #175 -define rx_mode2_pp=101110110; #176 -define rx_bist_gcrmsg_pp=101110111; #177 -define rx_scope_cntl_pp=101111000; #178 -define rx_fir_reset_pb=111110000; #1F0 -define rx_fir_pb=111110001; #1F1 -define rx_fir_mask_pb=111110010; #1F2 -define rx_fir_error_inject_pb=111110011; #1F3 -define rx_fir_msg_pb=111111111; #1FF -define abus_gcr_addr=08010C3F; -define dmi0_gcr_addr=02011A3F; -define dmi1_gcr_addr=02011E3F; -define cn_gcr_addr=0201043F; -define rx_grp0=000000; # 0x00 -define rx_grp1=000001; # 0x01 -define rx_grp2=000010; # 0x02 -define rx_grp3=000011; # 0x03 -define tx_grp0=100000; # 0x20 -define tx_grp1=100001; # 0x21 -define tx_grp2=100010; # 0x22 -define tx_grp3=100011; # 0x23 -define lane_na=00000; # 0x00 -define lane_0=00000; -define lane_1=00001; -define lane_2=00010; -define lane_3=00011; -define lane_4=00100; -define lane_5=00101; -define lane_6=00110; -define lane_7=00111; -define lane_8=01000; -define lane_9=01001; -define lane_10=01010; -define lane_11=01011; -define lane_12=01100; -define lane_13=01101; -define lane_14=01110; -define lane_15=01111; -define lane_16=10000; -define lane_17=10001; -define lane_18=10010; -define lane_19=10011; -define lane_20=10100; -define lane_21=10101; -define lane_22=10110; -define lane_23=10111; -define rx_prbs_tap_id_pattern_a=0b000; -define rx_prbs_tap_id_pattern_b=0b001; -define rx_prbs_tap_id_pattern_c=0b010; -define rx_prbs_tap_id_pattern_d=0b011; -define rx_prbs_tap_id_pattern_e=0b100; -define rx_prbs_tap_id_pattern_f=0b101; -define rx_prbs_tap_id_pattern_g=0b110; -define rx_prbs_tap_id_pattern_h=0b111; -define tx_prbs_tap_id_pattern_a=0b000; -define tx_prbs_tap_id_pattern_b=0b001; -define tx_prbs_tap_id_pattern_c=0b010; -define tx_prbs_tap_id_pattern_d=0b011; -define tx_prbs_tap_id_pattern_e=0b100; -define tx_prbs_tap_id_pattern_f=0b101; -define tx_prbs_tap_id_pattern_g=0b110; -define tx_prbs_tap_id_pattern_h=0b111; diff --git a/src/usr/hwpf/hwp/initfiles/ei4.io.define b/src/usr/hwpf/hwp/initfiles/ei4.io.define deleted file mode 100644 index 3c4af15c8..000000000 --- a/src/usr/hwpf/hwp/initfiles/ei4.io.define +++ /dev/null @@ -1,946 +0,0 @@ -define tx_mode_pl_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_lane_pdwn=48:48; #start_bit=48, number_of_bit=1 -define tx_lane_invert=49:49; #start_bit=49, number_of_bit=1 -define tx_lane_quiesce=50:51; #start_bit=50, number_of_bit=2 -define tx_lane_scramble_disable=54:54; #start_bit=54, number_of_bit=1 -#define #tx_lane_error_inject_mode=58:63; #start_bit=58, number_of_bit=6 -define tx_fifo_err=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 -define tx_pl_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 -define tx_pl_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 -define tx_pl_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 -define tx_pl_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 -define tx_pl_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 -define tx_pl_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 -#define #tx_lane_id=48:52; #start_bit=48, number_of_bit=5 -define tx_lane_bist_err=48:48; #start_bit=48, number_of_bit=1 -define tx_lane_bist_done=49:49; #start_bit=49, number_of_bit=1 -define tx_pl_fir_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_pl_fir_errs=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_fir_err_pl_regs=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_fir_errs_mask_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_pl_fir_errs_mask=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_fir_err_mask_pl_regs=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_fir_err_inj_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_pl_fir_err_inj=48:48; #start_bit=48, number_of_bit=1 -define tx_pl_fir_err_inj_pl_regs=48:48; #start_bit=48, number_of_bit=1 -define tx_prbs_tap_id=48:50; #start_bit=48, number_of_bit=3 -define tx_drv_data_pattern_gcrmsg=48:51; #start_bit=48, number_of_bit=4 -define tx_drv_func_data_gcrmsg=52:52; #start_bit=52, number_of_bit=1 -define tx_sls_lane_sel_gcrmsg=53:53; #start_bit=53, number_of_bit=1 -define tx_err_inj_a_enable=52:52; #start_bit=52, number_of_bit=1 -define tx_err_inj_b_enable=53:53; #start_bit=53, number_of_bit=1 -define tx_clk_pdwn=48:48; #start_bit=48, number_of_bit=1 -define tx_clk_invert=49:49; #start_bit=49, number_of_bit=1 -define tx_clk_quiesce_p=50:51; #start_bit=50, number_of_bit=2 -define tx_clk_quiesce_n=52:53; #start_bit=52, number_of_bit=2 -define tx_pg_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 -define tx_pg_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 -define tx_pg_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 -define tx_pg_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 -define tx_pg_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 -define tx_pg_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 -define tx_pg_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 -define tx_pg_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 -define tx_clk_bist_err=48:49; #start_bit=48, number_of_bit=2 -define tx_clk_bist_done=50:51; #start_bit=50, number_of_bit=2 -#define #tx_cntl_stat_pg_spare=48:48; #start_bit=48, number_of_bit=1 -define tx_max_bad_lanes=48:52; #start_bit=48, number_of_bit=5 -define tx_msbswap=53:53; #start_bit=53, number_of_bit=1 -define tx_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 -define tx_fir_reset=63:63; #start_bit=63, number_of_bit=1 -define tx_pg_fir_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_pg_fir_errs=48:55; #start_bit=48, number_of_bit=8 -define tx_pg_fir_err_pg_regs=48:48; #start_bit=48, number_of_bit=1 -define tx_pg_fir_err_gcr_buff=49:49; #start_bit=49, number_of_bit=1 -define tx_pg_fir_err_stat_rpr_snd_msg_sm=51:51; #start_bit=51, number_of_bit=1 -define tx_pg_fir_err_gcrs_ld_sm=52:52; #start_bit=52, number_of_bit=1 -define tx_pg_fir_err_gcrs_unld_sm=53:53; #start_bit=53, number_of_bit=1 -define tx_pl_fir_err=63:63; #start_bit=63, number_of_bit=1 -define tx_pg_fir_err_mask_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_pg_fir_errs_mask=48:55; #start_bit=48, number_of_bit=8 -define tx_pg_fir_err_mask_pg_regs=48:48; #start_bit=48, number_of_bit=1 -define tx_pg_fir_err_mask_gcr_buff=49:49; #start_bit=49, number_of_bit=1 -define tx_pg_fir_err_mask_stat_rpr_snd_msg_sm=51:51; #start_bit=51, number_of_bit=1 -define tx_pg_fir_err_mask_gcrs_ld_sm=52:52; #start_bit=52, number_of_bit=1 -define tx_pg_fir_err_mask_gcrs_unld_sm=53:53; #start_bit=53, number_of_bit=1 -define tx_pl_fir_err_mask=63:63; #start_bit=63, number_of_bit=1 -define tx_pg_fir_err_inj_full_reg=48:63; #start_bit=48, number_of_bit=16 -define tx_pg_fir_err_inj=48:55; #start_bit=48, number_of_bit=8 -define tx_pg_fir_err_inj_pg_regs=48:48; #start_bit=48, number_of_bit=1 -define tx_pg_fir_err_inj_gcr_buff=49:49; #start_bit=49, number_of_bit=1 -define tx_pg_fir_err_inj_stat_rpr_snd_msg_sm=51:51; #start_bit=51, number_of_bit=1 -define tx_pg_fir_err_inj_gcrs_ld_sm=52:52; #start_bit=52, number_of_bit=1 -define tx_pg_fir_err_inj_gcrs_unld_sm=53:53; #start_bit=53, number_of_bit=1 -define tx_bus_id=48:53; #start_bit=48, number_of_bit=6 -define tx_group_id=55:60; #start_bit=55, number_of_bit=6 -define tx_last_group_id=48:53; #start_bit=48, number_of_bit=6 -define tx_start_lane_id=49:55; #start_bit=49, number_of_bit=7 -define tx_end_lane_id=57:63; #start_bit=57, number_of_bit=7 -define tx_drv_clk_pattern_gcrmsg=48:49; #start_bit=48, number_of_bit=2 -define tx_wt_en_all_clk_segs_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define tx_wt_en_all_data_segs_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define tx_bad_lane1_gcrmsg=48:54; #start_bit=48, number_of_bit=7 -define tx_bad_lane2_gcrmsg=55:61; #start_bit=55, number_of_bit=7 -define tx_bad_lane_code_gcrmsg=62:63; #start_bit=62, number_of_bit=2 -define tx_sls_lane_gcrmsg=48:54; #start_bit=48, number_of_bit=7 -define tx_sls_lane_val_gcrmsg=55:55; #start_bit=55, number_of_bit=1 -#define #tx_term_n_mode_enc=48:51; #start_bit=48, number_of_bit=4 -#define #tx_term_p_mode_enc=52:55; #start_bit=52, number_of_bit=4 -#define #tx_term_test_mode=56:56; #start_bit=56, number_of_bit=1 -#define #tx_termffe_n_mode_enc=57:59; #start_bit=57, number_of_bit=3 -#define #tx_termffe_p_mode_enc=61:63; #start_bit=61, number_of_bit=3 -define tx_pc_test_mode=48:48; #start_bit=48, number_of_bit=1 -#define #tx_ffe_slice_en_enc=49:51; #start_bit=49, number_of_bit=3 -define tx_main_slice_en_enc=52:55; #start_bit=52, number_of_bit=4 -#define #tx_mt_slice_en_enc=57:59; #start_bit=57, number_of_bit=3 -define tx_pc_slice_en_enc=60:63; #start_bit=60, number_of_bit=4 -define tx_slewctl=48:51; #start_bit=48, number_of_bit=4 -#define #tx_pvtnb_enc=52:53; #start_bit=52, number_of_bit=2 -#define #tx_pvtpb_enc=54:55; #start_bit=54, number_of_bit=2 -define tx_pvtnl_enc=58:59; #start_bit=58, number_of_bit=2 -define tx_pvtpl_enc=62:63; #start_bit=62, number_of_bit=2 -define tx_lane_disabled_vec_0_15=48:63; #start_bit=48, number_of_bit=16 -define tx_lane_disabled_vec_16_31=48:63; #start_bit=48, number_of_bit=16 -define tx_sls_lane_shdw_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define tx_sls_hndshk_state=48:52; #start_bit=48, number_of_bit=5 -define tx_slv_mv_sls_shdw_req_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define tx_slv_mv_sls_shdw_rpr_req_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define tx_slv_mv_sls_unshdw_req_gcrmsg=50:50; #start_bit=50, number_of_bit=1 -define tx_slv_mv_sls_unshdw_rpr_req_gcrmsg=51:51; #start_bit=51, number_of_bit=1 -define tx_bus_width=52:58; #start_bit=52, number_of_bit=7 -define tx_slv_mv_sls_rpr_req_gcrmsg=59:59; #start_bit=59, number_of_bit=1 -define tx_sls_lane_sel_lg_gcrmsg=60:60; #start_bit=60, number_of_bit=1 -define tx_sls_lane_unsel_lg_gcrmsg=61:61; #start_bit=61, number_of_bit=1 -define tx_rdt_mode=48:48; #start_bit=48, number_of_bit=1 -define tx_run_rdt=49:49; #start_bit=49, number_of_bit=1 -define tx_wt_pattern_length=48:49; #start_bit=48, number_of_bit=2 -define tx_reduced_scramble_mode=48:49; #start_bit=48, number_of_bit=2 -define tx_prbs_scramble_mode=50:51; #start_bit=50, number_of_bit=2 -define tx_ei3_mode=63:63; #start_bit=63, number_of_bit=1 -define tx_bist_en=48:48; #start_bit=48, number_of_bit=1 -define tx_bist_clr=49:49; #start_bit=49, number_of_bit=1 -define tx_snd_sls_cmd_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define tx_dyn_recal_tsr_ignore_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define tx_sls_cmd_gcrmsg=50:55; #start_bit=50, number_of_bit=6 -define tx_snd_sls_cmd_prev_gcrmsg=56:56; #start_bit=56, number_of_bit=1 -define tx_snd_sls_using_reg_scramble=57:57; #start_bit=57, number_of_bit=1 -define tx_err_inj_a_rand_beat_dis=48:48; #start_bit=48, number_of_bit=1 -define tx_err_inj_a_fine_sel=49:51; #start_bit=49, number_of_bit=3 -define tx_err_inj_a_coarse_sel=52:55; #start_bit=52, number_of_bit=4 -define tx_err_inj_a_ber_sel=58:63; #start_bit=58, number_of_bit=6 -define tx_err_inj_b_rand_beat_dis=48:48; #start_bit=48, number_of_bit=1 -define tx_err_inj_b_fine_sel=49:51; #start_bit=49, number_of_bit=3 -define tx_err_inj_b_coarse_sel=52:55; #start_bit=52, number_of_bit=4 -define tx_err_inj_b_ber_sel=58:63; #start_bit=58, number_of_bit=6 -define tx_err_inj_sls_mode=48:48; #start_bit=48, number_of_bit=1 -define tx_err_inj_sls_all_cmd=49:49; #start_bit=49, number_of_bit=1 -define tx_err_inj_sls_recal=50:50; #start_bit=50, number_of_bit=1 -define tx_err_inj_sls_cmd=58:63; #start_bit=58, number_of_bit=6 -define tx_enable_reduced_scramble=48:48; #start_bit=48, number_of_bit=1 -define tx_reset_cfg_hld=48:63; #start_bit=48, number_of_bit=16 -define tx_tdr_pulse_offset=48:59; #start_bit=48, number_of_bit=12 -define tx_tdr_pulse_width=48:59; #start_bit=48, number_of_bit=12 -define rx_mode_pl_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_lane_pdwn=48:48; #start_bit=48, number_of_bit=1 -#define #rx_lane_invert=49:49; #start_bit=49, number_of_bit=1 -#define #rx_lane_known_bad=50:50; #start_bit=50, number_of_bit=1 -define rx_lane_scramble_disable=54:54; #start_bit=54, number_of_bit=1 -define rx_block_lock_lane=48:48; #start_bit=48, number_of_bit=1 -define rx_check_skew_lane=49:49; #start_bit=49, number_of_bit=1 -define rx_offcal_mode=51:51; #start_bit=51, number_of_bit=1 -define rx_pl_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 -define rx_pl_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 -define rx_pl_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 -define rx_pl_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 -define rx_pl_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 -define rx_pl_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 -define rx_pl_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 -define rx_pl_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 -#define #rx_lane_id_pl=48:52; #start_bit=48, number_of_bit=5 -define rx_bist_err=48:48; #start_bit=48, number_of_bit=1 -define rx_bist_done=49:49; #start_bit=49, number_of_bit=1 -#define ##rx_ddc_disable=48:48; #start_bit=48, number_of_bit=1 -#define #rx_eyeopt_stat_tbd=48:48; #start_bit=48, number_of_bit=1 -define rx_offset_even_samp1=49:55; #start_bit=49, number_of_bit=7 -#define #rx_offset_even_samp1=50:55; #start_bit=50, number_of_bit=6 -define rx_offset_even_samp0=57:63; #start_bit=57, number_of_bit=7 -#define #rx_offset_even_samp0=58:63; #start_bit=58, number_of_bit=6 -define rx_offset_odd_samp1=49:55; #start_bit=49, number_of_bit=7 -#define #rx_offset_odd_samp1=50:55; #start_bit=50, number_of_bit=6 -define rx_offset_odd_samp0=57:63; #start_bit=57, number_of_bit=7 -#define #rx_offset_odd_samp0=58:63; #start_bit=58, number_of_bit=6 -#define #rx_amp_peak=48:51; #start_bit=48, number_of_bit=4 -define rx_amp_peak=48:53; #start_bit=48, number_of_bit=6 -#define #rx_wiretest_lane_bad=48:48; #start_bit=48, number_of_bit=1 -#define #rx_lane_inverted=49:49; #start_bit=49, number_of_bit=1 -#define #rx_lane_fault_details=52:54; #start_bit=52, number_of_bit=3 -define rx_fifo_l2u_dly=48:51; #start_bit=48, number_of_bit=4 -#define #rx_fifo_cntl_spare=51:51; #start_bit=51, number_of_bit=1 -define rx_bad_block_lock=48:48; #start_bit=48, number_of_bit=1 -define rx_bad_skew=49:49; #start_bit=49, number_of_bit=1 -define rx_bad_deskew=50:50; #start_bit=50, number_of_bit=1 -define rx_bad_eye_opt_ber=48:48; #start_bit=48, number_of_bit=1 -define rx_bad_eye_opt_width=49:49; #start_bit=49, number_of_bit=1 -define rx_vref =48:55; #start_bit=48, number_of_bit=8 -define rx_pl_fir_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_pl_fir_errs=48:48; #start_bit=48, number_of_bit=1 -define rx_pl_fir_err_pl_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pl_fir_errs_mask_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_pl_fir_errs_mask=48:48; #start_bit=48, number_of_bit=1 -define rx_pl_fir_err_mask_pl_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pl_fir_err_inj_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_pl_fir_err_inj=48:48; #start_bit=48, number_of_bit=1 -define rx_pl_fir_err_inj_pl_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_prbs_tap_id=48:50; #start_bit=48, number_of_bit=3 -define rx_some_block_locked=48:48; #start_bit=48, number_of_bit=1 -define rx_all_block_locked_b=49:49; #start_bit=49, number_of_bit=1 -define rx_some_skew_valid=50:50; #start_bit=50, number_of_bit=1 -define rx_all_skew_valid_b=51:51; #start_bit=51, number_of_bit=1 -define rx_some_prbs_synced=52:52; #start_bit=52, number_of_bit=1 -define rx_prbs_synced_b=53:53; #start_bit=53, number_of_bit=1 -define rx_skew_value=54:59; #start_bit=54, number_of_bit=6 -define rx_sls_lane_sel=48:48; #start_bit=48, number_of_bit=1 -define rx_9th_pattern_en=49:49; #start_bit=49, number_of_bit=1 -define rx_wt_lane_disabled=48:48; #start_bit=48, number_of_bit=1 -define rx_wt_lane_inverted=49:49; #start_bit=49, number_of_bit=1 -define rx_wt_lane_bad_code=50:52; #start_bit=50, number_of_bit=3 -define rx_wt_lane_status_alias=49:52; #start_bit=49, number_of_bit=4 -define rx_phaserot_offset=49:55; #start_bit=49, number_of_bit=7 -define rx_phaserot_val=49:55; #start_bit=49, number_of_bit=7 -#define #rx_phaserot_left_edge=49:55; #start_bit=49, number_of_bit=7 -#define #rx_phaserot_gb_hist_valid=48:48; #start_bit=48, number_of_bit=1 -#define #rx_phaserot_gb_hist=51:55; #start_bit=51, number_of_bit=5 -define rx_eye_width=50:55; #start_bit=50, number_of_bit=6 -define rx_hist_min_eye_width_valid=56:56; #start_bit=56, number_of_bit=1 -define rx_hist_min_eye_width=58:63; #start_bit=58, number_of_bit=6 -define rx_ber_count=48:55; #start_bit=48, number_of_bit=8 -define rx_ber_count_saturated=56:56; #start_bit=56, number_of_bit=1 -define rx_ber_count_frozen_by_lane=57:57; #start_bit=57, number_of_bit=1 -define rx_ber_count_frozen_by_timer=58:58; #start_bit=58, number_of_bit=1 -define rx_ber_timer_saturated=59:59; #start_bit=59, number_of_bit=1 -define rx_ber_timer_value_0_15=48:63; #start_bit=48, number_of_bit=16 -define rx_ber_timer_value_16_31=48:63; #start_bit=48, number_of_bit=16 -define rx_ber_timer_value_32_39=48:55; #start_bit=48, number_of_bit=8 -define rx_servo_op_done=48:48; #start_bit=48, number_of_bit=1 -define rx_servo_op_all_done_b=49:49; #start_bit=49, number_of_bit=1 -define rx_servo_op=50:54; #start_bit=50, number_of_bit=5 -define rx_fifo_out_0_15=48:63; #start_bit=48, number_of_bit=16 -define rx_fifo_out_16_31=48:63; #start_bit=48, number_of_bit=16 -define rx_fifo_out_32_47=48:63; #start_bit=48, number_of_bit=16 -define rx_ln_trc_en=48:48; #start_bit=48, number_of_bit=1 -define rx_servo_ber_count=48:59; #start_bit=48, number_of_bit=12 -define rx_dcd_adjust=48:51; #start_bit=48, number_of_bit=4 -define rx_clk_pdwn=48:48; #start_bit=48, number_of_bit=1 -define rx_clk_invert=49:49; #start_bit=49, number_of_bit=1 -define rx_clk_amp_peak=58:63; #start_bit=58, number_of_bit=6 -define rx_pg_spare_mode_0=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_spare_mode_1=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_spare_mode_2=50:50; #start_bit=50, number_of_bit=1 -define rx_pg_spare_mode_3=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_spare_mode_4=52:52; #start_bit=52, number_of_bit=1 -#define #rx_pg_spare_mode_5=53:53; #start_bit=53, number_of_bit=1 -#define #rx_pg_spare_mode_6=54:54; #start_bit=54, number_of_bit=1 -#define #rx_pg_spare_mode_7=55:55; #start_bit=55, number_of_bit=1 -define rx_sls_extend_sel=53:55; #start_bit=53, number_of_bit=3 -define rx_master_mode=48:48; #start_bit=48, number_of_bit=1 -define rx_disable_fence_reset=49:49; #start_bit=49, number_of_bit=1 -define rx_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 -define rx_fir_reset=63:63; #start_bit=63, number_of_bit=1 -define rx_bus_id=48:53; #start_bit=48, number_of_bit=6 -define rx_group_id=55:60; #start_bit=55, number_of_bit=6 -define rx_last_group_id=48:53; #start_bit=48, number_of_bit=6 -define rx_start_lane_id=49:55; #start_bit=49, number_of_bit=7 -define rx_end_lane_id=57:63; #start_bit=57, number_of_bit=7 -define rx_sls_disable=48:48; #start_bit=48, number_of_bit=1 -define tx_sls_disable=49:49; #start_bit=49, number_of_bit=1 -define rx_sls_cntr_tap_pts=50:51; #start_bit=50, number_of_bit=2 -define rx_nonsls_cntr_tap_pts=52:53; #start_bit=52, number_of_bit=2 -define rx_sls_err_chk_run=54:54; #start_bit=54, number_of_bit=1 -define rx_start_wderf_alias=48:52; #start_bit=48, number_of_bit=5 -define rx_start_wiretest=48:48; #start_bit=48, number_of_bit=1 -define rx_start_deskew=49:49; #start_bit=49, number_of_bit=1 -define rx_start_eye_opt=50:50; #start_bit=50, number_of_bit=1 -define rx_start_repair=51:51; #start_bit=51, number_of_bit=1 -define rx_start_func_mode=52:52; #start_bit=52, number_of_bit=1 -define rx_start_bist=53:53; #start_bit=53, number_of_bit=1 -define rx_start_offset_cal=54:54; #start_bit=54, number_of_bit=1 -define rx_start_wt_bypass=55:55; #start_bit=55, number_of_bit=1 -define rx_wderf_done_alias=48:52; #start_bit=48, number_of_bit=5 -define rx_wiretest_done=48:48; #start_bit=48, number_of_bit=1 -define rx_deskew_done=49:49; #start_bit=49, number_of_bit=1 -define rx_eye_opt_done=50:50; #start_bit=50, number_of_bit=1 -define rx_repair_done=51:51; #start_bit=51, number_of_bit=1 -define rx_func_mode_done=52:52; #start_bit=52, number_of_bit=1 -define rx_bist_started=53:53; #start_bit=53, number_of_bit=1 -define rx_offset_cal_done=54:54; #start_bit=54, number_of_bit=1 -define rx_wt_bypass_done=55:55; #start_bit=55, number_of_bit=1 -define rx_wderf_failed_alias=56:60; #start_bit=56, number_of_bit=5 -define rx_wiretest_failed=56:56; #start_bit=56, number_of_bit=1 -define rx_deskew_failed=57:57; #start_bit=57, number_of_bit=1 -define rx_eye_opt_failed=58:58; #start_bit=58, number_of_bit=1 -define rx_repair_failed=59:59; #start_bit=59, number_of_bit=1 -define rx_func_mode_failed=60:60; #start_bit=60, number_of_bit=1 -define rx_start_bist_failed=61:61; #start_bit=61, number_of_bit=1 -define rx_offset_cal_failed=62:62; #start_bit=62, number_of_bit=1 -define rx_wt_bypass_failed=63:63; #start_bit=63, number_of_bit=1 -define rx_recal_status=48:63; #start_bit=48, number_of_bit=16 -define rx_wt_check_count=48:52; #start_bit=48, number_of_bit=5 -define rx_wt_check_lanes=53:54; #start_bit=53, number_of_bit=2 -define rx_wt_enable_term_mode=55:55; #start_bit=55, number_of_bit=1 -define rx_wt_term_phase=56:56; #start_bit=56, number_of_bit=1 -define rx_wt_term_mode_enc=57:61; #start_bit=57, number_of_bit=5 -define rx_sls_timeout_sel=48:50; #start_bit=48, number_of_bit=3 -define rx_sls_timeout_sel_dd2=48:51; #start_bit=49, number_of_bit=4 -define rx_ds_bl_timeout_sel=51:53; #start_bit=51, number_of_bit=3 -define rx_ds_bl_timeout_sel_dd2=52:54; #start_bit=52, number_of_bit=3 -define rx_cl_timeout_sel=54:56; #start_bit=54, number_of_bit=3 -define rx_cl_timeout_sel_dd2=55:57; #start_bit=55, number_of_bit=3 -define rx_wt_timeout_sel=57:59; #start_bit=57, number_of_bit=3 -define rx_wt_timeout_sel_dd2=58:60; #start_bit=58, number_of_bit=3 -define rx_ds_timeout_sel=60:62; #start_bit=60, number_of_bit=3 -define rx_ds_timeout_sel_dd2=61:63; #start_bit=61, number_of_bit=3 -define rx_eo_offset_timeout_sel=48:50; #start_bit=48, number_of_bit=3 -define rx_eo_vref_timeout_sel=51:53; #start_bit=51, number_of_bit=3 -define rx_eo_ctle_timeout_sel=54:56; #start_bit=54, number_of_bit=3 -define rx_eo_et_timeout_sel=60:62; #start_bit=60, number_of_bit=3 -define rx_eo_final_l2u_timeout_sel=63:63; #start_bit=63, number_of_bit=1 -define rx_func_mode_timeout_sel=48:50; #start_bit=48, number_of_bit=3 -define rx_rc_slowdown_timeout_sel=51:53; #start_bit=51, number_of_bit=3 -define rx_pup_lite_wait_sel=54:55; #start_bit=54, number_of_bit=2 -define rx_fifo_initial_l2u_dly=48:51; #start_bit=48, number_of_bit=4 -define rx_fifo_final_l2u_dly=52:55; #start_bit=52, number_of_bit=4 -define rx_fifo_max_deskew=56:59; #start_bit=56, number_of_bit=4 -define rx_fifo_final_l2u_min_err_thresh=60:61; #start_bit=60, number_of_bit=2 -#define #rx_start_at_state_en=48:48; #start_bit=48, number_of_bit=1 -#define #rx_stop_at_state_en=49:49; #start_bit=49, number_of_bit=1 -#define #rx_state_stopped=50:50; #start_bit=50, number_of_bit=1 -#define #rx_cur_state=51:58; #start_bit=51, number_of_bit=8 -#define #rx_start_state=48:55; #start_bit=48, number_of_bit=8 -#define #rx_stop_state=56:63; #start_bit=56, number_of_bit=8 -define rx_sls_cmd_val=48:48; #start_bit=48, number_of_bit=1 -define rx_sls_cmd_encode=50:55; #start_bit=50, number_of_bit=6 -define rx_sls_err_chk_cnt=56:63; #start_bit=56, number_of_bit=8 -define rx_pg_fir_training_error=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_static_spare_deployed=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_static_max_spares_exceeded=50:50; #start_bit=50, number_of_bit=1 -define rx_pg_fir_dynamic_repair_error=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_dynamic_spare_deployed=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_dynamic_max_spares_exceeded=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_recal_error=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir_recal_spare_deployed=55:55; #start_bit=55, number_of_bit=1 -define rx_pg_fir_recal_max_spares_exceeded=56:56; #start_bit=56, number_of_bit=1 -define rx_pg_fir_too_many_bus_errors=57:57; #start_bit=57, number_of_bit=1 -define rx_pg_fir_training_error_mask=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_static_spare_deployed_mask=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_static_max_spares_exceeded_mask=50:50; #start_bit=50, number_of_bit=1 -define rx_pg_fir_dynamic_repair_error_mask=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_dynamic_spare_deployed_mask=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_dynamic_max_spares_exceeded_mask=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_recal_error_mask=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir_recal_spare_deployed_mask=55:55; #start_bit=55, number_of_bit=1 -define rx_pg_fir_recal_max_spares_exceeded_mask=56:56; #start_bit=56, number_of_bit=1 -define rx_pg_fir_too_many_bus_errors_mask=57:57; #start_bit=57, number_of_bit=1 -define rx_pg_fir1_errs_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_pg_fir1_errs=48:61; #start_bit=48, number_of_bit=14 -define rx_pg_fir_err_pg_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_err_gcr_buff=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_err_gcrs_ld_sm=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_err_gcrs_unld_sm=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_err_glb_init_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_err_main_init_sm=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir_err_wtm_sm=55:55; #start_bit=55, number_of_bit=1 -define rx_pg_fir_err_wtr_sm=56:56; #start_bit=56, number_of_bit=1 -define rx_pg_fir_err_wtl_sm=57:57; #start_bit=57, number_of_bit=1 -define rx_pg_fir_err_rpr_sm=58:58; #start_bit=58, number_of_bit=1 -define rx_pg_fir_err_eyeopt_sm=59:59; #start_bit=59, number_of_bit=1 -define rx_pg_fir_err_dsm_sm=60:60; #start_bit=60, number_of_bit=1 -define rx_pg_fir_err_rxdsm_sm=61:61; #start_bit=61, number_of_bit=1 -define rx_pg_chan_fail_rsvd=62:62; #start_bit=62, number_of_bit=1 -define rx_pl_fir_err=63:63; #start_bit=63, number_of_bit=1 -define rx_pg_fir2_errs_full_reg=48:54; #start_bit=48, number_of_bit=7 -define rx_pg_fir2_errs=48:54; #start_bit=48, number_of_bit=7 -define rx_pg_fir_err_dyn_rpr_sm=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_err_sls_hndshk_sm=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_err_dyn_rpr_snd_msg_sm=50:50; #start_bit=50, number_of_bit=1 -define rx_pg_fir_err_recal_sm=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_err_sls_enc_snd_msg_sm=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_err_glb_cal_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_err_stat_rpr_snd_msg_sm=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir1_errs_mask_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_pg_fir1_errs_mask=48:61; #start_bit=48, number_of_bit=14 -define rx_pg_fir_err_mask_pg_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_err_mask_gcr_buff=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_err_mask_gcrs_ld_sm=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_err_mask_gcrs_unld_sm=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_err_mask_glb_init_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_err_mask_main_init_sm=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir_err_mask_wtm_sm=55:55; #start_bit=55, number_of_bit=1 -define rx_pg_fir_err_mask_wtr_sm=56:56; #start_bit=56, number_of_bit=1 -define rx_pg_fir_err_mask_wtl_sm=57:57; #start_bit=57, number_of_bit=1 -define rx_pg_fir_err_mask_rpr_sm=58:58; #start_bit=58, number_of_bit=1 -define rx_pg_fir_err_mask_eyeopt_sm=59:59; #start_bit=59, number_of_bit=1 -define rx_pg_fir_err_mask_dsm_sm=60:60; #start_bit=60, number_of_bit=1 -define rx_pg_fir_err_mask_rxdsm_sm=61:61; #start_bit=61, number_of_bit=1 -define rx_pl_fir_err_mask=63:63; #start_bit=63, number_of_bit=1 -define rx_pg_fir2_errs_mask_full_reg=48:54; #start_bit=48, number_of_bit=7 -define rx_pg_fir2_errs_mask=48:54; #start_bit=48, number_of_bit=7 -define rx_pg_fir_err_mask_dyn_rpr_sm=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_err_mask_sls_hndshk_sm=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_err_mask_dyn_rpr_snd_msg_sm=50:50; #start_bit=50, number_of_bit=1 -define rx_pg_fir_err_mask_recal_sm=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_err_mask_sls_enc_snd_msg_sm=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_err_mask_glb_cal_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_err_mask_stat_rpr_snd_msg_sm=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir1_err_inj_full_reg=48:63; #start_bit=48, number_of_bit=16 -define rx_pg_fir1_err_inj=48:61; #start_bit=48, number_of_bit=14 -define rx_pg_fir_err_inj_pg_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_err_inj_gcr_buff=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_err_inj_gcrs_ld_sm=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_err_inj_gcrs_unld_sm=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_err_inj_glb_init_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_err_inj_main_init_sm=54:54; #start_bit=54, number_of_bit=1 -define rx_pg_fir_err_inj_wtm_sm=55:55; #start_bit=55, number_of_bit=1 -define rx_pg_fir_err_inj_wtr_sm=56:56; #start_bit=56, number_of_bit=1 -define rx_pg_fir_err_inj_wtl_sm=57:57; #start_bit=57, number_of_bit=1 -define rx_pg_fir_err_inj_rpr_sm=58:58; #start_bit=58, number_of_bit=1 -define rx_pg_fir_err_inj_eyeopt_sm=59:59; #start_bit=59, number_of_bit=1 -define rx_pg_fir_err_inj_dsm_sm=60:60; #start_bit=60, number_of_bit=1 -define rx_pg_fir_err_inj_rxdsm_sm=61:61; #start_bit=61, number_of_bit=1 -define rx_pg_fir2_err_inj_full_reg=48:54; #start_bit=48, number_of_bit=7 -define rx_pg_fir2_err_inj=48:54; #start_bit=48, number_of_bit=7 -define rx_pg_fir_err_inj_dyn_rpr_sm=48:48; #start_bit=48, number_of_bit=1 -define rx_pg_fir_err_inj_sls_hndshk_sm=49:49; #start_bit=49, number_of_bit=1 -define rx_pg_fir_err_inj_dyn_rpr_snd_msg_sm=50:50; #start_bit=50, number_of_bit=1 -define rx_pg_fir_err_inj_recal_sm=51:51; #start_bit=51, number_of_bit=1 -define rx_pg_fir_err_inj_sls_enc_snd_msg_sm=52:52; #start_bit=52, number_of_bit=1 -define rx_pg_fir_err_inj_glb_cal_snd_msg_sm=53:53; #start_bit=53, number_of_bit=1 -define rx_pg_fir_err_inj_stat_rpr_snd_msg_sm=54:54; #start_bit=54, number_of_bit=1 -define rx_lane_bad_vec_0_15=48:63; #start_bit=48, number_of_bit=16 -define rx_lane_bad_vec_16_31=48:63; #start_bit=48, number_of_bit=16 -define rx_lane_disabled_vec_0_15=48:63; #start_bit=48, number_of_bit=16 -define rx_lane_disabled_vec_16_31=48:63; #start_bit=48, number_of_bit=16 -define rx_lane_swapped_vec_0_15=48:63; #start_bit=48, number_of_bit=16 -define rx_lane_swapped_vec_16_31=48:63; #start_bit=48, number_of_bit=16 -define rx_main_init_state=48:51; #start_bit=48, number_of_bit=4 -define rx_wtm_state=48:52; #start_bit=48, number_of_bit=5 -define rx_wtr_state=53:56; #start_bit=53, number_of_bit=4 -define rx_wtl_state=59:63; #start_bit=59, number_of_bit=5 -define rx_wtl_done_alias=59:59; #start_bit=59, number_of_bit=1 -define rx_wtl_p_n_swap_alias=60:60; #start_bit=60, number_of_bit=1 -define rx_wtl_fault_code_alias=61:63; #start_bit=61, number_of_bit=3 -define rx_wtr_cur_lane=48:52; #start_bit=48, number_of_bit=5 -define rx_wtr_max_bad_lanes=53:57; #start_bit=53, number_of_bit=5 -define rx_wtr_bad_lane_count=59:63; #start_bit=59, number_of_bit=5 -define rx_wt_prev_done_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define rx_wt_all_done_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define rx_wt_cu_pll_pgood=48:48; #start_bit=48, number_of_bit=1 -define rx_wt_cu_pll_reset=49:49; #start_bit=49, number_of_bit=1 -define rx_wt_cu_pll_pgooddly=50:52; #start_bit=50, number_of_bit=3 -define rx_wt_cu_pll_lock=53:53; #start_bit=53, number_of_bit=1 -define rx_wt_pll_refclksel=54:54; #start_bit=54, number_of_bit=1 -define rx_dll1_cal_good=48:48; #start_bit=48, number_of_bit=1 -define rx_dll1_cal_error=49:49; #start_bit=49, number_of_bit=1 -define rx_dll1_cal_error_fine=50:50; #start_bit=50, number_of_bit=1 -define rx_dll1_cal_skip=51:52; #start_bit=51, number_of_bit=2 -define rx_dll1_coarse_adj_by2=53:53; #start_bit=53, number_of_bit=1 -define rx_dll2_cal_good=56:56; #start_bit=56, number_of_bit=1 -define rx_dll2_cal_error=57:57; #start_bit=57, number_of_bit=1 -define rx_dll2_cal_error_fine=58:58; #start_bit=58, number_of_bit=1 -define rx_dll2_cal_skip=59:60; #start_bit=59, number_of_bit=2 -define rx_dll2_coarse_adj_by2=61:61; #start_bit=61, number_of_bit=1 -define rx_dll1_coarse_en=48:53; #start_bit=48, number_of_bit=6 -define rx_dll1_vreg_dac_coarse=55:61; #start_bit=55, number_of_bit=7 -define rx_dll1_vreg_dac_lower=48:62; #start_bit=48, number_of_bit=15 -define rx_dll1_vreg_dac_upper=48:62; #start_bit=48, number_of_bit=15 -define rx_dll2_coarse_en=48:53; #start_bit=48, number_of_bit=6 -define rx_dll2_vreg_dac_coarse=55:61; #start_bit=55, number_of_bit=7 -define rx_dll2_vreg_dac_lower=48:62; #start_bit=48, number_of_bit=15 -define rx_dll2_vreg_dac_upper=48:62; #start_bit=48, number_of_bit=15 -define rx_dll_dll_filter_length=48:50; #start_bit=48, number_of_bit=3 -define rx_dll_dll_lead_lag_separation=52:54; #start_bit=52, number_of_bit=3 -define rx_dll_vreg_con=48:48; #start_bit=48, number_of_bit=1 -define rx_dll_vreg_compcon=49:51; #start_bit=49, number_of_bit=3 -define rx_dll_vreg_ref_sel=52:54; #start_bit=52, number_of_bit=3 -define rx_dll1_vreg_drvcon=55:57; #start_bit=55, number_of_bit=3 -define rx_dll2_vreg_drvcon=58:60; #start_bit=58, number_of_bit=3 -define rx_dll_vreg_dac_pullup=61:61; #start_bit=61, number_of_bit=1 -define rx_deskew_seq_gcrmsg=48:50; #start_bit=48, number_of_bit=3 -define rx_deskew_skmin_gcrmsg=52:57; #start_bit=52, number_of_bit=6 -define rx_deskew_skmax_gcrmsg=58:63; #start_bit=58, number_of_bit=6 -define rx_dsm_state=50:55; #start_bit=50, number_of_bit=6 -define rx_rxdsm_state=57:63; #start_bit=57, number_of_bit=7 -define rx_deskew_max_limit=48:53; #start_bit=48, number_of_bit=6 -define rx_deskew_minskew_grp=48:53; #start_bit=48, number_of_bit=6 -define rx_deskew_maxskew_grp=54:59; #start_bit=54, number_of_bit=6 -define rx_bad_lane1_gcrmsg=48:54; #start_bit=48, number_of_bit=7 -define rx_bad_lane2_gcrmsg=55:61; #start_bit=55, number_of_bit=7 -define rx_bad_lane_code_gcrmsg=62:63; #start_bit=62, number_of_bit=2 -define rx_rpr_state=48:53; #start_bit=48, number_of_bit=6 -define rx_func_mode_state=48:51; #start_bit=48, number_of_bit=4 -define rx_tx_bus_width=48:54; #start_bit=48, number_of_bit=7 -define rx_rx_bus_width=55:61; #start_bit=55, number_of_bit=7 -define rx_sls_lane_gcrmsg=48:54; #start_bit=48, number_of_bit=7 -define rx_sls_lane_val_gcrmsg=55:55; #start_bit=55, number_of_bit=1 -define rx_fence =48:48; #start_bit=48, number_of_bit=1 -define rx_term_test_mode=48:48; #start_bit=48, number_of_bit=1 -#define #rx_term_n_mode_enc=48:51; #start_bit=48, number_of_bit=4 -define rx_term_mode_enc=51:55; #start_bit=51, number_of_bit=5 -#define #rx_termffe_n_mode_enc=57:59; #start_bit=57, number_of_bit=3 -#define #rx_termffe_p_mode_enc=61:63; #start_bit=61, number_of_bit=3 -#define #rx_pc_test_mode=48:48; #start_bit=48, number_of_bit=1 -#define #rx_ffe_slice_en_enc=49:51; #start_bit=49, number_of_bit=3 -#define #rx_main_slice_en_enc=52:55; #start_bit=52, number_of_bit=4 -#define #rx_mt_slice_en_enc=57:59; #start_bit=57, number_of_bit=3 -#define #rx_pc_slice_en_enc=60:63; #start_bit=60, number_of_bit=4 -#define #rx_slewctl=48:51; #start_bit=48, number_of_bit=4 -define rx_iref_bc=52:54; #start_bit=52, number_of_bit=3 -define rx_iref_bypass=55:55; #start_bit=55, number_of_bit=1 -define rx_dyn_rpr_state=50:55; #start_bit=50, number_of_bit=6 -define rx_sls_hndshk_state=56:63; #start_bit=56, number_of_bit=8 -define rx_dyn_rpr_req_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define rx_dyn_rpr_lane2rpr_gcrmsg=49:55; #start_bit=49, number_of_bit=7 -define rx_dyn_rpr_ip_gcrmsg=56:56; #start_bit=56, number_of_bit=1 -define rx_dyn_rpr_complete_gcrmsg=57:57; #start_bit=57, number_of_bit=1 -define rx_dyn_rpr_bad_lane_max=48:54; #start_bit=48, number_of_bit=7 -define rx_dyn_rpr_err_cntr1_duration=55:58; #start_bit=55, number_of_bit=4 -define rx_dyn_rpr_clr_err_cntr1=59:59; #start_bit=59, number_of_bit=1 -define rx_dyn_rpr_disable=60:60; #start_bit=60, number_of_bit=1 -define rx_dyn_rpr_enc_bad_data_lane_width=61:63; #start_bit=61, number_of_bit=3 -define rx_gcr_msg_debug_dest_bus_id=48:53; #start_bit=48, number_of_bit=6 -define rx_gcr_msg_debug_dest_group_id=54:59; #start_bit=54, number_of_bit=6 -define rx_gcr_msg_debug_src_bus_id=48:53; #start_bit=48, number_of_bit=6 -define rx_gcr_msg_debug_src_group_id=54:59; #start_bit=54, number_of_bit=6 -define rx_gcr_msg_debug_dest_addr=48:56; #start_bit=48, number_of_bit=9 -define rx_gcr_msg_debug_send_msg=63:63; #start_bit=63, number_of_bit=1 -define rx_gcr_msg_debug_write_data=48:63; #start_bit=48, number_of_bit=16 -#define #rx_eye_opt_state=48:55; #start_bit=48, number_of_bit=8 -define rx_eye_opt_state=48:55; #start_bit=48, number_of_bit=8 -define rx_recal_state=56:63; #start_bit=56, number_of_bit=8 -define rx_wt_clk_lane_inverted=49:49; #start_bit=49, number_of_bit=1 -define rx_wt_clk_lane_bad_code=50:52; #start_bit=50, number_of_bit=3 -define rx_wt_clk_lane_status_alias=49:52; #start_bit=49, number_of_bit=4 -define rx_eo_enable_latch_offset_cal=48:48; #start_bit=48, number_of_bit=1 -define rx_eo_enable_ctle_cal=49:49; #start_bit=49, number_of_bit=1 -define rx_eo_enable_vref_cal=51:51; #start_bit=51, number_of_bit=1 -define rx_eo_enable_measure_eye_width=55:55; #start_bit=55, number_of_bit=1 -define rx_eo_enable_final_l2u_adj=56:56; #start_bit=56, number_of_bit=1 -define rx_eo_enable_ber_test=57:57; #start_bit=57, number_of_bit=1 -define rx_eo_enable_result_check=58:58; #start_bit=58, number_of_bit=1 -define rx_eo_enable_dcd_cal=60:60; #start_bit=60, number_of_bit=1 -define rx_rc_enable_edge_track=51:51; #start_bit=51, number_of_bit=1 -define rx_rc_enable_measure_eye_width=55:55; #start_bit=55, number_of_bit=1 -define rx_rc_enable_result_check=57:57; #start_bit=57, number_of_bit=1 -define rx_rc_enable_dll_update=58:58; #start_bit=58, number_of_bit=1 -define rx_eo_latch_offset_done=48:48; #start_bit=48, number_of_bit=1 -define rx_eo_ctle_done=49:49; #start_bit=49, number_of_bit=1 -define rx_eo_vref_done=51:51; #start_bit=51, number_of_bit=1 -define rx_eo_measure_eye_width_done=55:55; #start_bit=55, number_of_bit=1 -define rx_eo_final_l2u_adj_done=56:56; #start_bit=56, number_of_bit=1 -define rx_eo_result_check_done=59:59; #start_bit=59, number_of_bit=1 -define rx_eo_latch_offset_failed=48:48; #start_bit=48, number_of_bit=1 -define rx_eo_ctle_failed=49:49; #start_bit=49, number_of_bit=1 -define rx_eo_vref_failed=51:51; #start_bit=51, number_of_bit=1 -define rx_eo_measure_eye_width_failed=55:55; #start_bit=55, number_of_bit=1 -define rx_eo_final_l2u_adj_failed=56:56; #start_bit=56, number_of_bit=1 -define rx_eo_result_check_failed=57:57; #start_bit=57, number_of_bit=1 -define rx_eo_dcd_failed=58:58; #start_bit=58, number_of_bit=1 -#define #rx_amp_peak_work=48:51; #start_bit=48, number_of_bit=4 -#define #rx_amp_peak_work=48:53; #start_bit=48, number_of_bit=6 -define rx_servo_ber_count_work=48:59; #start_bit=48, number_of_bit=12 -define rx_eo_final_l2u_dly_seq_gcrmsg=48:49; #start_bit=48, number_of_bit=2 -define rx_eo_final_l2u_dly_maxchg_gcrmsg=50:55; #start_bit=50, number_of_bit=6 -define rx_eo_final_l2u_dly_chg=58:63; #start_bit=58, number_of_bit=6 -define rx_sls_rcvy_disable=48:48; #start_bit=48, number_of_bit=1 -define rx_sls_rcvy_state=51:55; #start_bit=51, number_of_bit=5 -define rx_sls_rcvy_req_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define rx_sls_rcvy_ip_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define rx_sls_rcvy_done_gcrmsg=50:50; #start_bit=50, number_of_bit=1 -define rx_tx_bad_lane_cntr_gcrmsg=48:49; #start_bit=48, number_of_bit=2 -define rx_dis_synd_tallying_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define rx_run_rdt=48:48; #start_bit=48, number_of_bit=1 -define rx_rdt_check_mask=50:54; #start_bit=50, number_of_bit=5 -define rx_rdt_failed=55:55; #start_bit=55, number_of_bit=1 -define rx_trc_mode=48:51; #start_bit=48, number_of_bit=4 -define rx_trc_grp=54:59; #start_bit=54, number_of_bit=6 -define rx_dyn_rpr_enc_bad_data_lane_debug=49:55; #start_bit=49, number_of_bit=7 -define rx_bad_bus_err_cntr=57:63; #start_bit=57, number_of_bit=7 -define rx_bad_bus_lane_err_cntr_dis_clr=48:48; #start_bit=48, number_of_bit=1 -define rx_bad_bus_lane_err_cntr=49:55; #start_bit=49, number_of_bit=7 -define rx_last_bad_bus_lane=57:63; #start_bit=57, number_of_bit=7 -define rx_dyn_rpr_bad_bus_max=48:54; #start_bit=48, number_of_bit=7 -define rx_dyn_rpr_err_cntr2_duration=55:58; #start_bit=55, number_of_bit=4 -define rx_dyn_rpr_clr_err_cntr2=59:59; #start_bit=59, number_of_bit=1 -define rx_min_eye_width=50:55; #start_bit=50, number_of_bit=6 -define rx_max_ber_check_count=56:63; #start_bit=56, number_of_bit=8 -define rx_stop_state_enable=48:48; #start_bit=48, number_of_bit=1 -define rx_state_stopped=49:49; #start_bit=49, number_of_bit=1 -define rx_stop_addr_msb=56:59; #start_bit=56, number_of_bit=4 -define rx_stop_mask_msb=60:63; #start_bit=60, number_of_bit=4 -define rx_stop_addr_lsb=48:63; #start_bit=48, number_of_bit=16 -define rx_stop_mask_lsb=48:63; #start_bit=48, number_of_bit=16 -define rx_slv_shdw_done_fin_gcrmsg=48:48; #start_bit=48, number_of_bit=1 -define rx_slv_shdw_nop_fin_gcrmsg=49:49; #start_bit=49, number_of_bit=1 -define rx_slv_shdw_rpr_done_fin_gcrmsg=50:50; #start_bit=50, number_of_bit=1 -define rx_slv_shdw_rpr_nop_fin_gcrmsg=51:51; #start_bit=51, number_of_bit=1 -define rx_slv_unshdw_done_fin_gcrmsg=52:52; #start_bit=52, number_of_bit=1 -define rx_slv_unshdw_nop_fin_gcrmsg=53:53; #start_bit=53, number_of_bit=1 -define rx_slv_unshdw_rpr_done_fin_gcrmsg=54:54; #start_bit=54, number_of_bit=1 -define rx_slv_unshdw_rpr_nop_fin_gcrmsg=55:55; #start_bit=55, number_of_bit=1 -define rx_slv_recal_done_nop_fin_gcrmsg=56:56; #start_bit=56, number_of_bit=1 -define rx_slv_recal_fail_nop_fin_gcrmsg=57:57; #start_bit=57, number_of_bit=1 -define rx_slv_recal_presults_fin_gcrmsg=58:58; #start_bit=58, number_of_bit=1 -define rx_slv_recal_fresults_fin_gcrmsg=59:59; #start_bit=59, number_of_bit=1 -define rx_slv_recal_abort_ack_fin_gcrmsg=60:60; #start_bit=60, number_of_bit=1 -define rx_slv_recal_abort_mnop_fin_gcrmsg=61:61; #start_bit=61, number_of_bit=1 -define rx_slv_recal_abort_snop_fin_gcrmsg=62:62; #start_bit=62, number_of_bit=1 -define rx_reduced_scramble_mode=48:49; #start_bit=48, number_of_bit=2 -define rx_prbs_scramble_mode=50:51; #start_bit=50, number_of_bit=2 -define rx_act_check_timeout_sel=52:54; #start_bit=52, number_of_bit=3 -define rx_block_lock_timeout_sel=55:57; #start_bit=55, number_of_bit=3 -define rx_bit_lock_timeout_sel=58:60; #start_bit=58, number_of_bit=3 -define rx_reverse_shift=62:62; #start_bit=62, number_of_bit=1 -define rx_ei3_mode=63:63; #start_bit=63, number_of_bit=1 -define rx_pp_trc_mode=48:50; #start_bit=48, number_of_bit=3 -define rx_bist_jitter_pulse_sel=51:52; #start_bit=51, number_of_bit=2 -define rx_bist_min_eye_width=53:59; #start_bit=53, number_of_bit=7 -define rx_dis_block_lock_vref=60:60; #start_bit=60, number_of_bit=1 -define rx_wt_pattern_length=61:62; #start_bit=61, number_of_bit=2 -define rx_servo_timeout_sel_a=48:51; #start_bit=48, number_of_bit=4 -define rx_servo_timeout_sel_b=52:55; #start_bit=52, number_of_bit=4 -define rx_servo_timeout_sel_c=56:59; #start_bit=56, number_of_bit=4 -define rx_servo_timeout_sel_d=60:63; #start_bit=60, number_of_bit=4 -define rx_servo_timeout_sel_e=48:51; #start_bit=48, number_of_bit=4 -define rx_servo_timeout_sel_f=52:55; #start_bit=52, number_of_bit=4 -define rx_servo_timeout_sel_g=56:59; #start_bit=56, number_of_bit=4 -define rx_servo_timeout_sel_h=60:63; #start_bit=60, number_of_bit=4 -define rx_recal_timeout_sel_a=48:51; #start_bit=48, number_of_bit=4 -define rx_recal_timeout_sel_e=48:51; #start_bit=48, number_of_bit=4 -define rx_recal_timeout_sel_f=52:55; #start_bit=52, number_of_bit=4 -#define #rx_block_lock=48:48; #start_bit=48, number_of_bit=1 -define rx_prbs_check_sync=49:49; #start_bit=49, number_of_bit=1 -define rx_enable_reduced_scramble=50:50; #start_bit=50, number_of_bit=1 -define rx_recal_in_progress=48:48; #start_bit=48, number_of_bit=1 -define rx_ddc_use_cyc_block_lock=48:48; #start_bit=48, number_of_bit=1 -define rx_peak_baud_sel=49:50; #start_bit=49, number_of_bit=2 -define rx_peak_baud_toggle_sel=51:52; #start_bit=51, number_of_bit=2 -define rx_reverse_dcd=53:53; #start_bit=53, number_of_bit=1 -define rx_cal_inc_val_a=48:51; #start_bit=48, number_of_bit=4 -define rx_cal_inc_val_b=52:55; #start_bit=52, number_of_bit=4 -define rx_cal_inc_val_c=56:59; #start_bit=56, number_of_bit=4 -define rx_cal_inc_val_d=60:63; #start_bit=60, number_of_bit=4 -define rx_cal_inc_val_e=48:51; #start_bit=48, number_of_bit=4 -define rx_cal_inc_val_f=52:55; #start_bit=52, number_of_bit=4 -define rx_cal_inc_val_g=56:59; #start_bit=56, number_of_bit=4 -define rx_cal_inc_val_h=60:63; #start_bit=60, number_of_bit=4 -define rx_cal_dec_val_a=48:51; #start_bit=48, number_of_bit=4 -define rx_cal_dec_val_b=52:55; #start_bit=52, number_of_bit=4 -define rx_cal_dec_val_c=56:59; #start_bit=56, number_of_bit=4 -define rx_cal_dec_val_d=60:63; #start_bit=60, number_of_bit=4 -define rx_cal_dec_val_e=48:51; #start_bit=48, number_of_bit=4 -define rx_cal_dec_val_f=52:55; #start_bit=52, number_of_bit=4 -define rx_cal_dec_val_g=56:59; #start_bit=56, number_of_bit=4 -define rx_cal_dec_val_h=60:63; #start_bit=60, number_of_bit=4 -define rx_reset_cfg_hld=48:63; #start_bit=48, number_of_bit=16 -define rx_bist_en=48:48; #start_bit=48, number_of_bit=1 -define rx_ber_en=48:48; #start_bit=48, number_of_bit=1 -define rx_ber_timer_freeze_en=48:48; #start_bit=48, number_of_bit=1 -define rx_ber_count_freeze_en=49:49; #start_bit=49, number_of_bit=1 -define rx_ber_count_sel=51:53; #start_bit=51, number_of_bit=3 -define rx_ber_timer_sel=54:56; #start_bit=54, number_of_bit=3 -define rx_ber_clr_count_on_read_en=57:57; #start_bit=57, number_of_bit=1 -define rx_ber_clr_timer_on_read_en=58:58; #start_bit=58, number_of_bit=1 -define rx_pb_clr_par_errs=62:62; #start_bit=62, number_of_bit=1 -define rx_pb_fir_reset=63:63; #start_bit=63, number_of_bit=1 -define rx_pb_fir_errs_full_reg=48:57; #start_bit=48, number_of_bit=10 -define rx_pb_fir_errs=48:57; #start_bit=48, number_of_bit=10 -define rx_pb_fir_err_pb_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pb_fir_err_gcr_buff0=49:49; #start_bit=49, number_of_bit=1 -define rx_pb_fir_err_gcr_buff1=50:50; #start_bit=50, number_of_bit=1 -define rx_pb_fir_err_gcr_buff2=51:51; #start_bit=51, number_of_bit=1 -define rx_pb_fir_err_gcrs_ld_sm0=52:52; #start_bit=52, number_of_bit=1 -define rx_pb_fir_err_gcrs_ld_sm1=53:53; #start_bit=53, number_of_bit=1 -define rx_pb_fir_err_gcrs_ld_sm2=54:54; #start_bit=54, number_of_bit=1 -define rx_pb_fir_err_gcrs_unld_sm0=55:55; #start_bit=55, number_of_bit=1 -define rx_pb_fir_err_gcrs_unld_sm1=56:56; #start_bit=56, number_of_bit=1 -define rx_pb_fir_err_gcrs_unld_sm2=57:57; #start_bit=57, number_of_bit=1 -define rx_pb_fir_errs_mask_full_reg=48:57; #start_bit=48, number_of_bit=10 -define rx_pb_fir_errs_mask=48:57; #start_bit=48, number_of_bit=10 -define rx_pb_fir_err_mask_pb_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pb_fir_err_mask_gcr_buff0=49:49; #start_bit=49, number_of_bit=1 -define rx_pb_fir_err_mask_gcr_buff1=50:50; #start_bit=50, number_of_bit=1 -define rx_pb_fir_err_mask_gcr_buff2=51:51; #start_bit=51, number_of_bit=1 -define rx_pb_fir_err_mask_gcrs_ld_sm0=52:52; #start_bit=52, number_of_bit=1 -define rx_pb_fir_err_mask_gcrs_ld_sm1=53:53; #start_bit=53, number_of_bit=1 -define rx_pb_fir_err_mask_gcrs_ld_sm2=54:54; #start_bit=54, number_of_bit=1 -define rx_pb_fir_err_mask_gcrs_unld_sm0=55:55; #start_bit=55, number_of_bit=1 -define rx_pb_fir_err_mask_gcrs_unld_sm1=56:56; #start_bit=56, number_of_bit=1 -define rx_pb_fir_err_mask_gcrs_unld_sm2=57:57; #start_bit=57, number_of_bit=1 -define rx_pb_fir_errs_inj_full_reg=48:57; #start_bit=48, number_of_bit=10 -define rx_pb_fir_errs_inj=48:57; #start_bit=48, number_of_bit=10 -define rx_pb_fir_err_inj_pb_regs=48:48; #start_bit=48, number_of_bit=1 -define rx_pb_fir_err_inj_gcr_buff0=49:49; #start_bit=49, number_of_bit=1 -define rx_pb_fir_err_inj_gcr_buff1=50:50; #start_bit=50, number_of_bit=1 -define rx_pb_fir_err_inj_gcr_buff2=51:51; #start_bit=51, number_of_bit=1 -define rx_pb_fir_err_inj_gcrs_ld_sm0=52:52; #start_bit=52, number_of_bit=1 -define rx_pb_fir_err_inj_gcrs_ld_sm1=53:53; #start_bit=53, number_of_bit=1 -define rx_pb_fir_err_inj_gcrs_ld_sm2=54:54; #start_bit=54, number_of_bit=1 -define rx_pb_fir_err_inj_gcrs_unld_sm0=55:55; #start_bit=55, number_of_bit=1 -define rx_pb_fir_err_inj_gcrs_unld_sm1=56:56; #start_bit=56, number_of_bit=1 -define rx_pb_fir_err_inj_gcrs_unld_sm2=57:57; #start_bit=57, number_of_bit=1 -define tx_mode_pl=010000000; #080 -define tx_cntl_stat_pl=010000001; #081 -define tx_spare_mode_pl=010000010; #082 -#define #tx_id_pl=010000100; #084 -define tx_bist_stat_pl=010000101; #085 -define tx_prbs_mode_pl=010000110; #086 -define tx_data_cntl_gcrmsg_pl=010000111; #087 -define tx_sync_pattern_gcrmsg_pl=010001000; #088 -define tx_fir_pl=010001010; #08A -define tx_fir_mask_pl=010001011; #08B -define tx_fir_error_inject_pl=010001100; #08C -define tx_mode_fast_pl=010001101; #08D -define tx_clk_mode_pg=110000000; #180 -define tx_spare_mode_pg=110000001; #181 -define tx_cntl_stat_pg=110000010; #182 -define tx_mode_pg=110000011; #183 -define tx_reset_act_pg=110001000; #188 -define tx_bist_stat_pg=110001001; #189 -define tx_fir_pg=110001010; #18A -define tx_fir_mask_pg=110001011; #18B -define tx_fir_error_inject_pg=110001100; #18C -define tx_id1_pg=110010010; #192 -define tx_id2_pg=110010011; #193 -define tx_id3_pg=110010100; #194 -define tx_clk_cntl_gcrmsg_pg=110011000; #198 -define tx_bad_lane_enc_gcrmsg_pg=110011101; #19D -define tx_ber_cntl_pg=110011110; #19E -define tx_sls_lane_enc_gcrmsg_pg=110011111; #19F -define tx_wt_seg_enable_pg=110100000; #1A0 -#define #tx_term_pg=110100000; #1A0 -define tx_pc_ffe_pg=110100001; #1A1 -define tx_misc_analog_pg=110100010; #1A2 -define tx_lane_disabled_vec_0_15_pg=110100011; #1A3 -define tx_lane_disabled_vec_16_31_pg=110100100; #1A4 -define tx_sls_lane_mux_gcrmsg_pg=110100101; #1A5 -define tx_dyn_rpr_pg=110100110; #1A6 -define tx_slv_mv_sls_ln_req_gcrmsg_pg=110100111; #1A7 -define tx_rdt_cntl_pg=110101000; #1A8 -define rx_dll_cal_cntl_pg=111000111; #1C7 -define rx_dll1_setpoint1_pg=111001000; #1C8 -define rx_dll1_setpoint2_pg=111001001; #1C9 -define rx_dll1_setpoint3_pg=111001010; #1CA -define rx_dll2_setpoint1_pg=111001011; #1CB -define rx_dll2_setpoint2_pg=111001100; #1CC -define rx_dll2_setpoint3_pg=111001101; #1CD -define rx_dll_filter_mode_pg=111001110; #1CE -define rx_dll_analog_tweaks_pg=111001111; #1CF -define tx_wiretest_pp=111010000; #1D0 -define tx_mode_pp=111010001; #1D1 -define tx_sls_gcrmsg_pp=111010010; #1D2 -define tx_ber_cntl_a_pp=111010011; #1D3 -define tx_ber_cntl_b_pp=111010100; #1D4 -define tx_bist_cntl_pp=111010110; #1D6 -define tx_ber_cntl_sls_pp=111010111; #1D7 -define tx_cntl_pp=111011000; #1D8 -define tx_reset_cfg_pp=111011001; #1D9 -define tx_tdr_cntl2_pp=111011011; #1DB -define tx_tdr_cntl3_pp=111011100; #1DC -define tx_init_version_pb=111101000; #1E8 -define tx_scratch_reg_pb=111101001; #1E9 -define rx_mode_pl=000000000; #000 -define rx_cntl_pl=000000001; #001 -define rx_spare_mode_pl=000000010; #002 -define rx_prot_edge_status_pl=000000011; #003 -#define #rx_prot_gb_status_pl=000000100; #004 -define rx_bist_stat_pl=000000101; #005 -#define ##rx_eyeopt_mode_pl=000000110; #006 -#define #rx_eyeopt_stat_pl=000000111; #007 -define rx_offset_even_pl=000001000; #008 -define rx_offset_odd_pl=000001001; #009 -define rx_amp_val_pl=000001010; #00A -define rx_prot_status_pl=000001100; #00C -define rx_prot_mode_pl=000001101; #00D -define rx_prot_cntl_pl=000001110; #00E -#define #rx_wiretest_stat_pl=000001110; #00E -define rx_fifo_stat_pl=000001111; #00F -define rx_prbs_mode_pl=000010110; #016 -define rx_vref_pl=000010111; #017 -define rx_stat_pl=000011000; #018 -define rx_deskew_stat_pl=000011001; #019 -define rx_fir_pl=000011010; #01A -define rx_fir_mask_pl=000011011; #01B -define rx_fir_error_inject_pl=000011100; #01C -define rx_sls_pl=000011101; #01D -define rx_wt_status_pl=000011110; #01E -define rx_fifo_cntl_pl=000011111; #01F -define rx_ber_status_pl=000100000; #020 -define rx_ber_timer_0_15_pl=000100001; #021 -define rx_ber_timer_16_31_pl=000100010; #022 -define rx_ber_timer_32_39_pl=000100011; #023 -define rx_servo_cntl_pl=000100100; #024 -define rx_fifo_diag_0_15_pl=000100101; #025 -define rx_fifo_diag_16_31_pl=000100110; #026 -define rx_fifo_diag_32_47_pl=000100111; #027 -define rx_eye_width_status_pl=000101000; #028 -define rx_eye_width_cntl_pl=000101001; #029 -define rx_trace_pl=000101011; #02B -define rx_servo_ber_count_pl=000101100; #02C -define rx_eye_opt_stat_pl=000101101; #02D -define rx_dcd_adj_pl=000101110; #02E -define rx_clk_mode_pg=100000000; #100 -define rx_spare_mode_pg=100000001; #101 -define rx_stop_cntl_stat_pg=100000010; #102 -define rx_mode_pg=100000011; #103 -define rx_stop_addr_lsb_pg=100000111; #107 -define rx_stop_mask_lsb_pg=100001000; #108 -define rx_reset_act_pg=100001001; #109 -define rx_id1_pg=100001010; #10A -define rx_id2_pg=100001011; #10B -define rx_id3_pg=100001100; #10C -define rx_dyn_rpr_debug2_pg=100001110; #10E -define rx_sls_mode_pg=100001111; #10F -define rx_training_start_pg=100010000; #110 -define rx_training_status_pg=100010001; #111 -define rx_recal_status_pg=100010010; #112 -define rx_timeout_sel_pg=100010011; #113 -define rx_fifo_mode_pg=100010100; #114 -#define #rx_state_debug_pg=100010101; #115 -#define #rx_state_val_pg=100010110; #116 -define rx_sls_status_pg=100010111; #117 -define rx_fir1_pg=100011010; #11A -define rx_fir2_pg=100011011; #11B -define rx_fir1_mask_pg=100011100; #11C -define rx_fir2_mask_pg=100011101; #11D -define rx_fir1_error_inject_pg=100011110; #11E -define rx_fir2_error_inject_pg=100011111; #11F -define rx_fir_training_pg=100100000; #120 -define rx_fir_training_mask_pg=100100001; #121 -define rx_timeout_sel1_pg=100100010; #122 -define rx_lane_bad_vec_0_15_pg=100100011; #123 -define rx_lane_bad_vec_16_31_pg=100100100; #124 -define rx_lane_disabled_vec_0_15_pg=100100101; #125 -define rx_lane_disabled_vec_16_31_pg=100100110; #126 -define rx_lane_swapped_vec_0_15_pg=100100111; #127 -define rx_lane_swapped_vec_16_31_pg=100101000; #128 -define rx_init_state_pg=100101001; #129 -define rx_wiretest_state_pg=100101010; #12A -define rx_wiretest_laneinfo_pg=100101011; #12B -define rx_wiretest_gcrmsgs_pg=100101100; #12C -define rx_deskew_gcrmsgs_pg=100101101; #12D -define rx_deskew_state_pg=100101110; #12E -define rx_deskew_mode_pg=100101111; #12F -define rx_deskew_status_pg=100110000; #130 -define rx_bad_lane_enc_gcrmsg_pg=100110001; #131 -define rx_static_repair_state_pg=100110010; #132 -define rx_tx_bus_info_pg=100110011; #133 -define rx_sls_lane_enc_gcrmsg_pg=100110100; #134 -define rx_fence_pg=100110101; #135 -define rx_term_pg=100110110; #136 -define rx_timeout_sel2_pg=100110111; #137 -define rx_misc_analog_pg=100111000; #138 -define rx_dyn_rpr_pg=100111001; #139 -define rx_dyn_rpr_gcrmsg_pg=100111010; #13A -define rx_dyn_rpr_err_tallying1_pg=100111011; #13B -define rx_eo_final_l2u_gcrmsgs_pg=100111100; #13C -define rx_gcr_msg_debug_dest_ids_pg=100111101; #13D -define rx_gcr_msg_debug_src_ids_pg=100111110; #13E -define rx_gcr_msg_debug_dest_addr_pg=100111111; #13F -define rx_gcr_msg_debug_write_data_pg=101000000; #140 -define rx_wt_clk_status_pg=101000010; #142 -define rx_wt_config_pg=101000100; #144 -define rx_wiretest_pll_cntl_pg=101000110; #146 -define rx_eo_step_cntl_pg=101000111; #147 -define rx_eo_step_stat_pg=101001000; #148 -define rx_eo_step_fail_pg=101001001; #149 -define rx_amp_val_pg=101001110; #14E -define rx_sls_rcvy_pg=101010001; #151 -define rx_sls_rcvy_gcrmsg_pg=101010010; #152 -define rx_tx_lane_info_gcrmsg_pg=101010011; #153 -define rx_err_tallying_gcrmsg_pg=101010100; #154 -define rx_trace_pg=101010101; #155 -define rx_rdt_cntl_pg=101010110; #156 -define rx_rc_step_cntl_pg=101010111; #157 -define rx_eo_recal_pg=101011000; #158 -define rx_servo_ber_count_pg=101011001; #159 -define rx_func_state_pg=101011010; #15A -define rx_dyn_rpr_debug_pg=101011011; #15B -define rx_dyn_rpr_err_tallying2_pg=101011100; #15C -define rx_result_chk_pg=101011101; #15D -define rx_ber_chk_pg=101011110; #15E -define rx_sls_rcvy_fin_gcrmsg_pg=101011111; #15F -#define #rx_wiretest_pp=101100000; #160 -define rx_mode1_pp=101100001; #161 -define rx_cntl_fast_pp=101100010; #162 -define rx_ei4_cal_cntl_pp=101100011; #163 -define rx_ei4_cal_inc_a_d_pp=101100100; #164 -define rx_ei4_cal_inc_e_h_pp=101100101; #165 -define rx_ei4_cal_dec_a_d_pp=101100110; #166 -define rx_ei4_cal_dec_e_h_pp=101100111; #167 -define rx_ber_cntl_pp=101101010; #16A -define rx_ber_mode_pp=101101011; #16B -define rx_servo_to1_pp=101101100; #16C -define rx_servo_to2_pp=101101101; #16D -define rx_reset_cfg_pp=101110001; #171 -define rx_recal_to1_pp=101110010; #172 -define rx_recal_to2_pp=101110011; #173 -define rx_recal_cntl_pp=101110101; #175 -define rx_mode2_pp=101110110; #176 -define rx_bist_gcrmsg_pp=101110111; #177 -define rx_fir_reset_pb=111110000; #1F0 -define rx_fir_pb=111110001; #1F1 -define rx_fir_mask_pb=111110010; #1F2 -define rx_fir_error_inject_pb=111110011; #1F3 -define rx_fir_msg_pb=111111111; #1FF -define xbus0_gcr_addr=0401103F; -define xbus1_gcr_addr=0401143F; -define xbus2_gcr_addr=04011C3F; -define xbus3_gcr_addr=0401183F; -define rx_grp0=000000; # 0x00 -define rx_grp1=000001; # 0x01 -define rx_grp2=000010; # 0x02 -define rx_grp3=000011; # 0x03 -define tx_grp0=100000; # 0x20 -define tx_grp1=100001; # 0x21 -define tx_grp2=100010; # 0x22 -define tx_grp3=100011; # 0x23 -define lane_na=00000; # 0x00 -define lane_0=00000; -define lane_1=00001; -define lane_2=00010; -define lane_3=00011; -define lane_4=00100; -define lane_5=00101; -define lane_6=00110; -define lane_7=00111; -define lane_8=01000; -define lane_9=01001; -define lane_10=01010; -define lane_11=01011; -define lane_12=01100; -define lane_13=01101; -define lane_14=01110; -define lane_15=01111; -define lane_16=10000; -define lane_17=10001; -define lane_18=10010; -define lane_19=10011; -define lane_20=10100; -define lane_21=10101; -define lane_22=10110; -define lane_23=10111; -define rx_prbs_tap_id_pattern_a=0b0000000000000000; -define rx_prbs_tap_id_pattern_b=0b0010000000000000; -define rx_prbs_tap_id_pattern_c=0b0100000000000000; -define rx_prbs_tap_id_pattern_d=0b0110000000000000; -define rx_prbs_tap_id_pattern_e=0b1000000000000000; -define rx_prbs_tap_id_pattern_f=0b1010000000000000; -define rx_prbs_tap_id_pattern_g=0b1100000000000000; -define rx_prbs_tap_id_pattern_h=0b1110000000000000; -define tx_prbs_tap_id_pattern_a=0b0000000000000000; -define tx_prbs_tap_id_pattern_b=0b0010000000000000; -define tx_prbs_tap_id_pattern_c=0b0100000000000000; -define tx_prbs_tap_id_pattern_d=0b0110000000000000; -define tx_prbs_tap_id_pattern_e=0b1000000000000000; -define tx_prbs_tap_id_pattern_f=0b1010000000000000; diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile deleted file mode 100644 index 084765707..000000000 --- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile +++ /dev/null @@ -1,2525 +0,0 @@ -/#-- $Id: mba_def.initfile,v 1.76 2015/07/16 22:50:59 asaetow Exp $ -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -#-- 1.76|asaetow |07/16/15| Fixed define of def_RDODT_start_udimm and def_RDODT_start_rdimm which currently effects Habanero dual-drop and 128G CDIMM termination. -#-- 1.75|yctschan| 6/09/15| Updated Fast/Slow exit power down settings for MBAPC1Q and MBAREF1Q register -#-- 1.74|yctschan| 4/10/15| SW302059 - turn off row hammer when ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE is 1 -#-- 1.73|yctschan| 4/01/15| SW302059 - turn off row hammer -#-- 1.72|yctschan| 3/24/15| Added support for 2N mode for DDR4 parts for timing parms -#-- 1.71|yctschan| 2/13/15| SW294743 - Update initfile to support RCD parity error reporting -#-- 1.70|yctschan|12/05/14| Updated settings for fast exit power down -#-- 1.69|asaetow | 9/24/14| Force SpareCKE sync. Spare DRAM workaround. -#-- 1.68|jdsloat | 4/04/14| Turned off Power controls for GA1 concerns - Turn back on at a later date -#-- 1.67|tschang | 4/01/14| Adjusted the PUP Avail and SEPD/FEPD time. -#-- 1.66|tschang | 3/28/14| Removed Performance enhancement for rdtag with DMI freq -#-- |baysah | 3/31/14| Added def_margin_pup_fast=12 and def_margin_pup_slow=0 for Yuen with values from Randy/Anuwat -#-- 1.65|tschang | 3/18/14| Fixed typos in the dly7 settings from 0001 to 01111 -#-- 1.64|baysah | 3/05/14| Added MBA Power Ctrol Settings and backed out the refresh avoidance settings until spec benchmark results -#-- 1.63|tschang | 3/03/14| Performance enhancement for rdtag with DMI freq, refresh avoidance and CFG_PUP_AVAIL -#-- 1.62|tschang | 2/14/14| Set Safe mode throttle when ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE is 1 -#-- 1.61|tschang | 2/14/14| Safe mode throttle using sys attributes ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, ATTR_MRW_MEM_THROTTLE_DENOMINATOR -#-- 1.60|tschang | 2/03/14| Removed CDIMM TYPE and replace with custom dimm -#-- 1.59|tschang | 1/30/14| Using VPD values for CKE maps instead of calculated values - ATTR ATTR_VPD_CKE_PRI_MAP, ATTR ATTR_VPD_CKE_PWR_MAP -#-- 1.58|tschang | 1/30/14| HW278587 - if TFAW is 16, set it to 15 otherwise use the TFAW attribute value -#-- 1.57|tschang | 1/22/14| DD2 enhancement - Enable Page Mode for the Read Reorder Queue - MBA_RRQ0Q(57) = 1 -#-- 1.56|baysah | 1/16/14| Changed row hammer primary decrement interval from 64K DRAM clocks (3200 accesses) to 512 DRAM clocks (100K accesses) to hash group. -#-- 1.55|tschang | 1/07/14| ATTR_EFF_DRAM_TFAW attribute used for TFAW timing register. -#-- 1.54|tschang |11/21/13| HW271989 - updated SCOM write to do a full 64 bit write instead of a RMW -#-- 1.53|tschang |11/12/13|EFF to VPD attribute update -#-- 1.52|tschang |11/12/13|wrdata_dly updated with def_WLO parameter and RW_dly updated for LRDIMMS -#-- 1.51|tschang |11/06/13|DD2 row hammer enhancement added with ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE attribute -#-- 1.50|tschang |11/06/13|ATTR_CENTAUR_EC_ENABLE_NM_CHANGE_AFTER_SYNC is 1 for DD2 - HW245888 -#-- 1.49|tschang |10/24/13|added ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT, ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT to throttle settings -#-- 1.48|tschang | 9/30/13|add 10% margin to refresh check interval calculations -#-- 1.47|tschang | 8/15/13| HW259719 - dd2 only fix - ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL to turn on clock gates -#-- 1.46|tschang | 7/17/13|updated refresh interval and refresh check interval calculations -#-- 1.45|tschang | 6/04/13|using ATTR_EFF_DRAM_RRD, etc timing parms for settings -#-- setting RD ODT according to Menlo's equation -#-- 1.44|tschang | 5/06/13|added 2n_mode to timing parms equations -#-- 1.43|tschang | 5/01/13|def_refresh_interval optimized to avoid divide by 0 condition -#-- 1.42|tschang | 5/01/13|cfg_min_domain_reduction disabled as requested by performance team -#-- 1.41|tschang | 4/24/13|fixed typos for a couple type cfgs -#-- 1.40|tschang | 4/24/13|fixed 1d type cfg -#-- 1.39|tschang | 4/17/13|commented out maxall_min0 power controls until decision has been made for default value -#-- 1.38|tschang | 4/08/13|set cfg_min_domain_reduction_enable to 1 and maxall_min0 power controls -#-- 1.37|tschang | 4/04/13|ACT signal in CCS idle pattern set to 1 for DDR4 and 0 for non DDR4 -#-- 1.36|tschang | 4/04/13|MBA_FARB2Q fixed rank master typo for IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C cfg -#-- 1.35|tschang | 3/27/13|set trfc and refresh interval according to refresh equation -#-- update wrdata_dly parm with ATTR_EFF_DRAM_AL attribute -#-- 1.34|tschang | 3/26/13|wrdata_dly parm updated to detect LRDIMMs -#-- 1.33|tschang | 3/12/13|RWDM_dly margin increased by 1 to match other RW dlys - HW243893 -#-- 1.32|tschang | 3/12/13|Def_margin_rdtag set it to 4 - increased by 2 -#-- 1.31|tschang | 3/11/13|Defined new def_margin_rdtag and set it to 2 to increase it from figtree values -#-- 1.30|tschang | 3/05/13|Set def_margin2 to 0 to decrease timing parmeters for performance and added def_margin1 for RW parms -#-- 1.29|tschang | 2/27/13|Set def_margin to 1 to decrease timing parmeters for performance -#-- 1.28|tschang | 2/11/13|Set WR ODT start to 1 and end to 5 (HW239026) -#-- Updated cfg_nm_per_slot_enabled for CDIMM cfgs -#-- 1.27|tschang | 1/28/13|Set mba_cal3 register to max timeout values for periodic cal -#-- 1.26|tschang | 1/23/13|Write Latency equation changed for mba_tmr0 register - define def_WL = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 1 - 7) -#-- 1.25|tschang | 1/17/13|added def_margin constant to increment mba tmr0 register by the value of def_margin - current setting of margin is 2 -#-- 1.24|tschang | 1/04/13|added code to detect and overrun condition with periodic cal and choose a larger timebase when that happens -#-- |fixed periodic cal type to properly choose periodic cal -#-- 1.23|tschang |12/18/12|changed SYS.ATTR_IS_SIMULATION ==0 to CENTAUR.ATTR_MSS_FREQ ==1400 to cause a false coniditon place holder -#-- changed rdtag to be 36 for all configurations -#-- 1.22|menlowuu|12/04/12|changed CCS_Mode register to set RAS, CAS, WE to high on idles -#-- 1.21|tschang |11/14/12|added throttle control for n/m -#-- 1.20|tschang |11/13/12|updated file for new IBM_TYPE defnitions and added MCBIST ADDR and ADDR mapping fro SCHMOO -#-- 1.16|tschang |09/27/12| added partial good support for the SCOM write using ATTR_FUNCTIONAL -#-- 1.15|tschang |09/18/12|update periodic cal registers bit register definitions -#-- 1.14|tschang |09/11/12|update periodic cal registers -#-- 1.13|tschang |09/11/12|backout periodic cal registers settings change -#-- 1.12|tschang |09/10/12|added periodic cal registers settings -#-- 1.11|tschang |08/20/12|added mba mcbist setup values for simple write and read test -#-- 1.10|menlowuu|08/01/12|add/fixed comments in refresh section, missed a line -#-- 1.10|menlowuu|08/01/12|add/fixed comments in refresh section, missed a line -#-- 1.9 |menlowuu|07/30/12|add/fixed comments in refresh section -#-- 1.8 |tschang |07/28/12|set refresh interval value and refresh check interval values -#-- 1.4 |tschang |06/28/12|clean up define syntax and ()'s -#-- 1.3 |tschang |05/08/12|moved refresh settings from mss_draminit_mc to this init file -#-- 1.2 |bellows |05/03/12|Updates for working version -#-- 1.1 |bellows |04/04/12|Created File In Proper Directory -#-- 0.03|bellows |04/04/12|Fixed up this comment -#-- 0.02|bellows |03/27/12|Removed accesses to MBA23 -#-- 0.01|retter |01/13/12|Initial version -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- - -#--Master list of variables that can be used in this file is at: -#--<Attribute Definition Location> - -SyntaxVersion = 1 - -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Defines -#-- -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- - -define def_equal_test = (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT32_2); - -# EFF_DIMM_RANKS_CONFIGED [a][b] - a=0, def_mba01 a = 1, def_mba23 -# - b=0, socket0 (mrank 0:3) b = 1, socket1 (mrank 4:7)) -# EFF_NUM_RANKS_PER_DIMM = total number of master and slave ranks per socket -# -# ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] u8[2][2] 0x80 -# ATTR_EFF_MBA_POS (0=01, 1=2/3) -# -# ATTR_EFF_IBM_TYPE [][] 2x2 array -# OLD -# UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_2A = 4, TYPE_2B = 5, TYPE_2C = 6, TYPE_3A = 7, TYPE_3B = 8, TYPE_3C = 9, TYPE_4A = 10, TYPE_4B = 11, TYPE_4C = 12, -# TYPE_5A = 13, TYPE_5B = 14, TYPE_5C = 15, TYPE_5D = 16, TYPE_6A = 17, TYPE_6B = 18, TYPE_6C = 19, TYPE_7A = 20, TYPE_7B = 21, TYPE_7C = 22, TYPE_8A = 23, TYPE_8B = 24, TYPE_8C = 25 -# NEW -## UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_1D = 4, TYPE_2A = 5, TYPE_2B = 6, TYPE_2C = 7, TYPE_3A = 8, TYPE_3B = 9, TYPE_3C = 10, TYPE_4A = 11, TYPE_4B = 12, TYPE_4C = 13, -# TYPE_5A = 14, TYPE_5B = 15, TYPE_5C = 16, TYPE_5D = 17, TYPE_6A = 18, TYPE_6B = 19, TYPE_6C = 20, TYPE_7A = 21, TYPE_7B = 22, TYPE_7C = 23, TYPE_8A = 24, TYPE_8B = 25, TYPE_8C = 26</enum> -# -# ATTR_EFF_NUM_DROPS_PER_PORT -# EMPTY = 0, SINGLE = 1, DUAL = 2 -# -# ATTR_EFF_DIMM_TYPE -# CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3 -# -# ATTR_EFF_DRAM_DLL_PPD -# SLOWEXIT = 0, FASTEXIT = 1 -# -# ATTR_EFF_DRAM_GEN -# EMPTY = 0, DDR3 = 1, DDR4 = 2 -# -# CENTAUR.ATTR_MSS_FREQ = frequency -# not an mba attribute will need hierachy -# -# ATTR_CHIP_UNIT_POS -# 0 = MBA0 (mba01), 1 = MBA1 (mba23) -# -# <id>ATTR_EFF_MEMCAL_INTERVAL</id> -# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> -# <description>Specifies the memcal interval in clocks.</description> -# <valueType>uint32</valueType> -# <enum>DISABLE = 0</enum> - -# <id>ATTR_EFF_ZQCAL_INTERVAL</id> -# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType> -# <description>Specifies the zqcal interval in clocks.</description> -# <valueType>uint32</valueType> -# <enum>DISABLE = 0</enum> - - - -# mba tmr0 register timings are added to the value below -define def_margin1 = (1); -define def_margin2 = (0); -define def_margin_pup_fast = (0); -define def_margin_pup_slow = (0); -define def_margin_rdtag = (4); - - -define def_no_spare = (SYS.ATTR_IS_SIMULATION==1) ; -define def_has_spare = (SYS.ATTR_IS_SIMULATION==0) ; - -define CENTAUR = TGT1; - -# MBA0 (mba01) -define def_1a_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 1 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); # DDR3/4 are same -define def_1a_2socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 1 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)));# || (def_1b_cdimm)); # DDR3/4 are same -#define def_1a_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 1 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as 1a_1socket RDIMM - -define def_1b_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 2 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_1b_2socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 2 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_1c_cdimm)); -#define def_1b_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 2 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1A 2 socket RDIMM cfg for DDR3/4 - -## 1C 1 and 2 sockets not supported -define def_1c_1socket_nodt = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_1d_1socket); -define def_1c_2socket_nodt = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_1d_2socket); -define def_1c_1socket_odt = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_1c_2socket_odt = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_1c_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 3 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 3 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1B 2 socket RDIMM cfg for DDR3/4 - -## Current they is no 1D IBM type in the attribute -define def_1d_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_1d_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 4 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); - -## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs -define def_2a_1socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_cdimm)); -define def_2a_2socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_2c_cdimm) || (def_3a_cdimm)); -define def_2a_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket cfg -define def_2a_1socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_ddr4_cdimm)); -define def_2a_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3a_ddr4_cdimm)); -define def_2a_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 5 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket DDR4 cfg - -define def_2b_1socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2b_cdimm)); -define def_2b_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_2b_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket cfg -define def_2b_1socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2b_ddr4_cdimm)); -define def_2b_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3b_ddr4_cdimm)); -define def_2b_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 6 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket DDR4 cfg - -# centuar spec only has DDR4 for 2C cfg -define def_2c_1socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_cdimm)); -define def_2c_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_2c_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket cfg -define def_2c_1socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_2a_ddr4_cdimm)); -define def_2c_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_3c_ddr4_cdimm)); -define def_2c_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 7 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket DDR4 cfg - -define def_3a_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_3a_2socket = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_4a_cdimm)); -#define def_3a_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 2 socket cfg -define def_3a_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1))) && (ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg -define def_3a_1socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_3a_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_4a_ddr4_cdimm)); -define def_3a_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 8 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1))) && (ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg - -define def_3b_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_3b_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_3b_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg -define def_3b_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 9 )) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg ?? - -define def_3c_1socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_3c_2socket_ddr4 = (((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_4c_ddr4_cdimm)); -define def_3c_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg -define def_3c_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 10)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 10))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg - -define def_4a_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 11)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 11))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket cfg -define def_4a_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 11)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 11))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket DDR4 cfg - -define def_4b_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 12)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 12))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3B 2 socket DDR4 cfg - -define def_4c_ddr4_cdimm = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 13)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 13))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3C 2 socket DDR4 cfg - -define def_5b_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 15)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 15))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_5b_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 15)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 15))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); - -define def_5c_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 16)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 16))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_5c_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 16)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 16))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); - -define def_5d_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 17)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 17))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_5d_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 17)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 17))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); - -define def_7a_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_7a_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_7a_1socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_7a_2socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 21)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 21))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); - -define def_7b_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_7b_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_7b_1socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_7b_2socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 22)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 22))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); - -define def_7c_1socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 23)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 23))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_7c_2socket = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 23)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 23))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_7c_1socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 23)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 23))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_7c_2socket_ddr4 = ((((ATTR_CHIP_UNIT_POS == 1 ) && (ATTR_EFF_IBM_TYPE[1][0] == 23)) || ((ATTR_CHIP_UNIT_POS == 0 ) && (ATTR_EFF_IBM_TYPE[0][0] == 23))) && (ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (ATTR_EFF_DIMM_TYPE == 3)); - - - -define def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C = ((def_1a_1socket )||(def_1a_2socket )||(def_1b_1socket )||(def_1b_2socket )||(def_1c_cdimm )||(def_1c_1socket_nodt )||(def_1c_2socket_nodt )||(def_5b_1socket )||(def_5b_2socket )||(def_5c_1socket )||(def_5c_2socket)); -define def_IS7a_C4a_C3a = ((def_3a_1socket )||(def_3a_2socket )||(def_4a_cdimm )||(def_7a_1socket )||(def_7a_2socket)); -define def_IS3b_IS7b = ((def_3b_1socket )||(def_3b_2socket )||(def_4b_ddr4_cdimm )||(def_7b_1socket )||(def_7b_2socket)); -define def_IS7C = ((def_7c_1socket )||(def_7c_2socket)); -define def_C3b = ((def_2a_1socket )||(def_2a_2socket )||(def_3a_cdimm )||(def_2b_1socket )||(def_2b_2socket )||(def_3b_cdimm)); -define def_C3c = ((def_2c_1socket )||(def_2c_2socket )||(def_3c_cdimm)); -define def_C3c_C4C_ddr4 = ((def_2b_1socket_ddr4)||(def_2b_2socket_ddr4)||(def_3b_ddr4_cdimm )||(def_2c_1socket_ddr4)||(def_2c_2socket_ddr4)||(def_3c_ddr4_cdimm )||(def_3c_1socket_ddr4)||(def_3c_2socket_ddr4)||(def_4c_ddr4_cdimm )||(def_7b_1socket_ddr4)||(def_7b_2socket_ddr4)||(def_7c_1socket_ddr4)||(def_7c_2socket_ddr4)); -define def_C4A_ddr4 = ((def_2a_1socket_ddr4)||(def_2a_2socket_ddr4)||(def_3a_ddr4_cdimm )||(def_7a_1socket_ddr4)||(def_7a_2socket_ddr4)||(def_3a_1socket_ddr4)||(def_3a_2socket_ddr4)||(def_4a_ddr4_cdimm)); -define def_IS5D = ((def_5d_1socket )||(def_5d_2socket)); - -# ODT Mappings -define def_odt_mapping_1a = (def_1a_1socket); -define def_odt_mapping_1b1dimm = (def_1b_1socket ||def_3a_1socket ||def_3a_1socket_ddr4 ||def_3b_1socket ||def_3c_1socket_ddr4); -define def_odt_mapping_1b2dimm = (def_3c_2socket_ddr4 ||def_1b_2socket ||def_3a_2socket ||def_3a_2socket_ddr4 ||def_3b_2socket); -#define def_odt_mapping_1bcdimm = (def_1a_2socket ||def_1b_cdimm ||def_3a_cdimm ||def_3a_ddr4_cdimm ||def_3b_cdimm ||def_3b_ddr4_cdimm ||def_3c_cdimm ||def_3c_ddr4_cdimm); -define def_odt_mapping_1bcdimm = (def_1a_2socket ||def_3a_cdimm ||def_3a_ddr4_cdimm ||def_3b_cdimm ||def_3b_ddr4_cdimm ||def_3c_cdimm ||def_3c_ddr4_cdimm); -define def_odt_mapping_1c2dimm = (def_1c_2socket_odt); -define def_odt_mapping_1c1dimm = (def_1c_1socket_odt); -define def_odt_mapping_1ccdimm = (def_1c_cdimm ||def_4a_cdimm ||def_4a_ddr4_cdimm ||def_4b_ddr4_cdimm ||def_4c_ddr4_cdimm); -define def_odt_mapping_1dx82dimm = (def_1d_2socket); -define def_odt_mapping_1dx4 = (def_1d_1socket); -define def_odt_mapping_2abc = (def_2a_1socket ||def_2a_2socket ||def_2a_1socket_ddr4 ||def_2a_2socket_ddr4 ||def_2a_cdimm ||def_2a_ddr4_cdimm ||def_2b_1socket ||def_2b_2socket ||def_2b_1socket_ddr4 ||def_2b_2socket_ddr4 ||def_2b_cdimm ||def_2b_ddr4_cdimm ||def_2c_1socket ||def_2c_2socket ||def_2c_1socket_ddr4 ||def_2c_2socket_ddr4 ||def_2c_ddr4_cdimm); -define def_odt_mapping_56781lrdm = (def_5b_1socket ||def_5c_1socket ||def_7a_1socket ||def_7a_1socket_ddr4 ||def_7b_1socket ||def_7b_1socket_ddr4 ||def_7c_1socket ||def_7c_1socket_ddr4); -define def_odt_mapping_56782lrdm = (def_5b_2socket ||def_5c_2socket ||def_7a_2socket ||def_7a_2socket_ddr4 ||def_7b_2socket ||def_7b_2socket_ddr4 ||def_7c_2socket ||def_7c_2socket_ddr4); -define def_odt_mapping_5d1dimm = (def_5d_1socket); -define def_odt_mapping_5d2dimm = (def_5d_2socket); - - -#gdial std_size ( MBA_SRQ.mba_tmr1q_cfg_tfaw, MBA_SRQ.pc.MBAREF0Q_cfg_trfc, MBA_SRQ.pc.MBAREF0Q_cfg_refr_tsv_stack, MBA_SRQ.pc.MBARPC0Q_cfg_pup_pdn, MBA_SRQ.pc.MBARPC0Q_cfg_pdn_pup, MBA_SRQ.pc.MBARPC0Q_cfg_pup_avail, MBA_SRQ.mba_tmr0q_RRSMSR_dly , MBA_SRQ.mba_tmr0q_RRSMDR_dly, MBA_SRQ.mba_tmr0q_WWSMSR_dly, MBA_SRQ.mba_tmr0q_WWSMDR_dly , MBA_SRQ.MBA_TMR0Q_Trrd, MBA_SRQ.srqdbg.cfg_std_size_id)= -define def_1066_2gb = ((CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1066_4gb = ((CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1066_8gb = ((CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); - -define def_1066_2gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1066_4gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1066_8gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); - -define def_1333_2gb = ((CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1333_4gb = ((CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1333_8gb = ((CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1600_2gb = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1600_4gb = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1600_8gb = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1866_2gb = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1866_4gb = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1866_8gb = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1333_2gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1333_4gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1333_8gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1600_2gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1600_4gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1600_8gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1866_2gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1866_4gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1866_8gb_fast_exit_pd = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 1)); -define def_1600_2gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_1600_4gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_1600_8gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_1866_2gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_1866_4gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_1866_8gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_2133_2gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_2133_4gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_2133_8gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_2400_2gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_2400_4gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_2400_8gb_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 0 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_1600_2gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_1600_4gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_1600_8gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_1866_2gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_1866_4gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_1866_8gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_2133_2gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_2133_4gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_2133_8gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_2400_2gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_DENSITY == 2 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_2400_4gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_DENSITY == 4 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); -define def_2400_8gb_fast_exit_pd_ddr4 = ((CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_DENSITY == 8 ) && ( ATTR_EFF_DRAM_DLL_PPD == 1 ) && ( ATTR_EFF_DRAM_GEN == 2)); - -#gdial std_timming ( mba_tmr0q_RRDM_dly, mba_tmr0q_RWSMSR_dly, mba_tmr0q_RWSMDR_dly, mba_tmr0q_RWDM_dly, mba_tmr0q_WRSMSR_dly, mba_tmr0q_WRSMDR_dly, mba_tmr0q_WRDM_dly, mba_tmr0q_WWDM_dly, mba_tmr0q_RROP_dly, mba_tmr0q_WWOP_dly, mba_tmr1q_RRSBG_dly, MBA_TMR1Q_WRSBG_dly, mba_tmr1q_cfg_trap, mba_tmr1q_cfg_twap, mba_dsm0q_cfg_rdtag_dly, mba_dsm0q_cfg_wrdata_dly, mba_dsm0q_cfg_wrdone_dly, mba_dsm0q_CFG_RODT_start_dly, mba_dsm0q_CFG_RODT_end_dly, mba_dsm0q_CFG_RODT_BC4_END_DLY, mba_dsm0q_CFG_WODT_start_dly, mba_dsm0q_CFG_WODT_end_dly, mba_dsm0q_CFG_WODT_BC4_END_DLY, srqdbg.cfg_std_timing_id)= - - - - - - -define def_ddr3_1066_6_6_6 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1066_6_6_6R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1066_6_6_6_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1066_6_6_6_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1066_6_6_6_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 6 ) && ( ATTR_EFF_DRAM_TRCD == 6 ) && ( ATTR_EFF_DRAM_TRP == 6 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1066_6_6_6_group = ((def_ddr3_1066_6_6_6 )||( def_ddr3_1066_6_6_6_2N )||( def_ddr3_1066_6_6_6R )||( def_ddr3_1066_6_6_6_LR )||( def_ddr3_1066_6_6_6_L2)); -define def_ddr3_1066_7_7_7 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1066_7_7_7R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1066_7_7_7_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1066_7_7_7_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1066_7_7_7_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 7 ) && ( ATTR_EFF_DRAM_TRCD == 7 ) && ( ATTR_EFF_DRAM_TRP == 7 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1066_7_7_7_group = ((def_ddr3_1066_7_7_7 )||( def_ddr3_1066_7_7_7_2N )||( def_ddr3_1066_7_7_7R )||( def_ddr3_1066_7_7_7_LR )||( def_ddr3_1066_7_7_7_L2)); -define def_ddr3_1066_8_8_8 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1066_8_8_8R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1066_8_8_8_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1066_8_8_8_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1066_8_8_8_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1066 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1066_8_8_8_group = ((def_ddr3_1066_8_8_8 )||( def_ddr3_1066_8_8_8_2N )||( def_ddr3_1066_8_8_8R )||( def_ddr3_1066_8_8_8_LR )||( def_ddr3_1066_8_8_8_L2)); -define def_ddr3_1333_8_8_8 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1333_8_8_8R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1333_8_8_8_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1333_8_8_8_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1333_8_8_8_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 8 ) && ( ATTR_EFF_DRAM_TRCD == 8 ) && ( ATTR_EFF_DRAM_TRP == 8 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1333_9_9_9 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1333_9_9_9R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1333_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1333_9_9_9_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1333_9_9_9_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1333 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1600_10_10_10 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1600_10_10_10R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1600_10_10_10_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1600_10_10_10_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1600_10_10_10_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1600_11_11_11 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1600_11_11_11R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1600_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1600_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1600_9_9_9 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1600_9_9_9R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1600_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1600_9_9_9_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1600_9_9_9_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1866_11_11_11 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1866_11_11_11R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1866_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1866_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1866_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1866_12_12_12 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1866_12_12_12R = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr3_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr3_1866_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr3_1866_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 1 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); - -# DDR4 1600 -define def_ddr4_1600_9_9_9 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); -define def_ddr4_1600_9_9_9R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1600_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1600_9_9_9_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1600_9_9_9_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1600_10_10_10 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); -define def_ddr4_1600_10_10_10R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1600_10_10_10_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1600_10_10_10_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1600_10_10_10_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1600_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); -define def_ddr4_1600_11_11_11R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1600_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1600_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); - -define def_ddr4_1600_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); -define def_ddr4_1600_12_12_12R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1600_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1600_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1600_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); - -# DDR4 1866 -define def_ddr4_1866_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); -define def_ddr4_1866_11_11_11R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1866_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1866_11_11_11_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1866_11_11_11_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1866_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); -define def_ddr4_1866_12_12_12R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1866_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1866_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); - -define def_ddr4_1866_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); -define def_ddr4_1866_13_13_13R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -define def_ddr4_1866_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -define def_ddr4_1866_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -define def_ddr4_1866_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); - -# DDR4 2133 12 -13 - not supported -#define def_ddr4_2133_12_12_12 = 0; -#define def_ddr4_2133_12_12_12R = 0; -#define def_ddr4_2133_12_12_12_2N = 0; -#define def_ddr4_2133_12_12_12_L2 = 0; -#define def_ddr4_2133_12_12_12_LR = 0; -#define def_ddr4_2133_13_13_13 = 0; -#define def_ddr4_2133_13_13_13R = 0; -#define def_ddr4_2133_13_13_13_2N = 0; -#define def_ddr4_2133_13_13_13_L2 = 0; -#define def_ddr4_2133_13_13_13_LR = 0; -define def_ddr4_2133_12_12_12 = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2133_12_12_12R = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2133_12_12_12_2N = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2133_12_12_12_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2133_12_12_12_LR = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2133_13_13_13 = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2133_13_13_13R = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2133_13_13_13_2N = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2133_13_13_13_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2133_13_13_13_LR = (CENTAUR.ATTR_MSS_FREQ == 1400); - -#define def_ddr4_2133_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); -#define def_ddr4_2133_12_12_12R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -#define def_ddr4_2133_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2133_12_12_12_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -#define def_ddr4_2133_12_12_12_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -#define def_ddr4_2133_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); -#define def_ddr4_2133_13_13_13R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -#define def_ddr4_2133_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2133_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -#define def_ddr4_2133_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); - -# DDR4 2400 13-14 not supported -#define def_ddr4_2400_13_13_13 = 0; -#define def_ddr4_2400_13_13_13R = 0; -#define def_ddr4_2400_13_13_13_2N = 0; -#define def_ddr4_2400_13_13_13_L2 = 0; -#define def_ddr4_2400_13_13_13_LR = 0; -#define def_ddr4_2400_14_14_14 = 0; -#define def_ddr4_2400_14_14_14R = 0; -#define def_ddr4_2400_14_14_14_2N = 0; -#define def_ddr4_2400_14_14_14_L2 = 0; -#define def_ddr4_2400_14_14_14_LR = 0; -define def_ddr4_2400_13_13_13 = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2400_13_13_13R = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2400_13_13_13_2N = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2400_13_13_13_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2400_13_13_13_LR = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2400_14_14_14 = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2400_14_14_14R = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2400_14_14_14_2N = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2400_14_14_14_L2 = (CENTAUR.ATTR_MSS_FREQ == 1400); -define def_ddr4_2400_14_14_14_LR = (CENTAUR.ATTR_MSS_FREQ == 1400); - -#define def_ddr4_2400_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); -#define def_ddr4_2400_13_13_13R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -#define def_ddr4_2400_13_13_13_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2400_13_13_13_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -#define def_ddr4_2400_13_13_13_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); -#define def_ddr4_2400_14_14_14 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ((( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)) || (( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 1 )))); -#define def_ddr4_2400_14_14_14R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -#define def_ddr4_2400_14_14_14_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2400_14_14_14_L2 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 3)); -#define def_ddr4_2400_14_14_14_LR = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 3)); - -#define def_ddr4_1600_10_10_10 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr3_1600_10_10_10R = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 1 )); -#define def_ddr4_1600_10_10_10_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 10 ) && ( ATTR_EFF_DRAM_TRCD == 10 ) && ( ATTR_EFF_DRAM_TRP == 10 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1600_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1600_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1600_9_9_9 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1600_9_9_9_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1600 ) && ( ATTR_EFF_DRAM_CL == 9 ) && ( ATTR_EFF_DRAM_TRCD == 9 ) && ( ATTR_EFF_DRAM_TRP == 9 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1866_11_11_11 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1866_11_11_11_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 11 ) && ( ATTR_EFF_DRAM_TRCD == 11 ) && ( ATTR_EFF_DRAM_TRP == 11 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1866_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_1866_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 1866 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2133_12_12_12 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2133_12_12_12_2N = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 12 ) && ( ATTR_EFF_DRAM_TRCD == 12 ) && ( ATTR_EFF_DRAM_TRP == 12 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 1 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2133_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2133 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2400_13_13_13 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 13 ) && ( ATTR_EFF_DRAM_TRCD == 13 ) && ( ATTR_EFF_DRAM_TRP == 13 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); -#define def_ddr4_2400_14_14_14 = ((ATTR_EFF_DRAM_GEN == 2 ) && ( CENTAUR.ATTR_MSS_FREQ == 2400 ) && ( ATTR_EFF_DRAM_CL == 14 ) && ( ATTR_EFF_DRAM_TRCD == 14 ) && ( ATTR_EFF_DRAM_TRP == 14 ) && ( ATTR_VPD_DRAM_2N_MODE_ENABLED == 0 ) && (ATTR_EFF_DIMM_TYPE == 2)); - -# new 7,8,9 - -define def_mba_tmr0q_RW_dlys7 = ((def_ddr3_1066_6_6_6 )||( def_ddr3_1066_6_6_6_2N )||( def_ddr3_1066_6_6_6R )||( def_ddr4_1600_9_9_9 )||(def_ddr4_1600_9_9_9_2N )||(def_ddr4_1600_9_9_9R)); -define def_mba_tmr0q_RW_dlys8 = ((def_ddr3_1066_7_7_7 )||( def_ddr3_1066_7_7_7_2N )||( def_ddr3_1066_7_7_7R )||( def_ddr3_1333_8_8_8 )||(def_ddr3_1600_9_9_9 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1600_9_9_9_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1600_9_9_9R )||(def_ddr4_1600_10_10_10 )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1600_10_10_10R)); -define def_mba_tmr0q_RW_dlys9 = ((def_ddr3_1066_8_8_8 )||( def_ddr3_1066_8_8_8_2N )||( def_ddr3_1066_8_8_8R )||( def_ddr3_1333_9_9_9 )||(def_ddr3_1600_10_10_10 )||(def_ddr3_1333_9_9_9_2N )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1333_9_9_9R )||(def_ddr3_1600_10_10_10R )||(def_ddr4_1600_11_11_11 )||(def_ddr4_1866_11_11_11 )||(def_ddr4_2133_12_12_12 )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_1600_11_11_11R )||(def_ddr4_1866_11_11_11R )||(def_ddr4_2133_12_12_12R )); -define def_mba_tmr0q_RW_dlys10 = ((def_ddr4_1600_12_12_12)||(def_ddr4_1600_12_12_12_2N)||(def_ddr4_1600_12_12_12R)||(def_ddr4_2133_13_13_13R)||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_2133_13_13_13 )||(def_ddr3_1600_11_11_11 )||(def_ddr3_1866_11_11_11 )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1600_11_11_11R )||(def_ddr3_1866_11_11_11R )||(def_ddr4_1866_12_12_12 )||(def_ddr4_2400_13_13_13 )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_1866_12_12_12R )||(def_ddr4_2400_13_13_13R)); -define def_mba_tmr0q_RW_dlys11 = ((def_ddr4_1866_13_13_13)||(def_ddr4_1866_13_13_13_2N)||(def_ddr4_1866_13_13_13R)||(def_ddr3_1066_6_6_6_L2)||( def_ddr3_1066_6_6_6_LR )||(def_ddr3_1866_12_12_12 )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1866_12_12_12R )||(def_ddr4_2400_14_14_14 )||(def_ddr4_2400_14_14_14_2N )||(def_ddr4_2400_14_14_14R )||(def_ddr4_1600_9_9_9_LR )||(def_ddr4_1600_9_9_9_L2)); -define def_mba_tmr0q_RW_dlys12 = (( def_ddr3_1066_7_7_7_L2)||( def_ddr3_1066_7_7_7_LR )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1600_9_9_9_LR )||(def_ddr3_1333_8_8_8_L2 )||(def_ddr3_1600_9_9_9_L2 )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1600_10_10_10_L2)); -# change RW_dly for LRDIMMs -define def_mba_tmr0q_RW_dlys13 = (( def_ddr3_1066_8_8_8_L2)||( def_ddr3_1066_8_8_8_LR )||(def_ddr3_1333_9_9_9_L2 )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_1600_11_11_11_L2 )||(def_ddr4_1866_11_11_11_L2 )||(def_ddr4_2133_12_12_12_L2 )); -define def_mba_tmr0q_RW_dlys14 = ((def_ddr4_1600_12_12_12_LR)||(def_ddr4_1600_12_12_12_L2)||(def_ddr4_2133_13_13_13_L2)||(def_ddr4_2133_13_13_13_LR )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1600_11_11_11_L2 )||(def_ddr3_1866_12_12_12_L2 )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_1866_12_12_12_L2 )||(def_ddr4_2400_13_13_13_L2)||(def_ddr3_1333_9_9_9_LR )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1866_11_11_11_LR )); -define def_mba_tmr0q_RW_dlys15 = ((def_ddr4_1866_13_13_13_LR)||(def_ddr4_1866_13_13_13_L2)||(def_ddr4_2400_14_14_14_LR )||(def_ddr4_2400_14_14_14_L2)); - -#new 19,20,21 - -define def_mba_tmr0q_WRSM_dlys19 = (def_ddr3_1066_6_6_6_group); -define def_mba_tmr0q_WRSM_dlys20 = (def_ddr3_1066_7_7_7_group); -define def_mba_tmr0q_WRSM_dlys21 = (def_ddr3_1066_8_8_8_group); - -define def_mba_tmr0q_WRSM_dlys23 = ((def_ddr3_1333_8_8_8 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1333_8_8_8_L2)); -define def_mba_tmr0q_WRSM_dlys24 = ((def_ddr3_1333_9_9_9 )||(def_ddr3_1333_9_9_9_2N )||(def_ddr3_1333_9_9_9R )||(def_ddr3_1333_9_9_9_LR )||(def_ddr3_1333_9_9_9_L2 )); -define def_mba_tmr0q_WRSM_dlys25 = ((def_ddr4_1600_9_9_9 )||(def_ddr4_1600_9_9_9_2N )||(def_ddr4_1600_9_9_9R )||(def_ddr4_1600_9_9_9_LR )||(def_ddr4_1600_9_9_9_L2 )); -define def_mba_tmr0q_WRSM_dlys26 = ((def_ddr3_1600_9_9_9 )||(def_ddr3_1600_9_9_9_2N )||(def_ddr3_1600_9_9_9R )||(def_ddr3_1600_9_9_9_LR )||(def_ddr3_1600_9_9_9_L2 )||(def_ddr4_1600_10_10_10 )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1600_10_10_10R )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1600_10_10_10_L2 )); -define def_mba_tmr0q_WRSM_dlys27 = ((def_ddr3_1600_10_10_10 )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1600_10_10_10R )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr4_1600_11_11_11 )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1600_11_11_11R )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1600_11_11_11_L2 )); -define def_mba_tmr0q_WRSM_dlys28 = (def_ddr4_1600_12_12_12 ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 || (def_ddr3_1600_11_11_11 )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1600_11_11_11R )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1600_11_11_11_L2 )||(def_ddr4_1866_11_11_11 )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_1866_11_11_11R )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_1866_11_11_11_L2 )); -define def_mba_tmr0q_WRSM_dlys29 = ((def_ddr4_1866_12_12_12 )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_1866_12_12_12R )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_1866_12_12_12_L2 )); -define def_mba_tmr0q_WRSM_dlys30 = ((def_ddr4_2133_12_12_12 )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_2133_12_12_12R )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_2133_12_12_12_L2 )); -define def_mba_tmr0q_WRSM_dlys31 = ((def_ddr3_1866_11_11_11 )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1866_11_11_11R )||(def_ddr3_1866_11_11_11_LR )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_2133_13_13_13 )||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_2133_13_13_13R )||(def_ddr4_2133_13_13_13_LR )||(def_ddr4_2133_13_13_13_L2 )); -define def_mba_tmr0q_WRSM_dlys32 = (def_ddr4_1866_13_13_13 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2 || (def_ddr3_1866_12_12_12 )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1866_12_12_12R )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1866_12_12_12_L2 )||(def_ddr4_2400_13_13_13 )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_2400_13_13_13R )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_2400_13_13_13_L2 )); -define def_mba_tmr0q_WRSM_dlys33 = ((def_ddr4_2400_14_14_14 )||(def_ddr4_2400_14_14_14_2N )||(def_ddr4_2400_14_14_14R )||(def_ddr4_2400_14_14_14_LR )||(def_ddr4_2400_14_14_14_L2 )); - -#new 7,6,5 -define def_mba_tmr0q_WRDM_dlys4 = (def_ddr4_1600_12_12_12 ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 || (def_ddr3_1600_11_11_11 )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1600_11_11_11R )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1600_11_11_11_L2)); -define def_mba_tmr0q_WRDM_dlys5 = (def_ddr4_1866_13_13_13 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2 || (def_ddr3_1066_8_8_8_group )||(def_ddr3_1333_9_9_9 )||(def_ddr3_1600_10_10_10 )||(def_ddr3_1866_12_12_12 )||(def_ddr3_1333_9_9_9_2N )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1333_9_9_9R )||(def_ddr3_1600_10_10_10R )||(def_ddr3_1866_12_12_12R )||(def_ddr3_1333_9_9_9_LR )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1333_9_9_9_L2 )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr3_1866_12_12_12_L2 )||(def_ddr4_1600_11_11_11 )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1600_11_11_11R )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1600_11_11_11_L2)); -define def_mba_tmr0q_WRDM_dlys6 = ((def_ddr3_1066_7_7_7_group )||(def_ddr3_1333_8_8_8 )||(def_ddr3_1600_9_9_9 )||(def_ddr3_1866_11_11_11 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1600_9_9_9_2N )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1600_9_9_9R )||(def_ddr3_1866_11_11_11R )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1600_9_9_9_LR )||(def_ddr3_1866_11_11_11_LR )||(def_ddr3_1333_8_8_8_L2 )||(def_ddr3_1600_9_9_9_L2 )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_1600_10_10_10 )||(def_ddr4_1866_12_12_12 )||(def_ddr4_2133_13_13_13 )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_1600_10_10_10R )||(def_ddr4_1866_12_12_12R )||(def_ddr4_2133_13_13_13R )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_2133_13_13_13_LR )||(def_ddr4_1600_10_10_10_L2 )||(def_ddr4_1866_12_12_12_L2 )||(def_ddr4_2133_13_13_13_L2)); -define def_mba_tmr0q_WRDM_dlys7 = ((def_ddr3_1066_6_6_6_group )||(def_ddr4_1600_9_9_9 )||(def_ddr4_1866_11_11_11 )||(def_ddr4_2133_12_12_12 )||(def_ddr4_2400_14_14_14 )||(def_ddr4_1600_9_9_9_2N )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_2400_14_14_14_2N )||(def_ddr4_1600_9_9_9R )||(def_ddr4_1866_11_11_11R )||(def_ddr4_2133_12_12_12R )||(def_ddr4_2400_14_14_14R )||(def_ddr4_1600_9_9_9_LR )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_2400_14_14_14_LR )||(def_ddr4_1600_9_9_9_L2 )||(def_ddr4_1866_11_11_11_L2 )||(def_ddr4_2133_12_12_12_L2 )||(def_ddr4_2400_14_14_14_L2)); -define def_mba_tmr0q_WRDM_dlys8 = ((def_ddr4_2400_13_13_13 )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_2400_13_13_13R )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_2400_13_13_13_L2)); - -#new all 0 -define def_mba_tmr1q_RRSBG_dlys0 = ((def_ddr3_1066_6_6_6_group )||( def_ddr3_1066_7_7_7_group )||( def_ddr3_1066_8_8_8_group )||( def_ddr3_1600_11_11_11 )||( def_ddr3_1600_11_11_11_2N )||( def_ddr3_1600_11_11_11R )||( def_ddr3_1600_11_11_11_LR )||( def_ddr3_1600_11_11_11_L2 )||( def_ddr3_1333_9_9_9 )||( def_ddr3_1600_10_10_10 )||( def_ddr3_1333_9_9_9_2N )||( def_ddr3_1600_10_10_10_2N )||( def_ddr3_1333_9_9_9R )||( def_ddr3_1600_10_10_10R )||( def_ddr3_1333_9_9_9_LR )||( def_ddr3_1600_10_10_10_LR )||( def_ddr3_1333_9_9_9_L2 )||( def_ddr3_1600_10_10_10_L2 )||( def_ddr3_1333_8_8_8 )||( def_ddr3_1600_9_9_9 )||( def_ddr3_1333_8_8_8_2N )||( def_ddr3_1600_9_9_9_2N )||( def_ddr3_1333_8_8_8R )||( def_ddr3_1600_9_9_9R )||( def_ddr3_1333_8_8_8_LR )||( def_ddr3_1600_9_9_9_LR )||( def_ddr3_1333_8_8_8_L2 )||( def_ddr3_1600_9_9_9_L2 )||( def_ddr3_1866_12_12_12 )||( def_ddr3_1866_12_12_12_2N )||( def_ddr3_1866_12_12_12R )||( def_ddr3_1866_12_12_12_LR )||( def_ddr3_1866_12_12_12_L2 )||( def_ddr3_1866_11_11_11 )||( def_ddr3_1866_11_11_11_2N )||( def_ddr3_1866_11_11_11R )||( def_ddr3_1866_11_11_11_LR )||( def_ddr3_1866_11_11_11_L2)); -define def_mba_tmr1q_RRSBG_dlys5 = (def_ddr4_1600_12_12_12 ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 ||def_ddr4_1866_13_13_13 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2 || (def_ddr4_1600_11_11_11 )||( def_ddr4_1600_11_11_11_2N )||( def_ddr4_1600_11_11_11R )||( def_ddr4_1600_11_11_11_LR )||( def_ddr4_1600_11_11_11_L2 )||( def_ddr4_1600_10_10_10 )||( def_ddr4_1600_10_10_10_2N )||( def_ddr4_1600_10_10_10R )||( def_ddr4_1600_10_10_10_LR )||( def_ddr4_1600_10_10_10_L2 )||( def_ddr4_1600_9_9_9 )||( def_ddr4_1600_9_9_9_2N )||( def_ddr4_1600_9_9_9R )||( def_ddr4_1600_9_9_9_LR )||( def_ddr4_1600_9_9_9_L2 )||( def_ddr4_1866_12_12_12 )||( def_ddr4_1866_12_12_12_2N )||( def_ddr4_1866_12_12_12R )||( def_ddr4_1866_12_12_12_LR )||( def_ddr4_1866_12_12_12_L2 )||( def_ddr4_1866_11_11_11 )||( def_ddr4_1866_11_11_11_2N )||( def_ddr4_1866_11_11_11R )||( def_ddr4_1866_11_11_11_LR )||( def_ddr4_1866_11_11_11_L2)); -define def_mba_tmr1q_RRSBG_dlys6 = ((def_ddr4_2133_13_13_13 )||( def_ddr4_2133_13_13_13_2N )||( def_ddr4_2133_13_13_13R )||( def_ddr4_2133_13_13_13_LR )||( def_ddr4_2133_13_13_13_L2 )||( def_ddr4_2133_12_12_12 )||( def_ddr4_2133_12_12_12_2N )||( def_ddr4_2133_12_12_12R )||( def_ddr4_2133_12_12_12_LR )||( def_ddr4_2133_12_12_12_L2 )||( def_ddr4_2400_14_14_14 )||( def_ddr4_2400_14_14_14_2N )||( def_ddr4_2400_14_14_14R )||( def_ddr4_2400_14_14_14_LR )||( def_ddr4_2400_14_14_14_L2 )||( def_ddr4_2400_13_13_13 )||( def_ddr4_2400_13_13_13_2N )||( def_ddr4_2400_13_13_13R )||( def_ddr4_2400_13_13_13_LR )||( def_ddr4_2400_13_13_13_L2)); - -#new all 0 -define def_mba_tmr1q_WRSBG_dlys0 = ((def_ddr3_1066_6_6_6_group )||( def_ddr3_1066_7_7_7_group )||( def_ddr3_1066_8_8_8_group )||( def_ddr3_1333_8_8_8 )||( def_ddr3_1333_9_9_9 )||( def_ddr3_1600_9_9_9 )||( def_ddr3_1600_10_10_10 )||( def_ddr3_1600_11_11_11 )||( def_ddr3_1866_11_11_11 )||( def_ddr3_1866_12_12_12 )||( def_ddr3_1333_8_8_8_2N )||( def_ddr3_1333_9_9_9_2N )||( def_ddr3_1600_9_9_9_2N )||( def_ddr3_1600_10_10_10_2N )||( def_ddr3_1600_11_11_11_2N )||( def_ddr3_1866_11_11_11_2N )||( def_ddr3_1866_12_12_12_2N )||( def_ddr3_1333_8_8_8R )||( def_ddr3_1333_9_9_9R )||( def_ddr3_1600_9_9_9R )||( def_ddr3_1600_10_10_10R )||( def_ddr3_1600_11_11_11R )||( def_ddr3_1866_11_11_11R )||( def_ddr3_1866_12_12_12R )||( def_ddr3_1333_8_8_8_LR )||( def_ddr3_1333_9_9_9_LR )||( def_ddr3_1600_9_9_9_LR )||( def_ddr3_1600_10_10_10_LR )||( def_ddr3_1600_11_11_11_LR )||( def_ddr3_1866_11_11_11_LR )||( def_ddr3_1866_12_12_12_LR )||( def_ddr3_1333_8_8_8_L2 )||( def_ddr3_1333_9_9_9_L2 )||( def_ddr3_1600_9_9_9_L2 )||( def_ddr3_1600_10_10_10_L2 )||( def_ddr3_1600_11_11_11_L2 )||( def_ddr3_1866_11_11_11_L2 )||( def_ddr3_1866_12_12_12_L2)); -define def_mba_tmr1q_WRSBG_dlys26 = ((def_ddr4_1600_9_9_9 )||( def_ddr4_1600_9_9_9_2N )||( def_ddr4_1600_9_9_9R )||( def_ddr4_1600_9_9_9_LR )||( def_ddr4_1600_9_9_9_L2)); -define def_mba_tmr1q_WRSBG_dlys27 = ((def_ddr4_1600_10_10_10 )||( def_ddr4_1600_10_10_10_2N )||( def_ddr4_1600_10_10_10R )||( def_ddr4_1600_10_10_10_LR )||( def_ddr4_1600_10_10_10_L2)); -define def_mba_tmr1q_WRSBG_dlys28 = ((def_ddr4_1600_11_11_11 )||( def_ddr4_1600_11_11_11_2N )||( def_ddr4_1600_11_11_11R )||( def_ddr4_1600_11_11_11_LR )||( def_ddr4_1600_11_11_11_L2)); -define def_mba_tmr1q_WRSBG_dlys29 = (def_ddr4_1600_12_12_12 ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2 ); -define def_mba_tmr1q_WRSBG_dlys30 = ((def_ddr4_1866_11_11_11 )||( def_ddr4_1866_11_11_11_2N )||( def_ddr4_1866_11_11_11R )||( def_ddr4_1866_11_11_11_LR )||( def_ddr4_1866_11_11_11_L2)); -define def_mba_tmr1q_WRSBG_dlys31 = ((def_ddr4_1866_12_12_12 )||( def_ddr4_1866_12_12_12_2N )||( def_ddr4_1866_12_12_12R )||( def_ddr4_1866_12_12_12_LR )||( def_ddr4_1866_12_12_12_L2)); -#define def_mba_tmr1q_WRSBG_dlys32 = (def_ddr4_1866_13_13_13 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2 ); -#define def_mba_tmr1q_WRSBG_dlys33 = ((def_ddr4_2133_12_12_12 )||( def_ddr4_2133_12_12_12_2N )||( def_ddr4_2133_12_12_12R )||( def_ddr4_2133_12_12_12_LR )||( def_ddr4_2133_12_12_12_L2)); -#define def_mba_tmr1q_WRSBG_dlys34 = ((def_ddr4_2133_13_13_13 )||( def_ddr4_2133_13_13_13_2N )||( def_ddr4_2133_13_13_13R )||( def_ddr4_2133_13_13_13_LR )||( def_ddr4_2133_13_13_13_L2)); -#define def_mba_tmr1q_WRSBG_dlys36 = ((def_ddr4_2400_13_13_13 )||( def_ddr4_2400_13_13_13_2N )||( def_ddr4_2400_13_13_13R )||( def_ddr4_2400_13_13_13_LR )||( def_ddr4_2400_13_13_13_L2)); -#define def_mba_tmr1q_WRSBG_dlys37 = ((def_ddr4_2400_14_14_14 )||( def_ddr4_2400_14_14_14_2N )||( def_ddr4_2400_14_14_14R )||( def_ddr4_2400_14_14_14_LR )||( def_ddr4_2400_14_14_14_L2)); - -#new 26,27,28 -define def_mba_tmr1q_cfg_trap26 = ((def_ddr3_1066_6_6_6_group )||(def_ddr3_1333_8_8_8 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1333_8_8_8_L2)); -define def_mba_tmr1q_cfg_trap27 = ((def_ddr3_1066_7_7_7_group )||(def_ddr3_1333_8_8_8 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1333_8_8_8_L2)); -define def_mba_tmr1q_cfg_trap28 = ((def_ddr3_1066_8_8_8_group )||(def_ddr3_1333_8_8_8 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1333_8_8_8_L2)); - -define def_mba_tmr1q_cfg_trap32 = ((def_ddr3_1333_8_8_8 )||(def_ddr3_1333_8_8_8_2N )||(def_ddr3_1333_8_8_8R )||(def_ddr3_1333_8_8_8_LR )||(def_ddr3_1333_8_8_8_L2)); -define def_mba_tmr1q_cfg_trap33 = ((def_ddr3_1333_9_9_9 )||(def_ddr3_1333_9_9_9_2N )||(def_ddr3_1333_9_9_9R )||(def_ddr3_1333_9_9_9_LR )||(def_ddr3_1333_9_9_9_L2)); -define def_mba_tmr1q_cfg_trap37 = ((def_ddr3_1600_9_9_9 )||(def_ddr3_1600_9_9_9_2N )||(def_ddr3_1600_9_9_9R )||(def_ddr3_1600_9_9_9_LR )||(def_ddr3_1600_9_9_9_L2 )||(def_ddr4_1600_9_9_9 )||(def_ddr4_1600_9_9_9_2N )||(def_ddr4_1600_9_9_9R )||(def_ddr4_1600_9_9_9_LR )||(def_ddr4_1600_9_9_9_L2)); -define def_mba_tmr1q_cfg_trap38 = ((def_ddr3_1600_10_10_10 )||(def_ddr3_1600_10_10_10_2N )||(def_ddr3_1600_10_10_10R )||(def_ddr3_1600_10_10_10_LR )||(def_ddr3_1600_10_10_10_L2 )||(def_ddr4_1600_10_10_10 )||(def_ddr4_1600_10_10_10_2N )||(def_ddr4_1600_10_10_10R )||(def_ddr4_1600_10_10_10_LR )||(def_ddr4_1600_10_10_10_L2)); -define def_mba_tmr1q_cfg_trap39 = ((def_ddr3_1600_11_11_11 )||(def_ddr3_1866_11_11_11 )||(def_ddr3_1600_11_11_11_2N )||(def_ddr3_1866_11_11_11_2N )||(def_ddr3_1600_11_11_11R )||(def_ddr3_1866_11_11_11R )||(def_ddr3_1600_11_11_11_LR )||(def_ddr3_1866_11_11_11_LR )||(def_ddr3_1600_11_11_11_L2 )||(def_ddr3_1866_11_11_11_L2 )||(def_ddr4_1600_11_11_11 )||(def_ddr4_1600_11_11_11_2N )||(def_ddr4_1600_11_11_11R )||(def_ddr4_1600_11_11_11_LR )||(def_ddr4_1600_11_11_11_L2)); -define def_mba_tmr1q_cfg_trap40 = ((def_ddr3_1866_12_12_12 )||(def_ddr3_1866_12_12_12_2N )||(def_ddr3_1866_12_12_12R )||(def_ddr3_1866_12_12_12_LR )||(def_ddr3_1866_12_12_12_L2)); -define def_mba_tmr1q_cfg_trap42 = (def_ddr4_1600_12_12_12 ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2); -define def_mba_tmr1q_cfg_trap43 = ((def_ddr4_1866_11_11_11 )||(def_ddr4_1866_11_11_11_2N )||(def_ddr4_1866_11_11_11R )||(def_ddr4_1866_11_11_11_LR )||(def_ddr4_1866_11_11_11_L2)); -define def_mba_tmr1q_cfg_trap44 = ((def_ddr4_1866_12_12_12 )||(def_ddr4_1866_12_12_12_2N )||(def_ddr4_1866_12_12_12R )||(def_ddr4_1866_12_12_12_LR )||(def_ddr4_1866_12_12_12_L2)); -define def_mba_tmr1q_cfg_trap46 = (def_ddr4_1866_13_13_13 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2); -#define def_mba_tmr1q_cfg_trap48 = ((def_ddr4_2133_12_12_12 )||(def_ddr4_2133_12_12_12_2N )||(def_ddr4_2133_12_12_12R )||(def_ddr4_2133_12_12_12_LR )||(def_ddr4_2133_12_12_12_L2)); -#define def_mba_tmr1q_cfg_trap49 = ((def_ddr4_2133_13_13_13 )||(def_ddr4_2133_13_13_13_2N )||(def_ddr4_2133_13_13_13R )||(def_ddr4_2133_13_13_13_LR )||(def_ddr4_2133_13_13_13_L2)); -#define def_mba_tmr1q_cfg_trap52 = ((def_ddr4_2400_13_13_13 )||(def_ddr4_2400_13_13_13_2N )||(def_ddr4_2400_13_13_13R )||(def_ddr4_2400_13_13_13_LR )||(def_ddr4_2400_13_13_13_L2)); -#define def_mba_tmr1q_cfg_trap53 = ((def_ddr4_2400_14_14_14 )||(def_ddr4_2400_14_14_14_2N )||(def_ddr4_2400_14_14_14R )||(def_ddr4_2400_14_14_14_LR )||(def_ddr4_2400_14_14_14_L2)); - -#new 30,32,34 -define def_mba_tmr1q_cfg_twap30 = (def_ddr3_1066_6_6_6_group); -define def_mba_tmr1q_cfg_twap32 = (def_ddr3_1066_7_7_7_group); -define def_mba_tmr1q_cfg_twap34 = (def_ddr3_1066_8_8_8_group); - -define def_mba_tmr1q_cfg_twap37 = (def_mba_tmr1q_cfg_trap32); -define def_mba_tmr1q_cfg_twap39 = (def_mba_tmr1q_cfg_trap33); -define def_mba_tmr1q_cfg_twap42 = (def_mba_tmr1q_cfg_trap37); -define def_mba_tmr1q_cfg_twap44 = (def_mba_tmr1q_cfg_trap38); -define def_mba_tmr1q_cfg_twap46 = ((def_ddr3_1600_11_11_11 )||( def_ddr3_1600_11_11_11_2N )||( def_ddr3_1600_11_11_11R )||( def_ddr3_1600_11_11_11_LR )||( def_ddr3_1600_11_11_11_L2 )||( def_ddr4_1600_11_11_11 )||( def_ddr4_1600_11_11_11_2N )||( def_ddr4_1600_11_11_11R )||( def_ddr4_1600_11_11_11_LR )||( def_ddr4_1600_11_11_11_L2)); -define def_mba_tmr1q_cfg_twap48 = (def_ddr4_1600_12_12_12 ||def_ddr4_1600_12_12_12_2N ||def_ddr4_1600_12_12_12R ||def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12_L2); -define def_mba_tmr1q_cfg_twap49 = ((def_ddr3_1866_11_11_11 )||( def_ddr3_1866_11_11_11_2N )||( def_ddr3_1866_11_11_11R )||( def_ddr3_1866_11_11_11_LR )||( def_ddr3_1866_11_11_11_L2 )||( def_ddr4_1866_11_11_11 )||( def_ddr4_1866_11_11_11_2N )||( def_ddr4_1866_11_11_11R )||( def_ddr4_1866_11_11_11_LR )||( def_ddr4_1866_11_11_11_L2)); -define def_mba_tmr1q_cfg_twap51 = ((def_ddr3_1866_12_12_12 )||( def_ddr3_1866_12_12_12_2N )||( def_ddr3_1866_12_12_12R )||( def_ddr3_1866_12_12_12_LR )||( def_ddr3_1866_12_12_12_L2 )||( def_ddr4_1866_12_12_12 )||( def_ddr4_1866_12_12_12_2N )||( def_ddr4_1866_12_12_12R )||( def_ddr4_1866_12_12_12_LR )||( def_ddr4_1866_12_12_12_L2)); -define def_mba_tmr1q_cfg_twap53 = (def_ddr4_1866_13_13_13 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1866_13_13_13R ||def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13_L2); -#define def_mba_tmr1q_cfg_twap54 = (def_mba_tmr1q_cfg_trap48); -#define def_mba_tmr1q_cfg_twap56 = (def_mba_tmr1q_cfg_trap49); -#define def_mba_tmr1q_cfg_twap59 = (def_mba_tmr1q_cfg_trap52); -#define def_mba_tmr1q_cfg_twap61 = (def_mba_tmr1q_cfg_trap53); - -#mixed stop here -define def_mba_dsm0q_cfg_rdtag_dly12 = (def_ddr3_1066_6_6_6_2N); -define def_mba_dsm0q_cfg_rdtag_dly13 = (def_ddr3_1066_6_6_6); - -define def_mba_dsm0q_cfg_rdtag_dly14 = (def_ddr3_1066_7_7_7_2N || def_ddr3_1066_6_6_6R ||def_ddr3_1333_8_8_8_2N); -define def_mba_dsm0q_cfg_rdtag_dly15 = (def_ddr3_1066_7_7_7 ||def_ddr3_1066_8_8_8_2N ||def_ddr3_1333_8_8_8 ||def_ddr3_1600_9_9_9_2N ||def_ddr4_1600_9_9_9_2N); -define def_mba_dsm0q_cfg_rdtag_dly16 = (def_ddr3_1066_8_8_8 ||def_ddr3_1066_7_7_7R ||def_ddr3_1066_6_6_6_L2 ||def_ddr3_1600_9_9_9 ||def_ddr3_1333_9_9_9_2N ||def_ddr3_1600_10_10_10_2N ||def_ddr3_1333_8_8_8R ||def_ddr4_1600_9_9_9); -define def_mba_dsm0q_cfg_rdtag_dly17 = (def_ddr3_1066_8_8_8R ||def_ddr3_1066_6_6_6_LR ||def_ddr3_1333_9_9_9 ||def_ddr3_1600_9_9_9R ||def_ddr4_1600_10_10_10_2N ||def_ddr4_1600_9_9_9R); -define def_mba_dsm0q_cfg_rdtag_dly18 = (def_ddr3_1066_7_7_7_L2 ||def_ddr3_1600_10_10_10 ||def_ddr3_1600_11_11_11_2N ||def_ddr3_1866_11_11_11_2N ||def_ddr3_1333_9_9_9R ||def_ddr3_1333_8_8_8_L2 ||def_ddr4_1600_10_10_10); -define def_mba_dsm0q_cfg_rdtag_dly19 = (def_ddr3_1066_7_7_7_LR ||def_ddr3_1066_8_8_8_L2 ||def_ddr3_1600_10_10_10R ||def_ddr3_1333_8_8_8_LR ||def_ddr3_1600_9_9_9_L2 ||def_ddr4_1600_11_11_11_2N ||def_ddr4_1866_11_11_11_2N ||def_ddr4_1600_10_10_10R ||def_ddr4_1600_9_9_9_L2); -define def_mba_dsm0q_cfg_rdtag_dly20 = (def_ddr3_1066_8_8_8_LR ||def_ddr3_1600_11_11_11 ||def_ddr3_1866_11_11_11 ||def_ddr3_1866_12_12_12_2N ||def_ddr3_1600_9_9_9_LR ||def_ddr3_1333_9_9_9_L2 ||def_ddr4_1600_11_11_11 ||def_ddr4_1866_11_11_11 ||def_ddr4_1600_9_9_9_LR); -define def_mba_dsm0q_cfg_rdtag_dly21 = (def_ddr4_1600_12_12_12_2N ||def_ddr3_1600_11_11_11R ||def_ddr3_1866_11_11_11R ||def_ddr3_1333_9_9_9_LR ||def_ddr3_1600_10_10_10_L2 ||def_ddr4_1866_12_12_12_2N ||def_ddr4_2133_12_12_12_2N ||def_ddr4_1600_11_11_11R ||def_ddr4_1866_11_11_11R ||def_ddr4_1600_10_10_10_L2); -define def_mba_dsm0q_cfg_rdtag_dly22 = (def_ddr4_1600_12_12_12 ||def_ddr3_1866_12_12_12 ||def_ddr3_1600_10_10_10_LR ||def_ddr4_1866_12_12_12 ||def_ddr4_2133_12_12_12 ||def_ddr4_2400_13_13_13_2N ||def_ddr4_1600_10_10_10_LR); -define def_mba_dsm0q_cfg_rdtag_dly23 = (def_ddr4_1866_13_13_13_2N ||def_ddr4_1600_12_12_12R ||def_ddr3_1866_12_12_12R ||def_ddr3_1600_11_11_11_L2 ||def_ddr3_1866_11_11_11_L2 ||def_ddr4_2400_13_13_13 ||def_ddr4_2133_13_13_13_2N ||def_ddr4_1866_12_12_12R ||def_ddr4_2133_12_12_12R ||def_ddr4_1600_11_11_11_L2 ||def_ddr4_1866_11_11_11_L2); -define def_mba_dsm0q_cfg_rdtag_dly24 = (def_ddr4_1866_13_13_13 ||def_ddr3_1600_11_11_11_LR ||def_ddr3_1866_11_11_11_LR ||def_ddr4_2133_13_13_13 ||def_ddr4_2400_14_14_14_2N ||def_ddr4_2400_13_13_13R ||def_ddr4_1600_11_11_11_LR ||def_ddr4_1866_11_11_11_LR); -define def_mba_dsm0q_cfg_rdtag_dly25 = (def_ddr4_1866_13_13_13R ||def_ddr4_1600_12_12_12_L2 ||def_ddr3_1866_12_12_12_L2 ||def_ddr4_2400_14_14_14 ||def_ddr4_2133_13_13_13R ||def_ddr4_1866_12_12_12_L2 ||def_ddr4_2133_12_12_12_L2); -define def_mba_dsm0q_cfg_rdtag_dly26 = (def_ddr4_1600_12_12_12_LR ||def_ddr3_1866_12_12_12_LR ||def_ddr4_2400_14_14_14R ||def_ddr4_1866_12_12_12_LR ||def_ddr4_2133_12_12_12_LR ||def_ddr4_2400_13_13_13_L2); -define def_mba_dsm0q_cfg_rdtag_dly27 = (def_ddr4_1866_13_13_13_L2 ||def_ddr4_2400_13_13_13_LR ||def_ddr4_2133_13_13_13_L2); -define def_mba_dsm0q_cfg_rdtag_dly28 = (def_ddr4_1866_13_13_13_LR ||def_ddr4_2133_13_13_13_LR ||def_ddr4_2400_14_14_14_L2); -define def_mba_dsm0q_cfg_rdtag_dly29 = (def_ddr4_2400_14_14_14_LR); - -#mixed -define def_mba_dsm0q_cfg_wrdata_dly3 = (def_ddr3_1066_6_6_6_2N ||def_ddr3_1066_6_6_6_L2); -define def_mba_dsm0q_cfg_wrdata_dly4 = (def_ddr3_1066_6_6_6 ||def_ddr3_1066_7_7_7_2N ||def_ddr3_1066_6_6_6_LR ||def_ddr3_1066_7_7_7_L2); -define def_mba_dsm0q_cfg_wrdata_dly5 = (def_ddr3_1066_7_7_7 ||def_ddr3_1066_8_8_8_2N ||def_ddr3_1066_6_6_6R ||def_ddr3_1066_7_7_7_LR ||def_ddr3_1066_8_8_8_L2); - -define def_mba_dsm0q_cfg_wrdata_dly6 = (def_ddr3_1066_8_8_8 ||def_ddr3_1066_7_7_7R ||def_ddr3_1066_8_8_8_LR ||def_ddr3_1333_8_8_8_2N ||def_ddr3_1333_8_8_8_L2); -define def_mba_dsm0q_cfg_wrdata_dly7 = (def_ddr3_1066_8_8_8R ||def_ddr3_1333_8_8_8 ||def_ddr3_1333_9_9_9_2N ||def_ddr3_1333_8_8_8_LR ||def_ddr3_1333_9_9_9_L2); -define def_mba_dsm0q_cfg_wrdata_dly8 = (def_ddr3_1333_9_9_9 ||def_ddr3_1600_9_9_9_2N ||def_ddr3_1333_8_8_8R ||def_ddr3_1333_9_9_9_LR ||def_ddr3_1600_9_9_9_L2); -define def_mba_dsm0q_cfg_wrdata_dly9 = (def_ddr3_1600_9_9_9 ||def_ddr3_1600_10_10_10_2N ||def_ddr3_1333_9_9_9R ||def_ddr3_1600_9_9_9_LR ||def_ddr3_1600_10_10_10_L2 ||def_ddr4_1600_9_9_9_2N ||def_ddr4_1600_9_9_9_L2); -define def_mba_dsm0q_cfg_wrdata_dly10 = (def_ddr3_1600_10_10_10 ||def_ddr3_1600_11_11_11_2N ||def_ddr3_1600_9_9_9R ||def_ddr3_1600_10_10_10_LR ||def_ddr3_1600_11_11_11_L2 ||def_ddr4_1600_9_9_9 ||def_ddr4_1600_10_10_10_2N ||def_ddr4_1600_9_9_9_LR ||def_ddr4_1600_10_10_10_L2); -define def_mba_dsm0q_cfg_wrdata_dly11 = (def_ddr3_1600_11_11_11 ||def_ddr3_1866_11_11_11_2N ||def_ddr3_1600_10_10_10R ||def_ddr3_1600_11_11_11_LR ||def_ddr3_1866_11_11_11_L2 ||def_ddr4_1600_10_10_10 ||def_ddr4_1600_11_11_11_2N ||def_ddr4_1600_9_9_9R ||def_ddr4_1600_10_10_10_LR ||def_ddr4_1600_11_11_11_L2); -define def_mba_dsm0q_cfg_wrdata_dly12 = (def_ddr4_1600_12_12_12_L2 ||def_ddr4_1600_12_12_12_2N ||def_ddr3_1866_11_11_11 ||def_ddr3_1866_12_12_12_2N ||def_ddr3_1600_11_11_11R ||def_ddr3_1866_11_11_11_LR ||def_ddr3_1866_12_12_12_L2 ||def_ddr4_1600_11_11_11 ||def_ddr4_1866_11_11_11_2N ||def_ddr4_1600_10_10_10R ||def_ddr4_1600_11_11_11_LR ||def_ddr4_1866_11_11_11_L2); -define def_mba_dsm0q_cfg_wrdata_dly13 = (def_ddr4_1600_12_12_12_LR ||def_ddr4_1600_12_12_12 ||def_ddr3_1866_12_12_12 ||def_ddr3_1866_11_11_11R ||def_ddr3_1866_12_12_12_LR ||def_ddr4_1866_11_11_11 ||def_ddr4_1866_12_12_12_2N ||def_ddr4_1600_11_11_11R ||def_ddr4_1866_11_11_11_LR ||def_ddr4_1866_12_12_12_L2); -define def_mba_dsm0q_cfg_wrdata_dly14 = (def_ddr4_1866_13_13_13_L2 ||def_ddr4_1866_13_13_13_2N ||def_ddr4_1600_12_12_12R ||def_ddr3_1866_12_12_12R ||def_ddr4_1866_12_12_12 ||def_ddr4_2133_12_12_12_2N ||def_ddr4_1866_11_11_11R ||def_ddr4_1866_12_12_12_LR ||def_ddr4_2133_12_12_12_L2); -define def_mba_dsm0q_cfg_wrdata_dly15 = (def_ddr4_1866_13_13_13_LR ||def_ddr4_1866_13_13_13 ||def_ddr4_2133_12_12_12 ||def_ddr4_2133_13_13_13_2N ||def_ddr4_1866_12_12_12R ||def_ddr4_2133_12_12_12_LR ||def_ddr4_2133_13_13_13_L2); -define def_mba_dsm0q_cfg_wrdata_dly16 = (def_ddr4_1866_13_13_13R ||def_ddr4_2133_13_13_13 ||def_ddr4_2400_13_13_13_2N ||def_ddr4_2133_12_12_12R ||def_ddr4_2133_13_13_13_LR ||def_ddr4_2400_13_13_13_L2); -define def_mba_dsm0q_cfg_wrdata_dly17 = (def_ddr4_2400_13_13_13 ||def_ddr4_2400_14_14_14_2N ||def_ddr4_2133_13_13_13R ||def_ddr4_2400_13_13_13_LR ||def_ddr4_2400_14_14_14_L2); -define def_mba_dsm0q_cfg_wrdata_dly18 = (def_ddr4_2400_14_14_14 ||def_ddr4_2400_13_13_13R ||def_ddr4_2400_14_14_14_LR); -define def_mba_dsm0q_cfg_wrdata_dly19 = (def_ddr4_2400_14_14_14R); - - -# -define def_MBAREF0Q_cfg_refr_tsv_stack_dly32 = (def_1066_2gb || def_1333_2gb || def_1600_2gb || def_1866_2gb || def_1066_2gb_fast_exit_pd || def_1333_2gb_fast_exit_pd || def_1600_2gb_fast_exit_pd || def_1866_2gb_fast_exit_pd || def_1600_2gb_ddr4 || def_1866_2gb_ddr4 || def_2133_2gb_ddr4 || def_2400_2gb_ddr4 || def_1600_2gb_fast_exit_pd_ddr4 || def_1866_2gb_fast_exit_pd_ddr4 || def_2133_2gb_fast_exit_pd_ddr4 || def_2400_2gb_fast_exit_pd_ddr4 ); -define def_MBAREF0Q_cfg_refr_tsv_stack_dly48 = (def_1066_4gb || def_1333_4gb || def_1600_4gb || def_1866_4gb || def_1066_4gb_fast_exit_pd || def_1333_4gb_fast_exit_pd || def_1600_4gb_fast_exit_pd || def_1866_4gb_fast_exit_pd || def_1600_4gb_ddr4 || def_1866_4gb_ddr4 || def_2133_4gb_ddr4 || def_2400_4gb_ddr4 || def_1600_4gb_fast_exit_pd_ddr4 || def_1866_4gb_fast_exit_pd_ddr4 || def_2133_4gb_fast_exit_pd_ddr4 || def_2400_4gb_fast_exit_pd_ddr4 ); -define def_MBAREF0Q_cfg_refr_tsv_stack_dly64 = (def_1066_8gb || def_1333_8gb || def_1600_8gb || def_1866_8gb || def_1066_8gb_fast_exit_pd || def_1333_8gb_fast_exit_pd || def_1600_8gb_fast_exit_pd || def_1866_8gb_fast_exit_pd || def_1600_8gb_ddr4 || def_1866_8gb_ddr4 || def_2133_8gb_ddr4 || def_2400_8gb_ddr4 || def_1600_8gb_fast_exit_pd_ddr4 || def_1866_8gb_fast_exit_pd_ddr4 || def_2133_8gb_fast_exit_pd_ddr4 || def_2400_8gb_fast_exit_pd_ddr4 ); - -# 3 -- old -#define def_MBARPC0Q_cfg_pup_pdn_dly3 = (def_1066_2gb ||def_1066_2gb_fast_exit_pd ||def_1066_4gb ||def_1066_4gb_fast_exit_pd ||def_1066_8gb ||def_1066_8gb_fast_exit_pd ); -# -#define def_MBARPC0Q_cfg_pup_pdn_dly4 = (def_1333_2gb ||def_1333_2gb_fast_exit_pd ||def_1600_2gb ||def_1600_2gb_fast_exit_pd ||def_1600_2gb_ddr4 ||def_1600_2gb_fast_exit_pd_ddr4 ||def_1333_4gb ||def_1333_4gb_fast_exit_pd ||def_1333_8gb ||def_1333_8gb_fast_exit_pd ||def_1600_4gb ||def_1600_4gb_fast_exit_pd ||def_1600_4gb_ddr4 ||def_1600_4gb_fast_exit_pd_ddr4 ||def_1600_8gb ||def_1600_8gb_fast_exit_pd ||def_1600_8gb_ddr4 ||def_1600_8gb_fast_exit_pd_ddr4 ); -#define def_MBARPC0Q_cfg_pup_pdn_dly5 = (def_1866_2gb ||def_1866_2gb_fast_exit_pd ||def_1866_2gb_ddr4 ||def_1866_2gb_fast_exit_pd_ddr4 ||def_2133_2gb_ddr4 ||def_2133_2gb_fast_exit_pd_ddr4 ||def_2400_2gb_ddr4 ||def_2400_2gb_fast_exit_pd_ddr4 ||def_2133_4gb_fast_exit_pd_ddr4 ||def_2133_4gb_ddr4 ||def_2400_4gb_ddr4 ||def_2400_4gb_fast_exit_pd_ddr4 ||def_1866_4gb ||def_1866_4gb_fast_exit_pd ||def_1866_4gb_ddr4 ||def_1866_4gb_fast_exit_pd_ddr4 ||def_1866_8gb ||def_1866_8gb_fast_exit_pd ||def_1866_8gb_ddr4 ||def_1866_8gb_fast_exit_pd_ddr4 ||def_2133_8gb_fast_exit_pd_ddr4 ||def_2133_8gb_ddr4 ||def_2400_8gb_ddr4 ||def_2400_8gb_fast_exit_pd_ddr4 ); - -# new -define def_MBARPC0Q_cfg_pup_pdn_dly3 = (def_1066_2gb ||def_1066_4gb ||def_1066_8gb ||def_1066_2gb_fast_exit_pd ||def_1066_4gb_fast_exit_pd ||def_1066_8gb_fast_exit_pd ); -define def_MBARPC0Q_cfg_pup_pdn_dly4 = (def_1333_2gb ||def_1333_4gb ||def_1333_8gb ||def_1600_2gb ||def_1600_4gb ||def_1600_8gb ||def_1333_2gb_fast_exit_pd ||def_1333_4gb_fast_exit_pd ||def_1333_8gb_fast_exit_pd ||def_1600_2gb_fast_exit_pd ||def_1600_4gb_fast_exit_pd ||def_1600_8gb_fast_exit_pd ||def_1600_2gb_ddr4 ||def_1600_4gb_ddr4 ||def_1600_8gb_ddr4 ||def_1600_2gb_fast_exit_pd_ddr4 ||def_1600_4gb_fast_exit_pd_ddr4 ||def_1600_8gb_fast_exit_pd_ddr4 ); -define def_MBARPC0Q_cfg_pup_pdn_dly5 = (def_1866_2gb ||def_1866_4gb ||def_1866_8gb ||def_1866_2gb_fast_exit_pd ||def_1866_4gb_fast_exit_pd ||def_1866_8gb_fast_exit_pd ||def_1866_2gb_ddr4 ||def_1866_4gb_ddr4 ||def_1866_8gb_ddr4 ||def_1866_2gb_fast_exit_pd_ddr4 ||def_1866_4gb_fast_exit_pd_ddr4 ||def_1866_8gb_fast_exit_pd_ddr4 ); -define def_MBARPC0Q_cfg_pup_pdn_dly6 = (def_2133_2gb_ddr4 ||def_2133_4gb_ddr4 ||def_2133_8gb_ddr4 ||def_2400_2gb_ddr4 ||def_2400_4gb_ddr4 ||def_2400_8gb_ddr4 ||def_2133_2gb_fast_exit_pd_ddr4 ||def_2133_4gb_fast_exit_pd_ddr4 ||def_2133_8gb_fast_exit_pd_ddr4 ||def_2400_2gb_fast_exit_pd_ddr4 ||def_2400_4gb_fast_exit_pd_ddr4 ||def_2400_8gb_fast_exit_pd_ddr4 ); - -#3 -#define def_MBARPC0Q_cfg_pdn_pup_dly3 = (def_1066_2gb ||def_1066_2gb_fast_exit_pd ||def_1066_4gb ||def_1066_4gb_fast_exit_pd ||def_1066_8gb ||def_1066_8gb_fast_exit_pd ); - -#define def_MBARPC0Q_cfg_pdn_pup_dly4 = (def_1333_2gb ||def_1333_2gb_fast_exit_pd ||def_1600_2gb ||def_1600_2gb_fast_exit_pd ||def_1600_2gb_ddr4 ||def_1600_2gb_fast_exit_pd_ddr4 ||def_1333_4gb ||def_1333_4gb_fast_exit_pd ||def_1333_8gb ||def_1333_8gb_fast_exit_pd ||def_1600_4gb ||def_1600_4gb_fast_exit_pd ||def_1600_4gb_ddr4 ||def_1600_4gb_fast_exit_pd_ddr4 ||def_1600_8gb ||def_1600_8gb_fast_exit_pd ||def_1600_8gb_ddr4 ||def_1600_8gb_fast_exit_pd_ddr4 ); -#define def_MBARPC0Q_cfg_pdn_pup_dly5 = (def_1866_2gb ||def_1866_2gb_fast_exit_pd ||def_1866_2gb_ddr4 ||def_1866_2gb_fast_exit_pd_ddr4 ||def_2133_2gb_ddr4 ||def_2133_2gb_fast_exit_pd_ddr4 ||def_2400_2gb_ddr4 ||def_2400_2gb_fast_exit_pd_ddr4 ||def_2133_4gb_fast_exit_pd_ddr4 ||def_2133_4gb_ddr4 ||def_2400_4gb_ddr4 ||def_2400_4gb_fast_exit_pd_ddr4 ||def_1866_4gb ||def_1866_4gb_fast_exit_pd ||def_1866_4gb_ddr4 ||def_1866_4gb_fast_exit_pd_ddr4 ||def_1866_8gb ||def_1866_8gb_fast_exit_pd ||def_1866_8gb_ddr4 ||def_1866_8gb_fast_exit_pd_ddr4 ||def_2133_8gb_fast_exit_pd_ddr4 ||def_2133_8gb_ddr4 ||def_2400_8gb_ddr4 ||def_2400_8gb_fast_exit_pd_ddr4 ); - -#3 -define def_MBARPC0Q_cfg_pdn_pup_dly3 = (def_MBARPC0Q_cfg_pup_pdn_dly3); - -define def_MBARPC0Q_cfg_pdn_pup_dly4 = (def_MBARPC0Q_cfg_pup_pdn_dly4); -define def_MBARPC0Q_cfg_pdn_pup_dly5 = (def_MBARPC0Q_cfg_pup_pdn_dly5); -define def_MBARPC0Q_cfg_pdn_pup_dly6 = (def_MBARPC0Q_cfg_pup_pdn_dly6); - -# 13 -- old -#define def_MBARPC0Q_cfg_pup_avail_dly13 = (def_1066_2gb )||(def_1066_4gb )||(def_1066_8gb); -# -#define def_MBARPC0Q_cfg_pup_avail_dly4 = ((def_1066_2gb_fast_exit_pd )||(def_1066_4gb_fast_exit_pd )||(def_1066_8gb_fast_exit_pd )||(def_1333_2gb_fast_exit_pd )||(def_1333_4gb_fast_exit_pd )||(def_1333_8gb_fast_exit_pd)); -#define def_MBARPC0Q_cfg_pup_avail_dly5 = ((def_1600_2gb_fast_exit_pd )||(def_1600_2gb_fast_exit_pd_ddr4 )||(def_1600_4gb_fast_exit_pd )||(def_1600_4gb_fast_exit_pd_ddr4 )||(def_1600_8gb_fast_exit_pd )||(def_1600_8gb_fast_exit_pd_ddr4 )); -#define def_MBARPC0Q_cfg_pup_avail_dly6 = ((def_1866_2gb_fast_exit_pd )||(def_1866_2gb_fast_exit_pd_ddr4 )||(def_2133_2gb_fast_exit_pd_ddr4 )||(def_2400_2gb_fast_exit_pd_ddr4 )||(def_2133_4gb_fast_exit_pd_ddr4 )||(def_2400_4gb_fast_exit_pd_ddr4 )||(def_1866_4gb_fast_exit_pd )||(def_1866_4gb_fast_exit_pd_ddr4 )||(def_1866_8gb_fast_exit_pd )||(def_1866_8gb_fast_exit_pd_ddr4 )||(def_2133_8gb_fast_exit_pd_ddr4 )||(def_2400_8gb_fast_exit_pd_ddr4 )); -#define def_MBARPC0Q_cfg_pup_avail_dly16 = ((def_1333_2gb )||(def_1333_4gb )||(def_1333_8gb)); -#define def_MBARPC0Q_cfg_pup_avail_dly20 = ((def_1600_2gb )||(def_1600_2gb_ddr4 )||(def_1600_4gb )||(def_1600_4gb_ddr4 )||(def_1600_8gb )||(def_1600_8gb_ddr4 )); -#define def_MBARPC0Q_cfg_pup_avail_dly23 = ((def_1866_2gb )||(def_1866_2gb_ddr4 )||(def_2133_2gb_ddr4 )||(def_2400_2gb_ddr4 )||(def_2133_4gb_ddr4 )||(def_2400_4gb_ddr4 )||(def_1866_4gb )||(def_1866_4gb_ddr4 )||(def_1866_8gb )||(def_1866_8gb_ddr4 )||(def_2133_8gb_ddr4 )||(def_2400_8gb_ddr4 )); - -# new -define def_MBARPC0Q_cfg_pup_avail_dly4 = ( def_1066_2gb_fast_exit_pd ||def_1066_4gb_fast_exit_pd ||def_1066_8gb_fast_exit_pd ||def_1333_2gb_fast_exit_pd ||def_1333_4gb_fast_exit_pd ||def_1333_8gb_fast_exit_pd ); -define def_MBARPC0Q_cfg_pup_avail_dly5 = ( def_1600_2gb_fast_exit_pd ||def_1600_4gb_fast_exit_pd ||def_1600_8gb_fast_exit_pd ||def_1600_2gb_fast_exit_pd_ddr4 ||def_1600_4gb_fast_exit_pd_ddr4 ||def_1600_8gb_fast_exit_pd_ddr4 ); -define def_MBARPC0Q_cfg_pup_avail_dly6 = ( def_1866_2gb_fast_exit_pd ||def_1866_4gb_fast_exit_pd ||def_1866_8gb_fast_exit_pd ||def_1866_2gb_fast_exit_pd_ddr4 ||def_1866_4gb_fast_exit_pd_ddr4 ||def_1866_8gb_fast_exit_pd_ddr4 ); -define def_MBARPC0Q_cfg_pup_avail_dly7 = ( def_2133_2gb_fast_exit_pd_ddr4 ||def_2133_4gb_fast_exit_pd_ddr4 ||def_2133_8gb_fast_exit_pd_ddr4 ); -define def_MBARPC0Q_cfg_pup_avail_dly8 = ( def_2400_2gb_fast_exit_pd_ddr4 ||def_2400_4gb_fast_exit_pd_ddr4 ||def_2400_8gb_fast_exit_pd_ddr4 ); -define def_MBARPC0Q_cfg_pup_avail_dly13 = ( def_1066_2gb ||def_1066_4gb ||def_1066_8gb ); -define def_MBARPC0Q_cfg_pup_avail_dly16 = ( def_1333_2gb ||def_1333_4gb ||def_1333_8gb ); -define def_MBARPC0Q_cfg_pup_avail_dly20 = ( def_1600_2gb ||def_1600_4gb ||def_1600_8gb ||def_1600_2gb_ddr4 ||def_1600_4gb_ddr4 ||def_1600_8gb_ddr4 ); -define def_MBARPC0Q_cfg_pup_avail_dly23 = ( def_1866_2gb ||def_1866_4gb ||def_1866_8gb ||def_1866_2gb_ddr4 ||def_1866_4gb_ddr4 ||def_1866_8gb_ddr4 ); -define def_MBARPC0Q_cfg_pup_avail_dly26 = ( def_2133_2gb_ddr4 ||def_2133_4gb_ddr4 ||def_2133_8gb_ddr4 ); -define def_MBARPC0Q_cfg_pup_avail_dly29 = ( def_2400_2gb_ddr4 ||def_2400_4gb_ddr4 ||def_2400_8gb_ddr4 ); - - -## MCBIST address map defines -## cols -define def_mcb_addr_col13_29 = (ATTR_EFF_DRAM_COLS == 12); -define def_mcb_addr_unset_col13 = ((ATTR_EFF_DRAM_COLS == 10) || (ATTR_EFF_DRAM_COLS == 11)); - -define def_mcb_addr_col11_30 = ((ATTR_EFF_DRAM_COLS == 11) || (ATTR_EFF_DRAM_COLS == 12)); -define def_mcb_addr_unset_col11 = (ATTR_EFF_DRAM_COLS == 10); - - -## banks -define def_mcb_addr_bank3_27 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16)); -define def_mcb_addr_bank3_26 = ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16)); -define def_mcb_addr_bank3_25 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16)); -define def_mcb_addr_unset_bank3 = (ATTR_EFF_DRAM_BANKS == 8); - -define def_mcb_addr_bank2_28 = ((ATTR_EFF_DRAM_COLS == 10) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); -define def_mcb_addr_bank2_27 = ((ATTR_EFF_DRAM_COLS == 11) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); -define def_mcb_addr_bank2_26 = ((ATTR_EFF_DRAM_COLS == 12) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); - -define def_mcb_addr_bank1_29 = ((ATTR_EFF_DRAM_COLS == 10) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); -define def_mcb_addr_bank1_28 = ((ATTR_EFF_DRAM_COLS == 11) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); -define def_mcb_addr_bank1_27 = ((ATTR_EFF_DRAM_COLS == 12) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); - -define def_mcb_addr_bank0_30 = ((ATTR_EFF_DRAM_COLS == 10) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); -define def_mcb_addr_bank0_29 = ((ATTR_EFF_DRAM_COLS == 11) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); -define def_mcb_addr_bank0_28 = ((ATTR_EFF_DRAM_COLS == 12) && ((ATTR_EFF_DRAM_BANKS == 16) || (ATTR_EFF_DRAM_BANKS == 8))); - -## Rows -define def_mcb_addr_row16_11 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17)); -define def_mcb_addr_row16_10 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row16_9 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row16_8 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17)); -define def_mcb_addr_unset_row16 = ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16)); - -define def_mcb_addr_row15_12 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row15_11 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row15_10 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row15_9 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_unset_row15 = ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15)); - -define def_mcb_addr_row14_13 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row14_12 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row14_11 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row14_10 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_unset_row14 = (ATTR_EFF_DRAM_ROWS == 14); - -define def_mcb_addr_row13_14 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row13_13 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row13_12 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row13_11 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row12_15 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row12_14 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row12_13 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row12_12 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row11_16 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row11_15 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row11_14 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row11_13 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row10_17 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row10_16 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row10_15 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row10_14 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row9_18 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row9_17 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row9_16 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row9_15 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row8_19 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row8_18 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row8_17 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row8_16 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row7_20 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row7_19 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row7_18 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row7_17 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row6_21 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row6_20 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row6_19 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row6_18 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row5_22 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row5_21 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row5_20 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row5_19 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row4_23 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row4_22 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row4_21 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row4_20 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row3_24 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row3_23 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row3_22 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row3_21 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row2_25 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row2_24 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row2_23 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row2_22 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row1_26 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row1_25 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row1_24 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row1_23 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row0_27 = ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row0_26 = (((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row0_25 = (((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))) ||((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17)))); -define def_mcb_addr_row0_24 = ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && ((ATTR_EFF_DRAM_ROWS == 14) || (ATTR_EFF_DRAM_ROWS == 15) || (ATTR_EFF_DRAM_ROWS == 16) || (ATTR_EFF_DRAM_ROWS == 17))); - - -define def_mcb_srank0_unset = ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 8); -define def_mcb_srank1_unset = ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 4); -define def_mcb_srank2_unset = ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2); - -## SRANKS -############################################# SRANK bits Col = 10 , banks = 16 -define def_mcb_addr_col10_bnk16_srank2_12 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col10_bnk16_srank1_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col10_bnk16_srank0_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col10_bnk16_srank2_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col10_bnk16_srank1_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col10_bnk16_srank0_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col10_bnk16_srank2_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col10_bnk16_srank1_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col10_bnk16_srank0_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col10_bnk16_srank2_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_col10_bnk16_srank1_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_col10_bnk16_srank0_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -############################################# SRANK bits Col = 10 , banks = 8 -define def_mcb_addr_col10_bnk8_srank2_13 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col10_bnk8_srank1_12 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col10_bnk8_srank0_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col10_bnk8_srank2_12 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col10_bnk8_srank1_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col10_bnk8_srank0_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col10_bnk8_srank2_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col10_bnk8_srank1_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col10_bnk8_srank0_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col10_bnk8_srank2_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_col10_bnk8_srank1_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_col10_bnk8_srank0_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); - -############################################# SRANK bits Col = 11 , banks = 16 -define def_mcb_addr_col11_bnk16_srank2_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col11_bnk16_srank1_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col11_bnk16_srank0_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col11_bnk16_srank2_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col11_bnk16_srank1_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col11_bnk16_srank0_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col11_bnk16_srank2_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col11_bnk16_srank1_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col11_bnk16_srank0_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col11_bnk16_srank2_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_col11_bnk16_srank1_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_col11_bnk16_srank0_6 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -############################################# SRANK bits Col = 11 , banks = 8 -define def_mcb_addr_col11_bnk8_srank2_12 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col11_bnk8_srank1_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col11_bnk8_srank0_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col11_bnk8_srank2_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col11_bnk8_srank1_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col11_bnk8_srank0_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col11_bnk8_srank2_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col11_bnk8_srank1_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col11_bnk8_srank0_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col11_bnk8_srank2_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_col11_bnk8_srank1_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_col11_bnk8_srank0_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); - -############################################# SRANK bits Col = 12 , banks = 16 -define def_mcb_addr_col12_bnk16_srank2_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col12_bnk16_srank1_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col12_bnk16_srank0_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col12_bnk16_srank2_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col12_bnk16_srank1_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col12_bnk16_srank0_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col12_bnk16_srank2_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col12_bnk16_srank1_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col12_bnk16_srank0_6 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col12_bnk16_srank2_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_col12_bnk16_srank1_6 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_col12_bnk16_srank0_5 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -############################################# SRANK bits Col = 12 , banks = 8 -define def_mcb_addr_col12_bnk8_srank2_11 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col12_bnk8_srank1_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col12_bnk8_srank0_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_col12_bnk8_srank2_10 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col12_bnk8_srank1_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col12_bnk8_srank0_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_col12_bnk8_srank2_9 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col12_bnk8_srank1_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col12_bnk8_srank0_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_col12_bnk8_srank2_8 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 1) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_col12_bnk8_srank1_7 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 3) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_col12_bnk8_srank0_6 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) > 7) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8) && (ATTR_EFF_DRAM_ROWS == 17))); - -### MRANKS - -define def_mcb_mrank1_unset = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 8); -define def_mcb_mrank2_unset = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 4); -define def_mcb_mrank3_unset = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 0); - -############################################# MRANK bits Col = 10 , banks = 16 -define def_mcb_addr_row14_col10_bnk16_mrank3_12 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk16_mrank2_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk16_mrank1_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col10_bnk16_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk16_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk16_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col10_bnk16_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk16_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk16_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col10_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row15_col10_bnk16_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk16_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk16_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col10_bnk16_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk16_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk16_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col10_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col10_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row16_col10_bnk16_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk16_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk16_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col10_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col10_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col10_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row17_col10_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col10_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col10_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col10_bnk16_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk16_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk16_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -############################################# MRANK bits Col = 10 , banks = 8 -define def_mcb_addr_row14_col10_bnk8_mrank3_13 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk8_mrank2_12 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk8_mrank1_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col10_bnk8_mrank3_12 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk8_mrank2_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk8_mrank1_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col10_bnk8_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk8_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk8_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col10_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col10_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row15_col10_bnk8_mrank3_12 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk8_mrank2_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk8_mrank1_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col10_bnk8_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk8_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk8_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col10_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col10_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col10_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); - - -define def_mcb_addr_row16_col10_bnk8_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk8_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk8_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col10_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col10_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col10_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col10_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row17_col10_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col10_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col10_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col10_bnk8_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk8_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col10_bnk8_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 10) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); - -############################################# MRANK bits Col = 11 , banks = 16 -define def_mcb_addr_row14_col11_bnk16_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk16_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk16_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col11_bnk16_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk16_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk16_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col11_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col11_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row15_col11_bnk16_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk16_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk16_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col11_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col11_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col11_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row16_col11_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col11_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col11_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col11_bnk16_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk16_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk16_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row17_col11_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col11_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col11_bnk16_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk16_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk16_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col11_bnk16_mrank3_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk16_mrank2_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk16_mrank1_3 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -############################################# MRANK bits Col = 11 , banks = 8 -define def_mcb_addr_row14_col11_bnk8_mrank3_12 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk8_mrank2_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk8_mrank1_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col11_bnk8_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk8_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk8_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col11_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col11_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col11_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row15_col11_bnk8_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk8_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk8_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col11_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col11_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col11_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col11_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row16_col11_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col11_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col11_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col11_bnk8_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk8_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col11_bnk8_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row17_col11_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col11_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col11_bnk8_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk8_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk8_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col11_bnk8_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk8_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col11_bnk8_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 11) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); - -############################################# MRANK bits Col = 12 , banks = 16 -define def_mcb_addr_row14_col12_bnk16_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk16_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk16_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col12_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col12_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col12_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row15_col12_bnk16_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk16_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk16_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col12_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col12_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col12_bnk16_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk16_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk16_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row16_col12_bnk16_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk16_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk16_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col12_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col12_bnk16_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk16_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk16_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col12_bnk16_mrank3_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk16_mrank2_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk16_mrank1_3 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row17_col12_bnk16_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk16_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk16_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col12_bnk16_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk16_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk16_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col12_bnk16_mrank3_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk16_mrank2_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk16_mrank1_3 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col12_bnk16_mrank3_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk16_mrank2_3 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk16_mrank1_2 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 16) && (ATTR_EFF_DRAM_ROWS == 17))); - -############################################# MRANK bits Col = 12 , banks = 8 -define def_mcb_addr_row14_col12_bnk8_mrank3_11 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk8_mrank2_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk8_mrank1_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col12_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col12_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row14_col12_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); -define def_mcb_addr_row14_col12_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 14))); - -define def_mcb_addr_row15_col12_bnk8_mrank3_10 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk8_mrank2_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk8_mrank1_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col12_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col12_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row15_col12_bnk8_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk8_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); -define def_mcb_addr_row15_col12_bnk8_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 15))); - -define def_mcb_addr_row16_col12_bnk8_mrank3_9 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk8_mrank2_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk8_mrank1_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col12_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col12_bnk8_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk8_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk8_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row16_col12_bnk8_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk8_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); -define def_mcb_addr_row16_col12_bnk8_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 16))); - -define def_mcb_addr_row17_col12_bnk8_mrank3_8 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk8_mrank2_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk8_mrank1_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col12_bnk8_mrank3_7 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk8_mrank2_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk8_mrank1_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==2) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col12_bnk8_mrank3_6 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk8_mrank2_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk8_mrank1_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==4) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); - -define def_mcb_addr_row17_col12_bnk8_mrank3_5 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 0) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk8_mrank2_4 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 3) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); -define def_mcb_addr_row17_col12_bnk8_mrank1_3 = ((ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0] > 7) && ((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) ==8) && ((ATTR_EFF_DRAM_COLS == 12) && (ATTR_EFF_DRAM_BANKS == 8 ) && (ATTR_EFF_DRAM_ROWS == 17))); - -# ADDRESS setup for different SCHMOO setting -define def_mcb_addr_total28_max28 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 28 )); -define def_mcb_addr_total28_max29 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 28 )); -define def_mcb_addr_total28_max30 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 28 )); -define def_mcb_addr_total28_max31 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 28 )); - -define def_mcb_addr_total27_max27 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 27 )); -define def_mcb_addr_total27_max28 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 27 )); -define def_mcb_addr_total27_max29 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 27 )); -define def_mcb_addr_total27_max30 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 27 )); - -define def_mcb_addr_total26_max26 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 26 )); -define def_mcb_addr_total26_max27 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 26 )); -define def_mcb_addr_total26_max28 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 26 )); -define def_mcb_addr_total26_max29 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 26 )); - -define def_mcb_addr_total25_max25 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 25 )); -define def_mcb_addr_total25_max26 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 25 )); -define def_mcb_addr_total25_max27 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 25 )); -define def_mcb_addr_total25_max28 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 25 )); - -define def_mcb_addr_total24_max24 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 24 )); -define def_mcb_addr_total24_max25 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 24 )); -define def_mcb_addr_total24_max26 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 24 )); -define def_mcb_addr_total24_max27 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 24 )); - -define def_mcb_addr_total23_max23 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 23 )); -define def_mcb_addr_total23_max24 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 23 )); -define def_mcb_addr_total23_max25 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 23 )); -define def_mcb_addr_total23_max26 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 23 )); - -define def_mcb_addr_total22_max22 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) < 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 )); -define def_mcb_addr_total22_max23 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 2) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 )); -define def_mcb_addr_total22_max24 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 4) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 )); -define def_mcb_addr_total22_max25 = (((ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] - ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM[0][0]) == 8) && (((ATTR_EFF_DRAM_COLS - 3) + (ATTR_EFF_DRAM_BANKS/4) + ATTR_EFF_DRAM_ROWS) == 22 )); - -####################################### -# MBA01_MBA_MBAREFAQ Base Address: 0x03010436 -# MBA23_MBA_MBAREFAQ Base Address: 0x03010c36 -####################################### - -scom 0x03010436 { - bits , scom_data , ATTR_FUNCTIONAL, expr; -# 0:63 , 0xE1FFFFC421020C00 , 1 , any; #Enable Dynamic Refresh Avoidance with coef2 - 0:63 , 0x6591B48421021400 , 1 , any; #Old Default settings to turn off Dynamic refresh avoidance -} -####################################### -# MBA01_MBA_RRQ0Q Base Address: 0x0301040E -# MBA23_MBA_RRQ0Q Base Address: 0x03010C0E -####################################### - -scom 0x0301040E { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 57 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_PAGE_MODE_FOR_RRQ == 1); # Enable Page Mode for the Read Reorder Queue -} - -#Register Name Final Arb Parms -#Mnemonic MBA_FARB0Q -#Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use -#Description FARB command control -#1. FARB0 bit 38: cfg_parity_after_cmd -# - set this bit if DDR3 and (RDIMM or LDRIMM) -# - clear this bit if DDR4 and (RDIMM or LDRIMM) -#2. FARB0 bit 60: cfg_ignore_rcd_parity_err -# - clear this bit if (RDIMM or LDRIMM) -#3. FARB0 bit 61: cfg_enable_rcd_rw_retry -# - set this bit if (RDIMM or LDRIMM) - -scom 0x03010413 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 38 , 0b1 , 1 , (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_GEN == 1)); - 38 , 0b0 , 1 , (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_GEN == 2)); - 60 , 0b0 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)); - 61 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)); -} - - -####################################### -#MBA01 MBASRQ Base Address: 0x03010416 -#MBA23 MBASRQ Base Address: 0x03010C16 -####################################### -# -#Register Name N/M Throttling Control -#Mnemonic MBA_FARB3Q -#Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use -#Description N/M throttling control (Centaur only) -# 0:14 cfg_nm_n_per_mba MSS_MEM_THROTTLE_NUMERATOR_PER_MBA -# 15:30 cfg_nm_n_per_chip MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP -# 31:44 cfg_nm_m MSS_MEM_THROTTLE_DENOMINATOR -# 51 cfg_nm_per_slot_enabled 1 -# 52 cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else -#cfg_nm_ras_weight, bits 45:47 = ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT -#cfg_nm_cas_weight, bits 48:50 = ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT - - - -scom 0x03010416 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:14 , ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA , 1 , any; # cfg_nm_n_per_mba MSS_MEM_THROTTLE_NUMERATOR_PER_MBA - 15:30 , ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP , 1 , any; # cfg_nm_n_per_chip MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP - 31:44 , ATTR_MSS_MEM_THROTTLE_DENOMINATOR , 1 , any; # cfg_nm_m MSS_MEM_THROTTLE_DENOMINATOR - 45:47 , ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT , 1 , any; # cfg_nm_ras_weight - 48:50 , ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT , 1 , any; # cfg_nm_cas_weight - 51 , 0b0 , 1 , (ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1); # cfg_nm_per_slot_enabled Set to 0 for CDIMM, Set to 1 for everything else - 51 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 0)) || (ATTR_EFF_DIMM_TYPE == 3)); # cfg_nm_per_slot_enabled Set to 0 for CDIMM, Set to 1 for everything else - 52 , 0b0 , 1 , (ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 1); # cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else - 52 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 0)) || (ATTR_EFF_DIMM_TYPE == 3)); # cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else - 53 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_NM_CHANGE_AFTER_SYNC == 1); # cfg_nm_change_after_sync -} - - -#Register Name N/M Throttling Control -#Mnemonic MBA_FARB4Q -#Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use -#Description N/M throttling control (Centaur only) -#MBA_FARB4Q(0:1) cfg_rhmr_en 01 Track only (only FIRs will go off, signaling when a block would have occurred) -#MBA_FARB4Q(2) cfg_rhmr_secondary_en 0 Secondary Structure disabled (this is for repair sequence) -#MBA_FARB4Q(3) cfg_rhmr_hash_swizzle_en 0 Disable swizzling hash (so we don't switch which rows correspond to which counters) -#MBA_FARB4Q(4:9) Reserved 000000 Don't Care -#MBA_FARB4Q(10:11) cfg_rhmr_decrement_weight 01 Decrement by 1 (minimum weight) -#MBA_FARB4Q(12:18) cfg_rhmr_primary_decr_intv 1111111 Slowest rate of decrements. Once ever 2^14 or 16K DRAM clocks* -#MBA_FARB4Q(12:18) cfg_rhmr_primary_decr_intv 0000011 decrement every 512 DRAM clocks for 100K accesses to hash group -#MBA_FARB4Q(19:25) cfg_rhmr_secondary_decr_intv 0000000 Don't care -#MBA_FARB4Q(26) cfg_rhmr_sim_en 0 Disable sim mode -# -- bits 27:41 (cfg_emer_n) = ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP -# -- bits 42:55 (cfg_emer_m) = ATTR_MRW_MEM_THROTTLE_DENOMINATOR -#*I think this corresponds to protecting a row from being hammered 64K times. - -scom 0x03010417 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:1 , 0b00 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); # disable row hammer permanently eventhough attribute says enable it - 2 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); - 3 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); - 4:9 , 0b000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); - 10:11 , 0b01 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); - 12:18 , 0b0000011 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); - 19:25 , 0b0000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); - 26 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1); - 27:41 , SYS.ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, 1 , (ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE == 1); - 42:55 , SYS.ATTR_MRW_MEM_THROTTLE_DENOMINATOR , 1 , (ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE == 1); -} - - -# ATTR_EFF_DIMM_TYPE -# CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3 - -################################### -# TRACE_TRCTRL_CONFIG MBA01 Trace Control Configuration Register -# -# HW259719 - lcl_clk_gate_ctrl needs to be turned on and left on -# DD2 fixed ONLY -################################### - -scom 0x03010882 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:63 , 0x000C000000000000 , 1 , (CENTAUR.ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl -# 12:13 , 0b11 , 1 , (CENTAUR.ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl -} - -################################### -# Turn on DDR PHY clks -################################### -# Name = MBA01.MBA_MCBIST.SCOMFIR.CCS_MODEQ_Q(0:63) (scomdef) -# Turn on DDR phy clk p and n - -scom 0x030106A7 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 4:5 , 0b01 , 1 , any; # ddr_dphy_nclk 00 = off , 01 = on - 6:7 , 0b10 , 1 , any; # ddr_dphy_pclk 00 = off , 10 = on - 51 , 0b0 , 1 , ATTR_EFF_DRAM_GEN != 2; # set ACT signal to 0 for DDR3 - 51 , 0b1 , 1 , ATTR_EFF_DRAM_GEN == 2; # set ACT signal to 1 for DDR4 - 52 , 0b1 , 1 , any; # RAS# high - 53 , 0b1 , 1 , any; # CAS# high - 54 , 0b1 , 1 , any; # WE# high -} - - -################################### -# MBA chip select mapping tables # -################################### - -# Name = MBA01.FARB.FARB_CS (scomdef) -# MBA_FARB1Q Slot0, Master Rank 0/2 chip select programming -# -scom 0x03010414 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:5 , 0b011100, 1 , (def_C3b == 1); # cfg_M0S0_cs - 0:5 , 0b011100, 1 , (def_C3c == 1); # cfg_M0S0_cs - 0:5 , 0b010000, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S0_cs - 0:5 , 0b010100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S0_cs - 0:5 , 0b011100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S0_cs - 0:5 , 0b010000, 1 , (def_IS3b_IS7b == 1); # cfg_M0S0_cs - 0:5 , 0b010000, 1 , (def_IS5D == 1); # cfg_M0S0_cs - 0:5 , 0b010000, 1 , (def_IS7C == 1); # cfg_M0S0_cs - 0:5 , 0b011100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S0_cs - 6:11 , 0b101100, 1 , (def_C3b == 1); # cfg_M0S1_cs - 6:11 , 0b101100, 1 , (def_C3c == 1); # cfg_M0S1_cs - 6:11 , 0b011000, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S1_cs - 6:11 , 0b011100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S1_cs - 6:11 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S1_cs - 6:11 , 0b011000, 1 , (def_IS3b_IS7b == 1); # cfg_M0S1_cs - 6:11 , 0b011000, 1 , (def_IS5D == 1); # cfg_M0S1_cs - 6:11 , 0b011000, 1 , (def_IS7C == 1); # cfg_M0S1_cs - 6:11 , 0b110100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S1_cs - 12:17 , 0b110100, 1 , (def_C3b == 1); # cfg_M0S2_cs - 12:17 , 0b110100, 1 , (def_C3c == 1); # cfg_M0S2_cs - 12:17 , 0b010100, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S2_cs - 12:17 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S2_cs - 12:17 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S2_cs - 12:17 , 0b010100, 1 , (def_IS3b_IS7b == 1); # cfg_M0S2_cs - 12:17 , 0b010100, 1 , (def_IS5D == 1); # cfg_M0S2_cs - 12:17 , 0b010100, 1 , (def_IS7C == 1); # cfg_M0S2_cs - 12:17 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S2_cs - 18:23 , 0b111000, 1 , (def_C3b == 1); # cfg_M0S3_cs - 18:23 , 0b111000, 1 , (def_C3c == 1); # cfg_M0S3_cs - 18:23 , 0b011100, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S3_cs - 18:23 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S3_cs - 18:23 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S3_cs - 18:23 , 0b011100, 1 , (def_IS3b_IS7b == 1); # cfg_M0S3_cs - 18:23 , 0b011100, 1 , (def_IS5D == 1); # cfg_M0S3_cs - 18:23 , 0b011100, 1 , (def_IS7C == 1); # cfg_M0S3_cs - 18:23 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S3_cs - 24:29 , 0b111100, 1 , (def_C3b == 1); # cfg_M0S4_cs - 24:29 , 0b011110, 1 , (def_C3c == 1); # cfg_M0S4_cs - 24:29 , 0b010001, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S4_cs - 24:29 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S4_cs - 24:29 , 0b110100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S4_cs - 24:29 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M0S4_cs - 24:29 , 0b100000, 1 , (def_IS5D == 1); # cfg_M0S4_cs - 24:29 , 0b010010, 1 , (def_IS7C == 1); # cfg_M0S4_cs - 24:29 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S4_cs - 30:35 , 0b111100, 1 , (def_C3b == 1); # cfg_M0S5_cs - 30:35 , 0b101110, 1 , (def_C3c == 1); # cfg_M0S5_cs - 30:35 , 0b011001, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S5_cs - 30:35 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S5_cs - 30:35 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S5_cs - 30:35 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M0S5_cs - 30:35 , 0b101000, 1 , (def_IS5D == 1); # cfg_M0S5_cs - 30:35 , 0b011010, 1 , (def_IS7C == 1); # cfg_M0S5_cs - 30:35 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S5_cs - 36:41 , 0b111100, 1 , (def_C3b == 1); # cfg_M0S6_cs - 36:41 , 0b110110, 1 , (def_C3c == 1); # cfg_M0S6_cs - 36:41 , 0b010101, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S6_cs - 36:41 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S6_cs - 36:41 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S6_cs - 36:41 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M0S6_cs - 36:41 , 0b100100, 1 , (def_IS5D == 1); # cfg_M0S6_cs - 36:41 , 0b010110, 1 , (def_IS7C == 1); # cfg_M0S6_cs - 36:41 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S6_cs - 42:47 , 0b111100, 1 , (def_C3b == 1); # cfg_M0S7_cs - 42:47 , 0b111010, 1 , (def_C3c == 1); # cfg_M0S7_cs - 42:47 , 0b011101, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M0S7_cs - 42:47 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M0S7_cs - 42:47 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M0S7_cs - 42:47 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M0S7_cs - 42:47 , 0b101100, 1 , (def_IS5D == 1); # cfg_M0S7_cs - 42:47 , 0b011110, 1 , (def_IS7C == 1); # cfg_M0S7_cs - 42:47 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M0S7_cs - 48:51 , 0b1111, 1 , (def_C3b == 1); # cfg_cs_s0_mask - 48:51 , 0b1111, 1 , (def_C3c == 1); # cfg_cs_s0_mask - 48:51 , 0b1100, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_cs_s0_mask - 48:51 , 0b1101, 1 , (def_C4A_ddr4 == 1); # cfg_cs_s0_mask - 48:51 , 0b1111, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_cs_s0_mask - 48:51 , 0b1100, 1 , (def_IS3b_IS7b == 1); # cfg_cs_s0_mask - 48:51 , 0b1100, 1 , (def_IS5D == 1); # cfg_cs_s0_mask - 48:51 , 0b1100, 1 , (def_IS7C == 1); # cfg_cs_s0_mask - 48:51 , 0b1111, 1 , (def_IS7a_C4a_C3a == 1); # cfg_cs_s0_mask - 52 , 0b0 , 1 , (def_C3b == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR - 52 , 0b0 , 1 , (def_C3c == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR - 52 , 0b0 , 1 , (def_C3c_C4C_ddr4 == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR - 52 , 0b0 , 1 , (def_C4A_ddr4 == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR - 52 , 0b0 , 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR - 52 , 0b0 , 1 , (def_IS3b_IS7b == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR - 52 , 0b1 , 1 , (def_IS5D == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR - 52 , 0b0 , 1 , (def_IS7C == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR - 52 , 0b0 , 1 , (def_IS7a_C4a_C3a == 1); # MBA_FARB1Q_CFG_S0_DIS_SMDR -} - - -# MBA_FARB2Q Slot0, Master Rank 1/3 chip select programming -# -scom 0x03010415 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:5 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S0_cs - 0:5 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S0_cs - 0:5 , 0b100000, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S0_cs - 0:5 , 0b100100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S0_cs - 0:5 , 0b101100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S0_cs - 0:5 , 0b100000, 1 , (def_IS3b_IS7b == 1); # cfg_M1S0_cs - 0:5 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S0_cs - 0:5 , 0b100000, 1 , (def_IS7C == 1); # cfg_M1S0_cs - 0:5 , 0b101100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S0_cs - 6:11 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S1_cs - 6:11 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S1_cs - 6:11 , 0b101000, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S1_cs - 6:11 , 0b101100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S1_cs - 6:11 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S1_cs - 6:11 , 0b101000, 1 , (def_IS3b_IS7b == 1); # cfg_M1S1_cs - 6:11 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S1_cs - 6:11 , 0b101000, 1 , (def_IS7C == 1); # cfg_M1S1_cs - 6:11 , 0b111000, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S1_cs - 12:17 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S2_cs - 12:17 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S2_cs - 12:17 , 0b100100, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S2_cs - 12:17 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S2_cs - 12:17 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S2_cs - 12:17 , 0b100100, 1 , (def_IS3b_IS7b == 1); # cfg_M1S2_cs - 12:17 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S2_cs - 12:17 , 0b100100, 1 , (def_IS7C == 1); # cfg_M1S2_cs - 12:17 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S2_cs - 18:23 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S3_cs - 18:23 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S3_cs - 18:23 , 0b101100, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S3_cs - 18:23 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S3_cs - 18:23 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S3_cs - 18:23 , 0b101100, 1 , (def_IS3b_IS7b == 1); # cfg_M1S3_cs - 18:23 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S3_cs - 18:23 , 0b101100, 1 , (def_IS7C == 1); # cfg_M1S3_cs - 18:23 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S3_cs - 24:29 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S4_cs - 24:29 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S4_cs - 24:29 , 0b100001, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S4_cs - 24:29 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S4_cs - 24:29 , 0b111000, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S4_cs - 24:29 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M1S4_cs - 24:29 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S4_cs - 24:29 , 0b100010, 1 , (def_IS7C == 1); # cfg_M1S4_cs - 24:29 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S4_cs - 30:35 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S5_cs - 30:35 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S5_cs - 30:35 , 0b101001, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S5_cs - 30:35 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S5_cs - 30:35 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S5_cs - 30:35 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M1S5_cs - 30:35 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S5_cs - 30:35 , 0b101010, 1 , (def_IS7C == 1); # cfg_M1S5_cs - 30:35 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S5_cs - 36:41 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S6_cs - 36:41 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S6_cs - 36:41 , 0b100101, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S6_cs - 36:41 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S6_cs - 36:41 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S6_cs - 36:41 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M1S6_cs - 36:41 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S6_cs - 36:41 , 0b100110, 1 , (def_IS7C == 1); # cfg_M1S6_cs - 36:41 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S6_cs - 42:47 , 0b111100, 1 , (def_C3b == 1); # cfg_M1S7_cs - 42:47 , 0b111100, 1 , (def_C3c == 1); # cfg_M1S7_cs - 42:47 , 0b101101, 1 , (def_C3c_C4C_ddr4 == 1); # cfg_M1S7_cs - 42:47 , 0b111100, 1 , (def_C4A_ddr4 == 1); # cfg_M1S7_cs - 42:47 , 0b111100, 1 , (def_IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C == 1); # cfg_M1S7_cs - 42:47 , 0b111100, 1 , (def_IS3b_IS7b == 1); # cfg_M1S7_cs - 42:47 , 0b111100, 1 , (def_IS5D == 1); # cfg_M1S7_cs - 42:47 , 0b101110, 1 , (def_IS7C == 1); # cfg_M1S7_cs - 42:47 , 0b111100, 1 , (def_IS7a_C4a_C3a == 1); # cfg_M1S7_cs -} - - - -########################### -# MBA timer values # -########################### - -# eventually these timer settings will need to be generated from attributes -# but for the 2/12 initfile these are coded the same as the ddr3_1600_10_10_10_2N dial for vbu testing - -# MBA_TMR0Q mba01 timer settings -#< B0.C0.M00A.CENTAUR.MBU.MBA23.MBA_SRQ.MBA_TMR0Q(0:63) = 0x4479976DB5447445 -#> B0.C0.M00A.CENTAUR.MBU.MBA23.MBA_SRQ.MBA_TMR0Q(0:63) = 0x4479996DB5447445 -# -scom 0x0301040B { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:3 , 0b0100 + def_margin2 , 1 , any; # RRSMSR_dly is 4 for all cfgs 1 D - 4:7 , 0b0100 + def_margin2 , 1 , any; # RRSMDR_dly is 4 for all cfgs 2 D - 8:11 , 0b0111 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 1066) || (CENTAUR.ATTR_MSS_FREQ == 1333) || (CENTAUR.ATTR_MSS_FREQ == 1600); # RRDM_dly 3 D - 8:11 , 0b1000 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133); # RRDM_dly 3 D - 8:11 , 0b1001 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 2400); # RRDM_dly 3 D -# fails will 0 margin 12:15 - 12:15 , 0b0111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWSMSR_dly 4 - 12:15 , 0b1000 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys8 == 1); # RWSMSR_dly 4 - 12:15 , 0b1001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys9 == 1); # RWSMSR_dly 4 - 12:15 , 0b1010 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys10 == 1); # RWSMSR_dly 4 - 12:15 , 0b1011 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys11 == 1); # RWSMSR_dly 4 - 12:15 , 0b1100 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys12 == 1); # RWSMSR_dly 4 - 12:15 , 0b1101 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys13 == 1); # RWSMSR_dly 4 - 12:15 , 0b1110 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys14 == 1); # RWSMSR_dly 4 - 12:15 , 0b1111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys15 == 1); # RWSMSR_dly 4 - 16:19 , 0b0111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWSMDR_dly 5 - 16:19 , 0b1000 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys8 == 1); # RWSMDR_dly 5 - 16:19 , 0b1001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys9 == 1); # RWSMDR_dly 5 - 16:19 , 0b1010 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys10 == 1); # RWSMDR_dly 5 - 16:19 , 0b1011 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys11 == 1); # RWSMDR_dly 5 - 16:19 , 0b1100 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys12 == 1); # RWSMDR_dly 5 - 16:19 , 0b1101 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys13 == 1); # RWSMDR_dly 5 - 16:19 , 0b1110 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys14 == 1); # RWSMDR_dly 5 - 16:19 , 0b1111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys15 == 1); # RWSMDR_dly 5 - 20:23 , 0b0111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys7 == 1); # RWDM_dly 6 - 20:23 , 0b1000 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys8 == 1); # RWDM_dly 6 - 20:23 , 0b1001 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys9 == 1); # RWDM_dly 6 - 20:23 , 0b1010 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys10 == 1); # RWDM_dly 6 - 20:23 , 0b1011 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys11 == 1); # RWDM_dly 6 - 20:23 , 0b1100 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys12 == 1); # RWDM_dly 6 - 20:23 , 0b1101 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys13 == 1); # RWDM_dly 6 - 20:23 , 0b1110 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys14 == 1); # RWDM_dly 6 - 20:23 , 0b1111 + def_margin1 , 1 , (def_mba_tmr0q_RW_dlys15 == 1); # RWDM_dly 6 - 24:29 , 0b010011 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys19 == 1); # WRSMSR_dly 7 - 24:29 , 0b010100 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys20 == 1); # WRSMSR_dly 7 - 24:29 , 0b010101 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys21 == 1); # WRSMSR_dly 7 - 24:29 , 0b010111 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys23 == 1); # WRSMSR_dly 7 - 24:29 , 0b011000 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys24 == 1); # WRSMSR_dly 7 - 24:29 , 0b011001 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys25 == 1); # WRSMSR_dly 7 - 24:29 , 0b011010 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys26 == 1); # WRSMSR_dly 7 - 24:29 , 0b011011 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys27 == 1); # WRSMSR_dly 7 - 24:29 , 0b011100 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys28 == 1); # WRSMSR_dly 7 - 24:29 , 0b011101 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys29 == 1); # WRSMSR_dly 7 - 24:29 , 0b011110 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys30 == 1); # WRSMSR_dly 7 - 24:29 , 0b011111 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys31 == 1); # WRSMSR_dly 7 - 24:29 , 0b100000 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys32 == 1); # WRSMSR_dly 7 - 24:29 , 0b100001 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys33 == 1); # WRSMSR_dly 7 - 30:35 , 0b010111 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys23 == 1); # WRSMDR_dly 8 - 30:35 , 0b011000 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys24 == 1); # WRSMDR_dly 8 - 30:35 , 0b011001 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys25 == 1); # WRSMDR_dly 8 - 30:35 , 0b011010 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys26 == 1); # WRSMDR_dly 8 - 30:35 , 0b011011 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys27 == 1); # WRSMDR_dly 8 - 30:35 , 0b011100 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys28 == 1); # WRSMDR_dly 8 - 30:35 , 0b011101 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys29 == 1); # WRSMDR_dly 8 - 30:35 , 0b011110 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys30 == 1); # WRSMDR_dly 8 - 30:35 , 0b011111 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys31 == 1); # WRSMDR_dly 8 - 30:35 , 0b100000 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys32 == 1); # WRSMDR_dly 8 - 30:35 , 0b100001 + def_margin2 , 1 , (def_mba_tmr0q_WRSM_dlys33 == 1); # WRSMDR_dly 8 - 36:39 , 0b0100 + def_margin2 , 1 , (def_mba_tmr0q_WRDM_dlys4 == 1); # WRDM_dly 9 - 36:39 , 0b0101 + def_margin2 , 1 , (def_mba_tmr0q_WRDM_dlys5 == 1); # WRDM_dly 9 - 36:39 , 0b0110 + def_margin2 , 1 , (def_mba_tmr0q_WRDM_dlys6 == 1); # WRDM_dly 9 - 36:39 , 0b0111 + def_margin2 , 1 , (def_mba_tmr0q_WRDM_dlys7 == 1); # WRDM_dly 9 - 36:39 , 0b1000 + def_margin2 , 1 , (def_mba_tmr0q_WRDM_dlys8 == 1); # WRDM_dly 9 - 40:43 , 0b0100 + def_margin2 , 1 , any; # WWSMSR_dly is 4 for all cfgs 10 D - 44:47 , 0b0100 + def_margin2 , 1 , any; # WWSMDR_dly is 4 for all cfgs 11 D - 48:51 , 0b0111 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 1066) || (CENTAUR.ATTR_MSS_FREQ == 1333) || (CENTAUR.ATTR_MSS_FREQ == 1600); # WWDM_dly 12 D - 48:51 , 0b1000 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133); # WWDM_dly 12 D - 48:51 , 0b1001 + def_margin2 , 1 , (CENTAUR.ATTR_MSS_FREQ == 2400); # WWDM_dly 12 D - 52:55 , 0b0100 + def_margin2 , 1 , any; # RROP_dly is 4 for all cfgs 13 D - 56:59 , 0b0100 + def_margin2 , 1 , any; # WWOP_dly is 4 for all cfgs 14 D - 60:63 , ATTR_EFF_DRAM_TRRD , 1 , any; # TMR0Q_Trrd -} - -# MBA_TMR1Q mba01 timer settings -# -scom 0x0301040C { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:6 , 0b0011010 , 1 , (def_mba_tmr1q_cfg_trap26 == 1); # cfg_trap 16 - 0:6 , 0b0011011 , 1 , (def_mba_tmr1q_cfg_trap27 == 1); # cfg_trap 16 - 0:6 , 0b0011100 , 1 , (def_mba_tmr1q_cfg_trap28 == 1); # cfg_trap 16 - 0:6 , 0b0100000 , 1 , (def_mba_tmr1q_cfg_trap32 == 1); # cfg_trap 16 - 0:6 , 0b0100001 , 1 , (def_mba_tmr1q_cfg_trap33 == 1); # cfg_trap 16 - 0:6 , 0b0100101 , 1 , (def_mba_tmr1q_cfg_trap37 == 1); # cfg_trap 16 - 0:6 , 0b0100110 , 1 , (def_mba_tmr1q_cfg_trap38 == 1); # cfg_trap 16 - 0:6 , 0b0100111 , 1 , (def_mba_tmr1q_cfg_trap39 == 1); # cfg_trap 16 - 0:6 , 0b0101000 , 1 , (def_mba_tmr1q_cfg_trap40 == 1); # cfg_trap 16 - 0:6 , 0b0101010 , 1 , (def_mba_tmr1q_cfg_trap42 == 1); # cfg_trap 16 - 0:6 , 0b0101011 , 1 , (def_mba_tmr1q_cfg_trap43 == 1); # cfg_trap 16 - 0:6 , 0b0101100 , 1 , (def_mba_tmr1q_cfg_trap44 == 1); # cfg_trap 16 - 0:6 , 0b0101110 , 1 , (def_mba_tmr1q_cfg_trap46 == 1); # cfg_trap 16 - 7:13 , 0b0011110 , 1 , (def_mba_tmr1q_cfg_twap30 == 1); # cfg_twap 17 - 7:13 , 0b0100000 , 1 , (def_mba_tmr1q_cfg_twap32 == 1); # cfg_twap 17 - 7:13 , 0b0100010 , 1 , (def_mba_tmr1q_cfg_twap34 == 1); # cfg_twap 17 - 7:13 , 0b0100101 , 1 , (def_mba_tmr1q_cfg_twap37 == 1); # cfg_twap 17 - 7:13 , 0b0100111 , 1 , (def_mba_tmr1q_cfg_twap39 == 1); # cfg_twap 17 - 7:13 , 0b0101010 , 1 , (def_mba_tmr1q_cfg_twap42 == 1); # cfg_twap 17 - 7:13 , 0b0101100 , 1 , (def_mba_tmr1q_cfg_twap44 == 1); # cfg_twap 17 - 7:13 , 0b0101110 , 1 , (def_mba_tmr1q_cfg_twap46 == 1); # cfg_twap 17 - 7:13 , 0b0110000 , 1 , (def_mba_tmr1q_cfg_twap48 == 1); # cfg_twap 17 - 7:13 , 0b0110001 , 1 , (def_mba_tmr1q_cfg_twap49 == 1); # cfg_twap 17 - 7:13 , 0b0110011 , 1 , (def_mba_tmr1q_cfg_twap51 == 1); # cfg_twap 17 - 7:13 , 0b0110101 , 1 , (def_mba_tmr1q_cfg_twap53 == 1); # cfg_twap 17 - 14:19 , 0b0001111 , 1 , (ATTR_EFF_DRAM_TFAW == 16); # cfg_tfaw # HW278587 if tfaw is 16 set it to 15 - 14:19 , ATTR_EFF_DRAM_TFAW, 1 , (ATTR_EFF_DRAM_TFAW != 16); # cfg_tfaw # otherwise use the attribute value - 20:23 , 0b0000 , 1 , (def_mba_tmr1q_RRSBG_dlys0 == 1); # RRSBG_dly 19 - 20:23 , 0b0101 , 1 , (def_mba_tmr1q_RRSBG_dlys5 == 1); # RRSBG_dly 19 - 20:23 , 0b0110 , 1 , (def_mba_tmr1q_RRSBG_dlys6 == 1); # RRSBG_dly 19 - 24:28 , 0b00000 , 1 , (def_mba_tmr1q_WRSBG_dlys0 == 1); # WRSBG_dly 20 - 24:28 , 0b11010 , 1 , (def_mba_tmr1q_WRSBG_dlys26 == 1); # WRSBG_dly 20 - 24:28 , 0b11011 , 1 , (def_mba_tmr1q_WRSBG_dlys27 == 1); # WRSBG_dly 20 - 24:28 , 0b11100 , 1 , (def_mba_tmr1q_WRSBG_dlys28 == 1); # WRSBG_dly 20 - 24:28 , 0b11101 , 1 , (def_mba_tmr1q_WRSBG_dlys29 == 1); # WRSBG_dly 20 - 24:28 , 0b11110 , 1 , (def_mba_tmr1q_WRSBG_dlys30 == 1); # WRSBG_dly 20 - 24:28 , 0b11111 , 1 , (def_mba_tmr1q_WRSBG_dlys31 == 1); # WRSBG_dly 20 -# 24:28 , 0b00000 , 1 , (def_mba_tmr1q_WRSBG_dlys33 == 1); # WRSBG_dly ## 2133 and 2400 DRM not supported 20 -# 24:28 , 0b00000 , 1 , (def_mba_tmr1q_WRSBG_dlys34 == 1); # WRSBG_dly ## 2133 and 2400 DRM not supported 20 -# 24:28 , 0b00000 , 1 , (def_mba_tmr1q_WRSBG_dlys36 == 1); # WRSBG_dly ## 2133 and 2400 DRM not supported 20 -# 24:28 , 0b00000 , 1 , (def_mba_tmr1q_WRSBG_dlys37 == 1); # WRSBG_dly ## 2133 and 2400 DRM not supported 20 -} - -# 1333Mbps RDIMM WL = Setting + 7 = CWL + AL[CL-1] + 1= 16 -#putscom cen.mba 301040a 30 6 001001 -ib -pall -call -# 1600Mbps RDIMM WL = Setting + 7 = CWL + AL[CL-1] + 1= 19 -#putscom cen.mba 301040a 30 6 001100 -ib -pall -call -# 1333Mbps CDIMM WL = Setting + 7 = CWL + AL[CL-1] = 15 -#putscom cen.mba 301040a 30 6 001000 -ib -pall -call -# 1600Mbps CDIMM WL = Setting + 7 = CWL + AL[CL-1] = 18 -#putscom cen.mba 301040a 30 6 001011 -ib -pall -call - -define def_WLO = ((ATTR_VPD_WLO[0] & 0x07) - (((ATTR_VPD_WLO[0] & 0x0F) >> 3) * 8)); -define def_WL_AL0 = (ATTR_EFF_DRAM_CWL - 7); -define def_WL_AL_MINUS1 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 1 - 7); -define def_WL_AL_MINUS2 = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 2 - 7); - -define def_RDODT_start_udimm = (ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_CWL); -define def_RDODT_start_rdimm = (ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_CWL); -define def_RDODT_start_lrdimm = (ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_CWL + 6); -define def_RDODT_duration = (5); - -# MBA_DSM0Q mba01 data state machine settings -#< B0.C0.M00A.CENTAUR.MBU.MBA01.MBA_SRQ.MBA_DSM0Q(0:63) = 0x0870466094038800 -#> B0.C0.M00A.CENTAUR.MBU.MBA01.MBA_SRQ.MBA_DSM0Q(0:63) = 0x08704660A4838800 - - -scom 0x0301040A { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:5 , def_RDODT_start_udimm , 1 , (ATTR_EFF_DIMM_TYPE == 2); # CFG_RODT_start_dly 21 - 0:5 , def_RDODT_start_rdimm , 1 , (ATTR_EFF_DIMM_TYPE == 1); # CFG_RODT_start_dly 21 - 0:5 , def_RDODT_start_lrdimm , 1 , (ATTR_EFF_DIMM_TYPE == 3); # CFG_RODT_start_dly 21 - 6:11 , def_RDODT_start_udimm + def_RDODT_duration , 1 , (ATTR_EFF_DIMM_TYPE == 2); # CFG_RODT_end_dly 22 - 6:11 , def_RDODT_start_rdimm + def_RDODT_duration , 1 , (ATTR_EFF_DIMM_TYPE == 1); # CFG_RODT_end_dly 22 - 6:11 , def_RDODT_start_lrdimm + def_RDODT_duration , 1 , (ATTR_EFF_DIMM_TYPE == 3); # CFG_RODT_end_dly 22 - 12:17 , 0b000000 , 1 , any; # CFG_WODT_start_dly is 0 for all cfgs 23 D - 18:23 , 0b000101 , 1 , any; # CFG_WODT_end_dly is 5 for all cfgs 24 D - 24:29 , 0b011000 , 1 , any; # wrdone_dly is 24 for all cfgs 25 D - 30:35 , def_WL_AL0 + def_WLO , 1 , (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 0)); # wrdata_dly - 30:35 , def_WL_AL0 , 1 , ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_DRAM_AL == 0)); # wrdata_dly - 30:35 , def_WL_AL_MINUS1 + def_WLO , 1 , (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 1)); # wrdata_dly - 30:35 , def_WL_AL_MINUS1 , 1 , ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_DRAM_AL == 1)); # wrdata_dly - 30:35 , def_WL_AL_MINUS2 + def_WLO , 1 , (((ATTR_EFF_DIMM_TYPE == 1) || (ATTR_EFF_DIMM_TYPE == 3)) && (ATTR_EFF_DRAM_AL == 2)); # wrdata_dly - 30:35 , def_WL_AL_MINUS2 , 1 , ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_DRAM_AL == 2)); # wrdata_dly - 36:41 , 0b001100 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly12 == 1); # rdtag_dly 27 - 36:41 , 0b001101 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly13 == 1); # rdtag_dly 27 - 36:41 , 0b001110 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly14 == 1); # rdtag_dly 27 - 36:41 , 0b001111 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly15 == 1); # rdtag_dly 27 - 36:41 , 0b010000 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly16 == 1); # rdtag_dly 27 - 36:41 , 0b010001 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly17 == 1); # rdtag_dly 27 - 36:41 , 0b010010 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly18 == 1); # rdtag_dly 27 - 36:41 , 0b010011 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly19 == 1); # rdtag_dly 27 - 36:41 , 0b010100 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly20 == 1); # rdtag_dly 27 - 36:41 , 0b010101 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly21 == 1); # rdtag_dly 27 - 36:41 , 0b010110 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly22 == 1); # rdtag_dly 27 - 36:41 , 0b010111 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly23 == 1); # rdtag_dly 27 - 36:41 , 0b011000 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly24 == 1); # rdtag_dly 27 - 36:41 , 0b011001 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly25 == 1); # rdtag_dly 27 - 36:41 , 0b011010 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly26 == 1); # rdtag_dly 27 - 36:41 , 0b011011 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly27 == 1); # rdtag_dly 27 - 36:41 , 0b011100 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly28 == 1); # rdtag_dly 27 - 36:41 , 0b011101 + def_margin_rdtag , 1 , (def_mba_dsm0q_cfg_rdtag_dly29 == 1); # rdtag_dly 27 - 43:48 , def_RDODT_start_udimm + def_RDODT_duration - 2 , 1 , (ATTR_EFF_DIMM_TYPE == 2); # CFG_RODT_BC4_END_DLY 28 - 43:48 , def_RDODT_start_rdimm + def_RDODT_duration - 2 , 1 , (ATTR_EFF_DIMM_TYPE == 1); # CFG_RODT_BC4_END_DLY 28 - 43:48 , def_RDODT_start_lrdimm + def_RDODT_duration - 2 , 1 , (ATTR_EFF_DIMM_TYPE == 3); # CFG_RODT_BC4_END_DLY 28 - 49:54 , 0b000011 , 1 , any; # CFG_WODT_BC4_END_DLY is 3 for all cfgs 29 D -} - -## Refresh Interval Calculuation -## refresh_interval = ((ATTR_EFF_DRAM_TRFI/(def_num_ranks))/8); -#define def_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); -define def_mba01_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1]); -define def_mba23_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); -define def_mba01_refresh_interval = ((ATTR_EFF_DRAM_TRFI)/(8*def_mba01_num_ranks)); -define def_mba23_refresh_interval = ((ATTR_EFF_DRAM_TRFI)/(8*def_mba23_num_ranks)); -# mulitply by 1.1 to give it 10% margin -define def_refresh_check_interval = ((ATTR_EFF_DRAM_TRFI/8) + ((ATTR_EFF_DRAM_TRFI/8)/10)); # same for both mba01 and mba23 - -# MBAREF0Q mba01 refresh settings -# -scom 0x03010432 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 4:7 , 0b0111 , 1 , any; # MBAREF0Q_refresh priority threshold is 0x7 for all cfgs 30 ?# refresh interval = tREFI(7.8) / # ranks per port / DRAM clk(ns) / 0.008 - 8:18 , def_mba01_refresh_interval, 1 , ATTR_CHIP_UNIT_POS == 0; # see calculation above - 8:18 , def_mba23_refresh_interval, 1 , ATTR_CHIP_UNIT_POS == 1; # see calculation above - 19:29 , 0b00011000010, 1 , any; # MBAREF0Q_refresh reset interval set to 194 decimal 32 ? !!FIXME - 30:39 , ATTR_EFF_DRAM_TRFC, 1 , any; # MBAREF0Q_cfg_trfc 33 - 40:49 , 0b0000100000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly32 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 - 40:49 , 0b0000110000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly48 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 - 40:49 , 0b0001000000 , 1 , (def_MBAREF0Q_cfg_refr_tsv_stack_dly64 == 1); # MBAREF0Q_cfg_refr_tsv_stack 33 - 50:60 , def_refresh_check_interval, 1 , any; # MBAREF0Q_refresh check intveral set to 780 decimal 35 -} - -# MBAPC0Q power control settings reg 1 -# -scom 0x03010434 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 2 , 0b0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 0) || ((SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 0 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2)) || ((SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 0 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1)); # cfg_min_max_domains 36 - 2 , 0b1 , 1 , ((SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)) || ((SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # cfg_min_max_domains 36 -# 3:5 , 0b001 , 1 , any; # cfg_min_max_domains 36 - 6:10 , 0b00100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail - performance enhancemnt - 6:10 , 0b00011 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail - performance enhancemnt - 6:10 , 0b00101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b00100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b00110 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b00101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b00111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b00110 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b01000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b00111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b01101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b01100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b10000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b01111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b10100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b10011 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b10111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b10110 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b11010 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b11001 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b11101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 6:10 , 0b11100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36 - 11:15 , 0b00011 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly3 == 1); # MBARPC0Q_cfg_pup_pup 37 - 11:15 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly4 == 1); # MBARPC0Q_cfg_pup_pup 37 - 11:15 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly5 == 1); # MBARPC0Q_cfg_pup_pup 37 - 11:15 , 0b00110 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly6 == 1); # MBARPC0Q_cfg_pup_pup 37 - 16:20 , 0b00011 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly3 == 1); # MBARPC0Q_cfg_pup_pdn 38 - 16:20 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly4 == 1); # MBARPC0Q_cfg_pup_pdn 38 - 16:20 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly5 == 1); # MBARPC0Q_cfg_pup_pdn 38 - 16:20 , 0b00110 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly6 == 1); # MBARPC0Q_cfg_pup_pdn 38 - 22 , 0b0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 0) || ((SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 0 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2)) || ((SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 0 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1)); # cfg_min_max_domains 36 - 22 , 0b1 , 1 , ((SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)) || ((SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # cfg_min_max_domains 36 - 23:32 , 0b0000000011, 1 , any; # Set min doman reduction time to 30.7 us (10.245us * 3) - 42 , 0b1 , 1 , any; # Force SpareCKE sync - 43 , 0b1 , 1 , any; # Use 1 in 8k 2:1 cycle pulses for min domain reduction time interval -} - -# had to shifts the data to be able to get it into the proper positions -define shift_pwr_map1 = (ATTR_VPD_CKE_PWR_MAP >> 60); -define shift_pwr_map2 = (ATTR_VPD_CKE_PWR_MAP >> 56); -define shift_pwr_map3 = (ATTR_VPD_CKE_PWR_MAP >> 52); -define shift_pwr_map4 = (ATTR_VPD_CKE_PWR_MAP >> 48); -define shift_pwr_map5 = (ATTR_VPD_CKE_PWR_MAP >> 44); -define shift_pwr_map6 = (ATTR_VPD_CKE_PWR_MAP >> 40); -define shift_pwr_map7 = (ATTR_VPD_CKE_PWR_MAP >> 36); -define shift_pwr_map8 = (ATTR_VPD_CKE_PWR_MAP >> 32); -define shift_pwr_map9 = (ATTR_VPD_CKE_PWR_MAP >> 28); -define shift_pwr_map10 = (ATTR_VPD_CKE_PWR_MAP >> 24); -define shift_pwr_map11 = (ATTR_VPD_CKE_PWR_MAP >> 20); -define shift_pwr_map12 = (ATTR_VPD_CKE_PWR_MAP >> 16); -define shift_pwr_map13 = (ATTR_VPD_CKE_PWR_MAP >> 12); -define shift_pwr_map14 = (ATTR_VPD_CKE_PWR_MAP >> 8); -define shift_pwr_map15 = (ATTR_VPD_CKE_PWR_MAP >> 4); - -# MBAPC1Q power control settings reg 1 -# -scom 0x03010435 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:15 , shift_pwr_map4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3); # slow exit pdown - 0:15 , ATTR_VPD_CKE_PRI_MAP[0], 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3); # fast exit pdown - 16:31 , shift_pwr_map8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3); # slow exit pdown - 16:31 , ATTR_VPD_CKE_PRI_MAP[1], 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3); # fast exit pdown - 32:47 , shift_pwr_map12, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3); # slow exit pdown - 32:47 , ATTR_VPD_CKE_PRI_MAP[0], 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3); # fast exit pdown - 48:63 , ATTR_VPD_CKE_PWR_MAP, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3); # slow exit pdown - 48:63 , ATTR_VPD_CKE_PRI_MAP[1], 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2 || CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3); # fast exit pdown -} - - - -########################### -# MBA CKE mapping tables # -########################### - -# use prim map A for 1b, 1c - -# MBAREF1Q MBA01 Rank-to-primary-CKE mapping table -# -scom 0x03010433 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:15 , ATTR_VPD_CKE_PRI_MAP[0], 1 , any; # from VPD now - 16:31 , ATTR_VPD_CKE_PRI_MAP[1], 1 , any; # from VPD now -} - -#define def_zqcal_timebase_in_ms=(16384*(1/CENTAUR.ATTR_MSS_FREQ)*.001) -define def_zq_intv_sel10 = (ATTR_EFF_ZQCAL_INTERVAL / 16384); -define def_zq_intv_sel11 = (ATTR_EFF_ZQCAL_INTERVAL / 16777216); -#define def_memcal_timebase_in_ms=(16384*(1/CENTAUR.ATTR_MSS_FREQ)*.001) -define def_mem_intv_sel10 = (ATTR_EFF_MEMCAL_INTERVAL / 16384); -define def_mem_intv_sel11 = (ATTR_EFF_MEMCAL_INTERVAL / 16777216); -# ATTR_EFF_MEMCAL_INTERVAL are in clock cycles -# ATTR_EFF_ZQCAL_INTERVAL are in clock cycles -#ATTR_EFF_MEMCAL_INTERVAL u32 0x027b9fba -#ATTR_EFF_ZQCAL_INTERVAL u32 0x008798a -# MBA_CAL0Q (this timer to be used for zq cal) -# -scom 0x0301040F { - - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0 , 0b0 , 1 , any; #disable timer initially - 1:2 , 0b10 , 1 , (def_zq_intv_sel10 < 512); #timebase; use 16384 cycle timebase if less than max of 512 - 1:2 , 0b11 , 1 , (def_zq_intv_sel10 > 511); #timebase; use 16777216 cycle timebase if greater than max of 512 - 3:11 , def_zq_intv_sel10, 1 , (def_zq_intv_sel10 < 512); #interval timer; computed using zq cal interval attribute; zq_intv=zq_cal_interval_attr/zqcal_timebase_in_ms (assumes attribute defined in milliseconds) - 3:11 , 0b000000001 , 1 , (def_zq_intv_sel10 > 511) && (def_zq_intv_sel11 == 0); #interval timer; computed using zq cal interval attribute; zq_intv=zq_cal_interval_attr/zqcal_timebase_in_ms (assumes attribute defined in milliseconds) - 3:11 , def_zq_intv_sel11, 1 , (def_zq_intv_sel10 > 511) && (def_zq_intv_sel11 > 0); #interval timer; computed using zq cal interval attribute; zq_intv=zq_cal_interval_attr/zqcal_timebase_in_ms (assumes attribute defined in milliseconds) - 12 , 0b1 , 1 , any; #enable for type1 - 13:16 , 0b0100 , 1 , any; #select external zq cal for type1 - 17 , 0b1 , 1 , any; #wait for done from DDR for type1 - 18 , 0b0 , 1 , any; #disable type2 timer - 19:22 , 0b0000 , 1 , any; #type2 cal type - 23 , 0b0 , 1 , any; #disable type2 done - 24 , 0b0 , 1 , any; #disable type3 timer - 25:28 , 0b0000 , 1 , any; #type3 cal type - 29 , 0b0 , 1 , any; #disable type3 done - 30:38 , 0b000000000 , 1 , any; #set timer to 0 for z sync - 39:46 , 0b01000000 , 1 , any; #reset tmr - 47:48 , 0b00 , 1 , any; #reset tb - 49 , 0b0 , 1 , any; #disable for soft reset on cal timeout - 50 , 0b1 , 1 , any; #use single rank mode - 51 , 0b0 , 1 , any; #cal0_pare_err - 52 , 0b0 , 1 , any; #1hot_sm_err - 53:55 , 0b000 , 1 , any; #cal_single_port_mode off - 56:63 , 0b00000000 , 1 , any; #reserved -} - -# MBA_CAL1Q (this timer to be used for mem cal) -# -scom 0x03010410 { - - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0 , 0b0 , 1 , any; #disable timer initially - 1:2 , 0b10 , 1 , (def_mem_intv_sel10 < 512); #timebase; use 16384 cycle timebase if less than max of 512 - 1:2 , 0b11 , 1 , (def_mem_intv_sel10 > 511); #timebase; use 16777216 cycle timebase if greater than max of 512 - 3:11 , def_mem_intv_sel10 , 1 , (def_mem_intv_sel10 < 512); #interval timer; computed using zq cal interval attribute; mem_intv=mem_cal_interval_attr/memcal_timebase_in_ms (assumes attribute defined in milliseconds) - 3:11 , 0b000000001 , 1 , (def_mem_intv_sel10 > 511) && (def_mem_intv_sel11 == 0); #interval timer; computed using zq cal interval attribute; mem_intv=mem_cal_interval_attr/memcal_timebase_in_ms (assumes attribute defined in milliseconds) - 3:11 , def_mem_intv_sel11 , 1 , (def_mem_intv_sel10 > 511) && (def_mem_intv_sel11 > 0); #interval timer; computed using zq cal interval attribute; mem_intv=mem_cal_interval_attr/memcal_timebase_in_ms (assumes attribute defined in milliseconds) - 12 , 0b1 , 1 , any; #enable for type1 - 13:16 , 0b0011 , 1 , any; #select Periodic Calbration: Run SysClk, DQS and Read Eye all in parallel for type - 17 , 0b1 , 1 , any; #wait for done from DDR for type1 - 18 , 0b0 , 1 , any; #disable type2 timer - 19:22 , 0b0000 , 1 , any; #type2 cal type - 23 , 0b0 , 1 , any; #disable type2 done - 24 , 0b0 , 1 , any; #disable type3 timer - 25:28 , 0b0000 , 1 , any; #type3 cal type - 29 , 0b0 , 1 , any; #disable type3 done - 30:38 , 0b000000000 , 1 , any; #set timer to 0 for z sync - 39 , 0b0 , 1 , any; #use single rank mode - 40:63 , 0b000000000000000000000000 , 1 , any; #reserved to 0 -} - -# MBA_CAL3Q (this timer to be used for mem cal) -# -scom 0x03010412 { - - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:1 , 0b11 , 1 , any; #cfg_internal_zq_tb RW Internal ZQ time base - 2:9 , 0b11111111 , 1 , any; #cfg_internal_zq_length RW Number of internal ZQ time bases required to meet max internal zq length - 10:11 , 0b11 , 1 , any; #cfg_external_zq_tb RW External ZQ time base - 12:19 , 0b11111111 , 1 , any; #cfg_external_zq_length RW Number of external ZQ time bases required to meet max external zq length - 20:21 , 0b11 , 1 , any; #cfg_rdclk_sysclk_tb RW Readclk/Sysclk time base - 22:29 , 0b11111111 , 1 , any; #cfg_rdclk_sysclk_length RW Number of Readclk/sysclk time bases required to meet max rdclk length - 30:31 , 0b11 , 1 , any; #cfg_dqs_alignment_tb RW Dqs alignment time base - 32:39 , 0b11111111 , 1 , any; #cfg_dqs_alignment_length RW Number of Dqs alignment time bases required to meet max dqs alignment length - 40:41 , 0b11 , 1 , any; #cfg_mpr_readeye_tb RW Readeye time base - 42:49 , 0b11111111 , 1 , any; #cfg_mpr_readeye_length RW Number of readeye time bases required to meet max external zq length - 50:51 , 0b11 , 1 , any; #cfg_all_periodic_tb RW All Periodics time base - 52:59 , 0b11111111 , 1 , any; #cfg_all_periodic_length RW Number of all_periodic time bases required to meet max calibration length for all periodic calibration ( in parallel ) -} - -########################################################################################### -# MBA MCBIST SETUP SECTION # -########################################################################################### - -################################### -# MCBIST Memory Register -################################### -# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBMR0Q_Q(0:63) (scomdef) -# Setup subtest tests -# Setup subtest 0 is a write with fixed data -# Setup subtest 1 is a read with fixed data - -scom 0x030106A8 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:2 , 0b000, 1 ,any; # cfg_test00_op_type is a write - 3 , 0b0, 1 ,any; # cfg_test00_compl_1st_cmd - 4 , 0b0, 1 ,any; # cfg_test00_compl_2nd_cmd - 5 , 0b0, 1 ,any; # cfg_test00_compl_3rd_cmd - 6:7 , 0b00, 1 ,any; # cfg_test00_addr_mode - 8:10 , 0b000, 1 ,any; # cfg_test00_data_mode - 11 , 0b0 , 1 ,any; # cfg_test00_done - 12:13 , 0b00, 1 ,any; # cfg_test00_data_sel - 14:15 , 0b00, 1 ,any; # cfg_test00_addr_sel - 16:18 , 0b001, 1 ,any; # cfg_test01_op_type is a read - 19 , 0b0, 1 ,any; # cfg_test01_compl_1st_cmd - 20 , 0b0, 1 ,any; # cfg_test01_compl_2nd_cmd - 21 , 0b0, 1 ,any; # cfg_test01_compl_3rd_cmd - 22:23 , 0b00, 1 ,any; # cfg_test01_addr_mode - 24:26 , 0b000, 1 ,any; # cfg_test01_data_mode - 27 , 0b1 , 1 ,any; # cfg_test01_done is set - 28:29 , 0b00, 1 ,any; # cfg_test01_data_sel - 30:31 , 0b00, 1 ,any; # cfg_test01_addr_sel - 32:34 , 0b000, 1 ,any; # cfg_test02_op_type - 35 , 0b0, 1 ,any; # cfg_test02_compl_1st_cmd - 36 , 0b0, 1 ,any; # cfg_test02_compl_2nd_cmd - 37 , 0b0, 1 ,any; # cfg_test02_compl_3rd_cmd - 38:39 , 0b00, 1 ,any; # cfg_test02_addr_mode - 40:42 , 0b000, 1 ,any; # cfg_test02_data_mode - 43 , 0b0 , 1 ,any; # cfg_test02_done - 44:45 , 0b00, 1 ,any; # cfg_test02_data_sel - 46:47 , 0b00, 1 ,any; # cfg_test02_addr_sel - 48:50 , 0b000, 1 ,any; # cfg_test03_op_type - 51 , 0b0, 1 ,any; # cfg_test03_compl_1st_cmd - 52 , 0b0, 1 ,any; # cfg_test03_compl_2nd_cmd - 53 , 0b0, 1 ,any; # cfg_test03_compl_3rd_cmd - 54:55 , 0b00, 1 ,any; # cfg_test03_addr_mode - 56:58 , 0b000, 1 ,any; # cfg_test03_data_mode - 59 , 0b0 , 1 ,any; # cfg_test03_done - 60:61 , 0b00, 1 ,any; # cfg_test03_data_sel - 62:63 , 0b00, 1 ,any; # cfg_test03_addr_sel -} - -################################### -# MCBIST Fixed data pattern -################################### -# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFD[0-7]Q_Q(0:63) (scomdef) -# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDQ_Q(0:63) (scomdef) -# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDSPQ_Q(0:63) (scomdef) - -scom 0x030106BE { - bits , scom_data , ATTR_FUNCTIONAL ,expr; - 0:63 , 0x1111111111111111, 1 ,any; # Fixed data burst 0 -} - -scom 0x030106BF { - bits , scom_data , ATTR_FUNCTIONAL ,expr; - 0:63 , 0x2222222222222222, 1 ,any; # Fixed data burst 1 -} - -scom 0x030106C0 { - bits , scom_data , ATTR_FUNCTIONAL ,expr; - 0:63 , 0x3333333333333333, 1 ,any; # Fixed data burst 2 -} - -scom 0x030106C1 { - bits , scom_data , ATTR_FUNCTIONAL ,expr; - 0:63 , 0x4444444444444444, 1 ,any; # Fixed data burst 3 -} - -scom 0x030106C2 { - bits , scom_data , ATTR_FUNCTIONAL ,expr; - 0:63 , 0x5555555555555555, 1 ,any; # Fixed data burst 4 -} - -scom 0x030106C3 { - bits , scom_data , ATTR_FUNCTIONAL ,expr; - 0:63 , 0x6666666666666666, 1 ,any; # Fixed data burst 5 -} - -scom 0x030106C4 { - bits , scom_data , ATTR_FUNCTIONAL ,expr; - 0:63 , 0x7777777777777777, 1 ,any; # Fixed data burst 6 -} - -scom 0x030106C5 { - bits , scom_data , ATTR_FUNCTIONAL ,expr; - 0:63 , 0x8888888888888888, 1 ,any; # Fixed data burst 7 -} - -scom 0x030106C6 { - bits , scom_data , ATTR_FUNCTIONAL ,expr; - 0:63 , 0x9999999999999999, 1 ,any; # Fixed data burst 0-7 ECC bits -} - -scom 0x030106C7 { - bits , scom_data , ATTR_FUNCTIONAL ,expr; - 0:63 , 0xAAAAAAAAAAAAAAAA, 1 ,any; # Fixed data burst 0-7 SPARE bits -} - - -################################### -# MCBIST Fixed Addr A0 Start/End -################################### - -# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBSAARA0Q_Q (scomdef) -# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBSEARA0Q_Q (scomdef) -# - - -scom 0x030106D0 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:35 , 0x000000000 , 1 , any; # A0 start address - 36:37 , 0b00 , 1 , any; # A0 start address -} - - - -scom 0x030106D2 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:3 , 0x0 , 1 , any ; # A0 End address - 4:15 , 0xFFF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total22_max22) ; # A0 End address - 4:15 , 0x7FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total23_max23) ||(def_mcb_addr_total22_max23) ; # A0 End address - 4:15 , 0x3FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total24_max24) ||(def_mcb_addr_total23_max24) ||(def_mcb_addr_total22_max24) ; # A0 End address - 4:15 , 0x1FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total25_max25) ||(def_mcb_addr_total24_max25) ||(def_mcb_addr_total23_max25) ||(def_mcb_addr_total22_max25) ; # A0 End address - 4:15 , 0x0FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total26_max26) ||(def_mcb_addr_total25_max26) ||(def_mcb_addr_total24_max26) ||(def_mcb_addr_total23_max26) ; # A0 End address - 4:15 , 0x07F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total27_max27) ||(def_mcb_addr_total26_max27) ||(def_mcb_addr_total25_max27) ||(def_mcb_addr_total24_max27) ; # A0 End address - 4:15 , 0x03F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total28_max28) ||(def_mcb_addr_total27_max28) ||(def_mcb_addr_total26_max28) ||(def_mcb_addr_total25_max28) ||(def_mcb_addr_total28_max29) ; # A0 End address - 4:15 , 0x01F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total27_max29) ||(def_mcb_addr_total26_max29) ; # A0 End address - 4:15 , 0x00F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total28_max30) ||(def_mcb_addr_total27_max30) ; # A0 End address - 4:15 , 0x007 , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 3 ) && (def_mcb_addr_total28_max31) ; # A0 End address - 4:15 , 0x7FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total22_max22) ; # A0 End address - 4:15 , 0x3FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total23_max23) ||(def_mcb_addr_total22_max23) ; # A0 End address - 4:15 , 0x1FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total24_max24) ||(def_mcb_addr_total23_max24) ||(def_mcb_addr_total22_max24) ; # A0 End address - 4:15 , 0x0FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total25_max25) ||(def_mcb_addr_total24_max25) ||(def_mcb_addr_total23_max25) ||(def_mcb_addr_total22_max25) ; # A0 End address - 4:15 , 0x07F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total26_max26) ||(def_mcb_addr_total25_max26) ||(def_mcb_addr_total24_max26) ||(def_mcb_addr_total23_max26) ; # A0 End address - 4:15 , 0x03F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total27_max27) ||(def_mcb_addr_total26_max27) ||(def_mcb_addr_total25_max27) ||(def_mcb_addr_total24_max27) ; # A0 End address - 4:15 , 0x01F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total28_max28) ||(def_mcb_addr_total27_max28) ||(def_mcb_addr_total26_max28) ||(def_mcb_addr_total25_max28) ||(def_mcb_addr_total28_max29) ; # A0 End address - 4:15 , 0x00F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total27_max29) ||(def_mcb_addr_total26_max29) ; # A0 End address - 4:15 , 0x007 , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total28_max30) ||(def_mcb_addr_total27_max30) ; # A0 End address - 4:15 , 0x003 , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 2 ) && (def_mcb_addr_total28_max31) ; # A0 End address - 4:15 , 0x3FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total22_max22) ; # A0 End address - 4:15 , 0x1FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total23_max23) ||(def_mcb_addr_total22_max23) ; # A0 End address - 4:15 , 0x0FF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total24_max24) ||(def_mcb_addr_total23_max24) ||(def_mcb_addr_total22_max24) ; # A0 End address - 4:15 , 0x07F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total25_max25) ||(def_mcb_addr_total24_max25) ||(def_mcb_addr_total23_max25) ||(def_mcb_addr_total22_max25) ; # A0 End address - 4:15 , 0x03F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total26_max26) ||(def_mcb_addr_total25_max26) ||(def_mcb_addr_total24_max26) ||(def_mcb_addr_total23_max26) ; # A0 End address - 4:15 , 0x01F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total27_max27) ||(def_mcb_addr_total26_max27) ||(def_mcb_addr_total25_max27) ||(def_mcb_addr_total24_max27) ; # A0 End address - 4:15 , 0x00F , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total28_max28) ||(def_mcb_addr_total27_max28) ||(def_mcb_addr_total26_max28) ||(def_mcb_addr_total25_max28) ||(def_mcb_addr_total28_max29) ; # A0 End address - 4:15 , 0x007 , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total27_max29) ||(def_mcb_addr_total26_max29) ; # A0 End address - 4:15 , 0x003 , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total28_max30) ||(def_mcb_addr_total27_max30) ; # A0 End address - 4:15 , 0x001 , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1) && (ATTR_EFF_SCHMOO_ADDR_MODE == 1 ) && (def_mcb_addr_total28_max31) ; # A0 End address - 4:15 , 0x000 , 1 , ((ATTR_EFF_SCHMOO_TEST_VALID != 1) || (ATTR_EFF_SCHMOO_TEST_VALID == 1 && ATTR_EFF_SCHMOO_ADDR_MODE == 0)); # A0 End address - 16:35 , 0x00000 , 1 , ((ATTR_EFF_SCHMOO_TEST_VALID != 1) || (ATTR_EFF_SCHMOO_TEST_VALID == 1 && ATTR_EFF_SCHMOO_ADDR_MODE == 0)); # A0 End address - 16:35 , 0xFFFFF , 1 , (ATTR_EFF_SCHMOO_TEST_VALID == 1 && ATTR_EFF_SCHMOO_ADDR_MODE != 0); # A0 End address - 36:37 , 0b11 , 1 , any; # A0 End address -} - -################################### -# MCBIST Addr Gen Cfg Reg -################################### - -# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBAGRAQ_Q (scomdef) -# - -scom 0x030106D6 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:5 , 0b000000 , 1 , any; # A0 cfg_fixed_width_a0 - 24:25 , 0b10 , 1 , any; # A0 setup only A0 address gen -} - -###### - - - - - -############################################ -# MCBIST Port A Socket 0 Addr Map Reg 0 -############################################ - -# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBAMR0A0Q_Q (scomdef) -# - -scom 0x030106C8 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:5 , 0b000000 , 1 , any ; #cfg_a0map_mrank0 Master Rank Bit 0 (MSB) - 6:11 , 0b000000 , 1 , ((def_mcb_mrank1_unset) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 - 6:11 , 0b000010 , 1 , ((def_mcb_addr_row17_col12_bnk16_mrank1_2 ) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 - 6:11 , 0b000011 , 1 , (((def_mcb_addr_row17_col11_bnk16_mrank1_3 ) ||(def_mcb_addr_row16_col12_bnk16_mrank1_3 ) ||(def_mcb_addr_row17_col12_bnk16_mrank1_3 ) ||( def_mcb_addr_row17_col12_bnk8_mrank1_3 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 - 6:11 , 0b000100 , 1 , (((def_mcb_addr_row17_col10_bnk16_mrank1_4 ) ||(def_mcb_addr_row16_col11_bnk16_mrank1_4 ) ||(def_mcb_addr_row17_col11_bnk16_mrank1_4 ) ||(def_mcb_addr_row15_col12_bnk16_mrank1_4 ) ||(def_mcb_addr_row16_col12_bnk16_mrank1_4 ) ||(def_mcb_addr_row17_col12_bnk16_mrank1_4 ) ||( def_mcb_addr_row17_col11_bnk8_mrank1_4 ) ||( def_mcb_addr_row16_col12_bnk8_mrank1_4 ) ||( def_mcb_addr_row17_col12_bnk8_mrank1_4 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 - 6:11 , 0b000101 , 1 , (((def_mcb_addr_row16_col10_bnk16_mrank1_5 ) ||(def_mcb_addr_row17_col12_bnk16_mrank1_5 ) ||(def_mcb_addr_row17_col10_bnk16_mrank1_5 ) ||(def_mcb_addr_row15_col11_bnk16_mrank1_5 ) ||(def_mcb_addr_row16_col11_bnk16_mrank1_5 ) ||(def_mcb_addr_row17_col11_bnk16_mrank1_5 ) ||(def_mcb_addr_row14_col12_bnk16_mrank1_5 ) ||(def_mcb_addr_row15_col12_bnk16_mrank1_5 ) ||(def_mcb_addr_row16_col12_bnk16_mrank1_5 ) ||( def_mcb_addr_row17_col10_bnk8_mrank1_5 ) ||( def_mcb_addr_row16_col11_bnk8_mrank1_5 ) ||( def_mcb_addr_row17_col11_bnk8_mrank1_5 ) ||( def_mcb_addr_row15_col12_bnk8_mrank1_5 ) ||( def_mcb_addr_row16_col12_bnk8_mrank1_5 ) ||( def_mcb_addr_row17_col12_bnk8_mrank1_5 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 - 6:11 , 0b000110 , 1 , (((def_mcb_addr_row15_col10_bnk16_mrank1_6 ) ||(def_mcb_addr_row17_col11_bnk16_mrank1_6 )||(def_mcb_addr_row16_col12_bnk16_mrank1_6 )||( def_mcb_addr_row17_col12_bnk8_mrank1_6 ) ||(def_mcb_addr_row16_col10_bnk16_mrank1_6 ) ||(def_mcb_addr_row17_col10_bnk16_mrank1_6 ) ||(def_mcb_addr_row14_col11_bnk16_mrank1_6 ) ||(def_mcb_addr_row15_col11_bnk16_mrank1_6 ) ||(def_mcb_addr_row16_col11_bnk16_mrank1_6 ) ||(def_mcb_addr_row14_col12_bnk16_mrank1_6 ) ||(def_mcb_addr_row15_col12_bnk16_mrank1_6 ) ||( def_mcb_addr_row16_col10_bnk8_mrank1_6 ) ||( def_mcb_addr_row17_col10_bnk8_mrank1_6 ) ||( def_mcb_addr_row14_col11_bnk8_mrank1_6 ) ||( def_mcb_addr_row15_col11_bnk8_mrank1_6 ) ||( def_mcb_addr_row16_col11_bnk8_mrank1_6 ) ||( def_mcb_addr_row17_col11_bnk8_mrank1_6 ) ||( def_mcb_addr_row14_col12_bnk8_mrank1_6 ) ||( def_mcb_addr_row15_col12_bnk8_mrank1_6 ) ||( def_mcb_addr_row16_col12_bnk8_mrank1_6 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 - 6:11 , 0b000111 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank1_7 ) ||(def_mcb_addr_row17_col10_bnk16_mrank1_7 )||(def_mcb_addr_row16_col11_bnk16_mrank1_7 )||(def_mcb_addr_row15_col12_bnk16_mrank1_7 )||( def_mcb_addr_row17_col11_bnk8_mrank1_7 )||( def_mcb_addr_row16_col12_bnk8_mrank1_7 )||(def_mcb_addr_row15_col10_bnk16_mrank1_7 ) ||(def_mcb_addr_row16_col10_bnk16_mrank1_7 ) ||(def_mcb_addr_row14_col11_bnk16_mrank1_7 ) ||(def_mcb_addr_row15_col11_bnk16_mrank1_7 ) ||(def_mcb_addr_row14_col12_bnk16_mrank1_7 ) ||( def_mcb_addr_row15_col10_bnk8_mrank1_7 ) ||( def_mcb_addr_row16_col10_bnk8_mrank1_7 ) ||( def_mcb_addr_row17_col10_bnk8_mrank1_7 ) ||( def_mcb_addr_row15_col11_bnk8_mrank1_7 ) ||( def_mcb_addr_row16_col11_bnk8_mrank1_7 ) ||( def_mcb_addr_row14_col12_bnk8_mrank1_7 ) ||( def_mcb_addr_row15_col12_bnk8_mrank1_7 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 - 6:11 , 0b001000 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank1_8 ) ||(def_mcb_addr_row16_col10_bnk16_mrank1_8 )||(def_mcb_addr_row15_col11_bnk16_mrank1_8 )||(def_mcb_addr_row14_col12_bnk16_mrank1_8 )||( def_mcb_addr_row17_col10_bnk8_mrank1_8 )||( def_mcb_addr_row16_col11_bnk8_mrank1_8 )||( def_mcb_addr_row15_col12_bnk8_mrank1_8 ) ||(def_mcb_addr_row15_col10_bnk16_mrank1_8 ) ||(def_mcb_addr_row14_col11_bnk16_mrank1_8 ) ||( def_mcb_addr_row14_col10_bnk8_mrank1_8 ) ||( def_mcb_addr_row15_col10_bnk8_mrank1_8 ) ||( def_mcb_addr_row16_col10_bnk8_mrank1_8 ) ||( def_mcb_addr_row14_col11_bnk8_mrank1_8 ) ||( def_mcb_addr_row15_col11_bnk8_mrank1_8 ) ||( def_mcb_addr_row14_col12_bnk8_mrank1_8 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 - 6:11 , 0b001001 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank1_9 ) ||(def_mcb_addr_row15_col10_bnk16_mrank1_9 )||(def_mcb_addr_row14_col11_bnk16_mrank1_9 )||( def_mcb_addr_row16_col10_bnk8_mrank1_9 )||( def_mcb_addr_row15_col11_bnk8_mrank1_9 )||( def_mcb_addr_row14_col12_bnk8_mrank1_9 )||( def_mcb_addr_row14_col10_bnk8_mrank1_9 ) ||( def_mcb_addr_row15_col10_bnk8_mrank1_9 ) ||( def_mcb_addr_row14_col11_bnk8_mrank1_9 )) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 - 6:11 , 0b001010 , 1 , (((def_mcb_addr_row14_col10_bnk8_mrank1_10) ||(def_mcb_addr_row14_col10_bnk16_mrank1_10)||( def_mcb_addr_row15_col10_bnk8_mrank1_10)||( def_mcb_addr_row14_col11_bnk8_mrank1_10)) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 - 6:11 , 0b001011 , 1 , (( def_mcb_addr_row14_col10_bnk8_mrank1_11) == 1); #cfg_a0map_mrank1 Master Rank Bit 1 -} - -scom 0x030106C8 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 12:17 , 0b000000 , 1 , ((def_mcb_mrank2_unset)); #cfg_a0map_mrank2 Master Rank Rank Bit 2 - 12:17 , 0b000011 , 1 , ((def_mcb_addr_row17_col12_bnk16_mrank2_3 ) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 - 12:17 , 0b000100 , 1 , (((def_mcb_addr_row17_col11_bnk16_mrank2_4 ) ||(def_mcb_addr_row16_col12_bnk16_mrank2_4 ) ||(def_mcb_addr_row17_col12_bnk16_mrank2_4 ) ||( def_mcb_addr_row17_col12_bnk8_mrank2_4 )) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 - 12:17 , 0b000101 , 1 , (((def_mcb_addr_row17_col10_bnk16_mrank2_5 ) ||(def_mcb_addr_row16_col11_bnk16_mrank2_5 ) ||(def_mcb_addr_row17_col11_bnk16_mrank2_5 ) ||(def_mcb_addr_row15_col12_bnk16_mrank2_5 ) ||(def_mcb_addr_row16_col12_bnk16_mrank2_5 ) ||(def_mcb_addr_row17_col12_bnk16_mrank2_5 ) ||( def_mcb_addr_row17_col11_bnk8_mrank2_5 ) ||( def_mcb_addr_row16_col12_bnk8_mrank2_5 ) ||( def_mcb_addr_row17_col12_bnk8_mrank2_5 )) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 - 12:17 , 0b000110 , 1 , (((def_mcb_addr_row16_col10_bnk16_mrank2_6 ) ||(def_mcb_addr_row17_col12_bnk16_mrank2_6 ) ||(def_mcb_addr_row17_col10_bnk16_mrank2_6 ) ||(def_mcb_addr_row15_col11_bnk16_mrank2_6 ) ||(def_mcb_addr_row16_col11_bnk16_mrank2_6 ) ||(def_mcb_addr_row17_col11_bnk16_mrank2_6 ) ||(def_mcb_addr_row14_col12_bnk16_mrank2_6 ) ||(def_mcb_addr_row15_col12_bnk16_mrank2_6 ) ||(def_mcb_addr_row16_col12_bnk16_mrank2_6 ) ||( def_mcb_addr_row17_col10_bnk8_mrank2_6 ) ||( def_mcb_addr_row16_col11_bnk8_mrank2_6 ) ||( def_mcb_addr_row17_col11_bnk8_mrank2_6 ) ||( def_mcb_addr_row15_col12_bnk8_mrank2_6 ) ||( def_mcb_addr_row16_col12_bnk8_mrank2_6 ) ||( def_mcb_addr_row17_col12_bnk8_mrank2_6 )) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 - 12:17 , 0b000111 , 1 , (((def_mcb_addr_row15_col10_bnk16_mrank2_7 ) ||(def_mcb_addr_row17_col11_bnk16_mrank2_7 )||(def_mcb_addr_row16_col12_bnk16_mrank2_7 )||( def_mcb_addr_row17_col12_bnk8_mrank2_7 ) ||(def_mcb_addr_row16_col10_bnk16_mrank2_7 ) ||(def_mcb_addr_row17_col10_bnk16_mrank2_7 ) ||(def_mcb_addr_row14_col11_bnk16_mrank2_7 ) ||(def_mcb_addr_row15_col11_bnk16_mrank2_7 ) ||(def_mcb_addr_row16_col11_bnk16_mrank2_7 ) ||(def_mcb_addr_row14_col12_bnk16_mrank2_7 ) ||(def_mcb_addr_row15_col12_bnk16_mrank2_7 ) ||( def_mcb_addr_row16_col10_bnk8_mrank2_7 ) ||( def_mcb_addr_row17_col10_bnk8_mrank2_7 ) ||( def_mcb_addr_row14_col11_bnk8_mrank2_7 ) ||( def_mcb_addr_row15_col11_bnk8_mrank2_7 ) ||( def_mcb_addr_row16_col11_bnk8_mrank2_7 ) ||( def_mcb_addr_row17_col11_bnk8_mrank2_7 ) ||( def_mcb_addr_row14_col12_bnk8_mrank2_7 ) ||( def_mcb_addr_row15_col12_bnk8_mrank2_7 ) ||( def_mcb_addr_row16_col12_bnk8_mrank2_7 )) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 - 12:17 , 0b001000 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank2_8 ) ||(def_mcb_addr_row17_col10_bnk16_mrank2_8 )||(def_mcb_addr_row16_col11_bnk16_mrank2_8 )||(def_mcb_addr_row15_col12_bnk16_mrank2_8 )||( def_mcb_addr_row17_col11_bnk8_mrank2_8 )||( def_mcb_addr_row16_col12_bnk8_mrank2_8 ) ||(def_mcb_addr_row15_col10_bnk16_mrank2_8 ) ||(def_mcb_addr_row16_col10_bnk16_mrank2_8 ) ||(def_mcb_addr_row14_col11_bnk16_mrank2_8 ) ||(def_mcb_addr_row15_col11_bnk16_mrank2_8 ) ||(def_mcb_addr_row14_col12_bnk16_mrank2_8 ) ||( def_mcb_addr_row15_col10_bnk8_mrank2_8 ) ||( def_mcb_addr_row16_col10_bnk8_mrank2_8 ) ||( def_mcb_addr_row17_col10_bnk8_mrank2_8 ) ||( def_mcb_addr_row15_col11_bnk8_mrank2_8 ) ||( def_mcb_addr_row16_col11_bnk8_mrank2_8 ) ||( def_mcb_addr_row14_col12_bnk8_mrank2_8 ) ||( def_mcb_addr_row15_col12_bnk8_mrank2_8 )) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 - 12:17 , 0b001001 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank2_9 ) ||(def_mcb_addr_row16_col10_bnk16_mrank2_9 )||(def_mcb_addr_row15_col11_bnk16_mrank2_9 )||(def_mcb_addr_row14_col12_bnk16_mrank2_9 )||( def_mcb_addr_row17_col10_bnk8_mrank2_9 )||( def_mcb_addr_row16_col11_bnk8_mrank2_9 ) ||( def_mcb_addr_row15_col12_bnk8_mrank2_9 ) ||(def_mcb_addr_row15_col10_bnk16_mrank2_9 ) ||(def_mcb_addr_row14_col11_bnk16_mrank2_9 ) ||( def_mcb_addr_row14_col10_bnk8_mrank2_9 ) ||( def_mcb_addr_row15_col10_bnk8_mrank2_9 ) ||( def_mcb_addr_row16_col10_bnk8_mrank2_9 ) ||( def_mcb_addr_row14_col11_bnk8_mrank2_9 ) ||( def_mcb_addr_row15_col11_bnk8_mrank2_9 ) ||( def_mcb_addr_row14_col12_bnk8_mrank2_9 )) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 - 12:17 , 0b001010 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank2_10) ||(def_mcb_addr_row15_col10_bnk16_mrank2_10)||(def_mcb_addr_row14_col11_bnk16_mrank2_10)||( def_mcb_addr_row16_col10_bnk8_mrank2_10)||( def_mcb_addr_row15_col11_bnk8_mrank2_10)||( def_mcb_addr_row14_col12_bnk8_mrank2_10) ||( def_mcb_addr_row14_col10_bnk8_mrank2_10) ||( def_mcb_addr_row15_col10_bnk8_mrank2_10) ||( def_mcb_addr_row14_col11_bnk8_mrank2_10)) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 - 12:17 , 0b001011 , 1 , (((def_mcb_addr_row14_col10_bnk8_mrank2_11) ||(def_mcb_addr_row14_col10_bnk16_mrank2_11)||( def_mcb_addr_row15_col10_bnk8_mrank2_11)||( def_mcb_addr_row14_col11_bnk8_mrank2_11)) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 - 12:17 , 0b001100 , 1 , (( def_mcb_addr_row14_col10_bnk8_mrank2_12) == 1); #cfg_a0map_mrank2 Master Rank Rank Bit 2 -} - -scom 0x030106C8 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 18:23 , 0b000000 , 1 , ((def_mcb_mrank3_unset) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 - 18:23 , 0b000100 , 1 , ((def_mcb_addr_row17_col12_bnk16_mrank3_4 ) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 - 18:23 , 0b000101 , 1 , (((def_mcb_addr_row17_col11_bnk16_mrank3_5 ) ||(def_mcb_addr_row16_col12_bnk16_mrank3_5 ) ||(def_mcb_addr_row17_col12_bnk16_mrank3_5 ) ||( def_mcb_addr_row17_col12_bnk8_mrank3_5 )) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 - 18:23 , 0b000110 , 1 , (((def_mcb_addr_row17_col10_bnk16_mrank3_6 ) ||(def_mcb_addr_row16_col11_bnk16_mrank3_6 ) ||(def_mcb_addr_row17_col11_bnk16_mrank3_6 ) ||(def_mcb_addr_row15_col12_bnk16_mrank3_6 ) ||(def_mcb_addr_row16_col12_bnk16_mrank3_6 ) ||(def_mcb_addr_row17_col12_bnk16_mrank3_6 ) ||( def_mcb_addr_row17_col11_bnk8_mrank3_6 ) ||( def_mcb_addr_row16_col12_bnk8_mrank3_6 ) ||( def_mcb_addr_row17_col12_bnk8_mrank3_6 )) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 - 18:23 , 0b000111 , 1 , (((def_mcb_addr_row16_col10_bnk16_mrank3_7 ) ||(def_mcb_addr_row17_col12_bnk16_mrank3_7 ) ||(def_mcb_addr_row17_col10_bnk16_mrank3_7 ) ||(def_mcb_addr_row15_col11_bnk16_mrank3_7 ) ||(def_mcb_addr_row16_col11_bnk16_mrank3_7 ) ||(def_mcb_addr_row17_col11_bnk16_mrank3_7 ) ||(def_mcb_addr_row14_col12_bnk16_mrank3_7 ) ||(def_mcb_addr_row15_col12_bnk16_mrank3_7 ) ||(def_mcb_addr_row16_col12_bnk16_mrank3_7 ) ||( def_mcb_addr_row17_col10_bnk8_mrank3_7 ) ||( def_mcb_addr_row16_col11_bnk8_mrank3_7 ) ||( def_mcb_addr_row17_col11_bnk8_mrank3_7 ) ||( def_mcb_addr_row15_col12_bnk8_mrank3_7 ) ||( def_mcb_addr_row16_col12_bnk8_mrank3_7 ) ||( def_mcb_addr_row17_col12_bnk8_mrank3_7 )) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 - 18:23 , 0b001000 , 1 , (((def_mcb_addr_row15_col10_bnk16_mrank3_8 ) ||(def_mcb_addr_row17_col11_bnk16_mrank3_8 )||(def_mcb_addr_row16_col12_bnk16_mrank3_8 )||( def_mcb_addr_row17_col12_bnk8_mrank3_8 ) ||(def_mcb_addr_row16_col10_bnk16_mrank3_8 ) ||(def_mcb_addr_row17_col10_bnk16_mrank3_8 ) ||(def_mcb_addr_row14_col11_bnk16_mrank3_8 ) ||(def_mcb_addr_row15_col11_bnk16_mrank3_8 ) ||(def_mcb_addr_row16_col11_bnk16_mrank3_8 ) ||(def_mcb_addr_row14_col12_bnk16_mrank3_8 ) ||(def_mcb_addr_row15_col12_bnk16_mrank3_8 ) ||( def_mcb_addr_row16_col10_bnk8_mrank3_8 ) ||( def_mcb_addr_row17_col10_bnk8_mrank3_8 ) ||( def_mcb_addr_row14_col11_bnk8_mrank3_8 ) ||( def_mcb_addr_row15_col11_bnk8_mrank3_8 ) ||( def_mcb_addr_row16_col11_bnk8_mrank3_8 ) ||( def_mcb_addr_row17_col11_bnk8_mrank3_8 ) ||( def_mcb_addr_row14_col12_bnk8_mrank3_8 ) ||( def_mcb_addr_row15_col12_bnk8_mrank3_8 ) ||( def_mcb_addr_row16_col12_bnk8_mrank3_8 )) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 - 18:23 , 0b001001 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank3_9 ) ||(def_mcb_addr_row17_col10_bnk16_mrank3_9 )||(def_mcb_addr_row16_col11_bnk16_mrank3_9 )||(def_mcb_addr_row15_col12_bnk16_mrank3_9 )||( def_mcb_addr_row17_col11_bnk8_mrank3_9 )||( def_mcb_addr_row16_col12_bnk8_mrank3_9 ) ||(def_mcb_addr_row15_col10_bnk16_mrank3_9 ) ||(def_mcb_addr_row16_col10_bnk16_mrank3_9 ) ||(def_mcb_addr_row14_col11_bnk16_mrank3_9 ) ||(def_mcb_addr_row15_col11_bnk16_mrank3_9 ) ||(def_mcb_addr_row14_col12_bnk16_mrank3_9 ) ||( def_mcb_addr_row15_col10_bnk8_mrank3_9 ) ||( def_mcb_addr_row16_col10_bnk8_mrank3_9 ) ||( def_mcb_addr_row17_col10_bnk8_mrank3_9 ) ||( def_mcb_addr_row15_col11_bnk8_mrank3_9 ) ||( def_mcb_addr_row16_col11_bnk8_mrank3_9 ) ||( def_mcb_addr_row14_col12_bnk8_mrank3_9 ) ||( def_mcb_addr_row15_col12_bnk8_mrank3_9 )) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 - 18:23 , 0b001010 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank3_10) ||(def_mcb_addr_row16_col10_bnk16_mrank3_10)||(def_mcb_addr_row15_col11_bnk16_mrank3_10)||(def_mcb_addr_row14_col12_bnk16_mrank3_10)||( def_mcb_addr_row17_col10_bnk8_mrank3_10)||( def_mcb_addr_row16_col11_bnk8_mrank3_10)||( def_mcb_addr_row15_col12_bnk8_mrank3_10) ||(def_mcb_addr_row15_col10_bnk16_mrank3_10) ||(def_mcb_addr_row14_col11_bnk16_mrank3_10) ||( def_mcb_addr_row14_col10_bnk8_mrank3_10) ||( def_mcb_addr_row15_col10_bnk8_mrank3_10) ||( def_mcb_addr_row16_col10_bnk8_mrank3_10) ||( def_mcb_addr_row14_col11_bnk8_mrank3_10) ||( def_mcb_addr_row15_col11_bnk8_mrank3_10) ||( def_mcb_addr_row14_col12_bnk8_mrank3_10)) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 - 18:23 , 0b001011 , 1 , (((def_mcb_addr_row14_col10_bnk16_mrank3_11) ||(def_mcb_addr_row15_col10_bnk16_mrank3_11)||(def_mcb_addr_row14_col11_bnk16_mrank3_11)||( def_mcb_addr_row16_col10_bnk8_mrank3_11)||( def_mcb_addr_row15_col11_bnk8_mrank3_11)||( def_mcb_addr_row14_col12_bnk8_mrank3_11) ||( def_mcb_addr_row14_col10_bnk8_mrank3_11) ||( def_mcb_addr_row15_col10_bnk8_mrank3_11) ||( def_mcb_addr_row14_col11_bnk8_mrank3_11)) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 - 18:23 , 0b001100 , 1 , (((def_mcb_addr_row14_col10_bnk8_mrank3_12) ||(def_mcb_addr_row14_col10_bnk16_mrank3_12)||( def_mcb_addr_row15_col10_bnk8_mrank3_12)||( def_mcb_addr_row14_col11_bnk8_mrank3_12)) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 - 18:23 , 0b001101 , 1 , (( def_mcb_addr_row14_col10_bnk8_mrank3_13) == 1); #cfg_a0map_mrank3 Master Rank Rank Bit 3 -} - -scom 0x030106C8 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 24:29 , 0b000000 , 1 , ((def_mcb_srank0_unset) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) - 24:29 , 0b000101 , 1 , ((def_mcb_addr_col12_bnk16_srank0_5 ) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) - 24:29 , 0b000110 , 1 , (((def_mcb_addr_col11_bnk16_srank0_6 ) ||(def_mcb_addr_col12_bnk16_srank0_6 ) ||( def_mcb_addr_col12_bnk8_srank0_6 )) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) - 24:29 , 0b000111 , 1 , (((def_mcb_addr_col10_bnk16_srank0_7 ) ||(def_mcb_addr_col11_bnk16_srank0_7 ) ||(def_mcb_addr_col12_bnk16_srank0_7 ) ||( def_mcb_addr_col11_bnk8_srank0_7 ) ||( def_mcb_addr_col12_bnk8_srank0_7 )) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) - 24:29 , 0b001000 , 1 , (((def_mcb_addr_col10_bnk16_srank0_8 ) ||(def_mcb_addr_col11_bnk16_srank0_8 ) ||(def_mcb_addr_col12_bnk16_srank0_8 ) ||( def_mcb_addr_col10_bnk8_srank0_8 ) ||( def_mcb_addr_col11_bnk8_srank0_8 ) ||( def_mcb_addr_col12_bnk8_srank0_8 )) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) - 24:29 , 0b001001 , 1 , (((def_mcb_addr_col10_bnk16_srank0_9 ) ||(def_mcb_addr_col11_bnk16_srank0_9 ) ||( def_mcb_addr_col10_bnk8_srank0_9 ) ||( def_mcb_addr_col11_bnk8_srank0_9 ) ||( def_mcb_addr_col12_bnk8_srank0_9 )) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) - 24:29 , 0b001010 , 1 , ((( def_mcb_addr_col10_bnk8_srank0_10) ||( def_mcb_addr_col11_bnk8_srank0_10) ||(def_mcb_addr_col10_bnk16_srank0_10) ||( def_mcb_addr_col10_bnk8_srank0_11)) == 1); #cfg_a0map_srank0 Slave Rank Bit 0 (MSB) - 30:35 , 0b000000 , 1 , ((def_mcb_srank1_unset) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 - 30:35 , 0b000110 , 1 , ((def_mcb_addr_col12_bnk16_srank1_6 ) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 - 30:35 , 0b000111 , 1 , (((def_mcb_addr_col11_bnk16_srank1_7 ) ||(def_mcb_addr_col12_bnk16_srank1_7 ) ||( def_mcb_addr_col12_bnk8_srank1_7 )) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 - 30:35 , 0b001000 , 1 , (((def_mcb_addr_col10_bnk16_srank1_8 ) ||(def_mcb_addr_col11_bnk16_srank1_8 ) ||(def_mcb_addr_col12_bnk16_srank1_8 ) ||( def_mcb_addr_col11_bnk8_srank1_8 ) ||( def_mcb_addr_col12_bnk8_srank1_8 )) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 - 30:35 , 0b001001 , 1 , (((def_mcb_addr_col10_bnk16_srank1_9 ) ||(def_mcb_addr_col11_bnk16_srank1_9 ) ||(def_mcb_addr_col12_bnk16_srank1_9 ) ||( def_mcb_addr_col10_bnk8_srank1_9 ) ||( def_mcb_addr_col11_bnk8_srank1_9 ) ||( def_mcb_addr_col12_bnk8_srank1_9 )) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 - 30:35 , 0b001010 , 1 , (((def_mcb_addr_col10_bnk16_srank1_10) ||(def_mcb_addr_col11_bnk16_srank1_10) ||( def_mcb_addr_col10_bnk8_srank1_10) ||( def_mcb_addr_col11_bnk8_srank1_10) ||( def_mcb_addr_col12_bnk8_srank1_10)) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 - 30:35 , 0b001011 , 1 , (((def_mcb_addr_col10_bnk16_srank1_11) ||( def_mcb_addr_col10_bnk8_srank1_11) ||( def_mcb_addr_col11_bnk8_srank1_11)) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 - 30:35 , 0b001100 , 1 , (( def_mcb_addr_col10_bnk8_srank1_12) == 1); #cfg_a0map_srank1 Slave Rank Bit 1 -} - -scom 0x030106C8 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 36:41 , 0b000000 , 1 , ((def_mcb_srank2_unset) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 - 36:41 , 0b000111 , 1 , ((def_mcb_addr_col12_bnk16_srank2_7 ) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 - 36:41 , 0b001000 , 1 , (((def_mcb_addr_col11_bnk16_srank2_8 ) ||(def_mcb_addr_col12_bnk16_srank2_8 ) ||( def_mcb_addr_col12_bnk8_srank2_8 )) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 - 36:41 , 0b001001 , 1 , (((def_mcb_addr_col10_bnk16_srank2_9 ) ||(def_mcb_addr_col11_bnk16_srank2_9 ) ||(def_mcb_addr_col12_bnk16_srank2_9 ) ||( def_mcb_addr_col11_bnk8_srank2_9 ) ||( def_mcb_addr_col12_bnk8_srank2_9 )) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 - 36:41 , 0b001010 , 1 , (((def_mcb_addr_col10_bnk16_srank2_10) ||(def_mcb_addr_col11_bnk16_srank2_10) ||(def_mcb_addr_col12_bnk16_srank2_10) ||( def_mcb_addr_col10_bnk8_srank2_10) ||( def_mcb_addr_col11_bnk8_srank2_10) ||( def_mcb_addr_col12_bnk8_srank2_10) ||(def_mcb_addr_col10_bnk16_srank2_11)) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 - 36:41 , 0b001011 , 1 , (((def_mcb_addr_col11_bnk16_srank2_11) ||( def_mcb_addr_col10_bnk8_srank2_11) ||( def_mcb_addr_col11_bnk8_srank2_11) ||( def_mcb_addr_col12_bnk8_srank2_11)) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 - 36:41 , 0b001100 , 1 , (((def_mcb_addr_col10_bnk16_srank2_12) ||( def_mcb_addr_col10_bnk8_srank2_12) ||( def_mcb_addr_col11_bnk8_srank2_12)) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 - 36:41 , 0b001101 , 1 , (( def_mcb_addr_col10_bnk8_srank2_13) == 1); #cfg_a0map_srank2 Slave Rank Rank Bit 2 - 42:47 , 0b011011 , 1 , (def_mcb_addr_bank3_27 == 1); #cfg_a0map_bank3 DRAM Bank Address Bit 3 (MSB) - 42:47 , 0b011010 , 1 , (def_mcb_addr_bank3_26 == 1); #cfg_a0map_bank3 DRAM Bank Address Bit 3 (MSB) - 42:47 , 0b011001 , 1 , (def_mcb_addr_bank3_25 == 1); #cfg_a0map_bank3 DRAM Bank Address Bit 3 (MSB) - 42:47 , 0b000000 , 1 , (def_mcb_addr_unset_bank3 == 1); #cfg_a0map_bank3 DRAM Bank Address Bit 3 (MSB) - 48:53 , 0b011100 , 1 , (def_mcb_addr_bank2_28 == 1); #cfg_a0map_bank2 DRAM Bank Address Bit 2 (MSB) - 48:53 , 0b011011 , 1 , (def_mcb_addr_bank2_27 == 1); #cfg_a0map_bank2 DRAM Bank Address Bit 2 (MSB) - 48:53 , 0b011010 , 1 , (def_mcb_addr_bank2_26 == 1); #cfg_a0map_bank2 DRAM Bank Address Bit 2 (MSB) - 54:59 , 0b011101 , 1 , (def_mcb_addr_bank1_29 == 1); #cfg_a0map_bank1 DRAM Bank Address Bit 1 - 54:59 , 0b011100 , 1 , (def_mcb_addr_bank1_28 == 1); #cfg_a0map_bank1 DRAM Bank Address Bit 1 - 54:59 , 0b011011 , 1 , (def_mcb_addr_bank1_27 == 1); #cfg_a0map_bank1 DRAM Bank Address Bit 1 -} - - -scom 0x030106C9 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:5 , 0b011110 , 1 , (def_mcb_addr_bank0_30 == 1); #cfg_a0map_bank0 DRAM Bank Address Bit 0 - 0:5 , 0b011101 , 1 , (def_mcb_addr_bank0_29 == 1); #cfg_a0map_bank0 DRAM Bank Address Bit 0 - 0:5 , 0b011100 , 1 , (def_mcb_addr_bank0_28 == 1); #cfg_a0map_bank0 DRAM Bank Address Bit 0 - 6:11 , 0b001011 , 1 , (def_mcb_addr_row16_11 == 1); #cfg_a0map_row16 DRAM Row Address Bit16 (MSB) - 6:11 , 0b001010 , 1 , (def_mcb_addr_row16_10 == 1); #cfg_a0map_row16 DRAM Row Address Bit16 (MSB) - 6:11 , 0b001001 , 1 , (def_mcb_addr_row16_9 == 1); #cfg_a0map_row16 DRAM Row Address Bit16 (MSB) - 6:11 , 0b001000 , 1 , (def_mcb_addr_row16_8 == 1); #cfg_a0map_row16 DRAM Row Address Bit16 (MSB) - 6:11 , 0b000000 , 1 , (def_mcb_addr_unset_row16 == 1); #cfg_a0map_row16 DRAM Row Address Bit16 (MSB) - 12:17 , 0b001100 , 1 , (def_mcb_addr_row15_12 == 1); #cfg_a0map_row15 DRAM Row Address Bit15 - 12:17 , 0b001011 , 1 , (def_mcb_addr_row15_11 == 1); #cfg_a0map_row15 DRAM Row Address Bit15 - 12:17 , 0b001010 , 1 , (def_mcb_addr_row15_10 == 1); #cfg_a0map_row15 DRAM Row Address Bit15 - 12:17 , 0b001001 , 1 , (def_mcb_addr_row15_9 == 1); #cfg_a0map_row15 DRAM Row Address Bit15 - 12:17 , 0b000000 , 1 , (def_mcb_addr_unset_row15 == 1); #cfg_a0map_row15 DRAM Row Address Bit15 - 18:23 , 0b001101 , 1 , (def_mcb_addr_row14_13 == 1); #cfg_a0map_row14 DRAM Row Address Bit 14 - 18:23 , 0b001100 , 1 , (def_mcb_addr_row14_12 == 1); #cfg_a0map_row14 DRAM Row Address Bit 14 - 18:23 , 0b001011 , 1 , (def_mcb_addr_row14_11 == 1); #cfg_a0map_row14 DRAM Row Address Bit 14 - 18:23 , 0b001010 , 1 , (def_mcb_addr_row14_10 == 1); #cfg_a0map_row14 DRAM Row Address Bit 14 - 18:23 , 0b000000 , 1 , (def_mcb_addr_unset_row14 == 1); #cfg_a0map_row14 DRAM Row Address Bit 14 - 24:29 , 0b001110 , 1 , (def_mcb_addr_row13_14 == 1); #cfg_a0map_row13 DRAM Row Address Bit 13 - 24:29 , 0b001101 , 1 , (def_mcb_addr_row13_13 == 1); #cfg_a0map_row13 DRAM Row Address Bit 13 - 24:29 , 0b001100 , 1 , (def_mcb_addr_row13_12 == 1); #cfg_a0map_row13 DRAM Row Address Bit 13 - 24:29 , 0b001011 , 1 , (def_mcb_addr_row13_11 == 1); #cfg_a0map_row13 DRAM Row Address Bit 13 - 30:35 , 0b001111 , 1 , (def_mcb_addr_row12_15 == 1); #cfg_a0map_row12 DRAM Row Address Bit 12 - 30:35 , 0b001110 , 1 , (def_mcb_addr_row12_14 == 1); #cfg_a0map_row12 DRAM Row Address Bit 12 - 30:35 , 0b001101 , 1 , (def_mcb_addr_row12_13 == 1); #cfg_a0map_row12 DRAM Row Address Bit 12 - 30:35 , 0b001100 , 1 , (def_mcb_addr_row12_12 == 1); #cfg_a0map_row12 DRAM Row Address Bit 12 - 36:41 , 0b010000 , 1 , (def_mcb_addr_row11_16 == 1); #cfg_a0map_row11 DRAM Row Address Bit 11 - 36:41 , 0b001111 , 1 , (def_mcb_addr_row11_15 == 1); #cfg_a0map_row11 DRAM Row Address Bit 11 - 36:41 , 0b001110 , 1 , (def_mcb_addr_row11_14 == 1); #cfg_a0map_row11 DRAM Row Address Bit 11 - 36:41 , 0b001101 , 1 , (def_mcb_addr_row11_13 == 1); #cfg_a0map_row11 DRAM Row Address Bit 11 - 42:47 , 0b010001 , 1 , (def_mcb_addr_row10_17 == 1); #cfg_a0map_row10 DRAM Row Address Bit 10 - 42:47 , 0b010000 , 1 , (def_mcb_addr_row10_16 == 1); #cfg_a0map_row10 DRAM Row Address Bit 10 - 42:47 , 0b001111 , 1 , (def_mcb_addr_row10_15 == 1); #cfg_a0map_row10 DRAM Row Address Bit 10 - 42:47 , 0b001110 , 1 , (def_mcb_addr_row10_14 == 1); #cfg_a0map_row10 DRAM Row Address Bit 10 - 48:53 , 0b010010 , 1 , (def_mcb_addr_row9_18 == 1); #cfg_a0map_row9 DRAM Row Address Bit 9 - 48:53 , 0b010001 , 1 , (def_mcb_addr_row9_17 == 1); #cfg_a0map_row9 DRAM Row Address Bit 9 - 48:53 , 0b010000 , 1 , (def_mcb_addr_row9_16 == 1); #cfg_a0map_row9 DRAM Row Address Bit 9 - 48:53 , 0b001111 , 1 , (def_mcb_addr_row9_15 == 1); #cfg_a0map_row9 DRAM Row Address Bit 9 - 54:59 , 0b010011 , 1 , (def_mcb_addr_row8_19 == 1); #cfg_a0map_row8 DRAM Row Address Bit 8 - 54:59 , 0b010010 , 1 , (def_mcb_addr_row8_18 == 1); #cfg_a0map_row8 DRAM Row Address Bit 8 - 54:59 , 0b010001 , 1 , (def_mcb_addr_row8_17 == 1); #cfg_a0map_row8 DRAM Row Address Bit 8 - 54:59 , 0b010000 , 1 , (def_mcb_addr_row8_16 == 1); #cfg_a0map_row8 DRAM Row Address Bit 8 -} - -scom 0x030106CA { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:5 , 0b010100 , 1 , (def_mcb_addr_row7_20 == 1); #cfg_a0map_row7 DRAM Row Address Bit 7 - 0:5 , 0b010011 , 1 , (def_mcb_addr_row7_19 == 1); #cfg_a0map_row7 DRAM Row Address Bit 7 - 0:5 , 0b010010 , 1 , (def_mcb_addr_row7_18 == 1); #cfg_a0map_row7 DRAM Row Address Bit 7 - 0:5 , 0b010001 , 1 , (def_mcb_addr_row7_17 == 1); #cfg_a0map_row7 DRAM Row Address Bit 7 - 6:11 , 0b010101 , 1 , (def_mcb_addr_row6_21 == 1); #cfg_a0map_row6 DRAM Row Address Bit 6 - 6:11 , 0b010100 , 1 , (def_mcb_addr_row6_20 == 1); #cfg_a0map_row6 DRAM Row Address Bit 6 - 6:11 , 0b010011 , 1 , (def_mcb_addr_row6_19 == 1); #cfg_a0map_row6 DRAM Row Address Bit 6 - 6:11 , 0b010010 , 1 , (def_mcb_addr_row6_18 == 1); #cfg_a0map_row6 DRAM Row Address Bit 6 - 12:17 , 0b010110 , 1 , (def_mcb_addr_row5_22 == 1); #cfg_a0map_row5 DRAM Row Address Bit 5 - 12:17 , 0b010101 , 1 , (def_mcb_addr_row5_21 == 1); #cfg_a0map_row5 DRAM Row Address Bit 5 - 12:17 , 0b010100 , 1 , (def_mcb_addr_row5_20 == 1); #cfg_a0map_row5 DRAM Row Address Bit 5 - 12:17 , 0b010011 , 1 , (def_mcb_addr_row5_19 == 1); #cfg_a0map_row5 DRAM Row Address Bit 5 - 18:23 , 0b010111 , 1 , (def_mcb_addr_row4_23 == 1); #cfg_a0map_row4 DRAM Row Address Bit 4 - 18:23 , 0b010110 , 1 , (def_mcb_addr_row4_22 == 1); #cfg_a0map_row4 DRAM Row Address Bit 4 - 18:23 , 0b010101 , 1 , (def_mcb_addr_row4_21 == 1); #cfg_a0map_row4 DRAM Row Address Bit 4 - 18:23 , 0b010100 , 1 , (def_mcb_addr_row4_20 == 1); #cfg_a0map_row4 DRAM Row Address Bit 4 - 24:29 , 0b011000 , 1 , (def_mcb_addr_row3_24 == 1); #cfg_a0map_row3 DRAM Row Address Bit 3 - 24:29 , 0b010111 , 1 , (def_mcb_addr_row3_23 == 1); #cfg_a0map_row3 DRAM Row Address Bit 3 - 24:29 , 0b010110 , 1 , (def_mcb_addr_row3_22 == 1); #cfg_a0map_row3 DRAM Row Address Bit 3 - 24:29 , 0b010101 , 1 , (def_mcb_addr_row3_21 == 1); #cfg_a0map_row3 DRAM Row Address Bit 3 - 30:35 , 0b011001 , 1 , (def_mcb_addr_row2_25 == 1); #cfg_a0map_row2 DRAM Row Address Bit 2 - 30:35 , 0b011000 , 1 , (def_mcb_addr_row2_24 == 1); #cfg_a0map_row2 DRAM Row Address Bit 2 - 30:35 , 0b010111 , 1 , (def_mcb_addr_row2_23 == 1); #cfg_a0map_row2 DRAM Row Address Bit 2 - 30:35 , 0b010110 , 1 , (def_mcb_addr_row2_22 == 1); #cfg_a0map_row2 DRAM Row Address Bit 2 - 36:41 , 0b011010 , 1 , (def_mcb_addr_row1_26 == 1); #cfg_a0map_row1 DRAM Row Address Bit 1 - 36:41 , 0b011001 , 1 , (def_mcb_addr_row1_25 == 1); #cfg_a0map_row1 DRAM Row Address Bit 1 - 36:41 , 0b011000 , 1 , (def_mcb_addr_row1_24 == 1); #cfg_a0map_row1 DRAM Row Address Bit 1 - 36:41 , 0b010111 , 1 , (def_mcb_addr_row1_23 == 1); #cfg_a0map_row1 DRAM Row Address Bit 1 - 42:47 , 0b011011 , 1 , (def_mcb_addr_row0_27 == 1); #cfg_a0map_row0 DRAM Row Address Bit 0 - 42:47 , 0b011010 , 1 , (def_mcb_addr_row0_26 == 1); #cfg_a0map_row0 DRAM Row Address Bit 0 - 42:47 , 0b011001 , 1 , (def_mcb_addr_row0_25 == 1); #cfg_a0map_row0 DRAM Row Address Bit 0 - 42:47 , 0b011000 , 1 , (def_mcb_addr_row0_24 == 1); #cfg_a0map_row0 DRAM Row Address Bit 0 - 48:53 , 0b000000 , 1 , (def_mcb_addr_unset_col13 == 1); #cfg_a0map_col13 DRAM Column Address Bit 13 (MSB) - 48:53 , 0b011101 , 1 , (def_mcb_addr_col13_29 == 1); #cfg_a0map_col13 DRAM Column Address Bit 13 (MSB) - 54:59 , 0b000000 , 1 , (def_mcb_addr_unset_col11 == 1); #cfg_a0map_col11 DRAM Column Address Bit 11 - 54:59 , 0b011110 , 1 , (def_mcb_addr_col11_30 == 1); #cfg_a0map_col11 DRAM Column Address Bit 11 -} - -scom 0x030106CB { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:5 , 0b011111 , 1 , any; #cfg_a0map_col9 DRAM Column Address Bit 9 - 6:11 , 0b100000 , 1 , any; #cfg_a0map_col8 DRAM Column Address Bit 8 - 12:17 , 0b100001 , 1 , any; #cfg_a0map_col7 DRAM Column Address Bit 7 - 18:23 , 0b100010 , 1 , any; #cfg_a0map_col6 DRAM Column Address Bit 6 - 24:29 , 0b100011 , 1 , any; #cfg_a0map_col5 DRAM Column Address Bit 5 - 30:35 , 0b100100 , 1 , any; #cfg_a0map_col4 DRAM Column Address Bit 4 - 36:41 , 0b100101 , 1 , any; #cfg_a0map_col3 DRAM Column Address Bit 3 -# 42:47 , 0b100101 , 1 , any; #cfg_a0map_col2 DRAM Column Address Bit 2 Map to an Unused Address bit if NOT fixed BL= 4 - 42:47 , 0b000000 , 1 , any; #cfg_a0map_col2 DRAM Column Address Bit 2 Map to an Unused Address bit if NOT fixed BL= 4 -} - - diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile deleted file mode 100644 index 2c0b762c4..000000000 --- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile +++ /dev/null @@ -1,961 +0,0 @@ -#-- $Id: mbs_def.initfile,v 1.50 2014/08/12 14:22:13 yctschan Exp $ -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -#-- 1.50 |tschang | 8/06/14| FW626918 - Changed L4 Cleaner settings per rank group to be able to handle deconfigured MBAs -#-- 1.49 |tschang | 6/10/14| Enabled clock stop on xstop for the trace arrays FW624741 -#-- 1.48 |baysah |04/21/14| Added L4 Cleaner settings per rank group to improve memory performance -#-- 1.47 |tschang | 3/19/14| SW252733 - L4 Cache UE Handling -#-- 1.46 |tschang | 3/19/14| SW252733 - L4 Cache UE Handling typo -#-- 1.45 |tschang | 2/24/14| fixed MBA1 only cfg -#-- 1.44 |tschang | 2/17/14| bit 12 of MBAXCR23Q should be the same as MBAXCR01Q -#-- 1.43 |tschang | 2/07/14| HW246685 - RCE reported even if we also have chip marks or symbol marks in place -#-- 1.42 |tschang |01/30/14| Removed CDIMM TYPE and replace with custom dimm -#-- 1.41 |tschang |01/24/13| SYS.ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT changed to ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT -#-- SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE changed to ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE -#-- 1.40 |tschang |11/21/13| HW271989 - updated SCOM write to do a full 64 bit write instead of a RMW -#-- 1.39 |tschang |11/12/13| no functional changes - clean up unused variables -#-- 1.38 |tschang |10/30/13| hash mode update for other IBM types -#-- 1.37 |tschang |08/15/13| HW259719 - dd2 only fix - ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL to turn on clock gates -#-- 1.36 |tschang |07/03/13| L4.ATTR_FUNCTIONAL for cache enable for some bits I missed -#-- 1.35 |tschang |07/02/13| L4.ATTR_FUNCTIONAL for cache enable -#-- 1.34 |tschang |06/11/13| removed mask out bit 8 - internal parity error - HW244827 and HW251643 -#-- 1.33 |tschang |06/06/13| mask out bit 8 - internal parity error - HW244827 and HW251643 -#-- 1.32 |tschang |04/24/13| fixed 1d cfg type -#-- 1.31 |tschang |04/17/13| hash mode updated for type 1a/1b/5b -#-- 1.30 |tschang |04/16/13| updated file for new IBM_TYPE defnitions -#-- 1.29 |tschang |04/08/13| added MBI cfg register initialization for Irving -#-- 1.26 |tschang |03/13/13| changed cache interleave mode to have ATTR_MSS_CACHE_ENABLE as a condition -#-- 1.25 |tschang |01/17/13| cache enabled when (ATTR_MSS_CACHE_ENABLE != 0) - enabled cache when 1/2 cache mode is choosen -#-- 1.21 |tschang |10/23/12| disable interleaving when one or both MBA are disabled (partial good tests) -#-- 1.20 |tschang |09/27/12| added partial good support for the SCOM write using ATTR_FUNCTIONAL -#-- 1.19 |menlowuu|08/21/12| fixed 2 address typo's -#-- 1.18 |tschang |08/20/12| added mbs mcbist setup values for simple write and read test -#-- 1.17 |bellows |07/23/12| made ATTR_MSS_CACHE_ENABLE at centaur level instead of system -#-- 1.16 |yctschan|07/05/12| Removed sticks for subtype B -#-- 1.14 |yctschan|06/28/12| Cleanup define syntax and ()'s -#-- 1.13 |menlowuu|06/28/12| Fixed 0x201140B/C bit 9 definition -#-- 1.12 |yctschan| 6/25/12| Stuck subtype to B in MBAXCR01Q and MBAXCR23Q bits 4:5 until IBM_TYPE is fixed -#-- 1.6 |mwuu |05/09/12| Added extra '()' to work with new compiler -#-- 1.5 |bellows |05/03/12| Updates for working version -#-- |bellows |04/26/12| Match 1B hardware config -#-- |bellows |04/26/12| Updates for VBU -#-- |mwuu |04/19/12| fixed MBAXCR01Q address for MBA23 -#-- 0.01 |retter |01/13/12| Initial version -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- - -#--Master list of variables that can be used in this file is at: -#--<Attribute Definition Location> - -SyntaxVersion = 1 - -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Defines -#-- -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- - -define def_equal_test = (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT32_2); - -# EFF_DIMM_RANKS_CONFIGED [a][b] - a=0, def_mba01 a = 1, def_mba23 -# - b=0, socket0 (mrank 0:3) b = 1, socket1 (mrank 4:7)) -# EFF_NUM_RANKS_PER_DIMM = total number of master and slave ranks per socket -# -# ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] u8[2][2] 0x80 -# ATTR_EFF_MBA_POS (0=01, 1=2/3) -# -# ATTR_EFF_IBM_TYPE -# UNDEFINED = 0, TYPE_1A = 1, TYPE_1B = 2, TYPE_1C = 3, TYPE_2A = 4, TYPE_2B = 5, TYPE_2C = 6, TYPE_3A = 7, TYPE_3B = 8, TYPE_3C = 9, TYPE_4A = 10, TYPE_4B = 11, TYPE_4C = 12, -# TYPE_5A = 13, TYPE_5B = 14, TYPE_5C = 15, TYPE_5D = 16, TYPE_6A = 17, TYPE_6B = 18, TYPE_6C = 19, TYPE_7A = 20, TYPE_7B = 21, TYPE_7C = 22, TYPE_8A = 23, TYPE_8B = 24, TYPE_8C = 25 -# -# ATTR_EFF_NUM_DROPS_PER_PORT -# EMPTY = 0, SINGLE = 1, DUAL = 2 -# -# ATTR_EFF_DIMM_TYPE -# CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3 -# -# ATTR_EFF_DRAM_DLL_PPD -# SLOWEXIT = 0, FASTEXIT = 1 -# -# ATTR_EFF_DRAM_GEN -# EMPTY = 0, DDR3 = 1, DDR4 = 2 -# -# CENTAUR.ATTR_MSS_FREQ = frequency -# not an mba attribute will need hierachy -# -# ATTR_CHIP_UNIT_POS -# 0 = MBA0 (mba01), 1 = MBA1 (mba23) -# -# SYS.ATTR_MSS_CACHE_ENABLE - -define MBA0 = TGT1; -define MBA1 = TGT2; -define L4 = TGT3; -#define CENTAUR = TGT4; # parent Centaur - -# MBA0.ATTR_CHIP_UNIT_POS - that should equal 0 -# MBA1.ATTR_CHIP_UNIT_POS should equal - -define def_no_spare = (SYS.ATTR_IS_SIMULATION==1) ; -define def_has_spare = (SYS.ATTR_IS_SIMULATION==0) ; - -define def_mba01_nomem = ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0b00000000) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0b00000000)); -define def_mba23_nomem = ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0b00000000) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0b00000000)); - -# MBA0 (mba01) -define def_mba01_1a_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); # DDR3/4 are same -define def_mba01_1a_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2));# || (def_mba01_1b_cdimm)); # DDR3/4 are same -#define def_mba01_1a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as 1a_1socket RDIMM - -define def_mba01_1b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba01_1b_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_1c_cdimm)); -#define def_mba01_1b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1A 2 socket RDIMM cfg for DDR3/4 - -## 1C 1 and 2 sockets not supported -#define def_mba01_1c_1socket = 0; -#define def_mba01_1c_2socket = 0; -#define def_mba01_1c_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -#define def_mba01_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_1c_1socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_mba01_1d_1socket; -define def_mba01_1c_2socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_mba01_1d_2socket; -define def_mba01_1c_cdimm = (((MBA0.ATTR_EFF_IBM_TYPE[1][0] == 3 ) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 3 )) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1B 2 socket RDIMM cfg for DDR3/4 - -## Current they is no 1D IBM type in the attribute -#define def_mba01_1d_1socket = 0; -#define def_mba01_1d_2socket = 0; -#define def_mba01_1d_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -#define def_mba01_1d_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_1d_1socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba01_1d_2socket = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); - -## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs -define def_mba01_2a_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_cdimm)); -define def_mba01_2a_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_2c_cdimm) || (def_mba01_3a_cdimm)); -define def_mba01_2a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket cfg -define def_mba01_2a_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_ddr4_cdimm)); -define def_mba01_2a_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3a_ddr4_cdimm)); -define def_mba01_2a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket DDR4 cfg - -define def_mba01_2b_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2b_cdimm)); -define def_mba01_2b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_mba01_2b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket cfg -define def_mba01_2b_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2b_ddr4_cdimm)); -define def_mba01_2b_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3b_ddr4_cdimm)); -define def_mba01_2b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket DDR4 cfg - -# centuar spec only has DDR4 for 2C cfg -define def_mba01_2c_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_cdimm)); -define def_mba01_2c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_mba01_2c_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket cfg -define def_mba01_2c_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_ddr4_cdimm)); -define def_mba01_2c_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3c_ddr4_cdimm)); -define def_mba01_2c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket DDR4 cfg - -define def_mba01_3a_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba01_3a_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4a_cdimm)); -#define def_mba01_3a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 2 socket cfg -define def_mba01_3a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1))) && (MBA0.ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg -define def_mba01_3a_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba01_3a_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4a_ddr4_cdimm)); -define def_mba01_3a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1))) && (MBA0.ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg - -define def_mba01_3b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba01_3b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_mba01_3b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg -define def_mba01_3b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg ?? - -define def_mba01_3c_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba01_3c_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4c_ddr4_cdimm)); -define def_mba01_3c_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg -define def_mba01_3c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg - -define def_mba01_4a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 11))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket cfg -define def_mba01_4a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 11))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket DDR4 cfg - -define def_mba01_4b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 12))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3B 2 socket DDR4 cfg - -define def_mba01_4c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 13))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA0.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA0.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3C 2 socket DDR4 cfg - -define def_mba01_5b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba01_5b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); - -define def_mba01_5c_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba01_5c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); - -define def_mba01_5d_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 17))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba01_5d_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 17))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); - -define def_mba01_7a_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba01_7a_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba01_7a_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba01_7a_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); - -define def_mba01_7b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba01_7b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba01_7b_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba01_7b_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); - -define def_mba01_7c_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba01_7c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba01_7c_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba01_7c_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3)); - -# MBA1 (mba23) -define def_mba23_1a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); # DDR3/4 are same -define def_mba23_1a_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2));# || (def_mba23_1b_cdimm)); # DDR3/4 are same -#define def_mba23_1a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as 1a_1socket RDIMM - -define def_mba23_1b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba23_1b_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_1c_cdimm)); -#define def_mba23_1b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1A 2 socket RDIMM cfg for DDR3/4 - -## 1C 1 and 2 sockets not supported -#define def_mba23_1c_1socket = 0; -#define def_mba23_1c_2socket = 0; -#define def_mba23_1c_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -#define def_mba23_1c_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba23_1c_1socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || def_mba23_1d_1socket; -define def_mba23_1c_2socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || def_mba23_1d_2socket; -define def_mba23_1c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type1B 2 socket RDIMM cfg for DDR3/4 - -## Current they is no 1D IBM type in the attribute -#define def_mba23_1d_1socket = 0; -#define def_mba23_1d_2socket = 0; -#define def_mba23_1d_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -#define def_mba23_1d_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba23_1d_1socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba23_1d_2socket = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); - -## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs -define def_mba23_2a_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_cdimm)); -define def_mba23_2a_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_2c_cdimm) || (def_mba23_3a_cdimm)); -define def_mba23_2a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket cfg -define def_mba23_2a_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_ddr4_cdimm)); -define def_mba23_2a_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3a_ddr4_cdimm)); -define def_mba23_2a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 1 socket DDR4 cfg - -define def_mba23_2b_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2b_cdimm)); -define def_mba23_2b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_mba23_2b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket cfg -define def_mba23_2b_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2b_ddr4_cdimm)); -define def_mba23_2b_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3b_ddr4_cdimm)); -define def_mba23_2b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 1 socket DDR4 cfg - -# centuar spec only has DDR4 for 2C cfg -define def_mba23_2c_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_cdimm)); -define def_mba23_2c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_mba23_2c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket cfg -define def_mba23_2c_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_ddr4_cdimm)); -define def_mba23_2c_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3c_ddr4_cdimm)); -define def_mba23_2c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 1 socket DDR4 cfg - -define def_mba23_3a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba23_3a_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4a_cdimm)); -#define def_mba23_3a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2A 2 socket cfg -define def_mba23_3a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1))) && (MBA1.ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg -define def_mba23_3a_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba23_3a_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4a_ddr4_cdimm)); -define def_mba23_3a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1))) && (MBA1.ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg - -define def_mba23_3b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba23_3b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)); -define def_mba23_3b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg -define def_mba23_3b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2B 2 socket DDR4 cfg ?? - -define def_mba23_3c_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); -define def_mba23_3c_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4c_ddr4_cdimm)); -define def_mba23_3c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg -define def_mba23_3c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type2C 2 socket DDR4 cfg - -define def_mba23_4a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket cfg -define def_mba23_4a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3A 2 socket DDR4 cfg - -define def_mba23_4b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3B 2 socket DDR4 cfg - -define def_mba23_4c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 13))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (((MBA1.ATTR_EFF_DIMM_TYPE == 2 ) && (MBA1.ATTR_EFF_CUSTOM_DIMM == 1)))); # same as type3C 2 socket DDR4 cfg - -define def_mba23_5b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba23_5b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); - -define def_mba23_5c_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 16))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba23_5c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 16))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); - -define def_mba23_5d_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 17))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba23_5d_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 17))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); - -define def_mba23_7a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba23_7a_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba23_7a_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba23_7a_2socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); - -define def_mba23_7b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba23_7b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba23_7b_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba23_7b_2socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); - -define def_mba23_7c_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba23_7c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba23_7c_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); -define def_mba23_7c_2socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3)); - - -define def_mba01_mtype_1a = (def_mba01_1a_1socket ||def_mba01_1a_2socket);# ||def_mba01_1b_cdimm); -define def_mba01_mtype_1b = (def_mba01_1b_1socket ||def_mba01_1b_2socket ||def_mba01_1c_cdimm); -define def_mba01_mtype_1c = (def_mba01_1c_1socket ||def_mba01_1c_2socket); -define def_mba01_mtype_2a = (def_mba01_2a_1socket ||def_mba01_2a_2socket ||def_mba01_2a_1socket_ddr4||def_mba01_2a_2socket_ddr4||def_mba01_3a_cdimm ||def_mba01_3a_ddr4_cdimm); -define def_mba01_mtype_2b = (def_mba01_2b_1socket ||def_mba01_2b_2socket ||def_mba01_2b_1socket_ddr4||def_mba01_2b_2socket_ddr4||def_mba01_3b_cdimm ||def_mba01_3b_ddr4_cdimm); -define def_mba01_mtype_2c = (def_mba01_2c_1socket ||def_mba01_2c_2socket ||def_mba01_2c_1socket_ddr4||def_mba01_2c_2socket_ddr4||def_mba01_3c_cdimm ||def_mba01_3c_ddr4_cdimm); -define def_mba01_mtype_3a = (def_mba01_3a_1socket ||def_mba01_3a_2socket ||def_mba01_3a_1socket_ddr4||def_mba01_3a_2socket_ddr4||def_mba01_4a_cdimm ||def_mba01_4a_ddr4_cdimm); -define def_mba01_mtype_3b = (def_mba01_3b_1socket ||def_mba01_3b_2socket ||def_mba01_4b_ddr4_cdimm); -define def_mba01_mtype_3c = (def_mba01_3c_1socket_ddr4||def_mba01_3c_2socket_ddr4||def_mba01_4c_ddr4_cdimm); -#define def_mba01_mtype_4a = 0; # not supported -#define def_mba01_mtype_4b = 0; # not supported -#define def_mba01_mtype_4c = 0; # not supported -#define def_mba01_mtype_5a = 0; # not supported -define def_mba01_mtype_4a = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_mtype_4b = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_mtype_4c = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_mtype_5a = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_mtype_5b = ((def_mba01_5b_1socket )||(def_mba01_5b_2socket)); -define def_mba01_mtype_5c = ((def_mba01_5c_1socket )||(def_mba01_5c_2socket)); -define def_mba01_mtype_5d = ((def_mba01_5d_1socket )||(def_mba01_5d_2socket)); -#define def_mba01_mtype_6a = 0; # not supported -#define def_mba01_mtype_6b = 0; # not supported -#define def_mba01_mtype_6c = 0; # not supported -define def_mba01_mtype_6a = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_mtype_6b = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_mtype_6c = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba01_mtype_7a = (def_mba01_7a_1socket ||def_mba01_7a_2socket ||def_mba01_7a_1socket_ddr4||def_mba01_7a_2socket_ddr4); -define def_mba01_mtype_7b = (def_mba01_7b_1socket ||def_mba01_7b_2socket ||def_mba01_7b_1socket_ddr4||def_mba01_7b_2socket_ddr4); -define def_mba01_mtype_7c = (def_mba01_7c_1socket ||def_mba01_7c_2socket ||def_mba01_7c_1socket_ddr4||def_mba01_7c_2socket_ddr4); - -define def_mba23_mtype_1a = (def_mba23_1a_1socket ||def_mba23_1a_2socket);# ||def_mba23_1b_cdimm); -define def_mba23_mtype_1b = (def_mba23_1b_1socket ||def_mba23_1b_2socket ||def_mba23_1c_cdimm); -define def_mba23_mtype_1c = (def_mba23_1c_1socket ||def_mba23_1c_2socket); -define def_mba23_mtype_2a = (def_mba23_2a_1socket ||def_mba23_2a_2socket ||def_mba23_2a_1socket_ddr4||def_mba23_2a_2socket_ddr4||def_mba23_3a_cdimm ||def_mba23_3a_ddr4_cdimm); -define def_mba23_mtype_2b = (def_mba23_2b_1socket ||def_mba23_2b_2socket ||def_mba23_2b_1socket_ddr4||def_mba23_2b_2socket_ddr4||def_mba23_3b_cdimm ||def_mba23_3b_ddr4_cdimm); -define def_mba23_mtype_2c = (def_mba23_2c_1socket ||def_mba23_2c_2socket ||def_mba23_2c_1socket_ddr4||def_mba23_2c_2socket_ddr4||def_mba23_3c_cdimm ||def_mba23_3c_ddr4_cdimm); -define def_mba23_mtype_3a = (def_mba23_3a_1socket ||def_mba23_3a_2socket ||def_mba23_3a_1socket_ddr4||def_mba23_3a_2socket_ddr4||def_mba23_4a_cdimm ||def_mba23_4a_ddr4_cdimm); -define def_mba23_mtype_3b = (def_mba23_3b_1socket ||def_mba23_3b_2socket ||def_mba23_4b_ddr4_cdimm); -define def_mba23_mtype_3c = (def_mba23_3c_1socket_ddr4||def_mba23_3c_2socket_ddr4||def_mba23_4c_ddr4_cdimm); -#define def_mba23_mtype_4a = 0; # not supported -#define def_mba23_mtype_4b = 0; # not supported -#define def_mba23_mtype_4c = 0; # not supported -#define def_mba23_mtype_5a = 0; # not supported -define def_mba23_mtype_4a = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba23_mtype_4b = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba23_mtype_4c = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba23_mtype_5a = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba23_mtype_5b = ((def_mba23_5b_1socket )||(def_mba23_5b_2socket)); -define def_mba23_mtype_5c = ((def_mba23_5c_1socket )||(def_mba23_5c_2socket)); -define def_mba23_mtype_5d = ((def_mba23_5d_1socket )||(def_mba23_5d_2socket)); -#define def_mba23_mtype_6a = 0; # not supported -#define def_mba23_mtype_6b = 0; # not supported -#define def_mba23_mtype_6c = 0; # not supported -define def_mba23_mtype_6a = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba23_mtype_6b = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba23_mtype_6c = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false -define def_mba23_mtype_7a = (def_mba23_7a_1socket ||def_mba23_7a_2socket ||def_mba23_7a_1socket_ddr4||def_mba23_7a_2socket_ddr4); -define def_mba23_mtype_7b = (def_mba23_7b_1socket ||def_mba23_7b_2socket ||def_mba23_7b_1socket_ddr4||def_mba23_7b_2socket_ddr4); -define def_mba23_mtype_7c = (def_mba23_7c_1socket ||def_mba23_7c_2socket ||def_mba23_7c_1socket_ddr4||def_mba23_7c_2socket_ddr4); - - - -define def_mba01_type1_memory_populated_behind_MBA01 = (def_mba01_mtype_1a ||def_mba01_mtype_1b ||def_mba01_mtype_1c);# ||def_mba01_mtype_1d); -define def_mba01_type2_memory_populated_behind_MBA01 = (def_mba01_mtype_2a ||def_mba01_mtype_2b ||def_mba01_mtype_2c ||def_mba01_mtype_5d); -define def_mba01_type3_memory_populated_behind_MBA01 = (def_mba01_mtype_3a ||def_mba01_mtype_3b ||def_mba01_mtype_3c); -define def_mba01_type4_memory_populated_behind_MBA01 = (def_mba01_mtype_4a ||def_mba01_mtype_4b ||def_mba01_mtype_4c); -define def_mba01_type5_memory_populated_behind_MBA01 = (def_mba01_mtype_5a ||def_mba01_mtype_5b ||def_mba01_mtype_5c); -define def_mba01_type6_memory_populated_behind_MBA01 = (def_mba01_mtype_6a ||def_mba01_mtype_6b ||def_mba01_mtype_6c); -define def_mba01_type7_memory_populated_behind_MBA01 = (def_mba01_mtype_7a ||def_mba01_mtype_7b ||def_mba01_mtype_7c); -#define def_mba01_type8_memory_populated_behind_MBA01 = (def_mba01_mtype_8a ||def_mba01_mtype_8b ||def_mba01_mtype_8c); - -define def_mba23_type1_memory_populated_behind_MBA23 = (def_mba23_mtype_1a ||def_mba23_mtype_1b ||def_mba23_mtype_1c);# ||def_mba23_mtype_1d); -define def_mba23_type2_memory_populated_behind_MBA23 = (def_mba23_mtype_2a ||def_mba23_mtype_2b ||def_mba23_mtype_2c ||def_mba23_mtype_5d); -define def_mba23_type3_memory_populated_behind_MBA23 = (def_mba23_mtype_3a ||def_mba23_mtype_3b ||def_mba23_mtype_3c); -define def_mba23_type4_memory_populated_behind_MBA23 = (def_mba23_mtype_4a ||def_mba23_mtype_4b ||def_mba23_mtype_4c); -define def_mba23_type5_memory_populated_behind_MBA23 = (def_mba23_mtype_5a ||def_mba23_mtype_5b ||def_mba23_mtype_5c); -define def_mba23_type6_memory_populated_behind_MBA23 = (def_mba23_mtype_6a ||def_mba23_mtype_6b ||def_mba23_mtype_6c); -define def_mba23_type7_memory_populated_behind_MBA23 = (def_mba23_mtype_7a ||def_mba23_mtype_7b ||def_mba23_mtype_7c); -#define def_mba23_type8_memory_populated_behind_MBA23 = (def_mba23_mtype_8a ||def_mba23_mtype_8b ||def_mba23_mtype_8c); - -define def_mba01_subtype_A = (def_mba01_mtype_1a || def_mba01_mtype_2a || def_mba01_mtype_3a || def_mba01_mtype_4a || def_mba01_mtype_5a || def_mba01_mtype_6a || def_mba01_mtype_7a);# || def_mba01_mtype_8a); -define def_mba01_subtype_B = (def_mba01_mtype_1b || def_mba01_mtype_2b || def_mba01_mtype_3b || def_mba01_mtype_4b || def_mba01_mtype_5b || def_mba01_mtype_6b || def_mba01_mtype_7b);# || def_mba01_mtype_8b); -#define def_mba01_subtype_C = (def_mba01_mtype_1c || def_mba01_mtype_1d || def_mba01_mtype_2c || def_mba01_mtype_3c || def_mba01_mtype_4c || def_mba01_mtype_5c || def_mba01_mtype_5d || def_mba01_mtype_6c || def_mba01_mtype_7c);# || def_mba01_mtype_8c); -define def_mba01_subtype_C = (def_mba01_mtype_1c || def_mba01_mtype_2c || def_mba01_mtype_3c || def_mba01_mtype_4c || def_mba01_mtype_5c || def_mba01_mtype_5d || def_mba01_mtype_6c || def_mba01_mtype_7c );# || def_mba01_mtype_8c); - -define def_mba23_subtype_A = (def_mba23_mtype_1a || def_mba23_mtype_2a || def_mba23_mtype_3a || def_mba23_mtype_4a || def_mba23_mtype_5a || def_mba23_mtype_6a || def_mba23_mtype_7a);# || def_mba23_mtype_8a); -define def_mba23_subtype_B = (def_mba23_mtype_1b || def_mba23_mtype_2b || def_mba23_mtype_3b || def_mba23_mtype_4b || def_mba23_mtype_5b || def_mba23_mtype_6b || def_mba23_mtype_7b);# || def_mba23_mtype_8b); -#define def_mba23_subtype_C = (def_mba23_mtype_1c || def_mba23_mtype_1d || def_mba23_mtype_2c || def_mba23_mtype_3c || def_mba23_mtype_4c || def_mba23_mtype_5c || def_mba23_mtype_5d || def_mba23_mtype_6c || def_mba23_mtype_7c);# || def_mba23_mtype_8c); -define def_mba23_subtype_C = (def_mba23_mtype_1c || def_mba23_mtype_2c || def_mba23_mtype_3c || def_mba23_mtype_4c || def_mba23_mtype_5c || def_mba23_mtype_5d || def_mba23_mtype_6c || def_mba23_mtype_7c );# || def_mba23_mtype_8c); - -define def_mba01_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated = (def_mba01_1a_1socket ||def_mba01_1b_1socket ||def_mba01_1c_1socket ||def_mba01_2a_1socket ||def_mba01_2a_1socket_ddr4 ||def_mba01_2b_1socket ||def_mba01_2b_1socket_ddr4 ||def_mba01_2c_1socket ||def_mba01_2c_1socket_ddr4 ||def_mba01_3a_1socket ||def_mba01_3a_1socket_ddr4 ||def_mba01_3b_1socket ||def_mba01_3c_1socket_ddr4 ||def_mba01_5b_1socket ||def_mba01_5c_1socket ||def_mba01_5d_1socket ||def_mba01_7a_1socket ||def_mba01_7b_1socket ||def_mba01_7c_1socket ||def_mba01_7a_1socket_ddr4 ||def_mba01_7b_1socket_ddr4 ||def_mba01_7c_1socket_ddr4); -define def_mba01_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mba01_1a_2socket ||def_mba01_1b_2socket ||def_mba01_1c_2socket ||def_mba01_2a_2socket ||def_mba01_2a_2socket_ddr4 ||def_mba01_2b_2socket ||def_mba01_2b_2socket_ddr4 ||def_mba01_2c_2socket ||def_mba01_2c_2socket_ddr4 ||def_mba01_3a_2socket ||def_mba01_3a_2socket_ddr4 ||def_mba01_3b_2socket ||def_mba01_3c_2socket_ddr4 ||def_mba01_5b_2socket ||def_mba01_5c_2socket ||def_mba01_5d_2socket ||def_mba01_7a_2socket ||def_mba01_7b_2socket ||def_mba01_7c_2socket ||def_mba01_7a_2socket_ddr4 ||def_mba01_7b_2socket_ddr4 ||def_mba01_7c_2socket_ddr4 ||def_mba01_1c_cdimm ||def_mba01_3a_cdimm ||def_mba01_3b_cdimm ||def_mba01_3c_cdimm ||def_mba01_3a_ddr4_cdimm ||def_mba01_3b_ddr4_cdimm ||def_mba01_3c_ddr4_cdimm ||def_mba01_4a_cdimm ||def_mba01_4a_ddr4_cdimm ||def_mba01_4b_ddr4_cdimm ||def_mba01_4c_ddr4_cdimm); -#define def_mba01_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mba01_1a_2socket ||def_mba01_1b_2socket ||def_mba01_1c_2socket ||def_mba01_2a_2socket ||def_mba01_2a_2socket_ddr4 ||def_mba01_2b_2socket ||def_mba01_2b_2socket_ddr4 ||def_mba01_2c_2socket ||def_mba01_2c_2socket_ddr4 ||def_mba01_3a_2socket ||def_mba01_3a_2socket_ddr4 ||def_mba01_3b_2socket ||def_mba01_3c_2socket_ddr4 ||def_mba01_5b_2socket ||def_mba01_5c_2socket ||def_mba01_5d_2socket ||def_mba01_7a_2socket ||def_mba01_7b_2socket ||def_mba01_7c_2socket ||def_mba01_7a_2socket_ddr4 ||def_mba01_7b_2socket_ddr4 ||def_mba01_7c_2socket_ddr4 ||def_mba01_1b_cdimm ||def_mba01_1c_cdimm ||def_mba01_3a_cdimm ||def_mba01_3b_cdimm ||def_mba01_3c_cdimm ||def_mba01_3a_ddr4_cdimm ||def_mba01_3b_ddr4_cdimm ||def_mba01_3c_ddr4_cdimm ||def_mba01_4a_cdimm ||def_mba01_4a_ddr4_cdimm ||def_mba01_4b_ddr4_cdimm ||def_mba01_4c_ddr4_cdimm); - -define def_mba23_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated = (def_mba23_1a_1socket ||def_mba23_1b_1socket ||def_mba23_1c_1socket ||def_mba23_2a_1socket ||def_mba23_2a_1socket_ddr4 ||def_mba23_2b_1socket ||def_mba23_2b_1socket_ddr4 ||def_mba23_2c_1socket ||def_mba23_2c_1socket_ddr4 ||def_mba23_3a_1socket ||def_mba23_3a_1socket_ddr4 ||def_mba23_3b_1socket ||def_mba23_3c_1socket_ddr4 ||def_mba23_5b_1socket ||def_mba23_5c_1socket ||def_mba23_5d_1socket ||def_mba23_7a_1socket ||def_mba23_7b_1socket ||def_mba23_7c_1socket ||def_mba23_7a_1socket_ddr4 ||def_mba23_7b_1socket_ddr4 ||def_mba23_7c_1socket_ddr4); -#define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mba23_1a_2socket ||def_mba23_1b_2socket ||def_mba23_1c_2socket ||def_mba23_2a_2socket ||def_mba23_2a_2socket_ddr4 ||def_mba23_2b_2socket ||def_mba23_2b_2socket_ddr4 ||def_mba23_2c_2socket ||def_mba23_2c_2socket_ddr4 ||def_mba23_3a_2socket ||def_mba23_3a_2socket_ddr4 ||def_mba23_3b_2socket ||def_mba23_3c_2socket_ddr4 ||def_mba23_5b_2socket ||def_mba23_5c_2socket ||def_mba23_5d_2socket ||def_mba23_7a_2socket ||def_mba23_7b_2socket ||def_mba23_7c_2socket ||def_mba23_7a_2socket_ddr4 ||def_mba23_7b_2socket_ddr4 ||def_mba23_7c_2socket_ddr4 ||def_mba23_1b_cdimm ||def_mba23_1c_cdimm ||def_mba23_3a_cdimm ||def_mba23_3b_cdimm ||def_mba23_3c_cdimm ||def_mba23_3a_ddr4_cdimm ||def_mba23_3b_ddr4_cdimm ||def_mba23_3c_ddr4_cdimm ||def_mba23_4a_cdimm ||def_mba23_4a_ddr4_cdimm ||def_mba23_4b_ddr4_cdimm ||def_mba23_4c_ddr4_cdimm); -define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mba23_1a_2socket ||def_mba23_1b_2socket ||def_mba23_1c_2socket ||def_mba23_2a_2socket ||def_mba23_2a_2socket_ddr4 ||def_mba23_2b_2socket ||def_mba23_2b_2socket_ddr4 ||def_mba23_2c_2socket ||def_mba23_2c_2socket_ddr4 ||def_mba23_3a_2socket ||def_mba23_3a_2socket_ddr4 ||def_mba23_3b_2socket ||def_mba23_3c_2socket_ddr4 ||def_mba23_5b_2socket ||def_mba23_5c_2socket ||def_mba23_5d_2socket ||def_mba23_7a_2socket ||def_mba23_7b_2socket ||def_mba23_7c_2socket ||def_mba23_7a_2socket_ddr4 ||def_mba23_7b_2socket_ddr4 ||def_mba23_7c_2socket_ddr4 ||def_mba23_1c_cdimm ||def_mba23_3a_cdimm ||def_mba23_3b_cdimm ||def_mba23_3c_cdimm ||def_mba23_3a_ddr4_cdimm ||def_mba23_3b_ddr4_cdimm ||def_mba23_3c_ddr4_cdimm ||def_mba23_4a_cdimm ||def_mba23_4a_ddr4_cdimm ||def_mba23_4b_ddr4_cdimm ||def_mba23_4c_ddr4_cdimm); - -## Temp defines until the code adds these attributes - - - - -# Define the number of ranks per MBS (2 MBAs) for L4 Cleaner setup -#define def_mba01_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[0][1]); -#define def_mba23_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); -define def_num_mbs_ranks = (MBA0.ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + MBA0.ATTR_EFF_NUM_RANKS_PER_DIMM[0][1] + MBA1.ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + MBA1.ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); -define def_num_mba01_ranks = (MBA0.ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + MBA0.ATTR_EFF_NUM_RANKS_PER_DIMM[0][1]); -define def_num_mba23_ranks = (MBA1.ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + MBA1.ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]); - - - - -#--****************************************************************************** -#-- MBS FIR MASK Register -#--****************************************************************************** -# scom 0x02011403 { -# bits , scom_data ; -# 8 , 0b1 ; # int_parity_error - HW244827 and HW251643 -# -# } - -#--****************************************************************************** -#-- TRACE clock stop on checkstop MBA -#--****************************************************************************** -# TCM.EPS.DBG.DBG_MODE_REG - scom 0x03012300 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 7 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741 == 1); # EC2.0 or greater enable - } - -# TCM.EPS.DBG.DBG_TRACE_MODE_REG_2 - scom 0x0301230B { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 17 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741 == 1); # EC2.0 or greater enable - } - - - -#--****************************************************************************** -#-- TRACE clock stop on checkstop MBS -#--****************************************************************************** -# TCN.EPS.DBG.DBG_MODE_REG - scom 0x02012300 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 7 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741 == 1); # EC2.0 or greater enable - } - -# TCN.EPS.DBG.DBG_TRACE_MODE_REG_2 - scom 0x0201230B { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 17 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_ARRAY_CLKSTOP_ON_XSTOP_FW624741 == 1); # EC2.0 or greater enable - } - -#--****************************************************************************** -# HW246685 : Need RCE FIR bit if NCE/SCE/MPE/MCE on 2nd try -# - Want to be able to see RCE reported even if we also have chip marks or symbol marks in place. -# - To enable maint fix: set MBSTR(60)=1 to see the RCE in conjunction with the other errors -# - To enable mainline fix: set MBSECC(16)=1 to see the RCE in conjunction with the other errors -#--****************************************************************************** - -# MBS01_MBSTRQ - scom 0x02011655 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 60 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 == 1); # cfg_maint_rce_with_ce - } - -# MBS23_MBSTRQ - scom 0x02011755 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 60 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 == 1); # cfg_maint_rce_with_ce - } - -# MBU.MBS.ECC0.MBSECCQ - scom 0x0201144A { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 16 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 == 1); # Report RCE on corrections - } - -# MBU.MBS.ECC1.MBSECCQ - scom 0x0201148A { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 16 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 == 1); # Report RCE on corrections - } - - -#--****************************************************************************** -# TRACE_TRCTRL_CONFIG Trace Control Configuration Register -# -# HW259719 - lcl_clk_gate_ctrl needs to be turned on and left on -# DD2 fixed ONLY -#--****************************************************************************** - -# MBI trace -scom 0x02010C42 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:63 , 0x000C000000000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl -} -# MBS1 trace -scom 0x02011882 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:63 , 0x000C000000000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl -} -# MBS2 trace -scom 0x020118C2 { - bits , scom_data , ATTR_FUNCTIONAL, expr; - 0:63 , 0x000C000000000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl -} - -# YCT added for Irving -#--****************************************************************************** -#-- MBI Configuration Register -#--****************************************************************************** - scom 0x000000000201080A { - bits , scom_data ; - 0 , 0b0 ; # MBICFGQ_FORCE_CHANNEL_FAIL - 1 , 0b0 ; # MBICFGQ_REPLAY_CRC_DISABLE - 2 , 0b0 ; # MBICFGQ_REPLAY_NOACK_DISABLE - 3 , 0b0 ; # MBICFGQ_REPLAY_OUTOFORDER_DISABLE - 4 , 0b0 ; # MBICFGQ_FORCE_LFSR_REPLAY - 5 , 0b0 ; # MBICFGQ_CRC_CHECK_DISABLE - 6 , 0b0 ; # MBICFGQ_ECC_CHECK_DISABLE - 7 , 0b0 ; # MBICFGQ_START_FRAME_LOCK - 8 , 0b0 ; # MBICFGQ_FORCE_FRTL - 9 , 0b0 ; # MBICFGQ_AUTO_FRTL_DISABLE - 10:16, 0b0000000 ; # MBICFGQ_MANUAL_FRTL_VALUE - 17 , 0x0 ; # MBICFGQ_MANUAL_FRTL_DONE - 18 , 0b0 ; # MBICFGQ_ECC_CORRECT_DISABLE - 19 , 0b0 ; # MBICFGQ_SPARE1 - 20 , 0b0 ; # MBICFGQ_LANE_VOTING_BYPASS - 21:25, 0b00000 ; # MBICFGQ_BAD_LANE_VALUE - 26 , 0b0 ; # MBICFGQ_BAD_LANE_VOTING_DISABLE - 27:32, 0b010010 ; # MBICFGQ_NO_FORWARD_PROGRESS_TIMEOUT_VALUE (0x12 = 18 => 2ms) - 33:34, 0b00 ; # MBICFGQ_PERFORMANCE_DEGRADATION_PERCENT_SELECT - 35:36, 0b00 ; # MBICFGQ_CHANNEL_INITIALIZATION_STATE_MACHINE_TIMEOUT_VALUE - 37 , 0b0 ; # MBICFGQ_RESET_KEEPER - 38 , 0b0 ; # MBICFGQ_FAULT_LINE_ERROR_ENABLE - 39:43, 0b00000 ; # MBICFGQ_RESERVED - - } - -###################### -# temp VBU settings # -###################### - -# Name = MBU.MBS.ECC01 (scomdef) -# MBSECCQ MBS Memory ECC Control Register (01) -scom 0x0201144A { - bits, scom_data , MBA0.ATTR_FUNCTIONAL, expr ; - 0 , 0b1 , 1 , any ; # disable mba01 memory ecc check/correct -} - -# Name = MBU.MBS.ECC23 (scomdef) -# MBSECCQ MBS Memory ECC Control Register (23) -scom 0x0201148A { - bits, scom_data , MBA1.ATTR_FUNCTIONAL, expr ; - 0 , 0b1 , 1 , any ; # disable MBA23 memory ecc check/correct -} - -###################### -# MBS Configuration # -###################### - -# MBS OCC Idle Threshold count Regsiter -# B0.C0.M00A.CEN.MBU.MBS.MBSOCCITCQ(0:63) = 0x0000000600000000 -# added to match dials -MW -scom 0x02011428 { - scom_data ; - 0x0000000600000000 ; -} - - - -# Name = MBU.MBS (scomdef) -# MBSCFGQ MBS Configuration Register -scom 0x02011411 { - bits, scom_data , expr; - 0 , 0b0 , any ; # MBSCFGQ_eccbp_exit_sel - 1 , 0b0 , any ; # MBSCFGQ_dram_ecc_bypass_dis -} - -# Name = MBU.MBS (scomdef) -# MBCCFGQ MBC Configuration Register -scom 0x0201140F { - bits, scom_data , expr; - 0 , 0b0 , (L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0); # MBCCFGQ_cache_enable - 0 , 0b1 , (L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0); # MBCCFGQ_cache_enable - 1 , 0b0 , any ; # MBCCFGQ_cfg_dyn_whap_en - 2 , 0b0 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBCCFGQ_cleaner_enable - 2 , 0b1 , ((SYS.ATTR_MSS_CLEANER_ENABLE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBCCFGQ_cleaner_enable - 3 , 0b0 , any ; # MBCCFGQ_cache_only_enable - 4 , 0b0 , any ; # MBCCFGQ_lru_dmap_en - 5 , 0b0 , any ; # MBCCFGQ_lru_random_en - 6 , 0b0 , any ; # MBCCFGQ_lru_single_mem_en - 7 , 0b1 , any ; # MBCCFGQ_cfg_srw_delete_ue_en # SW252733 : L4 Cache UE Handling - 8 , 0b0 , any ; # MBCCFGQ_srw_line_delete_next_ce_en - 9 , 0b0 , any ; # MBCCFGQ_only_log_ecc_ue - 10 , 0b0 , any ; # MBCCFGQ_only_log_ecc_ce - 11 , 0b0 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 1); # MBCCFGQ_srw_prefetch_dis - 11 , 0b1 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 0); # MBCCFGQ_srw_prefetch_dis - 12 , 0b0 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 1); # MBCCFGQ_prq_prefetch_dis - 12 , 0b1 , (SYS.ATTR_MSS_PREFETCH_ENABLE == 0); # MBCCFGQ_prq_prefetch_dis - #13:16 , 0xE , any ; # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 - #17:22 , 0x1F , any ; # MBCCFGQ_cln_wrq_tgt_alloc_0_5 - #23:28 , 0x7 , any ; # MBCCFGQ_cln_wr_priority_wrq_hwmark_0_5 - #29:34 , 0x6 , any ; # MBCCFGQ_cln_wr_priority_wrq_lwmark_0_5 - #35:48 , 0x1000 , any ; # MBCCFGQ_cln_wr_priority_dv_hwmark_0_13 - #49:62 , 0x0FC0 , any ; # MBCCFGQ_cln_wr_priority_dv_lwmark_0_13 - 23:28 , 0b000111 , any ; # MBCCFGQ_cln_wr_priority_wrq_hwmark_0_5 is 7 for all rank groups - 29:34 , 0b000110 , any ; # MBCCFGQ_cln_wr_priority_wrq_lwmark_0_5 is 6 for all rank groups - 35:48 , 0b00001000000000 , any ; # MBCCFGQ_cln_wr_priority_dv_hwmark_0_13 is 512 for all rank groups - 49:62 , 0b00000111110000 , any ; # MBCCFGQ_cln_wr_priority_dv_lwmark_0_13 is 512-16 for all rank groups -} - - -scom 0x0201140F { - bits, scom_data , MBA0.ATTR_FUNCTIONAL, MBA1.ATTR_FUNCTIONAL, expr; - 13:16 , 0b1111 , 1 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && ((def_num_mbs_ranks == 2 ) || (def_num_mbs_ranks == 4)); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 15 for 2 and 4 rnkgrp - 13:16 , 0b0111 , 1 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 8 ); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 7 for 8 rnkgrp - 13:16 , 0b1111 , 1 , 0 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && ((def_num_mba01_ranks == 1 ) || (def_num_mba01_ranks == 2)); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 15 for 2 and 4 rnkgrp - 13:16 , 0b0111 , 1 , 0 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba01_ranks == 4 ); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 7 for 8 rnkgrp - 13:16 , 0b1111 , 0 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && ((def_num_mba23_ranks == 1 ) || (def_num_mba23_ranks == 2)); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 15 for 2 and 4 rnkgrp - 13:16 , 0b0111 , 0 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba23_ranks == 4 ); # MBCCFGQ_cln_page_mode_bundle_max_cnt_0_3 is 7 for 8 rnkgrp - 17:22 , 0b100000 , 1 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 2 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp - 17:22 , 0b100000 , 1 , 0 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba01_ranks == 1 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp - 17:22 , 0b100000 , 0 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba23_ranks == 1 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp - 17:22 , 0b010000 , 1 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 4 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 16 for 4 rnkgrp - 17:22 , 0b010000 , 1 , 0 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba01_ranks == 2 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp - 17:22 , 0b010000 , 0 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba23_ranks == 2 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp - 17:22 , 0b001000 , 1 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mbs_ranks == 8 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 8 for 8 rnkgrp - 17:22 , 0b001000 , 1 , 0 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba01_ranks == 4 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp - 17:22 , 0b001000 , 0 , 1 , (SYS.ATTR_MSS_CLEANER_ENABLE == 1) && (def_num_mba23_ranks == 4 ); # MBCCFGQ_cln_wrq_tgt_alloc_0_5 is 32 for 2 rnkgrp -} - -######################################## -#MBA Swizzle Control Register (MBAXCRMS) -######################################## - -# Name = MBU.MBS.ARB.MBAXCRMS (scomdef) -# MBA Swizzle Control Register (MBAXCRMS) - - -scom 0x0201140D { - bits, scom_data , MBA0.ATTR_FUNCTIONAL, MBA1.ATTR_FUNCTIONAL, expr; - 0:2 , 0b000 , 1 , 0 , any; # MBA01_master_rank_0_select is 0 for all cfgs - 0:2 , 0b000 , 1 , 1 , any; # MBA01_master_rank_0_select is 0 for all cfgs - 3:5 , 0b001 , 1 , 0 , any; # MBA01_master_rank_1_select is 1 for all cfgs - 3:5 , 0b001 , 1 , 1 , any; # MBA01_master_rank_1_select is 1 for all cfgs - 6:8 , 0b010 , 1 , 0 , any; # MBA01_master_rank_2_select is 2 for all cfgs - 6:8 , 0b010 , 1 , 1 , any; # MBA01_master_rank_2_select is 2 for all cfgs - 24:26 , 0b000 , 0 , 1 , any; # MBA23_master_rank_0_select is 0 for all cfgs - 24:26 , 0b000 , 1 , 1 , any; # MBA23_master_rank_0_select is 0 for all cfgs - 27:29 , 0b001 , 0 , 1 , any; # MBA23_master_rank_1_select is 1 for all cfgs - 27:29 , 0b001 , 1 , 1 , any; # MBA23_master_rank_1_select is 1 for all cfgs - 30:32 , 0b010 , 0 , 1 , any; # MBA23_master_rank_2_select is 2 for all cfgs - 30:32 , 0b010 , 1 , 1 , any; # MBA23_master_rank_2_select is 2 for all cfgs -} - - - -######################################## -# MBA address interleave bit selection # -######################################## - -# Name = MBU.MBS.ARB.RXLT (scomdef) -# MBSXCRQ MBS Address Translate Control Register -# address interleave mode -scom 0x0201140A { - bits, scom_data ,MBA0.ATTR_FUNCTIONAL, MBA1.ATTR_FUNCTIONAL, expr; - 0:4 , 0b00000 , 0 , 0 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 0) ; # no MBA interleave - 0:4 , 0b00000 , 0 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 0) ; # no MBA interleave - 0:4 , 0b00000 , 1 , 0 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 0) ; # no MBA interleave - 0:4 , 0b10000 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 23); # - 0:4 , 0b10001 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 24); # - 0:4 , 0b10010 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 25); # - 0:4 , 0b10011 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 26); # - 0:4 , 0b10100 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 27); # - 0:4 , 0b10101 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 28); # - 0:4 , 0b10110 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 29); # - 0:4 , 0b10111 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 30); # - 0:4 , 0b11000 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 31); # - 0:4 , 0b11001 , 1 , 1 ,(ATTR_MSS_DERIVED_MBA_ADDR_INTERLEAVE_BIT == 32); # -} - -scom 0x0201140A { - bits, scom_data , expr; - 5 , 0b0 , any ; # Z mode only -} - -# Hash mode Selection -# Select hash mode with most interleaving (higher hash number) -# Section 5.6 in centuar workbook for hashing -# MBA01 Type 1A - simplied table to hash mode 1 when both dimm configured -define def_mba01_hash1_type1a = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1) || (MBA0.ATTR_EFF_IBM_TYPE[0][1] == 1)) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] != 0) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] != 0); -define def_mba01_hash0_type1a = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1) || (MBA0.ATTR_EFF_IBM_TYPE[0][1] == 1)) && ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0) || (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0)); -# Type 1B/5B - simplied table to hash mode 2 when both dimm configured and hash mode 1 when 1 dimm is configured -define def_mba01_hash2_type1b_5b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15)) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] != 0) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] != 0); -define def_mba01_hash1_type1b_5b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15)) && ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0) || (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0)); -# Type 1D/5C - simplied table to hash mode 2 for all cfgs -define def_mba01_hash2_type1d_5c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16)); -# Type 2A - simplied table to hash mode 1 when both dimm configured and hash mode 0 when 1 dimm is configured -define def_mba01_hash1_type2a = (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] != 0) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] != 0); -define def_mba01_hash0_type2a = (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5) && ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0) || (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0)); -# Type 2B - simplied table to hash mode 0 for all cfgs -define def_mba01_hash0_type2b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6)); -# Type 3A/7A - simplied table to hash mode 1 for all cfgs -define def_mba01_hash1_type3a_7a = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21)); -# Type 3B/7B - simplied table to hash mode 0 for all cfgs -define def_mba01_hash0_type3b_7b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22)); -# Type 2C - simplied table to hash mode 0 for all cfgs -define def_mba01_hash0_type2c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7)); -# Type 3C/7C - simplied table to hash mode 0 for all cfgs -define def_mba01_hash0_type3c_7c = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23)); - - -# MBA23 Type 1A - simplied table to hash mode 1 when both dimm configured -define def_mba23_hash1_type1a = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1) || (MBA1.ATTR_EFF_IBM_TYPE[1][1] == 1)) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] != 0) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] != 0); -define def_mba23_hash0_type1a = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1) || (MBA1.ATTR_EFF_IBM_TYPE[1][1] == 1)) && ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0) || (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0)); -# Type 1B/5B - simplied table to hash mode 2 when both dimm configured and hash mode 1 when 1 dimm is configured -define def_mba23_hash2_type1b_5b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15)) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] != 0) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] != 0); -define def_mba23_hash1_type1b_5b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15)) && ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0) || (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0)); -# Type 1D/5C - simplied table to hash mode 2 for all cfgs -define def_mba23_hash2_type1d_5c = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 16)); -# Type 2A - simplied table to hash mode 1 when both dimm configured and hash mode 0 when 1 dimm is configured -define def_mba23_hash1_type2a = (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] != 0) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] != 0); -define def_mba23_hash0_type2a = (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5) && ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0) || (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0)); -# Type 2B - simplied table to hash mode 0 for all cfgs -define def_mba23_hash0_type2b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6)); -# Type 3A/7A - simplied table to hash mode 1 for all cfgs -define def_mba23_hash1_type3a_7a = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21)); -# Type 3B/7B - simplied table to hash mode 0 for all cfgs -define def_mba23_hash0_type3b_7b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22)); -# Type 2C - simplied table to hash mode 0 for all cfgs -define def_mba23_hash0_type2c = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7)); -# Type 3C/7C - simplied table to hash mode 0 for all cfgs -define def_mba23_hash0_type3c_7c = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23)); - -define def_mba01_hash0_sel = (def_mba01_hash0_type1a) ||(def_mba01_hash0_type2a) ||(def_mba01_hash0_type2b) ||(def_mba01_hash0_type2c) ||(def_mba01_hash0_type3b_7b) ||(def_mba01_hash0_type3c_7c) ; -define def_mba01_hash1_sel = (def_mba01_hash1_type1a) ||(def_mba01_hash1_type1b_5b) ||(def_mba01_hash1_type2a) ||(def_mba01_hash1_type3a_7a) ; -define def_mba01_hash2_sel = (def_mba01_hash2_type1b_5b) ||(def_mba01_hash2_type1d_5c) ; - -define def_mba23_hash0_sel = (def_mba23_hash0_type1a) ||(def_mba23_hash0_type2a) ||(def_mba23_hash0_type2b) ||(def_mba23_hash0_type2c) ||(def_mba23_hash0_type3b_7b) ||(def_mba23_hash0_type3c_7c) ; -define def_mba23_hash1_sel = (def_mba23_hash1_type1a) ||(def_mba23_hash1_type1b_5b) ||(def_mba23_hash1_type2a) ||(def_mba23_hash1_type3a_7a) ; -define def_mba23_hash2_sel = (def_mba23_hash2_type1b_5b) ||(def_mba23_hash2_type1d_5c) ; - -#################################### -# MBA01 address translation config # -#################################### - -# Name = MBU.MBS.ARB.RXLT (scomdef) -# MBU.MBS.ARB.RXLT.MBAXCR01Q_MBA01_CONFIG_TYPE from (edial spydef) -# MBAXCR01Q MBA01 Address Translate Control Register -# - -scom 0x0201140B { - bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; - 0:3 , 0b0000 , 1 , (def_mba01_nomem == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0001 , 1 , (def_mba01_type1_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0010 , 1 , (def_mba01_type2_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0011 , 1 , (def_mba01_type3_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0100 , 1 , (def_mba01_type4_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0101 , 1 , (def_mba01_type5_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0110 , 1 , (def_mba01_type6_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D - 0:3 , 0b0111 , 1 , (def_mba01_type7_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D -# 0:3 , 0b1000 , 1 , (def_mba01_type8_memory_populated_behind_MBA01 == 1); # MBAXCR01Q_MBA01_config_type D -# 4:5 , 0b01 , 1 , any ; # temp until ibm type is fully supported # MBAXCR01Q_MBA01_config_subtype D - 4:5 , 0b00 , 1 , (def_mba01_subtype_A == 1); # MBAXCR01Q_MBA01_config_subtype D - 4:5 , 0b01 , 1 , (def_mba01_subtype_B == 1); # MBAXCR01Q_MBA01_config_subtype D - 4:5 , 0b10 , 1 , (def_mba01_subtype_C == 1); # MBAXCR01Q_MBA01_config_subtype D - 6:7 , 0b00 , 1 , (MBA0.ATTR_EFF_DRAM_DENSITY == 2); # MBAXCR01Q_MBA01_DRAM_size D - 6:7 , 0b01 , 1 , (MBA0.ATTR_EFF_DRAM_DENSITY == 4); # MBAXCR01Q_MBA01_DRAM_size D - 6:7 , 0b10 , 1 , (MBA0.ATTR_EFF_DRAM_DENSITY == 8); # MBAXCR01Q_MBA01_DRAM_size D - 8 , 0b0 , 1 , (def_mba01_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated == 1); # MBAXCR01Q_MBA01_Configuration D - 8 , 0b1 , 1 , (def_mba01_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated == 1); # MBAXCR01Q_MBA01_Configuration D -# 8 , 0b0 , 1 , (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1); # MBAXCR01Q_MBA01_Configuration D -# 8 , 0b1 , 1 , (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2); # MBAXCR01Q_MBA01_Configuration D - 9 , 0b1 , 1 , (MBA0.ATTR_EFF_DRAM_WIDTH == 4); # MBAXCR01Q_MBA01_DRAM_Width D - 9 , 0b0 , 1 , (MBA0.ATTR_EFF_DRAM_WIDTH == 8); # MBAXCR01Q_MBA01_DRAM_Width D - 10:11 , 0b00 , 1 , def_mba01_hash0_sel; # MBAXCR01Q_MBA01_Hash_Mode - 10:11 , 0b01 , 1 , def_mba01_hash1_sel; # MBAXCR01Q_MBA01_Hash_Mode - 10:11 , 0b10 , 1 , def_mba01_hash2_sel; # MBAXCR01Q_MBA01_Hash_Mode -# 10:11 , 0b00 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 0); # MBAXCR01Q_MBA01_Hash_Mode -# 10:11 , 0b01 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 1); # MBAXCR01Q_MBA01_Hash_Mode -# 10:11 , 0b10 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 2); # MBAXCR01Q_MBA01_Hash_Mode - 12 , 0b0 , 1 , ((ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBAXCR01Q_MBA01_Interleave_Mode - 12 , 0b1 , 1 , ((ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBAXCR01Q_MBA01_Interleave_Mod -} - - -#################################### -# MBA23 address translation config # -#################################### - -# Name = MBU.MBS.ARB.RXLT (scomdef) -# MBU.MBS.ARB.RXLT.MBAXCR01Q_MBA23_CONFIG_TYPE from (edial spydef) -# MBAXCR23Q MBA23 Address Translate Control Register -# -scom 0x0201140C { - bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; - 0:3 , 0b0000 , 1 , (def_mba23_nomem == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0001 , 1 , (def_mba23_type1_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0010 , 1 , (def_mba23_type2_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0011 , 1 , (def_mba23_type3_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0100 , 1 , (def_mba23_type4_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0101 , 1 , (def_mba23_type5_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0110 , 1 , (def_mba23_type6_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D - 0:3 , 0b0111 , 1 , (def_mba23_type7_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D -# 0:3 , 0b1000 , 1 , (def_mba23_type8_memory_populated_behind_MBA23 == 1); # MBAXCR01Q_MBA23_config_type D -# 4:5 , 0b01 , 1 , any ;# temp until ibm type is fully supported # MBAXCR01Q_MBA23_config_subtype D - 4:5 , 0b00 , 1 , (def_mba23_subtype_A == 1); # MBAXCR01Q_MBA23_config_subtype D - 4:5 , 0b01 , 1 , (def_mba23_subtype_B == 1); # MBAXCR01Q_MBA23_config_subtype D - 4:5 , 0b10 , 1 , (def_mba23_subtype_C == 1); # MBAXCR01Q_MBA23_config_subtype D - 6:7 , 0b00 , 1 , (MBA1.ATTR_EFF_DRAM_DENSITY == 2); # MBAXCR01Q_MBA23_DRAM_size D - 6:7 , 0b01 , 1 , (MBA1.ATTR_EFF_DRAM_DENSITY == 4); # MBAXCR01Q_MBA23_DRAM_size D - 6:7 , 0b10 , 1 , (MBA1.ATTR_EFF_DRAM_DENSITY == 8); # MBAXCR01Q_MBA23_DRAM_size D - 8 , 0b0 , 1 , (def_mba23_Centaur_or_Planar_DIMM_with_only_DIMM_slot0_populated == 1); # MBAXCR01Q_MBA23_Configuration D - 8 , 0b1 , 1 , (def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated == 1); # MBAXCR01Q_MBA23_Configuration D -# 8 , 0b0 , 1 , (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1); # MBAXCR01Q_MBA23_Configuration D -# 8 , 0b1 , 1 , (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2); # MBAXCR01Q_MBA23_Configuration D - 9 , 0b1 , 1 , (MBA1.ATTR_EFF_DRAM_WIDTH == 4); # MBAXCR01Q_MBA23_DRAM_Width D - 9 , 0b0 , 1 , (MBA1.ATTR_EFF_DRAM_WIDTH == 8); # MBAXCR01Q_MBA23_DRAM_Width D - 10:11 , 0b00 , 1 , def_mba23_hash0_sel; # MBAXCR01Q_MBA23_Hash_Mode - 10:11 , 0b01 , 1 , def_mba23_hash1_sel; # MBAXCR01Q_MBA23_Hash_Mode - 10:11 , 0b10 , 1 , def_mba23_hash2_sel; # MBAXCR01Q_MBA23_Hash_Mode -# 12 , 0b0 , 1 , any; # -MW match dials # MBAXCR01Q_MBA23_Interleave_Mode - 12 , 0b0 , 1 , ((ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE == 0) || ((L4.ATTR_FUNCTIONAL == 0) || (ATTR_MSS_CACHE_ENABLE == 0))); # MBAXCR01Q_MBA23_Interleave_Mode - 12 , 0b1 , 1 , ((ATTR_MSS_DERIVED_MBA_CACHELINE_INTERLEAVE_MODE == 1) && ((L4.ATTR_FUNCTIONAL == 1) && (ATTR_MSS_CACHE_ENABLE != 0))); # MBAXCR01Q_MBA23_Interleave_Mode -} - - - - -########################################################################################### -# MBS MCBIST SETUP SECTION # -########################################################################################### - -################################### -# MCBIST Fixed data pattern MBA01 -################################### -# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFD[0-7]Q_Q(0:63) (scomdef) -# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDQ_Q(0:63) (scomdef) -# Name = MBA01.MBA_MCBIST.SCOMFIR.MCBFDSPQ_Q(0:63) (scomdef) - -scom 0x02011681 { - bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; - 0:63 , 0x1111111111111111, 1 , any; # Fixed data burst 0 -} - -scom 0x02011682 { - bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; - 0:63 , 0x2222222222222222, 1 , any; # Fixed data burst 1 -} - -scom 0x02011683 { - bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; - 0:63 , 0x3333333333333333, 1 , any; # Fixed data burst 2 -} - -scom 0x02011684 { - bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; - 0:63 , 0x4444444444444444, 1 , any; # Fixed data burst 3 -} - -scom 0x02011685 { - bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; - 0:63 , 0x5555555555555555, 1 , any; # Fixed data burst 4 -} - -scom 0x02011686 { - bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; - 0:63 , 0x6666666666666666, 1 , any; # Fixed data burst 5 -} - -scom 0x02011687 { - bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; - 0:63 , 0x7777777777777777, 1 , any; # Fixed data burst 6 -} - -scom 0x02011688 { - bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; - 0:63 , 0x8888888888888888, 1 , any; # Fixed data burst 7 -} - -scom 0x02011689 { - bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; - 0:63 , 0x9999999999999999, 1 , any; # Fixed data burst 0-7 ECC bits -} - -scom 0x0201168A { - bits , scom_data , MBA0.ATTR_FUNCTIONAL, expr; - 0:63 , 0xAAAAAAAAAAAAAAAA, 1 , any; # Fixed data burst 0-7 SPARE bits -} - - -################################### -# MCBIST Fixed data pattern MBA23 -################################### -# Name = MBA23.MBA_MCBIST.SCOMFIR.MCBFD[0-7]Q_Q(0:63) (scomdef) -# Name = MBA23.MBA_MCBIST.SCOMFIR.MCBFDQ_Q(0:63) (scomdef) -# Name = MBA23.MBA_MCBIST.SCOMFIR.MCBFDSPQ_Q(0:63) (scomdef) - -scom 0x02011781 { - bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; - 0:63 , 0x1111111111111111, 1 , any; # Fixed data burst 0 -} - -scom 0x02011782 { - bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; - 0:63 , 0x2222222222222222, 1 , any; # Fixed data burst 1 -} - -scom 0x02011783 { - bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; - 0:63 , 0x3333333333333333, 1 , any; # Fixed data burst 2 -} - -scom 0x02011784 { - bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; - 0:63 , 0x4444444444444444, 1 , any; # Fixed data burst 3 -} - -scom 0x02011785 { - bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; - 0:63 , 0x5555555555555555, 1 , any; # Fixed data burst 4 -} - -scom 0x02011786 { - bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; - 0:63 , 0x6666666666666666, 1 , any; # Fixed data burst 5 -} - -scom 0x02011787 { - bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; - 0:63 , 0x7777777777777777, 1 , any; # Fixed data burst 6 -} - -scom 0x02011788 { - bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; - 0:63 , 0x8888888888888888, 1 , any; # Fixed data burst 7 -} - -scom 0x02011789 { - bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; - 0:63 , 0x9999999999999999, 1 , any; # Fixed data burst 0-7 ECC bits -} - -scom 0x0201178A { - bits , scom_data , MBA1.ATTR_FUNCTIONAL, expr; - 0:63 , 0xAAAAAAAAAAAAAAAA, 1 , any; # Fixed data burst 0-7 SPARE bits -} - - diff --git a/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile deleted file mode 100644 index 55dd626fe..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.a_x_pci_dmi_fir.scom.initfile +++ /dev/null @@ -1,894 +0,0 @@ -#-- $Id: p8.a_x_pci_dmi_fir.scom.initfile,v 1.14 2015/07/17 16:52:32 jmcgill Exp $ -#------------------------------------------------------------------------------- -#-- -#-- (C) Copyright International Business Machines Corp. 2011 -#-- All Rights Reserved -- Property of IBM -#-- *** *** -#-- -#-- TITLE : p8.a_x_pci_dmi_fir.scom.initfile -#-- DESCRIPTION : Perform base A/X/DMI/PCI base FIR configuration -#-- -#-- OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -#-- -#-------------------------------------------------------------------------------- - -SyntaxVersion = 1 - - -#-------------------------------------------------------------------------------- -#-- Defines -#-------------------------------------------------------------------------------- - -define mcl_enabled = ((ATTR_CHIP_REGIONS_TO_ENABLE[2] & 0x0080000000000000) != 0); -define mcr_enabled = ((ATTR_CHIP_REGIONS_TO_ENABLE[2] & 0x0040000000000000) != 0); - -define xbus_enabled = (ATTR_PROC_X_ENABLE == ENUM_ATTR_PROC_X_ENABLE_ENABLE); -define abus_enabled = (ATTR_PROC_A_ENABLE == ENUM_ATTR_PROC_A_ENABLE_ENABLE); -define pcie_enabled = (ATTR_PROC_PCIE_ENABLE == ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE); - -define trace_on_scom = (ATTR_CHIP_EC_FEATURE_TRACE_CONTROL_ON_SCOM != 0); -define nv_present = (ATTR_CHIP_EC_FEATURE_NV_PRESENT != 0); - -define single_xbus_present = (ATTR_CHIP_EC_FEATURE_SINGLE_XBUS_PRESENT != 0); - -#-------------------------------------------------------------------------------- -#-- SCOM initializations -#-------------------------------------------------------------------------------- - - -#-- IOMC# (DMI) -#-- set base configuration for IOMC FIR, leaving link specific FIR bits *masked* -#-- (will be unmasked by IO training procedure) -#-- IOMC0.BUSCTL.SCOM.FIR_ACTION0_REG -scom 0x02011A06 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (mcl_enabled); -} - -#-- IOMC0.BUSCTL.SCOM.FIR_ACTION1_REG -scom 0x02011A07 { - bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFC000, (mcl_enabled); -} - -#-- IOMC0.BUSCTL.SCOM.FIR_MASK_REG -scom 0x02011A03 { - bits, scom_data, expr; - 0:63, 0xDFFFFFFFFFFFC000, (mcl_enabled); -} - -#-- IOMC1.BUSCTL.SCOM.FIR_ACTION0_REG -scom 0x02011E06 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (mcr_enabled); -} - -#-- IOMC1.BUSCTL.SCOM.FIR_ACTION1_REG -scom 0x02011E07 { - bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFC000, (mcr_enabled); -} - -#-- IOMC1.BUSCTL.SCOM.FIR_MASK_REG -scom 0x02011E03 { - bits, scom_data, expr; - 0:63, 0xDFFFFFFFFFFFC000, (mcr_enabled); -} - -#-- IOMC0 bus initialization/powerdown settings -#-- IOMC0.TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C946002011A3F { - bits, scom_data, expr; - 48:53, 0b000000, (mcl_enabled); -} - -#-- IOMC0.RX3.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008506002011A3F { - bits, scom_data, expr; - 48:53, 0b000000, (mcl_enabled); -} - -#-- IOMC0.TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C944002011A3F { - bits, scom_data, expr; - 48:53, 0b000001, (mcl_enabled); -} - -#-- IOMC0.RX2.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008504002011A3F { - bits, scom_data, expr; - 48:53, 0b000001, (mcl_enabled); -} - -#-- IOMC0.TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C940002011A3F { - bits, scom_data, expr; - 48:53, 0b000010, (mcl_enabled); -} - -#-- IOMC0.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008500002011A3F { - bits, scom_data, expr; - 48:53, 0b000010, (mcl_enabled); -} - -#-- IOMC0.TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C942002011A3F { - bits, scom_data, expr; - 48:53, 0b000011, (mcl_enabled); -} - -#-- IOMC0.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008502002011A3F { - bits, scom_data, expr; - 48:53, 0b000011, (mcl_enabled); -} - -#-- IOMC0 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN -scom 0x800001FF02011A3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (mcl_enabled); -} - -#-- IOMC0 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN -scom 0x800405FF02011A3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (mcl_enabled); -} - -#-- IOMC0 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800929E002011A3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (mcl_enabled); -} - -#-- IOMC0 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800931E002011A3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (mcl_enabled); -} - -#-- IOMC0 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN -scom 0x800801E002011A3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (mcl_enabled); -} - -#-- IOMC0 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800D1DE002011A3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (mcl_enabled); -} - -#-- IOMC0 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800D25E002011A3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (mcl_enabled); -} - -#-- IOMC0 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN -scom 0x800C05E002011A3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (mcl_enabled); -} - -#-- IOMC0 RX_FENCE_PG (broadcast to all groups), set RX_FENCE -scom 0x8009A9E002011A3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (mcl_enabled); -} - -#-- IOMC1 bus initialization/powerdown settings -#-- IOMC1.TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C946002011E3F { - bits, scom_data, expr; - 48:53, 0b000000, (mcr_enabled); -} - -#-- IOMC1.RX3.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008506002011E3F { - bits, scom_data, expr; - 48:53, 0b000000, (mcr_enabled); -} - -#-- IOMC1.TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C944002011E3F { - bits, scom_data, expr; - 48:53, 0b000001, (mcr_enabled); -} - -#-- IOMC1.RX2.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008504002011E3F { - bits, scom_data, expr; - 48:53, 0b000001, (mcr_enabled); -} - -#-- IOMC1.TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C940002011E3F { - bits, scom_data, expr; - 48:53, 0b000010, (mcr_enabled); -} - -#-- IOMC1.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008500002011E3F { - bits, scom_data, expr; - 48:53, 0b000010, (mcr_enabled); -} - -#-- IOMC1.TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C942002011E3F { - bits, scom_data, expr; - 48:53, 0b000011, (mcr_enabled); -} - -#-- IOMC1.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008502002011E3F { - bits, scom_data, expr; - 48:53, 0b000011, (mcr_enabled); -} - -#-- IOMC1 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN -scom 0x800001FF02011E3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (mcr_enabled); -} - -#-- IOMC1 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN -scom 0x800405FF02011E3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (mcr_enabled); -} - -#-- IOMC1 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800929E002011E3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (mcr_enabled); -} - -#-- IOMC1 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800931E002011E3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (mcr_enabled); -} - -#-- IOMC1 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN -scom 0x800801E002011E3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (mcr_enabled); -} - -#-- IOMC1 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800D1DE002011E3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (mcr_enabled); -} - -#-- IOMC1 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800D25E002011E3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (mcr_enabled); -} - -#-- IOMC1 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN -scom 0x800C05E002011E3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (mcr_enabled); -} - -#-- IOMC1 RX_FENCE_PG (broadcast to all groups), set RX_FENCE -scom 0x8009A9E002011E3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (mcr_enabled); -} - - -#-- XBUS IO (EI4) -#-- set base configuration for FIR, leaving link specific FIR bits *masked* -#-- (will be unmasked by IO training procedure) - -#-- X0 -#-- XBUS01.X0.BUSCTL.SCOM.FIR_ACTION0_REG -scom 0x04011006 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- XBUS01.X0.BUSCTL.SCOM.FIR_ACTION1_REG -scom 0x04011007 { - bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFC000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- XBUS01.X0.BUSCTL.SCOM.FIR_MASK_REG -scom 0x04011003 { - bits, scom_data, expr; - 0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X1 -#-- XBUS1.BUSCTL.SCOM.FIR_ACTION0_REG -#-- XBUS01.X1.BUSCTL.SCOM.FIR_ACTION0_REG -scom 0x04011406 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (xbus_enabled); -} - -#-- XBUS1.BUSCTL.SCOM.FIR_ACTION1_REG -#-- XBUS01.X1.BUSCTL.SCOM.FIR_ACTION1_REG -scom 0x04011407 { - bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFC000, (xbus_enabled); -} - -#-- XBUS1.BUSCTL.SCOM.FIR_MASK_REG -#-- XBUS01.X1.BUSCTL.SCOM.FIR_MASK_REG -scom 0x04011403 { - bits, scom_data, expr; - 0:63, 0xDFFFFFFFFFFFC000, (xbus_enabled); -} - -#-- X3 -#-- XBUS23.X0.BUSCTL.SCOM.FIR_ACTION0_REG -scom 0x04011806 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- XBUS23.X0.BUSCTL.SCOM.FIR_ACTION1_REG -scom 0x04011807 { - bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFC000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- XBUS23.X0.BUSCTL.SCOM.FIR_MASK_REG -scom 0x04011803 { - bits, scom_data, expr; - 0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X2 -#-- XBUS23.X1.BUSCTL.SCOM.FIR_ACTION0_REG -scom 0x04011C06 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- XBUS23.X1.BUSCTL.SCOM.FIR_ACTION1_REG -scom 0x04011C07 { - bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFC000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- XBUS23.X1.BUSCTL.SCOM.FIR_MASK_REG -scom 0x04011C03 { - bits, scom_data, expr; - 0:63, 0xDFFFFFFFFFFFC000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- bus powerdown settings -#-- X0 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN -scom 0x800001FF0401103F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X0 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN -scom 0x800405FF0401103F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X0 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800929E00401103F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X0 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800931E00401103F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X0 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN -scom 0x800801E00401103F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X0 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800D1DE00401103F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X0 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800D25E00401103F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X0 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN -scom 0x800C05E00401103F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X0 RX_FENCE_PG (broadcast to all groups), set RX_FENCE -scom 0x8009A9E00401103F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X1 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN -scom 0x800001FF0401143F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (xbus_enabled); -} - -#-- X1 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN -scom 0x800405FF0401143F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (xbus_enabled); -} - -#-- X1 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800929E00401143F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (xbus_enabled); -} - -#-- X1 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800931E00401143F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (xbus_enabled); -} - -#-- X1 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN -scom 0x800801E00401143F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (xbus_enabled); -} - -#-- X1 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800D1DE00401143F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (xbus_enabled); -} - -#-- X1 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800D25E00401143F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (xbus_enabled); -} - -#-- X1 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN -scom 0x800C05E00401143F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (xbus_enabled); -} - -#-- X1 RX_FENCE_PG (broadcast to all groups), set RX_FENCE -scom 0x8009A9E00401143F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (xbus_enabled); -} - -#-- X2 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN -scom 0x800001FF04011C3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X2 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN -scom 0x800405FF04011C3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X2 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800929E004011C3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X2 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800931E004011C3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X2 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN -scom 0x800801E004011C3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X2 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800D1DE004011C3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X2 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800D25E004011C3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X2 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN -scom 0x800C05E004011C3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X2 RX_FENCE_PG (broadcast to all groups), set RX_FENCE -scom 0x8009A9E004011C3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X3 RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN -scom 0x800001FF0401183F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X3 TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN -scom 0x800405FF0401183F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X3 RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800929E00401183F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X3 RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800931E00401183F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X3 RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN -scom 0x800801E00401183F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X3 TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800D1DE00401183F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X3 TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800D25E00401183F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X3 TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN -scom 0x800C05E00401183F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - -#-- X3 RX_FENCE_PG (broadcast to all groups), set RX_FENCE -scom 0x8009A9E00401183F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, ((xbus_enabled) && (!single_xbus_present)); -} - - -#-- XBUS PB (PBEN) -#-- set base configuration for FIR, leaving link specific FIR bits *masked* -#-- (will be unmasked by iovalid procedure) -#-- EN.PB.PBEN.MISC_IO.SCOM.FIR_REG_ACTION0 -scom 0x04010C06 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (xbus_enabled); -} - -#-- EN.PB.PBEN.MISC_IO.SCOM.FIR_REG_ACTION1 -scom 0x04010C07 { - bits, scom_data, expr; - 0:63, 0x9248000000000000, (xbus_enabled); -} - -#-- EN.PB.PBEN.MISC_IO.SCOM.FIR_MASK_REG -scom 0x04010C03 { - bits, scom_data, expr; - 0:63, 0xFFF4F7FFFC000000, (xbus_enabled); -} - -#-- XBUS pervasive LFIR -#-- EN.PB.TPC.EPS.FIR.LOCAL_FIR_ACTION0 -scom 0x04040010 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (xbus_enabled); -} - -#-- EN.PB.TPC.EPS.FIR.LOCAL_FIR_ACTION1 -scom 0x04040011 { - bits, scom_data, expr; - 0:63, 0x8002000000000000, (xbus_enabled); -} - -#-- EN.PB.TPC.EPS.FIR.LOCAL_FIR_MASK -scom 0x0404000D { - bits, scom_data, expr; - 0:63, 0x7FFDFFFFFF800000, (xbus_enabled); -} - -#-- XBUS chiplet XFIR -#-- EN.PB.TPC.FIR_MASK -scom 0x04040002 { - bits, scom_data, expr; - 0:63, 0x203FFFE000000000, (xbus_enabled); -} - -#-- configure chiplet trace arrays to stop on checkstop -scom 0x040107C0 { - bits, scom_data, expr; - 7, 0b1, (xbus_enabled && trace_on_scom); -} - -scom 0x040107CB { - bits, scom_data, expr; - 17, 0b1, (xbus_enabled && trace_on_scom); -} - - -#-- ABUS IO (EDI) / NV IO -#-- set base configuration for FIR, leaving link specific FIR bits *masked* -#-- (will be unsmaked by IO training procedure) -#-- ABUS.BUSCTL.SCOM.FIR_ACTION0_REG -#-- NVBUS0.BUSCTL.SCOM.FIR_ACTION0_REG -scom 0x08010C06 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (abus_enabled); -} - -#-- ABUS.BUSCTL.SCOM.FIR_ACTION1_REG -#-- NVBUS0.BUSCTL.SCOM.FIR_ACTION1_REG -scom 0x08010C07 { - bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFC000, (abus_enabled); -} - -#-- ABUS.BUSCTL.SCOM.FIR_MASK_REG -#-- NVBUS0.BUSCTL.SCOM.FIR_MASK_REG -scom 0x08010C03 { - bits, scom_data, expr; - 0:63, 0xDFFFFFFFFFFFC000, (abus_enabled) && (!nv_present); - 0:63, 0x1FFFFFFFFFFFC000, (abus_enabled) && (nv_present); -} - -#-- NVBUS1.BUSCTL.SCOM.FIR_ACTION0_REG -scom 0x08010C46 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (abus_enabled) && (nv_present); -} - -#-- NVBUS1.BUSCTL.SCOM.FIR_ACTION1_REG -scom 0x08010C47 { - bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFC000, (abus_enabled) && (nv_present); -} - -#-- NVBUS1.BUSCTL.SCOM.FIR_MASK_REG -scom 0x08010C43 { - bits, scom_data, expr; - 0:63, 0x1FFFFFFFFFFFC000, (abus_enabled) && (nv_present); -} - -#-- ABUS bus initialization/powerdown settings -#-- ABUS.TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C940008010C3F { - bits, scom_data, expr; - 48:53, 0b000001, (abus_enabled) && (!nv_present); -} - -#-- ABUS.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008500008010C3F { - bits, scom_data, expr; - 48:53, 0b000001, (abus_enabled) && (!nv_present); -} - -#-- ABUS.TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C942008010C3F { - bits, scom_data, expr; - 48:53, 0b000010, (abus_enabled) && (!nv_present); -} - -#-- ABUS.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008502008010C3F { - bits, scom_data, expr; - 48:53, 0b000010, (abus_enabled) && (!nv_present); -} - -#-- ABUS.TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C944008010C3F { - bits, scom_data, expr; - 48:53, 0b000011, (abus_enabled) && (!nv_present); -} - -#-- ABUS.RX2.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008504008010C3F { - bits, scom_data, expr; - 48:53, 0b000011, (abus_enabled) && (!nv_present); -} - -#-- ABUS RX_MODE_PL (broadcast to all groups/lanes), set RX_LANE_PDWN -scom 0x800001FF08010C3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (abus_enabled) && (!nv_present); -} - -#-- ABUS TX_MODE_PL (broadcast to all groups/lanes), set TX_LANE_PDWN -scom 0x800405FF08010C3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (abus_enabled) && (!nv_present); -} - -#-- ABUS RX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800929E008010C3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (abus_enabled) && (!nv_present); -} - -#-- ABUS RX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800931E008010C3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (abus_enabled) && (!nv_present); -} - -#-- ABUS RX_CLK_MODE_PG (broadcast to all groups), set RX_CLK_PDWN -scom 0x800801E008010C3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (abus_enabled) && (!nv_present); -} - -#-- ABUS TX_LANE_DISABLED_VEC_0_15_PG (broadcast to all groups), disable all -scom 0x800D1DE008010C3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (abus_enabled) && (!nv_present); -} - -#-- ABUS TX_LANE_DISABLED_VEC_16_31_PG (broadcast to all groups), disable all -scom 0x800D25E008010C3F { - bits, scom_data, expr; - 0:63, 0x000000000000FFFF, (abus_enabled) && (!nv_present); -} - -#-- ABUS TX_CLK_MODE_PG (broadcast to all groups), set TX_CLK_PDWN -scom 0x800C05E008010C3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (abus_enabled) && (!nv_present); -} - -#-- ABUS RX_FENCE_PG (broadcast to all groups), set RX_FENCE -scom 0x8009A9E008010C3F { - bits, scom_data, expr; - 0:63, 0x0000000000008000, (abus_enabled) && (!nv_present); -} - -#-- ABUS PB (PBES) -#-- set base configuration for FIR, leaving link specific FIR bits *masked* -#-- (will be unmasked by iovalid procedure) -#-- ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_ACTION0_REG -scom 0x08010806 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (abus_enabled) && (!nv_present); -} - -#-- ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_ACTION1_REG -scom 0x08010807 { - bits, scom_data, expr; - 0:63, 0x0249861800000000, (abus_enabled) && (!nv_present); -} - -#-- ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_MASK_REG -scom 0x08010803 { - bits, scom_data, expr; - 0:63, 0xFFFFFFFFFC000000, (abus_enabled) && (!nv_present); -} - -#-- ABUS pervasive LFIR -#-- ES.PBES_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION0 -scom 0x08040010 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (abus_enabled); -} - -#-- ES.PBES_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1 -scom 0x08040011 { - bits, scom_data, expr; - 0:63, 0x8000000000000000, (abus_enabled); -} - -#-- ES.PBES_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_MASK -scom 0x0804000D { - bits, scom_data, expr; - 0:63, 0x7FFFFFFFFF800000, (abus_enabled); -} - -#-- ABUS chiplet XFIR -#-- ES.PBES_WRAP_TOP.TPC.FIR_MASK -scom 0x08040002 { - bits, scom_data, expr; - 0:63, 0x23FFFFE000000000, (abus_enabled) && (!nv_present); - 0:63, 0x20FFFFE000000000, (abus_enabled) && (nv_present); -} - -#-- configure chiplet trace arrays to stop on checkstop -scom 0x080107C0 { - bits, scom_data, expr; - 7, 0b1, (abus_enabled && trace_on_scom); -} - -scom 0x080107CB { - bits, scom_data, expr; - 17, 0b1, (abus_enabled && trace_on_scom); -} - - -#-- FBUS PB -#-- set base configuration for FIR, leaving link specific FIR bits *masked* -#-- ES.PBES_WRAP_TOP.PBES_TOP.MISC_IOF.SCOM.PB_IOF_FIR_ACTION0_REG -scom 0x09010806 { - bits, scom_data, expr; - 0:63, 0xFE082030FE082030, (pcie_enabled) && (!nv_present); -} - -#-- ES.PBES_WRAP_TOP.PBES_TOP.MISC_IOF.SCOM.PB_IOF_FIR_ACTION1_REG -scom 0x09010807 { - bits, scom_data, expr; - 0:63, 0x01D7DFCC01D7DFCC, (pcie_enabled) && (!nv_present); -} - -#-- ES.PBES_WRAP_TOP.PBES_TOP.MISC_IOF.SCOM.PB_IOF_FIR_MASK_REG -scom 0x09010803 { - bits, scom_data, expr; - 0:63, 0xFFFFFFFFFFFFFFFF, (pcie_enabled) && (!nv_present); -} - -#-- PCIE pervasive LFIR -#-- ES.PE_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION0 -scom 0x09040010 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (pcie_enabled); -} - -#-- ES.PE_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1 -scom 0x09040011 { - bits, scom_data, expr; - 0:63, 0x8000000000000000, (pcie_enabled); -} - -#-- ES.PE_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_MASK -scom 0x0904000D { - bits, scom_data, expr; - 0:63, 0x7FFFFFFFFF800000, (pcie_enabled); -} - -#-- PCIE chiplet XFIR -#-- ES.PE_WRAP_TOP.TPC.FIR_MASK -scom 0x09040002 { - bits, scom_data, expr; - 0:63, 0x211FFFE000000000, (pcie_enabled); -} - -#-- configure chiplet trace arrays to stop on checkstop -scom 0x090107C0 { - bits, scom_data, expr; - 7, 0b1, (pcie_enabled && trace_on_scom); -} - -scom 0x090107CB { - bits, scom_data, expr; - 17, 0b1, (pcie_enabled && trace_on_scom); -} diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile deleted file mode 100644 index 02d4b5162..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile +++ /dev/null @@ -1,529 +0,0 @@ -#-- $Id: p8.abus.custom.scom.initfile,v 1.18 2015/04/13 16:17:02 jgrell Exp $ -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -#-- 1.18|jgrell |04/25/15| Updated attribute to system type at Thi's request so it can be applied to Brazos only. (SW299500) -#-- 1.17|jmcgill |03/24/15| remove l2u delay settings,given filter bypass soln (SW299659) -#-- 1.15|jgrell |02/25/15| Added rx_fifo_final_l2u_dly for Venice only (SW296793) -#-- 1.14|garyp |02/19/14| Added rx_min_eye_width and rx_min_eye_height for manufacturing and lab thresholding -#-- 1.13|jgrell |02/12/14| Added rx_wt_lane_disabled=1 on lane 17 (SW244284) -#-- 1.12|jgrell |12/03/13| Set rx_eo_ddc_timeout_sel to 110 for DD2 -#-- 1.11|jgrell |10/29/13| Changed rx_ds_timeout_sel setting to 111 -#-- 1.9 |jgrell |10/28/13| Re-enabled recal bits for DD2+ hw -#-- 1.8 |jgrell |09/24/13| Changed "1" expression to "any" -#-- 1.6 |jgrell |09/17/13| Added DD2 specific inits -#-- 1.4 |jgrell |06/18/13| Added Venice specific PRBS tap IDs due to common initfile -#-- 1.3 |thomsen |04/30/13| Added TGT1. to ATTR_CHIP_EC* attribute instances to reference a chip target rather than a chiplet target -#-- 1.2 |jgrell |04/18/13| Added EC controled Recal enables -#-- 1.1 |thomsen |01/29/13| Created initial version -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- - -#--Master list of variables that can be used in this file is at: -#--<Attribute Definition Location> - -SyntaxVersion = 1 - - -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Includes -#-- Note: Must include the path to the .define file. -#-- -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** - -include edi.io.define - - -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Defines -#-- -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** - -define def_all_lanes=11111; - -#--***************** -#-- set rx_min_eye_width and rx_min_eye_height if in manufacturing mode -#--***************** -scom 0x800.0b(rx_result_chk_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) { - bits, scom_data, expr; - rx_min_eye_width, SYS.ATTR_MNFG_ABUS_MIN_EYE_WIDTH, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); - rx_min_eye_height, SYS.ATTR_MNFG_ABUS_MIN_EYE_HEIGHT, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); -} - - - -#--****************************************************************************** -#-------------------------------------------------------------------------------- -# __ ____ __ __ -# / / ____ _____ ___ / __ \____ _ _____ _____ / / / /___ -# / / / __ `/ __ \/ _ \ / /_/ / __ \ | /| / / _ \/ ___/ / / / / __ \ -# / /___/ /_/ / / / / __/ / ____/ /_/ / |/ |/ / __/ / / /_/ / /_/ / -# /_____/\__,_/_/ /_/\___/ /_/ \____/|__/|__/\___/_/ \____/ .___/ -# /_/ -#-------------------------------------------------------------------------------- -#--****************************************************************************** - -### # rx_lane_pdwn -### scom 0x800.0b(rx_mode_pl)(tx_grp0)(def_all_lanes).0x(abus_gcr_addr) { -### bits, scom_data; -### rx_lane_pdwn, 0b0; -### } - - -### # tx_lane_pdwn -### scom 0x800.0b(tx_mode_pl)(tx_grp0)(def_all_lanes).0x(abus_gcr_addr) { -### bits, scom_data; -### tx_lane_pdwn, 0b0; -### } - - -#--****************************************************************************** -#-------------------------------------------------------------------------------- -# _______ __ __ ___ _ ________ _____ ___ ____________ ______ -# /_ __/ |/ / / / / | / | / / ____/ / _/ | / / | / / ____/ __ \/_ __/ -# / / | / / / / /| | / |/ / __/ / // |/ /| | / / __/ / /_/ / / / -# / / / | / /___/ ___ |/ /| / /___ _/ // /| / | |/ / /___/ _, _/ / / -# /_/ /_/|_| /_____/_/ |_/_/ |_/_____/ /___/_/ |_/ |___/_____/_/ |_| /_/ -# figlet -fslant -#-------------------------------------------------------------------------------- -#--****************************************************************************** - -# These only do a scom if the invert attribute is set (saves scom's). -# The default scanflush value of tx_lane_invert for each lane is '0'. - -# Lane 0 -# 0x8004040008010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_0).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x80000000) > 0); -} - -# -# Lane 1 -# 0x8004040108010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_1).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x40000000) > 0); -} - -# -# Lane 2 -# 0x8004040208010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_2).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x20000000) > 0); -} - -# -# Lane 3 -# 0x8004040308010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_3).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x10000000) > 0); -} - -# -# Lane 4 -# 0x8004040408010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_4).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x08000000) > 0); -} - -# -# Lane 5 -# 0x8004040508010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_5).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x04000000) > 0); -} - -# -# Lane 6 -# 0x8004040608010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_6).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x02000000) > 0); -} - -# -# Lane 7 -# 0x8004040708010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_7).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x01000000) > 0); -} - -# -# Lane 8 -# 0x8004040808010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_8).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00800000) > 0); -} - -# -# Lane 9 -# 0x8004040908010C3F{ -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_9).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00400000) > 0); -} - -# -# Lane 10 -# 0x8004040A08010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_10).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00200000) > 0); -} - -# Lane 11 -# 0x8004040B08010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_11).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00100000) > 0); -} - -# -# Lane 12 -# 0x8004040C08010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_12).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00080000) > 0); -} - -# -# Lane 13 -# 0x8004040D08010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_13).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00040000) > 0); -} - -# -# Lane 14 -# 0x8004040E08010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_14).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00020000) > 0); -} - -# -# Lane 15 -# 0x8004040F08010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_15).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00010000) > 0); -} - -# -# Lane 16 -# 0x8004041008010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_16).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00008000) > 0); -} - -# Lane 17 -# 0x8004042008010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_17).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00004000) > 0); -} - -# Lane 18 -# 0x8004043008010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_18).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00002000) > 0); -} - -# Lane 19 -# 0x8004044008010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_19).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00001000) > 0); -} - -# Lane 20 -# 0x8004045008010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_20).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00000800) > 0); -} - -# Lane 21 -# 0x8004046008010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_21).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00000400) > 0); -} - -# Lane 22 -# 0x8004047008010C3F -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_22).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00000200) > 0); -} - -#--****************************************************************************** -#-------------------------------------------------------------------------------- -# _____ _ _ _______ _ _ ___ _ -# /_ __/ |/ / / ____/ / / //_/ / _/___ _ _____ _____/ / -# / / | / / / / / / ,< / // __ \ | / / _ \/ ___/ __/ -# / / / | / /___/ /___/ /| | _/ // / / / |/ / __/ / / / -# /_/ /_/|_| \____/_____/_/ |_| /___/_/ /_/|___/\___/_/ \__/ -# figlet -fslant -#-------------------------------------------------------------------------------- -#--****************************************************************************** -# CLK Lane (assigned to bit 31 of TX Lane Invert Attribute) -# 0x800???7008010C3F -scom 0x800.0b(tx_clk_mode_pg)(tx_grp0)(lane_na).0x(abus_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00000001) > 0); -} - -#--****************************************************************************** -#-------------------------------------------------------------------------------- -# __ ________ ____ _____ -# / |/ / ___// __ ) / ___/ ______ _____ -# / /|_/ /\__ \/ __ | \__ \ | /| / / __ `/ __ \ -# / / / /___/ / /_/ / ___/ / |/ |/ / /_/ / /_/ / -# /_/ /_//____/_____/ /____/|__/|__/\__,_/ .___/ -# /_/ -# figlet -fslant -#-------------------------------------------------------------------------------- -#--****************************************************************************** - -# 0x800C1C0008010C3F -scom 0x800.0b(tx_mode_pg)(tx_grp0)(lane_na).0x(abus_gcr_addr) { - bits, scom_data; - tx_msbswap, (ATTR_EI_BUS_TX_MSBSWAP & 0x01); -} - -#--************************************************************************************************************** -#---------------------------------------------------------------------------------------------------------------- -# Recal -#---------------------------------------------------------------------------------------------------------------- -#--************************************************************************************************************** -# HW235842 - -scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) { -bits, scom_data, expr; -rx_rc_enable_dfe_h1_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0; -rx_rc_enable_ddc, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0; -rx_rc_enable_ctle_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0; -} - -#--************************************************************************************************************** -#---------------------------------------------------------------------------------------------------------------- -# Power Down Unused Lanes -#---------------------------------------------------------------------------------------------------------------- -#--************************************************************************************************************** - -scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_23).0x(abus_gcr_addr) { -bits, scom_data; -tx_lane_pdwn, 0b1; -} - -scom 0x800.0b(rx_mode_pl)(rx_grp0)(lane_23).0x(abus_gcr_addr) { -bits, scom_data; -rx_lane_pdwn, 0b1; -} - -scom 0x800.0b(rx_wt_status_pl)(rx_grp0)(lane_23).0x(abus_gcr_addr) { -bits, scom_data; -rx_wt_lane_disabled, 0b1; -} - -#--************************************************************************************************************** -#---------------------------------------------------------------------------------------------------------------- -# Venice Specific Inits -#---------------------------------------------------------------------------------------------------------------- -#--************************************************************************************************************** - -#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341408010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341508010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341308010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341608010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341108010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341008010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341208010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340F08010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#2.TXPACK_2.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340C08010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#2.TXPACK_2.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340D08010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#2.TXPACK_2.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340E08010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340108010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340208010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340008010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340308010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340608010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340508010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340708010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340408010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340908010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340A08010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340808010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - -#TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340B08010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; -} - - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -#-- Brazos only -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -scom 0x800.0b(rx_fifo_mode_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) { - bits, scom_data, expr; - rx_fifo_final_l2u_dly, 0b0011, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; -} - - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -#-- DD2+ Murano & Venice -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) { - bits, scom_data, expr; - rx_sls_timeout_sel_dd2, 0b1010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; -} - -scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) { - bits, scom_data, expr; - rx_eo_ddc_timeout_sel, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; -} - - -############################################################################################ -# END OF FILE -############################################################################################ diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile deleted file mode 100644 index e4d142853..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile +++ /dev/null @@ -1,1607 +0,0 @@ -#-- $Id: p8.abus.scom.initfile,v 1.18 2013/12/04 17:25:20 jgrell Exp $ - - -#################################################################### -## -## Auto-genrated by fig2scominit.pl -## Based on SETUP_ID_MODE A_BUS_TR_HW -## from ../../logic/mesa_sim/fusion/run/IODUV_ABUS_WRAP.IODUV_ABUS_WRAP.figdb -## -## Created on Tue Nov 26 11:34:06 CST 2013, by jgrell -#################################################################### - -## -- CHANGE HISTORY: - ## -------------------------------------------------------------------------------- - ## -- VersionID: |Author: | Date: | Comment: - ## -- -----------|---------|--------|------------------------------------------------- - ## -- jgr13112600| jgr |11-26-13| CYC rx_ds_timeout_sel setting changed to 111 - ## -- jgr13102800| jgr |10-28-13| rx_ds_timeout_sel change (110 -> 111) - ## -- jgr13092400| jgr |09-24-13| Fixed tx_zcal inits scom address - ## -- jgr13082100| jgr |08-21-13| Added tx_zcal inits so they can be removed from scan - ## -- jfg13072400| jfg |07-24-13| HW253558: change pgooddly to MAX from lab feedback - ## -- mbs13071200| mbs |07-12-13| Updates for HW239870 and HW258990 - ## -- jgr13062500| jgr |06-25-13| Added DFE override settings (HW244323) - ## -- jgr13041800| jgr |04-18-13| Added missing entries from rel 0128 - ## -- smr13032500| SMR |03-25-13| Changed rx_dyn_recal_overall_timeout_sel init to 0b100 & rx_sls_timeout_sel init to 0b110 - ## -- mbs13021100| mbs |02-11-13| Changed A bus id's to 1,2,3 from 0,1,2 (HW239245) - ## -- mbs13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) - ## -- mbs12121100| mbs |12-11-12| Added rx_prot_speed_slct and rx_c4_sel - ## -- smr12112700| SMR |11-27-12| Added rx_dyn_recal_overall_timeout_sel init to 0b001 - ## -- jfg12112101| jfg |11-21-12| Added Zcal inits - ## -- jfg12112100| jfg |11-21-12| Added CU pll modes - ## -- 12111300| berger |11-13-12| Updated with HW eyeopt and recal settings - ## -- 12062500| SMR |06-25-12| HW210654: Added rx_sls_timeout_sel default of 1 - ## -- jfg12041600 |jfg |- HW193450,HW197325,HW196562,HW197324 clkdist Layout updates - ## -- 11012500| mbs |01-25-12| Swizzle and typo fixes for HW191494, HW191518, HW188304 - ## -- 12011900| RJR |01-18-12| Added RX_CTL2_REGS FILE REFERENCES Issue HW164277 - ## -- 12011800| berger |01-19-12| Added SETUP_ID_MODE dials - ## -- 11112900| mbs |11-29-11| Fixed RX scramble mirror taps (HW186689) - ## -- 11121600| mbs |12-16-11| Initial version (copied from version 11112900 of iodsh_abus_wrap.fig) - ## -------------------------------------------------------------------------------- - - -SyntaxVersion = 1 - - - -#################################################################### -# Define File -#################################################################### -include edi.io.define - - define def_IS_HW = SYS.ATTR_IS_SIMULATION == 0; - define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1; - - - -define def_bus_id0 = (ATTR_CHIP_UNIT_POS == 0); -define def_bus_id1 = (ATTR_CHIP_UNIT_POS == 1); -define def_bus_id2 = (ATTR_CHIP_UNIT_POS == 2); - - -define prim_id = (TGT1.ATTR_FABRIC_NODE_ID*100) + TGT1.ATTR_POS; -define conn_id = (TGT3.ATTR_FABRIC_NODE_ID*100) + TGT3.ATTR_POS; - -define def_is_master = (prim_id < conn_id); -define def_is_slave = (prim_id > conn_id); - - - -#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_P_4X_PB -scom 0x800F1C0008010C3F { - bits, scom_data, expr; - tx_zcal_p_4x, 0b00100, any; -} - -#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_SWO2_PB -scom 0x800F2C0008010C3F { - bits, scom_data, expr; - tx_zcal_sm_max_val, 0b1000110, any; - tx_zcal_sm_min_val, 0b0010101 , def_IS_HW; - tx_zcal_sm_min_val, 0b0010110 , def_IS_VBU; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_AMAX_PG -scom 0x800A680008010C3F { - bits, scom_data, expr; - rx_amax_high, 0b01101110, def_IS_HW && def_bus_id0; - rx_amax_high, 0b01101110, def_IS_HW && def_bus_id1; - rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id1; - rx_amax_high, 0b01101110, def_IS_HW && def_bus_id2; - rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id2; - rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id0; - rx_amax_high, 0b01101110, def_IS_HW && def_bus_id1; - rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id1; - rx_amax_high, 0b01101110, def_IS_HW && def_bus_id2; - rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id2; - rx_amax_low, 0b01010000, def_IS_HW && def_bus_id0; - rx_amax_low, 0b01010000, def_IS_HW && def_bus_id1; - rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id1; - rx_amax_low, 0b01010000, def_IS_HW && def_bus_id2; - rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id2; - rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id0; - rx_amax_low, 0b01010000, def_IS_HW && def_bus_id1; - rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id1; - rx_amax_low, 0b01010000, def_IS_HW && def_bus_id2; - rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG -scom 0x800AF00008010C3F { - bits, scom_data, expr; - rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id0; - rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id1; - rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id1; - rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id2; - rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id2; - rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id0; - rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id1; - rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id1; - rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id2; - rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP -scom 0x800B780008010C3F { - bits, scom_data, expr; - rx_amin_cfg, 0b111, def_IS_HW && def_bus_id0; - rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; - rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; - rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; - rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; - rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_anap_cfg, 0b10, def_IS_HW && def_bus_id0; - rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_h1_cfg, 0b01, def_IS_HW && def_bus_id0; - rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; - rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; - rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; - rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; - rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_peak_cfg, 0b10, def_IS_HW && def_bus_id0; - rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_peak_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_peak_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP -scom 0x800B800008010C3F { - bits, scom_data, expr; - rx_ber_cfg, 0b100, def_IS_HW && def_bus_id0; - rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; - rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; - rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; - rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; - rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id0; - rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; - rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; - rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; - rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; - rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id0; - rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id0; - rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; - rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; - rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; - rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; - rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_prot_cfg, 0b10, def_IS_HW && def_bus_id0; - rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_prot_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_prot_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG -scom 0x800A180008010C3F { - bits, scom_data, expr; - rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id0; - rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id1; - rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_TIMEOUTS_PP -scom 0x800B400008010C3F { - bits, scom_data, expr; - rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; - rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; - rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG -scom 0x8009D80008010C3F { - bits, scom_data, expr; - rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id0; - rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id1; - rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id2; - rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id0; - rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id1; - rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id2; - rx_dyn_rpr_err_cntr1_duration, 0b1001, def_bus_id0; - rx_dyn_rpr_err_cntr1_duration, 0b1001, def_bus_id1; - rx_dyn_rpr_err_cntr1_duration, 0b1001, def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG -scom 0x800AE00008010C3F { - bits, scom_data, expr; - rx_dyn_rpr_bad_bus_max, 0b0011111, def_bus_id0; - rx_dyn_rpr_bad_bus_max, 0b0011111, def_bus_id1; - rx_dyn_rpr_bad_bus_max, 0b0011111, def_bus_id2; - rx_dyn_rpr_err_cntr2_duration, 0b0110, def_bus_id0; - rx_dyn_rpr_err_cntr2_duration, 0b0110, def_bus_id1; - rx_dyn_rpr_err_cntr2_duration, 0b0110, def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_EO_CONVERGENCE_PG -scom 0x800A800008010C3F { - bits, scom_data, expr; - rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id0; - rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id1; - rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id1; - rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id2; - rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id2; - rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id0; - rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id1; - rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id1; - rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id2; - rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG -scom 0x800A380008010C3F { - bits, scom_data, expr; - rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_dfe_h1_cal, 0b0, def_bus_id0; - rx_eo_enable_dfe_h1_cal, 0b0, def_bus_id1; - rx_eo_enable_dfe_h1_cal, 0b0, def_bus_id2; - rx_eo_enable_final_l2u_adj, 0b1, def_bus_id0; - rx_eo_enable_final_l2u_adj, 0b1, def_bus_id1; - rx_eo_enable_final_l2u_adj, 0b1, def_bus_id2; - rx_eo_enable_h1ap_tweak, 0b0, def_bus_id0; - rx_eo_enable_h1ap_tweak, 0b0, def_bus_id1; - rx_eo_enable_h1ap_tweak, 0b0, def_bus_id2; - rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG -scom 0x8009A80008010C3F { - bits, scom_data, expr; - rx_fence, 0b1, def_bus_id0; - rx_fence, 0b1, def_bus_id1; - rx_fence, 0b1, def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008500008010C3F { - bits, scom_data, expr; - rx_bus_id, 0b000001, def_bus_id0; - rx_bus_id, 0b000010, def_bus_id1; - rx_bus_id, 0b000011, def_bus_id2; - rx_group_id, 0b000000, def_bus_id0; - rx_group_id, 0b000000, def_bus_id1; - rx_group_id, 0b000000, def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_ID2_PG -scom 0x8008580008010C3F { - bits, scom_data, expr; - rx_last_group_id, 0b000000, def_bus_id0; - rx_last_group_id, 0b000000, def_bus_id1; - rx_last_group_id, 0b000000, def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_ID3_PG -scom 0x8008600008010C3F { - bits, scom_data, expr; - rx_end_lane_id, 0b0010110, def_bus_id0; - rx_end_lane_id, 0b0010110, def_bus_id1; - rx_end_lane_id, 0b0010110, def_bus_id2; - rx_start_lane_id, 0b0000000, def_bus_id0; - rx_start_lane_id, 0b0000000, def_bus_id1; - rx_start_lane_id, 0b0000000, def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG -scom 0x8009280008010C3F { - bits, scom_data, expr; - rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0; - rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1; - rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG -scom 0x8009300008010C3F { - bits, scom_data, expr; - rx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id0; - rx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id1; - rx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG -scom 0x8009C00008010C3F { - bits, scom_data, expr; - rx_c4_sel, 0b00, def_IS_HW && def_bus_id0; - rx_c4_sel, 0b00, def_IS_HW && def_bus_id1; - rx_c4_sel, 0b11, def_IS_VBU && def_bus_id1; - rx_c4_sel, 0b00, def_IS_HW && def_bus_id2; - rx_c4_sel, 0b11, def_IS_VBU && def_bus_id2; - rx_c4_sel, 0b11, def_IS_VBU && def_bus_id0; - rx_c4_sel, 0b00, def_IS_HW && def_bus_id1; - rx_c4_sel, 0b11, def_IS_VBU && def_bus_id1; - rx_c4_sel, 0b00, def_IS_HW && def_bus_id2; - rx_c4_sel, 0b11, def_IS_VBU && def_bus_id2; - rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id0; - rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id1; - rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id1; - rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id2; - rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id2; - rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id0; - rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id1; - rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id1; - rx_prot_speed_slct, 0b0, def_IS_HW && def_bus_id2; - rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG -scom 0x8008180008010C3F { - bits, scom_data, expr; - rx_master_mode, 0b1, def_is_master; - rx_master_mode, 0b1, def_is_master; - rx_master_mode, 0b1, def_is_master; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG -scom 0x800AB80008010C3F { - bits, scom_data, expr; - rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id0; - rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id1; - rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b0, def_bus_id0; - rx_rc_enable_h1ap_tweak, 0b0, def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b0, def_bus_id2; - rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO1_PP -scom 0x800B900008010C3F { - bits, scom_data, expr; - rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP -scom 0x800B980008010C3F { - bits, scom_data, expr; - rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP -scom 0x800BA00008010C3F { - bits, scom_data, expr; - rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP -scom 0x800B600008010C3F { - bits, scom_data, expr; - rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP -scom 0x800B680008010C3F { - bits, scom_data, expr; - rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP -scom 0x800B700008010C3F { - bits, scom_data, expr; - rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG -scom 0x8009100008010C3F { - bits, scom_data, expr; - rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG -scom 0x8008980008010C3F { - bits, scom_data, expr; - rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id0; - rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id1; - rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1; - rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2; - rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2; - rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id0; - rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id1; - rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1; - rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2; - rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2; - rx_ds_timeout_sel, 0b111, def_bus_id0; - rx_ds_timeout_sel, 0b111, def_bus_id1; - rx_ds_timeout_sel, 0b111, def_bus_id2; - rx_sls_timeout_sel, 0b110, def_bus_id0; - rx_sls_timeout_sel, 0b110, def_bus_id1; - rx_sls_timeout_sel, 0b110, def_bus_id2; - rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1; - rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id2; - rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id0; - rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1; - rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG -scom 0x8009980008010C3F { - bits, scom_data, expr; - rx_rx_bus_width, 0b0010111, def_bus_id0; - rx_rx_bus_width, 0b0010111, def_bus_id1; - rx_rx_bus_width, 0b0010111, def_bus_id2; - rx_tx_bus_width, 0b0010111, def_bus_id0; - rx_tx_bus_width, 0b0010111, def_bus_id1; - rx_tx_bus_width, 0b0010111, def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG -scom 0x8009580008010C3F { - bits, scom_data, expr; - rx_wtr_max_bad_lanes, 0b00001, def_bus_id0; - rx_wtr_max_bad_lanes, 0b00001, def_bus_id1; - rx_wtr_max_bad_lanes, 0b00001, def_bus_id2; -} - -#RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG -scom 0x800A300008010C3F { - bits, scom_data, expr; - rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id0; - rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; - rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; - rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0; - rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; - rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; - rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id0; - rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1; - rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id2; - rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2; - rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id0; - rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1; - rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id2; - rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000501508010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B01508010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, def_bus_id0; - rx_prbs_tap_id, 0b001, def_bus_id1; - rx_prbs_tap_id, 0b001, def_bus_id2; -} - -#RX0.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000501408010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B01408010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, def_bus_id0; - rx_prbs_tap_id, 0b010, def_bus_id1; - rx_prbs_tap_id, 0b010, def_bus_id2; -} - -#RX0.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000501608010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B01608010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, def_bus_id0; - rx_prbs_tap_id, 0b000, def_bus_id1; - rx_prbs_tap_id, 0b000, def_bus_id2; -} - -#RX0.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500A08010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00A08010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, def_bus_id0; - rx_prbs_tap_id, 0b010, def_bus_id1; - rx_prbs_tap_id, 0b010, def_bus_id2; -} - -#RX0.RXPACKS#0.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500B08010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#0.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00B08010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, def_bus_id0; - rx_prbs_tap_id, 0b011, def_bus_id1; - rx_prbs_tap_id, 0b011, def_bus_id2; -} - -#RX0.RXPACKS#0.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500908010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#0.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00908010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, def_bus_id0; - rx_prbs_tap_id, 0b001, def_bus_id1; - rx_prbs_tap_id, 0b001, def_bus_id2; -} - -#RX0.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000501208010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B01208010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, def_bus_id0; - rx_prbs_tap_id, 0b100, def_bus_id1; - rx_prbs_tap_id, 0b100, def_bus_id2; -} - -#RX0.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000501708010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B01708010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, def_bus_id0; - rx_prbs_tap_id, 0b000, def_bus_id1; - rx_prbs_tap_id, 0b000, def_bus_id2; -} - -#RX0.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500708010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00708010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, def_bus_id0; - rx_prbs_tap_id, 0b111, def_bus_id1; - rx_prbs_tap_id, 0b111, def_bus_id2; -} - -#RX0.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000501308010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B01308010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, def_bus_id0; - rx_prbs_tap_id, 0b011, def_bus_id1; - rx_prbs_tap_id, 0b011, def_bus_id2; -} - -#RX0.RXPACKS#1.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500608010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#1.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00608010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, def_bus_id0; - rx_prbs_tap_id, 0b110, def_bus_id1; - rx_prbs_tap_id, 0b110, def_bus_id2; -} - -#RX0.RXPACKS#1.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500808010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#1.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00808010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, def_bus_id0; - rx_prbs_tap_id, 0b000, def_bus_id1; - rx_prbs_tap_id, 0b000, def_bus_id2; -} - -#RX0.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500508010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00508010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, def_bus_id0; - rx_prbs_tap_id, 0b101, def_bus_id1; - rx_prbs_tap_id, 0b101, def_bus_id2; -} - -#RX0.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500308010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00308010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, def_bus_id0; - rx_prbs_tap_id, 0b011, def_bus_id1; - rx_prbs_tap_id, 0b011, def_bus_id2; -} - -#RX0.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000501108010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B01108010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, def_bus_id0; - rx_prbs_tap_id, 0b101, def_bus_id1; - rx_prbs_tap_id, 0b101, def_bus_id2; -} - -#RX0.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500408010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00408010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, def_bus_id0; - rx_prbs_tap_id, 0b100, def_bus_id1; - rx_prbs_tap_id, 0b100, def_bus_id2; -} - -#RX0.RXPACKS#2.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000501008010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#2.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B01008010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, def_bus_id0; - rx_prbs_tap_id, 0b110, def_bus_id1; - rx_prbs_tap_id, 0b110, def_bus_id2; -} - -#RX0.RXPACKS#2.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500F08010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#2.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00F08010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, def_bus_id0; - rx_prbs_tap_id, 0b111, def_bus_id1; - rx_prbs_tap_id, 0b111, def_bus_id2; -} - -#RX0.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500008010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00008010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, def_bus_id0; - rx_prbs_tap_id, 0b000, def_bus_id1; - rx_prbs_tap_id, 0b000, def_bus_id2; -} - -#RX0.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500208010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00208010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, def_bus_id0; - rx_prbs_tap_id, 0b010, def_bus_id1; - rx_prbs_tap_id, 0b010, def_bus_id2; -} - -#RX0.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500108010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00108010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, def_bus_id0; - rx_prbs_tap_id, 0b001, def_bus_id1; - rx_prbs_tap_id, 0b001, def_bus_id2; -} - -#RX0.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500E08010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00E08010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, def_bus_id0; - rx_prbs_tap_id, 0b000, def_bus_id1; - rx_prbs_tap_id, 0b000, def_bus_id2; -} - -#RX0.RXPACKS#3.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500C08010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#3.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00C08010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, def_bus_id0; - rx_prbs_tap_id, 0b010, def_bus_id1; - rx_prbs_tap_id, 0b010, def_bus_id2; -} - -#RX0.RXPACKS#3.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_AMP_VAL_PL -scom 0x8000500D08010C3F { - bits, scom_data, expr; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; - rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; - rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; -} - -#RX0.RXPACKS#3.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00D08010C3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, def_bus_id0; - rx_prbs_tap_id, 0b001, def_bus_id1; - rx_prbs_tap_id, 0b001, def_bus_id2; -} - -#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG -scom 0x800CC40008010C3F { - bits, scom_data, expr; - tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id0; - tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id1; - tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id2; -} - -#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_DYN_RECAL_TIMEOUTS_PP -scom 0x800EAC0008010C3F { - bits, scom_data, expr; - tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; - tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; - tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; -} - -#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C940008010C3F { - bits, scom_data, expr; - tx_bus_id, 0b000001, def_bus_id0; - tx_bus_id, 0b000010, def_bus_id1; - tx_bus_id, 0b000011, def_bus_id2; - tx_group_id, 0b100000, def_bus_id0; - tx_group_id, 0b100000, def_bus_id1; - tx_group_id, 0b100000, def_bus_id2; -} - -#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID2_PG -scom 0x800C9C0008010C3F { - bits, scom_data, expr; - tx_last_group_id, 0b100000, def_bus_id0; - tx_last_group_id, 0b100000, def_bus_id1; - tx_last_group_id, 0b100000, def_bus_id2; -} - -#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID3_PG -scom 0x800CA40008010C3F { - bits, scom_data, expr; - tx_end_lane_id, 0b0010110, def_bus_id0; - tx_end_lane_id, 0b0010110, def_bus_id1; - tx_end_lane_id, 0b0010110, def_bus_id2; - tx_start_lane_id, 0b0000000, def_bus_id0; - tx_start_lane_id, 0b0000000, def_bus_id1; - tx_start_lane_id, 0b0000000, def_bus_id2; -} - -#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG -scom 0x800D1C0008010C3F { - bits, scom_data, expr; - tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0; - tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1; - tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2; -} - -#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG -scom 0x800D240008010C3F { - bits, scom_data, expr; - tx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id0; - tx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id1; - tx_lane_disabled_vec_16_31, 0b0000000111111111, def_bus_id2; -} - -#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_MODE_PG -scom 0x800C1C0008010C3F { - bits, scom_data, expr; - tx_max_bad_lanes, 0b00001, def_bus_id0; - tx_max_bad_lanes, 0b00001, def_bus_id1; - tx_max_bad_lanes, 0b00001, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341108010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, def_bus_id0; - tx_prbs_tap_id, 0b101, def_bus_id1; - tx_prbs_tap_id, 0b101, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341208010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, def_bus_id0; - tx_prbs_tap_id, 0b100, def_bus_id1; - tx_prbs_tap_id, 0b100, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341608010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, def_bus_id0; - tx_prbs_tap_id, 0b000, def_bus_id1; - tx_prbs_tap_id, 0b000, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340008010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, def_bus_id0; - tx_prbs_tap_id, 0b000, def_bus_id1; - tx_prbs_tap_id, 0b000, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341008010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, def_bus_id0; - tx_prbs_tap_id, 0b110, def_bus_id1; - tx_prbs_tap_id, 0b110, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340108010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, def_bus_id0; - tx_prbs_tap_id, 0b001, def_bus_id1; - tx_prbs_tap_id, 0b001, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341408010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, def_bus_id0; - tx_prbs_tap_id, 0b010, def_bus_id1; - tx_prbs_tap_id, 0b010, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341508010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, def_bus_id0; - tx_prbs_tap_id, 0b001, def_bus_id1; - tx_prbs_tap_id, 0b001, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340E08010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, def_bus_id0; - tx_prbs_tap_id, 0b000, def_bus_id1; - tx_prbs_tap_id, 0b000, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340908010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, def_bus_id0; - tx_prbs_tap_id, 0b001, def_bus_id1; - tx_prbs_tap_id, 0b001, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340208010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, def_bus_id0; - tx_prbs_tap_id, 0b010, def_bus_id1; - tx_prbs_tap_id, 0b010, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004341308010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, def_bus_id0; - tx_prbs_tap_id, 0b011, def_bus_id1; - tx_prbs_tap_id, 0b011, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340308010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, def_bus_id0; - tx_prbs_tap_id, 0b011, def_bus_id1; - tx_prbs_tap_id, 0b011, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340508010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, def_bus_id0; - tx_prbs_tap_id, 0b101, def_bus_id1; - tx_prbs_tap_id, 0b101, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340408010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, def_bus_id0; - tx_prbs_tap_id, 0b100, def_bus_id1; - tx_prbs_tap_id, 0b100, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340D08010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, def_bus_id0; - tx_prbs_tap_id, 0b001, def_bus_id1; - tx_prbs_tap_id, 0b001, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340808010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, def_bus_id0; - tx_prbs_tap_id, 0b000, def_bus_id1; - tx_prbs_tap_id, 0b000, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340608010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, def_bus_id0; - tx_prbs_tap_id, 0b110, def_bus_id1; - tx_prbs_tap_id, 0b110, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340708010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, def_bus_id0; - tx_prbs_tap_id, 0b111, def_bus_id1; - tx_prbs_tap_id, 0b111, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340C08010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, def_bus_id0; - tx_prbs_tap_id, 0b010, def_bus_id1; - tx_prbs_tap_id, 0b010, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340B08010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, def_bus_id0; - tx_prbs_tap_id, 0b011, def_bus_id1; - tx_prbs_tap_id, 0b011, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340A08010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, def_bus_id0; - tx_prbs_tap_id, 0b010, def_bus_id1; - tx_prbs_tap_id, 0b010, def_bus_id2; -} - -#TX_WRAP.TX0.TXPACKS#5.TXPACK_5.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340F08010C3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, def_bus_id0; - tx_prbs_tap_id, 0b111, def_bus_id1; - tx_prbs_tap_id, 0b111, def_bus_id2; -} - diff --git a/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile deleted file mode 100644 index f4b32acbc..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile +++ /dev/null @@ -1,130 +0,0 @@ -#-- $Id: p8.as.scom.initfile,v 1.6 2014/01/29 23:19:32 kscarp Exp $ -#------------------------------------------------------------------------------- -#-- -#-- (C) Copyright International Business Machines Corp. 2013 -#-- All Rights Reserved -- Property of IBM -#-- *** *** -#-- -#-- TITLE : p8.as.scom.initfile -#-- DESCRIPTION : Perform AS configuration -#-- -#-- OWNER NAME : John Irish Email: irish@us.ibm.com -#-- -#-------------------------------------------------------------------------------- - -SyntaxVersion = 1 - -#-------------------------------------------------------------------------------- -#-- Includes -#-------------------------------------------------------------------------------- - -#-------------------------------------------------------------------------------- -#-- Defines -#-------------------------------------------------------------------------------- - -#-------------------------------------------------------------------------------- -#-- SCOM initializations -#-------------------------------------------------------------------------------- - -#-- AS Config Register (0x020130FE) -scom 0x020130FE { - bits , scom_data ; - 0 , 0b1 ; #-- pbus in enable (ON) - 1 , 0b0 ; #-- dslc enable (OFF - set to 1 if DSLC link needed) - 2 , 0b0 ; #-- copreq wait for data (OFF) - 3 , 0b0 ; #-- copreq wait for cresp (OFF) - 4 , 0b0 ; #-- credwt wait for data (OFF) - 5 , 0b0 ; #-- dredwt wait for cresp (OFF) - 6 , 0b0 ; #-- dslc wait for data (OFF) - 7 , 0b0 ; #-- data hang check (ON) - 8 , 0b0 ; #-- sary ce rewrite (ON) - 9 , 0b0 ; #-- rcmd pchk (ON) - 10 , 0b0 ; #-- capture mal-formed mmio st (OFF) - 11 , 0b0 ; #-- capture data hang (OFF) - 12 , 0b0 ; #-- capture multiple cam hit (OFF) - 13 , 0b0 ; #-- capture phyp credit retry (OFF) - 14 , 0b0 ; #-- capture correctable errors (OFF) - 15 , 0b1 ; #-- capture unsupported conf (ON) - 16 , 0b0 ; #-- hypervisor PID chk ovrrd (OFF) - 17 , 0b0 ; #-- priveledged PID chk ovrrd (OFF) - 18 , 0b0 ; #-- spare 0 (OFF) - 19 , 0b0 ; #-- spare 1 (OFF) - 20 , 0b0 ; #-- spare 2 (OFF) - 21 , 0b0 ; #-- spare 3 (OFF) - 22 , 0b0 ; #-- spare 5 (OFF) - 23 , 0b0 ; #-- spare 6 (OFF) - 24 , 0b0 ; #-- spare 7 (OFF) - 25 , 0b0 ; #-- spare 8 (OFF) - 26 , 0b0 ; #-- spare 9 (OFF) - 27 , 0b0 ; #-- spare 10 (OFF) - 28 , 0b0 ; #-- spare 11 (OFF) - 29 , 0b0 ; #-- spare 12 (OFF) - 30 , 0b0 ; #-- spare 13 (OFF) - 31 , 0b0 ; #-- spare 14 (OFF) - 32 , 0b1 ; #-- FL wait for data sent (ON) -} - -#-- AS EG Config Register (0x020130F2) -scom 0x020130F2 { - bits , scom_data ; - 0 , 0b0 ; #-- EG disable (OFF) - 1 , 0b0 ; #-- page migration mode (OFF) - 2:3 , 0b00 ; #-- credwt pref level (0) - 4 , 0b0 ; #-- relaxed DMA ordering (OFF) - 5 , 0b0 ; #-- dir cmd hang detect (OFF) - 6 , 0b1 ; #-- rary ce rewrite (ON) - 7 , 0b1 ; #-- cresp pchk (ON) - 8:9 , 0b00 ; #-- dma throttle (OFF) - 10:11 , 0b00 ; #-- notif throttle (OFF) - 12:13 , 0b00 ; #-- intr throttle (OFF) - 14:15 , 0b00 ; #-- credwt throttle (OFF) - 16:21 , 0b000000 ; #-- reserved (OFF) - 22 , 0b1 ; #-- force DMA to normal path (ON) - 23 , 0b0 ; #-- all notify to system scope (OFF) - 24 , 0b0 ; #-- grp notify to system scope (OFF) - 25 , 0b0 ; #-- rmt-grp notify to system scope (OFF) - 26 , 0b0 ; #-- all credwt to system scope (OFF) - 27 , 0b1 ; #-- grp credwt to system scope (ON) - 28 , 0b1 ; #-- rmt-grp credwt to system scope (ON) - 29 , 0b0 ; #-- hang on addr error (OFF) - 30:31 , 0b00 ; #-- dma worklist threshold (64) - 32:35 , 0b0000 ; #-- starve timer (OFF) - 36:39 , 0b0000 ; #-- stale timer (OFF) - 40 , 0b0 ; #-- force PM orig to normal path (OFF) - 41 , 0b0 ; #-- reserved (OFF) - 42:63 , 0x000 ; #-- reserved (OFF) -} - -#--****************************************************************************** -# FIR Action Register Decodes -#--****************************************************************************** -# (Action0, Action1, Mask) -# ------------------------ -# (0,0,0) = Checkstop -# (0,1,0) = Recoverable -# (1,0,0) = Reserved -# (1,1,0) = Local (Core) Checkstop / GX freeze' -# (x,x,1) = MASKED -#--****************************************************************************** -# -- description -#--****************************************************************************** -#-- Reset FIR -scom 0x020130C0 { - scom_data ; - 0x0000000000000000 ; - } -#-- Action 0 -scom 0x020130C6 { - scom_data ; - 0x0000000000000000 ; - } -#--- Action 1 -scom 0x020130C7 { - scom_data ; - 0x0000000000000000 ; - } -#--- Mask -scom 0x020130C3 { - scom_data ; - 0xFFFFFFFFFFE00000 ; - } diff --git a/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile deleted file mode 100644 index 92e1873bc..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile +++ /dev/null @@ -1,435 +0,0 @@ -#-- $Id: p8.cxa.scom.initfile,v 1.6 2015/05/20 18:55:23 jmcgill Exp $ -#------------------------------------------------------------------------------- -#-- -#-- (C) Copyright International Business Machines Corp. 2011 -#-- All Rights Reserved -- Property of IBM -#-- *** *** -#-- -#-- TITLE : p8.cxa.scom.initfile -#-- DESCRIPTION : Perform CAPP configuration -#-- -#-- OWNER NAME : Bill Daly Email: billdaly@us.ibm.com -#-- -#-------------------------------------------------------------------------------- - -SyntaxVersion = 1 - -#-------------------------------------------------------------------------------- -#-- Includes -#-------------------------------------------------------------------------------- - -#-------------------------------------------------------------------------------- -#-- Defines -#-------------------------------------------------------------------------------- -define capp_hang_ctl_on_scom = (ATTR_CHIP_EC_FEATURE_CAPP_HANG_CONTROL_ON_SCOM != 0); -define capp_prod = (ATTR_CHIP_EC_FEATURE_CAPP_PROD != 0); -define capp_dual = (ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT != 0); - -#-------------------------------------------------------------------------------- -#-- SCOM initializations -#-------------------------------------------------------------------------------- - - -#-- APC Master Config Register -scom 0x02013019 { - bits , scom_data, expr; - 4:7 , 0b0000, (capp_hang_ctl_on_scom); #-- HANG_POLL_SCALE -} - -scom 0x02013199 { - bits , scom_data, expr; - 4:7 , 0b0000, (capp_dual && capp_hang_ctl_on_scom); -} - -#-- CAPP Snoop Control Register -scom 0x0201301B { - bits , scom_data, expr; - 45:47 , 0b111, (capp_prod); #-- CXA_SNP_MASTER_ADDRESS_PIPELINE_WAIT_COUNT - 48:51 , 0b0010, (capp_hang_ctl_on_scom); #-- CXA_SNP_DATA_HANG_POLL_SCALE -} - -scom 0x0201319B { - bits , scom_data, expr; - 45:47 , 0b111, (capp_dual && capp_prod); - 48:51 , 0b0010, (capp_dual && capp_hang_ctl_on_scom); -} - -#-- CAPP Transport Control Register -scom 0x0201301C { - bits , scom_data; - 15:18 , 0b1000; #-- TLBI_DATA_POLL_PULSE_DIV -} - -scom 0x0201319C { - bits , scom_data, expr; - 15:18 , 0b1000, (capp_dual); -} - -#-- CAPP Flush uOP1 Configuration Register -scom 0x02013803 { - bits , scom_data; - 0:63 , 0xB188280728000000; -} - -scom 0x02013983 { - bits , scom_data, expr; - 0:63 , 0xB188280728000000, (capp_dual); -} - -#-- CAPP Flush uOP2 Configuration Register -scom 0x02013804 { - bits , scom_data; - 0:63 , 0xB188400F00000000; -} - -scom 0x02013984 { - bits , scom_data, expr; - 0:63 , 0xB188400F00000000, (capp_dual); -} - -#-- CXA FIR Action0/1 Registers -#-- action0,1 = 00 : checkstop -#-- 01 : recovered attention -#-- 10 : recoverable interrupt -#-- 11 : local checkstop = CAPP Machine Check - -scom 0x02013006 { - bits , scom_data, expr; #--Action - 0 , 0b0, any; #-- 0b00 masked BAR PE - 1 , 0b0, any; #-- 0b00 xstop Register PE - 2 , 0b0, any; #-- 0b01 recovered attn Master Array CE - 3 , 0b0, any; #-- 0b00 xstop Master Array UE - 4 , 0b1, any; #-- 0b11 capp mach check Timer Expired Recoverable Epoch - 5 , 0b0, any; #-- 0b00 xstop Timer Expired Xstop RCS sequencer hang - 6 , 0b1, any; #-- 0b11 capp mach check PSL Cmd UE - 7 , 0b1, any; #-- 0b11 capp mach check PSL Cmd SUE - 8 , 0b0, any; #-- 0b01 recovered attn Snoop Array CE - 9 , 0b0, any; #-- 0b00 xstop Snoop Array UE - 10 , 0b0, any; #-- 0b00 xstop Recovery Failed - 11 , 0b1, any; #-- 0b11 capp mach check Illegal LPC Bar Access DD2 only - 12 , 0b1, any; #-- 0b11 capp mach check XPT Recoverable err DD2 only - 13 , 0b1, any; #-- 0b11 capp mach check Master Recoverable Err - 14 , 0b0, any; #-- 0b00 masked Spare - 15 , 0b0, any; #-- 0b00 masked Scom satellite parity Err - 16 , 0b0, any; #-- 0b00 xstop Master Sys Xstop Err - 17 , 0b0, any; #-- 0b00 xstop Snooper Sys Xstop Err - 18 , 0b0, any; #-- 0b00 xstop XPT Sys Xstop Err - 19 , 0b0, any; #-- 0b00 masked Master Uop Err1 For Lab Use only - 20 , 0b0, any; #-- 0b00 masked Master Uop Err2 For Lab Use only - 21 , 0b0, any; #-- 0b00 masked Master Uop Err3 For Lab Use only - 22 , 0b0, any; #-- 0b00 masked Snooper Uop Err1 For Lab Use only - 23 , 0b0, any; #-- 0b00 masked Snooper Uop Err2 For Lab Use only - 24 , 0b0, any; #-- 0b00 masked Snooper Uop Err3 For Lab Use only - 25 , 0b0, any; #-- 0b00 xstop Unsolicited PowerBus Data or Cresp - 26 , 0b0, any; #-- 0b00 xstop PowerBus parity Err - 27 , 0b0, any; #-- 0b00 masked PowerBus Data Hang Err - 28 , 0b0, any; #-- 0b00 masked PowerBus Hang Err - 29 , 0b0, any; #-- 0b00 xstop PowerBus Address Err on LD class APC op - 30 , 0b0, any; #-- 0b00 xstop PowerBus Address Err on ST class APC op - 31 , 0b1, any; #-- 0b11 capp mach check PHB Link Down - 32 , 0b0, any; #-- 0b00 masked LD class Foreign Link err - 33 , 0b0, any; #-- 0b00 masked Foreign Link Hang err - 34 , 0b0, any; #-- 0b01 recovered attn XPT PowerBus CE - 35 , 0b0, any; #-- 0b00 masked XPT PowerBus UE - 36 , 0b0, any; #-- 0b00 masked XPT PowerBus SUE - 37 , 0b1, any; #-- 0b11 capp mach check TLBI Timeout Err - 38 , 0b0, any; #-- 0b00 xstop TLBI Seq Err - 39 , 0b0, any; #-- 0b00 xstop TLBI Bad Op Err - 40 , 0b0, any; #-- 0b00 xstop TLBI Seq Num Parity Err - 41 , 0b0, any; #-- 0b00 masked ST class Foreign Link Fail - 42 , 0b0, any; #-- 0b00 masked TimeBase Err DD2 only - 43 , 0b0, any; #-- 0b00 masked XPT Informational DD2 only - 44 , 0b0, any; #-- 0b00 masked Spare / CmdQ CE - 45 , 0b0, any; #-- 0b00 masked Spare / CmdQ UE - 46 , 0b1, any; #-- 0b11 capp mach check PSL Credit Timeout - 47 , 0b0, any; #-- 0b00 masked Scom satellite parity error Copy 1 / Spare - 48 , 0b0, any; #-- 0b00 masked Scom satellite parity error Copy 2 / Spare - 49 , 0b0, (capp_dual); #-- 0b00 masked NA / Scom satellite parity error Copy 1 - 50 , 0b0, (capp_dual); #-- 0b00 masked NA / Scom satellite parity error Copy 2 -} - -scom 0x02013186 { - bits , scom_data, expr; #--Action - 0 , 0b0, (capp_dual); #-- 0b00 masked BAR PE - 1 , 0b0, (capp_dual); #-- 0b00 xstop Register PE - 2 , 0b0, (capp_dual); #-- 0b01 recovered attn Master Array CE - 3 , 0b0, (capp_dual); #-- 0b00 xstop Master Array UE - 4 , 0b1, (capp_dual); #-- 0b11 capp mach check Timer Expired Recoverable Epoch - 5 , 0b0, (capp_dual); #-- 0b00 xstop Timer Expired Xstop RCS sequencer hang - 6 , 0b1, (capp_dual); #-- 0b11 capp mach check PSL Cmd UE - 7 , 0b1, (capp_dual); #-- 0b11 capp mach check PSL Cmd SUE - 8 , 0b0, (capp_dual); #-- 0b01 recovered attn Snoop Array CE - 9 , 0b0, (capp_dual); #-- 0b00 xstop Snoop Array UE - 10 , 0b0, (capp_dual); #-- 0b00 xstop Recovery Failed - 11 , 0b1, (capp_dual); #-- 0b11 capp mach check Illegal LPC Bar Access DD2 only - 12 , 0b1, (capp_dual); #-- 0b11 capp mach check XPT Recoverable err DD2 only - 13 , 0b1, (capp_dual); #-- 0b11 capp mach check Master Recoverable Err - 14 , 0b0, (capp_dual); #-- 0b00 masked Spare - 15 , 0b0, (capp_dual); #-- 0b00 masked Scom satellite parity Err - 16 , 0b0, (capp_dual); #-- 0b00 xstop Master Sys Xstop Err - 17 , 0b0, (capp_dual); #-- 0b00 xstop Snooper Sys Xstop Err - 18 , 0b0, (capp_dual); #-- 0b00 xstop XPT Sys Xstop Err - 19 , 0b0, (capp_dual); #-- 0b00 masked Master Uop Err1 For Lab Use only - 20 , 0b0, (capp_dual); #-- 0b00 masked Master Uop Err2 For Lab Use only - 21 , 0b0, (capp_dual); #-- 0b00 masked Master Uop Err3 For Lab Use only - 22 , 0b0, (capp_dual); #-- 0b00 masked Snooper Uop Err1 For Lab Use only - 23 , 0b0, (capp_dual); #-- 0b00 masked Snooper Uop Err2 For Lab Use only - 24 , 0b0, (capp_dual); #-- 0b00 masked Snooper Uop Err3 For Lab Use only - 25 , 0b0, (capp_dual); #-- 0b00 xstop Unsolicited PowerBus Data or Cresp - 26 , 0b0, (capp_dual); #-- 0b00 xstop PowerBus parity Err - 27 , 0b0, (capp_dual); #-- 0b00 masked PowerBus Data Hang Err - 28 , 0b0, (capp_dual); #-- 0b00 masked PowerBus Hang Err - 29 , 0b0, (capp_dual); #-- 0b00 xstop PowerBus Address Err on LD class APC op - 30 , 0b0, (capp_dual); #-- 0b00 xstop PowerBus Address Err on ST class APC op - 31 , 0b1, (capp_dual); #-- 0b11 capp mach check PHB Link Down - 32 , 0b0, (capp_dual); #-- 0b00 masked LD class Foreign Link err - 33 , 0b0, (capp_dual); #-- 0b00 masked Foreign Link Hang err - 34 , 0b0, (capp_dual); #-- 0b01 recovered attn XPT PowerBus CE - 35 , 0b0, (capp_dual); #-- 0b00 masked XPT PowerBus UE - 36 , 0b0, (capp_dual); #-- 0b00 masked XPT PowerBus SUE - 37 , 0b1, (capp_dual); #-- 0b11 capp mach check TLBI Timeout Err - 38 , 0b0, (capp_dual); #-- 0b00 xstop TLBI Seq Err - 39 , 0b0, (capp_dual); #-- 0b00 xstop TLBI Bad Op Err - 40 , 0b0, (capp_dual); #-- 0b00 xstop TLBI Seq Num Parity Err - 41 , 0b0, (capp_dual); #-- 0b00 masked ST class Foreign Link Fail - 42 , 0b0, (capp_dual); #-- 0b00 masked TimeBase Err DD2 only - 43 , 0b0, (capp_dual); #-- 0b00 masked XPT Informational DD2 only - 44 , 0b0, (capp_dual); #-- 0b00 masked CmdQ CE - 45 , 0b0, (capp_dual); #-- 0b00 masked CmdQ UE - 46 , 0b1, (capp_dual); #-- 0b11 capp mach check PSL Credit Timeout - 47 , 0b0, (capp_dual); #-- 0b00 masked Spare - 48 , 0b0, (capp_dual); #-- 0b00 masked Spare - 49 , 0b0, (capp_dual); #-- 0b00 masked Scom satellite parity error Copy 1 - 50 , 0b0, (capp_dual); #-- 0b00 masked Scom satellite parity error Copy 2 -} - -scom 0x02013007 { - bits , scom_data, expr; #--Action - 0 , 0b0, any; #-- 0b00 masked BAR PE - 1 , 0b0, any; #-- 0b00 xstop Register PE - 2 , 0b1, any; #-- 0b01 recovered attn Master Array CE - 3 , 0b0, any; #-- 0b10 xstop Master Array UE - 4 , 0b1, any; #-- 0b11 capp mach check Timer Expired Recoverable Epoch - 5 , 0b0, any; #-- 0b00 xstop Timer Expired Xstop RCS sequencer hang - 6 , 0b1, any; #-- 0b11 capp mach check PSL Cmd UE - 7 , 0b1, any; #-- 0b11 capp mach check PSL Cmd SUE - 8 , 0b1, any; #-- 0b01 recovered attn Snoop Array CE - 9 , 0b0, any; #-- 0b00 xstop Snoop Array UE - 10 , 0b0, any; #-- 0b00 xstop Recovery Failed - 11 , 0b1, any; #-- 0b11 capp mach check Illegal LPC Bar Access DD2 only - 12 , 0b1, any; #-- 0b11 capp mach check XPT Recoverable err DD2 only - 13 , 0b1, any; #-- 0b11 capp mach check Master Recoverable Err - 14 , 0b0, any; #-- 0b00 masked Spare - 15 , 0b0, any; #-- 0b00 masked Scom satellite parity Err - 16 , 0b0, any; #-- 0b00 xstop Master Sys Xstop Err - 17 , 0b0, any; #-- 0b00 xstop Snooper Sys Xstop Err - 18 , 0b0, any; #-- 0b00 xstop XPT Sys Xstop Err - 19 , 0b0, any; #-- 0b00 masked Master Uop Err1 For Lab Use only - 20 , 0b0, any; #-- 0b00 masked Master Uop Err2 For Lab Use only - 21 , 0b0, any; #-- 0b00 masked Master Uop Err3 For Lab Use only - 22 , 0b0, any; #-- 0b00 masked Snooper Uop Err1 For Lab Use only - 23 , 0b0, any; #-- 0b00 masked Snooper Uop Err2 For Lab Use only - 24 , 0b0, any; #-- 0b00 masked Snooper Uop Err3 For Lab Use only - 25 , 0b0, any; #-- 0b00 xstop Unsolicited PowerBus Data or Cresp - 26 , 0b0, any; #-- 0b00 xstop PowerBus parity Err - 27 , 0b0, any; #-- 0b00 masked PowerBus Data Hang Err - 28 , 0b0, any; #-- 0b00 masked PowerBus Hang Err - 29 , 0b0, any; #-- 0b00 xstop PowerBus Address Err on LD class APC op - 30 , 0b0, any; #-- 0b00 xstop PowerBus Address Err on ST class APC op - 31 , 0b1, any; #-- 0b11 capp mach check PHB Link Down - 32 , 0b0, any; #-- 0b00 masked LD class Foreign Link err - 33 , 0b0, any; #-- 0b00 masked Foreign Link Hang err - 34 , 0b1, any; #-- 0b01 recovered attn XPT PowerBus CE - 35 , 0b0, any; #-- 0b00 masked XPT PowerBus UE - 36 , 0b0, any; #-- 0b00 masked XPT PowerBus SUE - 37 , 0b1, any; #-- 0b11 capp mach check TLBI Timeout Err - 38 , 0b0, any; #-- 0b00 xstop TLBI Seq Err - 39 , 0b0, any; #-- 0b00 xstop TLBI Bad Op Err - 40 , 0b0, any; #-- 0b00 xstop TLBI Seq Num Parity Err - 41 , 0b0, any; #-- 0b00 masked ST class Foreign Link Fail - 42 , 0b0, any; #-- 0b00 masked TimeBase Err DD2 only - 43 , 0b0, any; #-- 0b00 masked XPT Informational DD2 only - 44 , 0b0, any; #-- 0b00 masked Spare / CmdQ CE - 45 , 0b0, any; #-- 0b00 masked Spare / CmdQ UE - 46 , 0b1, any; #-- 0b11 capp mach check PSL Credit Timeout - 47 , 0b0, any; #-- 0b00 masked Scom satellite parity error Copy 1 / Spare - 48 , 0b0, any; #-- 0b00 masked Scom satellite parity error Copy 2 / Spare - 49 , 0b0, (capp_dual); #-- 0b00 masked NA / Scom satellite parity error Copy 1 - 50 , 0b0, (capp_dual); #-- 0b00 masked NA / Scom satellite parity error Copy 2 -} - -scom 0x02013187 { - bits , scom_data, expr; #--Action - 0 , 0b0, (capp_dual); #-- 0b00 masked BAR PE - 1 , 0b0, (capp_dual); #-- 0b00 xstop Register PE - 2 , 0b1, (capp_dual); #-- 0b01 recovered attn Master Array CE - 3 , 0b0, (capp_dual); #-- 0b10 xstop Master Array UE - 4 , 0b1, (capp_dual); #-- 0b11 capp mach check Timer Expired Recoverable Epoch - 5 , 0b0, (capp_dual); #-- 0b00 xstop Timer Expired Xstop RCS sequencer hang - 6 , 0b1, (capp_dual); #-- 0b11 capp mach check PSL Cmd UE - 7 , 0b1, (capp_dual); #-- 0b11 capp mach check PSL Cmd SUE - 8 , 0b1, (capp_dual); #-- 0b01 recovered attn Snoop Array CE - 9 , 0b0, (capp_dual); #-- 0b00 xstop Snoop Array UE - 10 , 0b0, (capp_dual); #-- 0b00 xstop Recovery Failed - 11 , 0b1, (capp_dual); #-- 0b11 capp mach check Illegal LPC Bar Access DD2 only - 12 , 0b1, (capp_dual); #-- 0b11 capp mach check XPT Recoverable err DD2 only - 13 , 0b1, (capp_dual); #-- 0b11 capp mach check Master Recoverable Err - 14 , 0b0, (capp_dual); #-- 0b00 masked Spare - 15 , 0b0, (capp_dual); #-- 0b00 masked Scom satellite parity Err - 16 , 0b0, (capp_dual); #-- 0b00 xstop Master Sys Xstop Err - 17 , 0b0, (capp_dual); #-- 0b00 xstop Snooper Sys Xstop Err - 18 , 0b0, (capp_dual); #-- 0b00 xstop XPT Sys Xstop Err - 19 , 0b0, (capp_dual); #-- 0b00 masked Master Uop Err1 For Lab Use only - 20 , 0b0, (capp_dual); #-- 0b00 masked Master Uop Err2 For Lab Use only - 21 , 0b0, (capp_dual); #-- 0b00 masked Master Uop Err3 For Lab Use only - 22 , 0b0, (capp_dual); #-- 0b00 masked Snooper Uop Err1 For Lab Use only - 23 , 0b0, (capp_dual); #-- 0b00 masked Snooper Uop Err2 For Lab Use only - 24 , 0b0, (capp_dual); #-- 0b00 masked Snooper Uop Err3 For Lab Use only - 25 , 0b0, (capp_dual); #-- 0b00 xstop Unsolicited PowerBus Data or Cresp - 26 , 0b0, (capp_dual); #-- 0b00 xstop PowerBus parity Err - 27 , 0b0, (capp_dual); #-- 0b00 masked PowerBus Data Hang Err - 28 , 0b0, (capp_dual); #-- 0b00 masked PowerBus Hang Err - 29 , 0b0, (capp_dual); #-- 0b00 xstop PowerBus Address Err on LD class APC op - 30 , 0b0, (capp_dual); #-- 0b00 xstop PowerBus Address Err on ST class APC op - 31 , 0b1, (capp_dual); #-- 0b11 capp mach check PHB Link Down - 32 , 0b0, (capp_dual); #-- 0b00 masked LD class Foreign Link err - 33 , 0b0, (capp_dual); #-- 0b00 masked Foreign Link Hang err - 34 , 0b1, (capp_dual); #-- 0b01 recovered attn XPT PowerBus CE - 35 , 0b0, (capp_dual); #-- 0b00 masked XPT PowerBus UE - 36 , 0b0, (capp_dual); #-- 0b00 masked XPT PowerBus SUE - 37 , 0b1, (capp_dual); #-- 0b11 capp mach check TLBI Timeout Err - 38 , 0b0, (capp_dual); #-- 0b00 xstop TLBI Seq Err - 39 , 0b0, (capp_dual); #-- 0b00 xstop TLBI Bad Op Err - 40 , 0b0, (capp_dual); #-- 0b00 xstop TLBI Seq Num Parity Err - 41 , 0b0, (capp_dual); #-- 0b00 masked ST class Foreign Link Fail - 42 , 0b0, (capp_dual); #-- 0b00 masked TimeBase Err DD2 only - 43 , 0b0, (capp_dual); #-- 0b00 masked XPT Informational DD2 only - 44 , 0b0, (capp_dual); #-- 0b00 masked CmdQ CE - 45 , 0b0, (capp_dual); #-- 0b00 masked CmdQ UE - 46 , 0b1, (capp_dual); #-- 0b11 capp mach check PSL Credit Timeout - 47 , 0b0, (capp_dual); #-- 0b00 masked Spare - 48 , 0b0, (capp_dual); #-- 0b00 masked Spare - 49 , 0b0, (capp_dual); #-- 0b00 masked Scom satellite parity error Copy 1 - 50 , 0b0, (capp_dual); #-- 0b00 masked Scom satellite parity error Copy 2 -} - -#-- CXA CAPP FIR Mask Register -scom 0x02013003 { - bits , scom_data, expr; - 0 , 0b1, any; #-- BAR PE - 1 , 0b1, (!capp_prod); #-- mask for DD1 Register PE - 1 , 0b0, (capp_prod); #-- Register PE - 2 , 0b0, any; #-- Master Array CE - 3 , 0b0, any; #-- Master Array UE - 4 , 0b0, any; #-- Timer Expired Recoverable Epoch - 5 , 0b0, any; #-- Timer Expired Xstop RCS sequencer hang - 6 , 0b0, any; #-- PSL Cmd UE - 7 , 0b0, any; #-- PSL Cmd SUE - 8 , 0b0, any; #-- Snoop Array CE - 9 , 0b0, any; #-- Snoop Array UE - 10 , 0b0, any; #-- Recovery Failed - 11 , 0b1, (!capp_prod); #-- mask for DD1 Illegal LPC Bar Access DD2 only - 11 , 0b0, (capp_prod); #-- Illegal LPC Bar Access DD2 only - 12 , 0b1, (!capp_prod); #-- mask for DD1 XPT Recoverable err DD2 only - 12 , 0b0, (capp_prod); #-- XPT Recoverable err DD2 only - 13 , 0b0, any; #-- Master Recoverable Err - 14 , 0b1, any; #-- Spare - 15 , 0b1, any; #-- Scom satellite parity Err - 16 , 0b0, any; #-- Master Sys Xstop Err - 17 , 0b0, any; #-- Snooper Sys Xstop Err - 18 , 0b1, (!capp_prod); #-- mask for DD1 XPT Sys Xstop Err - 18 , 0b0, (capp_prod); #-- XPT Sys Xstop Err - 19 , 0b1, any; #-- Master Uop Err1 For Lab Use only - 20 , 0b1, any; #-- Master Uop Err2 For Lab Use only - 21 , 0b1, any; #-- Master Uop Err3 For Lab Use only - 22 , 0b1, any; #-- Snooper Uop Err1 ³or Lab Use only - 23 , 0b1, any; #-- Snooper Uop Err2 ³or Lab Use only - 24 , 0b1, any; #-- Snooper Uop Err3 ³or Lab Use only - 25 , 0b0, any; #-- Unsolicited PowerBus Data or Cresp - 26 , 0b1, (!capp_prod); #-- mask for DD1 PowerBus Parity Err - 26 , 0b0, (capp_prod); #-- PowerBus Parity Err - 27 , 0b1, any; #-- PowerBus Data Hang Err - 28 , 0b1, any; #-- PowerBus Hang Err - 29 , 0b0, any; #-- PowerBus Address Err on LD class APC op - 30 , 0b0, any; #-- PowerBus Address Err on ST class APC op - 31 , 0b0, any; #-- PHB Link Down - 32 , 0b1, any; #-- LD class Foreign Link err - 33 , 0b1, any; #-- Foreign Link Hang err - 34 , 0b0, any; #-- XPT PowerBus CE - 35 , 0b1, any; #-- XPT PowerBus UE - 36 , 0b1, any; #-- XPT PowerBus SUE - 37 , 0b0, any; #-- TLBI Timeout Err - 38 , 0b0, any; #-- TLBI Seq Err - 39 , 0b0, any; #-- TLBI Bad Op Err - 40 , 0b0, any; #-- TLBI Seq Num Parity Err - 41 , 0b1, any; #-- ST class Foreign Link Fail - 42 , 0b1, any; #-- TimeBase Err DD2 only - 43 , 0b1, any; #-- XPT Informational DD2 only - 44 , 0b1, any; #-- Spare / CmdQ CE - 45 , 0b1, any; #-- Spare / CmdQ UE - 46 , 0b0, any; #-- PSL Credit Timeout - 47 , 0b1, any; #-- Scom satellite parity error Copy 1 / Spare - 48 , 0b1, any; #-- Scom satellite parity error Copy 2 / Spare - 49 , 0b1, (capp_dual); #-- NA / Scom satellite parity error Copy 1 - 50 , 0b1, (capp_dual); #-- NA / Scom satellite parity error Copy 2 -} - -scom 0x02013183 { - bits , scom_data, expr; - 0 , 0b1, (capp_dual); #-- BAR PE - 1 , 0b1, (capp_dual && !capp_prod); #-- Register PE - 1 , 0b0, (capp_dual && capp_prod); #-- Register PE - 2 , 0b0, (capp_dual); #-- Master Array CE - 3 , 0b0, (capp_dual); #-- Master Array UE - 4 , 0b0, (capp_dual); #-- Timer Expired Recoverable Epoch - 5 , 0b0, (capp_dual); #-- Timer Expired Xstop RCS sequencer hang - 6 , 0b0, (capp_dual); #-- PSL Cmd UE - 7 , 0b0, (capp_dual); #-- PSL Cmd SUE - 8 , 0b0, (capp_dual); #-- Snoop Array CE - 9 , 0b0, (capp_dual); #-- Snoop Array UE - 10 , 0b0, (capp_dual); #-- Recovery Failed - 11 , 0b1, (capp_dual && !capp_prod); #-- Illegal LPC Bar Access DD2 only - 11 , 0b0, (capp_dual && capp_prod); #-- Illegal LPC Bar Access DD2 only - 12 , 0b1, (capp_dual && !capp_prod); #-- XPT Recoverable err DD2 only - 12 , 0b0, (capp_dual && capp_prod); #-- XPT Recoverable err DD2 only - 13 , 0b0, (capp_dual); #-- Master Recoverable Err - 14 , 0b1, (capp_dual); #-- Spare - 15 , 0b1, (capp_dual); #-- Scom satellite parity Err - 16 , 0b0, (capp_dual); #-- Master Sys Xstop Err - 17 , 0b0, (capp_dual); #-- Snooper Sys Xstop Err - 18 , 0b1, (capp_dual && !capp_prod); #-- XPT Sys Xstop Err - 18 , 0b0, (capp_dual && capp_prod); #-- XPT Sys Xstop Err - 19 , 0b1, (capp_dual); #-- Master Uop Err1 For Lab Use only - 20 , 0b1, (capp_dual); #-- Master Uop Err2 For Lab Use only - 21 , 0b1, (capp_dual); #-- Master Uop Err3 For Lab Use only - 22 , 0b1, (capp_dual); #-- Snooper Uop Err1 ³or Lab Use only - 23 , 0b1, (capp_dual); #-- Snooper Uop Err2 ³or Lab Use only - 24 , 0b1, (capp_dual); #-- Snooper Uop Err3 ³or Lab Use only - 25 , 0b0, (capp_dual); #-- Unsolicited PowerBus Data or Cresp - 26 , 0b1, (capp_dual && !capp_prod); #-- PowerBus Parity Err - 26 , 0b0, (capp_dual && capp_prod); #-- PowerBus Parity Err - 27 , 0b1, (capp_dual); #-- PowerBus Data Hang Err - 28 , 0b1, (capp_dual); #-- PowerBus Hang Err - 29 , 0b0, (capp_dual); #-- PowerBus Address Err on LD class APC op - 30 , 0b0, (capp_dual); #-- PowerBus Address Err on ST class APC op - 31 , 0b0, (capp_dual); #-- PHB Link Down - 32 , 0b1, (capp_dual); #-- LD class Foreign Link err - 33 , 0b1, (capp_dual); #-- Foreign Link Hang err - 34 , 0b0, (capp_dual); #-- XPT PowerBus CE - 35 , 0b1, (capp_dual); #-- XPT PowerBus UE - 36 , 0b1, (capp_dual); #-- XPT PowerBus SUE - 37 , 0b0, (capp_dual); #-- TLBI Timeout Err - 38 , 0b0, (capp_dual); #-- TLBI Seq Err - 39 , 0b0, (capp_dual); #-- TLBI Bad Op Err - 40 , 0b0, (capp_dual); #-- TLBI Seq Num Parity Err - 41 , 0b1, (capp_dual); #-- ST class Foreign Link Fail - 42 , 0b1, (capp_dual); #-- TimeBase Err DD2 only - 43 , 0b1, (capp_dual); #-- XPT Informational DD2 only - 44 , 0b1, (capp_dual); #-- CmdQ CE - 45 , 0b1, (capp_dual); #-- CmdQ UE - 46 , 0b0, (capp_dual); #-- PSL Credit Timeout - 47 , 0b1, (capp_dual); #-- Spare - 48 , 0b1, (capp_dual); #-- Spare - 49 , 0b1, (capp_dual); #-- Scom satellite parity error Copy 1 - 50 , 0b1, (capp_dual); #-- Scom satellite parity error Copy 2 -}
\ No newline at end of file diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile deleted file mode 100644 index 5d3e10797..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile +++ /dev/null @@ -1,340 +0,0 @@ -#-- $Id: p8.dmi.custom.scom.initfile,v 1.21 2014/02/20 15:28:48 garyp Exp $ -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -#-- 1.21|garyp |02/19/14|Added rx_min_eye_width and rx_min_eye_height for manufacturing and lab thresholding -#-- 1.20|jgrell |12/03/13|Set rx_eo_ddc_timeout_sel to 110 for DD2 -#-- 1.19|jgrell |10/29/13|Changed rx_ds_timeout_sel setting to 111 -#-- 1.18|jgrell |10/28/13|Re-enabled recal bits for DD2+ hw -#-- 1.17|jgrell |09/24/13|Changed "1" expression to "any" -#-- 1.15|jgrell |09/17/13|Added DD2 specific inits -#-- 1.13|jgrell |09/12/13|Re-added "Override" settings -#-- 1.9 |thomsen |04/30/13|Added TGT1. to ATTR_CHIP_EC* attribute instances to reference a chip target rather than a chiplet target -#-- 1.8 |jgrell |04/18/13|Added EC level control of the Recal DFE, DDC, and CTLE enable bits. ('0' when EC < 20) -#-- 1.7 |jgrell |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab. -#-- 1.6 |thomsen |03/07/13|Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab. -#-- 1.5 |thomsen |02/12/13|Added Lane Power Ups and Clock Invert -#-- 1.4 |jmcgill |02/09/13|Use chiplet level targeting, reference attributes -#-- 1.3 |thomsen |02/01/13|Fixed tx_msbswap for groups 1,2,3 -#-- 1.2 |berger |02/01/13|Removed a handful of settings already in the base file, added sim attr for MSB swap and lane invert -#-- 1.1 |thomsen |01/23/13|Created initial version -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- -#-- TARGETS: -#-- SYS. Chiplet target -#-- TGT1. Proc target - -#-- ATTR_CHIP_UNIT_POS is the MCS unit number (0-7 on Venice, 4-7 on Murano) and corresponds to the scom address translation done in -#-- the p8.chipunit.scominfo file. It is used to be able to select a specific clock group number. -#-- Chip UNIT_POS DMI_UNIT CLOCKGRP -#-- ---- -------- -------- -------- -#-- Venice: 0-3 DMI0 3-0 -#-- 4-7 DMI1 3-0 -#-- Murano: 4-7 DMI1 3-0 - - -SyntaxVersion = 1 - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -#-- -#-- Includes -#-- Note: Must include the path to the .define file. -#-- -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -include edi.io.define - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -#-- -#-- Defines -#-- -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -define def_IS_HW = (SYS.ATTR_IS_SIMULATION == 0); -define def_IS_VBU = (SYS.ATTR_IS_SIMULATION == 1); - -define def_all_lanes=11111; - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -#-- Overrides -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -#--***************** -#-- set rx_min_eye_width and rx_min_eye_height if in manufacturing mode -#--***************** -scom 0x800.0b(rx_result_chk_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - rx_min_eye_width, SYS.ATTR_MNFG_DMI_MIN_EYE_WIDTH, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); - rx_min_eye_height, SYS.ATTR_MNFG_DMI_MIN_EYE_HEIGHT, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); -} - - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -# __ ____ __ __ -# / / ____ _____ ___ / __ \____ _ _____ _____ / / / /___ -# / / / __ `/ __ \/ _ \ / /_/ / __ \ | /| / / _ \/ ___/ / / / / __ \ -# / /___/ /_/ / / / / __/ / ____/ /_/ / |/ |/ / __/ / / /_/ / /_/ / -# /_____/\__,_/_/ /_/\___/ /_/ \____/|__/|__/\___/_/ \____/ .___/ -# /_/ -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -# rx_lane_pdwn -#scom 0x800.0b(rx_mode_pl)(tx_grp3)(def_all_lanes).0x(dmi0_gcr_addr){ -# bits, scom_data; -# rx_lane_pdwn, 0b0; -#} - -# tx_lane_pdwn -#scom 0x800.0b(tx_mode_pl)(tx_grp3)(def_all_lanes).0x(dmi0_gcr_addr){ -# bits, scom_data; -# tx_lane_pdwn, 0b0; -#} - - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -# _______ __ __ ___ _ ________ _____ ___ ____________ ______ -# /_ __/ |/ / / / / | / | / / ____/ / _/ | / / | / / ____/ __ \/_ __/ -# / / | / / / / /| | / |/ / __/ / // |/ /| | / / __/ / /_/ / / / -# / / / | / /___/ ___ |/ /| / /___ _/ // /| / | |/ / /___/ _, _/ / / -# /_/ /_/|_| /_____/_/ |_/_/ |_/_____/ /___/_/ |_/ |___/_____/_/ |_| /_/ -# -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -# These only do a scom if the invert attribute is set (saves scom's). -# The default scanflush value of tx_lane_invert for each lane is '0'. - -# Lane 0 -# 0x8004040002011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_0).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x80000000) > 0); -} - -# Lane 1 -# 0x8004040102011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_1).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x40000000) > 0); -} - -# Lane 2 -# 0x8004040202011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_2).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x20000000) > 0); -} - -# Lane 3 -# 0x8004040302011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_3).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x10000000) > 0); -} - -# Lane 4 -# 0x8004040402011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_4).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x08000000) > 0); -} - -# Lane 5 -# 0x8004040502011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_5).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x04000000) > 0); -} - -# Lane 6 -# 0x8004040602011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_6).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x02000000) > 0); -} - -# Lane 7 -# 0x8004040702011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_7).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x01000000) > 0); -} - -# Lane 8 -# 0x8004040802011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_8).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00800000) > 0); -} - -# Lane 9 -# 0x8004040902011E3F { -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_9).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00400000) > 0); -} - -# Lane 10 -# 0x8004040A02011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_10).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00200000) > 0); -} - -# Lane 11 -# 0x8004040B02011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_11).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00100000) > 0); -} - -# Lane 12 -# 0x8004040C02011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_12).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00080000) > 0); -} - -# Lane 13 -# 0x8004040D02011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_13).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00040000) > 0); -} - -# Lane 14 -# 0x8004040E02011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_14).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00020000) > 0); -} - -# Lane 15 -# 0x8004040F02011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_15).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00010000) > 0); -} - -# Lane 16 -# 0x8004041002011E3F -scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_16).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - tx_lane_invert, 0b1, ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00008000) > 0); -} - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -# _______ __ ________ __ __ ____ __ -# /_ __/ |/ / / ____/ / / //_/ / _/___ _ _____ _____/ /_ -# / / | / / / / / / ,< / // __ \ | / / _ \/ ___/ __/ -# / / / | / /___/ /___/ /| | _/ // / / / |/ / __/ / / /_ -# /_/ /_/|_| \____/_____/_/ |_| /___/_/ /_/|___/\___/_/ \__/ - -# figlet -fslant -#------------------------------------------------------------------------------------- -#--*********************************************************************************** -# CLK Lane (assigned to bit 31 of TX Lane Invert Attribute) -# 0x800???7008010C3F -scom 0x800.0b(tx_clk_mode_pg)(tx_grp3)(lane_na).0x(dmi0_gcr_addr) { -bits, scom_data, expr; -tx_lane_invert, 0b1, (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000001) > 0; -} - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -# __ ________ ____ _____ -# / |/ / ___// __ ) / ___/ ______ _____ -# / /|_/ /\__ \/ __ | \__ \ | /| / / __ `/ __ \ -# / / / /___/ / /_/ / ___/ / |/ |/ / /_/ / /_/ / -# /_/ /_//____/_____/ /____/|__/|__/\__,_/ .___/ -# /_/ -# -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -# 0x800C1C0002011E3F -scom 0x800.0b(tx_mode_pg)(tx_grp3)(lane_na).0x(dmi0_gcr_addr) { - bits, scom_data; - tx_msbswap, (ATTR_EI_BUS_TX_MSBSWAP & 0x01); -} - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -# Recal (and part of DMI DFE Override) -#------------------------------------------------------------------------------------- -#--*********************************************************************************** -# HW235842 and HW244323 - -scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { -bits, scom_data, expr; -rx_rc_enable_dfe_h1_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0 || ATTR_DMI_DFE_OVERRIDE==1; -rx_rc_enable_ddc, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0; -rx_rc_enable_ctle_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0; -rx_rc_enable_h1ap_tweak, 0b0, ATTR_DMI_DFE_OVERRIDE==1; -} - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -# DMI DFE Override (HW244323) -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -#scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { -#bits, scom_data, expr; -#rx_rc_enable_dfe_h1_cal, 0b0, ATTR_DMI_DFE_OVERRIDE==1; -#rx_rc_enable_h1ap_tweak, 0b0, ATTR_DMI_DFE_OVERRIDE==1; -#} - -scom 0x800.0b(rx_eo_step_cntl_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { -bits, scom_data, expr; -rx_eo_enable_dfe_h1_cal, 0b0, ATTR_DMI_DFE_OVERRIDE==1; -rx_eo_enable_h1ap_tweak, 0b0, ATTR_DMI_DFE_OVERRIDE==1; -} - -scom 0x800.0b(rx_amax_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { -bits, scom_data, expr; -rx_amax_high, 0b01101110, ATTR_DMI_DFE_OVERRIDE==1; -rx_amax_low, 0b01010000, ATTR_DMI_DFE_OVERRIDE==1; -} - -scom 0x800.0b(rx_amp_val_pl)(rx_grp3)(def_all_lanes).0x(dmi0_gcr_addr) { -bits, scom_data, expr; -rx_amp_gain, 0b1001, ATTR_DMI_DFE_OVERRIDE==1; -} - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -#-- DD2+ Murano & Venice -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -scom 0x800.0b(rx_timeout_sel_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - rx_sls_timeout_sel_dd2, 0b1010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; -} - -scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { - bits, scom_data, expr; - rx_eo_ddc_timeout_sel, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; -} - -############################################################################################ -# END OF FILE -############################################################################################ diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile deleted file mode 100644 index c3b18dda0..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile +++ /dev/null @@ -1,1480 +0,0 @@ -#-- $Id: p8.dmi.scom.initfile,v 1.26 2014/02/04 19:06:24 jgrell Exp $ - - -#################################################################### -## -## Auto-genrated by fig2scominit.pl -## Based on SETUP_ID_MODE DMI_BUS_TR_HW -## from ../../logic/mesa_sim/fusion/run/IODPV_MC_WRAP.IODPV_MC_WRAP.figdb -## -## Created on Tue Nov 26 11:33:54 CST 2013, by jgrell -#################################################################### - -## -- CHANGE HISTORY: - ## -------------------------------------------------------------------------------- - ## -- VersionID: |Author: | Date: | Comment: - ## -- -----------|---------|--------|------------------------------------------------- - ## -- jgr14020400| jgr |02-04-14| Bus ID change for FIRs - ## -- jgr13112600| jgr |11-26-13| CYC rx_ds_timeout_sel setting changed to 111 - ## -- jgr13102800| jgr |10-28-13| rx_ds_timeout_sel change (110 -> 111) - ## -- jgr13082100| jgr |08-21-13| Added tx_zcal inits so they can be removed from scan - ## -- jfg13072400| jfg |07-24-13| HW253558: change pgooddly to MAX from lab feedback - ## -- mbs13071200| mbs |07-12-13| Updates for HW239870 and HW258990 - ## -- | | | Disable recal adjustment for allv1 (DFE bug) - ## -- jgr13041800| jgr |04-18-13| Added rx_max_ber_check_count setting to 0x03 - ## -- smr13032500| SMR |03-25-13| Changed rx_dyn_recal_overall_timeout_sel init to 0b100 & rx_sls_timeout_sel init to 0b110 - ## -- jgr13031300| jgr |03-13-13| Added missing entries from rel 0128 - ## -- mbs13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) - ## -- mbs12121100| mbs |12-11-12| Added rx_prot_speed_slct and rx_c4_sel - ## -- smr12112700| SMR |11-27-12| Added rx_dyn_recal_overall_timeout_sel init to 0b001 - ## -- jfg12112101| jfg |11-21-12| Added Zcal inits - ## -- jfg12112100| jfg |11-21-12| Added CU pll modes - ## -- 12111300| berger |11-13-12| Updated with HW eyeopt and recal settings - ## -- 12062500| SMR |06-25-12| HW210654: Added rx_sls_timeout_sel default of 1 - ## -- 11012500| mbs |01-25-12| Swizzle and typo fixes for HW191494, HW191518, HW188304 - ## -- 11011912| RJR |01-17-12| Added RX_CTL2_REGS FILE REFERENCES - ## -- 12011800| berger |01-19-12| Added SETUP_ID_MODE dials - ## -- 11121500| thomsen |12-15-11| Added Per-Pack GCR SCOM Addresses for Regchk (HW188381,HW182867) - ## -- | | | Removed 0x0000040000000000 from TX address definitions since it is in the lower level figtree files (HW187781,HW187893) - ## -- 11102100| SMR |10-21-11| HW181193: Added rx_dyn_rpr_enc_bad_data_lane_width register - ## -- 11102500| jfg |10-25-11| HW181485,HW181791: swizzle updates for scramble - ## -- 11092900| SMR |09-29-11| HW171978: Added dyn rpr error tallying defaults - ## -- 11050300| SMR |05-02-11| Added tx_max_bad_lanes - ## -- 11032200| jg |02-17-11| Added RX PLLREG register offsets - ## -- 11022800| thomsen |02-28-11| Fixed RX/TX scramble tap pattern match problem between driver and receiver. Also fixed in iodnc_mb_top.fig. - ## -- 11021700| thomsen |02-17-11| Fixed RX_BUS_WIDTH from 17 to 24 - ## -- 11021600| thomsen |02-16-11| Added Per-Bus, Per-Lane and Per-Group GCR SCOM addresses so Regchk would pass - ## -- 11020200| thomsen |02-02-11| Added RX & TX scramble/descramble tap ID settings - ## -- 11012500| berger |01-25-11| added TX lane disable and rx_bus_width fields, added missing SETUP_ID fields - ## -- 11010600| smc |01-06-11| changed prefix (generic vhdl only) to iodpv to match post generic - ## -- 11010600| berger |01-06-11| added lane disable and max bad lane - ## -- 10121600| thomsen |12-16-10| Added RX_FENCE - ## -- 10121300| thomsen |12-13-10| Fixed END_LANE_ID values per HW133020 - ## -- 10120800| thomsen |12-08-10| Added TX_BUS_WIDTH - ## -- 10102601| thomsen |10-26-10| Renamed gdial enum names from MC_BUS to DMI_BUS - ## -- 10102600| thomsen |10-26-10| Initial version - ## -------------------------------------------------------------------------------- - ## -- TODO: These need to be modified for Z - ## -- TODO: Not sure how to handle gdials since Z has extra the extra group, ie. P won't acknowledge RX4.RXCTL.RX_CTL_REGS.RX_* dials exist. - - -SyntaxVersion = 1 - - - -#################################################################### -# Define File -#################################################################### -include edi.io.define - - define def_IS_HW = SYS.ATTR_IS_SIMULATION == 0; - define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1; - - - -define def_bus_id3 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 7)); -define def_bus_id2 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 6)); -define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 1) || (ATTR_CHIP_UNIT_POS == 5)); -define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 0) || (ATTR_CHIP_UNIT_POS == 4)); - -#define def_bus_id3 = ((ATTR_CHIP_UNIT_POS == 0) || (ATTR_CHIP_UNIT_POS == 4)); -#define def_bus_id2 = ((ATTR_CHIP_UNIT_POS == 1) || (ATTR_CHIP_UNIT_POS == 5)); -#define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 7)); -#define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 6)); - - - -#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_P_4X_PB -scom 0x800F1C6002011A3F { - bits, scom_data, expr; - tx_zcal_p_4x, 0b00100, any; -} - -#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_SWO2_PB -scom 0x800F2C6002011A3F { - bits, scom_data, expr; - tx_zcal_sm_max_val, 0b1000110, any; - tx_zcal_sm_min_val, 0b0010101 , def_IS_HW; - tx_zcal_sm_min_val, 0b0010110 , def_IS_VBU; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG -scom 0x800AF06002011A3F { - bits, scom_data, expr; - rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id3; - rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id0; - rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id0; - rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id1; - rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id1; - rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id2; - rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id2; - rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id3; - rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id0; - rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id0; - rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id1; - rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id1; - rx_max_ber_check_count, 0b00000011, def_IS_HW && def_bus_id2; - rx_max_ber_check_count, 0b00000000, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP -scom 0x800B786002011A3F { - bits, scom_data, expr; - rx_amin_cfg, 0b111, def_IS_HW && def_bus_id3; - rx_amin_cfg, 0b111, def_IS_HW && def_bus_id0; - rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; - rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; - rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id3; - rx_amin_cfg, 0b111, def_IS_HW && def_bus_id0; - rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; - rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; - rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_anap_cfg, 0b10, def_IS_HW && def_bus_id3; - rx_anap_cfg, 0b10, def_IS_HW && def_bus_id0; - rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id3; - rx_anap_cfg, 0b10, def_IS_HW && def_bus_id0; - rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_h1_cfg, 0b01, def_IS_HW && def_bus_id3; - rx_h1_cfg, 0b01, def_IS_HW && def_bus_id0; - rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; - rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; - rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id3; - rx_h1_cfg, 0b01, def_IS_HW && def_bus_id0; - rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; - rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; - rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_peak_cfg, 0b10, def_IS_HW && def_bus_id3; - rx_peak_cfg, 0b10, def_IS_HW && def_bus_id0; - rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_peak_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id3; - rx_peak_cfg, 0b10, def_IS_HW && def_bus_id0; - rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_peak_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP -scom 0x800B806002011A3F { - bits, scom_data, expr; - rx_ber_cfg, 0b100, def_IS_HW && def_bus_id3; - rx_ber_cfg, 0b100, def_IS_HW && def_bus_id0; - rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; - rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; - rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id3; - rx_ber_cfg, 0b100, def_IS_HW && def_bus_id0; - rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; - rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; - rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id3; - rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id0; - rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; - rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; - rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id3; - rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id0; - rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; - rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; - rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id3; - rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id0; - rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id3; - rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id0; - rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id3; - rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id0; - rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; - rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; - rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id3; - rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id0; - rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; - rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; - rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_prot_cfg, 0b10, def_IS_HW && def_bus_id3; - rx_prot_cfg, 0b10, def_IS_HW && def_bus_id0; - rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_prot_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id3; - rx_prot_cfg, 0b10, def_IS_HW && def_bus_id0; - rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id0; - rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1; - rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id1; - rx_prot_cfg, 0b10, def_IS_HW && def_bus_id2; - rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG -scom 0x800A186002011A3F { - bits, scom_data, expr; - rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id3; - rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id0; - rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id1; - rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_TIMEOUTS_PP -scom 0x800B406002011A3F { - bits, scom_data, expr; - rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id3; - rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; - rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; - rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG -scom 0x8009D86002011A3F { - bits, scom_data, expr; - rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id3; - rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id0; - rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id1; - rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id2; - rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id3; - rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id0; - rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id1; - rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id2; - rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id3; - rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id0; - rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id1; - rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG -scom 0x800AE06002011A3F { - bits, scom_data, expr; - rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id3; - rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id0; - rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id1; - rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id2; - rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id3; - rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id0; - rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id1; - rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_EO_CONVERGENCE_PG -scom 0x800A806002011A3F { - bits, scom_data, expr; - rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id3; - rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id0; - rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id0; - rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id1; - rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id1; - rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id2; - rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id2; - rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id3; - rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id0; - rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id0; - rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id1; - rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id1; - rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id2; - rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG -scom 0x800A386002011A3F { - bits, scom_data, expr; - rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id3; - rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id3; - rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id3; - rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id3; - rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id3; - rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id3; - rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id3; - rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id3; - rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_final_l2u_adj, 0b1, def_bus_id3; - rx_eo_enable_final_l2u_adj, 0b1, def_bus_id0; - rx_eo_enable_final_l2u_adj, 0b1, def_bus_id1; - rx_eo_enable_final_l2u_adj, 0b1, def_bus_id2; - rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id3; - rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id3; - rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id3; - rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id3; - rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id3; - rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id3; - rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id3; - rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id3; - rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_FENCE_PG -scom 0x8009A86002011A3F { - bits, scom_data, expr; - rx_fence, 0b1, def_bus_id3; - rx_fence, 0b1, def_bus_id0; - rx_fence, 0b1, def_bus_id1; - rx_fence, 0b1, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x8008506002011A3F { - bits, scom_data, expr; - rx_bus_id, 0b000011, def_bus_id3; - rx_bus_id, 0b000000, def_bus_id0; - rx_bus_id, 0b000001, def_bus_id1; - rx_bus_id, 0b000010, def_bus_id2; - rx_group_id, 0b000000, def_bus_id3; - rx_group_id, 0b000000, def_bus_id0; - rx_group_id, 0b000000, def_bus_id1; - rx_group_id, 0b000000, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_ID2_PG -scom 0x8008586002011A3F { - bits, scom_data, expr; - rx_last_group_id, 0b000000, def_bus_id3; - rx_last_group_id, 0b000000, def_bus_id0; - rx_last_group_id, 0b000000, def_bus_id1; - rx_last_group_id, 0b000000, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_ID3_PG -scom 0x8008606002011A3F { - bits, scom_data, expr; - rx_end_lane_id, 0b0010111, def_bus_id3; - rx_end_lane_id, 0b0010111, def_bus_id0; - rx_end_lane_id, 0b0010111, def_bus_id1; - rx_end_lane_id, 0b0010111, def_bus_id2; - rx_start_lane_id, 0b0000000, def_bus_id3; - rx_start_lane_id, 0b0000000, def_bus_id0; - rx_start_lane_id, 0b0000000, def_bus_id1; - rx_start_lane_id, 0b0000000, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG -scom 0x8009286002011A3F { - bits, scom_data, expr; - rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id3; - rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0; - rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1; - rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG -scom 0x8009306002011A3F { - bits, scom_data, expr; - rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id3; - rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id0; - rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id1; - rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG -scom 0x8009C06002011A3F { - bits, scom_data, expr; - rx_c4_sel, 0b00, def_IS_HW && def_bus_id3; - rx_c4_sel, 0b00, def_IS_HW && def_bus_id0; - rx_c4_sel, 0b11, def_IS_VBU && def_bus_id0; - rx_c4_sel, 0b00, def_IS_HW && def_bus_id1; - rx_c4_sel, 0b11, def_IS_VBU && def_bus_id1; - rx_c4_sel, 0b00, def_IS_HW && def_bus_id2; - rx_c4_sel, 0b11, def_IS_VBU && def_bus_id2; - rx_c4_sel, 0b11, def_IS_VBU && def_bus_id3; - rx_c4_sel, 0b00, def_IS_HW && def_bus_id0; - rx_c4_sel, 0b11, def_IS_VBU && def_bus_id0; - rx_c4_sel, 0b00, def_IS_HW && def_bus_id1; - rx_c4_sel, 0b11, def_IS_VBU && def_bus_id1; - rx_c4_sel, 0b00, def_IS_HW && def_bus_id2; - rx_c4_sel, 0b11, def_IS_VBU && def_bus_id2; - rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id3; - rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id0; - rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id0; - rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id1; - rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id1; - rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id2; - rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id2; - rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id3; - rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id0; - rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id0; - rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id1; - rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id1; - rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id2; - rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_MODE_PG -scom 0x8008186002011A3F { - bits, scom_data, expr; - rx_master_mode, 0b1, def_bus_id3; - rx_master_mode, 0b1, def_bus_id0; - rx_master_mode, 0b1, def_bus_id1; - rx_master_mode, 0b1, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG -scom 0x800AB86002011A3F { - bits, scom_data, expr; - rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id3; - rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id3; - rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id3; - rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id3; - rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id3; - rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id3; - rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id3; - rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id0; - rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id1; - rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b0, def_bus_id3; - rx_rc_enable_h1ap_tweak, 0b0, def_bus_id0; - rx_rc_enable_h1ap_tweak, 0b0, def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b0, def_bus_id2; - rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id3; - rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id3; - rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id3; - rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id3; - rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id3; - rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id3; - rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO1_PP -scom 0x800B906002011A3F { - bits, scom_data, expr; - rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id3; - rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id3; - rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP -scom 0x800B986002011A3F { - bits, scom_data, expr; - rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id3; - rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id3; - rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id3; - rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id3; - rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP -scom 0x800BA06002011A3F { - bits, scom_data, expr; - rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id3; - rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id3; - rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id3; - rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id3; - rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id3; - rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id3; - rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP -scom 0x800B606002011A3F { - bits, scom_data, expr; - rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP -scom 0x800B686002011A3F { - bits, scom_data, expr; - rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP -scom 0x800B706002011A3F { - bits, scom_data, expr; - rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id3; - rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id3; - rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG -scom 0x8009106002011A3F { - bits, scom_data, expr; - rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id3; - rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id3; - rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id3; - rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id3; - rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id3; - rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id3; - rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id3; - rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id3; - rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id3; - rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; - rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id3; - rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id0; - rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id1; - rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG -scom 0x8008986002011A3F { - bits, scom_data, expr; - rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id3; - rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id0; - rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id0; - rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id1; - rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1; - rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2; - rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2; - rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id3; - rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id0; - rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id0; - rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id1; - rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1; - rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2; - rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2; - rx_ds_timeout_sel, 0b111, def_bus_id3; - rx_ds_timeout_sel, 0b111, def_bus_id0; - rx_ds_timeout_sel, 0b111, def_bus_id1; - rx_ds_timeout_sel, 0b111, def_bus_id2; - rx_sls_timeout_sel, 0b110, def_bus_id3; - rx_sls_timeout_sel, 0b110, def_bus_id0; - rx_sls_timeout_sel, 0b110, def_bus_id1; - rx_sls_timeout_sel, 0b110, def_bus_id2; - rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id3; - rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id0; - rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1; - rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id2; - rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id3; - rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id0; - rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1; - rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG -scom 0x8009986002011A3F { - bits, scom_data, expr; - rx_rx_bus_width, 0b0011000, def_bus_id3; - rx_rx_bus_width, 0b0011000, def_bus_id0; - rx_rx_bus_width, 0b0011000, def_bus_id1; - rx_rx_bus_width, 0b0011000, def_bus_id2; - rx_tx_bus_width, 0b0010001, def_bus_id3; - rx_tx_bus_width, 0b0010001, def_bus_id0; - rx_tx_bus_width, 0b0010001, def_bus_id1; - rx_tx_bus_width, 0b0010001, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG -scom 0x8009586002011A3F { - bits, scom_data, expr; - rx_wtr_max_bad_lanes, 0b00010, def_bus_id3; - rx_wtr_max_bad_lanes, 0b00010, def_bus_id0; - rx_wtr_max_bad_lanes, 0b00010, def_bus_id1; - rx_wtr_max_bad_lanes, 0b00010, def_bus_id2; -} - -#RX3.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG -scom 0x800A306002011A3F { - bits, scom_data, expr; - rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id3; - rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id0; - rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0; - rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; - rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; - rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id3; - rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id0; - rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0; - rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; - rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; - rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id3; - rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id0; - rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id0; - rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1; - rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id2; - rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2; - rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id3; - rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id0; - rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id0; - rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1; - rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id2; - rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2; -} - -#RX3.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06002011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, def_bus_id3; - rx_prbs_tap_id, 0b000, def_bus_id0; - rx_prbs_tap_id, 0b000, def_bus_id1; - rx_prbs_tap_id, 0b000, def_bus_id2; -} - -#RX3.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06102011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, def_bus_id3; - rx_prbs_tap_id, 0b001, def_bus_id0; - rx_prbs_tap_id, 0b001, def_bus_id1; - rx_prbs_tap_id, 0b001, def_bus_id2; -} - -#RX3.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06202011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, def_bus_id3; - rx_prbs_tap_id, 0b010, def_bus_id0; - rx_prbs_tap_id, 0b010, def_bus_id1; - rx_prbs_tap_id, 0b010, def_bus_id2; -} - -#RX3.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06302011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, def_bus_id3; - rx_prbs_tap_id, 0b011, def_bus_id0; - rx_prbs_tap_id, 0b011, def_bus_id1; - rx_prbs_tap_id, 0b011, def_bus_id2; -} - -#RX3.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06402011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, def_bus_id3; - rx_prbs_tap_id, 0b100, def_bus_id0; - rx_prbs_tap_id, 0b100, def_bus_id1; - rx_prbs_tap_id, 0b100, def_bus_id2; -} - -#RX3.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06502011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, def_bus_id3; - rx_prbs_tap_id, 0b101, def_bus_id0; - rx_prbs_tap_id, 0b101, def_bus_id1; - rx_prbs_tap_id, 0b101, def_bus_id2; -} - -#RX3.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06602011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, def_bus_id3; - rx_prbs_tap_id, 0b110, def_bus_id0; - rx_prbs_tap_id, 0b110, def_bus_id1; - rx_prbs_tap_id, 0b110, def_bus_id2; -} - -#RX3.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06702011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, def_bus_id3; - rx_prbs_tap_id, 0b111, def_bus_id0; - rx_prbs_tap_id, 0b111, def_bus_id1; - rx_prbs_tap_id, 0b111, def_bus_id2; -} - -#RX3.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B07402011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, def_bus_id3; - rx_prbs_tap_id, 0b011, def_bus_id0; - rx_prbs_tap_id, 0b011, def_bus_id1; - rx_prbs_tap_id, 0b011, def_bus_id2; -} - -#RX3.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B07502011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, def_bus_id3; - rx_prbs_tap_id, 0b010, def_bus_id0; - rx_prbs_tap_id, 0b010, def_bus_id1; - rx_prbs_tap_id, 0b010, def_bus_id2; -} - -#RX3.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B07602011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, def_bus_id3; - rx_prbs_tap_id, 0b001, def_bus_id0; - rx_prbs_tap_id, 0b001, def_bus_id1; - rx_prbs_tap_id, 0b001, def_bus_id2; -} - -#RX3.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B07702011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, def_bus_id3; - rx_prbs_tap_id, 0b000, def_bus_id0; - rx_prbs_tap_id, 0b000, def_bus_id1; - rx_prbs_tap_id, 0b000, def_bus_id2; -} - -#RX3.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B07002011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, def_bus_id3; - rx_prbs_tap_id, 0b111, def_bus_id0; - rx_prbs_tap_id, 0b111, def_bus_id1; - rx_prbs_tap_id, 0b111, def_bus_id2; -} - -#RX3.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B07102011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, def_bus_id3; - rx_prbs_tap_id, 0b110, def_bus_id0; - rx_prbs_tap_id, 0b110, def_bus_id1; - rx_prbs_tap_id, 0b110, def_bus_id2; -} - -#RX3.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B07202011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, def_bus_id3; - rx_prbs_tap_id, 0b101, def_bus_id0; - rx_prbs_tap_id, 0b101, def_bus_id1; - rx_prbs_tap_id, 0b101, def_bus_id2; -} - -#RX3.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B07302011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, def_bus_id3; - rx_prbs_tap_id, 0b100, def_bus_id0; - rx_prbs_tap_id, 0b100, def_bus_id1; - rx_prbs_tap_id, 0b100, def_bus_id2; -} - -#RX3.RXPACKS#4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06E02011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, def_bus_id3; - rx_prbs_tap_id, 0b001, def_bus_id0; - rx_prbs_tap_id, 0b001, def_bus_id1; - rx_prbs_tap_id, 0b001, def_bus_id2; -} - -#RX3.RXPACKS#4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06F02011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, def_bus_id3; - rx_prbs_tap_id, 0b000, def_bus_id0; - rx_prbs_tap_id, 0b000, def_bus_id1; - rx_prbs_tap_id, 0b000, def_bus_id2; -} - -#RX3.RXPACKS#4.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06C02011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, def_bus_id3; - rx_prbs_tap_id, 0b011, def_bus_id0; - rx_prbs_tap_id, 0b011, def_bus_id1; - rx_prbs_tap_id, 0b011, def_bus_id2; -} - -#RX3.RXPACKS#4.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06D02011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, def_bus_id3; - rx_prbs_tap_id, 0b010, def_bus_id0; - rx_prbs_tap_id, 0b010, def_bus_id1; - rx_prbs_tap_id, 0b010, def_bus_id2; -} - -#RX3.RXPACKS#5.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06A02011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, def_bus_id3; - rx_prbs_tap_id, 0b010, def_bus_id0; - rx_prbs_tap_id, 0b010, def_bus_id1; - rx_prbs_tap_id, 0b010, def_bus_id2; -} - -#RX3.RXPACKS#5.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06B02011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, def_bus_id3; - rx_prbs_tap_id, 0b011, def_bus_id0; - rx_prbs_tap_id, 0b011, def_bus_id1; - rx_prbs_tap_id, 0b011, def_bus_id2; -} - -#RX3.RXPACKS#5.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06802011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, def_bus_id3; - rx_prbs_tap_id, 0b000, def_bus_id0; - rx_prbs_tap_id, 0b000, def_bus_id1; - rx_prbs_tap_id, 0b000, def_bus_id2; -} - -#RX3.RXPACKS#5.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06902011A3F { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, def_bus_id3; - rx_prbs_tap_id, 0b001, def_bus_id0; - rx_prbs_tap_id, 0b001, def_bus_id1; - rx_prbs_tap_id, 0b001, def_bus_id2; -} - -#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG -scom 0x800CC46002011A3F { - bits, scom_data, expr; - tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id3; - tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id0; - tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id1; - tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id2; -} - -#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_DYN_RECAL_TIMEOUTS_PP -scom 0x800EAC6002011A3F { - bits, scom_data, expr; - tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id3; - tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; - tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; - tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; -} - -#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C946002011A3F { - bits, scom_data, expr; - tx_bus_id, 0b000011, def_bus_id3; - tx_bus_id, 0b000000, def_bus_id0; - tx_bus_id, 0b000001, def_bus_id1; - tx_bus_id, 0b000010, def_bus_id2; - tx_group_id, 0b100000, def_bus_id3; - tx_group_id, 0b100000, def_bus_id0; - tx_group_id, 0b100000, def_bus_id1; - tx_group_id, 0b100000, def_bus_id2; -} - -#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID2_PG -scom 0x800C9C6002011A3F { - bits, scom_data, expr; - tx_last_group_id, 0b100000, def_bus_id3; - tx_last_group_id, 0b100000, def_bus_id0; - tx_last_group_id, 0b100000, def_bus_id1; - tx_last_group_id, 0b100000, def_bus_id2; -} - -#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID3_PG -scom 0x800CA46002011A3F { - bits, scom_data, expr; - tx_end_lane_id, 0b0010000, def_bus_id3; - tx_end_lane_id, 0b0010000, def_bus_id0; - tx_end_lane_id, 0b0010000, def_bus_id1; - tx_end_lane_id, 0b0010000, def_bus_id2; - tx_start_lane_id, 0b0000000, def_bus_id3; - tx_start_lane_id, 0b0000000, def_bus_id0; - tx_start_lane_id, 0b0000000, def_bus_id1; - tx_start_lane_id, 0b0000000, def_bus_id2; -} - -#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG -scom 0x800D1C6002011A3F { - bits, scom_data, expr; - tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id3; - tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0; - tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1; - tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2; -} - -#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG -scom 0x800D246002011A3F { - bits, scom_data, expr; - tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id3; - tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id0; - tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id1; - tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id2; -} - -#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_MODE_PG -scom 0x800C1C6002011A3F { - bits, scom_data, expr; - tx_max_bad_lanes, 0b00010, def_bus_id3; - tx_max_bad_lanes, 0b00010, def_bus_id0; - tx_max_bad_lanes, 0b00010, def_bus_id1; - tx_max_bad_lanes, 0b00010, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346002011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, def_bus_id3; - tx_prbs_tap_id, 0b000, def_bus_id0; - tx_prbs_tap_id, 0b000, def_bus_id1; - tx_prbs_tap_id, 0b000, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346102011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, def_bus_id3; - tx_prbs_tap_id, 0b001, def_bus_id0; - tx_prbs_tap_id, 0b001, def_bus_id1; - tx_prbs_tap_id, 0b001, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346202011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, def_bus_id3; - tx_prbs_tap_id, 0b010, def_bus_id0; - tx_prbs_tap_id, 0b010, def_bus_id1; - tx_prbs_tap_id, 0b010, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346302011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, def_bus_id3; - tx_prbs_tap_id, 0b011, def_bus_id0; - tx_prbs_tap_id, 0b011, def_bus_id1; - tx_prbs_tap_id, 0b011, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346402011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, def_bus_id3; - tx_prbs_tap_id, 0b100, def_bus_id0; - tx_prbs_tap_id, 0b100, def_bus_id1; - tx_prbs_tap_id, 0b100, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346502011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, def_bus_id3; - tx_prbs_tap_id, 0b101, def_bus_id0; - tx_prbs_tap_id, 0b101, def_bus_id1; - tx_prbs_tap_id, 0b101, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346602011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, def_bus_id3; - tx_prbs_tap_id, 0b110, def_bus_id0; - tx_prbs_tap_id, 0b110, def_bus_id1; - tx_prbs_tap_id, 0b110, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346702011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, def_bus_id3; - tx_prbs_tap_id, 0b111, def_bus_id0; - tx_prbs_tap_id, 0b111, def_bus_id1; - tx_prbs_tap_id, 0b111, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004347002011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, def_bus_id3; - tx_prbs_tap_id, 0b000, def_bus_id0; - tx_prbs_tap_id, 0b000, def_bus_id1; - tx_prbs_tap_id, 0b000, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346F02011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, def_bus_id3; - tx_prbs_tap_id, 0b001, def_bus_id0; - tx_prbs_tap_id, 0b001, def_bus_id1; - tx_prbs_tap_id, 0b001, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346E02011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, def_bus_id3; - tx_prbs_tap_id, 0b010, def_bus_id0; - tx_prbs_tap_id, 0b010, def_bus_id1; - tx_prbs_tap_id, 0b010, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346D02011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, def_bus_id3; - tx_prbs_tap_id, 0b011, def_bus_id0; - tx_prbs_tap_id, 0b011, def_bus_id1; - tx_prbs_tap_id, 0b011, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346C02011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, def_bus_id3; - tx_prbs_tap_id, 0b100, def_bus_id0; - tx_prbs_tap_id, 0b100, def_bus_id1; - tx_prbs_tap_id, 0b100, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346B02011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, def_bus_id3; - tx_prbs_tap_id, 0b101, def_bus_id0; - tx_prbs_tap_id, 0b101, def_bus_id1; - tx_prbs_tap_id, 0b101, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346A02011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, def_bus_id3; - tx_prbs_tap_id, 0b110, def_bus_id0; - tx_prbs_tap_id, 0b110, def_bus_id1; - tx_prbs_tap_id, 0b110, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346902011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, def_bus_id3; - tx_prbs_tap_id, 0b111, def_bus_id0; - tx_prbs_tap_id, 0b111, def_bus_id1; - tx_prbs_tap_id, 0b111, def_bus_id2; -} - -#TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346802011A3F { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, def_bus_id3; - tx_prbs_tap_id, 0b000, def_bus_id0; - tx_prbs_tap_id, 0b000, def_bus_id1; - tx_prbs_tap_id, 0b000, def_bus_id2; -} - - -###################################### -## END OF FILE -####################################### diff --git a/src/usr/hwpf/hwp/initfiles/p8.fbc.define b/src/usr/hwpf/hwp/initfiles/p8.fbc.define deleted file mode 100644 index 3ad08a7ae..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.fbc.define +++ /dev/null @@ -1,76 +0,0 @@ -#-- $Id: p8.fbc.define,v 1.7 2013/05/07 23:15:00 jmcgill Exp $ -#------------------------------------------------------------------------------- -#-- -#-- (C) Copyright International Business Machines Corp. 2011 -#-- All Rights Reserved -- Property of IBM -#-- *** *** -#-- -#-- TITLE : p8.fbc.define -#-- DESCRIPTION : Register field/bit definitions for fabric initfile -#-- -#-- OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -#-------------------------------------------------------------------------------- - -#-- PB Mode Register (PB_MODE / 0x02010C[048]A) -define chip_is_system = 4; -define avp_mode = 6; -define sw_ab_wait = 12:15; -define sp_hw_mark = 16:21; -define gp_hw_mark = 22:27; -define lcl_hw_mark = 28:33; -define e2e_hw_mark = 34:40; -define fp_hw_mark = 41:46; -define switch_option_ab = 59; -define cpu_ratio_override = 60:62; - -#-- PB Trace Array Select Configuration Register (PB_EVENT_TRACE / 0x02010C4F) -define sn0_select = 0:1; -define sn1_select = 2:3; -define cr0_select = 4:5; -define cr1_select = 6:7; -define rt0_select = 8:9; -define rt1_select = 10:12; -define dat_select = 13:18; - -#-- PB Node Master Power Management Counter Register (PB_NMPM_COUNTER / 0x2010C50) -define apm_en = 0; -define pmucnt_en = 3; -define pmucnt_sel = 4:5; - -#-- MCD Even/Odd Recovery Control Registers (MCD_REC_[EVEN_ODD] / 0x0201341[01]) -define mcd_recov_continuous = 2; -define mcd_recov_pace_delay = 8:19; -define mcd_recov_recov_all = 20; -define mcd_recov_granule_count = 46:63; - -#-- MCD Recovery Pre Epsilon Configuration Register (MCD_PRE / 0x0201340B) -define mcd_retry_count = 40:43; - -#-- MCD Debug Configuration Register (MCD_DBG / 0x02013416) -define mcd_debug_enable = 3; -define mcd_debug_select = 4:7; - -#-- PB X Link Mode Register (PB_X_MODE / 0x04010C0A) -define x_avp_mode = 0; -define x_4b_mode = 1; -define x_tod_wait_limit = 12:15; - -#-- PB A Link Mode Register (PB_IOA_MODE / 0x0801080A) -define a_avp_mode = 0; - -#-- PB A Link Framer Configuration Register (PB_IOA_FMR_CFG / 0x08010813) -define a_tod_wait_limit = 0:3; -define a_prsp_wait_limit = 4:7; -define a_cc_wait_limit = 8:11; -define a0_dc_wait_limit = 12:15; -define a1_dc_wait_limit = 16:19; -define a2_dc_wait_limit = 20:23; -define a_ow_pack = 24; -define a_ow_pack_priority = 25; - -#-- PB IOF Link Mode Register (PB_IOF_MODE / 0x0901080A) -define f_avp_mode = 0; - -#-- PB F Link Framer Configuration Register (PB_IOF_FMR_CFG / 0x09010813) -define f_ow_pack = 20; -define f_ow_pack_priority = 21; diff --git a/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile deleted file mode 100644 index 1d57ad2ca..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.fbc.scom.initfile +++ /dev/null @@ -1,178 +0,0 @@ -#-- $Id: p8.fbc.scom.initfile,v 1.18 2014/11/18 17:24:13 jmcgill Exp $ -#------------------------------------------------------------------------------- -#-- -#-- (C) Copyright International Business Machines Corp. 2011 -#-- All Rights Reserved -- Property of IBM -#-- *** *** -#-- -#-- TITLE : p8.fbc.scom.initfile -#-- DESCRIPTION : Perform fabric configuration -#-- -#-- OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -#-- -#-------------------------------------------------------------------------------- - -SyntaxVersion = 1 - -#-------------------------------------------------------------------------------- -#-- Includes -#-------------------------------------------------------------------------------- -include p8.fbc.define - -#-------------------------------------------------------------------------------- -#-- Defines -#-------------------------------------------------------------------------------- - -define def_x_is_4b = (SYS.ATTR_PROC_X_BUS_WIDTH == ENUM_ATTR_PROC_X_BUS_WIDTH_W4BYTE); -define xbus_enabled = (ATTR_PROC_X_ENABLE == ENUM_ATTR_PROC_X_ENABLE_ENABLE); -define abus_enabled = (ATTR_PROC_A_ENABLE == ENUM_ATTR_PROC_A_ENABLE_ENABLE); -define pcie_enabled = (ATTR_PROC_PCIE_ENABLE == ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE); -define mcd_hang_poll_bug = (ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG != 0); -define nv_present = (ATTR_CHIP_EC_FEATURE_NV_PRESENT != 0); - -#-------------------------------------------------------------------------------- -#-- SCOM initializations -#-------------------------------------------------------------------------------- -#-- PB Mode Register (PB_MODE / 0x02010C[048]A) -scom 0x02010C(0,4,8)A { - bits, scom_data; - chip_is_system, 0b1; #-- single chip - avp_mode, 0b0; #-- AVP mode - sw_ab_wait, 0x8; #-- 8 (HW218406/HW214831) - sp_hw_mark, 0x20; #-- 32 - gp_hw_mark, 0x20; #-- 32 - lcl_hw_mark, 0x20; #-- 32 - e2e_hw_mark, 0x3B; #-- 59 - fp_hw_mark, 0x20; #-- 32 - switch_option_ab, 0b0; #-- no switch CD on switch AB - cpu_ratio_override, 0b000; #-- rcmd queue depth = 16 -} - -#-- PB Trace Array Select Configuration Register (PB_EVENT_TRACE / 0x02010C4F) -scom 0x02010C4F { - bits, scom_data; - sn0_select, 0b10; #-- rcmd 0 - sn1_select, 0b10; #-- rcmd 1 - cr0_select, 0b10; #-- cresp 0 / presp 0 - cr1_select, 0b10; #-- cresp 1 / presp 1 - rt0_select, 0b10; #-- rtag NW - rt1_select, 0b001; #-- MCD - dat_select, 0b000000; #-- none -} - -#-- PB Node Master Power Management Counter Register (PB_NMPM_COUNTER / 0x2010C50) -scom 0x02010C50 { - bits, scom_data; - apm_en, 0b0; #-- set shared counters to PMU mode - pmucnt_en, 0b1; #-- set shared counters to PMU mode - pmucnt_sel, 0b11; #-- PMU counter select = rcmd 0 OR rcmd 1 -} - -#-- FBC EXTFIR -#-- NOTE: init to all bits masked, proc_fab_iovalid will unmask bits for active links - -#-- PB EXTFIR Mask Register (EXTFIR_MASK_REG / 0x02010C71) -scom 0x02010C71 { - bits, scom_data; - 0:63, 0xFF00000000000000; -} - -#-- PB EXTFIR Action0 Register (EXTFIR_ACTION0_REG / 0x02010C74) -scom 0x02010C74 { - bits, scom_data; - 0:63, 0x0000000000000000; -} - -#-- PB EXTFIR Action1 Register (EXTFIR_ACTION1_REG / 0x02010C75) -scom 0x02010C75 { - bits, scom_data; - 0:63, 0x0000000000000000; -} - -#-- MCD FIR Mask Register (MCDCTL.FIR_MASK_REG / 0x02013403) -#-- NOTE: init to all bits masked, proc_setup_bars will unmask if MCD is enabled on this chip -scom 0x02013403 { - bits, scom_data; - 0:63, 0xFFC0000000000000; -} - -#-- MCD FIR Action0 Register (MCDCTL.FIR_ACTION0_REG / 0x02013406) -scom 0x02013406 { - bits, scom_data; - 0:63, 0x0000000000000000; -} - -#-- MCD FIR Action1 Register (MCDCTL.FIR_ACTION1_REG / 0x02013407) -scom 0x02013407 { - bits, scom_data, expr; - 0:3, 0xC, any; - 4, 0b0, (!mcd_hang_poll_bug); - 4, 0b0, (mcd_hang_poll_bug); - 5:7, 0b000, any; - 8:63, 0x00000000000000, any; -} - - -#-- MCD Even/Odd Recovery Control Registers (MCD_REC_[EVEN_ODD] / 0x0201341[01]) -#-- NOTE: set base configuration, proc_setup_bars will enable recovery for -#-- valid configuration registers based on memory configuration of this chip -scom 0x0201341(0,1) { - bits, scom_data; - mcd_recov_continuous, 0b1; #-- enable continuous recovery - mcd_recov_pace_delay, 0x040; #-- 1024 cycle wait between probes - mcd_recov_recov_all, 0b0; #-- disable recover all function - mcd_recov_granule_count, 0x3FFFF; #-- set granule count -} - -#-- MCD Recovery Pre Epsilon Configuration Register (MCD_PRE / 0x0201340B) -scom 0x0201340B { - bits, scom_data; - mcd_retry_count, 0b1111; #-- retry count of 15 -} - -#-- MCD Debug Configuration Register (MCD_DBG / 0x02013416) -scom 0x02013416 { - bits, scom_data; - mcd_debug_enable, 0b1; #-- enable debug clocks - mcd_debug_select, 0b1000; #-- default debug bus select -} - -#-- PB X Link Mode Register (PB_X_MODE / 0x04010C0A) -scom 0x04010C0A { - bits, scom_data, expr; - x_avp_mode, 0b0, (xbus_enabled); #-- X AVP mode - x_4b_mode, 0b1, (xbus_enabled) && (def_x_is_4b); #-- X bus 4/8B switch - x_tod_wait_limit, 0b0100, (xbus_enabled); #-- X bus TOD wait limit -} - -#-- PB A Link Mode Register (PB_IOA_MODE / 0x0801080A) -scom 0x0801080A { - bits, scom_data, expr; - a_avp_mode, 0b0, (abus_enabled) && (!nv_present); #-- A AVP mode -} - -#-- PB A Link Framer Configuration Register (PB_IOA_FMR_CFG / 0x08010813) -scom 0x08010813 { - bits, scom_data, expr; - a_tod_wait_limit, 0b0001, (abus_enabled) && (!nv_present); #-- A bus TOD wait limit - a_prsp_wait_limit, 0b1000, (abus_enabled) && (!nv_present); #-- A bus presp wait limit - a_cc_wait_limit, 0b1100, (abus_enabled) && (!nv_present); #-- A bus cresp credit wait limit - a0_dc_wait_limit, 0b1100, (abus_enabled) && (!nv_present); #-- A0 bus data credit wait limit - a1_dc_wait_limit, 0b1100, (abus_enabled) && (!nv_present); #-- A1 bus data credit wait limit - a2_dc_wait_limit, 0b1100, (abus_enabled) && (!nv_present); #-- A2 bus data credit wait limit - a_ow_pack, 0b0, (abus_enabled) && (!nv_present); #-- OW pack disabled - a_ow_pack_priority, 0b0, (abus_enabled) && (!nv_present); #-- low priority -} - -#-- PB F Link Mode Register (PB_IOF_MODE / 0x0901080A) -scom 0x0901080A { - bits, scom_data, expr; - f_avp_mode, 0b0, (pcie_enabled) && (!nv_present); #-- F AVP mode -} - -#-- PB F Link Framer Configuration Register (PB_IOF_FMR_CFG / 0x09010813) -scom 0x09010813 { - bits, scom_data, expr; - f_ow_pack, 0b0, (pcie_enabled) && (!nv_present); #-- OW pack disabled - f_ow_pack_priority, 0b0, (pcie_enabled) && (!nv_present); #-- low priority -} diff --git a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile deleted file mode 100644 index fded895b1..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile +++ /dev/null @@ -1,283 +0,0 @@ -#-- $Id: p8.mcs.scom.initfile,v 1.22 2015/09/23 21:23:38 baysah Exp $ -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -#-- | | | -#-- 1.22|baysah |09/18/15|- SW322180 : MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD from 0xF to 0x7 for all 4 DMI systems with SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD. -#-- | | | -#-- 1.21|baysah |11/17/14|- FW630892 : Disable MCS Read Data OctoWord Gathering to prevent dcbz starvation -#-- | | |- Don't attempt to enable this workaround for MurDD1.x, because it doesn't exist. -#-- | | | -#-- 1.20|baysah |11/14/14|- FW630892 : Disable MCS Read Data OctoWord Gathering to prevent dcbz starvation -#-- | | | -#-- 1.19|baysah |10/22/14|- SW281364 : Remove ATTR_PM_SLEEP_ENABLE condition so MCS workaround for L4-CAPI Deadlock is for all systems types -#-- | | |- per Kevin Reick -#-- | | | -#-- 1.18|baysah |10/20/14|- SW281364 : Use ATTR_PM_SLEEP_ENABLE to enable MCS workaround for L4-CAPI Deadlock for Saphire systems -#-- | | |- The workaround disables speculation for dma_pr_w, pte_updt, ci_pr_w and reserves 1 CL machine for reads. -#-- | | | -#-- 1.17|baysah |09/12/14|- SW277283 : MCS FCI Register is not in Murano DD1.x ... Qualify scom 201181c -#-- | | | -#-- 1.16|baysah |09/03/14|- SW275492 : MCS Command List Timer Needs to be Extended -#-- | | | -#-- 1.15|baysah |06/21/14|- SW274463 : Shut down mirror on first mirrored memory UE -#-- | | | -#-- 1.14|baysah |06/12/14|- SW265488 : enable channel checkstop for MCIFIR[40]: channel timeout error -#-- | | | -#-- 1.13|baysah |05/20/14|- Added Best MCS Spec filter setting to MODE2 reg (2011809 16 20 9007F) for power and perf improvement -#-- | | | -#-- 1.12|baysah |01/08/14|- Moved ECC bypass qualifier from MCMODE1(63) TO MCMODE1(62), bit 63 is perfmon. -#-- | | | -#-- 1.10|jmcgill |05/07/13|- Qualify ECC bypass disable by risk level -#-- | | | -#-- 1.9|baysah |05/05/13|- Disabled MCMODE1Q_DISABLE_FASTPATH_CRC_ECC_BYPASS and MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL. -#-- | | | -#-- 1.7|baysah |04/26/13|- Disabled MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP per firmware request for MPIPL. -#-- | | | -#-- 1.6|baysah |04/25/13|- Fix problem with incorrectly setting mcmode0 bit 1 which is marked as reserved, but its actually used to -#-- | | |- reset MCS channel fail. -#-- | | | -#-- 1.4|baysah |04/23/13|- Disable MCS bypass for dd1 less than 2.0 for defect HW247907 -#-- | | | -#-- 1.3|baysah |04/04/13|- Set MCI Replay timeout value to 2ms. -#-- | | |- Disable MCS arbiter blocking after checkstop. -#-- | | | -#-- --------|--------|--------|-------------------------------------------------- -#-- 1.0|baysah |08/12/12|Created MCS init file -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- - -#--Master list of variables that can be used in this file is at: -#--<Attribute Definition Location> - -SyntaxVersion = 1 - -#-------------------------------------------------------------------------------- -#-- Defines -#-------------------------------------------------------------------------------- - -# disable ECC bypass if instructed to by EC feature attribute AND -# running risk level 0 -define ecc_bypass_disable = ((TGT1.ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE != 0x0) && (SYS.ATTR_RISK_LEVEL == ENUM_ATTR_RISK_LEVEL_RL0)); - -# Set MCS PrefetchA retry threshold -define def_mcs_prefA_rtry_thrd = ((SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x00) || (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD >= 0x0F)); - - -#--****************************************************************************** -#-- MCS Mode0 Register -#--****************************************************************************** - scom 0x0000000002011807 { - bits , scom_data , expr ; - 0 , 0b1 , any ; # MCMODE0Q_ENABLE_CMD_BYP_STUTTER - 1 , 0b0 , any ; # MCMODE0Q_RESERVED Reserved - 2 , 0b1 , any ; # MCMODE0Q_ENABLE_NS_RD_AO_SFU_FOR_DCBZ - 3 , 0b1 , any ; # MCMODE0Q_ENABLE_CENTAUR_LOCAL_CHECKSTOP_COMMAND -# 4:7 , 0xF , any ; # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD (actual value is 2x register value => 15 x 2 = 30) - 4:7 , 0xF , (def_mcs_prefA_rtry_thrd); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0x1 , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x01); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0x2 , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x02); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0x3 , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x03); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0x4 , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x04); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0x5 , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x05); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0x6 , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x06); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0x7 , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x07); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0x8 , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x08); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0x9 , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x09); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0xA , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x0A); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0xB , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x0B); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0xC , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x0C); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0xD , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x0D); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - 4:7 , 0xE , (SYS.ATTR_MRW_MCS_PREFETCH_RETRY_THRESHOLD == 0x0E); # MCMODE0Q_L3_PREFETCH_RETRY_THRESHOLD - # 8:11 , 0x0 , any ; # MCMODE0Q_Number_of_CL_Entries_Reserved_for_Read - # 8:11 , 0x1 , (SYS.ATTR_PM_SLEEP_ENABLE == 1) ; # CAPI Deadlock workaround - 8:11 , 0x1 , any ; # CAPI Deadlock workaround - 12:15, 0x1 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_MIRRORED_OPS - 16:19, 0x0 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_WRITES - 20:23, 0x1 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_CP_WRITES - 24:27, 0x1 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_CP_IG - 28:31, 0x0 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HTM_OPS - 32:35, 0x0 , any ; # MCMODE0Q_NUMBER_OF_CL_ENTRIES_RESERVED_FOR_HA_ASSIST - 36 , 0b1 , any ; # MCMODE0Q_MCFGRP_19_IS_HO_BIT - 37 , 0b1 , any ; # MCMODE0Q_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL - 38 , 0b0 , any ; # MCMODE0Q_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP - 39:43, 0b00000 , any ; # MCMODE0Q_RESERVED_39_43 Reserved - 44:52, 0b001100010 , any ; # MCMODE0Q_ADDRESS_COLLISION_MODES - 53 , 0b0 , any ; # MCMODE0Q_INCLUDE_CP_IG_IN_CP_WRITE_FULLNESS_GROUP - 54 , 0b1 , any ; # MCMODE0Q_ENABLE_DMAWR_CMD_BIT - 55 , 0b0 , any ; # MCMODE0Q_ENABLE_READ_LFSR_DATA - 56 , 0b0 , any ; # MCMODE0Q_FORCE_CHANNEL_FAIL - 57 , 0b0 , any ; # MCMODE0Q_DISABLE_READ_CRC_ECC_BYPASS_TAKEN - 58 , 0b0 , any ; # MCMODE0Q_DISABLE_CL_AO_QUEUES - 59:60, 0b00 , any ; # MCMODE0Q_ADDRESS_SELECT_LFSR_VALUE (4k) - 61 , 0b0 , any ; # MCMODE0Q_ENABLE_CENTAUR_SYNC - 62 , 0b0 , any ; # MCMODE0Q_WRITE_DATA_BUFFER_ECC_CHECK_DISABLE - 63 , 0b0 , any ; # MCMODE0Q_WRITE_DATA_BUFFER_ECC_CORRECT_DISABLE - - } - - -#--****************************************************************************** -#-- MCS Mode1 Register -#--****************************************************************************** - scom 0x0000000002011808 { - bits , scom_data , expr ; - 0 , 0b0 , any ; # MCMODE1Q_DISABLE_ADDRESS_SELECT_LFSR_MODE - 1 , 0b0 , any ; # MCMODE1Q_NODAL_SCOPE_MCD_VALID - 2:6 , 0b00000 , any ; # MCMODE1Q_DISABLE_HIGH_PRIORITY - 7:9 , 0b111 , (ecc_bypass_disable) ; # MCMODE1Q_DISABLE_CRC_ECC_BYPASS - 10:15, 0b000000 , any ; # MCMODE1Q_DISABLE_READ_ALLOCATION_TO_CACHE - 16 , 0b0 , any ; # MCMODE1Q_DISABLE_READ_ALLOCATION_TO_CACHE_FOR_FASTPATH_OP - 17 , 0b0 , any ; # MCMODE1Q_ENABLE_CRC_ECC_BYPASS_NODAL_SCOPE_ONLY - 18:26, 0b000000000 , any ; # MCMODE1Q_DISABLE_SPEC_OPS_BY_SOURCE_AND_OR_SCOPE - 27:30, 0b0000 , any ; # MCMODE1Q_DISABLE_PREFETCH - 31 , 0b0 , any ; # MCMODE1Q_DISABLE_ALL_SPEC_OPS -# 32:48, 0b00000000000000000 , any ; # MCMODE1Q_DISABLE_SPEC_OPS - 32:40, 0b000000000 , any ; # MCMODE1Q_DISABLE_SPEC_OPS -# 41 , 0b1 , (SYS.ATTR_PM_SLEEP_ENABLE == 1) ; #CAPI Deadlock workaround - 41 , 0b1 , any ; #CAPI Deadlock workaround - 42 , 0b0 , any ; # MCMODE1Q_DISABLE_SPEC_OPS -# 43 , 0b1 , (SYS.ATTR_PM_SLEEP_ENABLE == 1) ; #CAPI Deadlock workaround - 43 , 0b1 , any ; #CAPI Deadlock workaround - 44 , 0b0 , any ; # MCMODE1Q_DISABLE_SPEC_OPS - 45 , 0b0 , any ; # MCMODE1Q_DISABLE_SPEC_OPS -# 46 , 0b1 , (SYS.ATTR_PM_SLEEP_ENABLE == 1) ; #CAPI Deadlock workaround - 46 , 0b1 , any ; #CAPI Deadlock workaround - 47:48, 0b00 , any ; # MCMODE1Q_DISABLE_SPEC_OPS - 49 , 0b0 , any ; # MCMODE1Q_DISABLE_OP_SOURCE_AND_SCOPE - 50:51, 0b00 , any ; # MCMODE1Q_DISABLE_CACHE_INHIBITED - 52 , 0b0 , any ; # MCMODE1Q_DISABLE_ALL_MCS_COMMAND_BYPASS - 53:59, 0b0000000 , any ; # MCMODE1Q_DISABLE_MCS_COMMAND_BYPASS - 60 , 0b0 , any ; # MCMODE1Q_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_GROUP_PUMP_LOCAL_READ - 61 , 0b0 , any ; # MCMODE1Q_ENABLE_DISABLE_SPEC_READ_FOR_NONDMA_SYSTEM_PUMP_LOCAL_READ - 62 , 0b1 , (ecc_bypass_disable) ; # MCMODE1Q_DISABLE_FASTPATH_MCS_COMMAND_BYPASS - 63 , 0b1 , any ; # MCMODE1Q_DISABLE_FASTPATH_CRC_ECC_BYPASS - - } - - -#--****************************************************************************** -#-- MCS Mode2 Register -#--****************************************************************************** - scom 0x0000000002011809 { - bits , scom_data ; - 0 , 0b0 ; # MCMODE2Q_FORCE_SFSTAT_GLOBAL - 1:13 , 0b0000000000000 ; # MCMODE2Q_DISABLE_WRITE_MDI_TO_ZERO - 14 , 0b0 ; # MCMODE2Q_DISABLE_SFU_OPERATIONS - 15 , 0b0 ; # MCMODE2Q_DISABLE_FASTPATH_QOS - # 16 , 0b0 ; # MCMODE2Q_ENABLE_2K_SPEC_READ_DISABLE_COUNTERS - 16 , 0b1 ; # MCMODE2Q_ENABLE_2K_SPEC_READ_DISABLE_COUNTERS - 17 , 0b0 ; # MCMODE2Q_ENABLE_ZERO_SPEC_HASH_ADDR_48_TO_50 - 18 , 0b0 ; # MCMODE2Q_DISABLE_SPEC_DISABLE_HINT_BIT - # 19 , 0b0 ; # MCMODE2Q_ENABLE_RESET_2K_COUNT_IF_HINT_BIT_SET - 19 , 0b1 ; # MCMODE2Q_ENABLE_RESET_2K_COUNT_IF_HINT_BIT_SET - 20:23, 0x0 ; # MCMODE2Q_D2K_SPEC_FILTER_COUNTER_LFSR_INC_SELECT - 24:27, 0x0 ; # MCMODE2Q_D2K_SPEC_FILTER_COUNTER_LFSR_DEC__SELECT - 28 , 0b0 ; # MCMODE2Q_SPEC_READ_FILTER_NO_HASH_MODE - 29 , 0b1 ; # MCMODE2Q_ENABLE_CHANNEL_HANG - 30:35, 0b111111 ; # MCMODE2Q_READ_SPECULATION_DISABLE_THRESHOLD - 36:38, 0b010 ; # MCMODE2Q_CHANNEL_ARB_WRITE_HP_THRESHOLD - 39 , 0b0 ; # MCMODE2Q_DISABLE_BAD_CRESP_TO_CENTAUR - 40 , 0b1 ; # MCMODE2Q_ENABLE_CRC_BYPASS_ALWAYS - 41:43, 0b011 ; # MCMODE2Q_CHANNEL_HANG_VALUE - 44 , 0b1 ; # MCMODE2Q_ENABLE_RD_HANG - 45 , 0b1 ; # MCMODE2Q_ENABLE_WR_HANG - 46 , 0b1 ; # MCMODE2Q_ENABLE_MIRROR_RD_HANG - 47 , 0b1 ; # MCMODE2Q_ENABLE_MIRROR_WR_HANG - 48 , 0b1 ; # MCMODE2Q_ENABLE_AO_HANG - 49 , 0b1 ; # MCMODE2Q_ENABLE_INBAND_HANG - 50:52, 0b100 ; # MCMODE2Q_NONMIRROR_HANG_VALUE - 53:55, 0b111 ; # MCMODE2Q_MIRROR_HANG_VALUE - 56 , 0b1 ; # MCMODE2Q_ENABLE_EMER_THROTTLE - 57 , 0b0 ; # MCMODE2Q_DRIVE_SHARED_PRESP_WITH_LOST_CLAIM - 58 , 0b0 ; # MCMODE2Q_DISABLE_SHARED_PRESP_ABORT - 59 , 0b0 ; # MCMODE2Q_DISABLE_RTY_LOST_CLAIM_PRESP - 60 , 0b0 ; # MCMODE2Q_DRIVE_BC4_WRITE_COMMAND - 61 , 0b1 ; # MCMODE2Q_ENABLE_CENTAUR_CHECKSTOP_COMMAND - 62 , 0b1 ; # MCMODE2Q_ENABLE_CENTAUR_TRACESTOP_COMMAND - 63 , 0b0 ; # MCMODE2Q_ENABLE_EVENT_BUS_B - - } - - -#--****************************************************************************** -#-- MCS Mode3 Register -#--****************************************************************************** - scom 0x000000000201180A { - bits , scom_data , expr ; - 24 , 0b1 , any ; # MCMODE3Q_ENABLE_LOCAL_TIMEOUT_TIMEBASE - 25:30, 0b000001 , any ; # MCMODE3Q_LOCAL_TIMEOUT_TIMEBASE_THRESHOLD - 48:52, 0b11111 , (ATTR_CHIP_EC_FEATURE_MCS_MURDD1_FIR_CONTROL == 0) ; # MCMODE3Q_READ_RAMP_PERF_TRESHOLD -} - - -#--****************************************************************************** -#-- MCS Mode4 Register -#--****************************************************************************** - scom 0x000000000201181A { - bits , scom_data ; - 1:3, 0b111 ; # DISABLE INTERFACE AND ARBITER BLOCKING DURING INTERNAL MCS CHECKSTOP - 17:18, 0b00 ; # MCMODE4Q_SELECT_RPTHANG_DECODE - 19 , 0b1 ; # MCMODE4Q_LOCAL_TIMEBASE_SELECT - 21 , 0b1 ; # MCMODE4Q_DISABLE_POWERBUS_READ_AND_WRITE_RAMPS_DURING_CHECKSTOP -} - -#--****************************************************************************** -#-- MC Busy Control Register -#--****************************************************************************** - scom 0x0000000002011818 { - bits , scom_data ; - 0 , 0b0 ; # MCBUSYQ_ENABLE_BUSY_COUNTERS - 1:3 , 0b100 ; # MCBUSYQ_BUSY_COUNTER_WINDOW_SELECT (256 Cycles) - 4:13 , 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD0 - 14:23, 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD1 - 24:33, 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD2 - 34:43, 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD3 -} - - -#--****************************************************************************** -#-- MCS Hardware Force Mirror Read (MCHWFM) -#--****************************************************************************** - scom 0x000000000201181C { - bits , scom_data , expr ; - 0 , 0b1 , (ATTR_CHIP_EC_FEATURE_MCS_MURDD1_FIR_CONTROL == 0) ; # ENABLE FORCED CHANNEL INACTIVE FOR MIRROR UE/SUE FUNCTION - 4 , 0b0 , (ATTR_CHIP_EC_FEATURE_MCS_MURDD1_FIR_CONTROL == 0) ; # DON'T SHUT DOWN MIRROR FOR INTERNAL CENTAUR UES, OR PASSED IN SUES - 5 , 0b1 , (ATTR_CHIP_EC_FEATURE_MCS_MURDD1_FIR_CONTROL == 0) ; # SHUT DOWN MIRROR FOR MIRRORED MEMORY UE ONLY -} - -#--****************************************************************************** -#-- MCI Configuration Register -#--****************************************************************************** - scom 0x000000000201184A { - bits , scom_data ; - 0 , 0b0 ; # MCICFGQ_FORCE_CHANNEL_FAIL - 1 , 0b0 ; # MCICFGQ_REPLAY_CRC_DISABLE - 2 , 0b0 ; # MCICFGQ_REPLAY_NOACK_DISABLE - 3 , 0b0 ; # MCICFGQ_REPLAY_OUTOFORDER_DISABLE - 4 , 0b0 ; # MCICFGQ_FORCE_LFSR_REPLAY - 5 , 0b0 ; # MCICFGQ_CRC_CHECK_DISABLE - 6 , 0b0 ; # MCICFGQ_ECC_CHECK_DISABLE - 7 , 0b0 ; # MCICFGQ_START_FRAME_LOCK - 8 , 0b0 ; # MCICFGQ_START_FRTL - 9 , 0b0 ; # MCICFGQ_AUTO_FRTL_DISABLE - 10:16, 0b0000000 ; # MCICFGQ_MANUAL_FRTL_VALUE - 17 , 0x0 ; # MCICFGQ_MANUAL_FRTL_DONE - 18 , 0b0 ; # MCICFGQ_ECC_CORRECT_DISABLE - 19 , 0b0 ; # MCICFGQ_SPARE1 - 20 , 0b0 ; # MCICFGQ_LANE_VOTING_BYPASS - 21:25, 0b00000 ; # MCICFGQ_BAD_LANE_VALUE - 26 , 0b0 ; # MCICFGQ_BAD_LANE_VOTING_DISABLE - 27:32, 0b001001 ; # MCICFGQ_NO_FORWARD_PROGRESS_TIMEOUT_VALUE (0x09 = 9 => 1ms) - 33:34, 0b00 ; # MCICFGQ_PERFORMANCE_DEGRADATION_PERCENT_SELECT - 35:36, 0b00 ; # MCICFGQ_CHANNEL_INITIALIZATION_STATE_MACHINE_TIMEOUT_VALUE - 37 , 0b0 ; # MCICFGQ_RESET_KEEPER - 38:41, 0b0001 ; # MCICFGQ_REPLAY_DELAY_VALUE (set to 1 for pSeries, which is default value) - 42:43, 0b00 ; # MCICFGQ_RESERVED - - } - - diff --git a/src/usr/hwpf/hwp/initfiles/p8.npu.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.npu.scom.initfile deleted file mode 100644 index c297e16c3..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.npu.scom.initfile +++ /dev/null @@ -1,349 +0,0 @@ -#-- $Id: p8.npu.scom.initfile,v 1.6 2015/03/16 14:33:36 lonny Exp $ -#------------------------------------------------------------------------------- -#-- -#-- (C) Copyright International Business Machines Corp. 2011 -#-- All Rights Reserved -- Property of IBM -#-- *** *** -#-- -#-- TITLE : p8.npu.scom.initfile -#-- DESCRIPTION : Perform NPU configuration -#-- -#-- OWNER NAME : Lonny Lambrecht Email: lonny@us.ibm.com -#-- -#-------------------------------------------------------------------------------- - -SyntaxVersion = 1 - -#--****************************************************************************** -# -- ESNPUFIR -#--****************************************************************************** -# spy name ES.NPU.NP_AT.REG.NPU_AT_ERR_HOLD -# scom 0x0000000008013DA8 { -# bits, scom_data ; -# 0:63, 0x0000000000000001 ; -# } -# -# # spy name ES.NPU.NP_AT.REG.FIR_REG -# scom 0x0000000008013D81 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } - -# start up procedure for the dl2tl parity error -#mask error bit 27 -# spy name ES.NPU.NP_AT.REG.FIR_MASK_REG -scom 0x0000000008013D83 { - bits, scom_data ; - 0:63, 0xE0002C12000F5F3F ; - } - -# set the clock speed in the gp0 registers -# spy name Perf register to set IOValids for nvlink (bits 54:57) and nvlink ref clock (52) 2:1 nvlink speed (18:19) = 0b01. -scom 0x0000000008000004 { - bits, scom_data ; - 0:63, 0xFFFFDFFFFFFFFFFF ; - } - -# # spy name Perf register to set IOValids for nvlink (bits 54:57) and nvlink ref clock (52) 2:1 nvlink speed (18:19) = 0b01. -# scom 0x0000000008000005 { -# bits, scom_data ; -# 0:63, 0x0000100000000000 ; -# } -# -# # turn on the nvlink refclocks -# # spy name Perf register to set IOValids for nvlink (bits 54:57) and nvlink ref clock (52) 2:1 nvlink speed (18:19) = 0b01. -# scom 0x0000000008000005 { -# bits, scom_data ; -# 0:63, 0x0000000000000800 ; -# } - -# turn on the iovalids -# spy name Perf register to set IOValids for nvlink (bits 54:57) and nvlink ref clock (52) 2:1 nvlink speed (18:19) = 0b01. -scom 0x0000000008000005 { - bits, scom_data ; - 0:63, 0x0000100000000BC0 ; - } - -# clear the first error and c_err_rpt hold registers -# # spy name ES.NPU.SL_WRAP0.NTL_WRAP0.NTL_ER_HOLD -scom 0x0000000008013C29 { - bits, scom_data ; - 0:63, 0x0000000000000000 ; - } - -# spy name ES.NPU.SL_WRAP0.NTL_WRAP0.NTL_FST_ERR_REG -scom 0x0000000008013C2A { - bits, scom_data ; - 0:63, 0x0000000000000000 ; - } - -# spy name ES.NPU.SL_WRAP0.NTL_WRAP1.NTL_ER_HOLD -scom 0x0000000008013C69 { - bits, scom_data ; - 0:63, 0x0000000000000000 ; - } - -# spy name ES.NPU.SL_WRAP0.NTL_WRAP1.NTL_FST_ERR_REG -scom 0x0000000008013C6A { - bits, scom_data ; - 0:63, 0x0000000000000000 ; - } - -# spy name ES.NPU.SL_WRAP2.NTL_WRAP0.NTL_ER_HOLD -scom 0x0000000008013D29 { - bits, scom_data ; - 0:63, 0x0000000000000000 ; - } - -# spy name ES.NPU.SL_WRAP2.NTL_WRAP0.NTL_FST_ERR_REG -scom 0x0000000008013D2A { - bits, scom_data ; - 0:63, 0x0000000000000000 ; - } - -# spy name ES.NPU.SL_WRAP2.NTL_WRAP1.NTL_ER_HOLD -scom 0x0000000008013D69 { - bits, scom_data ; - 0:63, 0x0000000000000000 ; - } - -# spy name ES.NPU.SL_WRAP2.NTL_WRAP1.NTL_FST_ERR_REG -scom 0x0000000008013D6A { - bits, scom_data ; - 0:63, 0x0000000000000000 ; - } - - -# unmask error bit 27 -# # spy name ES.NPU.NP_AT.REG.FIR_MASK_REG -# scom 0x0000000008013D83 { -# bits, scom_data ; -# 0:63, 0xE0002C02000F5F3F ; -# } - -# spy name ES.NPU.NP_AT.REG.FIR_ACTION0_REG -scom 0x0000000008013D86 { - bits, scom_data ; - 0:63, 0x1CBFC1FCB7F0A300 ; - } - -# spy name ES.NPU.NP_AT.REG.FIR_ACTION1_REG -scom 0x0000000008013D87 { - bits, scom_data ; - 0:63, 0xFFFFFFFFFFFFFFFF ; - } - -# # spy name ES.NPU.NP_AT.REG.FIR_WOF_REG -# scom 0x0000000008013D88 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } - - -# spy name ES.NPU.NP_AT.REG.NPU_AT_CNFG0 -scom 0x0000000008013DAB { - bits, scom_data ; - 0:63, 0x0211000043500000 ; - } - -# If only 1 GPU will need to configure as below. -# scom 0x0000000008013DAB { -# bits, scom_data ; -# 0:63, 0x0210000043510000 ; -# } - - -# spy name ES.NPU.NP_AT.REG.NPU_AT_LR_ER (Lem enable) -scom 0x0000000008013D9C { - bits, scom_data ; - 0:63, 0xFFFFF00000000000 ; - } - -# spy name ES.NPU.NP_AT.REG.NPU_AT_SI_ER (LSI enable) -scom 0x0000000008013D9D { - bits, scom_data ; - 0:63, 0xE000240200000000 ; - } - -# spy name ES.NPU.NP_AT.REG.NPU_AT_FR_ER (freeze enable) -scom 0x0000000008013D9E { - bits, scom_data ; - 0:63, 0xE00024020C000000 ; - } - -# spy name ES.NPU.NP_AT.REG.NPU_AT_FE_ER (fence enable) -scom 0x0000000008013D9F { - bits, scom_data ; - 0:63, 0x1CBFC1FCB7F0A000 ; - } - -# spy name ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NX_MISC_CONTROL_REG (hang pulses) -scom 0x0000000008013C09 { - bits , scom_data; - 4:7 , 0b0000; #-- HANG_POLL_SCALE - 8:11 , 0b0011; #-- HANG_DATA_SCALE - 12:15 , 0b1011; #-- HANG_SHM_SCALE -} - -# spy name ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK1.NXCQ_SCOM.NX_MISC_CONTROL_REG (hang pulses) -scom 0x0000000008013C49 { - bits , scom_data; - 4:7 , 0b0000; #-- HANG_POLL_SCALE - 8:11 , 0b0011; #-- HANG_DATA_SCALE - 12:15 , 0b1011; #-- HANG_SHM_SCALE -} - -# spy name ES.NPU.SL_WRAP2.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NX_MISC_CONTROL_REG (hang pulses) -scom 0x0000000008013D09 { - bits , scom_data; - 4:7 , 0b0000; #-- HANG_POLL_SCALE - 8:11 , 0b0011; #-- HANG_DATA_SCALE - 12:15 , 0b1011; #-- HANG_SHM_SCALE -} - -# spy name ES.NPU.SL_WRAP2.NP_CQ.NP_CQ_LNK1.NXCQ_SCOM.NX_MISC_CONTROL_REG (hang pulses) -scom 0x0000000008013D49 { - bits , scom_data; - 4:7 , 0b0000; #-- HANG_POLL_SCALE - 8:11 , 0b0011; #-- HANG_DATA_SCALE - 12:15 , 0b1011; #-- HANG_SHM_SCALE -} - -# spy name ES.NPU.NP_AT.REG.NPU_AT_DEBUG (Debug/trace control) -scom 0x0000000008013DA9 { - bits, scom_data ; - 0:63, 0x7000000000000000 ; - } - -# spy name ES.NPU.NP_AT.REG.NPU_AT_PMU_CTRL (at pmu counter) -scom 0x0000000008013DA6 { - bits, scom_data ; - 0:63, 0xF210145000000000 ; - } - -# spy name ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NX_PB_ERR_RPT_0 -# scom 0x0000000008013C00 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# # spy name ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NX_PB_ERR_RPT_1 -# scom 0x0000000008013C01 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# # spy name ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK1.NXCQ_SCOM.NX_PB_ERR_RPT_0 -# scom 0x0000000008013C40 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# # spy name ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK1.NXCQ_SCOM.NX_PB_ERR_RPT_1 -# scom 0x0000000008013C41 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# spy name ES.NPU.SL_WRAP2.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NX_PB_ERR_RPT_0 -# scom 0x0000000008013D00 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# # spy name ES.NPU.SL_WRAP2.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NX_PB_ERR_RPT_1 -# scom 0x0000000008013D01 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# # spy name ES.NPU.SL_WRAP2.NP_CQ.NP_CQ_LNK1.NXCQ_SCOM.NX_PB_ERR_RPT_0 -# scom 0x0000000008013D40 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# # spy name ES.NPU.SL_WRAP2.NP_CQ.NP_CQ_LNK1.NXCQ_SCOM.NX_PB_ERR_RPT_1 -# scom 0x0000000008013D41 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# spy name ES.NPU.SL_WRAP0.NTL_WRAP0.NTL_PMU_CONTROL (ntl00 pmu counter) -scom 0x0000000008013C27 { - bits, scom_data ; - 0:63, 0xF21045C200000000 ; - } - -# spy name ES.NPU.SL_WRAP0.NTL_WRAP1.NTL_PMU_CONTROL (ntl01 pmu counter) -scom 0x0000000008013C67 { - bits, scom_data ; - 0:63, 0xF21045C200000000 ; - } - -# spy name ES.NPU.SL_WRAP2.NTL_WRAP0.NTL_PMU_CONTROL (ntl20 pmu counter) -scom 0x0000000008013D27 { - bits, scom_data ; - 0:63, 0xF21045C200000000 ; - } - -# spy name ES.NPU.SL_WRAP2.NTL_WRAP1.NTL_PMU_CONTROL (ntl21 pmu counter) -scom 0x0000000008013D67 { - bits, scom_data ; - 0:63, 0xF21045C200000000 ; - } - -# # spy name ES.NPU.SL_WRAP0.NTL_WRAP0.NTL_ER_HOLD -# scom 0x0000000008013C29 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# # spy name ES.NPU.SL_WRAP0.NTL_WRAP0.NTL_FST_ERR_REG -# scom 0x0000000008013C2A { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# # spy name ES.NPU.SL_WRAP0.NTL_WRAP1.NTL_ER_HOLD -# scom 0x0000000008013C69 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# spy name ES.NPU.SL_WRAP0.NTL_WRAP1.NTL_FST_ERR_REG -# scom 0x0000000008013C6A { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# # spy name ES.NPU.SL_WRAP2.NTL_WRAP0.NTL_ER_HOLD -# scom 0x0000000008013D29 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# # spy name ES.NPU.SL_WRAP2.NTL_WRAP0.NTL_FST_ERR_REG -# scom 0x0000000008013D2A { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# # spy name ES.NPU.SL_WRAP2.NTL_WRAP1.NTL_ER_HOLD -# scom 0x0000000008013D69 { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } -# -# # spy name ES.NPU.SL_WRAP2.NTL_WRAP1.NTL_FST_ERR_REG -# scom 0x0000000008013D6A { -# bits, scom_data ; -# 0:63, 0x0000000000000000 ; -# } - -# spy name ES.NPU.SL_WRAP0.NP_CQ.NP_CQ_LNK0.NXCQ_SCOM.NP_BUID_REG (Interrupt control) -scom 0x0000000008013C13 { - bits, scom_data ; - 0:63, 0x0800000043500000 ; - } - diff --git a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile deleted file mode 100644 index a475183d6..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile +++ /dev/null @@ -1,354 +0,0 @@ -#-- $Id: p8.nx.scom.initfile,v 1.15 2015/03/19 20:45:09 johnre Exp $ -#------------------------------------------------------------------------------- -#-- -#-- (C) Copyright International Business Machines Corp. 2011 -#-- All Rights Reserved -- Property of IBM -#-- *** *** -#-- -#-- TITLE : p8.nx.scom.initfile -#-- DESCRIPTION : Perform NX configuration -#-- -#-- OWNER NAME : John Reilly Email: johnre@us.ibm.com -#-- -#-------------------------------------------------------------------------------- - -SyntaxVersion = 1 - -#-------------------------------------------------------------------------------- -#-- Includes -#-------------------------------------------------------------------------------- - -#-------------------------------------------------------------------------------- -#-- Defines -#-------------------------------------------------------------------------------- -define eft_ci = ( ((8*ATTR_FABRIC_NODE_ID) + (ATTR_FABRIC_CHIP_ID) + 1) * 4) ; -define sym_ci = ( ((8*ATTR_FABRIC_NODE_ID) + (ATTR_FABRIC_CHIP_ID) + 1) * 4) ; -define asym_ci = ( ((8*ATTR_FABRIC_NODE_ID) + (ATTR_FABRIC_CHIP_ID) + 1) * 16); - - -#-- Naples does not have AMF engines. Using chip attribute to identify Naples -define def_amf_available = (ATTR_CHIP_EC_FEATURE_NV_PRESENT == 0) ; - - -#-------------------------------------------------------------------------------- -#-- SCOM initializations -#-------------------------------------------------------------------------------- - -#-- Engine Enable Register (0x02013041) -scom 0x02013041 { - bits , scom_data , expr ; - 53 , 0b0 , (!def_amf_available) ; #-- ch7 ASYM enable - 53 , 0b1 , ( def_amf_available) ; - 54 , 0b0 , (!def_amf_available) ; #-- ch6 ASYM enable - 54 , 0b1 , ( def_amf_available) ; - 55 , 0b0 , (!def_amf_available) ; #-- ch5 ASYM enable - 55 , 0b1 , ( def_amf_available) ; - 56 , 0b0 , (!def_amf_available) ; #-- ch4 ASYM enable - 56 , 0b1 , ( def_amf_available) ; - 57 , 0b1 , any ; #-- ch3 SYM enable - 58 , 0b1 , any ; #-- ch2 SYM enable - 62 , 0b1 , any ; #-- ch1 842 enable - 63 , 0b1 , any ; #-- ch0 842 enable -} - - -#-- DMA Config Register (0x02013042) -scom 0x02013042 { - bits , scom_data ; - 23 , 0b1 ; #-- 842 comp prefetch hint enable - 24 , 0b1 ; #-- 842 decomp prefetch hint enable - 25:28 , 0b0011 ; #-- max sym reads - 29:32 , 0b0001 ; #-- max amf reads - 33:36 , 0b1101 ; #-- max comp reads - 37:40 , 0b0111 ; #-- max decomp reads - 41:42 , 0b01 ; #-- sym csb write type 01:128B cache inject - 43:44 , 0b01 ; #-- sym comp write type 01:128B cache inject - 45:46 , 0b10 ; #-- sym cpb write type 10:128B cache inject - 47 , 0b0 ; #-- sym data write type 0:DMA write - 49:50 , 0b01 ; #-- amf csb write type 01:128B cache inject - 51:52 , 0b01 ; #-- amf comp write type 01:128B cache inject - 55 , 0b0 ; #-- amf data write type 0:DMA write - 56 , 0b0 ; #-- 842 spbc write enable - 57:58 , 0b01 ; #-- 842 csb write type 01:128B cache inject - 59:60 , 0b01 ; #-- 842 comp write type 01:128B cache inject - 61:62 , 0b10 ; #-- 842 cpb write type 10:128B cache inject - 63 , 0b0 ; #-- 842 data write type 0:DMA write -} - - -#-- Symmetric Coprocessor Config Register (0x0201308A) -scom 0x0201308A { - bits , scom_data ; - 2:14 , sym_ci ; #-- sym CI. function of node, chip id - 18:23 , 0b000001 ; #-- sym CT - 32:39 , 0b10110010 ; #-- sym FC mask. enable 0,2,3,6 - 63 , 0b1 ; #-- sym enable -} - - -#-- Asymmetric Coprocessor Config Register (0x0201308B) -scom 0x0201308B { - bits , scom_data , expr ; - 2:14 , asym_ci , any ; #-- asym CI. function of node, chip id - 18:23 , 0b000010 , any ; #-- asym CT - 32:55 , 0xfffff8 , any ; #-- asym FC mask. enable 0-20 - 63 , 0b0 , (!def_amf_available) ; #-- asym enable - 63 , 0b1 , ( def_amf_available) ; -} - - -#-- 842 Coprocessor Config Register (0x0201308C) -scom 0x0201308C { - bits , scom_data ; - 2:14 , eft_ci ; #-- 842 CI. function of node, chip id - 18:23 , 0b000000 ; #-- 842 CT - 32:36 , 0b11111 ; #-- 842 FC mask. enable 0-4 - 63 , 0b1 ; #-- 842 enable -} - - -#-- RNG Config Register (0x02013092) -scom 0x02013092 { - bits , scom_data ; - 46:61 , 0x07cf ; #-- RNG pacing. 0x07CF=1999. 2000 cycles between samples - 63 , 0b1 ; #-- RNG enable -} - - -#-- ICS Lite Config Register (0x02013093) -scom 0x02013093 { - bits , scom_data ; - 8:15 , 0x00 ; #-- trusted interrupt priority - 16:31 , 0x0000 ; #-- trusted interrupt server - 44:47 , 0b1100 ; #-- time to wait before resending returned interrupts. average 12*856ns - 54:63 , 0b0 ; #-- number of returns before issuing trusted interrupt. 0=never -} - - -#-- NX BUID Config Register (0x0201308E) -scom 0x0201308E { - bits , scom_data ; - 0 , 0b0 ; #-- BUID enable - 1:2 , ATTR_FABRIC_NODE_ID ; #-- BUID Base(0:1) Node Id ???? - 3:5 , ATTR_FABRIC_CHIP_ID ; #-- BUID Base(2:4) Chip Id ???? - 6:19 , 0b00000000000000 ; #-- BUID Base(5:18) ???? - 20:32 , 0b1111111100000 ; #-- BUID Mask(6:18). Mask(0:5) implied 0b111111 -} - - -#-- NX Cop_Req Input Queue Config Register (0x0201308F) -scom 0x0201308F { - bits , scom_data ; - 0:2 , 0b001 ; #-- SYM max extra queue entries. 2 total = 1 dedicated + 1 floating - 3:5 , 0b000 ; #-- ASYM max extra queue entries. 1 total = just 1 dedicated -} - - -#-- PowerBus Epsilon Config Register (0x0201309D) -scom 0x0201309D { - bits , scom_data ; - 6 , 0b0 ; #-- disable epsilon counter -} - - -#-- NX Miscellaneous Control Register (0x020130A8) -scom 0x020130A8 { - bits , scom_data , expr; - 4:7 , 0b0000 , (ATTR_CHIP_EC_FEATURE_NX_HANG_CONTROL_ON_SCOM != 0) ; #-- HANG_POLL_SCALE - 8:11 , 0b0011 , (ATTR_CHIP_EC_FEATURE_NX_HANG_CONTROL_ON_SCOM != 0) ; #-- HANG_DATA_SCALE - 12:15 , 0b1011 , (ATTR_CHIP_EC_FEATURE_NX_HANG_CONTROL_ON_SCOM != 0) ; #-- HANG_SHM_SCALE -} - - -#-- PBI FIR Action0,1 Register (0x02013086,7) -#-- action0,1 = 00 : checkstop -#-- 01 : recoverable -#-- 10 : unused -#-- 11 : local checkstop -scom 0x02013086 { - bits , scom_data ; #--Action - 0 , 0b0 ; #-- 0b00 PBI internal parity error - 1 , 0b0 ; #-- 0b01 PowerBus CE error - 2 , 0b0 ; #-- 0b01 PowerBus UE error - 3 , 0b0 ; #-- 0b00 mask PowerBus SUE error - 4 , 0b0 ; #-- 0b01 Inbound array CE error - 5 , 0b0 ; #-- 0b01 Inbound array UE error - 6 , 0b0 ; #-- 0b01 PowerBus data hang error - 7 , 0b0 ; #-- 0b00 mask PowerBus command hang error - 8 , 0b0 ; #-- 0b00 PowerBus read address error - 9 , 0b0 ; #-- 0b00 PowerBus write address error - 10 , 0b0 ; #-- 0b01 PowerBus miscellaneous error - 11 , 0b0 ; #-- 0b01 MMIO BAR parity error - 12 , 0b1 ; #-- 0b11 CRB kill ISN received while holding ISN with UE error - 13 , 0b0 ; #-- 0b01 ACK_DEAD cresp received by read command - 14 , 0b0 ; #-- 0b01 ACK_DEAD cresp received by write command - 15 , 0b0 ; #-- 0b01 Link check aborted while waiting on data - 16 , 0b0 ; #-- 0b01 Hang poll time expired on internal transfer - 17 , 0b0 ; #-- 0b00 mask Write to secure RNG control register when not enabled - 18 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error - 19 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error duplicate -} -scom 0x02013087 { - bits , scom_data ; #--Action - 0 , 0b0 ; #-- 0b00 PBI internal parity error - 1 , 0b1 ; #-- 0b01 PowerBus CE error - 2 , 0b1 ; #-- 0b01 PowerBus UE error - 3 , 0b0 ; #-- 0b00 mask PowerBus SUE error - 4 , 0b1 ; #-- 0b01 Inbound array CE error - 5 , 0b1 ; #-- 0b01 Inbound array UE error - 6 , 0b1 ; #-- 0b01 PowerBus data hang error - 7 , 0b0 ; #-- 0b00 mask PowerBus command hang error - 8 , 0b0 ; #-- 0b00 PowerBus read address error - 9 , 0b0 ; #-- 0b00 PowerBus write address error - 10 , 0b1 ; #-- 0b01 PowerBus miscellaneous error - 11 , 0b1 ; #-- 0b01 MMIO BAR parity error - 12 , 0b1 ; #-- 0b11 CRB kill ISN received while holding ISN with UE error - 13 , 0b1 ; #-- 0b01 ACK_DEAD cresp received by read command - 14 , 0b1 ; #-- 0b01 ACK_DEAD cresp received by write command - 15 , 0b1 ; #-- 0b01 Link check aborted while waiting on data - 16 , 0b1 ; #-- 0b01 Hang poll time expired on internal transfer - 17 , 0b0 ; #-- 0b00 mask Write to secure RNG control register when not enabled - 18 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error - 19 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error duplicate -} - - -#-- PBI FIR Mask Register (0x02013083) -scom 0x02013083 { - bits , scom_data ; - 0 , 0b0 ; #-- PBI internal parity error - 1 , 0b0 ; #-- PowerBus CE error - 2 , 0b0 ; #-- PowerBus UE error - 3 , 0b1 ; #-- mask PowerBus SUE error - 4 , 0b0 ; #-- Inbound array CE error - 5 , 0b0 ; #-- Inbound array UE error - 6 , 0b0 ; #-- PowerBus data hang error - 7 , 0b1 ; #-- mask PowerBus command hang error - 8 , 0b0 ; #-- PowerBus read address error - 9 , 0b0 ; #-- PowerBus write address error - 10 , 0b0 ; #-- PowerBus miscellaneous error - 11 , 0b0 ; #-- MMIO BAR parity error - 12 , 0b0 ; #-- CRB kill ISN received while holding ISN with UE error - 13 , 0b0 ; #-- ACK_DEAD cresp received by read command - 14 , 0b0 ; #-- ACK_DEAD cresp received by write command - 15 , 0b0 ; #-- Link check aborted while waiting on data - 16 , 0b0 ; #-- Hang poll time expired on internal transfer - 17 , 0b1 ; #-- mask Write to secure RNG control register when not enabled - 18 , 0b1 ; #-- mask FIR/SCOM satellite parity error - 19 , 0b1 ; #-- mask FIR/SCOM satellite parity error duplicate -} - - -#-- DMA/Engine Action0/1 Registers (0x02013106,07) -#-- action0,1 = 00 : checkstop -#-- 01 : recoverable -#-- 10 : unused -#-- 11 : local checkstop -scom 0x02013106 { - bits , scom_data ; #--Action - 0 , 0b0 ; #-- 0b00 mask Reserved - 1 , 0b1 ; #-- 0b11 ICS invalid state error FIR bit - 2:3 , 0b00 ; #-- 0b00 mask Reserved - 4 , 0b0 ; #-- 0b01 Channel 0 842 array corrected ECC error FIR bit" ; - 5 , 0b0 ; #-- 0b01 Channel 0 842 array uncorrectable ECC error FIR bit" ; - 6 , 0b0 ; #-- 0b01 Channel 1 842 array corrected ECC error FIR bit" ; - 7 , 0b0 ; #-- 0b01 Channel 1 842 array uncorrectable ECC error FIR bit" ; - 8 , 0b0 ; #-- 0b00 mask DMA non-zero CSB CC detected FIR bit. Programming error." ; - 9 , 0b0 ; #-- 0b01 DMA array correctable ECC error FIR bit" ; - 10 , 0b0 ; #-- 0b01 DMA outbound write/inbound read correctable ECC error FIR bit" ; - 11:13 , 0b000 ; #-- 0b01 Channel 5,6,7 AMF array corrected ECC error FIR bit" ; - 14 , 0b0 ; #-- 0b00 mask Error from other SCOM satellites FIR bit" ; - 15 , 0b1 ; #-- 0b11 DMA invalid state error FIR bit. Unrecoverable despite name" ; - 16 , 0b1 ; #-- 0b11 DMA invalid state error FIR bit" ; - 17 , 0b0 ; #-- 0b01 DMA array uncorrectable ECC error FIR bit" ; - 18 , 0b0 ; #-- 0b01 DMA outbound write/inbound read uncorrectable ECC error FIR bit" ; - 19 , 0b0 ; #-- 0b01 DMA inbound read error FIR bit" ; - 20:27 , 0b11111111 ; #-- 0b11 Channel 0-7 invalid state error FIR bit" ; - 28:30 , 0b000 ; #-- 0b01 Channel 5,6,7 AMF array uncorrectable ECC error FIR bit" ; - 31 , 0b1 ; #-- 0b11 UE error on CRB(CSB address, CCB) FIR bit" ; - 32 , 0b1 ; #-- 0b11 SUE error on CRB(CSB address, CCB) FIR bit" ; - 33 , 0b0 ; #-- 0b00 mask SUE error on something other than CRB(CSB address, CCB) FIR bit" ; - 34 , 0b0 ; #-- 0b00 mask Reserved - 35 , 0b0 ; #-- 0b00 mask Reserved - 36 , 0b0 ; #-- 0b01 Channel 4 AMF array corrected ECC error FIR bit" ; - 37 , 0b0 ; #-- 0b01 Channel 4 AMF array uncorrectable ECC error FIR bit" ; - 38 , 0b0 ; #-- 0b01 PHYP uses to signal PRD during NX freeze - 39:47 , 0b000000000 ; #-- 0b00 mask Reserved - 48 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error FIR bit" ; - 49 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error FIR bit duplicate" -} -scom 0x02013107 { - bits , scom_data ; #--Action - 0 , 0b0 ; #-- 0b00 mask Reserved - 1 , 0b1 ; #-- 0b11 ICS invalid state error FIR bit - 2:3 , 0b00 ; #-- 0b00 mask Reserved - 4 , 0b1 ; #-- 0b01 Channel 0 842 array corrected ECC error FIR bit" ; - 5 , 0b1 ; #-- 0b01 Channel 0 842 array uncorrectable ECC error FIR bit" ; - 6 , 0b1 ; #-- 0b01 Channel 1 842 array corrected ECC error FIR bit" ; - 7 , 0b1 ; #-- 0b01 Channel 1 842 array uncorrectable ECC error FIR bit" ; - 8 , 0b0 ; #-- 0b00 mask DMA non-zero CSB CC detected FIR bit. Programming error." ; - 9 , 0b1 ; #-- 0b01 DMA array correctable ECC error FIR bit" ; - 10 , 0b1 ; #-- 0b01 DMA outbound write/inbound read correctable ECC error FIR bit" ; - 11:13 , 0b111 ; #-- 0b01 Channel 5,6,7 AMF array corrected ECC error FIR bit" ; - 14 , 0b0 ; #-- 0b00 mask Error from other SCOM satellites FIR bit" ; - 15 , 0b1 ; #-- 0b11 DMA invalid state error FIR bit. Unrecoverable despite name" ; - 16 , 0b1 ; #-- 0b11 DMA invalid state error FIR bit" ; - 17 , 0b1 ; #-- 0b01 DMA array uncorrectable ECC error FIR bit" ; - 18 , 0b1 ; #-- 0b01 DMA outbound write/inbound read uncorrectable ECC error FIR bit" ; - 19 , 0b1 ; #-- 0b01 DMA inbound read error FIR bit" ; - 20:27 , 0b11111111 ; #-- 0b11 Channel 0-7 invalid state error FIR bit" ; - 28:30 , 0b111 ; #-- 0b01 Channel 5,6,7 AMF array uncorrectable ECC error FIR bit" ; - 31 , 0b1 ; #-- 0b11 UE error on CRB(CSB address, CCB) FIR bit" ; - 32 , 0b1 ; #-- 0b11 SUE error on CRB(CSB address, CCB) FIR bit" ; - 33 , 0b0 ; #-- 0b00 mask SUE error on something other than CRB(CSB address, CCB) FIR bit" ; - 34 , 0b0 ; #-- 0b00 mask Reserved - 35 , 0b0 ; #-- 0b00 mask Reserved - 36 , 0b1 ; #-- 0b01 Channel 4 AMF array corrected ECC error FIR bit" ; - 37 , 0b1 ; #-- 0b01 Channel 4 AMF array uncorrectable ECC error FIR bit" ; - 38 , 0b1 ; #-- 0b01 PHYP uses to signal PRD during NX freeze - 39:47 , 0b000000000 ; #-- 0b00 mask Reserved - 48 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error FIR bit" ; - 49 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error FIR bit duplicate" -} - - -#-- DMA/Engine FIR Mask Register (0x02013103) -scom 0x02013103 { - bits , scom_data , expr ; - 0 , 0b1 , any ; #-- mask Reserved - 1 , 0b0 , any ; #-- ICS invalid state error FIR bit - 2:3 , 0b11 , any ; #-- mask Reserved - 4 , 0b0 , any ; #-- Channel 0 842 array corrected ECC error FIR bit" ; - 5 , 0b0 , any ; #-- Channel 0 842 array uncorrectable ECC error FIR bit" ; - 6 , 0b0 , any ; #-- Channel 1 842 array corrected ECC error FIR bit" ; - 7 , 0b0 , any ; #-- Channel 1 842 array uncorrectable ECC error FIR bit" ; - 8 , 0b1 , any ; #-- mask DMA non-zero CSB CC detected FIR bit. Programming error." ; - 9 , 0b0 , any ; #-- DMA array correctable ECC error FIR bit" ; - 10 , 0b0 , any ; #-- DMA outbound write/inbound read correctable ECC error FIR bit" ; - 11:13 , 0b111 , (!def_amf_available) ; #-- Channel 5,6,7 AMF array corrected ECC error FIR bit" ; - 11:13 , 0b000 , ( def_amf_available) ; - 14 , 0b1 , any ; #-- mask Error from other SCOM satellites FIR bit" ; - 15 , 0b0 , any ; #-- DMA invalid state error FIR bit. Unrecoverable despite name" ; - 16 , 0b0 , any ; #-- DMA invalid state error FIR bit" ; - 17 , 0b0 , any ; #-- DMA array uncorrectable ECC error FIR bit" ; - 18 , 0b0 , any ; #-- DMA outbound write/inbound read uncorrectable ECC error FIR bit" ; - 19 , 0b0 , any ; #-- DMA inbound read error FIR bit" ; - 20:23 , 0b0000 , any ; #-- Channel 0-3 invalid state error FIR bit" ; - 24:27 , 0b1111 , (!def_amf_available) ; #-- Channel 4-7 invalid state error FIR bit" ; - 24:27 , 0b0000 , ( def_amf_available) ; - 28:30 , 0b111 , (!def_amf_available) ; #-- Channel 5,6,7 AMF array uncorrectable ECC error FIR bit" ; - 28:30 , 0b000 , ( def_amf_available) ; - 31 , 0b0 , any ; #-- UE error on CRB(CSB address, CCB) FIR bit" ; - 32 , 0b0 , any ; #-- SUE error on CRB(CSB address, CCB) FIR bit" ; - 33 , 0b1 , any ; #-- mask SUE error on something other than CRB(CSB address, CCB) FIR bit" ; - 34 , 0b1 , any ; #-- mask Reserved - 35 , 0b1 , any ; #-- mask Reserved - 36 , 0b1 , (!def_amf_available) ; #-- Channel 4 AMF array corrected ECC error FIR bit" ; - 36 , 0b0 , ( def_amf_available) ; - 37 , 0b1 , (!def_amf_available) ; #-- Channel 4 AMF array uncorrectable ECC error FIR bit" ; - 37 , 0b0 , ( def_amf_available) ; - 38 , 0b0 , any ; #-- PHYP uses to signal PRD during NX freeze - 39:47 , 0b111111111 , any ; #-- mask Reserved - 48 , 0b1 , any ; #-- mask FIR/SCOM satellite parity error FIR bit" ; - 49 , 0b1 , any ; #-- mask FIR/SCOM satellite parity error FIR bit duplicate" -} diff --git a/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile deleted file mode 100644 index f0d223850..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile +++ /dev/null @@ -1,3132 +0,0 @@ -#-- $Id: p8.pe.phase1.scom.initfile,v 1.7 2014/11/18 17:25:31 jmcgill Exp $ -#------------------------------------------------------------------------------- -#-- -#-- (C) Copyright International Business Machines Corp. 2011 -#-- All Rights Reserved -- Property of IBM -#-- *** *** -#-- -#-- TITLE : p8.pcie.phase1.scom.initfile -#-- DESCRIPTION : Perform PCIe Physical IO Inits (Phase 1, Steps 5-6) -#-- -#-- OWNER NAME : Joe McDonald Email: joemc@us.ibm.com -#-- OWNER NAME : Rick Mata Email: ricmata@us.ibm.com -#-- -#-------------------------------------------------------------------------------- - -SyntaxVersion = 1 - -#-------------------------------------------------------------------------------- -#-- Includes -#-------------------------------------------------------------------------------- - -#-------------------------------------------------------------------------------- -#-- Defines -#-------------------------------------------------------------------------------- - -define iop0 = (ATTR_PROC_PCIE_NUM_IOP >= 1); -define iop1 = (ATTR_PROC_PCIE_NUM_IOP >= 2); -define iop2 = (ATTR_PROC_PCIE_NUM_IOP >= 3); - -define lane_00_07 = (ATTR_PROC_PCIE_NUM_LANES >= 8); -define lane_08_15 = (ATTR_PROC_PCIE_NUM_LANES >= 16); -define lane_16_23 = (ATTR_PROC_PCIE_NUM_LANES >= 24); -define lane_24_31 = (ATTR_PROC_PCIE_NUM_LANES >= 32); -define lane_32_40 = (ATTR_PROC_PCIE_NUM_LANES >= 40); - -define zcal_override = (ATTR_CHIP_EC_FEATURE_ZCAL_OVERRIDE != 0); - -#-------------------------------------------------------------------------------- -#-- SCOM initializations -#-------------------------------------------------------------------------------- - -#-- -#-- IOP 0 -#-- - -#-- IOP PLL FIR Action0 Register -scom 0x09011406 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (iop0); -} - -#-- IOP PLL FIR Action1 Register -scom 0x09011407 { - bits, scom_data, expr; - 0:63, 0xFF00000000000000, (iop0); -} - -#-- IOP PLL FIR Mask Register -scom 0x09011403 { - bits, scom_data, expr; - 0:63, 0xFF80000000000000, (iop0); -} - -#-- G3 PLL Control Register 0 -scom 0x800008010901143F { - bits, scom_data, expr; - 51:63, ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0[0], (iop0); -} - -#-- G2 PLL Control Register 0 -scom 0x800008050901143F { - bits, scom_data, expr; - 51:63, ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0[0], (iop0); -} - -#-- PLL Global Control Register 0 -scom 0x800008080901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0[0], (iop0); -} - -#-- PLL Global Control Register 1 -scom 0x800008090901143F { - bits, scom_data, expr; - 51:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1[0], (iop0); -} - -#-- PCS Control Register 0 -scom 0x800008800901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL0[0], (iop0); -} - -#-- PCS Control Register 1 -scom 0x800008810901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL1[0], (iop0); -} - -#-- TX FIFO Control Register (A0) -scom 0x800004000901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_00_07); -} - -#-- TX FIFO Control Register (A1) -scom 0x800004400901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_00_07); -} - -#-- TX FIFO Control Register (A2) -scom 0x800004800901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_00_07); -} - -#-- TX FIFO Control Register (A3) -scom 0x800004C00901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_00_07); -} - -#-- TX FIFO Control Register (A4) -scom 0x800005000901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_00_07); -} - -#-- TX FIFO Control Register (A5) -scom 0x800005400901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_00_07); -} - -#-- TX FIFO Control Register (A6) -scom 0x800005800901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_00_07); -} - -#-- TX FIFO Control Register (A7) -scom 0x800005C00901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_00_07); -} - -#-- TX FIFO Control Register (B0) -scom 0x800006000901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_08_15); -} - -#-- TX FIFO Control Register (B1) -scom 0x800006400901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_08_15); -} - -#-- TX FIFO Control Register (B2) -scom 0x800006800901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_08_15); -} - -#-- TX FIFO Control Register (B3) -scom 0x800006C00901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_08_15); -} - -#-- TX FIFO Control Register (B4) -scom 0x800007000901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_08_15); -} - -#-- TX FIFO Control Register (B5) -scom 0x800007400901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_08_15); -} - -#-- TX FIFO Control Register (B6) -scom 0x800007800901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_08_15); -} - -#-- TX FIFO Control Register (B7) -scom 0x800007C00901143F { - bits, scom_data, expr; - 53:56, 0b1111, (iop0 && lane_08_15); -} - -#-- TX FIFO Offset Register (A0) -scom 0x800004010901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][0], (iop0 && lane_00_07); -} - -#-- TX FIFO Offset Register (A1) -scom 0x800004410901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][1], (iop0 && lane_00_07); -} - -#-- TX FIFO Offset Register (A2) -scom 0x800004810901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][2], (iop0 && lane_00_07); -} - -#-- TX FIFO Offset Register (A3) -scom 0x800004C10901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][3], (iop0 && lane_00_07); -} - -#-- TX FIFO Offset Register (A4) -scom 0x800005010901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][4], (iop0 && lane_00_07); -} - -#-- TX FIFO Offset Register (A5) -scom 0x800005410901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][5], (iop0 && lane_00_07); -} - -#-- TX FIFO Offset Register (A6) -scom 0x800005810901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][6], (iop0 && lane_00_07); -} - -#-- TX FIFO Offset Register (A7) -scom 0x800005C10901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][7], (iop0 && lane_00_07); -} - -#-- TX FIFO Offset Register (B0) -scom 0x800006010901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][8], (iop0 && lane_08_15); -} - -#-- TX FIFO Offset Register (B1) -scom 0x800006410901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][9], (iop0 && lane_08_15); -} - -#-- TX FIFO Offset Register (B2) -scom 0x800006810901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][10], (iop0 && lane_08_15); -} - -#-- TX FIFO Offset Register (B3) -scom 0x800006C10901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][11], (iop0 && lane_08_15); -} - -#-- TX FIFO Offset Register (B4) -scom 0x800007010901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][12], (iop0 && lane_08_15); -} - -#-- TX FIFO Offset Register (B5) -scom 0x800007410901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][13], (iop0 && lane_08_15); -} - -#-- TX FIFO Offset Register (B6) -scom 0x800007810901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][14], (iop0 && lane_08_15); -} - -#-- TX FIFO Offset Register (B7) -scom 0x800007C10901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[0][15], (iop0 && lane_08_15); -} - -#-- TX Receiver Detect Control Register (A0) -scom 0x800004020901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][0], (iop0 && lane_00_07); -} - -#-- TX Receiver Detect Control Register (A1) -scom 0x800004420901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][1], (iop0 && lane_00_07); -} - -#-- TX Receiver Detect Control Register (A2) -scom 0x800004820901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][2], (iop0 && lane_00_07); -} - -#-- TX Receiver Detect Control Register (A3) -scom 0x800004C20901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][3], (iop0 && lane_00_07); -} - -#-- TX Receiver Detect Control Register (A4) -scom 0x800005020901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][4], (iop0 && lane_00_07); -} - -#-- TX Receiver Detect Control Register (A5) -scom 0x800005420901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][5], (iop0 && lane_00_07); -} - -#-- TX Receiver Detect Control Register (A6) -scom 0x800005820901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][6], (iop0 && lane_00_07); -} - -#-- TX Receiver Detect Control Register (A7) -scom 0x800005C20901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][7], (iop0 && lane_00_07); -} - -#-- TX Receiver Detect Control Register (B0) -scom 0x800006020901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][8], (iop0 && lane_08_15); -} - -#-- TX Receiver Detect Control Register (B1) -scom 0x800006420901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][9], (iop0 && lane_08_15); -} - -#-- TX Receiver Detect Control Register (B2) -scom 0x800006820901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][10], (iop0 && lane_08_15); -} - -#-- TX Receiver Detect Control Register (B3) -scom 0x800006C20901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][11], (iop0 && lane_08_15); -} - -#-- TX Receiver Detect Control Register (B4) -scom 0x800007020901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][12], (iop0 && lane_08_15); -} - -#-- TX Receiver Detect Control Register (B5) -scom 0x800007420901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][13], (iop0 && lane_08_15); -} - -#-- TX Receiver Detect Control Register (B6) -scom 0x800007820901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][14], (iop0 && lane_08_15); -} - -#-- TX Receiver Detect Control Register (B7) -scom 0x800007C20901143F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[0][15], (iop0 && lane_08_15); -} - -#-- TX Bandwidth Loss Coefficient Register (A0) -scom 0x8000041B0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][0], (iop0 && lane_00_07); -} - -#-- TX Bandwidth Loss Coefficient Register (A1) -scom 0x8000045B0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][1], (iop0 && lane_00_07); -} - -#-- TX Bandwidth Loss Coefficient Register (A2) -scom 0x8000049B0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][2], (iop0 && lane_00_07); -} - -#-- TX Bandwidth Loss Coefficient Register (A3) -scom 0x800004DB0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][3], (iop0 && lane_00_07); -} - -#-- TX Bandwidth Loss Coefficient Register (A4) -scom 0x8000051B0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][4], (iop0 && lane_00_07); -} - -#-- TX Bandwidth Loss Coefficient Register (A5) -scom 0x8000055B0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][5], (iop0 && lane_00_07); -} - -#-- TX Bandwidth Loss Coefficient Register (A6) -scom 0x8000059B0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][6], (iop0 && lane_00_07); -} - -#-- TX Bandwidth Loss Coefficient Register (A7) -scom 0x800005DB0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][7], (iop0 && lane_00_07); -} - -#-- TX Bandwidth Loss Coefficient Register (B0) -scom 0x8000061B0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][8], (iop0 && lane_08_15); -} - -#-- TX Bandwidth Loss Coefficient Register (B1) -scom 0x8000065B0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][9], (iop0 && lane_08_15); -} - -#-- TX Bandwidth Loss Coefficient Register (B2) -scom 0x8000069B0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][10], (iop0 && lane_08_15); -} - -#-- TX Bandwidth Loss Coefficient Register (B3) -scom 0x800006DB0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][11], (iop0 && lane_08_15); -} - -#-- TX Bandwidth Loss Coefficient Register (B4) -scom 0x8000071B0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][12], (iop0 && lane_08_15); -} - -#-- TX Bandwidth Loss Coefficient Register (B5) -scom 0x8000075B0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][13], (iop0 && lane_08_15); -} - -#-- TX Bandwidth Loss Coefficient Register (B6) -scom 0x8000079B0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][14], (iop0 && lane_08_15); -} - -#-- TX Bandwidth Loss Coefficient Register (B7) -scom 0x800007DB0901143F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[0][15], (iop0 && lane_08_15); -} - -#-- RX VGA Control Register2 (A0) -scom 0x8000000C0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][0], (iop0 && lane_00_07); -} - -#-- RX VGA Control Register2 (A1) -scom 0x8000004C0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][1], (iop0 && lane_00_07); -} - -#-- RX VGA Control Register2 (A2) -scom 0x8000008C0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][2], (iop0 && lane_00_07); -} - -#-- RX VGA Control Register2 (A3) -scom 0x800000CC0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][3], (iop0 && lane_00_07); -} - -#-- RX VGA Control Register2 (A4) -scom 0x8000010C0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][4], (iop0 && lane_00_07); -} - -#-- RX VGA Control Register2 (A5) -scom 0x8000014C0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][5], (iop0 && lane_00_07); -} - -#-- RX VGA Control Register2 (A6) -scom 0x8000018C0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][6], (iop0 && lane_00_07); -} - -#-- RX VGA Control Register2 (A7) -scom 0x800001CC0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][7], (iop0 && lane_00_07); -} - -#-- RX VGA Control Register2 (B0) -scom 0x8000020C0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][8], (iop0 && lane_08_15); -} - -#-- RX VGA Control Register2 (B1) -scom 0x8000024C0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][9], (iop0 && lane_08_15); -} - -#-- RX VGA Control Register2 (B2) -scom 0x8000028C0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][10], (iop0 && lane_08_15); -} - -#-- RX VGA Control Register2 (B3) -scom 0x800002CC0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][11], (iop0 && lane_08_15); -} - -#-- RX VGA Control Register2 (B4) -scom 0x8000030C0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][12], (iop0 && lane_08_15); -} - -#-- RX VGA Control Register2 (B5) -scom 0x8000034C0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][13], (iop0 && lane_08_15); -} - -#-- RX VGA Control Register2 (B6) -scom 0x8000038C0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][14], (iop0 && lane_08_15); -} - -#-- RX VGA Control Register2 (B7) -scom 0x800003CC0901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[0][15], (iop0 && lane_08_15); -} - -#-- RX Receiver Peaking Register (A0) -scom 0x800000100901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][0], (iop0 && lane_00_07); -} - -#-- RX Receiver Peaking Register (A1) -scom 0x800000500901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][1], (iop0 && lane_00_07); -} - -#-- RX Receiver Peaking Register (A2) -scom 0x800000900901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][2], (iop0 && lane_00_07); -} - -#-- RX Receiver Peaking Register (A3) -scom 0x800000D00901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][3], (iop0 && lane_00_07); -} - -#-- RX Receiver Peaking Register (A4) -scom 0x800001100901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][4], (iop0 && lane_00_07); -} - -#-- RX Receiver Peaking Register (A5) -scom 0x800001500901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][5], (iop0 && lane_00_07); -} - -#-- RX Receiver Peaking Register (A6) -scom 0x800001900901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][6], (iop0 && lane_00_07); -} - -#-- RX Receiver Peaking Register (A7) -scom 0x800001D00901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][7], (iop0 && lane_00_07); -} - -#-- RX Receiver Peaking Register (B0) -scom 0x800002100901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][8], (iop0 && lane_08_15); -} - -#-- RX Receiver Peaking Register (B1) -scom 0x800002500901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][9], (iop0 && lane_08_15); -} - -#-- RX Receiver Peaking Register (B2) -scom 0x800002900901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][10], (iop0 && lane_08_15); -} - -#-- RX Receiver Peaking Register (B3) -scom 0x800002D00901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][11], (iop0 && lane_08_15); -} - -#-- RX Receiver Peaking Register (B4) -scom 0x800003100901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][12], (iop0 && lane_08_15); -} - -#-- RX Receiver Peaking Register (B5) -scom 0x800003500901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][13], (iop0 && lane_08_15); -} - -#-- RX Receiver Peaking Register (B6) -scom 0x800003900901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][14], (iop0 && lane_08_15); -} - -#-- RX Receiver Peaking Register (B7) -scom 0x800003D00901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[0][15], (iop0 && lane_08_15); -} - -#-- RX Signal Detect Level Register (A0) -scom 0x800000370901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][0], (iop0 && lane_00_07); -} - -#-- RX Signal Detect Level Register (A1) -scom 0x800000770901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][1], (iop0 && lane_00_07); -} - -#-- RX Signal Detect Level Register (A2) -scom 0x800000B70901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][2], (iop0 && lane_00_07); -} - -#-- RX Signal Detect Level Register (A3) -scom 0x800000F70901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][3], (iop0 && lane_00_07); -} - -#-- RX Signal Detect Level Register (A4) -scom 0x800001370901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][4], (iop0 && lane_00_07); -} - -#-- RX Signal Detect Level Register (A5) -scom 0x800001770901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][5], (iop0 && lane_00_07); -} - -#-- RX Signal Detect Level Register (A6) -scom 0x800001B70901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][6], (iop0 && lane_00_07); -} - -#-- RX Signal Detect Level Register (A7) -scom 0x800001F70901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][7], (iop0 && lane_00_07); -} - -#-- RX Signal Detect Level Register (B0) -scom 0x800002370901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][8], (iop0 && lane_08_15); -} - -#-- RX Signal Detect Level Register (B1) -scom 0x800002770901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][9], (iop0 && lane_08_15); -} - -#-- RX Signal Detect Level Register (B2) -scom 0x800002B70901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][10], (iop0 && lane_08_15); -} - -#-- RX Signal Detect Level Register (B3) -scom 0x800002F70901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][11], (iop0 && lane_08_15); -} - -#-- RX Signal Detect Level Register (B4) -scom 0x800003370901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][12], (iop0 && lane_08_15); -} - -#-- RX Signal Detect Level Register (B5) -scom 0x800003770901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][13], (iop0 && lane_08_15); -} - -#-- RX Signal Detect Level Register (B6) -scom 0x800003B70901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][14], (iop0 && lane_08_15); -} - -#-- RX Signal Detect Level Register (B7) -scom 0x800003F70901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[0][15], (iop0 && lane_08_15); -} - -#-- TX GEN1 Coefficient Override Register (A0) -scom 0x800004100901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][0], (iop0 && lane_00_07); -} - -#-- TX GEN1 Coefficient Override Register (A1) -scom 0x800004500901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][1], (iop0 && lane_00_07); -} - -#-- TX GEN1 Coefficient Override Register (A2) -scom 0x800004900901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][2], (iop0 && lane_00_07); -} - -#-- TX GEN1 Coefficient Override Register (A3) -scom 0x800004D00901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][3], (iop0 && lane_00_07); -} - -#-- TX GEN1 Coefficient Override Register (A4) -scom 0x800005100901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][4], (iop0 && lane_00_07); -} - -#-- TX GEN1 Coefficient Override Register (A5) -scom 0x800005500901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][5], (iop0 && lane_00_07); -} - -#-- TX GEN1 Coefficient Override Register (A6) -scom 0x800005900901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][6], (iop0 && lane_00_07); -} - -#-- TX GEN1 Coefficient Override Register (A7) -scom 0x800005D00901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][7], (iop0 && lane_00_07); -} - -#-- TX GEN1 Coefficient Override Register (B0) -scom 0x800006100901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][8], (iop0 && lane_08_15); -} - -#-- TX GEN1 Coefficient Override Register (B1) -scom 0x800006500901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][9], (iop0 && lane_08_15); -} - -#-- TX GEN1 Coefficient Override Register (B2) -scom 0x800006900901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][10], (iop0 && lane_08_15); -} - -#-- TX GEN1 Coefficient Override Register (B3) -scom 0x800006D00901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][11], (iop0 && lane_08_15); -} - -#-- TX GEN1 Coefficient Override Register (B4) -scom 0x800007100901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][12], (iop0 && lane_08_15); -} - -#-- TX GEN1 Coefficient Override Register (B5) -scom 0x800007500901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][13], (iop0 && lane_08_15); -} - -#-- TX GEN1 Coefficient Override Register (B6) -scom 0x800007900901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][14], (iop0 && lane_08_15); -} - -#-- TX GEN1 Coefficient Override Register (B7) -scom 0x800007D00901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[0][15], (iop0 && lane_08_15); -} - -#-- TX GEN2 Coefficient Override Register (A0) -scom 0x800004110901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][0], (iop0 && lane_00_07); -} - -#-- TX GEN2 Coefficient Override Register (A1) -scom 0x800004510901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][1], (iop0 && lane_00_07); -} - -#-- TX GEN2 Coefficient Override Register (A2) -scom 0x800004910901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][2], (iop0 && lane_00_07); -} - -#-- TX GEN2 Coefficient Override Register (A3) -scom 0x800004D10901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][3], (iop0 && lane_00_07); -} - -#-- TX GEN2 Coefficient Override Register (A4) -scom 0x800005110901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][4], (iop0 && lane_00_07); -} - -#-- TX GEN2 Coefficient Override Register (A5) -scom 0x800005510901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][5], (iop0 && lane_00_07); -} - -#-- TX GEN2 Coefficient Override Register (A6) -scom 0x800005910901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][6], (iop0 && lane_00_07); -} - -#-- TX GEN2 Coefficient Override Register (A7) -scom 0x800005D10901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][7], (iop0 && lane_00_07); -} - -#-- TX GEN2 Coefficient Override Register (B0) -scom 0x800006110901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][8], (iop0 && lane_08_15); -} - -#-- TX GEN2 Coefficient Override Register (B1) -scom 0x800006510901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][9], (iop0 && lane_08_15); -} - -#-- TX GEN2 Coefficient Override Register (B2) -scom 0x800006910901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][10], (iop0 && lane_08_15); -} - -#-- TX GEN2 Coefficient Override Register (B3) -scom 0x800006D10901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][11], (iop0 && lane_08_15); -} - -#-- TX GEN1 Coefficient Override Register (B4) -scom 0x800007110901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][12], (iop0 && lane_08_15); -} - -#-- TX GEN2 Coefficient Override Register (B5) -scom 0x800007510901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][13], (iop0 && lane_08_15); -} - -#-- TX GEN2 Coefficient Override Register (B6) -scom 0x800007910901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][14], (iop0 && lane_08_15); -} - -#-- TX GEN2 Coefficient Override Register (B7) -scom 0x800007D10901143F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[0][15], (iop0 && lane_08_15); -} - -#-- RX Phase Rotator Flywheel Control Register (A0) -scom 0x8000002F0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_00_07); -} - -#-- RX Phase Rotator Flywheel Control Register (A1) -scom 0x8000006F0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_00_07); -} - -#-- RX Phase Rotator Flywheel Control Register (A2) -scom 0x800000AF0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_00_07); -} - -#-- RX Phase Rotator Flywheel Control Register (A3) -scom 0x800000EF0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_00_07); -} - -#-- RX Phase Rotator Flywheel Control Register (A4) -scom 0x8000012F0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_00_07); -} - -#-- RX Phase Rotator Flywheel Control Register (A5) -scom 0x8000016F0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_00_07); -} - -#-- RX Phase Rotator Flywheel Control Register (A6) -scom 0x800001AF0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_00_07); -} - -#-- RX Phase Rotator Flywheel Control Register (A7) -scom 0x800001EF0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_00_07); -} - -#-- RX Phase Rotator Flywheel Control Register (B0) -scom 0x8000022F0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_08_15); -} - -#-- RX Phase Rotator Flywheel Control Register (B1) -scom 0x8000026F0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_08_15); -} - -#-- RX Phase Rotator Flywheel Control Register (B2) -scom 0x800002AF0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_08_15); -} - -#-- RX Phase Rotator Flywheel Control Register (B3) -scom 0x800002EF0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_08_15); -} - -#-- RX Phase Rotator Flywheel Control Register (B4) -scom 0x8000032F0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_08_15); -} - -#-- RX Phase Rotator Flywheel Control Register (B5) -scom 0x8000036F0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_08_15); -} - -#-- RX Phase Rotator Flywheel Control Register (B6) -scom 0x800003AF0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_08_15); -} - -#-- RX Phase Rotator Flywheel Control Register (B7) -scom 0x800003EF0901143F { - bits, scom_data, expr; - 56:59, 0b1110, (iop0 && lane_08_15); -} - -#-- DFE Function Control Register 1 (A0) -scom 0x8000001F0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_00_07); -} - -#-- DFE Function Control Register 1 (A1) -scom 0x8000005F0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_00_07); -} - -#-- DFE Function Control Register 1 (A2) -scom 0x8000009F0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_00_07); -} - -#-- DFE Function Control Register 1 (A3) -scom 0x800000DF0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_00_07); -} - -#-- DFE Function Control Register 1 (A4) -scom 0x8000011F0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_00_07); -} - -#-- DFE Function Control Register 1 (A5) -scom 0x8000015F0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_00_07); -} - -#-- DFE Function Control Register 1 (A6) -scom 0x8000019F0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_00_07); -} - -#-- DFE Function Control Register 1 (A7) -scom 0x800001DF0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_00_07); -} - -#-- DFE Function Control Register 1 (B0) -scom 0x8000021F0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_08_15); -} - -#-- DFE Function Control Register 1 (B1) -scom 0x8000025F0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_08_15); -} - -#-- DFE Function Control Register 1 (B2) -scom 0x8000029F0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_08_15); -} - -#-- DFE Function Control Register 1 (B3) -scom 0x800002DF0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_08_15); -} - -#-- DFE Function Control Register 1 (B4) -scom 0x8000031F0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_08_15); -} - -#-- DFE Function Control Register 1 (B5) -scom 0x8000035F0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_08_15); -} - -#-- DFE Function Control Register 1 (B6) -scom 0x8000039F0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_08_15); -} - -#-- DFE Function Control Register 1 (B7) -scom 0x800003DF0901143F { - bits, scom_data, expr; - 49, 0b0, (iop0 && lane_08_15); -} - -#-- Receiver Configuration Mode Register (A0) -scom 0x800000000901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_00_07); -} - -#-- Receiver Configuration Mode Register (A1) -scom 0x800000400901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_00_07); -} - -#-- Receiver Configuration Mode Register (A2) -scom 0x800000800901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_00_07); -} - -#-- Receiver Configuration Mode Register (A3) -scom 0x800000C00901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_00_07); -} - -#-- Receiver Configuration Mode Register (A4) -scom 0x800001000901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_00_07); -} - -#-- Receiver Configuration Mode Register (A5) -scom 0x800001400901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_00_07); -} - -#-- Receiver Configuration Mode Register (A6) -scom 0x800001800901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_00_07); -} - -#-- Receiver Configuration Mode Register (A7) -scom 0x800001C00901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_00_07); -} - -#-- Receiver Configuration Mode Register (B0) -scom 0x800002000901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_08_15); -} - -#-- Receiver Configuration Mode Register (B1) -scom 0x800002400901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_08_15); -} - -#-- Receiver Configuration Mode Register (B2) -scom 0x800002800901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_08_15); -} - -#-- Receiver Configuration Mode Register (B3) -scom 0x800002C00901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_08_15); -} - -#-- Receiver Configuration Mode Register (B4) -scom 0x800003000901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_08_15); -} - -#-- Receiver Configuration Mode Register (B5) -scom 0x800003400901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_08_15); -} - -#-- Receiver Configuration Mode Register (B6) -scom 0x800003800901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_08_15); -} - -#-- Receiver Configuration Mode Register (B7) -scom 0x800003C00901143F { - bits, scom_data, expr; - 49, 0b1, (iop0 && lane_08_15); -} - -#-- ZCAL Control Register -scom 0x800008400901143F { - bits, scom_data, expr; - 53:60, ATTR_PROC_PCIE_IOP_ZCAL_CONTROL[0], (iop0); -} - -#-- ZCAL Override Register -scom 0x800008420901143F { - bits, scom_data, expr; - 48:63, 0xEC30, (iop0 && zcal_override); -} - - -#-- -#-- IOP 1 -#-- - -#-- IOP PLL FIR Action0 Register -scom 0x09011846 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (iop1); -} - -#-- IOP PLL FIR Action1 Register -scom 0x09011847 { - bits, scom_data, expr; - 0:63, 0xFF00000000000000, (iop1); -} - -#-- IOP PLL FIR Mask Register -scom 0x09011843 { - bits, scom_data expr; - 0:63, 0xFF80000000000000, (iop1); -} - -#-- G3 PLL Control Register 0 -scom 0x800008010901187F { - bits, scom_data, expr; - 51:63, ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0[1], (iop1); -} - -#-- G2 PLL Control Register 0 -scom 0x800008050901187F { - bits, scom_data, expr; - 51:63, ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0[1], (iop1); -} - -#-- PLL Global Control Register 0 -scom 0x800008080901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0[1], (iop1); -} - -#-- PLL Global Control Register 1 -scom 0x800008090901187F { - bits, scom_data, expr; - 51:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1[1], (iop1); -} - -#-- PCS Control Register 0 -scom 0x800008800901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL0[1], (iop1); -} - -#-- PCS Control Register 1 -scom 0x800008810901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL1[1], (iop1); -} - -#-- TX FIFO Control Register (A0) -scom 0x800004000901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_16_23); -} - -#-- TX FIFO Control Register (A1) -scom 0x800004400901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_16_23); -} - -#-- TX FIFO Control Register (A2) -scom 0x800004800901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_16_23); -} - -#-- TX FIFO Control Register (A3) -scom 0x800004C00901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_16_23); -} - -#-- TX FIFO Control Register (A4) -scom 0x800005000901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_16_23); -} - -#-- TX FIFO Control Register (A5) -scom 0x800005400901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_16_23); -} - -#-- TX FIFO Control Register (A6) -scom 0x800005800901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_16_23); -} - -#-- TX FIFO Control Register (A7) -scom 0x800005C00901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_16_23); -} - -#-- TX FIFO Control Register (B0) -scom 0x800006000901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_24_31); -} - -#-- TX FIFO Control Register (B1) -scom 0x800006400901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_24_31); -} - -#-- TX FIFO Control Register (B2) -scom 0x800006800901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_24_31); -} - -#-- TX FIFO Control Register (B3) -scom 0x800006C00901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_24_31); -} - -#-- TX FIFO Control Register (B4) -scom 0x800007000901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_24_31); -} - -#-- TX FIFO Control Register (B5) -scom 0x800007400901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_24_31); -} - -#-- TX FIFO Control Register (B6) -scom 0x800007800901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_24_31); -} - -#-- TX FIFO Control Register (B7) -scom 0x800007C00901187F { - bits, scom_data, expr; - 53:56, 0b1111, (iop1 && lane_24_31); -} - -#-- TX FIFO Offset Register (A0) -scom 0x800004010901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][0], (iop1 && lane_16_23); -} - -#-- TX FIFO Offset Register (A1) -scom 0x800004410901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][1], (iop1 && lane_16_23); -} - -#-- TX FIFO Offset Register (A2) -scom 0x800004810901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][2], (iop1 && lane_16_23); -} - -#-- TX FIFO Offset Register (A3) -scom 0x800004C10901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][3], (iop1 && lane_16_23); -} - -#-- TX FIFO Offset Register (A4) -scom 0x800005010901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][4], (iop1 && lane_16_23); -} - -#-- TX FIFO Offset Register (A5) -scom 0x800005410901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][5], (iop1 && lane_16_23); -} - -#-- TX FIFO Offset Register (A6) -scom 0x800005810901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][6], (iop1 && lane_16_23); -} - -#-- TX FIFO Offset Register (A7) -scom 0x800005C10901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][7], (iop1 && lane_16_23); -} - -#-- TX FIFO Offset Register (B0) -scom 0x800006010901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][8], (iop1 && lane_24_31); -} - -#-- TX FIFO Offset Register (B1) -scom 0x800006410901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][9], (iop1 && lane_24_31); -} - -#-- TX FIFO Offset Register (B2) -scom 0x800006810901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][10], (iop1 && lane_24_31); -} - -#-- TX FIFO Offset Register (B3) -scom 0x800006C10901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][11], (iop1 && lane_24_31); -} - -#-- TX FIFO Offset Register (B4) -scom 0x800007010901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][12], (iop1 && lane_24_31); -} - -#-- TX FIFO Offset Register (B5) -scom 0x800007410901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][13], (iop1 && lane_24_31); -} - -#-- TX FIFO Offset Register (B6) -scom 0x800007810901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][14], (iop1 && lane_24_31); -} - -#-- TX FIFO Offset Register (B7) -scom 0x800007C10901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[1][15], (iop1 && lane_24_31); -} - -#-- TX Receiver Detect Control Register (A0) -scom 0x800004020901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][0], (iop1 && lane_16_23); -} - -#-- TX Receiver Detect Control Register (A1) -scom 0x800004420901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][1], (iop1 && lane_16_23); -} - -#-- TX Receiver Detect Control Register (A2) -scom 0x800004820901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][2], (iop1 && lane_16_23); -} - -#-- TX Receiver Detect Control Register (A3) -scom 0x800004C20901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][3], (iop1 && lane_16_23); -} - -#-- TX Receiver Detect Control Register (A4) -scom 0x800005020901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][4], (iop1 && lane_16_23); -} - -#-- TX Receiver Detect Control Register (A5) -scom 0x800005420901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][5], (iop1 && lane_16_23); -} - -#-- TX Receiver Detect Control Register (A6) -scom 0x800005820901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][6], (iop1 && lane_16_23); -} - -#-- TX Receiver Detect Control Register (A7) -scom 0x800005C20901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][7], (iop1 && lane_16_23); -} - -#-- TX Receiver Detect Control Register (B0) -scom 0x800006020901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][8], (iop1 && lane_24_31); -} - -#-- TX Receiver Detect Control Register (B1) -scom 0x800006420901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][9], (iop1 && lane_24_31); -} - -#-- TX Receiver Detect Control Register (B2) -scom 0x800006820901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][10], (iop1 && lane_24_31); -} - -#-- TX Receiver Detect Control Register (B3) -scom 0x800006C20901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][11], (iop1 && lane_24_31); -} - -#-- TX Receiver Detect Control Register (B4) -scom 0x800007020901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][12], (iop1 && lane_24_31); -} - -#-- TX Receiver Detect Control Register (B5) -scom 0x800007420901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][13], (iop1 && lane_24_31); -} - -#-- TX Receiver Detect Control Register (B6) -scom 0x800007820901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][14], (iop1 && lane_24_31); -} - -#-- TX Receiver Detect Control Register (B7) -scom 0x800007C20901187F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[1][15], (iop1 && lane_24_31); -} - -#-- TX Bandwidth Loss Coefficient Register (A0) -scom 0x8000041B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][0], (iop1 && lane_16_23); -} - -#-- TX Bandwidth Loss Coefficient Register (A1) -scom 0x8000045B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][1], (iop1 && lane_16_23); -} - -#-- TX Bandwidth Loss Coefficient Register (A2) -scom 0x8000049B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][2], (iop1 && lane_16_23); -} - -#-- TX Bandwidth Loss Coefficient Register (A3) -scom 0x800004DB0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][3], (iop1 && lane_16_23); -} - -#-- TX Bandwidth Loss Coefficient Register (A4) -scom 0x8000051B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][4], (iop1 && lane_16_23); -} - -#-- TX Bandwidth Loss Coefficient Register (A5) -scom 0x8000055B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][5], (iop1 && lane_16_23); -} - -#-- TX Bandwidth Loss Coefficient Register (A6) -scom 0x8000059B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][6], (iop1 && lane_16_23); -} - -#-- TX Bandwidth Loss Coefficient Register (A7) -scom 0x800005DB0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][7], (iop1 && lane_16_23); -} - -#-- TX Bandwidth Loss Coefficient Register (B0) -scom 0x8000061B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][8], (iop1 && lane_24_31); -} - -#-- TX Bandwidth Loss Coefficient Register (B1) -scom 0x8000065B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][9], (iop1 && lane_24_31); -} - -#-- TX Bandwidth Loss Coefficient Register (B2) -scom 0x8000069B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][10], (iop1 && lane_24_31); -} - -#-- TX Bandwidth Loss Coefficient Register (B3) -scom 0x800006DB0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][11], (iop1 && lane_24_31); -} - -#-- TX Bandwidth Loss Coefficient Register (B4) -scom 0x8000071B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][12], (iop1 && lane_24_31); -} - -#-- TX Bandwidth Loss Coefficient Register (B5) -scom 0x8000075B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][13], (iop1 && lane_24_31); -} - -#-- TX Bandwidth Loss Coefficient Register (B6) -scom 0x8000079B0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][14], (iop1 && lane_24_31); -} - -#-- TX Bandwidth Loss Coefficient Register (B7) -scom 0x800007DB0901187F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[1][15], (iop1 && lane_24_31); -} - -#-- RX VGA Control Register2 (A0) -scom 0x8000000C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][0], (iop1 && lane_16_23); -} - -#-- RX VGA Control Register2 (A1) -scom 0x8000004C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][1], (iop1 && lane_16_23); -} - -#-- RX VGA Control Register2 (A2) -scom 0x8000008C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][2], (iop1 && lane_16_23); -} - -#-- RX VGA Control Register2 (A3) -scom 0x800000CC0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][3], (iop1 && lane_16_23); -} - -#-- RX VGA Control Register2 (A4) -scom 0x8000010C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][4], (iop1 && lane_16_23); -} - -#-- RX VGA Control Register2 (A5) -scom 0x8000014C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][5], (iop1 && lane_16_23); -} - -#-- RX VGA Control Register2 (A6) -scom 0x8000018C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][6], (iop1 && lane_16_23); -} - -#-- RX VGA Control Register2 (A7) -scom 0x800001CC0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][7], (iop1 && lane_16_23); -} - -#-- RX VGA Control Register2 (B0) -scom 0x8000020C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][8], (iop1 && lane_24_31); -} - -#-- RX VGA Control Register2 (B1) -scom 0x8000024C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][9], (iop1 && lane_24_31); -} - -#-- RX VGA Control Register2 (B2) -scom 0x8000028C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][10], (iop1 && lane_24_31); -} - -#-- RX VGA Control Register2 (B3) -scom 0x800002CC0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][11], (iop1 && lane_24_31); -} - -#-- RX VGA Control Register2 (B4) -scom 0x8000030C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][12], (iop1 && lane_24_31); -} - -#-- RX VGA Control Register2 (B5) -scom 0x8000034C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][13], (iop1 && lane_24_31); -} - -#-- RX VGA Control Register2 (B6) -scom 0x8000038C0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][14], (iop1 && lane_24_31); -} - -#-- RX VGA Control Register2 (B7) -scom 0x800003CC0901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[1][15], (iop1 && lane_24_31); -} - -#-- RX Receiver Peaking Register (A0) -scom 0x800000100901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][0], (iop1 && lane_16_23); -} - -#-- RX Receiver Peaking Register (A1) -scom 0x800000500901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][1], (iop1 && lane_16_23); -} - -#-- RX Receiver Peaking Register (A2) -scom 0x800000900901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][2], (iop1 && lane_16_23); -} - -#-- RX Receiver Peaking Register (A3) -scom 0x800000D00901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][3], (iop1 && lane_16_23); -} - -#-- RX Receiver Peaking Register (A4) -scom 0x800001100901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][4], (iop1 && lane_16_23); -} - -#-- RX Receiver Peaking Register (A5) -scom 0x800001500901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][5], (iop1 && lane_16_23); -} - -#-- RX Receiver Peaking Register (A6) -scom 0x800001900901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][6], (iop1 && lane_16_23); -} - -#-- RX Receiver Peaking Register (A7) -scom 0x800001D00901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][7], (iop1 && lane_16_23); -} - -#-- RX Receiver Peaking Register (B0) -scom 0x800002100901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][8], (iop1 && lane_24_31); -} - -#-- RX Receiver Peaking Register (B1) -scom 0x800002500901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][9], (iop1 && lane_24_31); -} - -#-- RX Receiver Peaking Register (B2) -scom 0x800002900901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][10], (iop1 && lane_24_31); -} - -#-- RX Receiver Peaking Register (B3) -scom 0x800002D00901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][11], (iop1 && lane_24_31); -} - -#-- RX Receiver Peaking Register (B4) -scom 0x800003100901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][12], (iop1 && lane_24_31); -} - -#-- RX Receiver Peaking Register (B5) -scom 0x800003500901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][13], (iop1 && lane_24_31); -} - -#-- RX Receiver Peaking Register (B6) -scom 0x800003900901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][14], (iop1 && lane_24_31); -} - -#-- RX Receiver Peaking Register (B7) -scom 0x800003D00901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[1][15], (iop1 && lane_24_31); -} - -#-- RX Signal Detect Level Register (A0) -scom 0x800000370901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][0], (iop1 && lane_16_23); -} - -#-- RX Signal Detect Level Register (A1) -scom 0x800000770901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][1], (iop1 && lane_16_23); -} - -#-- RX Signal Detect Level Register (A2) -scom 0x800000B70901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][2], (iop1 && lane_16_23); -} - -#-- RX Signal Detect Level Register (A3) -scom 0x800000F70901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][3], (iop1 && lane_16_23); -} - -#-- RX Signal Detect Level Register (A4) -scom 0x800001370901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][4], (iop1 && lane_16_23); -} - -#-- RX Signal Detect Level Register (A5) -scom 0x800001770901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][5], (iop1 && lane_16_23); -} - -#-- RX Signal Detect Level Register (A6) -scom 0x800001B70901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][6], (iop1 && lane_16_23); -} - -#-- RX Signal Detect Level Register (A7) -scom 0x800001F70901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][7], (iop1 && lane_16_23); -} - -#-- RX Signal Detect Level Register (B0) -scom 0x800002370901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][8], (iop1 && lane_24_31); -} - -#-- RX Signal Detect Level Register (B1) -scom 0x800002770901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][9], (iop1 && lane_24_31); -} - -#-- RX Signal Detect Level Register (B2) -scom 0x800002B70901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][10], (iop1 && lane_24_31); -} - -#-- RX Signal Detect Level Register (B3) -scom 0x800002F70901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][11], (iop1 && lane_24_31); -} - -#-- RX Signal Detect Level Register (B4) -scom 0x800003370901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][12], (iop1 && lane_24_31); -} - -#-- RX Signal Detect Level Register (B5) -scom 0x800003770901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][13], (iop1 && lane_24_31); -} - -#-- RX Signal Detect Level Register (B6) -scom 0x800003B70901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][14], (iop1 && lane_24_31); -} - -#-- RX Signal Detect Level Register (B7) -scom 0x800003F70901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[1][15], (iop1 && lane_24_31); -} - -#-- TX GEN1 Coefficient Override Register (A0) -scom 0x800004100901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][0], (iop1 && lane_16_23); -} - -#-- TX GEN1 Coefficient Override Register (A1) -scom 0x800004500901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][1], (iop1 && lane_16_23); -} - -#-- TX GEN1 Coefficient Override Register (A2) -scom 0x800004900901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][2], (iop1 && lane_16_23); -} - -#-- TX GEN1 Coefficient Override Register (A3) -scom 0x800004D00901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][3], (iop1 && lane_16_23); -} - -#-- TX GEN1 Coefficient Override Register (A4) -scom 0x800005100901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][4], (iop1 && lane_16_23); -} - -#-- TX GEN1 Coefficient Override Register (A5) -scom 0x800005500901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][5], (iop1 && lane_16_23); -} - -#-- TX GEN1 Coefficient Override Register (A6) -scom 0x800005900901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][6], (iop1 && lane_16_23); -} - -#-- TX GEN1 Coefficient Override Register (A7) -scom 0x800005D00901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][7], (iop1 && lane_16_23); -} - -#-- TX GEN1 Coefficient Override Register (B0) -scom 0x800006100901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][8], (iop1 && lane_24_31); -} - -#-- TX GEN1 Coefficient Override Register (B1) -scom 0x800006500901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][9], (iop1 && lane_24_31); -} - -#-- TX GEN1 Coefficient Override Register (B2) -scom 0x800006900901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][10], (iop1 && lane_24_31); -} - -#-- TX GEN1 Coefficient Override Register (B3) -scom 0x800006D00901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][11], (iop1 && lane_24_31); -} - -#-- TX GEN1 Coefficient Override Register (B4) -scom 0x800007100901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][12], (iop1 && lane_24_31); -} - -#-- TX GEN1 Coefficient Override Register (B5) -scom 0x800007500901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][13], (iop1 && lane_24_31); -} - -#-- TX GEN1 Coefficient Override Register (B6) -scom 0x800007900901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][14], (iop1 && lane_24_31); -} - -#-- TX GEN1 Coefficient Override Register (B7) -scom 0x800007D00901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[1][15], (iop1 && lane_24_31); -} - -#-- TX GEN2 Coefficient Override Register (A0) -scom 0x800004110901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][0], (iop1 && lane_16_23); -} - -#-- TX GEN2 Coefficient Override Register (A1) -scom 0x800004510901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][1], (iop1 && lane_16_23); -} - -#-- TX GEN2 Coefficient Override Register (A2) -scom 0x800004910901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][2], (iop1 && lane_16_23); -} - -#-- TX GEN2 Coefficient Override Register (A3) -scom 0x800004D10901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][3], (iop1 && lane_16_23); -} - -#-- TX GEN2 Coefficient Override Register (A4) -scom 0x800005110901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][4], (iop1 && lane_16_23); -} - -#-- TX GEN2 Coefficient Override Register (A5) -scom 0x800005510901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][5], (iop1 && lane_16_23); -} - -#-- TX GEN2 Coefficient Override Register (A6) -scom 0x800005910901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][6], (iop1 && lane_16_23); -} - -#-- TX GEN2 Coefficient Override Register (A7) -scom 0x800005D10901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][7], (iop1 && lane_16_23); -} - -#-- TX GEN2 Coefficient Override Register (B0) -scom 0x800006110901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][8], (iop1 && lane_24_31); -} - -#-- TX GEN2 Coefficient Override Register (B1) -scom 0x800006510901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][9], (iop1 && lane_24_31); -} - -#-- TX GEN2 Coefficient Override Register (B2) -scom 0x800006910901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][10], (iop1 && lane_24_31); -} - -#-- TX GEN2 Coefficient Override Register (B3) -scom 0x800006D10901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][11], (iop1 && lane_24_31); -} - -#-- TX GEN1 Coefficient Override Register (B4) -scom 0x800007110901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][12], (iop1 && lane_24_31); -} - -#-- TX GEN2 Coefficient Override Register (B5) -scom 0x800007510901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][13], (iop1 && lane_24_31); -} - -#-- TX GEN2 Coefficient Override Register (B6) -scom 0x800007910901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][14], (iop1 && lane_24_31); -} - -#-- TX GEN2 Coefficient Override Register (B7) -scom 0x800007D10901187F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[1][15], (iop1 && lane_24_31); -} - -#-- RX Phase Rotator Flywheel Control Register (A0) -scom 0x8000002F0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_16_23); -} - -#-- RX Phase Rotator Flywheel Control Register (A1) -scom 0x8000006F0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_16_23); -} - -#-- RX Phase Rotator Flywheel Control Register (A2) -scom 0x800000AF0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_16_23); -} - -#-- RX Phase Rotator Flywheel Control Register (A3) -scom 0x800000EF0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_16_23); -} - -#-- RX Phase Rotator Flywheel Control Register (A4) -scom 0x8000012F0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_16_23); -} - -#-- RX Phase Rotator Flywheel Control Register (A5) -scom 0x8000016F0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_16_23); -} - -#-- RX Phase Rotator Flywheel Control Register (A6) -scom 0x800001AF0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_16_23); -} - -#-- RX Phase Rotator Flywheel Control Register (A7) -scom 0x800001EF0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_16_23); -} - -#-- RX Phase Rotator Flywheel Control Register (B0) -scom 0x8000022F0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_24_31); -} - -#-- RX Phase Rotator Flywheel Control Register (B1) -scom 0x8000026F0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_24_31); -} - -#-- RX Phase Rotator Flywheel Control Register (B2) -scom 0x800002AF0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_24_31); -} - -#-- RX Phase Rotator Flywheel Control Register (B3) -scom 0x800002EF0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_24_31); -} - -#-- RX Phase Rotator Flywheel Control Register (B4) -scom 0x8000032F0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_24_31); -} - -#-- RX Phase Rotator Flywheel Control Register (B5) -scom 0x8000036F0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_24_31); -} - -#-- RX Phase Rotator Flywheel Control Register (B6) -scom 0x800003AF0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_24_31); -} - -#-- RX Phase Rotator Flywheel Control Register (B7) -scom 0x800003EF0901187F { - bits, scom_data, expr; - 56:59, 0b1110, (iop1 && lane_24_31); -} - -#-- DFE Function Control Register 1 (A0) -scom 0x8000001F0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_16_23); -} - -#-- DFE Function Control Register 1 (A1) -scom 0x8000005F0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_16_23); -} - -#-- DFE Function Control Register 1 (A2) -scom 0x8000009F0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_16_23); -} - -#-- DFE Function Control Register 1 (A3) -scom 0x800000DF0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_16_23); -} - -#-- DFE Function Control Register 1 (A4) -scom 0x8000011F0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_16_23); -} - -#-- DFE Function Control Register 1 (A5) -scom 0x8000015F0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_16_23); -} - -#-- DFE Function Control Register 1 (A6) -scom 0x8000019F0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_16_23); -} - -#-- DFE Function Control Register 1 (A7) -scom 0x800001DF0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_16_23); -} - -#-- DFE Function Control Register 1 (B0) -scom 0x8000021F0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_24_31); -} - -#-- DFE Function Control Register 1 (B1) -scom 0x8000025F0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_24_31); -} - -#-- DFE Function Control Register 1 (B2) -scom 0x8000029F0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_24_31); -} - -#-- DFE Function Control Register 1 (B3) -scom 0x800002DF0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_24_31); -} - -#-- DFE Function Control Register 1 (B4) -scom 0x8000031F0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_24_31); -} - -#-- DFE Function Control Register 1 (B5) -scom 0x8000035F0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_24_31); -} - -#-- DFE Function Control Register 1 (B6) -scom 0x8000039F0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_24_31); -} - -#-- DFE Function Control Register 1 (B7) -scom 0x800003DF0901187F { - bits, scom_data, expr; - 49, 0b0, (iop1 && lane_24_31); -} - -#-- Receiver Configuration Mode Register (A0) -scom 0x800000000901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_16_23); -} - -#-- Receiver Configuration Mode Register (A1) -scom 0x800000400901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_16_23); -} - -#-- Receiver Configuration Mode Register (A2) -scom 0x800000800901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_16_23); -} - -#-- Receiver Configuration Mode Register (A3) -scom 0x800000C00901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_16_23); -} - -#-- Receiver Configuration Mode Register (A4) -scom 0x800001000901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_16_23); -} - -#-- Receiver Configuration Mode Register (A5) -scom 0x800001400901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_16_23); -} - -#-- Receiver Configuration Mode Register (A6) -scom 0x800001800901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_16_23); -} - -#-- Receiver Configuration Mode Register (A7) -scom 0x800001C00901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_16_23); -} - -#-- Receiver Configuration Mode Register (B0) -scom 0x800002000901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_24_31); -} - -#-- Receiver Configuration Mode Register (B1) -scom 0x800002400901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_24_31); -} - -#-- Receiver Configuration Mode Register (B2) -scom 0x800002800901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_24_31); -} - -#-- Receiver Configuration Mode Register (B3) -scom 0x800002C00901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_24_31); -} - -#-- Receiver Configuration Mode Register (B4) -scom 0x800003000901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_24_31); -} - -#-- Receiver Configuration Mode Register (B5) -scom 0x800003400901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_24_31); -} - -#-- Receiver Configuration Mode Register (B6) -scom 0x800003800901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_24_31); -} - -#-- Receiver Configuration Mode Register (B7) -scom 0x800003C00901187F { - bits, scom_data, expr; - 49, 0b1, (iop1 && lane_24_31); -} - -#-- ZCAL Control Register -scom 0x800008400901187F { - bits, scom_data, expr; - 53:60, ATTR_PROC_PCIE_IOP_ZCAL_CONTROL[1], (iop1); -} - -#-- ZCAL Override Register -scom 0x800008420901187F { - bits, scom_data, expr; - 48:63, 0xEC30, (iop1 && zcal_override); -} - - -#-- -#-- IOP 2 -#-- - -#-- IOP PLL FIR Action0 Register -scom 0x09011C46 { - bits, scom_data, expr; - 0:63, 0x0000000000000000, (iop2); -} - -#-- IOP PLL FIR Action1 Register -scom 0x09011C47 { - bits, scom_data, expr; - 0:63, 0xFF00000000000000, (iop2); -} - -#-- IOP PLL FIR Mask Register -scom 0x09011C43 { - bits, scom_data, expr; - 0:63, 0xFF80000000000000, (iop2); -} - -#-- G3 PLL Control Register 0 -scom 0x8000080109011C7F { - bits, scom_data, expr; - 51:63, ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0[2], (iop2); -} - -#-- G2 PLL Control Register 0 -scom 0x8000080509011C7F { - bits, scom_data, expr; - 51:63, ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0[2], (iop2); -} - -#-- PLL Global Control Register 0 -scom 0x8000080809011C7F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0[2], (iop2); -} - -#-- PLL Global Control Register 1 -scom 0x8000080909011C7F { - bits, scom_data, expr; - 51:63, ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1[2], (iop2); -} - -#-- PCS Control Register 0 -scom 0x8000088009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL0[2], (iop2); -} - -#-- PCS Control Register 1 -scom 0x8000088109011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_PCS_CONTROL1[2], (iop2); -} - -#-- TX FIFO Control Register (A0) -scom 0x8000040009011C7F { - bits, scom_data, expr; - 53:56, 0b1111, (iop2 && lane_32_40); -} - -#-- TX FIFO Control Register (A1) -scom 0x8000044009011C7F { - bits, scom_data, expr; - 53:56, 0b1111, (iop2 && lane_32_40); -} - -#-- TX FIFO Control Register (A2) -scom 0x8000048009011C7F { - bits, scom_data, expr; - 53:56, 0b1111, (iop2 && lane_32_40); -} - -#-- TX FIFO Control Register (A3) -scom 0x800004C009011C7F { - bits, scom_data, expr; - 53:56, 0b1111, (iop2 && lane_32_40); -} - -#-- TX FIFO Control Register (A4) -scom 0x8000050009011C7F { - bits, scom_data, expr; - 53:56, 0b1111, (iop2 && lane_32_40); -} - -#-- TX FIFO Control Register (A5) -scom 0x8000054009011C7F { - bits, scom_data, expr; - 53:56, 0b1111, (iop2 && lane_32_40); -} - -#-- TX FIFO Control Register (A6) -scom 0x8000058009011C7F { - bits, scom_data, expr; - 53:56, 0b1111, (iop2 && lane_32_40); -} - -#-- TX FIFO Control Register (A7) -scom 0x800005C009011C7F { - bits, scom_data, expr; - 53:56, 0b1111, (iop2 && lane_32_40); -} - -#-- TX FIFO Offset Register (A0) -scom 0x8000040109011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][0], (iop2 && lane_32_40); -} - -#-- TX FIFO Offset Register (A1) -scom 0x8000044109011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][1], (iop2 && lane_32_40); -} - -#-- TX FIFO Offset Register (A2) -scom 0x8000048109011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][2], (iop2 && lane_32_40); -} - -#-- TX FIFO Offset Register (A3) -scom 0x800004C109011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][3], (iop2 && lane_32_40); -} - -#-- TX FIFO Offset Register (A4) -scom 0x8000050109011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][4], (iop2 && lane_32_40); -} - -#-- TX FIFO Offset Register (A5) -scom 0x8000054109011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][5], (iop2 && lane_32_40); -} - -#-- TX FIFO Offset Register (A6) -scom 0x8000058109011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][6], (iop2 && lane_32_40); -} - -#-- TX FIFO Offset Register (A7) -scom 0x800005C109011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET[2][7], (iop2 && lane_32_40); -} - -#-- TX Receiver Detect Control Register (A0) -scom 0x8000040209011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][0], (iop2 && lane_32_40); -} - -#-- TX Receiver Detect Control Register (A1) -scom 0x8000044209011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][1], (iop2 && lane_32_40); -} - -#-- TX Receiver Detect Control Register (A2) -scom 0x8000048209011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][2], (iop2 && lane_32_40); -} - -#-- TX Receiver Detect Control Register (A3) -scom 0x800004C209011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][3], (iop2 && lane_32_40); -} - -#-- TX Receiver Detect Control Register (A4) -scom 0x8000050209011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][4], (iop2 && lane_32_40); -} - -#-- TX Receiver Detect Control Register (A5) -scom 0x8000054209011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][5], (iop2 && lane_32_40); -} - -#-- TX Receiver Detect Control Register (A6) -scom 0x8000058209011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][6], (iop2 && lane_32_40); -} - -#-- TX Receiver Detect Control Register (A7) -scom 0x800005C209011C7F { - bits, scom_data, expr; - 49:63, ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL[2][7], (iop2 && lane_32_40); -} - -#-- TX Bandwidth Loss Coefficient Register (A0) -scom 0x8000041B09011C7F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][0], (iop2 && lane_32_40); -} - -#-- TX Bandwidth Loss Coefficient Register (A1) -scom 0x8000045B09011C7F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][1], (iop2 && lane_32_40); -} - -#-- TX Bandwidth Loss Coefficient Register (A2) -scom 0x8000049B09011C7F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][2], (iop2 && lane_32_40); -} - -#-- TX Bandwidth Loss Coefficient Register (A3) -scom 0x800004DB09011C7F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][3], (iop2 && lane_32_40); -} - -#-- TX Bandwidth Loss Coefficient Register (A4) -scom 0x8000051B09011C7F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][4], (iop2 && lane_32_40); -} - -#-- TX Bandwidth Loss Coefficient Register (A5) -scom 0x8000055B09011C7F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][5], (iop2 && lane_32_40); -} - -#-- TX Bandwidth Loss Coefficient Register (A6) -scom 0x8000059B09011C7F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][6], (iop2 && lane_32_40); -} - -#-- TX Bandwidth Loss Coefficient Register (A7) -scom 0x800005DB09011C7F { - bits, scom_data, expr; - 52:63, ATTR_PROC_PCIE_IOP_TX_BWLOSS1[2][7], (iop2 && lane_32_40); -} - -#-- RX VGA Control Register2 (A0) -scom 0x8000000C09011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][0], (iop2 && lane_32_40); -} - -#-- RX VGA Control Register2 (A1) -scom 0x8000004C09011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][1], (iop2 && lane_32_40); -} - -#-- RX VGA Control Register2 (A2) -scom 0x8000008C09011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][2], (iop2 && lane_32_40); -} - -#-- RX VGA Control Register2 (A3) -scom 0x800000CC09011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][3], (iop2 && lane_32_40); -} - -#-- RX VGA Control Register2 (A4) -scom 0x8000010C09011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][4], (iop2 && lane_32_40); -} - -#-- RX VGA Control Register2 (A5) -scom 0x8000014C09011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][5], (iop2 && lane_32_40); -} - -#-- RX VGA Control Register2 (A6) -scom 0x8000018C09011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][6], (iop2 && lane_32_40); -} - -#-- RX VGA Control Register2 (A7) -scom 0x800001CC09011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2[2][7], (iop2 && lane_32_40); -} - -#-- RX Receiver Peaking Register (A0) -scom 0x8000001009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][0], (iop2 && lane_32_40); -} - -#-- RX Receiver Peaking Register (A1) -scom 0x8000005009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][1], (iop2 && lane_32_40); -} - -#-- RX Receiver Peaking Register (A2) -scom 0x8000009009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][2], (iop2 && lane_32_40); -} - -#-- RX Receiver Peaking Register (A3) -scom 0x800000D009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][3], (iop2 && lane_32_40); -} - -#-- RX Receiver Peaking Register (A4) -scom 0x8000011009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][4], (iop2 && lane_32_40); -} - -#-- RX Receiver Peaking Register (A5) -scom 0x8000015009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][5], (iop2 && lane_32_40); -} - -#-- RX Receiver Peaking Register (A6) -scom 0x8000019009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][6], (iop2 && lane_32_40); -} - -#-- RX Receiver Peaking Register (A7) -scom 0x800001D009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_PEAK[2][7], (iop2 && lane_32_40); -} - -#-- RX Signal Detect Level Register (A0) -scom 0x8000003709011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][0], (iop2 && lane_32_40); -} - -#-- RX Signal Detect Level Register (A1) -scom 0x8000007709011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][1], (iop2 && lane_32_40); -} - -#-- RX Signal Detect Level Register (A2) -scom 0x800000B709011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][2], (iop2 && lane_32_40); -} - -#-- RX Signal Detect Level Register (A3) -scom 0x800000F709011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][3], (iop2 && lane_32_40); -} - -#-- RX Signal Detect Level Register (A4) -scom 0x8000013709011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][4], (iop2 && lane_32_40); -} - -#-- RX Signal Detect Level Register (A5) -scom 0x8000017709011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][5], (iop2 && lane_32_40); -} - -#-- RX Signal Detect Level Register (A6) -scom 0x800001B709011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][6], (iop2 && lane_32_40); -} - -#-- RX Signal Detect Level Register (A7) -scom 0x800001F709011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_RX_SDL[2][7], (iop2 && lane_32_40); -} - -#-- TX GEN1 Coefficient Override Register (A0) -scom 0x8000041009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][0], (iop2 && lane_32_40); -} - -#-- TX GEN1 Coefficient Override Register (A1) -scom 0x8000045009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][1], (iop2 && lane_32_40); -} - -#-- TX GEN1 Coefficient Override Register (A2) -scom 0x8000049009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][2], (iop2 && lane_32_40); -} - -#-- TX GEN1 Coefficient Override Register (A3) -scom 0x800004D009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][3], (iop2 && lane_32_40); -} - -#-- TX GEN1 Coefficient Override Register (A4) -scom 0x8000051009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][4], (iop2 && lane_32_40); -} - -#-- TX GEN1 Coefficient Override Register (A5) -scom 0x8000055009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][5], (iop2 && lane_32_40); -} - -#-- TX GEN1 Coefficient Override Register (A6) -scom 0x8000059009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][6], (iop2 && lane_32_40); -} - -#-- TX GEN1 Coefficient Override Register (A7) -scom 0x800005D009011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN1[2][7], (iop2 && lane_32_40); -} - -#-- TX GEN2 Coefficient Override Register (A0) -scom 0x8000041109011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][0], (iop2 && lane_32_40); -} - -#-- TX GEN2 Coefficient Override Register (A1) -scom 0x8000045109011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][1], (iop2 && lane_32_40); -} - -#-- TX GEN2 Coefficient Override Register (A2) -scom 0x8000049109011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][2], (iop2 && lane_32_40); -} - -#-- TX GEN2 Coefficient Override Register (A3) -scom 0x800004D109011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][3], (iop2 && lane_32_40); -} - -#-- TX GEN2 Coefficient Override Register (A4) -scom 0x8000051109011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][4], (iop2 && lane_32_40); -} - -#-- TX GEN2 Coefficient Override Register (A5) -scom 0x8000055109011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][5], (iop2 && lane_32_40); -} - -#-- TX GEN2 Coefficient Override Register (A6) -scom 0x8000059109011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][6], (iop2 && lane_32_40); -} - -#-- TX GEN2 Coefficient Override Register (A7) -scom 0x800005D109011C7F { - bits, scom_data, expr; - 48:63, ATTR_PROC_PCIE_IOP_TX_FFE_GEN2[2][7], (iop2 && lane_32_40); -} - -#-- RX Phase Rotator Flywheel Control Register (A0) -scom 0x8000002F09011C7F { - bits, scom_data, expr; - 56:59, 0b1110, (iop2 && lane_32_40); -} - -#-- RX Phase Rotator Flywheel Control Register (A1) -scom 0x8000006F09011C7F { - bits, scom_data, expr; - 56:59, 0b1110, (iop2 && lane_32_40); -} - -#-- RX Phase Rotator Flywheel Control Register (A2) -scom 0x800000AF09011C7F { - bits, scom_data, expr; - 56:59, 0b1110, (iop2 && lane_32_40); -} - -#-- RX Phase Rotator Flywheel Control Register (A3) -scom 0x800000EF09011C7F { - bits, scom_data, expr; - 56:59, 0b1110, (iop2 && lane_32_40); -} - -#-- RX Phase Rotator Flywheel Control Register (A4) -scom 0x8000012F09011C7F { - bits, scom_data, expr; - 56:59, 0b1110, (iop2 && lane_32_40); -} - -#-- RX Phase Rotator Flywheel Control Register (A5) -scom 0x8000016F09011C7F { - bits, scom_data, expr; - 56:59, 0b1110, (iop2 && lane_32_40); -} - -#-- RX Phase Rotator Flywheel Control Register (A6) -scom 0x800001AF09011C7F { - bits, scom_data, expr; - 56:59, 0b1110, (iop2 && lane_32_40); -} - -#-- RX Phase Rotator Flywheel Control Register (A7) -scom 0x800001EF09011C7F { - bits, scom_data, expr; - 56:59, 0b1110, (iop2 && lane_32_40); -} - -#-- DFE Function Control Register 1 (A0) -scom 0x8000001F09011C7F { - bits, scom_data, expr; - 49, 0b0, (iop2 && lane_32_40); -} - -#-- DFE Function Control Register 1 (A1) -scom 0x8000005F09011C7F { - bits, scom_data, expr; - 49, 0b0, (iop2 && lane_32_40); -} - -#-- DFE Function Control Register 1 (A2) -scom 0x8000009F09011C7F { - bits, scom_data, expr; - 49, 0b0, (iop2 && lane_32_40); -} - -#-- DFE Function Control Register 1 (A3) -scom 0x800000DF09011C7F { - bits, scom_data, expr; - 49, 0b0, (iop2 && lane_32_40); -} - -#-- DFE Function Control Register 1 (A4) -scom 0x8000011F09011C7F { - bits, scom_data, expr; - 49, 0b0, (iop2 && lane_32_40); -} - -#-- DFE Function Control Register 1 (A5) -scom 0x8000015F09011C7F { - bits, scom_data, expr; - 49, 0b0, (iop2 && lane_32_40); -} - -#-- DFE Function Control Register 1 (A6) -scom 0x8000019F09011C7F { - bits, scom_data, expr; - 49, 0b0, (iop2 && lane_32_40); -} - -#-- DFE Function Control Register 1 (A7) -scom 0x800001DF09011C7F { - bits, scom_data, expr; - 49, 0b0, (iop2 && lane_32_40); -} - -#-- Receiver Configuration Mode Register (A0) -scom 0x8000000009011C7F { - bits, scom_data, expr; - 49, 0b1, (iop2 && lane_32_40); -} - -#-- Receiver Configuration Mode Register (A1) -scom 0x8000004009011C7F { - bits, scom_data, expr; - 49, 0b1, (iop2 && lane_32_40); -} - -#-- Receiver Configuration Mode Register (A2) -scom 0x8000008009011C7F { - bits, scom_data, expr; - 49, 0b1, (iop2 && lane_32_40); -} - -#-- Receiver Configuration Mode Register (A3) -scom 0x800000C009011C7F { - bits, scom_data, expr; - 49, 0b1, (iop2 && lane_32_40); -} - -#-- Receiver Configuration Mode Register (A4) -scom 0x8000010009011C7F { - bits, scom_data, expr; - 49, 0b1, (iop2 && lane_32_40); -} - -#-- Receiver Configuration Mode Register (A5) -scom 0x8000014009011C7F { - bits, scom_data, expr; - 49, 0b1, (iop2 && lane_32_40); -} - -#-- Receiver Configuration Mode Register (A6) -scom 0x8000018009011C7F { - bits, scom_data, expr; - 49, 0b1, (iop2 && lane_32_40); -} - -#-- Receiver Configuration Mode Register (A7) -scom 0x800001C009011C7F { - bits, scom_data, expr; - 49, 0b1, (iop2 && lane_32_40); -} - -#-- ZCAL Control Register -scom 0x8000084009011C7F { - bits, scom_data, expr; - 53:60, ATTR_PROC_PCIE_IOP_ZCAL_CONTROL[2], (iop2); -} - -#-- ZCAL Override Register -scom 0x8000084209011C7F { - bits, scom_data, expr; - 48:63, 0xEC30, (iop2 && zcal_override); -} diff --git a/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile deleted file mode 100644 index 86a0b0b27..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile +++ /dev/null @@ -1,202 +0,0 @@ -#-- $Id: p8.pe.phase2.scom.initfile,v 1.8 2015/06/11 20:32:23 ricmata Exp $ -#------------------------------------------------------------------------------- -#-- -#-- (C) Copyright International Business Machines Corp. 2011 -#-- All Rights Reserved -- Property of IBM -#-- *** *** -#-- -#-- TITLE : p8.pcie.phase2.scom.initfile -#-- DESCRIPTION : Perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-17) -#-- -#-- OWNER NAME : Joe McDonald Email: joemc@us.ibm.com -#-- OWNER NAME : Rick Mata Email: ricmata@us.ibm.com -#-- -#-------------------------------------------------------------------------------- - -SyntaxVersion = 1 - -#-------------------------------------------------------------------------------- -#-- Includes -#-------------------------------------------------------------------------------- - -#-------------------------------------------------------------------------------- -#-- Defines -#-------------------------------------------------------------------------------- - -define phb0 = (ATTR_PROC_PCIE_NUM_PHB >= 1); -define phb1 = (ATTR_PROC_PCIE_NUM_PHB >= 2); -define phb2 = (ATTR_PROC_PCIE_NUM_PHB >= 3); -define phb3 = (ATTR_PROC_PCIE_NUM_PHB >= 4); - -define def_nest_freq_r0 = (SYS.ATTR_FREQ_PB >= 2200); -define def_nest_freq_r1 = ((SYS.ATTR_FREQ_PB <= 1700) && (SYS.ATTR_FREQ_PB < 2200)); -define def_nest_freq_r2 = (SYS.ATTR_FREQ_PB < 1700); - -define enable_enh_ive_ordering = (ATTR_CHIP_EC_FEATURE_ENABLE_IVE_PERFORMANCE_ORDERING != 0); -define enable_dmar_ooo = (ATTR_CHIP_EC_FEATURE_ENABLE_PCI_DMAR_OOO != 0); - - -#-------------------------------------------------------------------------------- -#-- SCOM initializations -#-------------------------------------------------------------------------------- - -#-- PBCQ Mode Control Register -scom 0x0201200B { - bits, scom_data, expr; - 6:7, 0b00, (phb0); #-- disable wr-cache-inject mode for TCPIP performance (SW275459) - 12, 0b1, (phb0); #-- disable group scope on TCE read requests - 26, 0b1, (phb0 && enable_enh_ive_ordering); #-- enable enhanced IVE performance ordering only where supported (HW226407) - 27, 0b1, (phb0); #-- force IVE write operations to system scope -} - -scom 0x0201240B { - bits, scom_data, expr; - 6:7, 0b00, (phb1); - 12, 0b1, (phb1); - 26, 0b1, (phb1 && enable_enh_ive_ordering); - 27, 0b1, (phb1); -} - -scom 0x0201280B { - bits, scom_data, expr; - 6:7, 0b00, (phb2); - 12, 0b1, (phb2); - 26, 0b1, (phb2 && enable_enh_ive_ordering); - 27, 0b1, (phb2); -} - -scom 0x02012C0B { - bits, scom_data, expr; - 6:7, 0b00, (phb3); - 12, 0b1, (phb3); - 26, 0b1, (phb3 && enable_enh_ive_ordering); - 27, 0b1, (phb3); -} - -#-- PCI Hardware Configuration 0 Register -scom 0x02012018 { - bits, scom_data, expr; - 0:3, 0b0001, (phb0); #-- hang poll scale (reg=1, value of 6) - 4:7, 0b0010, (phb0); #-- data poll scale (reg=2, value of 9) - 8:11, 0b0001, (phb0); #-- data poll scale (PE) (reg=1, value of 6) - 17, 0b1, (phb0); #-- disable out-of-order store behavior -} - -scom 0x02012418 { - bits, scom_data, expr; - 0:3, 0b0001, (phb1); - 4:7, 0b0010, (phb1); - 8:11, 0b0001, (phb1); - 17, 0b1, (phb1); -} - -scom 0x02012818 { - bits, scom_data, expr; - 0:3, 0b0001, (phb2); - 4:7, 0b0010, (phb2); - 8:11, 0b0001, (phb2); - 17, 0b1, (phb2); -} - -scom 0x02012C18 { - bits, scom_data, expr; - 0:3, 0b0001, (phb3); - 4:7, 0b0010, (phb3); - 8:11, 0b0001, (phb3); - 17, 0b1, (phb3); -} - -#-- PCI Hardware Configuration 1 Register -scom 0x02012019 { - bits, scom_data, expr; - 22, 0b0, (phb0); #-- diable OOO DMA read -} - -scom 0x02012419 { - bits, scom_data, expr; - 22, 0b0, (phb1); -} - -scom 0x02012819 { - bits, scom_data, expr; - 22, 0b0, (phb2); -} - -scom 0x02012C19 { - bits, scom_data, expr; - 22, 0b0, (phb3); -} - -#-- PCI Nest Clock Trace Control Register -scom 0x0201200D { - bits, scom_data, expr; - 0:3, 0b1001, (phb0); #-- enable trace, select inbound + address info -} - -scom 0x0201240D { - bits, scom_data, expr; - 0:3, 0b1001, (phb1); -} - -scom 0x0201280D { - bits, scom_data, expr; - 0:3, 0b1001, (phb2); -} - -scom 0x02012C0D { - bits, scom_data, expr; - 0:3, 0b1001, (phb3); -} - -#-- PB AIB Control/Status Register -scom 0x0901200F { - bits, scom_data, expr; - 0:2, 0b011, (phb0 && def_nest_freq_r0); #-- Maximum Ch0 command credit given to ETU - 0:2, 0b010, (phb0 && def_nest_freq_r1); - 0:2, 0b001, (phb0 && def_nest_freq_r2); - 3:5, 0b001, (phb0); #-- Maximum Ch1 command credit given to ETU - 6:8, 0b011, (phb0 && def_nest_freq_r0); #-- Maximum Ch2 command credit given to ETU - 6:8, 0b010, (phb0 && (def_nest_freq_r1 || def_nest_freq_r2)); - 9:11, 0b000, (phb0); #-- Maximum Ch3 command credit given to ETU - 12:13, 0b11, (phb0); #-- Overcommit of inbound speed matching buffer (HW245629) - 30:31, 0b11, (phb0); #-- enable PCI clock tracing w/ ETU as default -} - -scom 0x0901240F { - bits, scom_data, expr; - 0:2, 0b011, (phb1 && def_nest_freq_r0); - 0:2, 0b010, (phb1 && def_nest_freq_r1); - 0:2, 0b001, (phb1 && def_nest_freq_r2); - 3:5, 0b001, (phb1); - 6:8, 0b011, (phb1 && def_nest_freq_r0); - 6:8, 0b010, (phb1 && (def_nest_freq_r1 || def_nest_freq_r2)); - 9:11, 0b000, (phb1); - 12:13, 0b11, (phb1); - 30:31, 0b11, (phb1); -} - -scom 0x0901280F { - bits, scom_data, expr; - 0:2, 0b011, (phb2 && def_nest_freq_r0); - 0:2, 0b010, (phb2 && def_nest_freq_r1); - 0:2, 0b001, (phb2 && def_nest_freq_r2); - 3:5, 0b001, (phb2); - 6:8, 0b011, (phb2 && def_nest_freq_r0); - 6:8, 0b010, (phb2 && (def_nest_freq_r1 || def_nest_freq_r2)); - 9:11, 0b000, (phb2); - 12:13, 0b11, (phb2); - 30:31, 0b11, (phb2); -} - -scom 0x09012C0F { - bits, scom_data, expr; - 0:2, 0b011, (phb3 && def_nest_freq_r0); - 0:2, 0b010, (phb3 && def_nest_freq_r1); - 0:2, 0b001, (phb3 && def_nest_freq_r2); - 3:5, 0b001, (phb3); - 6:8, 0b011, (phb3 && def_nest_freq_r0); - 6:8, 0b010, (phb3 && (def_nest_freq_r1 || def_nest_freq_r2)); - 9:11, 0b000, (phb3); - 12:13, 0b11, (phb3); - 30:31, 0b11, (phb3); -} diff --git a/src/usr/hwpf/hwp/initfiles/p8.psi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.psi.scom.initfile deleted file mode 100644 index d291f3cfb..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.psi.scom.initfile +++ /dev/null @@ -1,50 +0,0 @@ -#-- $Id: p8.psi.scom.initfile,v 1.6 2014/04/23 13:47:41 jmcgill Exp $ -#------------------------------------------------------------------------------- -#-- -#-- (C) Copyright International Business Machines Corp. 2011 -#-- All Rights Reserved -- Property of IBM -#-- *** *** -#-- -#-- TITLE : p8.psi.scom.initfile -#-- DESCRIPTION : Perform PSI configuration -#-- -#-- OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -#-- -#-------------------------------------------------------------------------------- - -SyntaxVersion = 1 - -#-------------------------------------------------------------------------------- -#-- Includes -#-------------------------------------------------------------------------------- - - -#-------------------------------------------------------------------------------- -#-- SCOM initializations -#-------------------------------------------------------------------------------- - -# PSI Host Bridge Error Mask Register -scom 0x0201090F { - bits, scom_data; - 16:27, 0x000; - 48:52, 0b00000; -} - -# PSI Host Bridge FIR Action0 Register -scom 0x02010906 { - bits, scom_data; - 0:63, 0x0000000000000000; -} - -# PSI Host Bridge FIR Action1 Register -scom 0x02010907 { - bits, scom_data; - 0:63, 0xC629000000000000; -} - -# PSI Host Bridge FIR Mask Register -scom 0x02010903 { - bits, scom_data; - 0:63, 0x3902FFF800000000; -} - diff --git a/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile deleted file mode 100644 index 782a6deb1..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile +++ /dev/null @@ -1,113 +0,0 @@ -#-- $Id: p8.tpbridge.scom.initfile,v 1.9 2014/08/12 14:44:26 jmcgill Exp $ -#------------------------------------------------------------------------------- -#-- -#-- (C) Copyright International Business Machines Corp. 2011 -#-- All Rights Reserved -- Property of IBM -#-- *** *** -#-- -#-- TITLE : p8.tpbridge.scom.initfile -#-- DESCRIPTION : Perform SCOM configuration for TP bridge units -#-- -#-- OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -#-- -#-------------------------------------------------------------------------------- - -SyntaxVersion = 1 - -#-------------------------------------------------------------------------------- -#-- Includes -#-------------------------------------------------------------------------------- - - -#-------------------------------------------------------------------------------- -#-- HTM SCOM initializations -#-------------------------------------------------------------------------------- - -# HTM Configuration Register -scom 0x02010888 { - bits, scom_data; - 0:4, 0b00001; # oper hang divider = 1 -} - - -#-------------------------------------------------------------------------------- -#-- ICP SCOM initializations -#-------------------------------------------------------------------------------- - -# ICP Mode Register 0 -scom 0x020109CB { - bits, scom_data; - 15:19, 0b00001; # oper hang divider = 1 - 23:27, 0b00011; # data hang divider = 3 -} - -# ICP FIR Register initializations - -# EN.TPC.INTP.SYNC_FIR_ACTION0_REG -scom 0x020109C6 { - bits, scom_data; - 0:63, 0x0000000000000000; -} - -# EN.TPC.INTP.SYNC_FIR_ACTION1_REG -scom 0x020109C7 { - bits, scom_data; - 0:63, 0xF7E00DFFB0000000; -} - -# EN.TPC.INTP.SYNC_FIR_MASK_REG -scom 0x020109C3 { - bits, scom_data; - 0:63, 0x081FF2004C000000; -} - - -#-------------------------------------------------------------------------------- -#-- HCA SCOM initializations -#-------------------------------------------------------------------------------- - -# HCA Mode Register -scom 0x0201094F { - bits, scom_data, expr; - 16:20, 0b00011, (ATTR_CHIP_EC_FEATURE_HCA_SPLIT_HANG_CONTROL == 0); # oper/data hang divider = 3 (HW242836) - 16:20, 0b00001, (ATTR_CHIP_EC_FEATURE_HCA_SPLIT_HANG_CONTROL != 0); # oper hang divider = 1 (HW242836) - 30:34, 0b00011, (ATTR_CHIP_EC_FEATURE_HCA_SPLIT_HANG_CONTROL != 0); # data hang divider = 3 (HW242836) -} - -# HCA FIR Register initializations - -# EH.FIR ACTION0 -scom 0x02010986 { - bits, scom_data; - 0:63, 0x0000000000000000; -} - -# EH FIR ACTION1 -scom 0x02010987 { - bits, scom_data; - 0:63, 0x3333333300000000; -} - -# EH FIR MASK -scom 0x02010983 { - bits, scom_data; - 0:63, 0xCCCCCCCCF0000000; -} - -# EN FIR ACTION0 -scom 0x02010946 { - bits, scom_data; - 0:63, 0x0000000000000000; -} - -# EN FIR ACTION1 -scom 0x02010947 { - bits, scom_data; - 0:63, 0xE000000000000000; -} - -# EN FIR MASK -scom 0x02010943 { - bits, scom_data; - 0:63, 0x5FC0000000000000; -} diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile deleted file mode 100644 index 2c47e5754..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile +++ /dev/null @@ -1,188 +0,0 @@ -#-- $Id: p8.xbus.custom.scom.initfile,v 1.11 2015/04/13 16:17:02 jgrell Exp $ -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -#-- 1.11|jgrell |04/25/15|Updated attribute to system type at Thi's request so it can be applied to Brazos only. (SW299500) -#-- 1.10|jmcgill |03/24/15|remove l2u delay settings,given filter bypass soln (SW299659) -#-- 1.9 |jgrell |02/25/15|Added rx_fifo_final_l2u_dly for Venice only (SW296793) -#-- 1.8 |garyp |02/19/14|Added rx_min_eye_width for manufacturing and lab thresholding -#-- 1.7 |jgrell |12/03/13|Set rx_sls_extend_sel to 001 for DD2 -#-- 1.5 |jgrell |09/17/13|Added DD2 specific inits -#-- 1.3 |jgrell |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab. -#-- 1.2 |thomsen |02/13/13|Cleaned up and Added Commented-out Lane Power Ups -#-- | | |Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab. -#-- 1.1 |thomsen |01/29/13|Created initial version -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- -#-- TARGETS: -#-- SYS. Chiplet target -#-- TGT1. Proc target -#-- TGT2. Connected Chiplet target -#-- TGT3. Connected Proc target - -#--Master list of variables that can be used in this file is at: -#--<Attribute Definition Location> - -SyntaxVersion = 1 - -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Includes -#-- Note: Must include the path to the .define file. -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -include ei4.io.define - -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Defines -#-- -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -define def_IS_HW = (SYS.ATTR_IS_SIMULATION == 0); -define def_IS_VBU = (SYS.ATTR_IS_SIMULATION == 1); - -define def_all_lanes=11111; - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -#-- Overrides -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -#--***************** -#-- set rx_min_eye_width if in manufacturing mode -#--***************** -scom 0x800.0b(rx_result_chk_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_min_eye_width, SYS.ATTR_MNFG_XBUS_MIN_EYE_WIDTH, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); -} -scom 0x800.0b(rx_result_chk_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_min_eye_width, SYS.ATTR_MNFG_XBUS_MIN_EYE_WIDTH, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); -} -scom 0x800.0b(rx_result_chk_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_min_eye_width, SYS.ATTR_MNFG_XBUS_MIN_EYE_WIDTH, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); -} -scom 0x800.0b(rx_result_chk_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_min_eye_width, SYS.ATTR_MNFG_XBUS_MIN_EYE_WIDTH, ((SYS.ATTR_MNFG_FLAGS & ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS) > 0); -} - - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -# __ ____ __ __ -# / / ____ _____ ___ / __ \____ _ _____ _____ / / / /___ -# / / / __ `/ __ \/ _ \ / /_/ / __ \ | /| / / _ \/ ___/ / / / / __ \ -# / /___/ /_/ / / / / __/ / ____/ /_/ / |/ |/ / __/ / / /_/ / /_/ / -# /_____/\__,_/_/ /_/\___/ /_/ \____/|__/|__/\___/_/ \____/ .___/ -# /_/ -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -## rx_lane_pdwn -#scom 0x800.0b(rx_mode_pl)(rx_grp0)(def_all_lanes).0x(xbus0_gcr_addr){ -# bits, scom_data; -# rx_lane_pdwn, 0b0; -#} -# -## tx_lane_pdwn -#scom 0x800.0b(tx_mode_pl)(tx_grp0)(def_all_lanes).0x(xbus0_gcr_addr){ -# bits, scom_data; -# tx_lane_pdwn, 0b0; -#} - - -#--************************************************************************************************************** -#---------------------------------------------------------------------------------------------------------------- -# Brazos Specific Inits -#---------------------------------------------------------------------------------------------------------------- -#--************************************************************************************************************** -scom 0x800.0b(rx_fifo_mode_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_fifo_final_l2u_dly, 0b0100, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; -} -scom 0x800.0b(rx_fifo_mode_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_fifo_final_l2u_dly, 0b0100, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; -} -scom 0x800.0b(rx_fifo_mode_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_fifo_final_l2u_dly, 0b0100, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; -} -scom 0x800.0b(rx_fifo_mode_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_fifo_final_l2u_dly, 0b0100, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; -} - - -#--*********************************************************************************** -#------------------------------------------------------------------------------------- -#-- DD2+ Murano & Venice -#------------------------------------------------------------------------------------- -#--*********************************************************************************** - -scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_sls_timeout_sel_dd2, 0b1010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_timeout_sel_dd2, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; -} -scom 0x800.0b(rx_timeout_sel_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_sls_timeout_sel_dd2, 0b1010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_timeout_sel_dd2, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; -} -scom 0x800.0b(rx_timeout_sel_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_sls_timeout_sel_dd2, 0b1010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_timeout_sel_dd2, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; -} -scom 0x800.0b(rx_timeout_sel_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_sls_timeout_sel_dd2, 0b1010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_timeout_sel_dd2, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; -} - -scom 0x800.0b(rx_spare_mode_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_sls_extend_sel, 0b001, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; -} -scom 0x800.0b(rx_spare_mode_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_sls_extend_sel, 0b001, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; -} -scom 0x800.0b(rx_spare_mode_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_sls_extend_sel, 0b001, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; -} -scom 0x800.0b(rx_spare_mode_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { - bits, scom_data, expr; - rx_sls_extend_sel, 0b001, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; -} - -############################################################################################ -# END OF FILE -############################################################################################ diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile deleted file mode 100644 index 2afeda314..000000000 --- a/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile +++ /dev/null @@ -1,2190 +0,0 @@ -#-- $Id: p8.xbus.scom.initfile,v 1.11 2013/05/02 21:30:11 jgrell Exp $ - - -#################################################################### -## -## Auto-genrated by fig2scominit.pl -## Based on SETUP_ID_MODE X_BUS_8B_TR_HW -## from ../../logic/mesa_sim/fusion/run/IOEPC_XBUS_WRAP.IOEPC_XBUS_WRAP.figdb -## -## Created on Thu May 2 15:52:51 CDT 2013, by jgrell -#################################################################### - -## -- CHANGE HISTORY: - ## -------------------------------------------------------------------------------- - ## -- Version:|Author: | Date: | Comment: - ## -- --------|---------|--------|------------------------------------------------- - ## -- 13050200| jgr |05-02-13| Added rx_dll_vreg_dac_pullup=1 and changed rx_dll1/2_vreg_drvcon to 111 - ## -- 13042400| jgr |04-24-13| Added rx_max_ber_check_count=3 setting - ## -- 13041300| jgr |04-13-13| Made rx dll1/dll2 vreg drv changes - ## -- smr13032500| SMR |03-25-13| Changed rx_sls_timeout_sel init to 0b110 - ## -- jgr13031300| jgr |03-13-13| Added missing entries from rel 0128 - ## -- 13030500| thomsen |03-05-13| Added DLL settings for HW241376 - ## -- 13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) - ## -- 12112700| SMR |11-27-12| HW20806: Added rx_sls_extend_sel default of 0b101 (slave side only!) - ## -- 12111300| berger |11-13-12| Updated with HW eyeopt and recal settings - ## -- 12062500| SMR |06-25-12| HW210654: Added rx_sls_timeout_sel default of 1 - ## -- 12011800| RJR |01-18-12| Added RX_CTL2_REGS FILE REFERENCES Issue HW164277 - ## -- 12010300| berger |01-03-12| HW184227: Added SETUP_ID_MODE dials - ## -- 11122000| berger |12-20-11| HW186823: removed timer settings, set in regs - ## -- 11121500| thomsen |12-15-11| Added Per-Pack GCR SCOM Addresses for Regchk (HW188381,HW182867) - ## -- | | | Removed 0x0000040000000000 from TX address definitions since it is in the lower level figtree files (HW187781,HW187893) - ## -- 11122000| berger |12-20-11| HW186823: removed timer settings, set in regs - ## -- 11121500| thomsen |12-15-11| Added Per-Pack GCR SCOM Addresses for Regchk (HW188381,HW182867) - ## -- | | | Removed 0x0000040000000000 from TX address definitions since it is in the lower level figtree files (HW187781,HW187893) - ## -- 11102100| SMR |10-21-11| HW181193: Added rx_dyn_rpr_enc_bad_data_lane_width register - ## -- 11092900| SMR |09-29-11| HW171978: Added dyn rpr error tallying defaults - ## -- 11052300| berger |05-23-11| Added ds_timeout_sel and servo timeouts - ## -- 11050300| SMR |05-02-11| Added tx_max_bad_lanes - ## -- 11041900| smc |04-19-11| Per Mike, commented out BUSCTL.BUS_CTL_REGS.base_addr (SCOM) += 0x0000000000000000; - ## -- 11022400| thomsen |02-24-11| Fixed 4-byte mode settings - ## -- 11021600| thomsen |02-16-11| Added Per-Bus, Per-Lane and Per-Group GCR SCOM addresses so Regchk would pass - ## -- 11020200| thomsen |02-02-11| Added 4 Byte Mode settings (disable all RXTX0 lanes and parts of RXTX1) and simplified RX_TX_SCRAMBLER_TAP_ID - ## -- 11020200| thomsen |02-02-11| Added RX & TX scramble/descramble tap ID settings - ## -- 11012500| berger |01-25-11| added TX lane disable and rx_bus_width fields, added missing SETUP_ID fields - ## -- 11011800| mbs |01-18-11| Added "*_GEN." to group hierarchy - ## -- 11010700| berger |01-07-11| added lane disable and max bad lane - ## -- 10121600| thomsen |12-16-10| Added RX_FENCE - ## -- 10120800| thomsen |12-08-10| Added TX_BUS_WIDTH - ## -- 10120100| thomsen |12-01-10| Fixed typo - ## -- 10112900| thomsen |11-29-10| Fixed BUS_ID's and GROUP_ID's for TX - ## -- 10102600| thomsen |10-26-10| Initial version - ## -------------------------------------------------------------------------------- - ## -- TODO: These need to be modified for Z - - -SyntaxVersion = 1 - - - -#################################################################### -# Define File -#################################################################### -include ei4.io.define - - define def_IS_HW = SYS.ATTR_IS_SIMULATION == 0; - define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1; - - -define def_bus_id0 = (ATTR_CHIP_UNIT_POS == 0); -define def_bus_id1 = (ATTR_CHIP_UNIT_POS == 1); -define def_bus_id2 = (ATTR_CHIP_UNIT_POS == 2); -define def_bus_id3 = (ATTR_CHIP_UNIT_POS == 3); - -define prim_id = (TGT1.ATTR_FABRIC_NODE_ID*100) + TGT1.ATTR_POS; -define conn_id = (TGT3.ATTR_FABRIC_NODE_ID*100) + TGT3.ATTR_POS; - -define def_is_master = (prim_id < conn_id); -define def_is_slave = (prim_id > conn_id); - -define xbus_base_addr = xbus0_gcr_addr; - - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG -scom 0x800AF000(xbus_base_addr) { - bits, scom_data, expr; - rx_max_ber_check_count, 0b00000011 , def_IS_HW; - rx_max_ber_check_count, 0b00000000 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_DLL_ANALOG_TWEAKS_PG -scom 0x800E7800(xbus_base_addr) { - bits, scom_data, expr; - rx_dll1_vreg_drvcon, 0b111 , def_IS_HW; - rx_dll1_vreg_drvcon, 0b000 , def_IS_VBU; - rx_dll2_vreg_drvcon, 0b111 , def_IS_HW; - rx_dll2_vreg_drvcon, 0b000 , def_IS_VBU; - rx_dll_vreg_compcon, 0b101 , def_IS_HW; - rx_dll_vreg_compcon, 0b000 , def_IS_VBU; - rx_dll_vreg_dac_pullup, 0b1 , def_IS_HW; - rx_dll_vreg_dac_pullup, 0b0 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG -scom 0x8009D800(xbus_base_addr) { - bits, scom_data, expr; - rx_dyn_rpr_bad_lane_max, 0b0001111, any; - rx_dyn_rpr_enc_bad_data_lane_width, 0b111, any; - rx_dyn_rpr_err_cntr1_duration, 0b1010, any; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG -scom 0x800AE000(xbus_base_addr) { - bits, scom_data, expr; - rx_dyn_rpr_bad_bus_max, 0b0011111, any; - rx_dyn_rpr_err_cntr2_duration, 0b0111, any; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP -scom 0x800B1800(xbus_base_addr) { - bits, scom_data, expr; - rx_ddc_use_cyc_block_lock, 0b0 , def_IS_HW; - rx_ddc_use_cyc_block_lock, 0b1 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP -scom 0x800B3000(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_dec_val_a, 0b0111 , def_IS_HW; - rx_cal_dec_val_a, 0b1000 , def_IS_VBU; - rx_cal_dec_val_b, 0b0001 , def_IS_HW; - rx_cal_dec_val_b, 0b0000 , def_IS_VBU; - rx_cal_dec_val_c, 0b0111 , def_IS_HW; - rx_cal_dec_val_c, 0b0000 , def_IS_VBU; - rx_cal_dec_val_d, 0b0111 , def_IS_HW; - rx_cal_dec_val_d, 0b0110 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP -scom 0x800B3800(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_dec_val_e, 0b0111 , def_IS_HW; - rx_cal_dec_val_e, 0b0110 , def_IS_VBU; - rx_cal_dec_val_f, 0b0111 , def_IS_HW; - rx_cal_dec_val_f, 0b0000 , def_IS_VBU; - rx_cal_dec_val_g, 0b0111 , def_IS_HW; - rx_cal_dec_val_g, 0b0000 , def_IS_VBU; - rx_cal_dec_val_h, 0b0111 , def_IS_HW; - rx_cal_dec_val_h, 0b0000 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP -scom 0x800B2000(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_inc_val_a, 0b0111 , def_IS_HW; - rx_cal_inc_val_a, 0b1000 , def_IS_VBU; - rx_cal_inc_val_b, 0b0001 , def_IS_HW; - rx_cal_inc_val_b, 0b0000 , def_IS_VBU; - rx_cal_inc_val_c, 0b0111 , def_IS_HW; - rx_cal_inc_val_c, 0b0000 , def_IS_VBU; - rx_cal_inc_val_d, 0b0111 , def_IS_HW; - rx_cal_inc_val_d, 0b0110 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP -scom 0x800B2800(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_inc_val_e, 0b0111 , def_IS_HW; - rx_cal_inc_val_e, 0b0110 , def_IS_VBU; - rx_cal_inc_val_f, 0b0111 , def_IS_HW; - rx_cal_inc_val_f, 0b0000 , def_IS_VBU; - rx_cal_inc_val_g, 0b0111 , def_IS_HW; - rx_cal_inc_val_g, 0b0000 , def_IS_VBU; - rx_cal_inc_val_h, 0b0111 , def_IS_HW; - rx_cal_inc_val_h, 0b0000 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG -scom 0x800A3800(xbus_base_addr) { - bits, scom_data, expr; - rx_eo_enable_ber_test, 0b1 , def_IS_HW; - rx_eo_enable_ber_test, 0b0 , def_IS_VBU; - rx_eo_enable_ctle_cal, 0b1 , def_IS_HW; - rx_eo_enable_ctle_cal, 0b0 , def_IS_VBU; - rx_eo_enable_dcd_cal, 0b1 , def_IS_HW; - rx_eo_enable_dcd_cal, 0b0 , def_IS_VBU; - rx_eo_enable_final_l2u_adj, 0b1, any; - rx_eo_enable_latch_offset_cal, 0b1 , def_IS_HW; - rx_eo_enable_latch_offset_cal, 0b0 , def_IS_VBU; - rx_eo_enable_measure_eye_width, 0b1 , def_IS_HW; - rx_eo_enable_measure_eye_width, 0b0 , def_IS_VBU; - rx_eo_enable_result_check, 0b1 , def_IS_HW; - rx_eo_enable_result_check, 0b0 , def_IS_VBU; - rx_eo_enable_vref_cal, 0b1 , def_IS_HW; - rx_eo_enable_vref_cal, 0b0 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG -scom 0x8009A800(xbus_base_addr) { - bits, scom_data, expr; - rx_fence, 0b1, any; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x80085000(xbus_base_addr) { - bits, scom_data, expr; - rx_bus_id, 0b000000, any; - rx_group_id, 0b000000, any; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_ID2_PG -scom 0x80085800(xbus_base_addr) { - bits, scom_data, expr; - rx_last_group_id, 0b000011, any; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_ID3_PG -scom 0x80086000(xbus_base_addr) { - bits, scom_data, expr; - rx_end_lane_id, 0b0010011, any; - rx_start_lane_id, 0b0000000, any; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG -scom 0x80092800(xbus_base_addr) { - bits, scom_data, expr; - rx_lane_disabled_vec_0_15, 0b0000000000000000, any; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG -scom 0x80093000(xbus_base_addr) { - bits, scom_data, expr; - rx_lane_disabled_vec_16_31, 0b0000111111111111, any; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_MODE1_PP -scom 0x800B0800(xbus_base_addr) { - bits, scom_data, expr; - rx_bit_lock_timeout_sel, 0b110 , def_IS_HW; - rx_bit_lock_timeout_sel, 0b101 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG -scom 0x80081800(xbus_base_addr) { - bits, scom_data, expr; - rx_master_mode, 0b1, def_is_master; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG -scom 0x800AB800(xbus_base_addr) { - bits, scom_data, expr; - rx_rc_enable_dll_update, 0b1 , def_IS_HW; - rx_rc_enable_dll_update, 0b0 , def_IS_VBU; - rx_rc_enable_edge_track, 0b1 , def_IS_HW; - rx_rc_enable_edge_track, 0b0 , def_IS_VBU; - rx_rc_enable_measure_eye_width, 0b1 , def_IS_HW; - rx_rc_enable_measure_eye_width, 0b0 , def_IS_VBU; - rx_rc_enable_result_check, 0b1 , def_IS_HW; - rx_rc_enable_result_check, 0b0 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP -scom 0x800B6000(xbus_base_addr) { - bits, scom_data, expr; - rx_servo_timeout_sel_a, 0b0101 , def_IS_HW; - rx_servo_timeout_sel_a, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_b, 0b1010 , def_IS_HW; - rx_servo_timeout_sel_b, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_c, 0b0101 , def_IS_HW; - rx_servo_timeout_sel_c, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_d, 0b1001 , def_IS_HW; - rx_servo_timeout_sel_d, 0b0101 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP -scom 0x800B6800(xbus_base_addr) { - bits, scom_data, expr; - rx_servo_timeout_sel_f, 0b1000 , def_IS_HW; - rx_servo_timeout_sel_f, 0b0110 , def_IS_VBU; - rx_servo_timeout_sel_h, 0b1110 , def_IS_HW; - rx_servo_timeout_sel_h, 0b1000 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG -scom 0x80080800(xbus_base_addr) { - bits, scom_data, expr; - rx_sls_extend_sel, 0b101, def_is_slave; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG -scom 0x80091000(xbus_base_addr) { - bits, scom_data, expr; - rx_eo_ctle_timeout_sel, 0b111 , def_IS_HW; - rx_eo_ctle_timeout_sel, 0b110 , def_IS_VBU; - rx_eo_offset_timeout_sel, 0b111 , def_IS_HW; - rx_eo_offset_timeout_sel, 0b110 , def_IS_VBU; - rx_eo_vref_timeout_sel, 0b111 , def_IS_HW; - rx_eo_vref_timeout_sel, 0b110 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG -scom 0x80089800(xbus_base_addr) { - bits, scom_data, expr; - rx_ds_bl_timeout_sel, 0b101 , def_IS_HW; - rx_ds_bl_timeout_sel, 0b001 , def_IS_VBU; - rx_ds_timeout_sel, 0b110 , def_IS_HW; - rx_ds_timeout_sel, 0b010 , def_IS_VBU; - rx_sls_timeout_sel, 0b110, any; - rx_wt_timeout_sel, 0b111 , def_IS_HW; - rx_wt_timeout_sel, 0b011 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG -scom 0x80099800(xbus_base_addr) { - bits, scom_data, expr; - rx_rx_bus_width, 0b1010000, any; - rx_tx_bus_width, 0b1010000, any; -} - -#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG -scom 0x80095800(xbus_base_addr) { - bits, scom_data, expr; - rx_wtr_max_bad_lanes, 0b00010, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B000(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B001(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B002(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B003(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B004(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B005(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B006(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B007(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B008(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#0.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B009(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00A(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00B(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00C(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00D(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00E(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B00F(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B010(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B011(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B012(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX01_GEN.RX01.RX0.RXPACKS#1.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B013(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG -scom 0x800AF020(xbus_base_addr) { - bits, scom_data, expr; - rx_max_ber_check_count, 0b00000011 , def_IS_HW; - rx_max_ber_check_count, 0b00000000 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_DLL_ANALOG_TWEAKS_PG -scom 0x800E7820(xbus_base_addr) { - bits, scom_data, expr; - rx_dll1_vreg_drvcon, 0b111 , def_IS_HW; - rx_dll1_vreg_drvcon, 0b000 , def_IS_VBU; - rx_dll2_vreg_drvcon, 0b111 , def_IS_HW; - rx_dll2_vreg_drvcon, 0b000 , def_IS_VBU; - rx_dll_vreg_compcon, 0b101 , def_IS_HW; - rx_dll_vreg_compcon, 0b000 , def_IS_VBU; - rx_dll_vreg_dac_pullup, 0b1 , def_IS_HW; - rx_dll_vreg_dac_pullup, 0b0 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG -scom 0x8009D820(xbus_base_addr) { - bits, scom_data, expr; - rx_dyn_rpr_bad_lane_max, 0b0001111, any; - rx_dyn_rpr_enc_bad_data_lane_width, 0b111, any; - rx_dyn_rpr_err_cntr1_duration, 0b1010, any; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG -scom 0x800AE020(xbus_base_addr) { - bits, scom_data, expr; - rx_dyn_rpr_bad_bus_max, 0b0011111, any; - rx_dyn_rpr_err_cntr2_duration, 0b0111, any; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP -scom 0x800B1820(xbus_base_addr) { - bits, scom_data, expr; - rx_ddc_use_cyc_block_lock, 0b0 , def_IS_HW; - rx_ddc_use_cyc_block_lock, 0b1 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP -scom 0x800B3020(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_dec_val_a, 0b0111 , def_IS_HW; - rx_cal_dec_val_a, 0b1000 , def_IS_VBU; - rx_cal_dec_val_b, 0b0001 , def_IS_HW; - rx_cal_dec_val_b, 0b0000 , def_IS_VBU; - rx_cal_dec_val_c, 0b0111 , def_IS_HW; - rx_cal_dec_val_c, 0b0000 , def_IS_VBU; - rx_cal_dec_val_d, 0b0111 , def_IS_HW; - rx_cal_dec_val_d, 0b0110 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP -scom 0x800B3820(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_dec_val_e, 0b0111 , def_IS_HW; - rx_cal_dec_val_e, 0b0110 , def_IS_VBU; - rx_cal_dec_val_f, 0b0111 , def_IS_HW; - rx_cal_dec_val_f, 0b0000 , def_IS_VBU; - rx_cal_dec_val_g, 0b0111 , def_IS_HW; - rx_cal_dec_val_g, 0b0000 , def_IS_VBU; - rx_cal_dec_val_h, 0b0111 , def_IS_HW; - rx_cal_dec_val_h, 0b0000 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP -scom 0x800B2020(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_inc_val_a, 0b0111 , def_IS_HW; - rx_cal_inc_val_a, 0b1000 , def_IS_VBU; - rx_cal_inc_val_b, 0b0001 , def_IS_HW; - rx_cal_inc_val_b, 0b0000 , def_IS_VBU; - rx_cal_inc_val_c, 0b0111 , def_IS_HW; - rx_cal_inc_val_c, 0b0000 , def_IS_VBU; - rx_cal_inc_val_d, 0b0111 , def_IS_HW; - rx_cal_inc_val_d, 0b0110 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP -scom 0x800B2820(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_inc_val_e, 0b0111 , def_IS_HW; - rx_cal_inc_val_e, 0b0110 , def_IS_VBU; - rx_cal_inc_val_f, 0b0111 , def_IS_HW; - rx_cal_inc_val_f, 0b0000 , def_IS_VBU; - rx_cal_inc_val_g, 0b0111 , def_IS_HW; - rx_cal_inc_val_g, 0b0000 , def_IS_VBU; - rx_cal_inc_val_h, 0b0111 , def_IS_HW; - rx_cal_inc_val_h, 0b0000 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG -scom 0x800A3820(xbus_base_addr) { - bits, scom_data, expr; - rx_eo_enable_ber_test, 0b1 , def_IS_HW; - rx_eo_enable_ber_test, 0b0 , def_IS_VBU; - rx_eo_enable_ctle_cal, 0b1 , def_IS_HW; - rx_eo_enable_ctle_cal, 0b0 , def_IS_VBU; - rx_eo_enable_dcd_cal, 0b1 , def_IS_HW; - rx_eo_enable_dcd_cal, 0b0 , def_IS_VBU; - rx_eo_enable_final_l2u_adj, 0b1, any; - rx_eo_enable_latch_offset_cal, 0b1 , def_IS_HW; - rx_eo_enable_latch_offset_cal, 0b0 , def_IS_VBU; - rx_eo_enable_measure_eye_width, 0b1 , def_IS_HW; - rx_eo_enable_measure_eye_width, 0b0 , def_IS_VBU; - rx_eo_enable_result_check, 0b1 , def_IS_HW; - rx_eo_enable_result_check, 0b0 , def_IS_VBU; - rx_eo_enable_vref_cal, 0b1 , def_IS_HW; - rx_eo_enable_vref_cal, 0b0 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_FENCE_PG -scom 0x8009A820(xbus_base_addr) { - bits, scom_data, expr; - rx_fence, 0b1, any; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x80085020(xbus_base_addr) { - bits, scom_data, expr; - rx_bus_id, 0b000000, any; - rx_group_id, 0b000001, any; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_ID2_PG -scom 0x80085820(xbus_base_addr) { - bits, scom_data, expr; - rx_last_group_id, 0b000011, any; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_ID3_PG -scom 0x80086020(xbus_base_addr) { - bits, scom_data, expr; - rx_end_lane_id, 0b0100111, any; - rx_start_lane_id, 0b0010100, any; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG -scom 0x80092820(xbus_base_addr) { - bits, scom_data, expr; - rx_lane_disabled_vec_0_15, 0b0000000000000000, any; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG -scom 0x80093020(xbus_base_addr) { - bits, scom_data, expr; - rx_lane_disabled_vec_16_31, 0b0000111111111111, any; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_MODE1_PP -scom 0x800B0820(xbus_base_addr) { - bits, scom_data, expr; - rx_bit_lock_timeout_sel, 0b110 , def_IS_HW; - rx_bit_lock_timeout_sel, 0b101 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_MODE_PG -scom 0x80081820(xbus_base_addr) { - bits, scom_data, expr; - rx_master_mode, 0b1, def_is_master; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG -scom 0x800AB820(xbus_base_addr) { - bits, scom_data, expr; - rx_rc_enable_dll_update, 0b1 , def_IS_HW; - rx_rc_enable_dll_update, 0b0 , def_IS_VBU; - rx_rc_enable_edge_track, 0b1 , def_IS_HW; - rx_rc_enable_edge_track, 0b0 , def_IS_VBU; - rx_rc_enable_measure_eye_width, 0b1 , def_IS_HW; - rx_rc_enable_measure_eye_width, 0b0 , def_IS_VBU; - rx_rc_enable_result_check, 0b1 , def_IS_HW; - rx_rc_enable_result_check, 0b0 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP -scom 0x800B6020(xbus_base_addr) { - bits, scom_data, expr; - rx_servo_timeout_sel_a, 0b0101 , def_IS_HW; - rx_servo_timeout_sel_a, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_b, 0b1010 , def_IS_HW; - rx_servo_timeout_sel_b, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_c, 0b0101 , def_IS_HW; - rx_servo_timeout_sel_c, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_d, 0b1001 , def_IS_HW; - rx_servo_timeout_sel_d, 0b0101 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP -scom 0x800B6820(xbus_base_addr) { - bits, scom_data, expr; - rx_servo_timeout_sel_f, 0b1000 , def_IS_HW; - rx_servo_timeout_sel_f, 0b0110 , def_IS_VBU; - rx_servo_timeout_sel_h, 0b1110 , def_IS_HW; - rx_servo_timeout_sel_h, 0b1000 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG -scom 0x80080820(xbus_base_addr) { - bits, scom_data, expr; - rx_sls_extend_sel, 0b101, def_is_slave; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG -scom 0x80091020(xbus_base_addr) { - bits, scom_data, expr; - rx_eo_ctle_timeout_sel, 0b111 , def_IS_HW; - rx_eo_ctle_timeout_sel, 0b110 , def_IS_VBU; - rx_eo_offset_timeout_sel, 0b111 , def_IS_HW; - rx_eo_offset_timeout_sel, 0b110 , def_IS_VBU; - rx_eo_vref_timeout_sel, 0b111 , def_IS_HW; - rx_eo_vref_timeout_sel, 0b110 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG -scom 0x80089820(xbus_base_addr) { - bits, scom_data, expr; - rx_ds_bl_timeout_sel, 0b101 , def_IS_HW; - rx_ds_bl_timeout_sel, 0b001 , def_IS_VBU; - rx_ds_timeout_sel, 0b110 , def_IS_HW; - rx_ds_timeout_sel, 0b010 , def_IS_VBU; - rx_sls_timeout_sel, 0b110, any; - rx_wt_timeout_sel, 0b111 , def_IS_HW; - rx_wt_timeout_sel, 0b011 , def_IS_VBU; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG -scom 0x80099820(xbus_base_addr) { - bits, scom_data, expr; - rx_rx_bus_width, 0b1010000, any; - rx_tx_bus_width, 0b1010000, any; -} - -#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG -scom 0x80095820(xbus_base_addr) { - bits, scom_data, expr; - rx_wtr_max_bad_lanes, 0b00010, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B020(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B021(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B022(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B023(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B024(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B025(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B026(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B027(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B028(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#0.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B029(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B02A(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B02B(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B02C(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B02D(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B02E(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B02F(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B030(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B031(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B032(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX01_GEN.RX01.RX1.RXPACKS#1.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B033(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG -scom 0x800AF040(xbus_base_addr) { - bits, scom_data, expr; - rx_max_ber_check_count, 0b00000011 , def_IS_HW; - rx_max_ber_check_count, 0b00000000 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_DLL_ANALOG_TWEAKS_PG -scom 0x800E7840(xbus_base_addr) { - bits, scom_data, expr; - rx_dll1_vreg_drvcon, 0b111 , def_IS_HW; - rx_dll1_vreg_drvcon, 0b000 , def_IS_VBU; - rx_dll2_vreg_drvcon, 0b111 , def_IS_HW; - rx_dll2_vreg_drvcon, 0b000 , def_IS_VBU; - rx_dll_vreg_compcon, 0b101 , def_IS_HW; - rx_dll_vreg_compcon, 0b000 , def_IS_VBU; - rx_dll_vreg_dac_pullup, 0b1 , def_IS_HW; - rx_dll_vreg_dac_pullup, 0b0 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG -scom 0x8009D840(xbus_base_addr) { - bits, scom_data, expr; - rx_dyn_rpr_bad_lane_max, 0b0001111, any; - rx_dyn_rpr_enc_bad_data_lane_width, 0b111, any; - rx_dyn_rpr_err_cntr1_duration, 0b1010, any; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG -scom 0x800AE040(xbus_base_addr) { - bits, scom_data, expr; - rx_dyn_rpr_bad_bus_max, 0b0011111, any; - rx_dyn_rpr_err_cntr2_duration, 0b0111, any; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP -scom 0x800B1840(xbus_base_addr) { - bits, scom_data, expr; - rx_ddc_use_cyc_block_lock, 0b0 , def_IS_HW; - rx_ddc_use_cyc_block_lock, 0b1 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP -scom 0x800B3040(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_dec_val_a, 0b0111 , def_IS_HW; - rx_cal_dec_val_a, 0b1000 , def_IS_VBU; - rx_cal_dec_val_b, 0b0001 , def_IS_HW; - rx_cal_dec_val_b, 0b0000 , def_IS_VBU; - rx_cal_dec_val_c, 0b0111 , def_IS_HW; - rx_cal_dec_val_c, 0b0000 , def_IS_VBU; - rx_cal_dec_val_d, 0b0111 , def_IS_HW; - rx_cal_dec_val_d, 0b0110 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP -scom 0x800B3840(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_dec_val_e, 0b0111 , def_IS_HW; - rx_cal_dec_val_e, 0b0110 , def_IS_VBU; - rx_cal_dec_val_f, 0b0111 , def_IS_HW; - rx_cal_dec_val_f, 0b0000 , def_IS_VBU; - rx_cal_dec_val_g, 0b0111 , def_IS_HW; - rx_cal_dec_val_g, 0b0000 , def_IS_VBU; - rx_cal_dec_val_h, 0b0111 , def_IS_HW; - rx_cal_dec_val_h, 0b0000 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP -scom 0x800B2040(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_inc_val_a, 0b0111 , def_IS_HW; - rx_cal_inc_val_a, 0b1000 , def_IS_VBU; - rx_cal_inc_val_b, 0b0001 , def_IS_HW; - rx_cal_inc_val_b, 0b0000 , def_IS_VBU; - rx_cal_inc_val_c, 0b0111 , def_IS_HW; - rx_cal_inc_val_c, 0b0000 , def_IS_VBU; - rx_cal_inc_val_d, 0b0111 , def_IS_HW; - rx_cal_inc_val_d, 0b0110 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP -scom 0x800B2840(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_inc_val_e, 0b0111 , def_IS_HW; - rx_cal_inc_val_e, 0b0110 , def_IS_VBU; - rx_cal_inc_val_f, 0b0111 , def_IS_HW; - rx_cal_inc_val_f, 0b0000 , def_IS_VBU; - rx_cal_inc_val_g, 0b0111 , def_IS_HW; - rx_cal_inc_val_g, 0b0000 , def_IS_VBU; - rx_cal_inc_val_h, 0b0111 , def_IS_HW; - rx_cal_inc_val_h, 0b0000 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG -scom 0x800A3840(xbus_base_addr) { - bits, scom_data, expr; - rx_eo_enable_ber_test, 0b1 , def_IS_HW; - rx_eo_enable_ber_test, 0b0 , def_IS_VBU; - rx_eo_enable_ctle_cal, 0b1 , def_IS_HW; - rx_eo_enable_ctle_cal, 0b0 , def_IS_VBU; - rx_eo_enable_dcd_cal, 0b1 , def_IS_HW; - rx_eo_enable_dcd_cal, 0b0 , def_IS_VBU; - rx_eo_enable_final_l2u_adj, 0b1, any; - rx_eo_enable_latch_offset_cal, 0b1 , def_IS_HW; - rx_eo_enable_latch_offset_cal, 0b0 , def_IS_VBU; - rx_eo_enable_measure_eye_width, 0b1 , def_IS_HW; - rx_eo_enable_measure_eye_width, 0b0 , def_IS_VBU; - rx_eo_enable_result_check, 0b1 , def_IS_HW; - rx_eo_enable_result_check, 0b0 , def_IS_VBU; - rx_eo_enable_vref_cal, 0b1 , def_IS_HW; - rx_eo_enable_vref_cal, 0b0 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG -scom 0x8009A840(xbus_base_addr) { - bits, scom_data, expr; - rx_fence, 0b1, any; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x80085040(xbus_base_addr) { - bits, scom_data, expr; - rx_bus_id, 0b000000, any; - rx_group_id, 0b000010, any; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_ID2_PG -scom 0x80085840(xbus_base_addr) { - bits, scom_data, expr; - rx_last_group_id, 0b000011, any; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_ID3_PG -scom 0x80086040(xbus_base_addr) { - bits, scom_data, expr; - rx_end_lane_id, 0b0111011, any; - rx_start_lane_id, 0b0101000, any; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG -scom 0x80092840(xbus_base_addr) { - bits, scom_data, expr; - rx_lane_disabled_vec_0_15, 0b0000000000000000, any; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG -scom 0x80093040(xbus_base_addr) { - bits, scom_data, expr; - rx_lane_disabled_vec_16_31, 0b0000111111111111, any; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_MODE1_PP -scom 0x800B0840(xbus_base_addr) { - bits, scom_data, expr; - rx_bit_lock_timeout_sel, 0b110 , def_IS_HW; - rx_bit_lock_timeout_sel, 0b101 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG -scom 0x80081840(xbus_base_addr) { - bits, scom_data, expr; - rx_master_mode, 0b1, def_is_master; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG -scom 0x800AB840(xbus_base_addr) { - bits, scom_data, expr; - rx_rc_enable_dll_update, 0b1 , def_IS_HW; - rx_rc_enable_dll_update, 0b0 , def_IS_VBU; - rx_rc_enable_edge_track, 0b1 , def_IS_HW; - rx_rc_enable_edge_track, 0b0 , def_IS_VBU; - rx_rc_enable_measure_eye_width, 0b1 , def_IS_HW; - rx_rc_enable_measure_eye_width, 0b0 , def_IS_VBU; - rx_rc_enable_result_check, 0b1 , def_IS_HW; - rx_rc_enable_result_check, 0b0 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP -scom 0x800B6040(xbus_base_addr) { - bits, scom_data, expr; - rx_servo_timeout_sel_a, 0b0101 , def_IS_HW; - rx_servo_timeout_sel_a, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_b, 0b1010 , def_IS_HW; - rx_servo_timeout_sel_b, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_c, 0b0101 , def_IS_HW; - rx_servo_timeout_sel_c, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_d, 0b1001 , def_IS_HW; - rx_servo_timeout_sel_d, 0b0101 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP -scom 0x800B6840(xbus_base_addr) { - bits, scom_data, expr; - rx_servo_timeout_sel_f, 0b1000 , def_IS_HW; - rx_servo_timeout_sel_f, 0b0110 , def_IS_VBU; - rx_servo_timeout_sel_h, 0b1110 , def_IS_HW; - rx_servo_timeout_sel_h, 0b1000 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG -scom 0x80080840(xbus_base_addr) { - bits, scom_data, expr; - rx_sls_extend_sel, 0b101, def_is_slave; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG -scom 0x80091040(xbus_base_addr) { - bits, scom_data, expr; - rx_eo_ctle_timeout_sel, 0b111 , def_IS_HW; - rx_eo_ctle_timeout_sel, 0b110 , def_IS_VBU; - rx_eo_offset_timeout_sel, 0b111 , def_IS_HW; - rx_eo_offset_timeout_sel, 0b110 , def_IS_VBU; - rx_eo_vref_timeout_sel, 0b111 , def_IS_HW; - rx_eo_vref_timeout_sel, 0b110 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG -scom 0x80089840(xbus_base_addr) { - bits, scom_data, expr; - rx_ds_bl_timeout_sel, 0b101 , def_IS_HW; - rx_ds_bl_timeout_sel, 0b001 , def_IS_VBU; - rx_ds_timeout_sel, 0b110 , def_IS_HW; - rx_ds_timeout_sel, 0b010 , def_IS_VBU; - rx_sls_timeout_sel, 0b110, any; - rx_wt_timeout_sel, 0b111 , def_IS_HW; - rx_wt_timeout_sel, 0b011 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG -scom 0x80099840(xbus_base_addr) { - bits, scom_data, expr; - rx_rx_bus_width, 0b1010000, any; - rx_tx_bus_width, 0b1010000, any; -} - -#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG -scom 0x80095840(xbus_base_addr) { - bits, scom_data, expr; - rx_wtr_max_bad_lanes, 0b00010, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B040(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B041(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B042(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B043(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B044(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B045(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B046(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B047(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B048(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#0.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B049(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B04A(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B04B(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B04C(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B04D(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B04E(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B04F(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B050(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B051(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B052(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX23_GEN.RX23.RX0.RXPACKS#1.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B053(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG -scom 0x800AF060(xbus_base_addr) { - bits, scom_data, expr; - rx_max_ber_check_count, 0b00000011 , def_IS_HW; - rx_max_ber_check_count, 0b00000000 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_DLL_ANALOG_TWEAKS_PG -scom 0x800E7860(xbus_base_addr) { - bits, scom_data, expr; - rx_dll1_vreg_drvcon, 0b111 , def_IS_HW; - rx_dll1_vreg_drvcon, 0b000 , def_IS_VBU; - rx_dll2_vreg_drvcon, 0b111 , def_IS_HW; - rx_dll2_vreg_drvcon, 0b000 , def_IS_VBU; - rx_dll_vreg_compcon, 0b101 , def_IS_HW; - rx_dll_vreg_compcon, 0b000 , def_IS_VBU; - rx_dll_vreg_dac_pullup, 0b1 , def_IS_HW; - rx_dll_vreg_dac_pullup, 0b0 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG -scom 0x8009D860(xbus_base_addr) { - bits, scom_data, expr; - rx_dyn_rpr_bad_lane_max, 0b0001111, any; - rx_dyn_rpr_enc_bad_data_lane_width, 0b111, any; - rx_dyn_rpr_err_cntr1_duration, 0b1010, any; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG -scom 0x800AE060(xbus_base_addr) { - bits, scom_data, expr; - rx_dyn_rpr_bad_bus_max, 0b0011111, any; - rx_dyn_rpr_err_cntr2_duration, 0b0111, any; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP -scom 0x800B1860(xbus_base_addr) { - bits, scom_data, expr; - rx_ddc_use_cyc_block_lock, 0b0 , def_IS_HW; - rx_ddc_use_cyc_block_lock, 0b1 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP -scom 0x800B3060(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_dec_val_a, 0b0111 , def_IS_HW; - rx_cal_dec_val_a, 0b1000 , def_IS_VBU; - rx_cal_dec_val_b, 0b0001 , def_IS_HW; - rx_cal_dec_val_b, 0b0000 , def_IS_VBU; - rx_cal_dec_val_c, 0b0111 , def_IS_HW; - rx_cal_dec_val_c, 0b0000 , def_IS_VBU; - rx_cal_dec_val_d, 0b0111 , def_IS_HW; - rx_cal_dec_val_d, 0b0110 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP -scom 0x800B3860(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_dec_val_e, 0b0111 , def_IS_HW; - rx_cal_dec_val_e, 0b0110 , def_IS_VBU; - rx_cal_dec_val_f, 0b0111 , def_IS_HW; - rx_cal_dec_val_f, 0b0000 , def_IS_VBU; - rx_cal_dec_val_g, 0b0111 , def_IS_HW; - rx_cal_dec_val_g, 0b0000 , def_IS_VBU; - rx_cal_dec_val_h, 0b0111 , def_IS_HW; - rx_cal_dec_val_h, 0b0000 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP -scom 0x800B2060(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_inc_val_a, 0b0111 , def_IS_HW; - rx_cal_inc_val_a, 0b1000 , def_IS_VBU; - rx_cal_inc_val_b, 0b0001 , def_IS_HW; - rx_cal_inc_val_b, 0b0000 , def_IS_VBU; - rx_cal_inc_val_c, 0b0111 , def_IS_HW; - rx_cal_inc_val_c, 0b0000 , def_IS_VBU; - rx_cal_inc_val_d, 0b0111 , def_IS_HW; - rx_cal_inc_val_d, 0b0110 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP -scom 0x800B2860(xbus_base_addr) { - bits, scom_data, expr; - rx_cal_inc_val_e, 0b0111 , def_IS_HW; - rx_cal_inc_val_e, 0b0110 , def_IS_VBU; - rx_cal_inc_val_f, 0b0111 , def_IS_HW; - rx_cal_inc_val_f, 0b0000 , def_IS_VBU; - rx_cal_inc_val_g, 0b0111 , def_IS_HW; - rx_cal_inc_val_g, 0b0000 , def_IS_VBU; - rx_cal_inc_val_h, 0b0111 , def_IS_HW; - rx_cal_inc_val_h, 0b0000 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG -scom 0x800A3860(xbus_base_addr) { - bits, scom_data, expr; - rx_eo_enable_ber_test, 0b1 , def_IS_HW; - rx_eo_enable_ber_test, 0b0 , def_IS_VBU; - rx_eo_enable_ctle_cal, 0b1 , def_IS_HW; - rx_eo_enable_ctle_cal, 0b0 , def_IS_VBU; - rx_eo_enable_dcd_cal, 0b1 , def_IS_HW; - rx_eo_enable_dcd_cal, 0b0 , def_IS_VBU; - rx_eo_enable_final_l2u_adj, 0b1, any; - rx_eo_enable_latch_offset_cal, 0b1 , def_IS_HW; - rx_eo_enable_latch_offset_cal, 0b0 , def_IS_VBU; - rx_eo_enable_measure_eye_width, 0b1 , def_IS_HW; - rx_eo_enable_measure_eye_width, 0b0 , def_IS_VBU; - rx_eo_enable_result_check, 0b1 , def_IS_HW; - rx_eo_enable_result_check, 0b0 , def_IS_VBU; - rx_eo_enable_vref_cal, 0b1 , def_IS_HW; - rx_eo_enable_vref_cal, 0b0 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_FENCE_PG -scom 0x8009A860(xbus_base_addr) { - bits, scom_data, expr; - rx_fence, 0b1, any; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG -scom 0x80085060(xbus_base_addr) { - bits, scom_data, expr; - rx_bus_id, 0b000000, any; - rx_group_id, 0b000011, any; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_ID2_PG -scom 0x80085860(xbus_base_addr) { - bits, scom_data, expr; - rx_last_group_id, 0b000011, any; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_ID3_PG -scom 0x80086060(xbus_base_addr) { - bits, scom_data, expr; - rx_end_lane_id, 0b1001111, any; - rx_start_lane_id, 0b0111100, any; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG -scom 0x80092860(xbus_base_addr) { - bits, scom_data, expr; - rx_lane_disabled_vec_0_15, 0b0000000000000000, any; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG -scom 0x80093060(xbus_base_addr) { - bits, scom_data, expr; - rx_lane_disabled_vec_16_31, 0b0000111111111111, any; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_MODE1_PP -scom 0x800B0860(xbus_base_addr) { - bits, scom_data, expr; - rx_bit_lock_timeout_sel, 0b110 , def_IS_HW; - rx_bit_lock_timeout_sel, 0b101 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_MODE_PG -scom 0x80081860(xbus_base_addr) { - bits, scom_data, expr; - rx_master_mode, 0b1, def_is_master; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG -scom 0x800AB860(xbus_base_addr) { - bits, scom_data, expr; - rx_rc_enable_dll_update, 0b1 , def_IS_HW; - rx_rc_enable_dll_update, 0b0 , def_IS_VBU; - rx_rc_enable_edge_track, 0b1 , def_IS_HW; - rx_rc_enable_edge_track, 0b0 , def_IS_VBU; - rx_rc_enable_measure_eye_width, 0b1 , def_IS_HW; - rx_rc_enable_measure_eye_width, 0b0 , def_IS_VBU; - rx_rc_enable_result_check, 0b1 , def_IS_HW; - rx_rc_enable_result_check, 0b0 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP -scom 0x800B6060(xbus_base_addr) { - bits, scom_data, expr; - rx_servo_timeout_sel_a, 0b0101 , def_IS_HW; - rx_servo_timeout_sel_a, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_b, 0b1010 , def_IS_HW; - rx_servo_timeout_sel_b, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_c, 0b0101 , def_IS_HW; - rx_servo_timeout_sel_c, 0b1000 , def_IS_VBU; - rx_servo_timeout_sel_d, 0b1001 , def_IS_HW; - rx_servo_timeout_sel_d, 0b0101 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP -scom 0x800B6860(xbus_base_addr) { - bits, scom_data, expr; - rx_servo_timeout_sel_f, 0b1000 , def_IS_HW; - rx_servo_timeout_sel_f, 0b0110 , def_IS_VBU; - rx_servo_timeout_sel_h, 0b1110 , def_IS_HW; - rx_servo_timeout_sel_h, 0b1000 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG -scom 0x80080860(xbus_base_addr) { - bits, scom_data, expr; - rx_sls_extend_sel, 0b101, def_is_slave; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG -scom 0x80091060(xbus_base_addr) { - bits, scom_data, expr; - rx_eo_ctle_timeout_sel, 0b111 , def_IS_HW; - rx_eo_ctle_timeout_sel, 0b110 , def_IS_VBU; - rx_eo_offset_timeout_sel, 0b111 , def_IS_HW; - rx_eo_offset_timeout_sel, 0b110 , def_IS_VBU; - rx_eo_vref_timeout_sel, 0b111 , def_IS_HW; - rx_eo_vref_timeout_sel, 0b110 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG -scom 0x80089860(xbus_base_addr) { - bits, scom_data, expr; - rx_ds_bl_timeout_sel, 0b101 , def_IS_HW; - rx_ds_bl_timeout_sel, 0b001 , def_IS_VBU; - rx_ds_timeout_sel, 0b110 , def_IS_HW; - rx_ds_timeout_sel, 0b010 , def_IS_VBU; - rx_sls_timeout_sel, 0b110, any; - rx_wt_timeout_sel, 0b111 , def_IS_HW; - rx_wt_timeout_sel, 0b011 , def_IS_VBU; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG -scom 0x80099860(xbus_base_addr) { - bits, scom_data, expr; - rx_rx_bus_width, 0b1010000, any; - rx_tx_bus_width, 0b1010000, any; -} - -#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG -scom 0x80095860(xbus_base_addr) { - bits, scom_data, expr; - rx_wtr_max_bad_lanes, 0b00010, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B060(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B061(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B062(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B063(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B064(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B065(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B066(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B067(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B068(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#0.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B069(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06A(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06B(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06C(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b111, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06D(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b110, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06E(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b101, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B06F(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b100, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#6.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B070(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b011, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#7.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B071(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b010, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#8.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B072(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b001, any; -} - -#RX23_GEN.RX23.RX1.RXPACKS#1.RXPACK.DD.SLICE#9.RD.RX_BIT_REGS.RX_PRBS_MODE_PL -scom 0x8000B073(xbus_base_addr) { - bits, scom_data, expr; - rx_prbs_tap_id, 0b000, any; -} - -#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG -scom 0x800CC400(xbus_base_addr) { - bits, scom_data, expr; - tx_drv_clk_pattern_gcrmsg, 0b00, any; -} - -#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C9400(xbus_base_addr) { - bits, scom_data, expr; - tx_bus_id, 0b000000, any; - tx_group_id, 0b100000, any; -} - -#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_ID2_PG -scom 0x800C9C00(xbus_base_addr) { - bits, scom_data, expr; - tx_last_group_id, 0b100011, any; -} - -#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_ID3_PG -scom 0x800CA400(xbus_base_addr) { - bits, scom_data, expr; - tx_end_lane_id, 0b0010011, any; - tx_start_lane_id, 0b0000000, any; -} - -#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG -scom 0x800D1C00(xbus_base_addr) { - bits, scom_data, expr; - tx_lane_disabled_vec_0_15, 0b0000000000000000, any; -} - -#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG -scom 0x800D2400(xbus_base_addr) { - bits, scom_data, expr; - tx_lane_disabled_vec_16_31, 0b0000111111111111, any; -} - -#TX01_GEN.TX01.TX0.TXCTL.TX_CTL_REGS.TX_MODE_PG -scom 0x800C1C00(xbus_base_addr) { - bits, scom_data, expr; - tx_max_bad_lanes, 0b00010, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043400(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043401(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043402(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043403(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043404(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043405(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043406(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043407(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043408(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#0.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043409(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340A(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340B(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340C(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340D(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340E(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004340F(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043410(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043411(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043412(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX01_GEN.TX01.TX0.TXPACKS#1.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043413(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG -scom 0x800CC420(xbus_base_addr) { - bits, scom_data, expr; - tx_drv_clk_pattern_gcrmsg, 0b00, any; -} - -#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C9420(xbus_base_addr) { - bits, scom_data, expr; - tx_bus_id, 0b000000, any; - tx_group_id, 0b100001, any; -} - -#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_ID2_PG -scom 0x800C9C20(xbus_base_addr) { - bits, scom_data, expr; - tx_last_group_id, 0b100011, any; -} - -#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_ID3_PG -scom 0x800CA420(xbus_base_addr) { - bits, scom_data, expr; - tx_end_lane_id, 0b0100111, any; - tx_start_lane_id, 0b0010100, any; -} - -#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG -scom 0x800D1C20(xbus_base_addr) { - bits, scom_data, expr; - tx_lane_disabled_vec_0_15, 0b0000000000000000, any; -} - -#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG -scom 0x800D2420(xbus_base_addr) { - bits, scom_data, expr; - tx_lane_disabled_vec_16_31, 0b0000111111111111, any; -} - -#TX01_GEN.TX01.TX1.TXCTL.TX_CTL_REGS.TX_MODE_PG -scom 0x800C1C20(xbus_base_addr) { - bits, scom_data, expr; - tx_max_bad_lanes, 0b00010, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043420(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043421(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043422(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043423(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043424(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043425(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043426(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043427(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043428(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#0.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043429(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004342A(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004342B(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004342C(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004342D(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004342E(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004342F(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043430(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043431(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043432(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX01_GEN.TX01.TX1.TXPACKS#1.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043433(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG -scom 0x800CC440(xbus_base_addr) { - bits, scom_data, expr; - tx_drv_clk_pattern_gcrmsg, 0b00, any; -} - -#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C9440(xbus_base_addr) { - bits, scom_data, expr; - tx_bus_id, 0b000000, any; - tx_group_id, 0b100010, any; -} - -#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_ID2_PG -scom 0x800C9C40(xbus_base_addr) { - bits, scom_data, expr; - tx_last_group_id, 0b100011, any; -} - -#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_ID3_PG -scom 0x800CA440(xbus_base_addr) { - bits, scom_data, expr; - tx_end_lane_id, 0b0111011, any; - tx_start_lane_id, 0b0101000, any; -} - -#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG -scom 0x800D1C40(xbus_base_addr) { - bits, scom_data, expr; - tx_lane_disabled_vec_0_15, 0b0000000000000000, any; -} - -#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG -scom 0x800D2440(xbus_base_addr) { - bits, scom_data, expr; - tx_lane_disabled_vec_16_31, 0b0000111111111111, any; -} - -#TX23_GEN.TX23.TX0.TXCTL.TX_CTL_REGS.TX_MODE_PG -scom 0x800C1C40(xbus_base_addr) { - bits, scom_data, expr; - tx_max_bad_lanes, 0b00010, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043440(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043441(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043442(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043443(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043444(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043445(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043446(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043447(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043448(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#0.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043449(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004344A(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004344B(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004344C(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004344D(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004344E(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004344F(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043450(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043451(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043452(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX23_GEN.TX23.TX0.TXPACKS#1.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043453(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG -scom 0x800CC460(xbus_base_addr) { - bits, scom_data, expr; - tx_drv_clk_pattern_gcrmsg, 0b00, any; -} - -#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG -scom 0x800C9460(xbus_base_addr) { - bits, scom_data, expr; - tx_bus_id, 0b000000, any; - tx_group_id, 0b100011, any; -} - -#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_ID2_PG -scom 0x800C9C60(xbus_base_addr) { - bits, scom_data, expr; - tx_last_group_id, 0b100011, any; -} - -#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_ID3_PG -scom 0x800CA460(xbus_base_addr) { - bits, scom_data, expr; - tx_end_lane_id, 0b1001111, any; - tx_start_lane_id, 0b0111100, any; -} - -#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG -scom 0x800D1C60(xbus_base_addr) { - bits, scom_data, expr; - tx_lane_disabled_vec_0_15, 0b0000000000000000, any; -} - -#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG -scom 0x800D2460(xbus_base_addr) { - bits, scom_data, expr; - tx_lane_disabled_vec_16_31, 0b0000111111111111, any; -} - -#TX23_GEN.TX23.TX1.TXCTL.TX_CTL_REGS.TX_MODE_PG -scom 0x800C1C60(xbus_base_addr) { - bits, scom_data, expr; - tx_max_bad_lanes, 0b00010, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043460(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043461(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043462(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043463(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043464(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043465(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043466(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043467(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043468(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#0.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043469(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346A(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346B(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346C(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b111, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346D(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b110, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346E(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b101, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#5.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x8004346F(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b100, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#6.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043470(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b011, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#7.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043471(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b010, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#8.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043472(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b001, any; -} - -#TX23_GEN.TX23.TX1.TXPACKS#1.TXPACK.DD.SLICE#9.TD.TX_BIT_REGS.TX_PRBS_MODE_PL -scom 0x80043473(xbus_base_addr) { - bits, scom_data, expr; - tx_prbs_tap_id, 0b000, any; -} - - -###################################### -## END OF FILE -####################################### diff --git a/src/usr/hwpf/hwp/initfiles/sample.define b/src/usr/hwpf/hwp/initfiles/sample.define deleted file mode 100755 index b4c9e72ad..000000000 --- a/src/usr/hwpf/hwp/initfiles/sample.define +++ /dev/null @@ -1,44 +0,0 @@ -#-- ----------------------------------------------------------------------------- -#-- Change Log ************************************************************************************* -#-- -#-- Flag Userid Date Description -#-- ----- -------- -------- ------------------------------------------------------------- -#-- camvanng 02/07/12 Created sample define file -#-- End Change Log ********************************************************************************* -#-- ----------------------------------------------------------------------------- - -#-- @file sample.define -#-- @brief common scom initfile defines - -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Defines -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -define def_uint8_greater_test = (SYS.ATTR_SCRATCH_UINT8_1 > SYS.ATTR_SCRATCH_UINT8_2); -define def_uint32_greater_test = (SYS.ATTR_SCRATCH_UINT32_1 > SYS.ATTR_SCRATCH_UINT32_2); - -define addr=0x800; -define addr2=0x04011; -define addr3=F3; -define rx_mode_reg=0b100100000; - -define xbus0=0; -define xbus3=C; - -define rx0=000000; -define rx1=000001; - -define lane0=00000; -define lane2=00010; -define lane3=00011; - -define rx_field1 = 48:51; - -define rx_field1_enum_value1 = 0b0000; -define rx_field1_enum_value2 = 0b0001; - -define attr_value1 = 5; diff --git a/src/usr/hwpf/hwp/initfiles/sample.initfile b/src/usr/hwpf/hwp/initfiles/sample.initfile deleted file mode 100755 index ce1e89294..000000000 --- a/src/usr/hwpf/hwp/initfiles/sample.initfile +++ /dev/null @@ -1,236 +0,0 @@ -#-- $Id: sample.initfile,v 1.1 2011/07/13 16:03:44 andrewg Exp $ -#-- CHANGE HISTORY: -#-------------------------------------------------------------------------------- -#-- Version:|Author: | Date: | Comment: -#-- --------|--------|--------|-------------------------------------------------- -#-- 0.01|andrewg |05/24/11|Created sample file -#-- --------|--------|--------|-------------------------------------------------- -#-------------------------------------------------------------------------------- -# End of revision history -#-------------------------------------------------------------------------------- - -#--Master list of variables that can be used in this file is at: -#--<Attribute Definition Location> - -SyntaxVersion = 1 - -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Includes -#-- Note: -# Must specify the path to the .define file here; i.e. -# "include ./hwp/initfiles/sample.define" -# Or specify the directories to search for the include file (-I <path to search>) -# in priority order at the initCompiler command line; i.e. -# "initCompiler -init ./sample.initfile -outdir . -attr ./fapiAttributeIds.H \ -# -I hwp/initfiles -I hwp" -# -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -include sample.define - -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Defines -#-- -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- - -define def_equal_test = (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT32_2); -define def_not_equal_test = (SYS.ATTR_SCRATCH_UINT64_1 != SYS.ATTR_SCRATCH_UINT64_2); - -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -#-- ----------------------------------------------------------------------------- -#-- -#-- Defines for associated targets -#-- User can either use the generic target name TGTn within the initfile or -#-- define a more informative name to use here. -#-- By default attributes without the associated target name prefix or the "SYS." -#-- prefix is the primary target's attribute. The targets must be passed to -#-- fapiHwpExecInitFile() as a std::vector<fapi::Target> with the elements in the -#-- same order as defined in the initfile; i.e. the primary target is the first -#-- element followed by TGT1, 2, 3... -#-- -#-- ----------------------------------------------------------------------------- -#--****************************************************************************** -define MBA0 = TGT1; -define MBA1 = TGT2; - -#--****************************************************************************** -#-- Basic SCOM to PORE_GPE0_SCRATCH0_0x0006000A -#--****************************************************************************** -scom 0x000000000006000A { - scom_data ; - 0x0ABBC00000000000 ; -} - -#--****************************************************************************** -#-- SCOM with Address and Data of Array Type, Range of Index, Bit Support to -#-- PORE_GPE0_SCRATCH1_0x0006000B and PORE_GPE0_SCRATCH2_0x0006000C -#-- The following Scom is equivalent to: -#scom 0x000000000006000B { -# bits, scom_data , expr; -# 0:7, SYS.ATTR_SCRATCH_UINT8_ARRAY_1[2], SYS.ATTR_SCRATCH_UINT8_ARRAY_1[2] > SYS.ATTR_SCRATCH_UINT8_1; -# 24:31, SYS.ATTR_SCRATCH_UINT8_ARRAY_1[2], SYS.ATTR_SCRATCH_UINT8_1 == SYS.ATTR_SCRATCH_UINT8_ARRAY_1[3]; -# 32:39, SYS.ATTR_SCRATCH_UINT8_ARRAY_2[0][1][2], SYS.ATTR_SCRATCH_UINT8_ARRAY_1[0] < SYS.ATTR_SCRATCH_UINT8_ARRAY_1[1]; -#} -# -#scom 0x000000000006000C { -# bits, scom_data , expr; -# 0:7, SYS.ATTR_SCRATCH_UINT8_ARRAY_1[2], SYS.ATTR_SCRATCH_UINT8_ARRAY_1[31] > SYS.ATTR_SCRATCH_UINT8_1; -# 24:31, SYS.ATTR_SCRATCH_UINT8_ARRAY_1[31], SYS.ATTR_SCRATCH_UINT8_1 == SYS.ATTR_SCRATCH_UINT8_ARRAY_1[7]; -# 32:39, SYS.ATTR_SCRATCH_UINT8_ARRAY_2[1][2][3], SYS.ATTR_SCRATCH_UINT8_ARRAY_1[17] < SYS.ATTR_SCRATCH_UINT8_ARRAY_1[18]; -#} -scom 0x000000000006000(B,C) { - bits, scom_data , expr; - 0:7, SYS.ATTR_SCRATCH_UINT8_ARRAY_1[2], SYS.ATTR_SCRATCH_UINT8_ARRAY_1[2,31] > SYS.ATTR_SCRATCH_UINT8_1; - 24:31, SYS.ATTR_SCRATCH_UINT8_ARRAY_1[2,31], SYS.ATTR_SCRATCH_UINT8_1 == SYS.ATTR_SCRATCH_UINT8_ARRAY_1[3,7]; - 32:39, SYS.ATTR_SCRATCH_UINT8_ARRAY_2[0..1][1,2][2,3], SYS.ATTR_SCRATCH_UINT8_ARRAY_1[0,17] < SYS.ATTR_SCRATCH_UINT8_ARRAY_1[1,18]; -} - -#--****************************************************************************** -#-- Basic SCOM with define used to PORE_GPE1_SCRATCH0_0x0006002A -#--****************************************************************************** -scom 0x000000000006002A { - scom_data, expr ; - 0x0000000000000184, def_equal_test ; -} - -#--****************************************************************************** -#-- Basic SCOM with a single bit set to PORE_GPE1_SCRATCH1_0x0006002B -#--****************************************************************************** -scom 0x000000000006002B { - bits , scom_data ; - 23 , 0b1 ; -} - -#--****************************************************************************** -#-- Basic SCOM with same address but different bits set & Scom data of Attr type -#-- Simple operations on Scom data -#--****************************************************************************** -scom 0x000000000006002B { - bits , scom_data , expr ; - 24:31, (MBA1.ATTR_CHIP_UNIT_POS + SYS.ATTR_SCRATCH_UINT8_ARRAY_2[1][2][3]) , (SYS.ATTR_SCRATCH_UINT8_1 | 0b00000001) != 1; - 24:31, ((MBA1.ATTR_CHIP_UNIT_POS | SYS.ATTR_SCRATCH_UINT8_ARRAY_2[1][2][3]) + 1) / 2, !(SYS.ATTR_SCRATCH_UINT8_1 == 3); - 32:63, (((SYS.ATTR_SCRATCH_UINT32_1 * 20) & 0x000000F0)) << 8 , (SYS.ATTR_SCRATCH_UINT32_1 & 0x0000FFFF) == 3; -} - -#--****************************************************************************** -#-- Basic SCOM with bits to PORE_GPE1_SCRATCH2_0x0006002C -#--****************************************************************************** -scom 0x000000000006002C { - bits , scom_data ; - 0:11 , 0b000011001001 ; - 12 , 0b1 ; - 13 , 0x1 ; - 14:59, 0x00c190010480 ; - 60:63, 0b1101 ; -} - -#--****************************************************************************** -#-- Complex SCOM with Bit Support, define, and attributes to -#-- PORE_SLW_SCRATCH0_0x0006800A -#--****************************************************************************** -scom 0x000000000006800A { - bits , scom_data, expr ; - 0:11 , 0b000011001001, ANY ; - 12 , 0b1, def_equal_test ; - 12 , 0b0, def_not_equal_test ; - 13 , 0b1, def_uint8_greater_test ; - 14:59, 0b0000001100000110010000000000010000010010000000, SYS.ATTR_SCRATCH_UINT64_2 == ENUM_ATTR_SCRATCH_UINT64_2_VAL_C; -} - -#--****************************************************************************** -#-- Complex SCOM with Bit Support, and logical operators to -#-- PORE_SLW_SCRATCH1_0x0006800B -#--****************************************************************************** -scom 0x000000000006800B { - bits , scom_data, expr ; - 12 , 0b1, def_equal_test && def_not_equal_test ; - 12 , 0b0, def_equal_test || def_not_equal_test ; - 14 , 0b1, SYS.ATTR_SCRATCH_UINT32_1 < SYS.ATTR_SCRATCH_UINT32_2 ; - 15 , 0b1, def_uint32_greater_test ; - 16 , 0b1, SYS.ATTR_SCRATCH_UINT32_1 >= SYS.ATTR_SCRATCH_UINT32_2 ; - 17 , 0b1, SYS.ATTR_SCRATCH_UINT32_1 <= SYS.ATTR_SCRATCH_UINT32_2 ; - 18 , 0b1, SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT32_2 ; - 19 , 0b1, SYS.ATTR_SCRATCH_UINT32_1 != SYS.ATTR_SCRATCH_UINT32_2 ; - 20 , 0b1, (SYS.ATTR_SCRATCH_UINT32_1 + SYS.ATTR_SCRATCH_UINT32_2) == 4 ; - 21:59, 0b000000110000011001000000000001000001001, SYS.ATTR_SCRATCH_UINT8_1 == SYS.ATTR_SCRATCH_UINT8_2 ; -} - -#--****************************************************************************** -#-- SCOM with 'ec' column - Use scratch for now since all attributes work -#-- To PORE_SLW_SCRATCH2_0x0006800C -#--****************************************************************************** -scom 0x000000000006800C { - scom_data, SYS.ATTR_SCRATCH_UINT32_1, SYS.ATTR_SCRATCH_UINT32_2 ; - 0x0000000000000192, != 0, >= ENUM_ATTR_SCRATCH_UINT64_ARRAY_2_VAL_B ; -} - -#--****************************************************************************** -#-- Basic SCOM with an array to PORE_SBE_SCRATCH0_0x000E000A -#--****************************************************************************** -scom 0x00000000000E000A { - scom_data, expr ; - 0x0000000000000182, SYS.ATTR_SCRATCH_UINT8_ARRAY_1[2] == SYS.ATTR_SCRATCH_UINT8_1 ; -} - -#--****************************************************************************** -#-- SCOM with 'ec' & expr column - Use scratch for now since all attributes work -#-- To PORE_SBE_SCRATCH1_0x000E000B -#--****************************************************************************** -scom 0x00000000000E000B { - scom_data, SYS.ATTR_SCRATCH_UINT32_1, expr; - 0x0000000000000192, 3, SYS.ATTR_SCRATCH_UINT8_ARRAY_2[1][2][3] == 0x00000000000000BE; -} - -#--****************************************************************************** -#-- Complex SCOM with Bit Support, associated attributes and logical operators -#-- To PORE_SBE_SCRATCH2_0x000E000C -#--****************************************************************************** -# TODO: RTC:Issue 66579 remove this register as it is now being used by dump -scom 0x00000000000E000C { - bits, scom_data, MBA1.ATTR_CHIP_UNIT_POS, expr; - 23, 0b0, 1, MBA0.ATTR_CHIP_UNIT_POS == 1; - 23, MBA1.ATTR_CHIP_UNIT_POS, 1, MBA0.ATTR_CHIP_UNIT_POS == 0; - 24:25, 0b10, 0, any; - 24:25, 0b01, 1, SYS.ATTR_SCRATCH_UINT8_ARRAY_1[2] == SYS.ATTR_SCRATCH_UINT8_1; -} - -#--****************************************************************************** -#-- Basic SCOM with Multiple Arrays/Address Ranges -#-- Note: These are not valid SCOM addresses. Just included here as an example of -#-- the supported syntax. Uncomment only for debugging code. -#--****************************************************************************** -#scom 0x0000006(0E..10,3c)4(A,1)(D..F)56(7,8,9,0)1 { -# scom_data ; -# 0x0000000000000193 ; -#} - -#--****************************************************************************** -#-- Basic SCOM with Bin and Hex Scom Addresses of Multiple Arrays/Address Ranges -#-- Note: These are not valid SCOM addresses. Just included here as an example of -#-- the supported syntax. Uncomment only for debugging code. -#--****************************************************************************** -#scom 0x(7,8)000001301.0b1(01..10,00)(00,01)0(1,0)1.0xD(8A,8B)C { -# scom_data ; -# 0x0000000000000194 ; -#} - -#--****************************************************************************** -#-- SCOM with defines for Scom address and each supported column. -#-- Note: This SCOM is inluded here as an example of the supported syntax. -#-- Uncomment only for debugging code. -#--****************************************************************************** -#scom addr.rx_mode_reg(rx0,rx1)(lane0, lane2..lane3).addr2(xbus0,xbus3)addr3 { -# bits , scom_data, SYS.ATTR_SCRATCH_UINT32_1, expr; -# rx_field1, rx_field1_enum_value1, any, def_equal_test; -# rx_field1, rx_field1_enum_value2, attr_value1, def_not_equal_test; -#} diff --git a/src/usr/hwpf/hwp/pll_accessors/getPllRingAttr.C b/src/usr/hwpf/hwp/pll_accessors/getPllRingAttr.C deleted file mode 100755 index 3c1d6ef31..000000000 --- a/src/usr/hwpf/hwp/pll_accessors/getPllRingAttr.C +++ /dev/null @@ -1,984 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/pll_accessors/getPllRingAttr.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getPllRingAttr.C,v 1.9 2014/12/08 18:48:21 thi Exp $ -/** - * @file getPllRingAttr.C - * - * @brief fetch PLL ring attributes based on chip EC and frequencies - * from data from static arrays (fapiPllRingAttr.H) - * Note: Throughout this program all 3 potential attributes - * (i.e. _DATA, _FLUSH & _LENGTH) for each PLL ring have - * been listed with those that are not currently defined - * being commented out. This was done to help show that - * these were not accidentally left out. - * - */ - -#include <stdint.h> - -// FAPI_SIMULATION is controlled by makefile -#ifndef FAPI_SIMULATION -#define HW -#endif - -// fapi support -#include <fapiPllRingAttr.H> -#include <getPllRingAttr.H> - -// Maximum # of frequencies needed to determine correct PLL ring data -#define MAX_FREQ_KEYS 4 - -// Logic overview - -// Define and initialize variables -// Get chip type -// Get EC level -// Case statement to get frequncy keys -// 1. Set array element length -// 2. Get additional keys -// Case statement for each PLL ring -// 1. Set pointer to first array element -// 2. Set array size -// Loop through array to return requested element -// Case statement for each attribute -// 1. Set return attr value - -extern "C" -{ - -// getPllRingAttr -fapi::ReturnCode getPllRingAttr( const fapi::AttributeId i_attrId, - const fapi::Target i_pChipTarget, - uint32_t & o_ringBitLength, - uint8_t *o_data) -{ - // Define and initialize variables - const uint32_t PU_PCIE_REF_CLOCK_CONST = 100; - fapi::ReturnCode rc; - fapi::ATTR_NAME_Type l_chipType = 0x00; - fapi::ATTR_EC_Type l_attrDdLevel = 0x00; - uint8_t l_numKeys = 0; - uint8_t l_arySize = 0; - uint8_t l_idx = 0; - uint16_t l_arrayEntryLength = 0; - // Up to 4 frequencies to query to get PLL data - uint32_t l_freqKeys[MAX_FREQ_KEYS] = {0,0,0,0}; - const PLL_RING_ATTR_WITH_4_KEYS * l_pllArrayPtr = NULL; - const PLL_RING_ATTR_WITH_2_KEYS * l_2KeyPllArrayPtr = NULL; - const PLL_RING_ATTR_WITH_1_KEYS * l_1KeyPllArrayPtr = NULL; - - // Error FFDC - const fapi::AttributeId & ATTR_ID = i_attrId; - const fapi::Target & PROC_CHIP = i_pChipTarget; - const fapi::ATTR_NAME_Type & CHIP_NAME = l_chipType; - const fapi::ATTR_NAME_Type & CHIP_EC = l_attrDdLevel; - - // Initialize array pointers to base EC level arrays - FAPI_DBG("getPllRingAttr: request i_attrId=0x%x",i_attrId ); - - do - { - // Get chip type - FAPI_DBG("getPllRingAttr: Querying Chip type"); - rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME, &i_pChipTarget, l_chipType); - if (rc) - { - FAPI_ERR("getPllRingAttr: Get ATTR_NAME failed"); - break; - } - - // Get EC level - FAPI_DBG("getPllRingAttr: Querying EC level"); - rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_EC, &i_pChipTarget, l_attrDdLevel); - if (rc) - { - FAPI_ERR("getPllRingAttr: Get ATTR_EC failed"); - break; - } - - // Murano DD1.2 and DD1.0 are equivalent in terms of engineering data - if ((l_chipType == fapi::ENUM_ATTR_NAME_MURANO) && - (l_attrDdLevel == 0x12)) - { - FAPI_INF("getPllRingAttr: Treating Murano EC1.2 like EC1.0"); - l_attrDdLevel = 0x10; - } - - FAPI_DBG("getPllRingAttr: Chip type=0x%02x EC=0x%02x", l_chipType, - l_attrDdLevel); - - // Case statement to get frequncy keys - // 1. Set array element length - // 2. Get additional keys - switch (i_attrId) - { - case fapi::ATTR_PROC_AB_BNDY_PLL_DATA: - case fapi::ATTR_PROC_AB_BNDY_PLL_FLUSH: - case fapi::ATTR_PROC_AB_BNDY_PLL_LENGTH: - // Set entry size - l_numKeys = 1; - l_arrayEntryLength = sizeof(PLL_RING_ATTR_WITH_1_KEYS); - // Get a bus frequency attribute - rc = FAPI_ATTR_GET(ATTR_FREQ_A, NULL, l_freqKeys[0]); - if (rc) - { - FAPI_ERR("getPllRingAttr: Get ATTR_FREQ_A failed"); - break; - } - // a bus frequency needs to be halved for table lookup - l_freqKeys[0] /= 2; - FAPI_DBG("getPllRingAttr: Queryied frequency ATTR_FREQ_A = %i ", - l_freqKeys[0]); - break; - case fapi::ATTR_PROC_PB_BNDY_DMIPLL_DATA: - case fapi::ATTR_PROC_PB_BNDY_DMIPLL_FLUSH: - case fapi::ATTR_PROC_PB_BNDY_DMIPLL_LENGTH: - // Set entry size - l_numKeys = 1; - l_arrayEntryLength = sizeof(PLL_RING_ATTR_WITH_1_KEYS); - // Get pb frequency attribute - rc = FAPI_ATTR_GET(ATTR_FREQ_X, NULL, l_freqKeys[0]); - if (rc) - { - FAPI_ERR("getPllRingAttr: Get ATTR_FREQ_X failed"); - break; - } - break; - case fapi::ATTR_PROC_PCI_BNDY_PLL_DATA: - case fapi::ATTR_PROC_PCI_BNDY_PLL_FLUSH: - case fapi::ATTR_PROC_PCI_BNDY_PLL_LENGTH: - // Set entry size - l_numKeys = 1; - l_arrayEntryLength = sizeof(PLL_RING_ATTR_WITH_1_KEYS); - // Get PCI frequency attribute - rc = FAPI_ATTR_GET(ATTR_FREQ_PCIE, NULL, l_freqKeys[0]); - if (rc) - { - FAPI_ERR("getPllRingAttr: Get ATTR_FREQ_PCIE failed"); - break; - } - break; - case fapi::ATTR_PROC_PERV_BNDY_PLL_DATA: - case fapi::ATTR_PROC_PERV_BNDY_PLL_FLUSH: - case fapi::ATTR_PROC_PERV_BNDY_PLL_LENGTH: - // Set entry size - l_numKeys = 4; - l_arrayEntryLength = sizeof(PLL_RING_ATTR_WITH_4_KEYS); - // Get pu nest, PCI, ref clock and x bus frequencies attributes - rc = FAPI_ATTR_GET(ATTR_NEST_FREQ_MHZ, NULL, l_freqKeys[0]); - if (rc) - { - FAPI_ERR("getPllRingAttr: Get ATTR_NEST_FREQ_MHZ failed "); - break; - } - - // No equivalent FAPI attribute exists for this cronus key. - // Always set to 100. - l_freqKeys[1] = PU_PCIE_REF_CLOCK_CONST; - - rc = FAPI_ATTR_GET(ATTR_FREQ_PROC_REFCLOCK, NULL, - l_freqKeys[2]); - if (rc) - { - FAPI_ERR("getPllRingAttr: Get ATTR_FREQ_PROC_REFCLOCK failed"); - break; - } - - rc = FAPI_ATTR_GET(ATTR_FREQ_X, NULL, l_freqKeys[3]); - if (rc) - { - FAPI_ERR("getPllRingAttr: Get ATTR_FREQ_X failed"); - break; - } - FAPI_DBG("getPllRingAttr: Queryied frequency ATTR_FREQ_X = %i ", - l_freqKeys[3]); - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_FLUSH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH: - // Set entry size - l_numKeys = 2; - l_arrayEntryLength = sizeof(PLL_RING_ATTR_WITH_2_KEYS); - // Get keys - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &i_pChipTarget, - l_freqKeys[0]); - if (rc) - { - FAPI_ERR("getPllRingAttr: Get ATTR_MSS_FREQ failed"); - break; - } - - rc = FAPI_ATTR_GET(ATTR_FREQ_X, NULL, l_freqKeys[1]); - if (rc) - { - FAPI_ERR("getPllRingAttr: Get ATTR_FREQ_X failed"); - break; - } - break; - default: - FAPI_ERR("getPllRingAttr: Requested attribute not supported. attrId=0x%x", - i_attrId); - FAPI_SET_HWP_ERROR(rc, RC_GET_PLL_RING_ATTR_INVALID_ATTRIBUTE_ID); - }; - - // Exit on error - if (rc) - { - break; - } - -// Freqs are set as 0 in ring attribute files for SIM environment -#ifdef FAPI_SIMULATION - for (uint8_t ii = 0; ii < MAX_FREQ_KEYS; ii++) - { - l_freqKeys[ii] = 0; - } -#endif - - // Case statement for each PLL ring - // 1. Set pointer to first array element - // 2. Set array size (# of elements) - switch (i_attrId) - { - case fapi::ATTR_PROC_AB_BNDY_PLL_DATA: - case fapi::ATTR_PROC_AB_BNDY_PLL_FLUSH: - case fapi::ATTR_PROC_AB_BNDY_PLL_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_MURANO) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &S1_10_ATTR_PROC_AB_BNDY_PLL_DATA_array); - l_arySize = sizeof(S1_10_ATTR_PROC_AB_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x13) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &S1_13_ATTR_PROC_AB_BNDY_PLL_DATA_array); - l_arySize = sizeof(S1_13_ATTR_PROC_AB_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &S1_20_ATTR_PROC_AB_BNDY_PLL_DATA_array); - l_arySize = sizeof(S1_20_ATTR_PROC_AB_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &S1_21_ATTR_PROC_AB_BNDY_PLL_DATA_array); - l_arySize = sizeof(S1_21_ATTR_PROC_AB_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - } - else if (l_chipType == ENUM_ATTR_NAME_VENICE) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &P8_10_ATTR_PROC_AB_BNDY_PLL_DATA_array); - l_arySize = sizeof(P8_10_ATTR_PROC_AB_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = - reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *> - ( &P8_20_ATTR_PROC_AB_BNDY_PLL_DATA_array); - l_arySize = - sizeof(P8_20_ATTR_PROC_AB_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - } - else if (l_chipType == ENUM_ATTR_NAME_NAPLES) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &N1_10_ATTR_PROC_AB_BNDY_PLL_DATA_array); - l_arySize = sizeof(N1_10_ATTR_PROC_AB_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - } - break; - case fapi::ATTR_PROC_PB_BNDY_DMIPLL_DATA: - case fapi::ATTR_PROC_PB_BNDY_DMIPLL_FLUSH: - case fapi::ATTR_PROC_PB_BNDY_DMIPLL_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_MURANO) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &S1_10_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array); - l_arySize = sizeof(S1_10_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x13) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &S1_13_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array); - l_arySize = sizeof(S1_13_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &S1_20_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array); - l_arySize = sizeof(S1_20_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &S1_21_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array); - l_arySize = sizeof(S1_21_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array) / - l_arrayEntryLength; - } - } - else if (l_chipType == ENUM_ATTR_NAME_VENICE) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &P8_10_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array); - l_arySize = sizeof(P8_10_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = - reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *> - ( &P8_20_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array); - l_arySize = - sizeof(P8_20_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array) / - l_arrayEntryLength; - } - } - else if (l_chipType == ENUM_ATTR_NAME_NAPLES) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = - reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &N1_10_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array); - l_arySize = - sizeof(N1_10_ATTR_PROC_PB_BNDY_DMIPLL_DATA_array) / - l_arrayEntryLength; - } - } - break; - case fapi::ATTR_PROC_PCI_BNDY_PLL_DATA: - case fapi::ATTR_PROC_PCI_BNDY_PLL_FLUSH: - case fapi::ATTR_PROC_PCI_BNDY_PLL_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_MURANO) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &S1_10_ATTR_PROC_PCI_BNDY_PLL_DATA_array); - l_arySize = sizeof(S1_10_ATTR_PROC_PCI_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x13) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &S1_13_ATTR_PROC_PCI_BNDY_PLL_DATA_array); - l_arySize = sizeof(S1_13_ATTR_PROC_PCI_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &S1_20_ATTR_PROC_PCI_BNDY_PLL_DATA_array); - l_arySize = sizeof(S1_20_ATTR_PROC_PCI_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &S1_21_ATTR_PROC_PCI_BNDY_PLL_DATA_array); - l_arySize = sizeof(S1_21_ATTR_PROC_PCI_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - } - else if (l_chipType == ENUM_ATTR_NAME_VENICE) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &P8_10_ATTR_PROC_PCI_BNDY_PLL_DATA_array); - l_arySize = sizeof(P8_10_ATTR_PROC_PCI_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = - reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *> - ( &P8_20_ATTR_PROC_PCI_BNDY_PLL_DATA_array); - l_arySize = - sizeof(P8_20_ATTR_PROC_PCI_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - } - else if (l_chipType == ENUM_ATTR_NAME_NAPLES) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = - reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &N1_10_ATTR_PROC_PCI_BNDY_PLL_DATA_array); - l_arySize = - sizeof(N1_10_ATTR_PROC_PCI_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - } - break; - case fapi::ATTR_PROC_PERV_BNDY_PLL_DATA: - case fapi::ATTR_PROC_PERV_BNDY_PLL_FLUSH: - case fapi::ATTR_PROC_PERV_BNDY_PLL_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_MURANO) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &S1_10_ATTR_PROC_PERV_BNDY_PLL_DATA_array); - l_arySize = sizeof(S1_10_ATTR_PROC_PERV_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x13) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &S1_13_ATTR_PROC_PERV_BNDY_PLL_DATA_array); - l_arySize = sizeof(S1_13_ATTR_PROC_PERV_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &S1_20_ATTR_PROC_PERV_BNDY_PLL_DATA_array); - l_arySize = sizeof(S1_20_ATTR_PROC_PERV_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &S1_21_ATTR_PROC_PERV_BNDY_PLL_DATA_array); - l_arySize = sizeof(S1_21_ATTR_PROC_PERV_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - } - else if (l_chipType == ENUM_ATTR_NAME_VENICE) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &P8_10_ATTR_PROC_PERV_BNDY_PLL_DATA_array); - l_arySize = sizeof(P8_10_ATTR_PROC_PERV_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = - reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *> - ( &P8_20_ATTR_PROC_PERV_BNDY_PLL_DATA_array); - l_arySize = - sizeof(P8_20_ATTR_PROC_PERV_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - } - else if (l_chipType == ENUM_ATTR_NAME_NAPLES) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = - reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>( - &N1_10_ATTR_PROC_PERV_BNDY_PLL_DATA_array); - l_arySize = - sizeof(N1_10_ATTR_PROC_PERV_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - } - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_FLUSH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_CENTAUR) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_10_ATTR_MEMB_TP_BNDY_PLL_DATA_array); - l_arySize = sizeof(Centaur_10_ATTR_MEMB_TP_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_20_ATTR_MEMB_TP_BNDY_PLL_DATA_array); - l_arySize = sizeof(Centaur_20_ATTR_MEMB_TP_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_21_ATTR_MEMB_TP_BNDY_PLL_DATA_array); - l_arySize = sizeof(Centaur_21_ATTR_MEMB_TP_BNDY_PLL_DATA_array) / - l_arrayEntryLength; - } - } - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_CENTAUR) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA_array); - l_arySize = sizeof(Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA_array); - l_arySize = sizeof(Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA_array); - l_arySize = sizeof(Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA_array) / - l_arrayEntryLength; - } - } - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_CENTAUR) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA_array); - l_arySize = sizeof(Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA_array); - l_arySize = sizeof(Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA_array); - l_arySize = sizeof(Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA_array) / - l_arrayEntryLength; - } - } - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_CENTAUR) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA_array); - l_arySize = sizeof(Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA_array); - l_arySize = sizeof(Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA_array); - l_arySize = sizeof(Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA_array) / - l_arrayEntryLength; - } - } - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_CENTAUR) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA_array); - l_arySize = sizeof(Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA_array); - l_arySize = sizeof(Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA_array); - l_arySize = sizeof(Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA_array) / - l_arrayEntryLength; - } - } - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_CENTAUR) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA_array); - l_arySize = sizeof(Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA_array); - l_arySize = sizeof(Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA_array); - l_arySize = sizeof(Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA_array) / - l_arrayEntryLength; - } - } - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_CENTAUR) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA_array); - l_arySize = sizeof(Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA_array); - l_arySize = sizeof(Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA_array); - l_arySize = sizeof(Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA_array) / - l_arrayEntryLength; - } - } - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_CENTAUR) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA_array); - l_arySize = sizeof(Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA_array); - l_arySize = sizeof(Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA_array); - l_arySize = sizeof(Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA_array) / - l_arrayEntryLength; - } - } - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH: - if (l_chipType == ENUM_ATTR_NAME_CENTAUR) - { - if (l_attrDdLevel == 0x10) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA_array); - l_arySize = sizeof(Centaur_10_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x20) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA_array); - l_arySize = sizeof(Centaur_20_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA_array) / - l_arrayEntryLength; - } - else if (l_attrDdLevel == 0x21) - { - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS *>( - &Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA_array); - l_arySize = sizeof(Centaur_21_ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA_array) / - l_arrayEntryLength; - } - } - break; - default: - FAPI_ERR("getPllRingAttr: Requested attribute not supported. attrId=0x%x", - i_attrId); - FAPI_SET_HWP_ERROR(rc, RC_GET_PLL_RING_ATTR_INVALID_ATTRIBUTE_ID); - }; - - // Exit on error - if (rc) - { - break; - } - - if (l_pllArrayPtr == NULL) - { - FAPI_ERR("getPllRingAttr: Bad chip name (0x%02x) or Bad EC (0x%02x) for attrId 0x%x", - l_chipType, l_attrDdLevel, i_attrId); - FAPI_SET_HWP_ERROR(rc, RC_GET_PLL_RING_ATTR_BAD_CHIP_NAME_EC); - break; - } - - // Loop through array to return requested element - bool l_foundMatch = false; - - // Find array entry for that frequency - for(l_idx = 0; (l_idx < l_arySize) && (!l_foundMatch); l_idx++ ) - { - // For each frequency key to match - if (((l_numKeys == 1) && - (l_pllArrayPtr->l_freq_1 == l_freqKeys[0])) || - ((l_numKeys == 2) && - (l_pllArrayPtr->l_freq_1 == l_freqKeys[0]) && - (l_pllArrayPtr->l_freq_2 == l_freqKeys[1])) || - ((l_numKeys == 4) && - (l_pllArrayPtr->l_freq_1 == l_freqKeys[0]) && - (l_pllArrayPtr->l_freq_2 == l_freqKeys[1]) && - (l_pllArrayPtr->l_freq_3 == l_freqKeys[2]) && - (l_pllArrayPtr->l_freq_4 == l_freqKeys[3]))) - { - FAPI_DBG("getPllRingAttr: Found matching array entry"); - l_foundMatch = true; - } - else - { - // Move to next entry - uint64_t l_rawAddr = reinterpret_cast<uint64_t>(l_pllArrayPtr); - l_rawAddr += l_arrayEntryLength; - l_pllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_4_KEYS*>(l_rawAddr); - } - } - if (l_foundMatch) - { - // Case statement for each attribute (grouped by number - // of keys and attribute type (i.e. data, flush, length) - // 1. Set return attr value - - l_1KeyPllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_1_KEYS *>(l_pllArrayPtr); - l_2KeyPllArrayPtr = reinterpret_cast<const PLL_RING_ATTR_WITH_2_KEYS *>(l_pllArrayPtr); - switch (i_attrId) - { - case fapi::ATTR_PROC_AB_BNDY_PLL_DATA: - //case fapi::ATTR_PROC_AB_BNDY_PLL_FOR_DCCAL_DATA: - case fapi::ATTR_PROC_PB_BNDY_DMIPLL_DATA: - // case fapi::ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA: - case fapi::ATTR_PROC_PCI_BNDY_PLL_DATA: - // Copy ring data - for (uint16_t i = 0; - i < (l_1KeyPllArrayPtr -> l_ATTR_PLL_RING_BYTE_LENGTH); - i++) - { - o_data[i] =l_1KeyPllArrayPtr->l_ATTR_PLL_RING_DATA[i]; - } - break; - case fapi::ATTR_PROC_AB_BNDY_PLL_FLUSH: - case fapi::ATTR_PROC_PB_BNDY_DMIPLL_FLUSH: - case fapi::ATTR_PROC_PCI_BNDY_PLL_FLUSH: - // Copy flush data - for (uint16_t i = 0; - i < (l_1KeyPllArrayPtr -> l_ATTR_PLL_RING_BYTE_LENGTH); - i++) - { - o_data[i] =l_1KeyPllArrayPtr->l_ATTR_PLL_RING_FLUSH[i]; - } - break; - case fapi::ATTR_PROC_AB_BNDY_PLL_LENGTH: - case fapi::ATTR_PROC_PB_BNDY_DMIPLL_LENGTH: - case fapi::ATTR_PROC_PCI_BNDY_PLL_LENGTH: - // Set length - o_ringBitLength = l_1KeyPllArrayPtr -> l_ATTR_PLL_RING_BIT_LENGTH; - break; - case fapi::ATTR_PROC_PERV_BNDY_PLL_DATA: - // Copy ring data - for (uint16_t i = 0; - i < (l_pllArrayPtr -> l_ATTR_PLL_RING_BYTE_LENGTH); - i++) - { - o_data[i] =l_pllArrayPtr->l_ATTR_PLL_RING_DATA[i]; - } - break; - case fapi::ATTR_PROC_PERV_BNDY_PLL_FLUSH: - // Copy flush data - for (uint16_t i = 0; - i < (l_pllArrayPtr -> l_ATTR_PLL_RING_BYTE_LENGTH); - i++) - { - o_data[i] =l_pllArrayPtr->l_ATTR_PLL_RING_FLUSH[i]; - } - break; - case fapi::ATTR_PROC_PERV_BNDY_PLL_LENGTH: - // Set length - o_ringBitLength = l_pllArrayPtr -> l_ATTR_PLL_RING_BIT_LENGTH; - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA: - // Copy ring data - for (uint16_t i = 0; - i < (l_2KeyPllArrayPtr -> l_ATTR_PLL_RING_BYTE_LENGTH); - i++) - { - o_data[i] = l_2KeyPllArrayPtr->l_ATTR_PLL_RING_DATA[i]; - } - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_FLUSH: - // Copy flush data - for (uint16_t i = 0; - i < (l_2KeyPllArrayPtr->l_ATTR_PLL_RING_BYTE_LENGTH); - i++) - { - o_data[i] = l_2KeyPllArrayPtr->l_ATTR_PLL_RING_FLUSH[i]; - } - break; - case fapi::ATTR_MEMB_TP_BNDY_PLL_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH: - case fapi::ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH: - // Set length - o_ringBitLength = l_2KeyPllArrayPtr->l_ATTR_PLL_RING_BIT_LENGTH; - break; - default: - FAPI_ERR("getPllRingAttr: Requested attribute not supported. attrId=0x%x", - i_attrId); - FAPI_SET_HWP_ERROR(rc, RC_GET_PLL_RING_ATTR_INVALID_ATTRIBUTE_ID); - break; - }; - } - else - { - if (l_numKeys == 1) - { - FAPI_ERR("getPllRingAttr: No match found for attrId=0x%x chiptype=0x%x EC=0x%x freq1=%d", - i_attrId, l_chipType, l_attrDdLevel, l_freqKeys[0]); - const uint32_t & FREQ_1 = l_pllArrayPtr->l_freq_1; - FAPI_SET_HWP_ERROR(rc, RC_GET_PLL_RING_ATTR_UNSUPPORTED_FREQ_1); - } - else if (l_numKeys == 2) - { - FAPI_ERR("getPllRingAttr: No match found for attrId=0x%x chiptype=0x%x EC=0x%x", - i_attrId, l_chipType, l_attrDdLevel); - FAPI_ERR("getPllRingAttr: freq1=%d, freq2=%d", l_freqKeys[0], - l_freqKeys[1]); - const uint32_t & FREQ_1 = l_pllArrayPtr->l_freq_1; - const uint32_t & FREQ_2 = l_pllArrayPtr->l_freq_2; - FAPI_SET_HWP_ERROR(rc, RC_GET_PLL_RING_ATTR_UNSUPPORTED_FREQ_2); - } - else - { - FAPI_ERR("getPllRingAttr: No match found for attrId=0x%x chiptype=0x%x EC=0x%x", - i_attrId, l_chipType, l_attrDdLevel); - FAPI_ERR("getPllRingAttr: freq1=%d, freq2=%d, freq3=%d, freq4=%d", - l_freqKeys[0], l_freqKeys[1], l_freqKeys[2], - l_freqKeys[3]); - const uint32_t & FREQ_1 = l_pllArrayPtr->l_freq_1; - const uint32_t & FREQ_2 = l_pllArrayPtr->l_freq_2; - const uint32_t & FREQ_3 = l_pllArrayPtr->l_freq_3; - const uint32_t & FREQ_4 = l_pllArrayPtr->l_freq_4; - FAPI_SET_HWP_ERROR(rc, RC_GET_PLL_RING_ATTR_UNSUPPORTED_FREQ_4); - } - break; - } - } while (0); - - FAPI_DBG("getPllRingAttr: exit rc=0x%08x",static_cast<uint32_t>(rc)); - return rc; -} - -} // extern "C" - diff --git a/src/usr/hwpf/hwp/pll_accessors/getPllRingAttrErrors.xml b/src/usr/hwpf/hwp/pll_accessors/getPllRingAttrErrors.xml deleted file mode 100644 index bbac780fa..000000000 --- a/src/usr/hwpf/hwp/pll_accessors/getPllRingAttrErrors.xml +++ /dev/null @@ -1,115 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/pll_accessors/getPllRingAttrErrors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2014 --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: getPllRingAttrErrors.xml,v 1.2 2014/01/22 14:04:34 mjjones Exp $ --> -<hwpErrors> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_PLL_RING_ATTR_INVALID_ATTRIBUTE_ID</rc> - <description> - Request to get a PLL ring attribute with an invalid Attribute ID - </description> - <ffdc>ATTR_ID</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_PLL_RING_ATTR_BAD_CHIP_NAME_EC</rc> - <description> - Request to get a PLL ring attribute with an unsupported - Processor Chip Name and EC level. The getPllRingAttr Attribute - Accessor needs updating to support this chip. - </description> - <ffdc>ATTR_ID</ffdc> - <ffdc>PROC_CHIP</ffdc> - <ffdc>CHIP_NAME</ffdc> - <ffdc>CHIP_EC</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_PLL_RING_ATTR_UNSUPPORTED_FREQ_1</rc> - <description> - Request to get a PLL ring attribute with an unsupported frequency - attribute. Refer to the generated fapiPllRingAttr.H file to find - which frequency attribute corresponds to FREQ_1 and to find the - supported frequencies - </description> - <ffdc>ATTR_ID</ffdc> - <ffdc>PROC_CHIP</ffdc> - <ffdc>CHIP_NAME</ffdc> - <ffdc>CHIP_EC</ffdc> - <ffdc>FREQ_1</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_PLL_RING_ATTR_UNSUPPORTED_FREQ_2</rc> - <description> - Request to get a PLL ring attribute with an unsupported frequency - attribute. Refer to the generated fapiPllRingAttr.H file to find - which frequency attribute corresponds to FREQ_1/2 and to find the - supported frequencies - </description> - <ffdc>ATTR_ID</ffdc> - <ffdc>PROC_CHIP</ffdc> - <ffdc>CHIP_NAME</ffdc> - <ffdc>CHIP_EC</ffdc> - <ffdc>FREQ_1</ffdc> - <ffdc>FREQ_2</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_PLL_RING_ATTR_UNSUPPORTED_FREQ_4</rc> - <description> - Request to get a PLL ring attribute with an unsupported frequency - attribute. Refer to the generated fapiPllRingAttr.H file to find - which frequency attribute corresponds to FREQ_1/2/3/4 and to find the - supported frequencies - </description> - <ffdc>ATTR_ID</ffdc> - <ffdc>PROC_CHIP</ffdc> - <ffdc>CHIP_NAME</ffdc> - <ffdc>CHIP_EC</ffdc> - <ffdc>FREQ_1</ffdc> - <ffdc>FREQ_2</ffdc> - <ffdc>FREQ_3</ffdc> - <ffdc>FREQ_4</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/pll_accessors/getPllRingInfoAttr.C b/src/usr/hwpf/hwp/pll_accessors/getPllRingInfoAttr.C deleted file mode 100644 index 7530a2556..000000000 --- a/src/usr/hwpf/hwp/pll_accessors/getPllRingInfoAttr.C +++ /dev/null @@ -1,609 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/pll_accessors/getPllRingInfoAttr.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: getPllRingInfoAttr.C,v 1.3 2014/04/23 17:23:40 thi Exp $ -/** - * @file getPllRingInfoAttr.C - * - * @brief Accessor HWP that gets attributes containing information about PLL - * Rings - * - */ - -#include <stdint.h> -#include <fapi.H> -#include <getPllRingInfoAttr.H> - -extern "C" -{ - -/** - * @brief Checks the user's buffer size - * - * @param[in] i_attr Attribute ID (just used for tracing) - * @param[in] i_actualSize Actual buffer size - * @param[in] i_expectedSize Expected buffer size - * - * @return fapi::ReturnCode Indicating success or error - */ -fapi::ReturnCode pllInfoCheckSize(const fapi::getPllRingInfo::Attr i_attr, - const size_t i_actualSize, - const size_t i_expectedSize) -{ - fapi::ReturnCode l_rc; - - if (i_actualSize != i_expectedSize) - { - FAPI_ERR("getPllRingInfoAttr: Incorrect Attribute output buffer size %d:%d:%d", - i_attr, i_actualSize, i_expectedSize); - const fapi::getPllRingInfo::Attr & ATTR_ID = i_attr; - const size_t & ACTUAL_SIZE = i_actualSize; - const size_t & EXPECTED_SIZE = i_expectedSize; - FAPI_SET_HWP_ERROR(l_rc, RC_GET_PLL_RING_INFO_ATTR_INVALID_OUTPUT_SIZE); - } - - return l_rc; -} - -/** - * @brief Returns a chip's name and EC level - * - * @param[in] i_attr Attribute ID (just used for tracing) - * @param[in] i_chip Reference to Chip fapi target - * @param[out] o_name Filled in with the chip name - * @param[out] o_ec Filled in with the chip EC level - * - * @return fapi::ReturnCode Indicating success or error - */ -fapi::ReturnCode pllInfoGetChipNameEc( - const fapi::getPllRingInfo::Attr i_attr, - const fapi::Target & i_chip, - fapi::ATTR_NAME_Type & o_name, - fapi::ATTR_EC_Type & o_ec) -{ - fapi::ReturnCode l_rc; - - // As an Attribute Accessor HWP that needs the chip's name/EC to figure out - // the data to return, it is valid to access these privileged attributes - l_rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME, &i_chip, o_name); - - if (l_rc) - { - FAPI_ERR("getPllRingInfoAttr: error getting ATTR_NAME for attr %d", - i_attr); - } - else - { - l_rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_EC, &i_chip, o_ec); - - if (l_rc) - { - FAPI_ERR("getPllRingInfoAttr: error getting ATTR_EC for attr %d", - i_attr); - } - } - - return l_rc; -} - -/** - * @brief Returns PROC_DMI_CUPLL_PFD360_OFFSET data - * - * This is the offset within a PLL ring of some specific data - * - * @param[in] i_procChip Reference to Processor Chip fapi target - * @param[out] o_pVal Pointer to data buffer filled in with attribute data - * @param[in] i_len Size of o_pVal - * - * @return fapi::ReturnCode Indicating success or error - */ -fapi::ReturnCode get_PROC_DMI_CUPLL_PFD360_OFFSET( - const fapi::Target & i_procChip, - void * o_pVal, - const size_t i_len) -{ - fapi::ATTR_PROC_DMI_CUPLL_PFD360_OFFSET_Type & o_val = - *(reinterpret_cast<fapi::ATTR_PROC_DMI_CUPLL_PFD360_OFFSET_Type *>( - o_pVal)); - - fapi::ReturnCode l_rc = pllInfoCheckSize( - fapi::getPllRingInfo::PROC_DMI_CUPLL_PFD360_OFFSET, i_len, - sizeof(o_val)); - - if (!l_rc) - { - fapi::ATTR_NAME_Type l_name = 0; - fapi::ATTR_EC_Type l_ec = 0; - - l_rc = pllInfoGetChipNameEc( - fapi::getPllRingInfo::PROC_DMI_CUPLL_PFD360_OFFSET, i_procChip, - l_name, l_ec); - - if (!l_rc) - { - // Data supplied by HW team - if ((l_name == fapi::ENUM_ATTR_NAME_MURANO) && - ((l_ec == 0x10) || (l_ec == 0x12) || (l_ec == 0x13) || - (l_ec == 0x20) || (l_ec == 0x21))) - { - o_val[0] = 0; - o_val[1] = 0; - o_val[2] = 0; - o_val[3] = 0; - o_val[4] = 360; - o_val[5] = 407; - o_val[6] = 501; - o_val[7] = 454; - } - else if ((l_name == fapi::ENUM_ATTR_NAME_VENICE) && - ((l_ec == 0x10) || ((l_ec >= 0x20) && (l_ec < 0x30)))) - { - o_val[0] = 430; - o_val[1] = 477; - o_val[2] = 571; - o_val[3] = 524; - o_val[4] = 1359; - o_val[5] = 1406; - o_val[6] = 1500; - o_val[7] = 1453; - } - // TODO RTC: 109249 Check to see if this data is valid for Naples - // It was based off of Murano. - else if ((l_name == fapi::ENUM_ATTR_NAME_NAPLES) && - (l_ec == 0x10)) - { - o_val[0] = 0; - o_val[1] = 0; - o_val[2] = 0; - o_val[3] = 0; - o_val[4] = 360; - o_val[5] = 407; - o_val[6] = 501; - o_val[7] = 454; - } - else - { - FAPI_ERR("get_PROC_DMI_CUPLL_PFD360_OFFSET: No data for Chip Name:EC %d:0x%x", - l_name, l_ec); - const fapi::Target & PROC_CHIP = i_procChip; - const fapi::ATTR_NAME_Type & CHIP_NAME = l_name; - const fapi::ATTR_EC_Type & CHIP_EC = l_ec; - FAPI_SET_HWP_ERROR(l_rc, - RC_GET_PROC_DMI_CUPLL_PFD360_OFFSET_BAD_CHIP_NAME_EC); - } - } - } - - return l_rc; -} - -/** - * @brief Returns PROC_DMI_CUPLL_REFCLKSEL_OFFSET data - * - * This is the offset within a PLL ring of some specific data - * - * @param[in] i_procChip Reference to Processor Chip fapi target - * @param[out] o_pVal Pointer to data buffer filled in with attribute data - * @param[in] i_len Size of o_pVal - * - * @return fapi::ReturnCode Indicating success or error - */ -fapi::ReturnCode get_PROC_DMI_CUPLL_REFCLKSEL_OFFSET( - const fapi::Target & i_procChip, - void * o_pVal, - const size_t i_len) -{ - fapi::ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET_Type & o_val = - *(reinterpret_cast<fapi::ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET_Type *>( - o_pVal)); - - fapi::ReturnCode l_rc = pllInfoCheckSize( - fapi::getPllRingInfo::PROC_DMI_CUPLL_REFCLKSEL_OFFSET, i_len, - sizeof(o_val)); - - if (!l_rc) - { - fapi::ATTR_NAME_Type l_name = 0; - fapi::ATTR_EC_Type l_ec = 0; - - l_rc = pllInfoGetChipNameEc( - fapi::getPllRingInfo::PROC_DMI_CUPLL_REFCLKSEL_OFFSET, i_procChip, - l_name, l_ec); - - if (!l_rc) - { - // Data supplied by HW team - if ((l_name == fapi::ENUM_ATTR_NAME_MURANO) && - ((l_ec == 0x10) || (l_ec == 0x12) || (l_ec == 0x13) || - (l_ec == 0x20) || (l_ec == 0x21))) - { - o_val[0] = 0; - o_val[1] = 0; - o_val[2] = 0; - o_val[3] = 0; - o_val[4] = 318; - o_val[5] = 365; - o_val[6] = 459; - o_val[7] = 412; - } - else if ((l_name == fapi::ENUM_ATTR_NAME_VENICE) && - ((l_ec == 0x10) || ((l_ec >= 0x20) && (l_ec < 0x30)))) - { - o_val[0] = 388; - o_val[1] = 435; - o_val[2] = 529; - o_val[3] = 482; - o_val[4] = 1317; - o_val[5] = 1364; - o_val[6] = 1458; - o_val[7] = 1411; - } - // TODO RTC: 109249 Check to see if this data is valid for Naples - // It was based off of Murano. - else if ((l_name == fapi::ENUM_ATTR_NAME_NAPLES) && - (l_ec == 0x10)) - { - o_val[0] = 0; - o_val[1] = 0; - o_val[2] = 0; - o_val[3] = 0; - o_val[4] = 318; - o_val[5] = 365; - o_val[6] = 459; - o_val[7] = 412; - } - else - { - FAPI_ERR("get_PROC_DMI_CUPLL_REFCLKSEL_OFFSET: No data for Chip Name:EC %d:0x%x", - l_name, l_ec); - const fapi::Target & PROC_CHIP = i_procChip; - const fapi::ATTR_NAME_Type & CHIP_NAME = l_name; - const fapi::ATTR_EC_Type & CHIP_EC = l_ec; - FAPI_SET_HWP_ERROR(l_rc, - RC_GET_PROC_DMI_CUPLL_REFCLKSEL_OFFSET_BAD_CHIP_NAME_EC); - } - } - } - - return l_rc; -} - -/** - * @brief Returns PROC_ABUS_CUPLL_PFD360_OFFSET data - * - * This is the offset within a PLL ring of some specific data - * - * @param[in] i_procChip Reference to Processor Chip fapi target - * @param[out] o_pVal Pointer to data buffer filled in with attribute data - * @param[in] i_len Size of o_pVal - * - * @return fapi::ReturnCode Indicating success or error - */ -fapi::ReturnCode get_PROC_ABUS_CUPLL_PFD360_OFFSET( - const fapi::Target & i_procChip, - void * o_pVal, - const size_t i_len) -{ - fapi::ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET_Type & o_val = - *(reinterpret_cast<fapi::ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET_Type *>( - o_pVal)); - - fapi::ReturnCode l_rc = pllInfoCheckSize( - fapi::getPllRingInfo::PROC_ABUS_CUPLL_PFD360_OFFSET, i_len, - sizeof(o_val)); - - if (!l_rc) - { - fapi::ATTR_NAME_Type l_name = 0; - fapi::ATTR_EC_Type l_ec = 0; - - l_rc = pllInfoGetChipNameEc( - fapi::getPllRingInfo::PROC_ABUS_CUPLL_PFD360_OFFSET, i_procChip, - l_name, l_ec); - - if (!l_rc) - { - // Data supplied by HW team - if ( ((l_name == fapi::ENUM_ATTR_NAME_MURANO) && - ((l_ec == 0x10) || (l_ec == 0x12) || (l_ec == 0x13) || - (l_ec == 0x20) || (l_ec == 0x21))) || - ((l_name == fapi::ENUM_ATTR_NAME_VENICE) && - ((l_ec == 0x10) || ((l_ec >= 0x20) && (l_ec < 0x30)))) || - ((l_name == fapi::ENUM_ATTR_NAME_NAPLES) && - (l_ec == 0x10)) ) - { - o_val[0] = 198; - o_val[1] = 151; - o_val[2] = 104; - } - else - { - FAPI_ERR("get_PROC_ABUS_CUPLL_PFD360_OFFSET: No data for Chip Name:EC %d:0x%x", - l_name, l_ec); - const fapi::Target & PROC_CHIP = i_procChip; - const fapi::ATTR_NAME_Type & CHIP_NAME = l_name; - const fapi::ATTR_EC_Type & CHIP_EC = l_ec; - FAPI_SET_HWP_ERROR(l_rc, - RC_GET_PROC_ABUS_CUPLL_PFD360_OFFSET_BAD_CHIP_NAME_EC); - } - } - } - - return l_rc; -} - -/** - * @brief Returns PROC_ABUS_CUPLL_REFCLKSEL_OFFSET data - * - * This is the offset within a PLL ring of some specific data - * - * @param[in] i_procChip Reference to Processor Chip fapi target - * @param[out] o_pVal Pointer to data buffer filled in with attribute data - * @param[in] i_len Size of o_pVal - * - * @return fapi::ReturnCode Indicating success or error - */ -fapi::ReturnCode get_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET( - const fapi::Target & i_procChip, - void * o_pVal, - const size_t i_len) -{ - fapi::ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET_Type & o_val = - *(reinterpret_cast<fapi::ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET_Type *>( - o_pVal)); - - fapi::ReturnCode l_rc = pllInfoCheckSize( - fapi::getPllRingInfo::PROC_ABUS_CUPLL_REFCLKSEL_OFFSET, i_len, - sizeof(o_val)); - - if (!l_rc) - { - fapi::ATTR_NAME_Type l_name = 0; - fapi::ATTR_EC_Type l_ec = 0; - - l_rc = pllInfoGetChipNameEc( - fapi::getPllRingInfo::PROC_ABUS_CUPLL_REFCLKSEL_OFFSET, i_procChip, - l_name, l_ec); - - if (!l_rc) - { - // TODO RTC: 109249 Check to see if this data is valid for Naples - // It was based off of Murano. - // Data supplied by HW team - if ( ((l_name == fapi::ENUM_ATTR_NAME_MURANO) && - ((l_ec == 0x10) || (l_ec == 0x12) || (l_ec == 0x13) || - (l_ec == 0x20) || (l_ec == 0x21))) || - ((l_name == fapi::ENUM_ATTR_NAME_VENICE) && - ((l_ec == 0x10) || ((l_ec >= 0x20) && (l_ec < 0x30)))) || - ((l_name == fapi::ENUM_ATTR_NAME_NAPLES) && - (l_ec == 0x10)) ) - { - o_val[0] = 156; - o_val[1] = 109; - o_val[2] = 62; - } - else - { - FAPI_ERR("get_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET: No data for Chip Name:EC %d:0x%x", - l_name, l_ec); - const fapi::Target & PROC_CHIP = i_procChip; - const fapi::ATTR_NAME_Type & CHIP_NAME = l_name; - const fapi::ATTR_EC_Type & CHIP_EC = l_ec; - FAPI_SET_HWP_ERROR(l_rc, - RC_GET_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET_BAD_CHIP_NAME_EC); - } - } - } - - return l_rc; -} - -/** - * @brief Returns MEMB_DMI_CUPLL_PFD360_OFFSET data - * - * This is the offset within a PLL ring of some specific data - * - * @param[in] i_membChip Reference to Membuf Chip fapi target - * @param[out] o_pVal Pointer to data buffer filled in with attribute data - * @param[in] i_len Size of o_pVal - * - * @return fapi::ReturnCode Indicating success or error - */ -fapi::ReturnCode get_MEMB_DMI_CUPLL_PFD360_OFFSET( - const fapi::Target & i_membChip, - void * o_pVal, - const size_t i_len) -{ - fapi::ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET_Type & o_val = - *(reinterpret_cast<fapi::ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET_Type *>( - o_pVal)); - - fapi::ReturnCode l_rc = pllInfoCheckSize( - fapi::getPllRingInfo::MEMB_DMI_CUPLL_PFD360_OFFSET, i_len, - sizeof(o_val)); - - if (!l_rc) - { - fapi::ATTR_NAME_Type l_name = 0; - fapi::ATTR_EC_Type l_ec = 0; - - l_rc = pllInfoGetChipNameEc( - fapi::getPllRingInfo::MEMB_DMI_CUPLL_PFD360_OFFSET, i_membChip, - l_name, l_ec); - - if (!l_rc) - { - // Data supplied by HW team - if ((l_name == fapi::ENUM_ATTR_NAME_CENTAUR) && - ((l_ec == 0x10) || (l_ec == 0x20) || (l_ec == 0x21))) - { - o_val = 134; - } - else - { - FAPI_ERR("get_MEMB_DMI_CUPLL_PFD360_OFFSET: No data for Chip Name:EC %d:0x%x", - l_name, l_ec); - const fapi::Target & MEMBUF_CHIP = i_membChip; - const fapi::ATTR_NAME_Type & CHIP_NAME = l_name; - const fapi::ATTR_EC_Type & CHIP_EC = l_ec; - FAPI_SET_HWP_ERROR(l_rc, - RC_GET_MEMB_DMI_CUPLL_PFD360_OFFSET_BAD_CHIP_NAME_EC); - } - } - } - - return l_rc; -} - -/** - * @brief Returns MEMB_DMI_CUPLL_REFCLKSEL_OFFSET data - * - * This is the offset within a PLL ring of some specific data - * - * @param[in] i_membChip Reference to Membuf Chip fapi target - * @param[out] o_pVal Pointer to data buffer filled in with attribute data - * @param[in] i_len Size of o_pVal - * - * @return fapi::ReturnCode Indicating success or error - */ -fapi::ReturnCode get_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET( - const fapi::Target & i_membChip, - void * o_pVal, - const size_t i_len) -{ - fapi::ATTR_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET_Type & o_val = - *(reinterpret_cast<fapi::ATTR_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET_Type *>( - o_pVal)); - - fapi::ReturnCode l_rc = pllInfoCheckSize( - fapi::getPllRingInfo::MEMB_DMI_CUPLL_REFCLKSEL_OFFSET, i_len, - sizeof(o_val)); - - if (!l_rc) - { - fapi::ATTR_NAME_Type l_name = 0; - fapi::ATTR_EC_Type l_ec = 0; - - l_rc = pllInfoGetChipNameEc( - fapi::getPllRingInfo::MEMB_DMI_CUPLL_REFCLKSEL_OFFSET, i_membChip, - l_name, l_ec); - - if (!l_rc) - { - // Data supplied by HW team - if ((l_name == fapi::ENUM_ATTR_NAME_CENTAUR) && - ((l_ec == 0x10) || (l_ec == 0x20) || (l_ec == 0x21))) - { - o_val = 92; - } - else - { - FAPI_ERR("get_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET: No data for Chip Name:EC %d:0x%x", - l_name, l_ec); - const fapi::Target & MEMBUF_CHIP = i_membChip; - const fapi::ATTR_NAME_Type & CHIP_NAME = l_name; - const fapi::ATTR_EC_Type & CHIP_EC = l_ec; - FAPI_SET_HWP_ERROR(l_rc, - RC_GET_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET_BAD_CHIP_NAME_EC); - } - } - } - - return l_rc; -} - -/** - * @brief Returns MEMB_MEM_PLL_CFG_UPDATE_OFFSET data - * - * This is the scan chain position of MEM PLL PLLCTRL1(44) bit in tp_pll_bndy - * chain (Offset from beginning of chain) - * - * @param[in] i_membChip Reference to Membuf Chip fapi target - * @param[out] o_pVal Pointer to data buffer filled in with attribute data - * @param[in] i_len Size of o_pVal - * - * @return fapi::ReturnCode Indicating success or error - */ -fapi::ReturnCode get_MEMB_MEM_PLL_CFG_UPDATE_OFFSET( - const fapi::Target & i_membChip, - void * o_pVal, - const size_t i_len) -{ - fapi::ATTR_MEMB_MEM_PLL_CFG_UPDATE_OFFSET_Type & o_val = - *(reinterpret_cast<fapi::ATTR_MEMB_MEM_PLL_CFG_UPDATE_OFFSET_Type *>( - o_pVal)); - - fapi::ReturnCode l_rc = pllInfoCheckSize( - fapi::getPllRingInfo::MEMB_MEM_PLL_CFG_UPDATE_OFFSET, i_len, - sizeof(o_val)); - - if (!l_rc) - { - o_val = 322; // for all current Centaur ECs - } - return l_rc; -} - -//----------------------------------------------------------------------------- -// getPllRingInfoAttr HWP - See header file for details -//----------------------------------------------------------------------------- -fapi::ReturnCode getPllRingInfoAttr(const fapi::Target & i_chip, - const fapi::getPllRingInfo::Attr i_attr, - void * o_pVal, - const size_t i_len) -{ - fapi::ReturnCode l_rc; - - switch (i_attr) - { - case fapi::getPllRingInfo::PROC_DMI_CUPLL_PFD360_OFFSET: - l_rc = get_PROC_DMI_CUPLL_PFD360_OFFSET(i_chip, o_pVal, i_len); - break; - case fapi::getPllRingInfo::PROC_DMI_CUPLL_REFCLKSEL_OFFSET: - l_rc = get_PROC_DMI_CUPLL_REFCLKSEL_OFFSET(i_chip, o_pVal, i_len); - break; - case fapi::getPllRingInfo::PROC_ABUS_CUPLL_PFD360_OFFSET: - l_rc = get_PROC_ABUS_CUPLL_PFD360_OFFSET(i_chip, o_pVal, i_len); - break; - case fapi::getPllRingInfo::PROC_ABUS_CUPLL_REFCLKSEL_OFFSET: - l_rc = get_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET(i_chip, o_pVal, i_len); - break; - case fapi::getPllRingInfo::MEMB_DMI_CUPLL_PFD360_OFFSET: - l_rc = get_MEMB_DMI_CUPLL_PFD360_OFFSET(i_chip, o_pVal, i_len); - break; - case fapi::getPllRingInfo::MEMB_DMI_CUPLL_REFCLKSEL_OFFSET: - l_rc = get_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET(i_chip, o_pVal, i_len); - break; - case fapi::getPllRingInfo::MEMB_MEM_PLL_CFG_UPDATE_OFFSET: - l_rc = get_MEMB_MEM_PLL_CFG_UPDATE_OFFSET(i_chip, o_pVal, i_len); - break; - default: - FAPI_ERR("getPllRingInfoAttr: Invalid Attribute ID 0x%02x", i_attr); - const fapi::getPllRingInfo::Attr & ATTR_ID = i_attr; - FAPI_SET_HWP_ERROR(l_rc, - RC_GET_PLL_RING_INFO_ATTR_INVALID_ATTRIBUTE_ID); - } - - return l_rc; -} - -} diff --git a/src/usr/hwpf/hwp/pll_accessors/getPllRingInfoAttrErrors.xml b/src/usr/hwpf/hwp/pll_accessors/getPllRingInfoAttrErrors.xml deleted file mode 100644 index 675b8666f..000000000 --- a/src/usr/hwpf/hwp/pll_accessors/getPllRingInfoAttrErrors.xml +++ /dev/null @@ -1,147 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/pll_accessors/getPllRingInfoAttrErrors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2013,2014 --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: getPllRingInfoAttrErrors.xml,v 1.1 2013/12/05 18:23:56 mjjones Exp $ --> -<hwpErrors> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_PLL_RING_INFO_ATTR_INVALID_ATTRIBUTE_ID</rc> - <description> - Request to get PLL ring Info with invalid attribute ID. Code bug - </description> - <ffdc>ATTR_ID</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_PLL_RING_INFO_ATTR_INVALID_OUTPUT_SIZE</rc> - <description> - Request to get PLL ring Info with invalid output buffer size. Code bug - </description> - <ffdc>ATTR_ID</ffdc> - <ffdc>ACTUAL_SIZE</ffdc> - <ffdc>EXPECTED_SIZE</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_PROC_DMI_CUPLL_PFD360_OFFSET_BAD_CHIP_NAME_EC</rc> - <description> - Request to get ATTR_PROC_DMI_CUPLL_PFD360_OFFSET with an unsupported - Processor Chip Name and EC level. The getPllRingInfoAttr Attribute - Accessor needs updating to support this chip. - </description> - <ffdc>PROC_CHIP</ffdc> - <ffdc>CHIP_NAME</ffdc> - <ffdc>CHIP_EC</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_PROC_DMI_CUPLL_REFCLKSEL_OFFSET_BAD_CHIP_NAME_EC</rc> - <description> - Request to get ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET with an unsupported - Processor Chip Name and EC level. The getPllRingInfoAttr Attribute - Accessor needs updating to support this chip. - </description> - <ffdc>PROC_CHIP</ffdc> - <ffdc>CHIP_NAME</ffdc> - <ffdc>CHIP_EC</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_PROC_ABUS_CUPLL_PFD360_OFFSET_BAD_CHIP_NAME_EC</rc> - <description> - Request to get ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET with an unsupported - Processor Chip Name and EC level. The getPllRingInfoAttr Attribute - Accessor needs updating to support this chip. - </description> - <ffdc>PROC_CHIP</ffdc> - <ffdc>CHIP_NAME</ffdc> - <ffdc>CHIP_EC</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET_BAD_CHIP_NAME_EC</rc> - <description> - Request to get ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET with an unsupported - Processor Chip Name and EC level. The getPllRingInfoAttr Attribute - Accessor needs updating to support this chip. - </description> - <ffdc>PROC_CHIP</ffdc> - <ffdc>CHIP_NAME</ffdc> - <ffdc>CHIP_EC</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_MEMB_DMI_CUPLL_PFD360_OFFSET_BAD_CHIP_NAME_EC</rc> - <description> - Request to get ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET with an unsupported - Processor Chip Name and EC level. The getPllRingInfoAttr Attribute - Accessor needs updating to support this chip. - </description> - <ffdc>MEMBUF_CHIP</ffdc> - <ffdc>CHIP_NAME</ffdc> - <ffdc>CHIP_EC</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ********************************************************************* --> - <hwpError> - <rc>RC_GET_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET_BAD_CHIP_NAME_EC</rc> - <description> - Request to get ATTR_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET with an unsupported - Processor Chip Name and EC level. The getPllRingInfoAttr Attribute - Accessor needs updating to support this chip. - </description> - <ffdc>MEMBUF_CHIP</ffdc> - <ffdc>CHIP_NAME</ffdc> - <ffdc>CHIP_EC</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/pll_accessors/pll.mk b/src/usr/hwpf/hwp/pll_accessors/pll.mk deleted file mode 100644 index beb364b26..000000000 --- a/src/usr/hwpf/hwp/pll_accessors/pll.mk +++ /dev/null @@ -1,31 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/hwpf/hwp/pll_accessors/pll.mk $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2013,2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/pll_accessors - -VPATH += ${HWPPATH}/pll_accessors -CFLAGS += $(if $(CONFIG_VPO_COMPILE),-DFAPI_SIMULATION,) -OBJS += getPllRingAttr.o -OBJS += getPllRingInfoAttr.o - diff --git a/src/usr/hwpf/hwp/pll_attributes/centaur_10_pll_ring.attributes b/src/usr/hwpf/hwp/pll_attributes/centaur_10_pll_ring.attributes deleted file mode 100644 index a315a1bbe..000000000 --- a/src/usr/hwpf/hwp/pll_attributes/centaur_10_pll_ring.attributes +++ /dev/null @@ -1,2377 +0,0 @@ -# $Id: centaur_10_pll_ring.attributes,v 1.13 2014/09/23 22:01:00 jmcgill Exp $ -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x0000000000000000000000000000040000010000000000000001200070008051A79000000000000040008000001D960C00A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13CB1402001C0009000000000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0060D3700000020004000000 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x04 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA7 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x1D -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x0C -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1066 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD1044000201000000000000200024007000C052C430000000008000400080000014961800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D2500000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1333 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD1044000201000000000000200024007000C052C430000000008000400080000019161400A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0050D1300000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1600 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD1044000201000000000000200024007000C052C430000000008000400080000019161800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D1300000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1866 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD1044000201000000000000200024007000C052C43000000000800040008000001B561500A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0150D5B00000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x1B -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x56 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x15 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1066 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD10440002010000000000002000200060008051A430000000008000400080000014961800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D2500000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1333 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD10440002010000000000002000200060008051A430000000008000400080000019161400A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0050D1300000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1600 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD10440002010000000000002000200060008051A430000000008000400080000019161800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D1300000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1866 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD10440002010000000000002000200060008051A43000000000800040008000001B561500A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0150D5B00000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x1B -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x56 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x15 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1066 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA = 0x000000000000000000000000FD1044000201000000000000200024007000C052C430000000008000400080000014961800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D2500000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[45] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1333 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA = 0x000000000000000000000000FD1044000201000000000000200024007000C052C430000000008000400080000019161400A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0050D1300000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[47] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1600 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA = 0x000000000000000000000000FD1044000201000000000000200024007000C052C430000000008000400080000019161800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D1300000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1866 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA = 0x000000000000000000000000FD1044000201000000000000200024007000C052C43000000000800040008000001B561500A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0150D5B00000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[45] u8[80] 0x1B -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[46] u8[80] 0x56 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[47] u8[80] 0x15 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1066 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA = 0x000000000000000000000000FD10440002010000000000002000200060008051A430000000008000400080000014961800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D2500000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[45] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1333 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA = 0x000000000000000000000000FD10440002010000000000002000200060008051A430000000008000400080000019161400A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0050D1300000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[47] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1600 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA = 0x000000000000000000000000FD10440002010000000000002000200060008051A430000000008000400080000019161800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D1300000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1866 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA = 0x000000000000000000000000FD10440002010000000000002000200060008051A43000000000800040008000001B561500A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000100 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0150D5B00000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[17] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[45] u8[80] 0x1B -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[46] u8[80] 0x56 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[47] u8[80] 0x15 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - diff --git a/src/usr/hwpf/hwp/pll_attributes/centaur_20_pll_ring.attributes b/src/usr/hwpf/hwp/pll_attributes/centaur_20_pll_ring.attributes deleted file mode 100644 index 32e87610c..000000000 --- a/src/usr/hwpf/hwp/pll_attributes/centaur_20_pll_ring.attributes +++ /dev/null @@ -1,2377 +0,0 @@ -# $Id: centaur_20_pll_ring.attributes,v 1.9 2014/09/23 22:01:17 jmcgill Exp $ -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x0000000000000000000000000000040000000000000000000001200070008051A79000000000000040008000001D960C00A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13CB1402001C0009000000000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0060D3700000020004000000 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x04 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA7 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x1D -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x0C -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1066 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C430000000008000400080000014961800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D2500000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1333 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C430000000008000400080000019161400A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0050D1300000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1600 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C430000000008000400080000019161800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D1300000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1866 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C43000000000800040008000001B561500A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0150D5B00000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x1B -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x56 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x15 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1066 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A430000000008000400080000014961800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D2500000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1333 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A430000000008000400080000019161400A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0050D1300000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1600 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A430000000008000400080000019161800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D1300000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1866 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A43000000000800040008000001B561500A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0150D5B00000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x1B -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x56 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x15 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1066 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C430000000008000400080000014961800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D2500000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[45] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1333 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C430000000008000400080000019161400A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0050D1300000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[47] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1600 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C430000000008000400080000019161800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D1300000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1866 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C43000000000800040008000001B561500A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0150D5B00000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[45] u8[80] 0x1B -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[46] u8[80] 0x56 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[47] u8[80] 0x15 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1066 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A430000000008000400080000014961800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D2500000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[45] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1333 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A430000000008000400080000019161400A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0050D1300000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[47] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1600 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A430000000008000400080000019161800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D1300000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1866 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A43000000000800040008000001B561500A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0150D5B00000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[45] u8[80] 0x1B -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[46] u8[80] 0x56 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[47] u8[80] 0x15 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - diff --git a/src/usr/hwpf/hwp/pll_attributes/centaur_21_pll_ring.attributes b/src/usr/hwpf/hwp/pll_attributes/centaur_21_pll_ring.attributes deleted file mode 100644 index 4f52c8af4..000000000 --- a/src/usr/hwpf/hwp/pll_attributes/centaur_21_pll_ring.attributes +++ /dev/null @@ -1,2377 +0,0 @@ -# $Id: centaur_21_pll_ring.attributes,v 1.2 2014/09/24 14:34:32 jmcgill Exp $ -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x0000000000000000000000000000040000000000000000000001200070008051A79000000000000040008000001D960C00A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13CB1402001C0009000000000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0060D3700000020004000000 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x04 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x01 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA7 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x1D -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x0C -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1066 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C430000000008000400080000014961800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D2500000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1333 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C430000000008000400080000019161400A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0050D1300000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1600 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C430000000008000400080000019161800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D1300000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1866 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C43000000000800040008000001B561500A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0150D5B00000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x1B -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x56 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x15 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1066 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A430000000008000400080000014961800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D2500000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1333 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A430000000008000400080000019161400A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0050D1300000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1600 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A430000000008000400080000019161800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D1300000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#MEMB_MEM_FREQ = 1866 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A43000000000800040008000001B561500A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0150D5B00000020004000200 -#ATTR_MEMB_TP_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[45] u8[80] 0x1B -ATTR_MEMB_TP_BNDY_PLL_DATA[46] u8[80] 0x56 -ATTR_MEMB_TP_BNDY_PLL_DATA[47] u8[80] 0x15 -ATTR_MEMB_TP_BNDY_PLL_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_DATA[79] u8[80] 0x00 - -ATTR_MEMB_TP_BNDY_PLL_FLUSH[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[12] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[13] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[14] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[16] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[24] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[26] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[28] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[30] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[31] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[32] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[33] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[38] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[40] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[42] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[45] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[46] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[47] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[49] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[52] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[53] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_FLUSH[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1066 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C430000000008000400080000014961800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D2500000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[45] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1333 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C430000000008000400080000019161400A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0050D1300000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[47] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1600 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C430000000008000400080000019161800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D1300000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1866 -#MEMB_NEST_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA = 0x000000000000000000000000FD1044000200000000000000200024007000C052C43000000000800040008000001B561500A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x18469406001C0048000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0150D5B00000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[26] u8[80] 0x24 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[28] u8[80] 0x70 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[30] u8[80] 0xC0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[31] u8[80] 0x52 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[32] u8[80] 0xC4 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[45] u8[80] 0x1B -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[46] u8[80] 0x56 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[47] u8[80] 0x15 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1066 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A430000000008000400080000014961800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D2500000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[45] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[46] u8[80] 0x96 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1333 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A430000000008000400080000019161400A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0050D1300000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[47] u8[80] 0x14 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1600 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A430000000008000400080000019161800A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0030D1300000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[45] u8[80] 0x19 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[46] u8[80] 0x16 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[47] u8[80] 0x18 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#GEN_FLUSH=NO -#MEMB_MEM_FREQ = 1866 -#MEMB_NEST_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH = 442 -#ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA = 0x000000000000000000000000FD10440002000000000000002000200060008051A43000000000800040008000001B561500A000000290000 -# DMI.DMIPLL.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x184B1402000C0008000800000000000000 -# DMI.RX.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# PLLMEM.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0150D5B00000020004000200 -#------------------------------------------------------------------------------- Attribute View - -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH u32 442 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[0] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[1] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[2] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[3] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[4] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[5] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[6] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[7] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[8] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[9] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[10] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[11] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[12] u8[80] 0xFD -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[13] u8[80] 0x10 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[14] u8[80] 0x44 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[15] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[16] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[17] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[18] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[19] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[20] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[21] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[22] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[23] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[24] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[25] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[26] u8[80] 0x20 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[27] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[28] u8[80] 0x60 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[29] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[30] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[31] u8[80] 0x51 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[32] u8[80] 0xA4 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[33] u8[80] 0x30 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[34] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[35] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[36] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[37] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[38] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[39] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[40] u8[80] 0x40 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[41] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[42] u8[80] 0x80 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[43] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[44] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[45] u8[80] 0x1B -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[46] u8[80] 0x56 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[47] u8[80] 0x15 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[48] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[49] u8[80] 0xA0 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[50] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[51] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[52] u8[80] 0x02 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[53] u8[80] 0x90 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[54] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[55] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[56] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[57] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[58] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[59] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[60] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[61] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[62] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[63] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[64] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[65] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[66] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[67] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[68] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[69] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[70] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[71] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[72] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[73] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[74] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[75] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[76] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[77] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[78] u8[80] 0x00 -ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA[79] u8[80] 0x00 -#===============================================================================END Entry - diff --git a/src/usr/hwpf/hwp/pll_attributes/n1_10_pll_ring.attributes b/src/usr/hwpf/hwp/pll_attributes/n1_10_pll_ring.attributes deleted file mode 100644 index c1a7adf89..000000000 --- a/src/usr/hwpf/hwp/pll_attributes/n1_10_pll_ring.attributes +++ /dev/null @@ -1,4069 +0,0 @@ -# $Id: n1_10_pll_ring.attributes,v 1.5 2015/02/12 19:13:09 jmcgill Exp $ -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000008000800180040146E740000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x173B1401000C0008000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xE7 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000080009001C003015D1740000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x5D -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000080009001C003014B1740000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2000 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000080009001C003014B1740000000000000022000A00060012051BB90000000000000022000A00060012051BB9000000000000000200024007000C052C590000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x24 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x52 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xC5 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000080048001C00201469740000000000000022001A00070008051A790000000000000022001A00070008051A790000000000000002000200060008051A610000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13CB1402001C000B000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13CB1402001C000B000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174B1402001C0009000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0x97 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA7 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xA7 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xA6 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x10 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2400 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 812 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x0000000000000000000000000000000000001000000C0000025B32000000000000000001000000C0000025B32000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# NVBUS0.PLL.PLL22.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13369000000C0000020000000000000000 -# NVBUS1.PLL.PLL22.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13369000000C0000020000000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 812 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x0C -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x5B -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x32 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0xC0 -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x25 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0xB3 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x20 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 812 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x0000000000000000000000000000000001001000000C0000023732000000000000001001000000C0000023732000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# NVBUS0.PLL.PLL22.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1000000C0000020020000000000000 -# NVBUS1.PLL.PLL22.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1000000C0000020020000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 812 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x0C -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x37 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x32 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0xC0 -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x23 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x73 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x20 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 812 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x0000000000000000000000000000000001001000000C0000023732000000000000001001000000C0000023732000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# NVBUS0.PLL.PLL22.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1000000C0000020020000000000000 -# NVBUS1.PLL.PLL22.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1000000C0000020020000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 812 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x0C -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x37 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x32 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0xC0 -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x23 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x73 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x20 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1896 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FD1044000201FA2088000403F44110000807E8822000100000000000000100012003800602962C80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007E8822000100FD1044000201FA2088000403F4411000080000000000000080009001C003014B16400000000000000000000000000000000000000000000000000000 -# IOMC0.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1896 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0xF4 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x41 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x07 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0xE8 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0x82 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x06 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x96 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x2C -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0xF4 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x41 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x90 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x4B -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x16 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1896 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FD1044000201FA2088000403F44110000807E88220001000000000000001000100030008028DC180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007E8822000100FD1044000201FA2088000403F441100008000000000000008000800180040146E0C00000000000000000000000000000000000000000000000000000 -# IOMC0.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x183B1401000C0008000800000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x183B1401000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1896 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0xF4 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x41 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x07 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0xE8 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0x82 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x8D -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0xC1 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0xF4 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x41 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x46 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0xE0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1896 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000008000000000010000000000020000000000000000001000100030004028D308000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000004000000000008000000000010000000000000000000800080018002014698400000000000000000000000000000000000000000000000000000 -# IOMC0.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC0.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC0.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC0.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC0.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1896 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x8D -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x30 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x46 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x98 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_PCIE_FREQ = 1000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 653 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x00000000000000000000000000000000000000000000000000000000000000000AAB0F0050000081480000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128100000A00F0D5500000000000000000 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 653 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x0A -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0xAB -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x0F -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x50 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x81 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x48 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 653 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x00000000000000000000000000000000000000000000000000000000004000000BBB0C8050000001480000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0130DDD00000020000000000 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 653 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x40 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x0B -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0xBB -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x0C -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x80 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x50 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x01 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x48 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - diff --git a/src/usr/hwpf/hwp/pll_attributes/p8_10_pll_ring.attributes b/src/usr/hwpf/hwp/pll_attributes/p8_10_pll_ring.attributes deleted file mode 100644 index 337492d88..000000000 --- a/src/usr/hwpf/hwp/pll_attributes/p8_10_pll_ring.attributes +++ /dev/null @@ -1,4313 +0,0 @@ -# $Id: p8_10_pll_ring.attributes,v 1.12 2014/11/13 20:19:33 szhong Exp $ -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000008000800180040146E740000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x173B1401000C0008000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xE7 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000080009001C003015D1740000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x5D -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000080009001C003014B1740000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2000 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000080009001C003014B1740000000000000022000A00060012051BB90000000000000022000A00060012051BB9000000000000000200024007000C052C590000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x24 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x52 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xC5 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000080048001C00201469740000000000000002001A000700080454790000000000000002001A000700080454790000000000000002000200060008051A610000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13C54402001C000B000800000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13C54402001C000B000800000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174B1402001C0009000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0x97 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x45 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0x47 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x45 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x47 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xA6 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x10 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2400 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602CE2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17473406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2C -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xE2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2666 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602BB2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174DD406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xB2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602BA2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xA2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x0000000000000000000001000000000002000000000004000000000000000000100010003800402BA30800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10C5D402001C0008000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x04 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x40 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xA3 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0x08 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1848 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FD1044000201FA2088000403F44110000807E8822000100000000000000100012003800602962C80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007E8822000100FD1044000201FA2088000403F4411000080000000000000080009001C003014B16400000000000000000000000000000000000000000000000000000 -# IOMC0.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1848 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0xF4 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x41 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x07 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0xE8 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x82 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x06 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x96 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x2C -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0xF4 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x41 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x90 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x4B -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x16 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1848 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FD1044000201FA2088000403F44110000807E88220001000000000000001000100030008028DC180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007E8822000100FD1044000201FA2088000403F441100008000000000000008000800180040146E0C00000000000000000000000000000000000000000000000000000 -# IOMC0.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x183B1401000C0008000800000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x183B1401000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1848 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0xF4 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x41 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x07 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0xE8 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x82 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x8D -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0xC1 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0xF4 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x41 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x46 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0xE0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1848 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000008000000000010000000000020000000000000000001000100030004028D308000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000004000000000008000000000010000000000000000000800080018002014698400000000000000000000000000000000000000000000000000000 -# IOMC0.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC0.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC0.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC0.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC0.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1848 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x8D -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x30 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x46 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x98 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_PCIE_FREQ = 1000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 565 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000002AAC3C0140000205200000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128100000A00F0D5500000000000000000 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 565 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x02 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0xAA -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0xC3 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0xC0 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x14 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x20 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x52 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 565 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000000000000010000002EEC320140000005200000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0130DDD00000020000000000 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 565 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x10 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x02 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0xEE -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0xC3 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0x20 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x14 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x52 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - diff --git a/src/usr/hwpf/hwp/pll_attributes/p8_20_pll_ring.attributes b/src/usr/hwpf/hwp/pll_attributes/p8_20_pll_ring.attributes deleted file mode 100644 index 0106d540b..000000000 --- a/src/usr/hwpf/hwp/pll_attributes/p8_20_pll_ring.attributes +++ /dev/null @@ -1,4313 +0,0 @@ -# $Id: p8_20_pll_ring.attributes,v 1.7 2014/11/13 20:20:50 szhong Exp $ -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000008000800180040146E740000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x173B1401000C0008000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xE7 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000080009001C003015D1740000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x5D -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000080009001C003014B1740000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2000 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000080009001C003014B1740000000000000022000A00060012051BB90000000000000022000A00060012051BB9000000000000000200024007000C052C590000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x24 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x52 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xC5 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 855 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000080048001C00201469740000000000000022001A00070008051A790000000000000022001A00070008051A790000000000000002000200060008051A610000000000000000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13CB1402001C000B000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13CB1402001C000B000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174B1402001C0009000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 855 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0x97 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA7 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0xA7 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0xA6 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x10 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2400 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602CE2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17473406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2C -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xE2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2666 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602BB2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174DD406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xB2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602BA2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xA2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x0000000000000000000001000000000002000000000004000000000000000000100010003800402BA30800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10C5D402001C0008000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x04 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x40 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xA3 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0x08 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1848 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FD1044000201FA2088000403F44110000807E8822000100000000000000100012003800602962C80000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007E8822000100FD1044000201FA2088000403F4411000080000000000000080009001C003014B16400000000000000000000000000000000000000000000000000000 -# IOMC0.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1848 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0xF4 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x41 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x07 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0xE8 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x82 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x06 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x96 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x2C -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0xF4 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x41 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x90 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x4B -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x16 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1848 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000FD1044000201FA2088000403F44110000807E88220001000000000000001000100030008028DC180000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000007E8822000100FD1044000201FA2088000403F441100008000000000000008000800180040146E0C00000000000000000000000000000000000000000000000000000 -# IOMC0.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC0.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x183B1401000C0008000800000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x183B1401000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1848 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0xF4 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x41 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x07 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0xE8 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x82 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x8D -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0xC1 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0xF4 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x41 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x46 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0xE0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1848 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000000008000000000010000000000020000000000000000001000100030004028D308000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002000000000004000000000008000000000010000000000000000000800080018002014698400000000000000000000000000000000000000000000000000000 -# IOMC0.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC0.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC0.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC0.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC0.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1848 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x03 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x8D -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x30 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x46 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x98 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_PCIE_FREQ = 1000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 565 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000002AAC3C0140000205200000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128100000A00F0D5500000000000000000 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 565 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x02 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0xAA -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0xC3 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0xC0 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x14 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x20 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x52 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 565 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000000000000010000002EEC320140000005200000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0130DDD00000020000000000 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 565 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x10 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x02 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0xEE -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0xC3 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0x20 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x14 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x52 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - diff --git a/src/usr/hwpf/hwp/pll_attributes/s1_10_pll_ring.attributes b/src/usr/hwpf/hwp/pll_attributes/s1_10_pll_ring.attributes deleted file mode 100644 index dd4ce007d..000000000 --- a/src/usr/hwpf/hwp/pll_attributes/s1_10_pll_ring.attributes +++ /dev/null @@ -1,4298 +0,0 @@ -# $Id: s1_10_pll_ring.attributes,v 1.24 2014/11/13 20:22:06 szhong Exp $ -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B99000000000000000008000800180040146E740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x173B1401000C0008000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0xE7 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000080009801C003015D1740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C00C8000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x98 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x5D -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000080009801C003014B1740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C00C8000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x98 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2000 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB9000000000000000200024007000C052C590000000000000000080009801C003014B1740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C00C8000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x24 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x52 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xC5 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x98 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000002001A000700080454790000000000000002001A000700080454790000000000000002000200060008051A610000000000000000080048001C00201469740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13C54402001C000B000800000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13C54402001C000B000800000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174B1402001C0009000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x45 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x47 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x45 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x47 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xA6 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x10 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x97 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2400 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602CE2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17473406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2C -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xE2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2666 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602BB2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174DD406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xB2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602BA2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xA2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x0000000000000000000001000000000002000000000004000000000000000000100010003800402BA30800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10C5D402001C0008000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x04 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x40 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xA3 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0x08 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1234 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000003F44110000807E8822000100FD1044000201FA208800040000000000000040004800E00180A58B2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1234 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x3F -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x11 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x48 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0xE0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0xA5 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x8B -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1234 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000003F44110000807E8822000100FD1044000201FA208800040000000000000040004000C00200A3706000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x183B1401000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1234 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x3F -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x11 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0xA3 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x70 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x60 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1234 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000200000000000400000000000800000000000000000040004000C00100A34C2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1234 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0xA3 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x4C -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_PCIE_FREQ = 1000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 565 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000001000000000000002AAC3C0140000005200000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A00F0D5500000000000000200 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 565 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0x10 -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x02 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0xAA -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0xC3 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0xC0 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x14 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x52 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 565 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000000000000010000002EEC320140000005200000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0130DDD00000020000000000 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 565 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x10 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x02 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0xEE -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0xC3 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0x20 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x14 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x52 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - diff --git a/src/usr/hwpf/hwp/pll_attributes/s1_13_pll_ring.attributes b/src/usr/hwpf/hwp/pll_attributes/s1_13_pll_ring.attributes deleted file mode 100644 index 1f6ec1c56..000000000 --- a/src/usr/hwpf/hwp/pll_attributes/s1_13_pll_ring.attributes +++ /dev/null @@ -1,4298 +0,0 @@ -# $Id: s1_13_pll_ring.attributes,v 1.12 2014/11/13 20:22:49 szhong Exp $ -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B99000000000000000008000800180040146E740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x173B1401000C0008000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0xE7 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000080009801C003015D1740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C00C8000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x98 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x5D -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000080009801C003014B1740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C00C8000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x98 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2000 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB9000000000000000200024007000C052C590000000000000000080009801C003014B1740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C00C8000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x24 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x52 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xC5 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x98 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000002001A000700080454790000000000000002001A000700080454790000000000000002000200060008051A610000000000000000080048001C00201469740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13C54402001C000B000800000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13C54402001C000B000800000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174B1402001C0009000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x45 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x47 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x45 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x47 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xA6 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x10 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x97 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2400 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602CE2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17473406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2C -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xE2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2666 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602BB2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174DD406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xB2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602BA2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xA2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x0000000000000000000001000000000002000000000004000000000000000000100010003800402BA30800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10C5D402001C0008000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x04 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x40 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xA3 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0x08 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1234 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000003F44110000807E8822000100FD1044000201FA208800040000000000000040004800E00180A58B2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1234 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x3F -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x11 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x48 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0xE0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0xA5 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x8B -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1234 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000003F44110000807E8822000100FD1044000201FA208800040000000000000040004000C00200A3706000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x183B1401000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1234 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x3F -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x11 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0xA3 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x70 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x60 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1234 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000200000000000400000000000800000000000000000040004000C00100A34C2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1234 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0xA3 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x4C -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_PCIE_FREQ = 1000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 565 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000001000000000000002AAC3C0140000005200000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A00F0D5500000000000000200 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 565 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0x10 -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x02 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0xAA -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0xC3 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0xC0 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x14 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x52 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 565 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000000000000010000002EEC320140000005200000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0130DDD00000020000000000 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 565 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x10 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x02 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0xEE -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0xC3 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0x20 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x14 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x52 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - diff --git a/src/usr/hwpf/hwp/pll_attributes/s1_20_pll_ring.attributes b/src/usr/hwpf/hwp/pll_attributes/s1_20_pll_ring.attributes deleted file mode 100644 index 4fcdbc825..000000000 --- a/src/usr/hwpf/hwp/pll_attributes/s1_20_pll_ring.attributes +++ /dev/null @@ -1,4298 +0,0 @@ -# $Id: s1_20_pll_ring.attributes,v 1.14 2014/11/13 20:24:46 szhong Exp $ -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B99000000000000000008000800180040146E740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x173B1401000C0008000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0xE7 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000080009001C003015D1740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x5D -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000080009001C003014B1740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2000 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB9000000000000000200024007000C052C590000000000000000080009001C003014B1740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x24 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x52 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xC5 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000002001A000700080454790000000000000002001A000700080454790000000000000002000200060008051A610000000000000000080048001C00201469740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13C54402001C000B000800000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13C54402001C000B000800000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174B1402001C0009000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x45 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0x47 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x45 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0x47 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xA6 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x10 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x97 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2400 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602CE2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17473406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2C -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xE2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2666 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602BB2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174DD406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xB2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602BA2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xA2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x0000000000000000000001000000000002000000000004000000000000000000100010003800402BA30800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10C5D402001C0008000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x04 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x40 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xA3 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0x08 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1234 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000003F44110000807E8822000100FD1044000201FA208800040000000000000040004800E00180A58B2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1234 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x3F -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x11 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x48 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0xE0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0xA5 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x8B -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1234 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000003F44110000807E8822000100FD1044000201FA208800040000000000000040004000C00200A3706000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x183B1401000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1234 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x3F -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x11 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0xA3 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x70 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x60 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1234 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000200000000000400000000000800000000000000000040004000C00100A34C2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1234 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0xA3 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x4C -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_PCIE_FREQ = 1000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 565 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000001000000000000002AAC3C0140000005200000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A00F0D5500000000000000200 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 565 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0x10 -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x02 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0xAA -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0xC3 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0xC0 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x14 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x52 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 565 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000000000000010000002EEC320140000005200000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0130DDD00000020000000000 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 565 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x10 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x02 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0xEE -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0xC3 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0x20 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x14 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x52 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - diff --git a/src/usr/hwpf/hwp/pll_attributes/s1_21_pll_ring.attributes b/src/usr/hwpf/hwp/pll_attributes/s1_21_pll_ring.attributes deleted file mode 100644 index 01ef03bfd..000000000 --- a/src/usr/hwpf/hwp/pll_attributes/s1_21_pll_ring.attributes +++ /dev/null @@ -1,4298 +0,0 @@ -# $Id: s1_21_pll_ring.attributes,v 1.13 2014/11/13 20:26:12 szhong Exp $ -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B99000000000000000008000800180040146E740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x173B1401000C0008000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0xE7 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000080009001C003015D1740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x5D -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2400 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB90000000000000002000200060010051B990000000000000000080009001C003014B1740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x133B1401000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xB9 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_NEST_FREQ = 2000 -#PU_PCIE_REF_CLOCK = 100 -#PU_REF_CLOCK = 133 -#PU_XBUS_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022000A00060012051BB90000000000000022000A00060012051BB9000000000000000200024007000C052C590000000000000000080009001C003014B1740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13BB1409000C000A000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17469406001C0048000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xBB -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x24 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x52 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xC5 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x03 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x4B -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x17 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PERV_BNDY_PLL_LENGTH = 861 -#ATTR_PROC_PERV_BNDY_PLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000022001A00070008051A790000000000000022001A00070008051A790000000000000002000200060008051A610000000000000000080048001C00201469740000000000000000000000000000000 -# TPFLEX.PLLEMFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13CB1402001C000B000880000000000000 -# TPFLEX.PLLNEST.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -# TPFLEX.PLLNESTFLT.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13CB1402001C000B000880000000000000 -# TPFLEX.PLLXB.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174B1402001C0009000800000000000000 -#ATTR_PROC_PERV_BNDY_PLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PERV_BNDY_PLL_LENGTH u32 861 -ATTR_PROC_PERV_BNDY_PLL_DATA[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[30] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[31] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[32] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[33] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[35] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[37] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[38] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[39] u8[128] 0xA7 -ATTR_PROC_PERV_BNDY_PLL_DATA[40] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[47] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[48] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[49] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[50] u8[128] 0xA0 -ATTR_PROC_PERV_BNDY_PLL_DATA[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[52] u8[128] 0x70 -ATTR_PROC_PERV_BNDY_PLL_DATA[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[54] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[55] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[56] u8[128] 0xA7 -ATTR_PROC_PERV_BNDY_PLL_DATA[57] u8[128] 0x90 -ATTR_PROC_PERV_BNDY_PLL_DATA[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[65] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[67] u8[128] 0x20 -ATTR_PROC_PERV_BNDY_PLL_DATA[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[69] u8[128] 0x60 -ATTR_PROC_PERV_BNDY_PLL_DATA[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[71] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[72] u8[128] 0x51 -ATTR_PROC_PERV_BNDY_PLL_DATA[73] u8[128] 0xA6 -ATTR_PROC_PERV_BNDY_PLL_DATA[74] u8[128] 0x10 -ATTR_PROC_PERV_BNDY_PLL_DATA[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[83] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[84] u8[128] 0x04 -ATTR_PROC_PERV_BNDY_PLL_DATA[85] u8[128] 0x80 -ATTR_PROC_PERV_BNDY_PLL_DATA[86] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[87] u8[128] 0xC0 -ATTR_PROC_PERV_BNDY_PLL_DATA[88] u8[128] 0x02 -ATTR_PROC_PERV_BNDY_PLL_DATA[89] u8[128] 0x01 -ATTR_PROC_PERV_BNDY_PLL_DATA[90] u8[128] 0x46 -ATTR_PROC_PERV_BNDY_PLL_DATA[91] u8[128] 0x97 -ATTR_PROC_PERV_BNDY_PLL_DATA[92] u8[128] 0x40 -ATTR_PROC_PERV_BNDY_PLL_DATA[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_DATA[127] u8[128] 0x00 - -ATTR_PROC_PERV_BNDY_PLL_FLUSH[0] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[1] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[2] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[3] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[4] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[5] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[6] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[7] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[8] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[9] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[10] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[11] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[12] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[13] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[14] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[15] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[16] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[17] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[18] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[19] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[20] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[21] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[22] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[23] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[24] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[25] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[26] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[27] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[28] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[29] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[30] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[31] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[32] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[33] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[34] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[35] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[36] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[37] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[38] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[39] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[40] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[41] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[42] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[43] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[44] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[45] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[46] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[47] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[48] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[49] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[50] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[51] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[52] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[53] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[54] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[55] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[56] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[57] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[58] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[59] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[60] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[61] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[62] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[63] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[64] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[65] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[66] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[67] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[68] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[69] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[70] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[71] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[72] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[73] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[74] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[75] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[76] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[77] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[78] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[79] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[80] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[81] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[82] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[83] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[84] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[85] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[86] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[87] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[88] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[89] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[90] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[91] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[92] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[93] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[94] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[95] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[96] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[97] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[98] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[99] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[100] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[101] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[102] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[103] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[104] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[105] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[106] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[107] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[108] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[109] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[110] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[111] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[112] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[113] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[114] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[115] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[116] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[117] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[118] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[119] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[120] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[121] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[122] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[123] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[124] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[125] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[126] u8[128] 0x00 -ATTR_PROC_PERV_BNDY_PLL_FLUSH[127] u8[128] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2400 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602CE2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x17473406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2C -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xE2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 2666 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602BB2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x174DD406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xB2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_ABUS_FREQ = 3200 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x00000000000000003F44110000807E8822000100FD1044000200000000000000100012003800602BA2E800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x1745D406001C0048000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x3F -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x11 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x80 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x7E -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x88 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x22 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0xFD -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x44 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x12 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x60 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xA2 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0xE8 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_AB_BNDY_PLL_LENGTH = 536 -#ATTR_PROC_AB_BNDY_PLL_DATA = 0x0000000000000000000001000000000002000000000004000000000000000000100010003800402BA30800000000000000000000000000000000000000000000000000 -# ABUS.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# ABUS.TX_WRAP.PLL_A.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10C5D402001C0008000800000000000000 -#ATTR_PROC_AB_BNDY_PLL_FLUSH = 0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_AB_BNDY_PLL_LENGTH u32 536 -ATTR_PROC_AB_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[10] u8[110] 0x01 -ATTR_PROC_AB_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[16] u8[110] 0x02 -ATTR_PROC_AB_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[22] u8[110] 0x04 -ATTR_PROC_AB_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[32] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[34] u8[110] 0x10 -ATTR_PROC_AB_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[36] u8[110] 0x38 -ATTR_PROC_AB_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[38] u8[110] 0x40 -ATTR_PROC_AB_BNDY_PLL_DATA[39] u8[110] 0x2B -ATTR_PROC_AB_BNDY_PLL_DATA[40] u8[110] 0xA3 -ATTR_PROC_AB_BNDY_PLL_DATA[41] u8[110] 0x08 -ATTR_PROC_AB_BNDY_PLL_DATA[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_AB_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_AB_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1234 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000003F44110000807E8822000100FD1044000201FA208800040000000000000040004800E00180A58B2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x13469406001C0048000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1234 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x3F -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x11 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x48 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0xE0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0xA5 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x8B -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_DMI_FREQ = 4800 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1234 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000003F44110000807E8822000100FD1044000201FA208800040000000000000040004000C00200A3706000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x800044117E00 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x183B1401000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1234 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x3F -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x11 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x80 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x7E -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x22 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0xFD -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x10 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x44 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0xFA -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x88 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0xA3 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x70 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x60 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PB_BNDY_DMIPLL_LENGTH = 1234 -#ATTR_PROC_PB_BNDY_DMIPLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000200000000000400000000000800000000000000000040004000C00100A34C2000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -# IOMC1.RX0.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX1.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX2.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.RX3.RXCLKCTL.CFG_LAT.NLC.L2(0:46) 0x000040000000 -# IOMC1.TX_WRAP.PLL_MCIO.CWRAP.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x10CB1402000C0008000800000000000000 -#ATTR_PROC_PB_BNDY_DMIPLL_FLUSH = 0x000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PB_BNDY_DMIPLL_LENGTH u32 1234 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[42] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[48] u8[240] 0x02 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[54] u8[240] 0x04 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[60] u8[240] 0x08 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[70] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[72] u8[240] 0x40 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[74] u8[240] 0xC0 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[75] u8[240] 0x01 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[77] u8[240] 0xA3 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[78] u8[240] 0x4C -ATTR_PROC_PB_BNDY_DMIPLL_DATA[79] u8[240] 0x20 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_DATA[239] u8[240] 0x00 - -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[0] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[1] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[2] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[3] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[4] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[5] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[6] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[7] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[8] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[9] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[10] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[11] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[12] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[13] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[14] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[15] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[16] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[17] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[18] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[19] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[20] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[21] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[22] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[23] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[24] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[25] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[26] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[27] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[28] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[29] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[30] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[31] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[32] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[33] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[34] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[35] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[36] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[37] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[38] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[39] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[40] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[41] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[42] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[43] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[44] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[45] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[46] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[47] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[48] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[49] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[50] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[51] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[52] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[53] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[54] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[55] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[56] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[57] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[58] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[59] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[60] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[61] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[62] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[63] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[64] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[65] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[66] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[67] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[68] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[69] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[70] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[71] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[72] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[73] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[74] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[75] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[76] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[77] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[78] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[79] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[80] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[81] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[82] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[83] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[84] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[85] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[86] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[87] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[88] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[89] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[90] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[91] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[92] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[93] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[94] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[95] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[96] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[97] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[98] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[99] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[100] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[101] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[102] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[103] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[104] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[105] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[106] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[107] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[108] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[109] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[110] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[111] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[112] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[113] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[114] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[115] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[116] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[117] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[118] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[119] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[120] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[121] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[122] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[123] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[124] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[125] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[126] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[127] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[128] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[129] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[130] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[131] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[132] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[133] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[134] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[135] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[136] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[137] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[138] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[139] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[140] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[141] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[142] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[143] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[144] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[145] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[146] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[147] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[148] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[149] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[150] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[151] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[152] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[153] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[154] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[155] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[156] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[157] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[158] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[159] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[160] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[161] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[162] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[163] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[164] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[165] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[166] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[167] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[168] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[169] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[170] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[171] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[172] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[173] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[174] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[175] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[176] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[177] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[178] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[179] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[180] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[181] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[182] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[183] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[184] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[185] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[186] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[187] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[188] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[189] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[190] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[191] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[192] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[193] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[194] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[195] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[196] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[197] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[198] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[199] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[200] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[201] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[202] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[203] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[204] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[205] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[206] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[207] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[208] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[209] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[210] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[211] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[212] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[213] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[214] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[215] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[216] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[217] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[218] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[219] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[220] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[221] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[222] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[223] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[224] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[225] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[226] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[227] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[228] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[229] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[230] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[231] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[232] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[233] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[234] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[235] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[236] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[237] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[238] u8[240] 0x00 -ATTR_PROC_PB_BNDY_DMIPLL_FLUSH[239] u8[240] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=HW -#PU_PCIE_FREQ = 1000 -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 565 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000001000000000000002AAC3C0140000005200000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A00F0D5500000000000000200 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 565 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0x10 -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x02 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0xAA -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0xC3 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0xC0 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x14 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x52 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - -#===============================================================================BEGIN Entry -# -#ENV=SIM -#------------------------------------------------------------------------------- Ring String View -#ATTR_PROC_PCI_BNDY_PLL_LENGTH = 565 -#ATTR_PROC_PCI_BNDY_PLL_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000000000000010000002EEC320140000005200000000000000000000000000000000000000000000 -# TPFLEX.PLLPCIE.PLLCTL.C_PLL_CNTRL_LEAF.CFG_LAT.NLC.L2(0:135) 0x128000000A0130DDD00000020000000000 -#ATTR_PROC_PCI_BNDY_PLL_FLUSH = 0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -#------------------------------------------------------------------------------- Attribute View - -ATTR_PROC_PCI_BNDY_PLL_LENGTH u32 565 -ATTR_PROC_PCI_BNDY_PLL_DATA[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[37] u8[110] 0x10 -ATTR_PROC_PCI_BNDY_PLL_DATA[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[40] u8[110] 0x02 -ATTR_PROC_PCI_BNDY_PLL_DATA[41] u8[110] 0xEE -ATTR_PROC_PCI_BNDY_PLL_DATA[42] u8[110] 0xC3 -ATTR_PROC_PCI_BNDY_PLL_DATA[43] u8[110] 0x20 -ATTR_PROC_PCI_BNDY_PLL_DATA[44] u8[110] 0x14 -ATTR_PROC_PCI_BNDY_PLL_DATA[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[48] u8[110] 0x52 -ATTR_PROC_PCI_BNDY_PLL_DATA[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_DATA[109] u8[110] 0x00 - -ATTR_PROC_PCI_BNDY_PLL_FLUSH[0] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[1] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[2] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[3] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[4] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[5] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[6] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[7] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[8] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[9] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[10] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[11] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[12] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[13] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[14] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[15] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[16] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[17] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[18] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[19] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[20] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[21] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[22] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[23] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[24] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[25] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[26] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[27] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[28] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[29] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[30] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[31] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[32] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[33] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[34] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[35] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[36] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[37] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[38] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[39] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[40] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[41] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[42] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[43] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[44] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[45] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[46] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[47] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[48] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[49] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[50] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[51] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[52] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[53] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[54] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[55] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[56] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[57] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[58] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[59] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[60] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[61] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[62] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[63] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[64] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[65] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[66] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[67] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[68] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[69] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[70] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[71] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[72] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[73] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[74] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[75] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[76] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[77] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[78] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[79] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[80] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[81] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[82] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[83] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[84] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[85] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[86] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[87] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[88] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[89] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[90] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[91] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[92] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[93] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[94] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[95] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[96] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[97] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[98] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[99] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[100] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[101] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[102] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[103] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[104] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[105] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[106] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[107] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[108] u8[110] 0x00 -ATTR_PROC_PCI_BNDY_PLL_FLUSH[109] u8[110] 0x00 -#===============================================================================END Entry - diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml deleted file mode 100644 index 0201d6f97..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml +++ /dev/null @@ -1,62 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_check_master_errors.xml,v 1.3 2014/07/23 19:51:49 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_check_master --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_CHECK_MASTER_NO_VALID_MCS</rc> - <description> - Procedure: proc_sbe_check_master - Both MCL/MCR fences asserted, no functional MCS units are available for use on master chip. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_SBE_CHECK_MASTER</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <registerFfdc> - <id>REG_FFDC_SBE_CHECK_MASTER</id> - <scomRegister>NEST_GP0_0x02000000</scomRegister> - <scomRegister>DEVICE_ID_REG_0x000F000F</scomRegister> - </registerFfdc> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml deleted file mode 100644 index 72cfce8be..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml +++ /dev/null @@ -1,87 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_chiplet_init_errors.xml,v 1.3 2014/07/23 19:51:49 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_chiplet_init.S --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_MPIPL_CLOCK_START_ERROR</rc> - <description> - Procedure: proc_sbe_chiplet_init - Check that clocks were started to allow AISS access for PCB Fencing failed - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P1</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_MPIPL_PBC_FENCE_TIMEOUT_ERROR</rc> - <description> - Procedure: proc_sbe_chiplet_init - Check that the PCB Fence was raised for MPIPL reset failed - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_MPIPL_SECURITY_UNLOCK_ERROR</rc> - <description> - Procedure: proc_sbe_chiplet_init - The security function failed to unlock for MPIPL restart - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P1</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml deleted file mode 100644 index 0b0aa0e23..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml +++ /dev/null @@ -1,193 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_decompress_scan_halt_codes.xml,v 1.4 2014/07/23 19:51:49 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_decompress_scan.S --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SCAN_MULTICAST_TYPE_ERROR</rc> - <description> - Subroutine: proc_sbe_decompress_scan - The subroutine was given a chiplet Id that is a multicast chiplet, - however it is not a multicast WRITE type as required. The bad chiplet Id - will be found in P0 at the halt. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SCAN_MAGIC_MISMATCH</rc> - <description> - Subroutine: proc_sbe_decompress_scan - The subroutine was passed a data structure whose magic number was - incorrect. The magic number of the data structure can be found in PORE - register D0. The most likely cause of this error is a problem with the - tool chain used to build the SBE IPL images. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SCAN_HEADER_VERSION_ERROR</rc> - <description> - Subroutine: proc_sbe_decompress_scan - The subroutine was passed a data structure whose header version is - different from the one the code was expecting. The header version of the - data structure can be found in PORE register D0. The most likely cause of - this error is a problem with the tool chain used to build the SBE IPL - images. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> - <callout> - <target>CHIP</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SCAN_DATA_SIZE_ERROR</rc> - <description> - Subroutine: proc_sbe_decompress_scan - Each scan data structure contains the total expected size of the - structure, however in this case the compressed scan string required - either more or less data than indicated in the header. The PORE register - D0 contains the number (signed) of excess doublewords. The most likely - cause of this error is a problem with the tool chain used to build the - SBE IPL images. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> - <callout> - <target>CHIP</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SCAN_RING_LENGTH_ERROR</rc> - <description> - Subroutine: proc_sbe_decompress_scan - The number of bits scanned does not match the ring length stored in the - scan data header. The PORE register D0 contains the number (signed) of - excess bits. The most likely cause of this error is a problem with the - tool chain used to build the SBE IPL images. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> - <callout> - <target>CHIP</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SCAN_CHECKWORD_ERROR</rc> - <description> - Subroutine: proc_sbe_decompress_scan - The initial checkword did not rotate back into the scan data register at - the completion of the scan. The contents of the PORE D0 register have - been loaded with the received checkword, whose value may provide a clue - as to what happened. The expected value is 0xa5a55a5a00000000. This error - could be caused by broken hardware, or by any tool problem that would - misrepresent the length of the actual hardware scan ring. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml deleted file mode 100644 index a36fd1c70..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml +++ /dev/null @@ -1,53 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_ex_dpll_setup_halt_codes.xml,v 1.3 2014/07/23 19:51:49 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_ex_dpll_setup.S --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_DPLL_SETUP_NOLOCK</rc> - <description> - Procedure: proc_sbe_ex_dpll_setup - This error is signalled when the EX DPLL fails to lock after ~150us. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_DPLL_LOCK_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE </procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml deleted file mode 100644 index 1797f7107..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml +++ /dev/null @@ -1,70 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_ex_startclocks_errors.xml,v 1.2 2014/07/23 19:51:49 jmcgill Exp $ --> -<!-- Error definitions for proc_sbe_ex_startclocks procedure --> -<hwpErrors> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_EX_STARTCLOCKS_CLOCKS_NOT_STARTED</rc> - <description> - Procedure: proc_sbe_ex_startclocks - After trying to start all of the EX clocks, some of the tholds were still high - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_EX_STARTCLOCKS_CHIP_XSTOPPED</rc> - <description> - Procedure: proc_sbe_ex_startclocks - After starting the EX clocks the system was xstopped - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml deleted file mode 100644 index 3cab561af..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml +++ /dev/null @@ -1,87 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_fabricinit_errors.xml,v 1.4 2014/07/23 19:51:49 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_fabricinit --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_FABRICINIT_FBC_STOPPED_ERR</rc> - <description> - Procedure: proc_sbe_fabricinit - Fabric init sequence not attempted, fabric arbitration is stopped. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_SBE_FABRICINIT</id> - <target>CHIP</target> - </collectRegisterFfdc> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_FABRICINIT_ERR</rc> - <description> - Procedure: proc_sbe_fabricinit - Fabric init failed, or mismatch in expected ADU status. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_SBE_FABRICINIT</id> - <target>CHIP</target> - </collectRegisterFfdc> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <registerFfdc> - <id>REG_FFDC_SBE_FABRICINIT</id> - <scomRegister>PB_MODE_CENT_0x02010C4A</scomRegister> - <scomRegister>PB_HP_MODE_NEXT_CENT_0x02010C4B</scomRegister> - <scomRegister>PB_HP_MODE_CURR_CENT_0x02010C4C</scomRegister> - <scomRegister>PB_HPX_MODE_NEXT_CENT_0x02010C4D</scomRegister> - <scomRegister>PB_HPX_MODE_CURR_CENT_0x02010C4E</scomRegister> - <scomRegister>ADU_PMISC_MODE_0x0202000B</scomRegister> - </registerFfdc> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml deleted file mode 100644 index 4479fa5d4..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml +++ /dev/null @@ -1,88 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_instruct_start_errors.xml,v 1.5 2014/07/23 19:51:49 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_instruct_start --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_INSTR_START_SPWU_FAILED</rc> - <description> - Procedure: proc_sbe_instruct_start - Special wakeup before starting instructions failed. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_INSTRUCT_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_INSTR_START_THREAD0_NOT_RUNNING</rc> - <description> - Procedure: proc_sbe_instruct_start - Thread 0 is still in nap/sleep/winkle after the instruct start - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_INSTRUCT_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_INSTR_START_MAINT_MODE</rc> - <description> - Procedure: proc_sbe_instruct_start - Can't start instructions because the core is still in maintenance mode. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_INSTRUCT_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml deleted file mode 100644 index 6b6405f07..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml +++ /dev/null @@ -1,277 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_lco_loader_errors.xml,v 1.4 2014/07/23 19:51:49 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_lco_loader --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_LCO_LOADER_MULTICAST_ERR</rc> - <description> - Procedure: proc_sbe_lco_loader - Attempted to execute procedure with cv_multicast option. - </description> - <sbeError/> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_LCO_LOADER_FBC_STOPPED_ERR</rc> - <description> - Procedure: proc_sbe_lco_loader - LCO load sequence not attempted, fabric arbitration is stopped. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_SBE_FABRICINIT</id> - <target>CHIP</target> - </collectRegisterFfdc> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_LCO_LOADER_IMAGE_SIZE_PAD_ERR</rc> - <description> - Procedure: proc_sbe_lco_loader - Hostboot image size is not evenly divisible by cacheline size. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_LCO_LOADER_IMAGE_SIZE_OVERFLOW_ERR</rc> - <description> - Procedure: proc_sbe_lco_loader - Hostboot image size is larger than master chiplet cache size. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_LCO_LOADER_IMAGE_WRAP_ERR</rc> - <description> - Procedure: proc_sbe_lco_loader - Combination of target base address and hostboot image size will wrap OCB address. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_LCO_LOADER_IMAGE_ALIGN_ERR</rc> - <description> - Procedure: proc_sbe_lco_loader - Target base address is not cacheline aligned. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_LCO_LOADER_PBA_RESET_ERR</rc> - <description> - Procedure: proc_sbe_lco_loader - PBA slave reset still in progress or buffer is busy. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_LCO_LOADER_LPCM_FIR_ERR</rc> - <description> - Procedure: proc_sbe_lco_loader - LPCM FIR register was non-zero after PNOR read. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_LCO_LOADER_OCB_STATUS_ERR</rc> - <description> - Procedure: proc_sbe_lco_loader - Unexpected state in OCB Status Control Register at end of write stream. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_LCO_LOADER_PBA_FIR_ERR</rc> - <description> - Procedure: proc_sbe_lco_loader - Unexpected state in PBA FIR Register at end of write stream. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_LCO_LOADER_PBA_WBUF0_ERR</rc> - <description> - Procedure: proc_sbe_lco_loader - Unexpected state in PBA Write Buffer0 Register at end of write stream. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_LCO_LOADER_PBA_WBUF1_ERR</rc> - <description> - Procedure: proc_sbe_lco_loader - Unexpected state in PBA Write Buffer1 Register at end of write stream. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_PBA_UTILS_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml deleted file mode 100644 index ae455f87e..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml +++ /dev/null @@ -1,153 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_npll_setup_errors.xml,v 1.5 2014/07/23 19:51:49 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_npll_setup --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_NPLL_SETUP_CPFILT_NOLOCK</rc> - <description> - Procedure: proc_sbe_npll_setup - CP Filter PLL failed to lock. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SBE_NPLL_SETUP_FILTER_PLL</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <hw> - <hwid>PROC_REF_CLOCK</hwid> - <refTarget>CHIP</refTarget> - </hw> - <priority>HIGH</priority> - </callout> - <callout> - <target>CHIP</target> - <priority>MEDIUM</priority> - </callout> - <callout> - <procedure>CODE </procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_NPLL_SETUP_EMFILT_NOLOCK</rc> - <description> - Procedure: proc_sbe_npll_setup - EM Filter PLL failed to lock. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SBE_NPLL_SETUP_FILTER_PLL</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <hw> - <hwid>PROC_REF_CLOCK</hwid> - <refTarget>CHIP</refTarget> - </hw> - <priority>HIGH</priority> - </callout> - <callout> - <target>CHIP</target> - <priority>MEDIUM</priority> - </callout> - <callout> - <procedure>CODE </procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_NPLL_SETUP_XBUS_NOLOCK</rc> - <description> - Procedure: proc_sbe_npll_setup - X-Bus PLL failed to lock. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SBE_NPLL_SETUP_XBUS_PLL</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <hw> - <hwid>PROC_REF_CLOCK</hwid> - <refTarget>CHIP</refTarget> - </hw> - <priority>HIGH</priority> - </callout> - <callout> - <target>CHIP</target> - <priority>MEDIUM</priority> - </callout> - <callout> - <procedure>CODE </procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <registerFfdc> - <id>REG_FFDC_PROC_SBE_NPLL_SETUP_FILTER_PLL</id> - <cfamRegister>CFAM_FSI_GP3_0x00002812</cfamRegister> - <cfamRegister>CFAM_FSI_GP4_0x00002813</cfamRegister> - <cfamRegister>CFAM_FSI_GP6_0x00002815</cfamRegister> - <cfamRegister>CFAM_FSI_GP7_0x00002816</cfamRegister> - <scomRegister>TP_PLL_LOCK_0x010F0019</scomRegister> - </registerFfdc> - <!-- ******************************************************************** --> - <registerFfdc> - <id>REG_FFDC_PROC_SBE_NPLL_SETUP_XBUS_PLL</id> - <cfamRegister>CFAM_FSI_GP3_0x00002812</cfamRegister> - <cfamRegister>CFAM_FSI_GP4_0x00002813</cfamRegister> - <cfamRegister>CFAM_FSI_GP6_0x00002815</cfamRegister> - <cfamRegister>CFAM_FSI_GP7_0x00002816</cfamRegister> - <cfamRegister>CFAM_FSI_GP3_MIRROR_0x0000281B</cfamRegister> - <scomRegister>X_PLLLOCKREG_0x040F0019</scomRegister> - </registerFfdc> - <!-- ******************************************************************** --> -</hwpErrors> - - - diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml deleted file mode 100644 index 26ab416a7..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml +++ /dev/null @@ -1,49 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_pb_startclocks.xml,v 1.3 2014/07/23 19:51:49 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_pb_startclocks --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>PROC_SBE_PB_START_CLOCK_ERROR</rc> - <description> - Procedure: proc_sbe_pb_startclocks - Failed to start clocks on PB chiplet. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_NEST_CHIPLET</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml deleted file mode 100644 index 4db5b30b9..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml +++ /dev/null @@ -1,134 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_pibmem_loader_halt_codes.xml,v 1.3 2014/07/23 19:51:50 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_pibmem_loader.S --> -<hwpErrors> - <hwpError> - <rc>RC_SBE_PIBMEM_PRE_ERROR</rc> - <description> - Procedure: proc_sbe_pibmem_loader - The PIBMEM either shows error status or is not in the idle state prior to - the execution of the procedure. The contents of the PIBMEM Status - Register are in D0 at the time of the halt. Resetting the PIBMEM prior - to running proc_sbe_pibmem_loader should clear up this error. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PIBMEM_POST_ERROR</rc> - <description> - Procedure: proc_sbe_pibmem_loader - The PIBMEM either shows error status or is not in the idle state after - execution of the procedure. The contents of the PIBMEM Status Register - are in D0 at the time of the halt. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PIBMEM_IMAGE_SIZE_ALIGNMENT</rc> - <description> - Procedure: proc_sbe_pibmem_loader - The size of the PIBMEM image to load is not a multiple of 8 bytes, which - is a hard requirement due to the PORE architecture. The image size passed - to the procedure can be found in SPRG0. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PIBMEM_LOAD_ADDRESS_ALIGNMENT</rc> - <description> - Procedure: proc_sbe_pibmem_loader - The load address of the PIBMEM image is not a multiple of 8 bytes, which - is a hard requirement due to the PORE architecture. The load address - passed to the procedure can be found in SPRG0. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PIBMEM_OVERFLOW</rc> - <description> - Procedure: proc_sbe_pibmem_loader - The load address and size of the PIBMEM image would overflow the physical - PIBMEM. The image size (in bytes) passed to the procedure is in SPRG0; - D1 contains the PIBMEM load address passed to the procedure. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml deleted file mode 100644 index 2b5299ca1..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml +++ /dev/null @@ -1,121 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_scominit_errors.xml,v 1.7 2014/07/23 19:51:50 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_scomint.S --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_WINKLE_STATE_OR_ERROR</rc> - <description> - Procedure: proc_sbe_scominit - Check of winkle state across all IPLed chiplets using READ-OR failed. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> - <basedOnPresentChildren> - <target>CHIP</target> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> - </basedOnPresentChildren> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_WINKLE_STATE_AND_ERROR</rc> - <description> - Procedure: proc_sbe_scominit - Check of winkle state across all IPLed chiplets using READ-AND failed. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> - <basedOnPresentChildren> - <target>CHIP</target> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> - </basedOnPresentChildren> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_WINKLE_FSM_TIMEOUT_ERROR</rc> - <description> - Procedure: proc_sbe_scominit - Polling of Idle FSM timed out. - </description> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> - <basedOnPresentChildren> - <target>CHIP</target> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> - </basedOnPresentChildren> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <sbeError/> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_WINKLE_PFET_TIMEOUT_ERROR</rc> - <description> - Procedure: proc_sbe_scominit - Polling of PFET controller for idle timed out. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> - <basedOnPresentChildren> - <target>CHIP</target> - <childType>TARGET_TYPE_EX_CHIPLET</childType> - <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> - </basedOnPresentChildren> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_select_ex_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_select_ex_errors.xml deleted file mode 100644 index 2d9bfe1ba..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_select_ex_errors.xml +++ /dev/null @@ -1,88 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_select_ex_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_select_ex_errors.xml,v 1.3 2014/07/23 19:51:50 jmcgill Exp $ --> -<!-- Error definitions for proc_sbe_select_ex procedure --> -<hwpErrors> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_SELECT_EX_NO_GOOD_BOOT_CORES_FOUND</rc> - <description> - Procedure: proc_sbe_select_ex - None of the valid boot cores are enabled - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_SBE_SELECT_EX</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_SELECT_EX_NO_SECOND_GOOD_BOOT_CORE_FOUND</rc> - <description> - Procedure: proc_sbe_select_ex - Skipped the first good boot core and no other good boot core was found - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_SBE_SELECT_EX</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <registerFfdc> - <id>REG_FFDC_SBE_SELECT_EX</id> - <scomRegister>EX_PARTIAL_GOOD_0x520F0012</scomRegister> - </registerFfdc> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml deleted file mode 100644 index c2317fbed..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml +++ /dev/null @@ -1,98 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_setup_evid_errors.xml,v 1.4 2014/07/23 19:51:50 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_setup_evid --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SET_VID_TIMEOUT</rc> - <description> - Procedure: proc_sbe_setup_evid - Setting EVID during boot timed out on the SPIVID bus - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_O2S_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SPIVID_STATUS_ERROR</rc> - <description> - Procedure: proc_sbe_setup_evid - Errors detected in O2S Status Reg setting Boot Voltage - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_O2S_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SPIVID_WRITE_RETURN_STATUS_ERROR</rc> - <description> - Procedure: proc_sbe_setup_evid - SPIVID Device did not return good status the Boot Voltage Write operation - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_O2S_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml deleted file mode 100644 index 60a0f106e..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml +++ /dev/null @@ -1,83 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_tp_switch_gears_errors.xml,v 1.3 2014/07/23 19:51:50 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_tp_switch_gears --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_TP_SWITCH_GEARS_XBUS_NOLOCK</rc> - <description> - Procedure: proc_sbe_tp_switch_gears - X-Bus PLL failed to lock (Murano DD1.x workaround). - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_SBE_NPLL_SETUP_XBUS_PLL</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <hw> - <hwid>PROC_REF_CLOCK</hwid> - <refTarget>CHIP</refTarget> - </hw> - <priority>HIGH</priority> - </callout> - <callout> - <target>CHIP</target> - <priority>MEDIUM</priority> - </callout> - <callout> - <procedure>CODE </procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_TP_SWITCH_GEARS_XBUS_HEADER_CHECK_FAIL</rc> - <description> - Procedure: proc_sbe_tp_switch_gears - X-Bus Murano DD1.x workaround header check fail (ie. scan failed) - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FAIL, POR_FFDC_OFFSET_USE_P0</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml deleted file mode 100644 index 2a7a48ea5..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml +++ /dev/null @@ -1,121 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_sbe_trigger_winkle_errors.xml,v 1.5 2014/07/23 19:51:50 jmcgill Exp $ --> -<!-- Error definitions for proc_sbe_trigger_winkle procedure --> -<hwpErrors> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_TRIGGER_WINKLE_EX_DID_NOT_ENTER_WINKLE</rc> - <description> - Procedure: proc_sbe_trigger_winkle - The master EX chiplet did not enter winkle before the deadman timer expired. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_TRIGGER_WINKLE_EX_WAKEUP_DID_NOT_HIT_GOTO</rc> - <description> - Procedure: proc_sbe_trigger_winkle - The master EX chiplet wakeup did not hit GOTO before the deadman timer expired. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_TRIGGER_WINKLE_EX_WAKEUP_DID_NOT_FINISH</rc> - <description> - Procedure: proc_sbe_trigger_winkle - The master EX chiplet wakeup didn't finish before the deadman timer expired. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_TRIGGER_WINKLE_HOSTBOOT_DID_NOT_RESPOND</rc> - <description> - Procedure: proc_sbe_trigger_winkle - The master EX chiplet woke up but hostboot didn't indicate that it was running before the deadman timer expired. - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml deleted file mode 100644 index da69d145f..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml +++ /dev/null @@ -1,631 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_slw_base_halt_codes.xml,v 1.10 2014/07/23 19:51:50 jmcgill Exp $ --> -<!-- Halt codes for proc_slw_*.S --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_UNDEFINED_SV</rc> - <description> - This error is signalled by proc_slw_base and indicates that an - invalid start vector was detected in the EXE_TRIGGER (ETR) register when - kicking off an idle transition. The start vector is in ETR(8:11). - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_PFET_VDD_TIMEOUT_ERROR</rc> - <description> - This error is signalled by proc_slw_poweronoff and indicates that a timeout - occured waiting for the VDD PFET sequencer(s) to complete. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_PFET_VCS_TIMEOUT_ERROR</rc> - <description> - This error is signalled by proc_slw_poweronoff and indicates that a timeout - occured waiting for the VCS PFET sequencer(s) to complete. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_PFET_DECODE_ERROR</rc> - <description> - This error is signalled by proc_slw_poweronoff and indicates that an invalid - PFET decode was detected. This is an SLW firmware issue. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_IVRM_BS_SLEEP_ENTRY_TIMEOUT</rc> - <description> - This error is signalled by proc_slw_base and indicates that a timeout - occured waiting for the internal VRM babystepper to synchronize the idle - transition command during sleep entry. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_IVRM_BS_WINKLE_ENTRY_TIMEOUT</rc> - <description> - This error is signalled by proc_slw_base and indicates that a timeout - occured waiting for the internal VRM babystepper to synchronize the idle - transition command during winkle entry. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_IVRM_BS_EXIT_TIMEOUT</rc> - <description> - This error is signalled by proc_slw_base and indicates that a timeout - occured waiting for the internal VRM babystepper to synchronize the idle - transition command during a fast exit. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_IVRM_CAL_TIMEOUT</rc> - <description> - This error is signalled by proc_slw_base and indicates that a timeout - occured while polling for the iVRM calibration to complete. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_IVRM_CAL_BS_EXIT_TIMEOUT</rc> - <description> - This error is signalled by proc_slw_base and indicates that a timeout - occured waiting for the internal VRM babystepper to synchronize the idle - transition command during a deep exit after iVRM calibration. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_IVRM_FORCESM_TIMEOUT</rc> - <description> - This error is signalled by proc_slw_base and indicates that a timeout - occured waiting for the internal VRM force safe mode to take effect. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_RAM_THREAD_CHECK_ERROR</rc> - <description> - This error is signalled by proc_slw_ram and indicates that a timeout - occured waiting the RAM hardware to accept the instruction given to it.. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_RAM_THREAD_QUIESCE_ERROR</rc> - <description> - This error is signalled by proc_slw_ram and indicates that a timeout - occured waiting the RAM hardware to quiesce. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_RAM_CONTROL_EXCEPTION_ERROR</rc> - <description> - This error is signalled by proc_slw_ram and indicates that RAM controller - indicates recovery is inprogress or an exception has occured.. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_RAM_STATUS_TIMEOUT_ERROR</rc> - <description> - This error is signalled by proc_slw_ram and indicates that a timeout occured - looking for good status from the RAM Controller. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_GOTO_TIMEOUT_ERROR</rc> - <description> - This error is signalled by proc_slw_base and indicates that a timeout occured - looking for the proper PCBS-PM state before issuing a PCBS-PM "GOTO" command. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_ERRINJ_NEVER_REACH_HALT</rc> - <description> - This error is signalled by proc_slw_pro_epi_log and indicates that the image - updated the PMC status reg but never reached the subsequent halt op. PMC SLW - Timeouts will be indicated without further FIR bits. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_ERRINJ_SIMPLE_HALT</rc> - <description> - This error is signalled by proc_slw_pro_epi_log and indicates that the image - executed the simple halt error injection. PMC SLW Timeouts will be indicated - without further FIR bits. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_ERRINJ_INVALID_INSTR</rc> - <description> - This error is signalled by proc_slw_pro_epi_log and indicates that the image - enabled invalid instruction error injection occured. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_ERRINJ_INVALID_OCI_ADDRESS</rc> - <description> - This error is signalled by proc_slw_pro_epi_log and indicates that the image - enabled invalid OCI address error injection occured. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_ERRINJ_INVALID_PIB_ADDRESS</rc> - <description> - This error is signalled by proc_slw_pro_epi_log and indicates that the image - enabled invalid PIB address error injection occured. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_ERRINJ_PC_UNDERFLOW</rc> - <description> - This error is signalled by proc_slw_pro_epi_log and indicates that the image - enabled PC underflow error injection occured. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_ERRINJ_PC_OVERRFLOW</rc> - <description> - This error is signalled by proc_slw_pro_epi_log and indicates that the image - enabled PC overflow error injection occured. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_ERRINJ_TIMEOUT_ERROR</rc> - <description> - This error is signalled by proc_slw_pro_epi_log and indicates that the image - enabled timeout error injection occured. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_EH_PIB_ERROR</rc> - <description> - This error is signalled by proc_slw_error_handler upon a detected error 0 - event (non-masked PIB error code). - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_EH_OCI_ERROR</rc> - <description> - This error is signalled by proc_slw_error_handler upon a detected error 1 - event (non-masked OCI error code). - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_EH_INSTRUCTION_ERROR</rc> - <description> - This error is signalled by proc_slw_error_handler upon a detected error 2 - event (instruction fetch or decode). - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_EH_INTERNAL_DATA_ERROR</rc> - <description> - This error is signalled by proc_slw_error_handler upon a detected error 3 - event (internal data error). - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_EH_ERROR_ON_ERROR</rc> - <description> - This error is signalled by proc_slw_error_handler upon a detected error 4 - event (an error was detected upon an error). - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_PMGP1_ENABLE_CONFIG_ERROR</rc> - <description> - This error is signalled by proc_slw_base code when the multicast read AND - and the multicast read OR of the PMGP1 register for the chiplets - represented in the EXE Trigger register do not match. This could be caused - by a configuration error with the Deep Sleep power up and/or down bits or - Deep Winkle power up bit. If these bits match, then a hardware fault is - the next most probable. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>SLW_RC_ILLEGAL_WINKLE_ENTRY_POWER_DOWN</rc> - <description> - This error is signalled by proc_slw_base code (poweronoff portion) and indicates - that the PMGP1 bit for WINKLE_POWER_DOWN when WINKLE_POWER_OFF_SEL is set to 1 - (eg a Deep Winkle) has been detected. This is an illegal configuration as it - causes the loss of the High Availability Log Write pointer in the L3 before it - could be saved for restoration upon Deep Winkle Exit. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>SLW_RC_OHA_SPWUP_TIMEOUT</rc> - <description> - This error is signalled by proc_slw_base code when the polling for OHA AISS - achieving the special wake-up state after hitting the PCBS GOTO operation to - complete deep sleep exit. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SLW_CPM_SPWKUP_NOT_SET</rc> - <description> - This error is signalled by proc_slw_occ_cpm code when it is detected that - special wake-up override isnt enabled which it must be prior to calling - any of the CPM install or enable routines. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/sbe_common_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/sbe_common_halt_codes.xml deleted file mode 100644 index 2842ad9ef..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/sbe_common_halt_codes.xml +++ /dev/null @@ -1,332 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/sbe_common_halt_codes.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: sbe_common_halt_codes.xml,v 1.6 2014/07/23 19:51:50 jmcgill Exp $ --> -<!-- Halt codes for proc_sbe_* procedures common to P8 and Centaur --> -<hwpErrors> - <!-- ******************************************************************** --> - <!-- ** Generic halt codes --> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SUCCESS</rc> - <description> - This halt code does not represent an error; This is the code associated - with the normal successful completion of an IPL by an SBE istep - procedure. - </description> - <sbeError/> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SUCCESS_SLAVE_CHIP</rc> - <description> - This halt code does not represent an error; This is the code associated - with the normal successful completion of an IPL by an SBE istep - procedure on a slave chip. - </description> - <sbeError/> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PAUSE_WITH_SUCCESS</rc> - <description> - This halt code does not represent an error; This is the code associated - with a procedure initiated halt of the SBE code, with the expectation - that it will be resumed at a later point in time. - </description> - <sbeError/> - </hwpError> - <!-- ******************************************************************** --> - <!-- ** Halt codes from sbe_common.H --> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PROC_ENTRY_HALT</rc> - <description> - This halt code does not represent an error; This is the code associated - with a HALT requested by the user prior to the execution of a procedure - by setting the PROC_CONTROL_ENTRY_HALT bit in the control word for the - procedure. - </description> - <sbeError/> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PROC_EXIT_HALT</rc> - <description> - This halt code does not represent an error; This is the code associated - with a HALT requested by the user after the execution of a procedure - by setting the PROC_CONTROL_EXIT_HALT bit in the control word for the - procedure. - </description> - <sbeError/> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PROC_CHECKSTOP</rc> - <description> - This halt code indicates that a checkstop was detected after executing a - procedure. Use the fields of the SBEVITAL register to identify the - procedure that failed. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PROC_RECOVERABLE</rc> - <description> - This halt code indicates that a recoverable error was detected after - executing a procedure. Use the fields of the SBEVITAL register to - identify the procedure that failed. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> - <callout> - <target>CHIP</target> - <priority>LOW</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PROC_SPATTN</rc> - <description> - This halt code indicates that a Special Attention was detected after - executing a procedure. Use the fields of the SBEVITAL register to - identify the procedure that failed. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_FIR_FAIL, POR_FFDC_OFFSET_NONE</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <!-- ** Halt codes from proc_sbe_pore_errors.S --> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PORE_ERROR0</rc> - <description> - This halt code indicates that an execution-phase PIB/PCB access - returned a non-0 response. The PORE PIBMS_DBG registers 0 and 1 - (plus the remainder of the PORE state) contain the information required - for an initial debug of the problem. - - This error should never occur for SBE/SLW, based on the fact that the - HW error handler mechanism is disabled. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PORE_ERROR1</rc> - <description> - This halt code indicates that an execution-phase OCI accesss had an - error. The PORE PIBMS_DBG registers 0 and 1 (plus the remainder of the - PORE state) contain the information required for an initial debug of the - problem. - - This error should never occur for SBE/SLW, based on the fact that the - HW error handler mechanism is disabled. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PORE_ERROR2</rc> - <description> - This halt code indicates an instruction fetch or decode error. The PORE - specification lists several causes of this error code. The most likely - causes in a production system are: - o An I2C hang when fetching code from SEEPROM; - o A bad branch that starts executing garbage or data; - o Memory corruption - - This error should never occur for SBE/SLW, based on the fact that the - HW error handler mechanism is disabled. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PORE_ERROR3</rc> - <description> - This halt code indicates an internal data error during consistency - checking, e.g., a bad scan-data CRC. - - This error should never occur for SBE/SLW, based on the fact that the - HW error handler mechanism is disabled. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_PORE_ERROR4</rc> - <description> - This halt code indicates that a second error occurred during processing - of an initial error. - - This error should never occur for SBE/SLW, based on the fact that the - HW error handler mechanism is disabled. - </description> - <sbeError/> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <!-- ** Halt codes from scan0 subroutine --> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_SCAN0_DONE_POLL_THRESHOLD</rc> - <description> - This error is signalled by the scan0 subroutine, indicating that the - scan0 DONE polling reached the specified threshold value. The scan0 - subroutine could have been called by various procedures. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_SCAN_FLUSH_FAIL, POR_FFDC_OFFSET_USE_P1</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> - <!-- ** Halt codes from arrayinit subroutine --> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_SBE_ARRAYINIT_POLL_THRESHOLD</rc> - <description> - This error is signalled by the arrayinit subroutine, indicating that the - arrayinit DONE polling reached the specified threshold value. The arrayinit - subroutine could have been called by various procedures. - </description> - <sbeError/> - <collectFfdc>proc_extract_pore_halt_ffdc, pore_state, PORE_HALT_ARRAYINIT_FAIL, POR_FFDC_OFFSET_USE_P1</collectFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml deleted file mode 100644 index 876e0afca..000000000 --- a/src/usr/hwpf/hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml +++ /dev/null @@ -1,121 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: sbe_load_ring_vec_ex_errors.xml,v 1.4 2014/07/23 19:51:50 jmcgill Exp $ --> -<!-- Error definitions for sbe_load_ring_vec_ex procedure --> -<hwpErrors> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_LOAD_RING_VEC_EX_ex_time_core_ERROR</rc> - <description> - Procedure: proc_sbe_ex_core_gptr_time_initf - Failed to find a chiplet to scan for ex_time_core - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_SBE_SELECT_EX</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_LOAD_RING_VEC_EX_ex_time_eco_ERROR</rc> - <description> - Procedure: proc_sbe_ex_gptr_time_initf - Failed to find a chiplet to scan for ex_time_eco - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_SBE_SELECT_EX</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_LOAD_RING_VEC_EX_ex_repr_core_ERROR</rc> - <description> - Procedure: proc_sbe_ex_core_repair_initf - Failed to find a chiplet to scan for ex_repr_core - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_SBE_SELECT_EX</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_SBE_LOAD_RING_VEC_EX_ex_repr_eco_ERROR</rc> - <description> - Procedure: proc_sbe_ex_repair_initf - Failed to find a chiplet to scan for ex_repr_eco - </description> - <sbeError/> - <collectRegisterFfdc> - <id>REG_FFDC_SBE_SELECT_EX</id> - <target>CHIP</target> - </collectRegisterFfdc> - <callout> - <target>CHIP</target> - <priority>HIGH</priority> - </callout> - <deconfigure> - <target>CHIP</target> - </deconfigure> - <gard> - <target>CHIP</target> - </gard> - </hwpError> - <!-- *********************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_init/proc_tod_init.C b/src/usr/hwpf/hwp/tod_init/proc_tod_init/proc_tod_init.C deleted file mode 100644 index 820863315..000000000 --- a/src/usr/hwpf/hwp/tod_init/proc_tod_init/proc_tod_init.C +++ /dev/null @@ -1,439 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/tod_init/proc_tod_init/proc_tod_init.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_tod_init.C,v 1.15 2014/10/23 18:56:17 jklazyns Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *! -// *! TITLE : proc_tod_init.C -// *! -// *! DESCRIPTION : Initializes the TOD topology to 'running' -// *! -// *! OWNER NAME : Nick Klazynski Email: jklazyns@us.ibm.com -// *! BACKUP NAME : Email: -// *! -// *! ADDITIONAL COMMENTS : -// *! -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "proc_tod_utils.H" -#include "proc_tod_init.H" -#include "p8_scom_addresses.H" - -extern "C" -{ - -//------------------------------------------------------------------------------ -// Function definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// function: proc_tod_init -// -// parameters: -// i_tod_node Reference to TOD topology (FAPI targets included within) -// -// i_failingTodProc, Pointer to the fapi target, the memory location -// addressed by this parameter will be populated with processor target -// which is not able to recieve proper singals from OSC. -// Caller needs to look at this parameter only when proc_tod_init fails -// and reason code indicates OSC failure. It is defaulted to NULL. -// -// returns: FAPI_RC_SUCCESS if TOD topology is successfully initialized -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_tod_init(const tod_topology_node* i_tod_node, - fapi::Target* i_failingTodProc ) -{ - fapi::ReturnCode rc; - - FAPI_INF("proc_tod_init: Start"); - do - { - if (i_tod_node == NULL) - { - FAPI_ERR("proc_tod_init: null node passed into function!"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_NULL_NODE); - break; - } - - rc = proc_tod_clear_error_reg(i_tod_node); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_init: Failure clearing TOD error registers!"); - break; - } - - //Start configuring each node; (init_tod_node will recurse on each child) - rc = init_tod_node(i_tod_node,i_failingTodProc); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_init: Failure initializing TOD!"); - break; - } - - } while (0); - - FAPI_INF("proc_tod_init: End"); - return rc; -} - -//------------------------------------------------------------------------------ -// function: proc_tod_clear_error_reg -// -// parameters: i_tod_node Reference to TOD topology (FAPI targets included within) -// -// returns: FAPI_RC_SUCCESS if every TOD node is cleared of errors -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_tod_clear_error_reg(const tod_topology_node* i_tod_node) -{ - fapi::ReturnCode rc; - ecmdDataBufferBase data(64); - uint32_t rc_ecmd = 0; - fapi::Target* target = i_tod_node->i_target; - - FAPI_INF("proc_tod_clear_error_reg: Start"); - do - { - if (i_tod_node == NULL) - { - FAPI_ERR("proc_tod_clear_error_reg: null node passed into function!"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_NULL_NODE); - break; - } - - FAPI_DBG("proc_tod_clear_error_reg: Clear any previous errors from TOD_ERROR_REG_00040030"); - rc_ecmd |= data.flushTo1(); - if (rc_ecmd) - { - FAPI_ERR("proc_tod_clear_error_reg: Error 0x%08X in ecmdDataBuffer setup for TOD_ERROR_REG_00040030.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target, TOD_ERROR_REG_00040030, data); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_clear_error_reg: Could not write TOD_ERROR_REG_00040030."); - break; - } - - for (std::list<tod_topology_node*>::const_iterator child = (i_tod_node->i_children).begin(); - child != (i_tod_node->i_children).end(); - ++child) - { - tod_topology_node* tod_node = *child; - rc = proc_tod_clear_error_reg(tod_node); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_clear_error_reg: Failure clearing errors from downstream node!"); - break; - } - } - if (!rc.ok()) - { - break; // error in above for loop - } - } while (0); - - FAPI_INF("proc_tod_clear_error_reg: End"); - return rc; -} - -//------------------------------------------------------------------------------ -// function: init_tod_node -// -// parameters: -// i_tod_node Reference to TOD topology (FAPI targets included within) -// -// i_failingTodProc, Pointer to the fapi target, the memory location -// addressed by this parameter will be populated with processor target -// which is not able to recieve proper singals from OSC. -// Caller needs to look at this parameter only when proc_tod_init fails -// and reason code indicates OSC failure. It is defaulted to NULL. -// -// returns: FAPI_RC_SUCCESS if TOD topology is successfully initialized -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode init_tod_node(const tod_topology_node* i_tod_node, - fapi::Target* i_failingTodProc) -{ - fapi::ReturnCode rc; - ecmdDataBufferBase data(64); - uint32_t rc_ecmd = 0; - uint32_t tod_init_pending_count = 0; // Timeout counter for bits that are cleared by hardware - fapi::Target* target = i_tod_node->i_target; - - FAPI_INF("init_tod_node: Start: Initializing %s", target->toEcmdString()); - - do - { - const bool is_mdmt = (i_tod_node->i_tod_master && i_tod_node->i_drawer_master); - - if (is_mdmt) - { - FAPI_INF("init_tod_node: Master: Chip TOD step checkers enable"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setBit(0); - if (rc_ecmd) - { - FAPI_ERR("init_tod_node: Error 0x%08X in ecmdDataBuffer setup for TOD_TX_TTYPE_2_REG_00040013 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target, TOD_TX_TTYPE_2_REG_00040013, data); - if (!rc.ok()) - { - FAPI_ERR("init_tod_node: Could not write TOD_TX_TTYPE_2_REG_00040013."); - break; - } - - FAPI_INF("init_tod_node: Master: switch local Chip TOD to 'Not Set' state"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setBit(TOD_LOAD_TOD_MOD_REG_FSM_LOAD_TOD_MOD_TRIG); - if (rc_ecmd) - { - FAPI_ERR("init_tod_node: Master: Error 0x%08X in ecmdDataBuffer setup for TOD_LOAD_TOD_MOD_REG_00040018 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target, TOD_LOAD_TOD_MOD_REG_00040018, data); - if (!rc.ok()) - { - FAPI_ERR("init_tod_node: Master: Could not write TOD_LOAD_TOD_MOD_REG_00040018"); - break; - } - FAPI_INF("init_tod_node: Master: switch all Chip TOD in the system to 'Not Set' state"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setBit(0); - if (rc_ecmd) - { - FAPI_ERR("init_tod_node: Master: Error 0x%08X in ecmdDataBuffer setup for TOD_TX_TTYPE_5_REG_00040016 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target, TOD_TX_TTYPE_5_REG_00040016, data); - if (!rc.ok()) - { - FAPI_ERR("init_tod_node: Master: Could not write TOD_TX_TTYPE_5_REG_00040016"); - break; - } - - FAPI_INF("init_tod_node: Master: Chip TOD load value (move TB to TOD)"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setWord(0,0x00000000); - rc_ecmd |= data.setWord(1,0x00003FF0); // bits 51:59 must be 1s - if (rc_ecmd) - { - FAPI_ERR("init_tod_node: Master: Error 0x%08X in ecmdDataBuffer setup for TOD_LOAD_TOD_REG_00040021 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target, TOD_LOAD_TOD_REG_00040021, data); - if (!rc.ok()) - { - FAPI_ERR("init_tod_node: Master: Could not write TOD_LOAD_TOD_REG_00040021"); - break; - } - FAPI_INF("init_tod_node: Master: Chip TOD start_tod (switch local Chip TOD to 'Running' state)"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setBit(TOD_START_TOD_REG_FSM_START_TOD_TRIGGER); - if (rc_ecmd) - { - FAPI_ERR("init_tod_node: Master: Error 0x%08X in ecmdDataBuffer setup for TOD_START_TOD_REG_00040022 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target, TOD_START_TOD_REG_00040022, data); - if (!rc.ok()) - { - FAPI_ERR("init_tod_node: Master: Could not write TOD_START_TOD_REG_00040022"); - break; - } - - FAPI_INF("init_tod_node: Master: Send local Chip TOD value to all Chip TODs"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setBit(0); - if (rc_ecmd) - { - FAPI_ERR("init_tod_node: Master: Error 0x%08X in ecmdDataBuffer setup for TOD_TX_TTYPE_4_REG_00040015", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target, TOD_TX_TTYPE_4_REG_00040015, data); - if (!rc.ok()) - { - FAPI_ERR("init_tod_node: Master: Could not write TOD_TX_TTYPE_4_REG_00040015"); - break; - } - } - - FAPI_INF("init_tod_node: Check TOD is Running"); - tod_init_pending_count = 0; - while (tod_init_pending_count < PROC_TOD_UTIL_TIMEOUT_COUNT) - { - FAPI_DBG("init_tod_node: Waiting for TOD to assert TOD_FSM_REG_TOD_IS_RUNNING..."); - - rc = fapiDelay(PROC_TOD_UTILS_HW_NS_DELAY, - PROC_TOD_UTILS_SIM_CYCLE_DELAY); - if (!rc.ok()) - { - FAPI_ERR("init_tod_node: fapiDelay error"); - break; - } - rc = fapiGetScom(*target, TOD_FSM_REG_00040024, data); - if (!rc.ok()) - { - FAPI_ERR("init_tod_node: Could not retrieve TOD_FSM_REG_00040024"); - break; - } - if (data.isBitSet(TOD_FSM_REG_TOD_IS_RUNNING)) - { - FAPI_INF("init_tod_node: TOD is running!"); - break; - } - ++tod_init_pending_count; - } - if (!rc.ok()) - { - break; // error in above while loop - } - if (tod_init_pending_count>=PROC_TOD_UTIL_TIMEOUT_COUNT) - { - FAPI_ERR("init_tod_node: TOD is not running! (It should be)"); - const fapi::Target & CHIP_TARGET = *target; - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_INIT_NOT_RUNNING); - break; - } - - FAPI_INF("init_tod_node: clear TTYPE#2, TTYPE#4, and TTYPE#5 status"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setBit(TOD_ERROR_REG_RX_TTYPE_2); - rc_ecmd |= data.setBit(TOD_ERROR_REG_RX_TTYPE_4); - rc_ecmd |= data.setBit(TOD_ERROR_REG_RX_TTYPE_5); - if (rc_ecmd) - { - FAPI_ERR("init_tod_node: Error 0x%08X in ecmdDataBuffer setup for TOD_ERROR_REG_00040030.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target, TOD_ERROR_REG_00040030, data); - if (!rc.ok()) - { - FAPI_ERR("init_tod_node: Could not write TOD_ERROR_REG_00040030."); - break; - } - - FAPI_INF("init_tod_node: checking for TOD errors"); - rc = fapiGetScom(*target, TOD_ERROR_REG_00040030, data); - if (!rc.ok()) - { - FAPI_ERR("init_tod_node: Could not read TOD_ERROR_REG_00040030."); - break; - } - if (data.getDoubleWord(0) != 0) - { - const fapi::Target & CHIP_TARGET = *target; - const uint64_t TOD_ERROR_REG = data.getDoubleWord(0); - if (data.isBitSet(TOD_ERROR_REG_M_PATH_0_STEP_CHECK_ERROR)) - { - FAPI_ERR("init_tod_node: M_PATH_0_STEP_CHECK_ERROR! (TOD_ERROR_REG = 0x%016llX)",data.getDoubleWord(0)); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_INIT_M_PATH_0_STEP_CHECK_ERROR); - *i_failingTodProc = *target; - } - else if (data.isBitSet(TOD_ERROR_REG_M_PATH_1_STEP_CHECK_ERROR)) - { - FAPI_ERR("init_tod_node: M_PATH_1_STEP_CHECK_ERROR! (TOD_ERROR_REG = 0x%016llX)",data.getDoubleWord(0)); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_INIT_M_PATH_1_STEP_CHECK_ERROR); - *i_failingTodProc = *target; - } - else - { - FAPI_ERR("init_tod_node: FIR bit active! (TOD_ERROR_REG = 0x%016llX)",data.getDoubleWord(0)); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_INIT_ERROR); - } - break; - } - - // TOD_ERROR_MASK_STATUS_REG_00040032 is not writable on some chips - uint8_t chipHasTodErrorMaskBug = 0; - rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_HW_BUG_TOD_ERROR_MASK_NOT_WRITABLE, target, chipHasTodErrorMaskBug); - if(rc) - { - FAPI_ERR("init_tod_node: Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_HW_BUG_TOD_ERROR_MASK_NOT_WRITABLE"); - break; - } - if(!chipHasTodErrorMaskBug) - { - FAPI_INF("init_tod_node: set error mask to runtime configuration"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setWord(1,0x03F00000); // Mask TTYPE received informational bits 38:43 - if (rc_ecmd) - { - FAPI_ERR("init_tod_node: Error 0x%08X in ecmdDataBuffer setup for TOD_ERROR_MASK_STATUS_REG_00040032 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target, TOD_ERROR_MASK_STATUS_REG_00040032, data); - if (!rc.ok()) - { - FAPI_ERR("init_tod_node: Could not write TOD_ERROR_MASK_STATUS_REG_00040032"); - break; - } - } - else - { - FAPI_INF("init_tod_node: Skipping TOD error mask setup because of chip limitation."); - } - - // Finish configuring downstream nodes - for (std::list<tod_topology_node*>::const_iterator child = (i_tod_node->i_children).begin(); - child != (i_tod_node->i_children).end(); - ++child) - { - tod_topology_node* tod_node = *child; - rc = init_tod_node(tod_node,i_failingTodProc); - if (!rc.ok()) - { - FAPI_ERR("init_tod_node: Failure configuring downstream node!"); - break; - } - } - if (!rc.ok()) - { - break; // error in above for loop - } - - } while(0); - - FAPI_INF("init_tod_node: End"); - return rc; -} - -} // extern "C" diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_init/proc_tod_init.H b/src/usr/hwpf/hwp/tod_init/proc_tod_init/proc_tod_init.H deleted file mode 100644 index 0461dae5f..000000000 --- a/src/usr/hwpf/hwp/tod_init/proc_tod_init/proc_tod_init.H +++ /dev/null @@ -1,117 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/tod_init/proc_tod_init/proc_tod_init.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_tod_init.H,v 1.5 2014/10/03 18:44:52 thi Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *! -// *! TITLE : proc_tod_init.H -// *! -// *! DESCRIPTION : Header for proc_tod_init.C -// *! -// *! OWNER NAME : Nick Klazynski Email: jklazyns@us.ibm.com -// *! BACKUP NAME : Email: -// *! -// *! ADDITIONAL COMMENTS : -// *! -//------------------------------------------------------------------------------ - -#ifndef PROC_TOD_INIT_H_ -#define PROC_TOD_INIT_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <fapi.H> -#include "proc_tod_utils.H" - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*proc_tod_init_FP_t) (const tod_topology_node*, - fapi::Target* ); - -//------------------------------------------------------------------------------ -// Function prototypes -//------------------------------------------------------------------------------ - -extern "C" -{ - -/** - * @brief Initializes the TOD to 'running' state - * - * @param[in] i_tod_node Reference to TOD topology (FAPI targets included within) - * - * @param[in] i_failingTodProc, Pointer to the fapi target, the memory location - * addressed by this parameter will be populated with processor target - * which is not able to recieve proper singals from OSC. - * Caller needs to look at this parameter only when proc_tod_init fails - * and reason code indicates OSC failure. It is defaulted to NULL. - * - * @return FAPI_RC_SUCCESS if TOD topology is successfully initialized - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode proc_tod_init(const tod_topology_node* i_tod_node, - fapi::Target* i_failingTodProc = NULL ); - -/** - * @brief Clears TOD error register - * - * @param[in] i_tod_node Reference to TOD topology (FAPI targets included within) - * - * @return FAPI_RC_SUCCESS if TOD topology is cleared of previous errors - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode proc_tod_clear_error_reg(const tod_topology_node* i_tod_node); - -/** - * @brief Helper function for proc_tod_init - * - * @param[in] i_tod_node Reference to TOD topology (FAPI targets included within) - * - * @param[in] i_failingTodProc, Pointer to the fapi target, the memory location - * addressed by this parameter will be populated with processor target - * which is not able to recieve proper singals from OSC. - * Caller needs to look at this parameter only when proc_tod_init fails - * and reason code indicates OSC failure. It is defaulted to NULL. - * - * @return FAPI_RC_SUCCESS if TOD topology is successfully initialized - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode init_tod_node(const tod_topology_node* i_tod_node, - fapi::Target* i_failingTodProc = NULL); - -} // extern "C" - -#endif // PROC_TOD_INIT_H_ diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_save_config/proc_tod_save_config.C b/src/usr/hwpf/hwp/tod_init/proc_tod_save_config/proc_tod_save_config.C deleted file mode 100644 index b8c1b590d..000000000 --- a/src/usr/hwpf/hwp/tod_init/proc_tod_save_config/proc_tod_save_config.C +++ /dev/null @@ -1,204 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/tod_init/proc_tod_save_config/proc_tod_save_config.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_tod_save_config.C,v 1.5 2012/12/03 21:00:06 jklazyns Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *! -// *! TITLE : proc_tod_save_config.C -// *! -// *! DESCRIPTION : Saves TOD configuration registers to i_tod_node->o_todRegs -// *! -// *! OWNER NAME : Nick Klazynski Email: jklazyns@us.ibm.com -// *! BACKUP NAME : Email: -// *! -// *! ADDITIONAL COMMENTS : -// *! -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "proc_tod_save_config.H" -#include "p8_scom_addresses.H" - -extern "C" -{ - -//------------------------------------------------------------------------------ -// Function definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// function: proc_tod_save_config -// -// parameters: i_tod_node Reference to TOD topology (FAPI targets included within) -// -// returns: FAPI_RC_SUCCESS if all registers were read and saved in node structure -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_tod_save_config(tod_topology_node* i_tod_node) -{ - fapi::ReturnCode rc; - - FAPI_DBG("proc_tod_save_config: Start"); - do - { - if (i_tod_node == NULL) - { - FAPI_ERR("proc_tod_save_config: null node passed into function!"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_NULL_NODE); - break; - } - fapi::Target* target = i_tod_node->i_target; - - rc = proc_tod_save_single_reg(*target, TOD_M_PATH_CTRL_REG_00040000, i_tod_node->o_todRegs.tod_m_path_ctrl_reg); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_save_config: Error saving TOD_M_PATH_CTRL_REG_00040000..."); - break; - } - - rc = proc_tod_save_single_reg(*target, TOD_PRI_PORT_0_CTRL_REG_00040001,i_tod_node->o_todRegs.tod_pri_port_0_ctrl_reg); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_save_config: Error saving TOD_PRI_PORT_0_CTRL_REG_00040001..."); - break; - } - - rc = proc_tod_save_single_reg(*target, TOD_PRI_PORT_1_CTRL_REG_00040002,i_tod_node->o_todRegs.tod_pri_port_1_ctrl_reg); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_save_config: Error saving TOD_PRI_PORT_1_CTRL_REG_00040002..."); - break; - } - - rc = proc_tod_save_single_reg(*target, TOD_SEC_PORT_0_CTRL_REG_00040003,i_tod_node->o_todRegs.tod_sec_port_0_ctrl_reg); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_save_config: Error saving TOD_SEC_PORT_0_CTRL_REG_00040003..."); - break; - } - - rc = proc_tod_save_single_reg(*target, TOD_SEC_PORT_1_CTRL_REG_00040004,i_tod_node->o_todRegs.tod_sec_port_1_ctrl_reg); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_save_config: Error saving TOD_SEC_PORT_1_CTRL_REG_00040004..."); - break; - } - - rc = proc_tod_save_single_reg(*target, TOD_S_PATH_CTRL_REG_00040005,i_tod_node->o_todRegs.tod_s_path_ctrl_reg); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_save_config: Error saving TOD_S_PATH_CTRL_REG_00040005..."); - break; - } - - rc = proc_tod_save_single_reg(*target, TOD_I_PATH_CTRL_REG_00040006,i_tod_node->o_todRegs.tod_i_path_ctrl_reg); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_save_config: Error saving TOD_I_PATH_CTRL_REG_00040006..."); - break; - } - - rc = proc_tod_save_single_reg(*target, TOD_PSS_MSS_CTRL_REG_00040007,i_tod_node->o_todRegs.tod_pss_mss_ctrl_reg); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_save_config: Error saving TOD_PSS_MSS_CTRL_REG_00040007..."); - break; - } - - rc = proc_tod_save_single_reg(*target, TOD_CHIP_CTRL_REG_00040010,i_tod_node->o_todRegs.tod_chip_ctrl_reg); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_save_config: Error saving TOD_CHIP_CTRL_REG_00040010..."); - break; - } - - // Recurse to save children configuration - for (std::list<tod_topology_node*>::iterator child = (i_tod_node->i_children).begin(); - child != (i_tod_node->i_children).end(); - ++child) - { - tod_topology_node* tod_node = *child; - rc = proc_tod_save_config(tod_node); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_save_config: Failure saving downstream configurations!"); - break; - } - } - if (!rc.ok()) - { - break; // error in above for loop - } - } while(0); - - FAPI_DBG("proc_tod_save_config: End"); - return rc; -} - -//------------------------------------------------------------------------------ -// function: proc_tod_save_single_reg -// -// parameters: i_target FAPI target -// i_addr SCOM address to read -// o_data Buffer to save register read -// -// returns: FAPI_RC_SUCCESS if the given register was read and saved into buffer -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_tod_save_single_reg(const fapi::Target& i_target, - const uint64_t i_addr, - ecmdDataBufferBase& o_data) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - - FAPI_DBG("proc_tod_save_single_reg: Start"); - do - { - rc_ecmd |= o_data.setBitLength(64); - if (rc_ecmd) - { - FAPI_ERR("proc_tod_save_single_reg: Error 0x%08X in ecmdDataBuffer setup for 0x%016llX SCOM.", rc_ecmd, i_addr); - rc.setEcmdError(rc_ecmd); - break; - } - rc=fapiGetScom(i_target,i_addr,o_data); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_save_single_reg: Error from fapiGetScom when retrieving 0x%016llX...", i_addr); - break; - } - FAPI_DBG("proc_tod_save_single_reg: %016llX = %016llX",i_addr, o_data.getDoubleWord(0)); - } while(0); - - FAPI_DBG("proc_tod_save_single_reg: End"); - return rc; -} - -} // extern "C" diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_save_config/proc_tod_save_config.H b/src/usr/hwpf/hwp/tod_init/proc_tod_save_config/proc_tod_save_config.H deleted file mode 100644 index 1a5094fc3..000000000 --- a/src/usr/hwpf/hwp/tod_init/proc_tod_save_config/proc_tod_save_config.H +++ /dev/null @@ -1,97 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/tod_init/proc_tod_save_config/proc_tod_save_config.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_tod_save_config.H,v 1.1 2012/10/31 21:34:27 jklazyns Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *! -// *! TITLE : proc_tod_save_config.H -// *! -// *! DESCRIPTION : Header for proc_tod_save_config.C -// *! -// *! OWNER NAME : Nick Klazynski Email: jklazyns@us.ibm.com -// *! BACKUP NAME : Email: -// *! -// *! ADDITIONAL COMMENTS : -// *! -//------------------------------------------------------------------------------ - -#ifndef PROC_TOD_SAVE_CONFIG_H_ -#define PROC_TOD_SAVE_CONFIG_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <fapi.H> -#include "proc_tod_utils.H" - -extern "C" -{ - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode -(*proc_tod_save_config_FP_t) (tod_topology_node*); - -//------------------------------------------------------------------------------ -// Function prototypes -//------------------------------------------------------------------------------ - -/** - * @brief Saves TOD configuration registers to i_tod_node->o_todRegs - * - * @param[in] i_tod_node Reference to TOD topology (FAPI targets included within) - * - * @return FAPI_RC_SUCCESS if all registers were read and saved in node structure - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode proc_tod_save_config(tod_topology_node* i_tod_node); - -/** - * @brief Helper function which saves a single register to output buffer - * - * @param[in] i_target FAPI target - * i_addr SCOM address to read - * @param[out] o_data Buffer to save register read - * - * @return FAPI_RC_SUCCESS if the given register was read and saved into buffer - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode proc_tod_save_single_reg(const fapi::Target& i_target, - const uint64_t i_addr, - ecmdDataBufferBase& o_data); - -} // extern "C" - -#endif // PROC_TOD_SAVE_CONFIG_H_ diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_check_osc.C b/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_check_osc.C deleted file mode 100644 index a6d471281..000000000 --- a/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_check_osc.C +++ /dev/null @@ -1,184 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/tod_init/proc_tod_setup//proc_tod_check_osc.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_tod_check_osc.C,v 1.1 2014/12/11 17:01:53 jklazyns Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *! -// *! TITLE : proc_tod_check_osc.C -// *! -// *! DESCRIPTION : Checks the validity of TOD oscillators connected to a target -// *! -// *! OWNER NAME : Nick Klazynski Email: jklazyns@us.ibm.com -// *! BACKUP NAME : Email: -// *! -// *! ADDITIONAL COMMENTS : -// *! -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "proc_tod_utils.H" -#include "proc_tod_check_osc.H" -#include "p8_scom_addresses.H" - -extern "C" -{ - -//------------------------------------------------------------------------------ -// Function definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// function: proc_tod_check_osc -// parameters: -// i_target FAPI target which will have its oscillator validity checked -// o_osc_stat Oscillator(s) which passed the validity check -// -// returns: FAPI_RC_SUCCESS if the oscillators were successfully tested -// (o_osc_stat will have the check's result) -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_tod_check_osc(const fapi::Target* i_target, - proc_tod_setup_osc_sel* o_osc_stat) -{ - fapi::ReturnCode rc; - ecmdDataBufferBase m_path_ctrl_reg_save_data(64); - ecmdDataBufferBase data(64); - uint32_t rc_ecmd = 0; - - FAPI_INF("proc_tod_check_osc: Start"); - do - { - // Read TOD_M_PATH_CTRL_REG_00040000 to be restored at the end of the procedure - rc=fapiGetScom(*i_target,TOD_M_PATH_CTRL_REG_00040000,m_path_ctrl_reg_save_data); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_check_osc: Error from fapiGetScom when retrieving TOD_M_PATH_CTRL_REG_00040000!"); - break; - } - - FAPI_DBG("proc_tod_check_osc: Configuring Master OSC paths in TOD_M_PATH_CTRL_REG_00040000 for oscillator testing."); - - // OSC0 is connected - rc_ecmd |= data.clearBit(TOD_M_PATH_CTRL_REG_M_PATH_0_OSC_NOT_VALID); - - // OSC0 step alignment enabled - rc_ecmd |= data.clearBit(TOD_M_PATH_CTRL_REG_M_PATH_0_STEP_ALIGN_DIS); - - // Set 512 steps per sync for path 0 - rc_ecmd |= data.insertFromRight(TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_512, - TOD_M_PATH_CTRL_REG_M_PATH_0_SYNC_FREQ_SEL, - TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_LEN); - - // Set step check CPS deviation to 50% - rc_ecmd |= data.insertFromRight(STEP_CHECK_CPS_DEVIATION_50_00_PCENT, - TOD_M_PATH_CTRL_REG_M_PATH_0_STEP_CHECK_CPS_DEVIATION, - STEP_CHECK_CPS_DEVIATION_LEN); - - // 8 valid steps are required before step check is enabled - rc_ecmd |= data.insertFromRight(STEP_CHECK_VALIDITY_COUNT_8, - TOD_M_PATH_CTRL_REG_M_PATH_0_STEP_CHECK_VALIDITY_COUNT, - STEP_CHECK_VALIDITY_COUNT_LEN); - - // OSC1 is connected - rc_ecmd |= data.clearBit(TOD_M_PATH_CTRL_REG_M_PATH_1_OSC_NOT_VALID); - - // OSC1 step alignment enabled - rc_ecmd |= data.clearBit(TOD_M_PATH_CTRL_REG_M_PATH_1_STEP_ALIGN_DIS); - - // Set 512 steps per sync for path 1 - rc_ecmd |= data.insertFromRight(TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_512, - TOD_M_PATH_CTRL_REG_M_PATH_1_SYNC_FREQ_SEL, - TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_LEN); - - // Set step check CPS deviation to 50% - rc_ecmd |= data.insertFromRight(STEP_CHECK_CPS_DEVIATION_50_00_PCENT, - TOD_M_PATH_CTRL_REG_M_PATH_1_STEP_CHECK_CPS_DEVIATION, - STEP_CHECK_CPS_DEVIATION_LEN); - - // 8 valid steps are required before step check is enabled - rc_ecmd |= data.insertFromRight(STEP_CHECK_VALIDITY_COUNT_8, - TOD_M_PATH_CTRL_REG_M_PATH_1_STEP_CHECK_VALIDITY_COUNT, - STEP_CHECK_VALIDITY_COUNT_LEN); - - // CPS deviation factor configures both path-0 and path-1 - rc_ecmd |= data.insertFromRight(STEP_CHECK_CPS_DEVIATION_FACTOR_1, - TOD_M_PATH_CTRL_REG_M_PATH_STEP_CHECK_DEVIATION_FACTOR, - STEP_CHECK_CPS_DEVIATION_FACTOR_LEN); - - if (rc_ecmd) - { - FAPI_ERR("proc_tod_check_osc: Error 0x%08X in ecmdDataBuffer setup for TOD_M_PATH_CTRL_REG_00040000 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*i_target,TOD_M_PATH_CTRL_REG_00040000,data); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_check_osc: fapiPutScom error for TOD_M_PATH_CTRL_REG_00040000 SCOM."); - break; - } - - FAPI_DBG("proc_tod_check_osc: Checking oscillator validity."); - rc=fapiGetScom(*i_target,TOD_PSS_MSS_STATUS_REG_00040008,data); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_check_osc: Error from fapiGetScom when retrieving TOD_PSS_MSS_STATUS_REG_00040008!"); - break; - } - - *o_osc_stat = TOD_OSC_NONE; - if (data.isBitSet(TOD_PSS_MSS_STATUS_REG_M_PATH_0_STEP_CHECK_VALID) && - data.isBitSet(TOD_PSS_MSS_STATUS_REG_M_PATH_1_STEP_CHECK_VALID)) { - FAPI_DBG("proc_tod_check_osc: both master path-0 and path-1 are valid! (TOD_PSS_MSS_STATUS_REG = 0x%016llX)",data.getDoubleWord(0)); - *o_osc_stat = TOD_OSC_0_AND_1; - } - else if (data.isBitSet(TOD_PSS_MSS_STATUS_REG_M_PATH_0_STEP_CHECK_VALID)) { - FAPI_DBG("proc_tod_check_osc: master path-0 is valid; path-1 is not! (TOD_PSS_MSS_STATUS_REG = 0x%016llX)",data.getDoubleWord(0)); - *o_osc_stat = TOD_OSC_0; - } - else if (data.isBitSet(TOD_PSS_MSS_STATUS_REG_M_PATH_1_STEP_CHECK_VALID)) { - FAPI_DBG("proc_tod_check_osc: master path-1 is valid; path-0 is not! (TOD_PSS_MSS_STATUS_REG = 0x%016llX)",data.getDoubleWord(0)); - *o_osc_stat = TOD_OSC_1; - } - - FAPI_DBG("proc_tod_check_osc: Restoring previous TOD_M_PATH_CTRL_REG_00040000 value."); - rc = fapiPutScom(*i_target,TOD_M_PATH_CTRL_REG_00040000,m_path_ctrl_reg_save_data); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_check_osc: fapiPutScom error for TOD_M_PATH_CTRL_REG_00040000 SCOM."); - break; - } - - } while (0); - - FAPI_INF("proc_tod_check_osc: End"); - return rc; -} - -} // extern "C" diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_check_osc.H b/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_check_osc.H deleted file mode 100644 index f2aec381e..000000000 --- a/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_check_osc.H +++ /dev/null @@ -1,87 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/tod_init/proc_tod_setup//proc_tod_check_osc.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_tod_check_osc.H,v 1.1 2014/12/11 17:01:53 jklazyns Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *! -// *! TITLE : proc_tod_check_osc.H -// *! -// *! DESCRIPTION : Header for proc_tod_check_osc.C -// *! -// *! OWNER NAME : Nick Klazynski Email: jklazyns@us.ibm.com -// *! BACKUP NAME : Email: -// *! -// *! ADDITIONAL COMMENTS : -// *! -//------------------------------------------------------------------------------ - -#ifndef PROC_TOD_CHECK_OSC_H_ -#define PROC_TOD_CHECK_OSC_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <fapi.H> -#include "proc_tod_utils.H" - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*proc_tod_check_osc_FP_t) (const fapi::Target*, - proc_tod_setup_osc_sel*); - -//------------------------------------------------------------------------------ -// Function prototypes -//------------------------------------------------------------------------------ - -extern "C" -{ - -/** - * @brief Checks oscillator validality for a given target - * - * @param[in] i_target FAPI target which will have its oscillator - * validity checked - * - * @param[out] o_osc_stat Oscillator(s) which passed the validity check - * - * @return FAPI_RC_SUCCESS if the oscillators were successfully tested - * (o_osc_stat will have the check's result) - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode proc_tod_check_osc(const fapi::Target* i_target, - proc_tod_setup_osc_sel* o_osc_stat); - -} // extern "C" - -#endif // PROC_TOD_CHECK_OSC_H_ diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.C b/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.C deleted file mode 100644 index bb1a0c85c..000000000 --- a/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.C +++ /dev/null @@ -1,1154 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_tod_setup.C,v 1.23 2015/01/08 19:50:38 jklazyns Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *! -// *! TITLE : proc_tod_setup.C -// *! -// *! DESCRIPTION : Configures the TOD topology -// *! -// *! OWNER NAME : Nick Klazynski Email: jklazyns@us.ibm.com -// *! BACKUP NAME : Email: -// *! -// *! ADDITIONAL COMMENTS : -// *! Procedure implemented: -// *! - First, configure topology delays -// *! - The longest delay (node furthest away) needs to be found first. This will -// *! be the MDMT's delay and the children will be derived from this. The node -// *! that's furthest away should have a delay of 0 (step as soon as signal is -// *! received -// *! - Next, configure TOD registers based on pervasive workbook (section 17.8) -// *! - Primary and Secondary topologies are configured in a similar manner -// *! with different registers. This code attempts to use common code to -// *! implement this. -// *! - Initialization is required (pervasive workbook 17.8.3.1) in order to verify -// *! the topology is correctly configured -// *! -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "proc_tod_setup.H" -#include "p8_scom_addresses.H" - -extern "C" -{ - -//------------------------------------------------------------------------------ -// Function definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// function: proc_tod_setup -// -// parameters: i_tod_node Reference to TOD topology (FAPI targets included within) -// i_tod_sel Specifies the topology to configure -// i_osc_sel Specifies the oscillator to use for the master -// -// returns: FAPI_RC_SUCCESS if TOD topology is successfully configured -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_tod_setup(tod_topology_node* i_tod_node, - const proc_tod_setup_tod_sel i_tod_sel, - const proc_tod_setup_osc_sel i_osc_sel) -{ - fapi::ReturnCode rc; - fapi::ATTR_IS_MPIPL_Type is_mpipl = 0x00; - - // Mark HWP entry - FAPI_INF("proc_tod_setup: Start"); - - do - { - if (i_tod_node == NULL || i_tod_node->i_target == NULL) - { - FAPI_ERR("proc_tod_setup: null node or target passed into function!"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_NULL_NODE); - break; - } - if (!(i_tod_node->i_tod_master && i_tod_node->i_drawer_master)) - { - FAPI_ERR("proc_tod_setup: non-root (slave) node passed into main function!"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_SETUP_INVALID_TOPOLOGY); - break; - } - - FAPI_INF("proc_tod_setup: Configuring %s topology (OSC0 is %s, OSC1 is %s)", - (i_tod_sel==TOD_PRIMARY)?"Primary":"Secondary", - (i_osc_sel==TOD_OSC_0 || - i_osc_sel==TOD_OSC_0_AND_1 || - i_osc_sel==TOD_OSC_0_AND_1_SEL_0 || - i_osc_sel==TOD_OSC_0_AND_1_SEL_1)?"connected":"not connected", - (i_osc_sel==TOD_OSC_1 || - i_osc_sel==TOD_OSC_0_AND_1 || - i_osc_sel==TOD_OSC_0_AND_1_SEL_0 || - i_osc_sel==TOD_OSC_0_AND_1_SEL_1)?"connected":"not connected"); - - // calculate_node_delays populates o_int_path_delay for each node - rc = calculate_node_delays(i_tod_node); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_setup: Failure calculating TOD delays!"); - break; - } - display_tod_nodes(i_tod_node,0); - - rc = FAPI_ATTR_GET(ATTR_IS_MPIPL, NULL, is_mpipl); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_setup: fapiGetAttribute of ATTR_IS_MPIPL failed!"); - break; - } - - // If there is a previous topology, it needs to be cleared - rc = clear_tod_node(i_tod_node, i_tod_sel, is_mpipl); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_setup: Failure clearing previous TOD configuration!"); - break; - } - - //Start configuring each node; (configure_tod_node will recurse on each child) - rc = configure_tod_node(i_tod_node,i_tod_sel,i_osc_sel); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_setup: Failure configuring TOD!"); - break; - } - - } while (0); - - FAPI_INF("proc_tod_setup: End"); - return rc; -} - -//------------------------------------------------------------------------------ -// function: clear_tod_topology -// -// parameters: i_tod_node Reference to TOD topology (FAPI targets included within) -// i_tod_sel Specifies the topology to clear -// i_is_mpipl if this IPL is an MPIPL, additional setup is needed; -// determined via an attribute -// -// returns: FAPI_RC_SUCCESS if TOD topology is successfully cleared -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode clear_tod_node(tod_topology_node* i_tod_node, - const proc_tod_setup_tod_sel i_tod_sel, - const fapi::ATTR_IS_MPIPL_Type i_is_mpipl) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase data(64); - fapi::Target* target = i_tod_node->i_target; - uint32_t port_ctrl_reg = 0; - uint32_t port_ctrl_check_reg = 0; - - FAPI_INF("clear_tod_node: Clearing previous %s topology from %s", - (i_tod_sel==TOD_PRIMARY)?"Primary":"Secondary", - target->toEcmdString()); - do - { - if (i_tod_sel==TOD_PRIMARY) - { - FAPI_DBG("clear_tod_node: TOD_PRI_PORT_0_CTRL_REG_00040001 and TOD_SEC_PORT_0_CTRL_REG_00040003 will be cleared."); - port_ctrl_reg = TOD_PRI_PORT_0_CTRL_REG_00040001; - port_ctrl_check_reg = TOD_SEC_PORT_0_CTRL_REG_00040003; - } - else // (i_tod_sel==TOD_SECONDARY) - { - FAPI_DBG("clear_tod_node: TOD_PRI_PORT_1_CTRL_REG_00040002 and TOD_SEC_PORT_1_CTRL_REG_00040004 will be cleared."); - port_ctrl_reg = TOD_SEC_PORT_1_CTRL_REG_00040004; - port_ctrl_check_reg = TOD_PRI_PORT_1_CTRL_REG_00040002; - } - rc = fapiPutScom(*target,port_ctrl_reg,data); - if (!rc.ok()) - { - FAPI_ERR("clear_tod_node: fapiPutScom error for port_ctrl_reg SCOM."); - break; - } - rc = fapiPutScom(*target,port_ctrl_check_reg,data); - if (!rc.ok()) - { - FAPI_ERR("clear_tod_node: fapiPutScom error for port_ctrl_check_reg SCOM."); - break; - } - - if (i_is_mpipl) - { - FAPI_INF("clear_tod_node: MPIPL: switch TOD to 'Not Set' state"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setBit(0); - if (rc_ecmd) - { - FAPI_ERR("clear_tod_node: Error 0x%08X in ecmdDataBuffer setup for TOD_TX_TTYPE_5_REG_00040016 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target, TOD_TX_TTYPE_5_REG_00040016, data); - if (!rc.ok()) - { - FAPI_ERR("clear_tod_node: Could not write TOD_TX_TTYPE_5_REG_00040016"); - break; - } - } - else - { - FAPI_INF("clear_tod_node: Normal IPL: Bypass TTYPE#5"); - } - - // TOD is cleared for this node; if it has children, start clearing their registers - for (std::list<tod_topology_node*>::iterator child = (i_tod_node->i_children).begin(); - child != (i_tod_node->i_children).end(); - ++child) - { - tod_topology_node* tod_node = *child; - rc = clear_tod_node(tod_node,i_tod_sel,i_is_mpipl); - if (!rc.ok()) - { - FAPI_ERR("clear_tod_node: Failure clearing downstream TOD node!"); - break; - } - } - if (!rc.ok()) - { - break; // error in above for loop - } - } while(0); - - FAPI_INF("clear_tod_node: End"); - return rc; -} - -//------------------------------------------------------------------------------ -// function: configure_tod_node -// -// parameters: i_tod_node Reference to TOD topology (FAPI targets included within) -// i_tod_sel Specifies the topology to configure -// i_osc_sel Specifies the oscillator to use for the master -// -// returns: FAPI_RC_SUCCESS if TOD topology is successfully configured -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode configure_tod_node(tod_topology_node* i_tod_node, - const proc_tod_setup_tod_sel i_tod_sel, - const proc_tod_setup_osc_sel i_osc_sel) -{ - fapi::ReturnCode rc; - ecmdDataBufferBase data(64); - ecmdDataBufferBase data2(64); - uint32_t rc_ecmd = 0; - fapi::Target* target = i_tod_node->i_target; - - FAPI_INF("configure_tod_node: Start: Configuring %s", target->toEcmdString()); - - do - { - const bool is_mdmt = (i_tod_node->i_tod_master && i_tod_node->i_drawer_master); - - // Read TOD_PSS_MSS_CTRL_REG_00040007 in order to perserve any prior configuration - rc=fapiGetScom(*target,TOD_PSS_MSS_CTRL_REG_00040007,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: Error from fapiGetScom when retrieving TOD_PSS_MSS_CTRL_REG_00040007!"); - break; - } - FAPI_DBG("configure_tod_node: Set Master TOD/Slave TOD and Master Drawer/Slave Drawer"); - if (i_tod_sel==TOD_PRIMARY) - { - if (is_mdmt) - { - rc_ecmd |= data.setBit(TOD_PSS_MSS_CTRL_REG_PRI_M_S_TOD_SEL); - if (i_osc_sel == TOD_OSC_0 || - i_osc_sel == TOD_OSC_0_AND_1 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_0) - { - rc_ecmd |= data.clearBit(TOD_PSS_MSS_CTRL_REG_PRI_M_PATH_SEL); - } - else if (i_osc_sel == TOD_OSC_1 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_1) - { - rc_ecmd |= data.setBit(TOD_PSS_MSS_CTRL_REG_PRI_M_PATH_SEL); - } - else // i_osc_sel == TOD_OSC_NONE - { - FAPI_ERR("configure_tod_node: Invalid oscillator configuration!"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_SETUP_INVALID_TOPOLOGY); - break; - } - } - else // Slave nodes (Drawer master is still a slave) - { - rc_ecmd |= data.clearBit(TOD_PSS_MSS_CTRL_REG_PRI_M_S_TOD_SEL); - } - if (i_tod_node->i_drawer_master) - { - rc_ecmd |= data.setBit(TOD_PSS_MSS_CTRL_REG_PRI_M_S_DRAWER_SEL); - } - } - else // (i_tod_sel==TOD_SECONDARY) - { - if (is_mdmt) - { - rc_ecmd |= data.setBit(TOD_PSS_MSS_CTRL_REG_SEC_M_S_TOD_SEL); - if (i_osc_sel == TOD_OSC_1 || - i_osc_sel == TOD_OSC_0_AND_1 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_1) - { - rc_ecmd |= data.setBit(TOD_PSS_MSS_CTRL_REG_SEC_M_PATH_SEL); - } - else if (i_osc_sel == TOD_OSC_0 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_0) - { - rc_ecmd |= data.clearBit(TOD_PSS_MSS_CTRL_REG_SEC_M_PATH_SEL); - } - else // i_osc_sel == TOD_OSC_NONE - { - FAPI_ERR("configure_tod_node: Invalid oscillator configuration!"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_SETUP_INVALID_TOPOLOGY); - break; - } - } - else // Slave nodes (Drawer master is still a slave) - { - rc_ecmd |= data.clearBit(TOD_PSS_MSS_CTRL_REG_SEC_M_S_TOD_SEL); - } - if (i_tod_node->i_drawer_master) - { - rc_ecmd |= data.setBit(TOD_PSS_MSS_CTRL_REG_SEC_M_S_DRAWER_SEL); - } - } - if (rc_ecmd) - { - FAPI_ERR("configure_tod_node: Error 0x%08X in ecmdDataBuffer setup for TOD_PSS_MSS_CTRL_REG_00040007 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target,TOD_PSS_MSS_CTRL_REG_00040007,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: fapiPutScom error for TOD_PSS_MSS_CTRL_REG_00040007 SCOM."); - break; - } - - // Read TOD_S_PATH_CTRL_REG_00040005 in order to perserve any prior configuration - rc=fapiGetScom(*target,TOD_S_PATH_CTRL_REG_00040005,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: Error from fapiGetScom when retrieving TOD_S_PATH_CTRL_REG_00040005!"); - break; - } - - // Slave TODs are enabled on all but the MDMT - if (!is_mdmt) - { - FAPI_DBG("configure_tod_node: Selection of Slave OSC path"); - if (i_tod_sel==TOD_PRIMARY) - { - rc_ecmd |= data.clearBit(TOD_S_PATH_CTRL_REG_PRI_S_PATH_SEL); // For primary slave, use slave path 0 (path_0_sel=OFF) - - // Set CPS deviation to 75% (CPS deviation bits = 0xC, factor=1), 8 valid steps to enable step check - rc_ecmd |= data.insertFromRight(STEP_CHECK_CPS_DEVIATION_FACTOR_1, - TOD_S_PATH_CTRL_REG_S_PATH_STEP_CHECK_CPS_DEVIATION_FACTOR, - STEP_CHECK_CPS_DEVIATION_FACTOR_LEN); - rc_ecmd |= data.insertFromRight(STEP_CHECK_CPS_DEVIATION_75_00_PCENT, - TOD_S_PATH_CTRL_REG_S_PATH_0_STEP_CHECK_CPS_DEVIATION, - STEP_CHECK_CPS_DEVIATION_LEN); - rc_ecmd |= data.insertFromRight(STEP_CHECK_VALIDITY_COUNT_8, - TOD_S_PATH_CTRL_REG_S_PATH_0_STEP_CHECK_VALIDITY_COUNT, - STEP_CHECK_VALIDITY_COUNT_LEN); - } - else // (i_tod_sel==TOD_SECONDARY) - { - rc_ecmd |= data.setBit(TOD_S_PATH_CTRL_REG_SEC_S_PATH_SEL); // For secondary slave, use slave path 1 (path_1_sel=ON) - - // Set CPS deviation to 75% (CPS deviation bits = 0xC, factor=1), 8 valid steps to enable step check - rc_ecmd |= data.insertFromRight(STEP_CHECK_CPS_DEVIATION_FACTOR_1, - TOD_S_PATH_CTRL_REG_S_PATH_STEP_CHECK_CPS_DEVIATION_FACTOR, - STEP_CHECK_CPS_DEVIATION_FACTOR_LEN); - rc_ecmd |= data.insertFromRight(STEP_CHECK_CPS_DEVIATION_75_00_PCENT, - TOD_S_PATH_CTRL_REG_S_PATH_1_STEP_CHECK_CPS_DEVIATION, - STEP_CHECK_CPS_DEVIATION_LEN); - rc_ecmd |= data.insertFromRight(STEP_CHECK_VALIDITY_COUNT_8, - TOD_S_PATH_CTRL_REG_S_PATH_1_STEP_CHECK_VALIDITY_COUNT, - STEP_CHECK_VALIDITY_COUNT_LEN); - } - if (rc_ecmd) - { - FAPI_ERR("configure_tod_node: Error 0x%08X in ecmdDataBuffer setup for TOD_S_PATH_CTRL_REG_00040005 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target,TOD_S_PATH_CTRL_REG_00040005,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: fapiPutScom error for TOD_S_PATH_CTRL_REG_00040005 SCOM."); - break; - } - } - - // TOD_PRI_PORT_0_CTRL_REG_00040001 is only used for Primary configurations - // TOD_SEC_PORT_1_CTRL_REG_00040004 is only used for Secondary configurations - // In order to check primary and secondary networks are working simultaneously... - // - The result of TOD_PRI_PORT_0_CTRL_REG_00040001 are also inserted into TOD_SEC_PORT_0_CTRL_REG_00040003 - // (preserving i_path_delay which can be different between 40001 and 40003) - // - The result of TOD_SEC_PORT_1_CTRL_REG_00040004 are also inserted into TOD_PRI_PORT_1_CTRL_REG_00040002 - uint32_t port_ctrl_reg = 0; - uint32_t port_ctrl_check_reg = 0; - if (i_tod_sel==TOD_PRIMARY) - { - FAPI_DBG("configure_tod_node: TOD_PRI_PORT_0_CTRL_REG_00040001 will be configured for primary topology"); - port_ctrl_reg = TOD_PRI_PORT_0_CTRL_REG_00040001; - port_ctrl_check_reg = TOD_SEC_PORT_0_CTRL_REG_00040003; - } - else // (i_tod_sel==TOD_SECONDARY) - { - FAPI_DBG("configure_tod_node: TOD_SEC_PORT_1_CTRL_REG_00040004 will be configured for secondary topology"); - port_ctrl_reg = TOD_SEC_PORT_1_CTRL_REG_00040004; - port_ctrl_check_reg = TOD_PRI_PORT_1_CTRL_REG_00040002; - } - - // Read port_ctrl_reg in order to perserve any prior configuration - rc = fapiGetScom(*target,port_ctrl_reg,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: Error from fapiGetScom when retrieving port_ctrl_reg!"); - break; - } - - // Read port_ctrl_check_reg in order to perserve any prior configuration - rc = fapiGetScom(*target,port_ctrl_check_reg,data2); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: Error from fapiGetScom when retrieving port_ctrl_check_reg!"); - break; - } - - //Determine RX port - uint32_t port_rx_select_val = 0; - switch (i_tod_node->i_bus_rx) - { - case(NONE): break; // MDMT has no rx - case(XBUS0): port_rx_select_val = TOD_PORT_CTRL_REG_RX_X0_SEL; break; - case(XBUS1): port_rx_select_val = TOD_PORT_CTRL_REG_RX_X1_SEL; break; - case(XBUS2): port_rx_select_val = TOD_PORT_CTRL_REG_RX_X2_SEL; break; - case(XBUS3): port_rx_select_val = TOD_PORT_CTRL_REG_RX_X3_SEL; break; - case(ABUS0): port_rx_select_val = TOD_PORT_CTRL_REG_RX_A0_SEL; break; - case(ABUS1): port_rx_select_val = TOD_PORT_CTRL_REG_RX_A1_SEL; break; - case(ABUS2): port_rx_select_val = TOD_PORT_CTRL_REG_RX_A2_SEL; break; - } - rc_ecmd |= data.insertFromRight(port_rx_select_val, - TOD_PORT_CTRL_REG_RX, - TOD_PORT_CTRL_REG_RX_LEN); - rc_ecmd |= data2.insertFromRight(port_rx_select_val, - TOD_PORT_CTRL_REG_RX, - TOD_PORT_CTRL_REG_RX_LEN); - - //Determine which tx path should be selected for all children - uint32_t path_sel = 0; - if (is_mdmt) - { - if (i_tod_sel==TOD_PRIMARY) - { - if (i_osc_sel == TOD_OSC_0 || - i_osc_sel == TOD_OSC_0_AND_1 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_0) - { - path_sel = TOD_PORT_CTRL_REG_M_PATH_0; - } - else if (i_osc_sel == TOD_OSC_1 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_1) - { - path_sel = TOD_PORT_CTRL_REG_M_PATH_1; - } - else // i_osc_sel == TOD_OSC_NONE - { - FAPI_ERR("configure_tod_node: Invalid oscillator configuration!"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_SETUP_INVALID_TOPOLOGY); - break; - } - } - else // i_tod_sel==TOD_SECONDARY - { - if (i_osc_sel == TOD_OSC_1 || - i_osc_sel == TOD_OSC_0_AND_1 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_1) - { - path_sel = TOD_PORT_CTRL_REG_M_PATH_1; - } - else if (i_osc_sel == TOD_OSC_0 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_0) - { - path_sel = TOD_PORT_CTRL_REG_M_PATH_0; - } - else // i_osc_sel == TOD_OSC_NONE - { - FAPI_ERR("configure_tod_node: Invalid oscillator configuration!"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_SETUP_INVALID_TOPOLOGY); - break; - } - } - } - else // Chip is not master; slave path selected - { - if (i_tod_sel==TOD_PRIMARY) - { - path_sel = TOD_PORT_CTRL_REG_S_PATH_0; - } - else // (i_tod_sel==TOD_SECONDARY) - { - path_sel = TOD_PORT_CTRL_REG_S_PATH_1; - } - } - - // Loop through all of the out busses, determine which tx buses to enable as senders - uint32_t bus_sel = 0; - uint32_t bus_sel_en = 0; - - for (std::list<tod_topology_node*>::iterator child = (i_tod_node->i_children).begin(); - child != (i_tod_node->i_children).end(); - ++child) - { - tod_topology_node* tod_node = *child; - switch (tod_node->i_bus_tx) - { - case(NONE): FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_SETUP_INVALID_TOPOLOGY); break; - case(XBUS0): bus_sel = TOD_PORT_CTRL_REG_TX_X0; bus_sel_en = TOD_PORT_CTRL_REG_TX_X0_EN; break; - case(XBUS1): bus_sel = TOD_PORT_CTRL_REG_TX_X1; bus_sel_en = TOD_PORT_CTRL_REG_TX_X1_EN; break; - case(XBUS2): bus_sel = TOD_PORT_CTRL_REG_TX_X2; bus_sel_en = TOD_PORT_CTRL_REG_TX_X2_EN; break; - case(XBUS3): bus_sel = TOD_PORT_CTRL_REG_TX_X3; bus_sel_en = TOD_PORT_CTRL_REG_TX_X3_EN; break; - case(ABUS0): bus_sel = TOD_PORT_CTRL_REG_TX_A0; bus_sel_en = TOD_PORT_CTRL_REG_TX_A0_EN; break; - case(ABUS1): bus_sel = TOD_PORT_CTRL_REG_TX_A1; bus_sel_en = TOD_PORT_CTRL_REG_TX_A1_EN; break; - case(ABUS2): bus_sel = TOD_PORT_CTRL_REG_TX_A2; bus_sel_en = TOD_PORT_CTRL_REG_TX_A2_EN; break; - } - if (!rc.ok()) - { - break; // error in above switch - } - rc_ecmd |= data.insertFromRight(path_sel, bus_sel, TOD_PORT_CTRL_REG_TX_LEN); - rc_ecmd |= data.setBit(bus_sel_en); - rc_ecmd |= data2.insertFromRight(path_sel, bus_sel, TOD_PORT_CTRL_REG_TX_LEN); - rc_ecmd |= data2.setBit(bus_sel_en); - } - if (!rc.ok()) - { - break; // error in above for loop - } - if (rc_ecmd) - { - FAPI_ERR("configure_tod_node: Error 0x%08X in ecmdDataBuffer setup for port_ctrl_reg/port_ctrl_check_reg SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // All children have been configured; save both port configurations! - rc = fapiPutScom(*target,port_ctrl_reg,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: fapiPutScom error for port_ctrl_reg SCOM."); - break; - } - rc = fapiPutScom(*target,port_ctrl_check_reg,data2); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: fapiPutScom error for port_ctrl_check_reg SCOM."); - break; - } - - // Read TOD_M_PATH_CTRL_REG_00040000 in order to perserve any prior configuration - rc=fapiGetScom(*target,TOD_M_PATH_CTRL_REG_00040000,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: Error from fapiGetScom when retrieving TOD_M_PATH_CTRL_REG_00040000!"); - break; - } - - // Configure Master OSC0/OSC1 path - if (is_mdmt) - { - FAPI_DBG("configure_tod_node: Configuring Master OSC path in TOD_M_PATH_CTRL_REG_00040000"); - - if (i_osc_sel == TOD_OSC_0 || - i_osc_sel == TOD_OSC_0_AND_1 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_0 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_1) - { - FAPI_DBG("configure_tod_node: OSC0 is valid; master path-0 will be configured."); - - // OSC0 is connected - rc_ecmd |= data.clearBit(TOD_M_PATH_CTRL_REG_M_PATH_0_OSC_NOT_VALID); - - // OSC0 step alignment enabled - rc_ecmd |= data.clearBit(TOD_M_PATH_CTRL_REG_M_PATH_0_STEP_ALIGN_DIS); - - // Set 512 steps per sync for path 0 - rc_ecmd |= data.insertFromRight(TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_512, - TOD_M_PATH_CTRL_REG_M_PATH_0_SYNC_FREQ_SEL, - TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_LEN); - - // Set step check CPS deviation to 50% - rc_ecmd |= data.insertFromRight(STEP_CHECK_CPS_DEVIATION_50_00_PCENT, - TOD_M_PATH_CTRL_REG_M_PATH_0_STEP_CHECK_CPS_DEVIATION, - STEP_CHECK_CPS_DEVIATION_LEN); - - // 8 valid steps are required before step check is enabled - rc_ecmd |= data.insertFromRight(STEP_CHECK_VALIDITY_COUNT_8, - TOD_M_PATH_CTRL_REG_M_PATH_0_STEP_CHECK_VALIDITY_COUNT, - STEP_CHECK_VALIDITY_COUNT_LEN); - } - else - { - FAPI_DBG("configure_tod_node: OSC0 is not connected."); - - // OSC0 is not connected; any previous path-0 settings will be ignored - rc_ecmd |= data.setBit(TOD_M_PATH_CTRL_REG_M_PATH_0_OSC_NOT_VALID); - } - if (i_osc_sel == TOD_OSC_1 || - i_osc_sel == TOD_OSC_0_AND_1 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_0 || - i_osc_sel == TOD_OSC_0_AND_1_SEL_1) - { - FAPI_DBG("configure_tod_node: OSC1 is valid; master path-1 will be configured."); - - // OSC1 is connected - rc_ecmd |= data.clearBit(TOD_M_PATH_CTRL_REG_M_PATH_1_OSC_NOT_VALID); - - // OSC1 step alignment enabled - rc_ecmd |= data.clearBit(TOD_M_PATH_CTRL_REG_M_PATH_1_STEP_ALIGN_DIS); - - // Set 512 steps per sync for path 1 - rc_ecmd |= data.insertFromRight(TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_512, - TOD_M_PATH_CTRL_REG_M_PATH_1_SYNC_FREQ_SEL, - TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_LEN); - - // Set step check CPS deviation to 50% - rc_ecmd |= data.insertFromRight(STEP_CHECK_CPS_DEVIATION_50_00_PCENT, - TOD_M_PATH_CTRL_REG_M_PATH_1_STEP_CHECK_CPS_DEVIATION, - STEP_CHECK_CPS_DEVIATION_LEN); - - // 8 valid steps are required before step check is enabled - rc_ecmd |= data.insertFromRight(STEP_CHECK_VALIDITY_COUNT_8, - TOD_M_PATH_CTRL_REG_M_PATH_1_STEP_CHECK_VALIDITY_COUNT, - STEP_CHECK_VALIDITY_COUNT_LEN); - } - else - { - FAPI_DBG("configure_tod_node: OSC1 is not connected."); - - // OSC1 is not connected; any previous path-1 settings will be ignored - rc_ecmd |= data.setBit(TOD_M_PATH_CTRL_REG_M_PATH_1_OSC_NOT_VALID); - } - - // CPS deviation factor configures both path-0 and path-1 - rc_ecmd |= data.insertFromRight(STEP_CHECK_CPS_DEVIATION_FACTOR_1, - TOD_M_PATH_CTRL_REG_M_PATH_STEP_CHECK_DEVIATION_FACTOR, - STEP_CHECK_CPS_DEVIATION_FACTOR_LEN); - - if (rc_ecmd) - { - FAPI_ERR("configure_tod_node: Error 0x%08X in ecmdDataBuffer setup for TOD_M_PATH_CTRL_REG_00040000 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target,TOD_M_PATH_CTRL_REG_00040000,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: fapiPutScom error for TOD_M_PATH_CTRL_REG_00040000 SCOM."); - break; - } - } - - FAPI_DBG("configure_tod_node: Setting internal path delay"); - // This is the number of TOD-grid-cycles to delay the internal path (0-0xFF valid); 1 TOD-grid-cycle = 400ps (default) - if (i_tod_sel==TOD_PRIMARY) - { - // Primary topology internal path delay set TOD_PRI_PORT_0_CTRL_REG_00040001, regardless of master/slave/port - FAPI_DBG("configure_tod_node: TOD_PRI_PORT_0_CTRL_REG_00040001 will be used to set internal delay"); - port_ctrl_reg = TOD_PRI_PORT_0_CTRL_REG_00040001; - } - else // (i_tod_sel==TOD_SECONDARY) - { - // Secondary topology internal path delay set TOD_SEC_PORT_0_CTRL_REG_00040003 regardless of master/slave/port - FAPI_DBG("configure_tod_node: TOD_SEC_PORT_0_CTRL_REG_00040003 will be used to set internal delay"); - port_ctrl_reg = TOD_SEC_PORT_0_CTRL_REG_00040003; - } - rc=fapiGetScom(*target,port_ctrl_reg,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: Error from fapiGetScom when retrieving port_ctrl_reg!"); - break; - } - FAPI_DBG("configure_tod_node: configuring an internal delay of %d TOD-grid-cycles", i_tod_node->o_int_path_delay); - rc_ecmd |= data.insertFromRight(i_tod_node->o_int_path_delay, - TOD_PORT_CTRL_REG_I_PATH_DELAY, - TOD_PORT_CTRL_REG_I_PATH_DELAY_LEN); - if (rc_ecmd) - { - FAPI_ERR("configure_tod_node: Error 0x%08X in ecmdDataBuffer setup for port_ctrl_reg SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target,port_ctrl_reg,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: fapiPutScom error for port_ctrl_reg SCOM."); - break; - } - - FAPI_DBG("configure_tod_node: Enable delay logic in TOD_I_PATH_CTRL_REG_00040006"); - // Read TOD_I_PATH_CTRL_REG_00040006 in order to perserve any prior configuration - rc=fapiGetScom(*target,TOD_I_PATH_CTRL_REG_00040006,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: Error from fapiGetScom when retrieving TOD_I_PATH_CTRL_REG_00040006!"); - break; - } - - // Ensure delay is enabled - rc_ecmd |= data.clearBit(TOD_I_PATH_CTRL_REG_DELAY_DIS); - rc_ecmd |= data.clearBit(TOD_I_PATH_CTRL_REG_DELAY_ADJUST_DIS); - - // Deviation for internal OSC should be set to max, allowing backup master TOD to run the active topology, - // when switching from Slave OSC path to Master OSC path - rc_ecmd |= data.insertFromRight(STEP_CHECK_CPS_DEVIATION_93_75_PCENT, - TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION, - STEP_CHECK_CPS_DEVIATION_LEN); - rc_ecmd |= data.insertFromRight(STEP_CHECK_CPS_DEVIATION_FACTOR_1, - TOD_M_PATH_CTRL_REG_M_PATH_STEP_CHECK_DEVIATION_FACTOR, - STEP_CHECK_CPS_DEVIATION_FACTOR_LEN); - rc_ecmd |= data.insertFromRight(STEP_CHECK_VALIDITY_COUNT_8, - TOD_I_PATH_CTRL_REG_STEP_CHECK_VALIDITY_COUNT, - STEP_CHECK_VALIDITY_COUNT_LEN); - if (rc_ecmd) - { - FAPI_ERR("configure_tod_node: Error 0x%08X in ecmdDataBuffer setup for TOD_I_PATH_CTRL_REG_00040006 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(*target,TOD_I_PATH_CTRL_REG_00040006,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: fapiPutScom error for TOD_I_PATH_CTRL_REG_00040006 SCOM."); - break; - } - - FAPI_DBG("configure_tod_node: Set low order step value to 3F in TOD_CHIP_CTRL_REG_00040010"); - // Read TOD_CHIP_CTRL_REG_00040010 in order to perserve any prior configuration - rc=fapiGetScom(*target,TOD_CHIP_CTRL_REG_00040010,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: Error from fapiGetScom when retrieving TOD_CHIP_CTRL_REG_00040010!"); - break; - } - - rc = init_chip_ctrl_reg(data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: Error from init_chip_ctrl_reg while setting TOD_CHIP_CTRL_REG_00040010"); - break; - } - - rc = fapiPutScom(*target,TOD_CHIP_CTRL_REG_00040010,data); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: fapiPutScom error for TOD_CHIP_CTRL_REG_00040010 SCOM."); - break; - } - - // TOD is configured for this node; if it has children, start their configuration - for (std::list<tod_topology_node*>::iterator child = (i_tod_node->i_children).begin(); - child != (i_tod_node->i_children).end(); - ++child) - { - tod_topology_node* tod_node = *child; - rc = configure_tod_node(tod_node,i_tod_sel,i_osc_sel); - if (!rc.ok()) - { - FAPI_ERR("configure_tod_node: Failure configuring downstream node!"); - break; - } - } - if (!rc.ok()) - { - break; // error in above for loop - } - } while(0); - - FAPI_INF("configure_tod_node: End"); - return rc; -} - -//------------------------------------------------------------------------------ -// function: display_tod_node -// -// parameters: i_tod_node Reference to TOD topology -// -// returns: nothing (display-only helper function) -//------------------------------------------------------------------------------ -void display_tod_nodes(const tod_topology_node* i_tod_node, const uint32_t i_depth) -{ - - do - { - if (i_tod_node == NULL || i_tod_node->i_target == NULL) - { - FAPI_ERR("display_tod_nodes: NULL tod_node or target passed to display_tod_nodes()!"); - break; - } - FAPI_INF("display_tod_nodes: %s (Delay = %d)",i_tod_node->i_target->toEcmdString(), - i_tod_node->o_int_path_delay); - - for (std::list<tod_topology_node*>::const_iterator child = (i_tod_node->i_children).begin(); - child != (i_tod_node->i_children).end(); - ++child) - { - display_tod_nodes(*child,i_depth+1); - } - } while(0); -} - -//------------------------------------------------------------------------------ -// function: calculate_node_delays -// -// parameters: i_tod_node Reference to TOD topology -// -// returns: FAPI_RC_SUCCESS if TOD topology is successfully configured with delays -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode calculate_node_delays(tod_topology_node* i_tod_node) -{ - fapi::ReturnCode rc; - ecmdDataBufferBase data(64); - - FAPI_INF("calculate_node_delays: Start"); - do - { - // retrieve X-bus and A-bus frequencies - uint32_t freq_x = 0; - uint32_t freq_a = 0; - rc = FAPI_ATTR_GET(ATTR_FREQ_X, NULL, freq_x); - if (!rc.ok()) - { - FAPI_ERR("calculate_node_delays: Failure reading XBUS frequency attribute!"); - break; - } - rc = FAPI_ATTR_GET(ATTR_FREQ_A, NULL, freq_a); - if (!rc.ok()) - { - FAPI_ERR("calculate_node_delays: Failure reading ABUS frequency attribute!"); - break; - } - - // Bus frequencies are global for the system (i.e. A0 and A1 will always run with the same frequency) - FAPI_DBG("calculate_node_delays: XBUS=%dMHz ABUS=%dMHz", freq_x, freq_a); - - // Find the most-delayed path in the topology; this is the MDMT's delay - uint32_t longest_delay = 0; - rc = calculate_longest_topolopy_delay(i_tod_node, freq_x, freq_a, &longest_delay); - if (!rc.ok()) - { - FAPI_ERR("calculate_node_delays: Failure calculating longest topology delay!"); - break; - } - FAPI_DBG("calculate_node_delays: the longest delay is %d TOD-grid-cycles.", longest_delay); - - rc = set_topology_delays(i_tod_node, freq_x, freq_a, longest_delay); - if (!rc.ok()) - { - FAPI_ERR("calculate_node_delays: Unable to set topology delays!"); - break; - } - - // Finally, the MDMT delay must include additional TOD-grid-cycles to account for staging latches in slaves - i_tod_node->o_int_path_delay += MDMT_TOD_GRID_CYCLE_STAGING_DELAY; - } while(0); - - FAPI_INF("calculate_node_delays: End"); - return rc; -} - -//------------------------------------------------------------------------------ -// function: calculate_longest_topolopy_delay -// -// parameters: i_tod_node Reference to TOD topology -// i_freq_x XBUS frequency in MHz -// i_freq_a ABUS frequency in MHz -// o_longest_delay Contains the longest delay for the topology in TOD-grid-cycles -// (This is the delay of MDMT; children are derived from this) -// -// returns: FAPI_RC_SUCCESS if a longest TOD delay was found in topology -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode calculate_longest_topolopy_delay(tod_topology_node* i_tod_node, - const uint32_t i_freq_x, - const uint32_t i_freq_a, - uint32_t* o_longest_delay) -{ - fapi::ReturnCode rc; - - FAPI_INF("calculate_longest_topolopy_delay: Start"); - - do - { - uint32_t node_delay = 0; - - rc = calculate_node_link_delay(i_tod_node, i_freq_x, i_freq_a, &node_delay); - if (!rc.ok()) - { - FAPI_ERR("calculate_longest_topolopy_delay: Failure calculating single node delay!"); - break; - } - *o_longest_delay = node_delay; - - uint32_t current_longest_delay = 0; - for (std::list<tod_topology_node*>::const_iterator child = (i_tod_node->i_children).begin(); - child != (i_tod_node->i_children).end(); - ++child) - { - tod_topology_node* tod_node = *child; - rc = calculate_longest_topolopy_delay(tod_node, i_freq_x, i_freq_a, &node_delay); - if (!rc.ok()) - { - FAPI_ERR("calculate_longest_topolopy_delay: Failure calculating topology delay!"); - break; - } - if (node_delay>current_longest_delay) - { - current_longest_delay=node_delay; - } - } - if (!rc.ok()) - { - break; // error in above for loop - } - *o_longest_delay += current_longest_delay; - } while(0); - - FAPI_INF("calculate_longest_topolopy_delay: End"); - return rc; -} - -//------------------------------------------------------------------------------ -// function: calculate_node_link_delay -// -// parameters: i_tod_node Reference to TOD topology -// i_freq_x XBUS frequency in MHz -// i_freq_a ABUS frequency in MHz -// o_node_delay Delay of a single node in TOD-grid-cycles -// (Does not include upstream or downstream delays) -// -// returns: FAPI_RC_SUCCESS if TOD node delay is successfully calculated -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode calculate_node_link_delay(tod_topology_node* i_tod_node, - const uint32_t i_freq_x, - const uint32_t i_freq_a, - uint32_t* o_node_delay) -{ - fapi::ReturnCode rc; - ecmdDataBufferBase data(64); - uint32_t rc_ecmd = 0; - fapi::Target* target = i_tod_node->i_target; - - FAPI_INF("calculate_node_link_delay: Start"); - - do - { - // MDMT is originator and therefore has no node delay - if (i_tod_node->i_tod_master && i_tod_node->i_drawer_master) - { - *o_node_delay = 0; - } - else // slave node - { - uint32_t bus_mode_addr = 0; - uint32_t bus_mode_sel = 0; - uint32_t bus_freq = 0; - uint8_t bus_delay = 0; - switch (i_tod_node->i_bus_rx) - { - case(NONE): FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_SETUP_INVALID_TOPOLOGY); break; - case(XBUS0): bus_freq = i_freq_x; bus_mode_addr = PB_X_MODE_0x04010C0A; bus_mode_sel = PB_X_MODE_LINK_X0_ROUND_TRIP_DELAY; break; - case(XBUS1): bus_freq = i_freq_x; bus_mode_addr = PB_X_MODE_0x04010C0A; bus_mode_sel = PB_X_MODE_LINK_X1_ROUND_TRIP_DELAY; break; - case(XBUS2): bus_freq = i_freq_x; bus_mode_addr = PB_X_MODE_0x04010C0A; bus_mode_sel = PB_X_MODE_LINK_X2_ROUND_TRIP_DELAY; break; - case(XBUS3): bus_freq = i_freq_x; bus_mode_addr = PB_X_MODE_0x04010C0A; bus_mode_sel = PB_X_MODE_LINK_X3_ROUND_TRIP_DELAY; break; - case(ABUS0): bus_freq = i_freq_a; bus_mode_addr = PB_A_MODE_0x0801080A; bus_mode_sel = PB_A_MODE_LINK_A0_ROUND_TRIP_DELAY; break; - case(ABUS1): bus_freq = i_freq_a; bus_mode_addr = PB_A_MODE_0x0801080A; bus_mode_sel = PB_A_MODE_LINK_A1_ROUND_TRIP_DELAY; break; - case(ABUS2): bus_freq = i_freq_a; bus_mode_addr = PB_A_MODE_0x0801080A; bus_mode_sel = PB_A_MODE_LINK_A2_ROUND_TRIP_DELAY; break; - } - if (!rc.ok()) - { - break; // error in above switch - } - rc=fapiGetScom(*target,bus_mode_addr,data); - if (!rc.ok()) - { - FAPI_ERR("calculate_node_link_delay: Error from fapiGetScom when retrieving bus_mode_addr!"); - break; - } - rc_ecmd = data.extract(&bus_delay, bus_mode_sel, LINK_ROUND_TRIP_DELAY_LEN); - if (rc_ecmd) - { - FAPI_ERR("calculate_node_link_delay: Error 0x%08X in ecmdDataBuffer extract.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // By default, the TOD grid runs at 400ps; TOD counts its delay based on this - // Example: Bus round trip delay is 35 cycles and the bus is running at 4800MHz - // - Divide by 2 to get one-way delay time - // - Divide by 4800 * 10^6 to get delay in seconds - // - Multiply by 10^12 to get delay in picoseconds - // - Divide by 400ps to get TOD-grid-cycles - // - (To avoid including math.h) Add 1 and cast to uint32_t to round up to nearest TOD-grid-cycle - // - (To avoid including math.h) 10^12/10^6=1000000 - // - (uint32_t)(( 35 / 2 / (4800 * 10^6) * 10^12 / 400 ) + 1) = 10 TOD-grid-cycles - *o_node_delay = (uint32_t)(((double)bus_delay / 2 / (double)bus_freq * 1000000 / TOD_GRID_PS) + 1); - } - // This is not the final internal path delay, only saved so two calls aren't needed to calculate_node_link_delay - i_tod_node->o_int_path_delay = *o_node_delay; - - FAPI_DBG("calculate_node_link_delay: TOD-grid-cycles for single link: %d", *o_node_delay); - } while(0); - - FAPI_INF("calculate_node_link_delay: End"); - return rc; -} - -//------------------------------------------------------------------------------ -// function: set_topology_delays -// -// parameters: i_tod_node Reference to TOD topology -// i_freq_x XBUS frequency in MHz -// i_freq_a ABUS frequency in MHz -// i_longest_delay Longest topology delay; sub-delays are computed from it -// -// returns: FAPI_RC_SUCCESS if o_int_path_delay was set for every node in the topology -// else FAPI or ECMD error is sent through -//------------------------------------------------------------------------------ -fapi::ReturnCode set_topology_delays(tod_topology_node* i_tod_node, - const uint32_t i_freq_x, - const uint32_t i_freq_a, - const uint32_t i_longest_delay) -{ - fapi::ReturnCode rc; - FAPI_INF("set_topology_delays: Start"); - - do - { - // Retreive saved node_delay from calculate_node_link_delay instead of making a second call - i_tod_node->o_int_path_delay=i_longest_delay-(i_tod_node->o_int_path_delay); - - // Verify the delay is between 0 and 255 inclusive. - if (i_tod_node->o_int_path_delay<MIN_TOD_DELAY || - i_tod_node->o_int_path_delay>MAX_TOD_DELAY) - { - FAPI_ERR("set_topology_delays: Invalid delay of %d calculated!", i_tod_node->o_int_path_delay); - FAPI_SET_HWP_ERROR(rc, RC_PROC_TOD_SETUP_INVALID_NODE_DELAY); - break; - } - - // Recurse on downstream nodes - for (std::list<tod_topology_node*>::const_iterator child = (i_tod_node->i_children).begin(); - child != (i_tod_node->i_children).end(); - ++child) - { - tod_topology_node* tod_node = *child; - rc = set_topology_delays(tod_node,i_freq_x,i_freq_a,i_tod_node->o_int_path_delay); - if (!rc.ok()) - { - FAPI_ERR("set_topology_delays: Failure calculating topology delay!"); - break; - } - } - } while(0); - - FAPI_INF("set_topology_delays: End"); - return rc; -} - -//------------------------------------------------------------------------------ -// function: init_chip_ctrl_reg -// -// parameters: o_chic_ctrlReg_val => ecmdDataBuffer containing the -// Chip Control Status Register configuration -// -// returns: FAPI_RC_SUCCESS if TOD_CHIP_CTRL_REG_00040010's value was successfully -// calculated else ECMD error is sent back -// -//------------------------------------------------------------------------------ -fapi::ReturnCode init_chip_ctrl_reg (ecmdDataBufferBase& o_chic_ctrlReg_val) -{ - fapi::ReturnCode rc; - FAPI_INF("init_chip_ctrl_reg: Start"); - - do - { - uint32_t rc_ecmd = 0; - - // Default core sync period is 8us - rc_ecmd |= o_chic_ctrlReg_val.insertFromRight(TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL_8, - TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL, - TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL_LEN); - - // Enable internal path sync check - rc_ecmd |= o_chic_ctrlReg_val.clearBit(TOD_CHIP_CTRL_REG_I_PATH_SYNC_CHECK_DIS); - - // 1x sync boundaries for Move-TOD-To-Timebase - rc_ecmd |= o_chic_ctrlReg_val.clearBit(TOD_CHIP_CTRL_REG_MOVE_TOD_TO_TB_ON_2X_SYNC_EN); - - // Use eclipz sync mechanism - rc_ecmd |= o_chic_ctrlReg_val.clearBit(TOD_CHIP_CTRL_REG_USE_TB_SYNC_MECHANISM); - - // Use timebase step sync from internal path - rc_ecmd |= o_chic_ctrlReg_val.clearBit(TOD_CHIP_CTRL_REG_USE_TB_STEP_SYNC); - - // Chip TOD WOF incrementer ratio (eclipz mode) - // 4-bit WOF counter is incremented with each 200MHz clock cycle - rc_ecmd |= o_chic_ctrlReg_val.insertFromRight(TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VAL_3F, - TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VAL, - TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VAL_LEN); - - // Stop TOD when system checkstop occurs - rc_ecmd |= o_chic_ctrlReg_val.clearBit(TOD_CHIP_CTRL_REG_XSTOP_GATE); - - if (rc_ecmd) - { - FAPI_ERR("init_chip_ctrl_reg: Error 0x%08X in ecmdDataBuffer", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - } while(0); - - FAPI_INF("init_chip_ctrl_reg: End"); - return rc; -} - -} // extern "C" diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.H b/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.H deleted file mode 100644 index ee553ab1d..000000000 --- a/src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.H +++ /dev/null @@ -1,202 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/tod_init/proc_tod_setup/proc_tod_setup.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_tod_setup.H,v 1.9 2014/10/22 17:11:13 jklazyns Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *! -// *! TITLE : proc_tod_setup.H -// *! -// *! DESCRIPTION : Header for proc_tod_setup.C -// *! -// *! OWNER NAME : Nick Klazynski Email: jklazyns@us.ibm.com -// *! BACKUP NAME : Email: -// *! -// *! ADDITIONAL COMMENTS : -// *! -//------------------------------------------------------------------------------ - -#ifndef PROC_TOD_SETUP_H_ -#define PROC_TOD_SETUP_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include "proc_tod_utils.H" - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode -(*proc_tod_setup_FP_t) (tod_topology_node*, - const proc_tod_setup_tod_sel, - const proc_tod_setup_osc_sel); - -// function pointer which allows HWSV to calculate TOD_CHIP_CTRL_REG_00040010's value -// (Does not set the register) -typedef fapi::ReturnCode -(*init_chip_ctrl_reg_FP_t) (ecmdDataBufferBase&); - -//------------------------------------------------------------------------------ -// Function prototypes -//------------------------------------------------------------------------------ - -extern "C" -{ - -/** - * @brief Configures the TOD topology - * - * @param[in] i_tod_node Reference to TOD topology (FAPI targets included within) - * i_tod_sel Specifies the topology to configure - * i_osc_sel Specifies the oscillator to use for the master - * - * @return FAPI_RC_SUCCESS if TOD topology is successfully configured - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode proc_tod_setup(tod_topology_node* i_tod_node, - const proc_tod_setup_tod_sel i_tod_sel, - const proc_tod_setup_osc_sel i_osc_sel); - -/** - * @brief Helper function for proc_tod_setup - * - * @param[in] i_tod_node Reference to TOD topology (FAPI targets included within) - * i_tod_sel Specifies the topology to configure - * i_osc_sel Specifies the oscillator to use for the master - * - * @return FAPI_RC_SUCCESS if TOD topology is successfully configured - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode configure_tod_node(tod_topology_node* i_tod_node, - const proc_tod_setup_tod_sel i_tod_sel, - const proc_tod_setup_osc_sel i_osc_sel); - -/** - * @brief Helper function for proc_tod_setup - * - * @param[in] i_tod_node Reference to TOD topology (FAPI targets included within) - * i_tod_sel Specifies the topology to clear - * i_is_mpipl if this IPL is an MPIPL, additional setup is needed; - * determined via an attribute - * - * @return FAPI_RC_SUCCESS if TOD topology is successfully cleared - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode clear_tod_node(tod_topology_node* i_tod_node, - const proc_tod_setup_tod_sel i_tod_sel, - const fapi::ATTR_IS_MPIPL_Type i_is_mpipl); - -/** - * @brief Calculates TOD_CHIP_CTRL_REG_00040010 value; will be called - * while configuring the TOD node - * - * @param[out] o_chic_ctrlReg_val => ecmdDataBuffer containing the - * Chip Control Status Register configuration - * - * @return FAPI_RC_SUCCESS if TOD_CHIP_CTRL_REG_00040010's value was successfully - * calculated else ECMD error is sent back - */ -fapi::ReturnCode init_chip_ctrl_reg(ecmdDataBufferBase& o_chic_ctrlReg_val); - -/** - * @brief Displays the TOD topology - * - * @param[in] i_tod_node Reference to TOD topology - * - * @return void - */ -void display_tod_nodes(const tod_topology_node* i_tod_node, const uint32_t depth); - -/** - * @brief Calculates and populates the topology delays - * - * @param[in] i_tod_node Reference to TOD topology - * - * @return FAPI_RC_SUCCESS if TOD topology is successfully configured with delays - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode calculate_node_delays(tod_topology_node* i_tod_node); - -/** - * @brief Finds the longest delay in the topology (additionally sets each node delay) - * - * @param[in] i_tod_node Reference to TOD topology - * @param[in] i_freq_x XBUS frequency in MHz - * @param[in] i_freq_a ABUS frequency in MHz - * - * @param[out] o_longest_delay Longest delay in TOD-grid-cycles - * - * @return FAPI_RC_SUCCESS if a longest TOD delay was found in topology - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode calculate_longest_topolopy_delay(tod_topology_node* i_tod_node, - const uint32_t i_freq_x, - const uint32_t i_freq_a, - uint32_t* o_longest_delay); - -/** - * @brief Calculates the delay for a node in TOD-grid-cycles - * - * @param[in] i_tod_node Reference to TOD topology - * @param[in] i_freq_x XBUS frequency in MHz - * @param[in] i_freq_a ABUS frequency in MHz - * - * @param[out] o_node_delay Delay of a single node in TOD-grid-cycles - * - * @return FAPI_RC_SUCCESS if TOD node delay is successfully calculated - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode calculate_node_link_delay(tod_topology_node* i_tod_node, - const uint32_t i_freq_x, - const uint32_t i_freq_a, - uint32_t* o_node_delay); - -/** - * @brief Updates the topology struct with the final delay values - * - * @param[in] i_tod_node Reference to TOD topology - * @param[in] i_freq_x XBUS frequency in MHz - * @param[in] i_freq_a ABUS frequency in MHz - * @param[in] i_longest_delay Longest delay in the topology - * - * @return FAPI_RC_SUCCESS if o_int_path_delay was set for every node in the topology - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode set_topology_delays(tod_topology_node* i_tod_node, - const uint32_t i_freq_x, - const uint32_t i_freq_a, - const uint32_t i_longest_delay); -} // extern "C" - -#endif // PROC_TOD_SETUP_H_ diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_utils/proc_tod_utils.C b/src/usr/hwpf/hwp/tod_init/proc_tod_utils/proc_tod_utils.C deleted file mode 100644 index 63db742bd..000000000 --- a/src/usr/hwpf/hwp/tod_init/proc_tod_utils/proc_tod_utils.C +++ /dev/null @@ -1,190 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/tod_init/proc_tod_utils/proc_tod_utils.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_tod_utils.C,v 1.4 2012/10/23 19:17:00 jklazyns Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *! -// *! TITLE : proc_tod_utils.C -// *! -// *! DESCRIPTION : TOD helper functions; not called directly, but used by other -// *! FAPI procedures -// *! -// *! OWNER NAME : Nick Klazynski Email: jklazyns@us.ibm.com -// *! BACKUP NAME : Email: -// *! -// *! ADDITIONAL COMMENTS : -// *! -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "proc_tod_utils.H" -#include "p8_scom_addresses.H" - -//------------------------------------------------------------------------------ -// Function definitions -//------------------------------------------------------------------------------ - -extern "C" -{ - -//------------------------------------------------------------------------------ -// function: proc_tod_utils_get_tfmr_reg -// -// parameters: i_target => chip target -// o_tfmr_val => TFMR value read -// returns: FAPI_RC_SUCCESS if TFMR read is successful -// else FAPI or ECMD error is sent through -// -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_tod_utils_get_tfmr_reg( - const fapi::Target& i_target, - ecmdDataBufferBase& o_tfmr_val) -{ - fapi::ReturnCode rc; - ecmdDataBufferBase data(64); - uint32_t rc_ecmd = 0; - - FAPI_INF("proc_tod_utils_get_tfmr_reg: Start"); - - do - { - //FAPI_DBG("proc_tod_utils_get_tfmr_reg: Setting SPR_MODE to LPAR0/T0"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setBit(SPR_MODE_REG_MODE_SPRC_WR_EN); - rc_ecmd |= data.setBit(SPR_MODE_REG_MODE_SPRC0_SEL); - rc_ecmd |= data.setBit(SPR_MODE_REG_MODE_SPRC_T0_SEL); - if (rc_ecmd) - { - FAPI_ERR("proc_tod_utils_get_tfmr_reg: Error 0x%08X in ecmdDataBuffer setup for EX_PERV_SPR_MODE_10013281 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, EX_PERV_SPR_MODE_10013281, data); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_utils_get_tfmr_reg: fapiPutScom error for EX_PERV_SPR_MODE_10013281 SCOM."); - break; - } - //FAPI_DBG("proc_tod_utils_get_tfmr_reg: Setting SPRC to T0's TMFR"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.insertFromRight(SPRC_REG_SEL_TFMR_T0,SPRC_REG_SEL,SPRC_REG_SEL_LEN); - if (rc_ecmd) - { - FAPI_ERR("proc_tod_utils_get_tfmr_reg: Error 0x%08X in ecmdDataBuffer setup for EX_PERV_L0_SCOM_SPRC_10013280 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, EX_PERV_L0_SCOM_SPRC_10013280, data); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_utils_get_tfmr_reg: fapiPutScom error for EX_PERV_L0_SCOM_SPRC_10013280 SCOM."); - break; - } - - //FAPI_DBG("proc_tod_utils_get_tfmr_reg: Reading SPRD for T0's TMFR"); - rc = fapiGetScom(i_target, EX_PERV_SPRD_L0_100132A3, o_tfmr_val); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_utils_get_tfmr_reg: fapiGetScom error for EX_PERV_SPRD_L0_100132A3 SCOM."); - break; - } - - } while(0); - - FAPI_INF("proc_tod_utils_get_tfmr_reg: End"); - return rc; -} - -//------------------------------------------------------------------------------ -// function: proc_tod_utils_set_tfmr_reg -// -// parameters: i_target => chip target -// i_tfmr_val => TFMR value to write -// returns: FAPI_RC_SUCCESS if TFMR write is successful -// else FAPI or ECMD error is sent through -// -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_tod_utils_set_tfmr_reg( - const fapi::Target& i_target, - ecmdDataBufferBase& i_tfmr_val) -{ - fapi::ReturnCode rc; - ecmdDataBufferBase data(64); - uint32_t rc_ecmd = 0; - - FAPI_INF("proc_tod_utils_set_tfmr_reg: Start"); - - do - { - //FAPI_DBG("proc_tod_utils_set_tfmr_reg: Setting SPR_MODE to LPAR0/T0"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setBit(SPR_MODE_REG_MODE_SPRC_WR_EN); - rc_ecmd |= data.setBit(SPR_MODE_REG_MODE_SPRC0_SEL); - rc_ecmd |= data.setBit(SPR_MODE_REG_MODE_SPRC_T0_SEL); - if (rc_ecmd) - { - FAPI_ERR("proc_tod_utils_set_tfmr_reg: Error 0x%08X in ecmdDataBuffer setup for EX_PERV_SPR_MODE_10013281 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, EX_PERV_SPR_MODE_10013281, data); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_utils_set_tfmr_reg: fapiPutScom error for EX_PERV_SPR_MODE_10013281 SCOM."); - break; - } - //FAPI_DBG("proc_tod_utils_set_tfmr_reg: Setting SPRC to T0's TMFR"); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.insertFromRight(SPRC_REG_SEL_TFMR_T0,SPRC_REG_SEL,SPRC_REG_SEL_LEN); - if (rc_ecmd) - { - FAPI_ERR("proc_tod_utils_set_tfmr_reg: Error 0x%08X in ecmdDataBuffer setup for EX_PERV_L0_SCOM_SPRC_10013280 SCOM.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, EX_PERV_L0_SCOM_SPRC_10013280, data); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_utils_set_tfmr_reg: fapiPutScom error for EX_PERV_L0_SCOM_SPRC_10013280 SCOM."); - break; - } - //FAPI_DBG("proc_tod_utils_set_tfmr_reg: Writing SPRD to set T0's TMFR"); - rc = fapiPutScom(i_target, EX_PERV_SPRD_L0_100132A3, i_tfmr_val); - if (!rc.ok()) - { - FAPI_ERR("proc_tod_utils_set_tfmr_reg: fapiGetScom error for EX_PERV_SPRD_L0_100132A3 SCOM."); - break; - } - } while(0); - - FAPI_INF("proc_tod_utils_set_tfmr_reg: End"); - return rc; -} - -} // extern "C" diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_utils/proc_tod_utils.H b/src/usr/hwpf/hwp/tod_init/proc_tod_utils/proc_tod_utils.H deleted file mode 100644 index 464136f9a..000000000 --- a/src/usr/hwpf/hwp/tod_init/proc_tod_utils/proc_tod_utils.H +++ /dev/null @@ -1,500 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/tod_init/proc_tod_utils/proc_tod_utils.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_tod_utils.H,v 1.17 2015/01/08 19:50:37 jklazyns Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *! -// *! TITLE : proc_tod_utils.H -// *! -// *! DESCRIPTION : Header for proc_tod_utils.C -// *! -// *! OWNER NAME : Nick Klazynski Email: jklazyns@us.ibm.com -// *! BACKUP NAME : Email: -// *! -// *! ADDITIONAL COMMENTS : -// *! -//------------------------------------------------------------------------------ - -#ifndef PROC_TOD_UTILS_H_ -#define PROC_TOD_UTILS_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <fapi.H> -#include <list> // Required by firmware for std::list use - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// TOD-grid-cycles added to MDMT delay to account for slave staging -const uint32_t MDMT_TOD_GRID_CYCLE_STAGING_DELAY = 6; - -// Duration of TOD GRID cycle in picoseconds -const uint32_t TOD_GRID_PS = 400; - -// Minimum/Maximum allowable delay for any node -const uint32_t MIN_TOD_DELAY = 0; -const uint32_t MAX_TOD_DELAY = 0xFF; - -// TOD operation delay times for HW/sim -const uint32_t PROC_TOD_UTILS_HW_NS_DELAY = 50000; -const uint32_t PROC_TOD_UTILS_SIM_CYCLE_DELAY = 50000; - -// TOD retry count for hardware-cleared bits -const uint32_t PROC_TOD_UTIL_TIMEOUT_COUNT = 20; - -// HANG_PULSE_4_REG is needed for TB[60:63] -const uint32_t HANG_PULSE_4_REG_VAL = 0; -const uint32_t HANG_PULSE_4_REG_VAL_LEN = 6; - -//Bit definitions for SPRC_REG -const uint32_t SPRC_REG_SEL = 52; -const uint32_t SPRC_REG_SEL_LEN = 9; -const uint32_t SPRC_REG_SEL_TFMR_T0 = 0; - -//Bit definitions for SPR_MODE_REG -const uint32_t SPR_MODE_REG_MODE_SPRC_WR_EN = 3; -const uint32_t SPR_MODE_REG_MODE_SPRC0_SEL = 16; -const uint32_t SPR_MODE_REG_MODE_SPRC_T0_SEL = 20; - -//Bit definitions for TOD_M_PATH_CTRL_REG -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_0_OSC_NOT_VALID = 0; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_1_OSC_NOT_VALID = 1; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_0_STEP_ALIGN_DIS = 2; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_1_STEP_ALIGN_DIS = 3; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_0_SYNC_FREQ_SEL = 4; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_1_SYNC_FREQ_SEL = 6; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_0_STEP_CHECK_CPS_DEVIATION = 8; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_0_STEP_CHECK_VALIDITY_COUNT = 13; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_1_STEP_CHECK_CPS_DEVIATION = 16; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_1_STEP_CHECK_VALIDITY_COUNT = 21; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_STEP_CHECK_DEVIATION_FACTOR = 24; - -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_LEN = 2; - -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_512 = 0; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_2048 = 1; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_1024 = 2; -const uint32_t TOD_M_PATH_CTRL_REG_M_PATH_SYNC_FREQ_SEL_256 = 3; - -//Bit definitions for TOD_I_PATH_CTRL_REG -const uint32_t TOD_I_PATH_CTRL_REG_DELAY_DIS = 0; -const uint32_t TOD_I_PATH_CTRL_REG_DELAY_ADJUST_DIS = 1; -const uint32_t TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION_FACTOR = 6; -const uint32_t TOD_I_PATH_CTRL_REG_STEP_CHECK_CPS_DEVIATION = 8; -const uint32_t TOD_I_PATH_CTRL_REG_STEP_CHECK_VALIDITY_COUNT = 13; - -//Bit definitions for TOD_START_TOD_REG -const uint32_t TOD_START_TOD_REG_FSM_START_TOD_TRIGGER = 0; // Write-only -const uint32_t TOD_START_TOD_REG_FSM_START_TOD_DATA02 = 2; // Write-only - -//Bit definitions for TOD_LOAD_TOD_REG -const uint32_t TOD_LOAD_TOD_REG_LOAD_TOD_VAL = 0; -const uint32_t TOD_LOAD_TOD_REG_WOF = 60; - -const uint32_t TOD_LOAD_TOD_REG_LOAD_TOD_VAL_LEN = 60; -const uint32_t TOD_LOAD_TOD_REG_WOF_LEN = 4; - -//Bit definitions for TOD_VALUE_REG -const uint32_t TOD_VALUE_REG_TOD_VAL = 0; -const uint32_t TOD_VALUE_REG_WOF_COUNTER_VAL = 60; - -const uint32_t TOD_VALUE_REG_TOD_VAL_LEN = 60; -const uint32_t TOD_VALUE_REG_WOF_COUNTER_VAL_LEN = 4; - -//Bit definitions for TOD_LOAD_TOD_MOD_REG -const uint32_t TOD_LOAD_TOD_MOD_REG_FSM_LOAD_TOD_MOD_TRIG = 0; //Write-only - -//Bit definitions for TOD_TX_TTYPE_CTRL_REG -const uint32_t TOD_TX_TTYPE_CTRL_REG_TX_TTYPE_PIB_MST_ADDR_CFG = 24; -const uint32_t TOD_TX_TTYPE_CTRL_REG_TX_TTYPE_PIB_MST_ADDR_CFG_C5 = 0x15; -const uint32_t TOD_TX_TTYPE_CTRL_REG_TX_TTYPE_PIB_MST_ADDR_CFG_LEN = 8; - -//Bit definitions for TOD_CHIP_CTRL_REG -const uint32_t TOD_CHIP_CTRL_REG_TIMEBASE_EN = 0; -const uint32_t TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL = 1; -const uint32_t TOD_CHIP_CTRL_REG_I_PATH_SYNC_CHECK_DIS = 4; -const uint32_t TOD_CHIP_CTRL_REG_TX_TTYPE_PIB_MST_FSM_STATE_DIS = 5; -const uint32_t TOD_CHIP_CTRL_REG_MOVE_TOD_TO_TB_ON_2X_SYNC_EN = 7; -const uint32_t TOD_CHIP_CTRL_REG_USE_TB_SYNC_MECHANISM = 8; -const uint32_t TOD_CHIP_CTRL_REG_USE_TB_STEP_SYNC = 9; -const uint32_t TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VAL = 10; -const uint32_t TOD_CHIP_CTRL_REG_TX_TTYPE_PIB_MST_IF_RESET = 26; -const uint32_t TOD_CHIP_CTRL_REG_XSTOP_GATE = 30; -const uint32_t TOD_CHIP_CTRL_STICKY_ERROR_INJECT_EN = 31; - -const uint32_t TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL_LEN = 3; -const uint32_t TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VAL_LEN = 6; - -const uint32_t TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL_8 = 0; -const uint32_t TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL_4 = 1; -const uint32_t TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL_2 = 2; -const uint32_t TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL_1 = 3; -const uint32_t TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL_128 = 4; -const uint32_t TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL_64 = 5; -const uint32_t TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL_32 = 6; -const uint32_t TOD_CHIP_CTRL_REG_I_PATH_CORE_SYNC_PERIOD_SEL_16 = 7; - -const uint32_t TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VAL_1 = 0x1; -const uint32_t TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VAL_2 = 0x2; -const uint32_t TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VAL_3 = 0x3; -const uint32_t TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VAL_4 = 0x4; -const uint32_t TOD_CHIP_CTRL_REG_LOW_ORDER_STEP_VAL_3F = 0x3F; - -//Bit definitions for TOD_FSM_REG -const uint32_t TOD_FSM_REG_I_FSM_STATE = 0; -const uint32_t TOD_FSM_REG_TOD_IS_RUNNING = 4; - -const uint32_t TOD_FSM_REG_I_FSM_STATE_LEN = 4; - -const uint32_t TOD_FSM_REG_I_FSM_STATE_ERROR = 0x0; -const uint32_t TOD_FSM_REG_I_FSM_STATE_NOT_SET = 0x7; -const uint32_t TOD_FSM_REG_I_FSM_STATE_STOPPED = 0x1; -const uint32_t TOD_FSM_REG_I_FSM_STATE_WAIT_FOR_SYNC = 0xD; -const uint32_t TOD_FSM_REG_I_FSM_STATE_RUNNING_2 = 0x2; -const uint32_t TOD_FSM_REG_I_FSM_STATE_RUNNING_A = 0xA; -const uint32_t TOD_FSM_REG_I_FSM_STATE_RUNNING_E = 0xE; - -//Bit definitions for TOD_PSS_MSS_CTRL_REG -const uint32_t TOD_PSS_MSS_CTRL_REG_PRI_M_PATH_SEL = 0; -const uint32_t TOD_PSS_MSS_CTRL_REG_PRI_M_S_TOD_SEL = 1; -const uint32_t TOD_PSS_MSS_CTRL_REG_PRI_M_S_DRAWER_SEL = 2; -const uint32_t TOD_PSS_MSS_CTRL_REG_PRI_S_PATH1_STEP_CHECK_EN = 3; -const uint32_t TOD_PSS_MSS_CTRL_REG_PRI_M_PATH0_STEP_CHECK_EN = 4; -const uint32_t TOD_PSS_MSS_CTRL_REG_PRI_M_PATH1_STEP_CHECK_EN = 5; -const uint32_t TOD_PSS_MSS_CTRL_REG_PRI_S_PATH0_STEP_CHECK_EN = 6; -const uint32_t TOD_PSS_MSS_CTRL_REG_PRI_I_PATH_STEP_CHECK_EN = 7; -const uint32_t TOD_PSS_MSS_CTRL_REG_SEC_M_PATH_SEL = 8; -const uint32_t TOD_PSS_MSS_CTRL_REG_SEC_M_S_TOD_SEL = 9; -const uint32_t TOD_PSS_MSS_CTRL_REG_SEC_M_S_DRAWER_SEL = 10; -const uint32_t TOD_PSS_MSS_CTRL_REG_SEC_S_PATH1_STEP_CHECK_EN = 11; -const uint32_t TOD_PSS_MSS_CTRL_REG_SEC_M_PATH0_STEP_CHECK_EN = 12; -const uint32_t TOD_PSS_MSS_CTRL_REG_SEC_M_PATH1_STEP_CHECK_EN = 13; -const uint32_t TOD_PSS_MSS_CTRL_REG_SEC_S_PATH0_STEP_CHECK_EN = 14; -const uint32_t TOD_PSS_MSS_CTRL_REG_SEC_I_PATH_STEP_CHECK_EN = 15; -const uint32_t TOD_PSS_MSS_CTRL_REG_PSS_SWITCH_SYNC_ERR_DISABLE = 16; -const uint32_t TOD_PSS_MSS_CTRL_REG_I_PATH_STEP_CHECK_CPS_DEVIATION_X_DISABLE = 17; -const uint32_t TOD_PSS_MSS_CTRL_REG_STEP_CHECK_ENABLE_CHICKENSWITCH = 18; -const uint32_t TOD_PSS_MSS_CTRL_REG_MISC_RESYNC_OSC_FROM_TOD = 21; - -//Bit definitions for TOD_S_PATH_CTRL_REG -const uint32_t TOD_S_PATH_CTRL_REG_PRI_S_PATH_SEL = 0; -const uint32_t TOD_S_PATH_CTRL_REG_SEC_S_PATH_SEL = 4; -const uint32_t TOD_S_PATH_CTRL_REG_S_PATH_STEP_CHECK_CPS_DEVIATION_FACTOR = 6; -const uint32_t TOD_S_PATH_CTRL_REG_S_PATH_0_STEP_CHECK_CPS_DEVIATION = 8; -const uint32_t TOD_S_PATH_CTRL_REG_S_PATH_0_STEP_CHECK_VALIDITY_COUNT = 13; -const uint32_t TOD_S_PATH_CTRL_REG_S_PATH_1_STEP_CHECK_CPS_DEVIATION = 16; -const uint32_t TOD_S_PATH_CTRL_REG_S_PATH_1_STEP_CHECK_VALIDITY_COUNT = 21; - -const uint32_t STEP_CHECK_CPS_DEVIATION_FACTOR_LEN = 2; -const uint32_t STEP_CHECK_CPS_DEVIATION_FACTOR_1 = 0; -const uint32_t STEP_CHECK_CPS_DEVIATION_FACTOR_2 = 1; -const uint32_t STEP_CHECK_CPS_DEVIATION_FACTOR_4 = 2; -const uint32_t STEP_CHECK_CPS_DEVIATION_FACTOR_8 = 3; - -const uint32_t STEP_CHECK_CPS_DEVIATION_LEN = 4; -const uint32_t STEP_CHECK_CPS_DEVIATION_00_00_PCENT = 0x0; -const uint32_t STEP_CHECK_CPS_DEVIATION_06_25_PCENT = 0x1; -const uint32_t STEP_CHECK_CPS_DEVIATION_12_50_PCENT = 0x2; -const uint32_t STEP_CHECK_CPS_DEVIATION_18_75_PCENT = 0x3; -const uint32_t STEP_CHECK_CPS_DEVIATION_25_00_PCENT = 0x4; -const uint32_t STEP_CHECK_CPS_DEVIATION_31_25_PCENT = 0x5; -const uint32_t STEP_CHECK_CPS_DEVIATION_37_50_PCENT = 0x6; -const uint32_t STEP_CHECK_CPS_DEVIATION_43_75_PCENT = 0x7; -const uint32_t STEP_CHECK_CPS_DEVIATION_50_00_PCENT = 0x8; -const uint32_t STEP_CHECK_CPS_DEVIATION_56_25_PCENT = 0x9; -const uint32_t STEP_CHECK_CPS_DEVIATION_62_50_PCENT = 0xA; -const uint32_t STEP_CHECK_CPS_DEVIATION_68_75_PCENT = 0xB; -const uint32_t STEP_CHECK_CPS_DEVIATION_75_00_PCENT = 0xC; -const uint32_t STEP_CHECK_CPS_DEVIATION_81_25_PCENT = 0xD; -const uint32_t STEP_CHECK_CPS_DEVIATION_87_50_PCENT = 0xE; -const uint32_t STEP_CHECK_CPS_DEVIATION_93_75_PCENT = 0xF; - -const uint32_t STEP_CHECK_VALIDITY_COUNT_LEN = 3; -const uint32_t STEP_CHECK_VALIDITY_COUNT_1 = 0; -const uint32_t STEP_CHECK_VALIDITY_COUNT_2 = 1; -const uint32_t STEP_CHECK_VALIDITY_COUNT_4 = 2; -const uint32_t STEP_CHECK_VALIDITY_COUNT_8 = 3; -const uint32_t STEP_CHECK_VALIDITY_COUNT_16 = 4; -const uint32_t STEP_CHECK_VALIDITY_COUNT_32 = 5; -const uint32_t STEP_CHECK_VALIDITY_COUNT_64 = 6; -const uint32_t STEP_CHECK_VALIDITY_COUNT_128 = 7; - -//Bit definitions for TOD_{PRI,SEC}_PORT_{0,1}_CTRL_REG (40001, 40002, 40003, 40004) -const uint32_t TOD_PORT_CTRL_REG_RX = 0; -const uint32_t TOD_PORT_CTRL_REG_TX_A0 = 4; -const uint32_t TOD_PORT_CTRL_REG_TX_A1 = 6; -const uint32_t TOD_PORT_CTRL_REG_TX_A2 = 8; -const uint32_t TOD_PORT_CTRL_REG_TX_X0 = 10; -const uint32_t TOD_PORT_CTRL_REG_TX_X1 = 12; -const uint32_t TOD_PORT_CTRL_REG_TX_X2 = 14; -const uint32_t TOD_PORT_CTRL_REG_TX_X3 = 16; -const uint32_t TOD_PORT_CTRL_REG_TX_X4 = 18; -const uint32_t TOD_PORT_CTRL_REG_TX_A0_EN = 20; // 0->Receiver 1->Sender -const uint32_t TOD_PORT_CTRL_REG_TX_A1_EN = 21; // 0->Receiver 1->Sender -const uint32_t TOD_PORT_CTRL_REG_TX_A2_EN = 22; // 0->Receiver 1->Sender -const uint32_t TOD_PORT_CTRL_REG_TX_X0_EN = 23; // 0->Receiver 1->Sender -const uint32_t TOD_PORT_CTRL_REG_TX_X1_EN = 24; // 0->Receiver 1->Sender -const uint32_t TOD_PORT_CTRL_REG_TX_X2_EN = 25; // 0->Receiver 1->Sender -const uint32_t TOD_PORT_CTRL_REG_TX_X3_EN = 26; // 0->Receiver 1->Sender -const uint32_t TOD_PORT_CTRL_REG_TX_X4_EN = 27; // 0->Receiver 1->Sender -const uint32_t TOD_PORT_CTRL_REG_I_PATH_DELAY = 32; // 40001 40003 (port 0) setting only! - -const uint32_t TOD_PORT_CTRL_REG_RX_LEN = 3; -const uint32_t TOD_PORT_CTRL_REG_TX_LEN = 2; -const uint32_t TOD_PORT_CTRL_REG_I_PATH_DELAY_LEN = 8; - -const uint32_t TOD_PORT_CTRL_REG_RX_A0_SEL = 0x0; -const uint32_t TOD_PORT_CTRL_REG_RX_A1_SEL = 0x1; -const uint32_t TOD_PORT_CTRL_REG_RX_A2_SEL = 0x2; -const uint32_t TOD_PORT_CTRL_REG_RX_X0_SEL = 0x3; -const uint32_t TOD_PORT_CTRL_REG_RX_X1_SEL = 0x4; -const uint32_t TOD_PORT_CTRL_REG_RX_X2_SEL = 0x5; -const uint32_t TOD_PORT_CTRL_REG_RX_X3_SEL = 0x6; -const uint32_t TOD_PORT_CTRL_REG_RX_X4_SEL = 0x7; - -const uint32_t TOD_PORT_CTRL_REG_S_PATH_0 = 0x0; -const uint32_t TOD_PORT_CTRL_REG_S_PATH_1 = 0x1; -const uint32_t TOD_PORT_CTRL_REG_M_PATH_0 = 0x2; -const uint32_t TOD_PORT_CTRL_REG_M_PATH_1 = 0x3; - -//Bit definitions for TOD_PSS_MSS_STATUS_REG -const uint32_t TOD_PSS_MSS_STATUS_REG_M_PATH_0_STEP_CHECK_VALID = 6; -const uint32_t TOD_PSS_MSS_STATUS_REG_M_PATH_1_STEP_CHECK_VALID = 7; - -//Bit definitions for PB_X_MODE_0x04010C0A -const uint32_t PB_X_MODE_LINK_X0_ROUND_TRIP_DELAY = 24; -const uint32_t PB_X_MODE_LINK_X1_ROUND_TRIP_DELAY = 32; -const uint32_t PB_X_MODE_LINK_X2_ROUND_TRIP_DELAY = 40; -const uint32_t PB_X_MODE_LINK_X3_ROUND_TRIP_DELAY = 48; - -//Bit definitions for PB_A_MODE_0x0801080A -const uint32_t PB_A_MODE_LINK_A0_ROUND_TRIP_DELAY = 40; -const uint32_t PB_A_MODE_LINK_A1_ROUND_TRIP_DELAY = 48; -const uint32_t PB_A_MODE_LINK_A2_ROUND_TRIP_DELAY = 56; - -const uint32_t LINK_ROUND_TRIP_DELAY_LEN = 8; - -//Bit definitions for TOD_ERROR_REG -const uint32_t TOD_ERROR_REG_M_PATH_0_STEP_CHECK_ERROR = 14; -const uint32_t TOD_ERROR_REG_M_PATH_1_STEP_CHECK_ERROR = 15; -const uint32_t TOD_ERROR_REG_RX_TTYPE_0 = 38; -const uint32_t TOD_ERROR_REG_RX_TTYPE_1 = 39; -const uint32_t TOD_ERROR_REG_RX_TTYPE_2 = 40; -const uint32_t TOD_ERROR_REG_RX_TTYPE_3 = 41; -const uint32_t TOD_ERROR_REG_RX_TTYPE_4 = 42; -const uint32_t TOD_ERROR_REG_RX_TTYPE_5 = 43; - -//Bit definitions for TOD_ERROR_MASK_REG -const uint32_t TOD_ERROR_MASK_REG_M_PATH_0_STEP_CHECK_ERROR = 14; -const uint32_t TOD_ERROR_MASK_REG_M_PATH_1_STEP_CHECK_ERROR = 15; - -//Bit definitions for TFMR -const uint32_t TFMR_MAX_CYC_BET_STEPS = 0; -const uint32_t TFMR_N_CLKS_PER_STEP = 8; -const uint32_t TFMR_MASK_HMI = 10; -const uint32_t TFMR_SYNC_BIT_SEL = 11; -const uint32_t TFMR_TB_ECLIPZ = 14; -const uint32_t TFMR_LOAD_TOD_MOD = 16; -const uint32_t TFMR_MOVE_CHIP_TOD_TO_TB = 18; -const uint32_t TFMR_CLEAR_TB_ERRORS = 24; -const uint32_t TFMR_HDEC_PARITY_ERROR = 26; -const uint32_t TFMR_TBST_CORRUPT = 27; -const uint32_t TFMR_TBST_ENCODED = 28; -const uint32_t TFMR_TBST_LAST = 32; -const uint32_t TFMR_TB_ENABLED = 40; -const uint32_t TFMR_TB_VALID = 41; -const uint32_t TFMR_TB_SYNC_OCCURED = 42; -const uint32_t TFMR_TB_MISSING_SYNC = 43; -const uint32_t TFMR_TB_MISSING_STEP = 44; -const uint32_t TFMR_TB_RESIDUE_ERR = 45; -const uint32_t TFMR_FIRMWARE_CONTROL_ERROR = 46; -const uint32_t TFMR_CHIP_TOD_STATUS = 47; -const uint32_t TFMR_CHIP_TOD_INTERRUPT = 51; -const uint32_t TFMR_CHIP_TOD_PARITY_ERROR = 56; -const uint32_t TFMR_TX_PURR_PARITY_ERROR = 57; -const uint32_t TFMR_TX_SPURR_PARITY_ERROR = 58; -const uint32_t TFMR_TX_DEC_PARITY_ERROR = 59; -const uint32_t TFMR_TX_TFMR_CORRUPT = 60; -const uint32_t TFMR_TX_PURR_OVERFLOW_ERROR = 61; -const uint32_t TFMR_TX_SPURR_OVERFLOW_ERROR = 62; - -const uint32_t TFMR_MAX_CYC_BET_STEPS_LEN = 8; -const uint32_t TFMR_N_CLKS_PER_STEP_LEN = 2; -const uint32_t TFMR_SYNC_BIT_SEL_LEN = 3; -const uint32_t TFMR_TBST_ENCODED_LEN = 4; -const uint32_t TFMR_TBST_LAST_LEN = 4; -const uint32_t TFMR_CHIP_TOD_STATUS_LEN = 4; - -const uint32_t TFMR_N_CLKS_PER_STEP_1CLK = 0; -const uint32_t TFMR_N_CLKS_PER_STEP_2CLK = 1; -const uint32_t TFMR_N_CLKS_PER_STEP_3CLK = 2; -const uint32_t TFMR_N_CLKS_PER_STEP_4CLK = 3; - -const uint32_t TFMR_SYNC_BIT_SEL_1US = 0; -const uint32_t TFMR_SYNC_BIT_SEL_2US = 1; -const uint32_t TFMR_SYNC_BIT_SEL_4US = 2; -const uint32_t TFMR_SYNC_BIT_SEL_8US = 3; -const uint32_t TFMR_SYNC_BIT_SEL_16US = 4; -const uint32_t TFMR_SYNC_BIT_SEL_32US = 5; -const uint32_t TFMR_SYNC_BIT_SEL_64US = 6; - -// For TFMR_TBST_ENCODED and TFMR_TBST_LAST -const uint32_t TFMR_TBST_ENCODED_TB_RESET = 0; -const uint32_t TFMR_TBST_ENCODED_TB_SEND_TOD_MOD = 1; -const uint32_t TFMR_TBST_ENCODED_TB_NOT_SET = 2; -const uint32_t TFMR_TBST_ENCODED_TB_SYNC_WAIT = 6; -const uint32_t TFMR_TBST_ENCODED_TB_GET_TOD = 7; -const uint32_t TFMR_TBST_ENCODED_TB_RUNNING = 8; -const uint32_t TFMR_TBST_ENCODED_TB_ERROR = 9; - -const uint32_t NUM_A_BUSES = 3; -const uint32_t NUM_X_BUSES = 5; - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -extern "C" -{ - -// Used by wrapper to determine which FAPI procedure to call -enum tod_action -{ - TOD_SETUP, - TOD_INIT, - TOD_STATUS, - TOD_CLEANUP, - TOD_CHECK_OSC -}; - -// Input which determines the topology being configured -enum proc_tod_setup_tod_sel -{ - TOD_PRIMARY, // configure primary TOD - TOD_SECONDARY // configure secondary TOD -}; - -// Input which determines the master oscillator to use -enum proc_tod_setup_osc_sel -{ - TOD_OSC_0, // oscillator connected to OSC0 and not OSC1 - TOD_OSC_1, // oscillator connected to OSC1 and not OSC0 - TOD_OSC_0_AND_1, // oscillators connected to both OSC0 and OSC1 - TOD_OSC_0_AND_1_SEL_0, // oscillators connected to both OSC0 and OSC1, but OSC0 will always be selected - TOD_OSC_0_AND_1_SEL_1, // oscillators connected to both OSC0 and OSC1, but OSC1 will always be selected - TOD_OSC_NONE // No oscillators connected -}; - -// Defines the upstream connection for the given node -enum proc_tod_setup_bus -{ - NONE, // MDMT has no bus_in - XBUS0, - XBUS1, - XBUS2, - XBUS3, - ABUS0, - ABUS1, - ABUS2 -}; - -// Saves the final configuration (register values) for each node -// Port 0 will always be used for Primary, 1 will always be used for Secondary -struct proc_tod_setup_conf_regs -{ - ecmdDataBufferBase tod_m_path_ctrl_reg; - ecmdDataBufferBase tod_pri_port_0_ctrl_reg; - ecmdDataBufferBase tod_pri_port_1_ctrl_reg; - ecmdDataBufferBase tod_sec_port_0_ctrl_reg; - ecmdDataBufferBase tod_sec_port_1_ctrl_reg; - ecmdDataBufferBase tod_s_path_ctrl_reg; - ecmdDataBufferBase tod_i_path_ctrl_reg; - ecmdDataBufferBase tod_pss_mss_ctrl_reg; - ecmdDataBufferBase tod_chip_ctrl_reg; -}; - -// i_bus_rx and i_bus_tx can differ, based on system configuration (see *'d lines) -// Example (croquery eiinfo) -// Drive Chip, Drive Port, Bus, Receive Port, Receive Chip, Depth, Bus Flags, Group Id -// s1.xbus:k0:n0:s0:p00:c1, PRT_EI4_X1, BUS_EI4_X, PRT_EI4_X1, s1.xbus:k0:n0:s0:p01:c1, 00, 0x80000000, 0000 -// s1.xbus:k0:n0:s0:p01:c1, PRT_EI4_X1, BUS_EI4_X, PRT_EI4_X1, s1.xbus:k0:n0:s0:p00:c1, 10, 0x80000000, 0001 -// s1.xbus:k0:n2:s0:p00:c1, PRT_EI4_X1, BUS_EI4_X, PRT_EI4_X1, s1.xbus:k0:n2:s0:p01:c1, 00, 0x80000000, 0200 -// s1.xbus:k0:n2:s0:p01:c1, PRT_EI4_X1, BUS_EI4_X, PRT_EI4_X1, s1.xbus:k0:n2:s0:p00:c1, 10, 0x80000000, 0201 -// * s1.abus:k0:n0:s0:p00:c1, PRT_EDI_A1, BUS_EDI_A, PRT_EDI_A0, s1.abus:k0:n2:s0:p00:c0, 00, 0x80000000, 0000 -// * s1.abus:k0:n2:s0:p00:c0, PRT_EDI_A0, BUS_EDI_A, PRT_EDI_A1, s1.abus:k0:n0:s0:p00:c1, 10, 0x80000000, 0200 -// * s1.abus:k0:n0:s0:p01:c1, PRT_EDI_A1, BUS_EDI_A, PRT_EDI_A0, s1.abus:k0:n2:s0:p01:c0, 00, 0x80000000, 0001 -// * s1.abus:k0:n2:s0:p01:c0, PRT_EDI_A0, BUS_EDI_A, PRT_EDI_A1, s1.abus:k0:n0:s0:p01:c1, 10, 0x80000000, 0201 - -// TOD Topology node definition -struct tod_topology_node -{ - fapi::Target* i_target; - bool i_tod_master; - bool i_drawer_master; - proc_tod_setup_bus i_bus_rx; // Current node's bus from which step/sync is received ("Receive Port" in eiinfo) - proc_tod_setup_bus i_bus_tx; // Upstream node's bus from which step/sync is transmitted ("Drive Port" in eiinfo) - std::list<tod_topology_node*> i_children; - proc_tod_setup_conf_regs o_todRegs; - uint32_t o_int_path_delay; -}; - -// no function pointer; direct access not needed - -/** - * @brief Retrieves TFMR using indirect SPRC/SPRD method - * - * @param[in] i_target => chip target - * - * @param[out] o_tfmr_val => TFMR value read - * - * @return FAPI_RC_SUCCESS if TFMR read is successful - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode proc_tod_utils_get_tfmr_reg( - const fapi::Target& i_target, - ecmdDataBufferBase& o_tfmr_val); - -/** - * @brief Sets TFMR using indirect SPRC/SPRD method - * - * @param[in] i_target => chip target - * i_tfmr_val => TFMR value to write - * - * @return FAPI_RC_SUCCESS if TFMR write is successful - * else FAPI or ECMD error is sent through - */ -fapi::ReturnCode proc_tod_utils_set_tfmr_reg( - const fapi::Target& i_target, - ecmdDataBufferBase& i_tfmr_val); - -} // extern "C" - -#endif // PROC_TOD_UTILS_H_ diff --git a/src/usr/hwpf/hwp/tod_init/proc_tod_utils/proc_tod_utils.xml b/src/usr/hwpf/hwp/tod_init/proc_tod_utils/proc_tod_utils.xml deleted file mode 100644 index d572a1bdd..000000000 --- a/src/usr/hwpf/hwp/tod_init/proc_tod_utils/proc_tod_utils.xml +++ /dev/null @@ -1,136 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/tod_init/proc_tod_utils/proc_tod_utils.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2013,2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_tod_utils.xml,v 1.12 2014/10/16 15:32:24 jklazyns Exp $ --> -<!-- Error codes for proc_tod_utils (used by setup, init, status) --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_PROC_TOD_SETUP_INVALID_TOPOLOGY</rc> - <description>The TOD topology includes an invalid configuration</description> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_PROC_TOD_SETUP_INVALID_NODE_DELAY</rc> - <description>Node delay must be between 0 and 0xFF inclusive.</description> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_PROC_TOD_INIT_NOT_RUNNING</rc> - <description>TOD is expected to be running, but is not.</description> - <ffdc>CHIP_TARGET</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <target>CHIP_TARGET</target> - <priority>MEDIUM</priority> - </callout> - <deconfigure> - <target>CHIP_TARGET</target> - </deconfigure> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_PROC_TOD_INIT_ERROR</rc> - <description>A FIR bit is active after starting the TOD topology</description> - <ffdc>CHIP_TARGET</ffdc> - <ffdc>TOD_ERROR_REG</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <target>CHIP_TARGET</target> - <priority>MEDIUM</priority> - </callout> - <deconfigure> - <target>CHIP_TARGET</target> - </deconfigure> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_PROC_TOD_INIT_M_PATH_0_STEP_CHECK_ERROR</rc> - <description>Master Path 0 step check error is active after starting the TOD topology</description> - <ffdc>CHIP_TARGET</ffdc> - <ffdc>TOD_ERROR_REG</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_PROC_TOD_INIT_M_PATH_1_STEP_CHECK_ERROR</rc> - <description>Master Path 1 step check error is active after starting the TOD topology</description> - <ffdc>CHIP_TARGET</ffdc> - <ffdc>TOD_ERROR_REG</ffdc> - </hwpError> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_PROC_TOD_NULL_NODE</rc> - <description>An null node has been passed into the procedure</description> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <!-- ******************************************************************** --> - <registerFfdc> - <id>REG_FFDC_TOD_REGISTERS</id> - <scomRegister>TOD_M_PATH_CTRL_REG_00040000</scomRegister> - <scomRegister>TOD_PRI_PORT_0_CTRL_REG_00040001</scomRegister> - <scomRegister>TOD_PRI_PORT_1_CTRL_REG_00040002</scomRegister> - <scomRegister>TOD_SEC_PORT_0_CTRL_REG_00040003</scomRegister> - <scomRegister>TOD_SEC_PORT_1_CTRL_REG_00040004</scomRegister> - <scomRegister>TOD_S_PATH_CTRL_REG_00040005</scomRegister> - <scomRegister>TOD_I_PATH_CTRL_REG_00040006</scomRegister> - <scomRegister>TOD_PSS_MSS_CTRL_REG_00040007</scomRegister> - <scomRegister>TOD_PSS_MSS_STATUS_REG_00040008</scomRegister> - <scomRegister>TOD_M_PATH_STATUS_REG_00040009</scomRegister> - <scomRegister>TOD_S_PATH_STATUS_REG_0004000A</scomRegister> - <scomRegister>TOD_MISC_RESET_REG_0004000B</scomRegister> - <scomRegister>TOD_PROBE_SELECT_REG_0004000C</scomRegister> - <scomRegister>TOD_CHIP_CTRL_REG_00040010</scomRegister> - <scomRegister>TOD_TRACE_DATA_1_REG_0004001D</scomRegister> - <scomRegister>TOD_TRACE_DATA_2_REG_0004001E</scomRegister> - <scomRegister>TOD_TRACE_DATA_3_REG_0004001F</scomRegister> - <scomRegister>TOD_VALUE_REG_00040020</scomRegister> - <scomRegister>TOD_LOAD_TOD_REG_00040021</scomRegister> - <scomRegister>TOD_START_TOD_REG_00040022</scomRegister> - <scomRegister>TOD_LOW_ORDER_STEP_REG_00040023</scomRegister> - <scomRegister>TOD_FSM_REG_00040024</scomRegister> - <scomRegister>TOD_TX_TTYPE_CTRL_REG_00040027</scomRegister> - <scomRegister>TOD_RX_TTYPE_CTRL_REG_00040029</scomRegister> - <scomRegister>TOD_ERROR_REG_00040030</scomRegister> - <scomRegister>TOD_ERROR_MASK_STATUS_REG_00040032</scomRegister> - <scomRegister>TOD_ERROR_ROUTING_REG_00040033</scomRegister> - </registerFfdc> - <!-- ******************************************************************** --> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/utility_procedures/memory_mss_maint_cmds.xml b/src/usr/hwpf/hwp/utility_procedures/memory_mss_maint_cmds.xml deleted file mode 100644 index 98a6ee2c0..000000000 --- a/src/usr/hwpf/hwp/utility_procedures/memory_mss_maint_cmds.xml +++ /dev/null @@ -1,512 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/utility_procedures/memory_mss_maint_cmds.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2013,2014 --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<hwpErrors> -<!-- $Id: memory_mss_maint_cmds.xml,v 1.2 2014/04/07 18:41:53 gollub Exp $ --> -<!-- For file ../../ipl/fapi/mss_maint_cmds.C --> - -<!-- Original Source for RC_MSS_MAINT_UNSUCCESSFUL_FORCED_MAINT_CMD_STOP memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_UNSUCCESSFUL_FORCED_MAINT_CMD_STOP</rc> - <description>MBMSRQ[0] = 1, unsuccessful forced maint cmd stop.</description> - <!-- FFDC: Capture register we used to stop cmd --> - <ffdc>MBMCC</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBMSR</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- Callout MBA HIGH --> - <callout><target>MBA</target><priority>HIGH</priority></callout> - <!-- Deconfigure MBA --> - <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MBA --> - <gard><target>MBA</target></gard> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_START_NOT_RESET memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_START_NOT_RESET</rc> - <description>MBMCCQ[0]: maint_cmd_start not reset by hw.</description> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBMCC</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- FFDC: MBMCT[0:4] contains the cmd type set in hw --> - <ffdc>MBMCT</ffdc> - <!-- Callout MBA HIGH --> - <callout><target>MBA</target><priority>HIGH</priority></callout> - <!-- Deconfigure MBA --> - <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MBA --> - <gard><target>MBA</target></gard> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_STOP_NOT_RESET memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_STOP_NOT_RESET</rc> - <description>MBMCCQ[1]: maint_cmd_stop not reset by hw.</description> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBMCC</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- FFDC: MBMCT[0:4] contains the cmd type previously run --> - <ffdc>MBMCT</ffdc> - <!-- Callout MBA HIGH --> - <callout><target>MBA</target><priority>HIGH</priority></callout> - <!-- Deconfigure MBA --> - <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MBA --> - <gard><target>MBA</target></gard> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_CMD_IN_PROGRESS memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_CMD_IN_PROGRESS</rc> - <description>MBMSRQ[0]: Can't start new cmd if previous cmd still in progress.</description> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBMSR</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- FFDC: MBMCT[0:4] contains the cmd type previously run --> - <ffdc>MBMCT</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> - <!-- Callout MBA LOW --> - <callout><target>MBA</target><priority>LOW</priority></callout> - <!-- Deconfigure MBA --> - <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MBA --> - <gard><target>MBA</target></gard> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_NO_MEM_CNFG memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_NO_MEM_CNFG</rc> - <description>MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBAXCR</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_CCS_MUX_NOT_MAINLINE memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_CCS_MUX_NOT_MAINLINE</rc> - <description>CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>CCS_MODE</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_ECC_DISABLED memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_ECC_DISABLED</rc> - <description>MBSECC[0] non zero, meaning ECC check/correct disabled.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBSECC</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_INVALID_CMD memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_INVALID_CMD</rc> - <description>MBAFIRQ[0], invalid_maint_cmd.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBAFIR</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- FFDC: MBMCT[0:4] contains the cmd type set in hw --> - <ffdc>MBMCT</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_INVALID_ADDR memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_INVALID_ADDR</rc> - <description>MBAFIRQ[1], cmd started with invalid_maint_address.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBAFIR</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- FFDC: MBMCT[0:4] contains the cmd type set in hw --> - <ffdc>MBMCT</ffdc> - <!-- Collect registers as FFDC --> - <collectRegisterFfdc> - <id>REG_FFDC_INVALID_ADDR</id> - <target>MBA</target> - </collectRegisterFfdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_CMD_TIMEOUT memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_CMD_TIMEOUT</rc> - <description>Maint cmd timeout.</description> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- Collect MBA registers as FFDC --> - <collectRegisterFfdc> - <id>REG_FFDC_CMD_TIMEOUT_MBA_REGS</id> - <target>MBA</target> - </collectRegisterFfdc> - <!-- Collect MBS registers as FFDC --> - <collectRegisterFfdc> - <id>REG_FFDC_CMD_TIMEOUT_MBS_REGS</id> - <target>CENTAUR</target> - </collectRegisterFfdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> - <!-- Callout MBA LOW --> - <callout><target>MBA</target><priority>LOW</priority></callout> - <!-- Deconfigure MBA --> - <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MBA --> - <gard><target>MBA</target></gard> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_ZERO_DDR_FREQ memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_ZERO_DDR_FREQ</rc> - <description>ATTR_MSS_FREQ set to zero so can't calculate scrub rate.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture command type we are trying to run --> - <ffdc>CMD_TYPE</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH</rc> - <description>Invalid dramSize or dramWidth in MBAXCRn.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBAXCR</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: DRAM gen: DDR3 or DDR4 --> - <ffdc>DRAM_GEN</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_INVALID_DIMM_CNFG memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_INVALID_DIMM_CNFG</rc> - <description>MBAXCRn configured with invalid combination of configType, configSubType, slotConfig.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: Capture register we are checking --> - <ffdc>MBAXCR</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_GET_ADDRESS_RANGE_BAD_INPUT memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_GET_ADDRESS_RANGE_BAD_INPUT</rc> - <description>i_rank input to mss_get_address_range out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: RANK we are trying to get address range for --> - <ffdc>RANK</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_GET_MARK_STORE_BAD_INPUT memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_GET_MARK_STORE_BAD_INPUT</rc> - <description>i_rank input to mss_get_mark_store out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: RANK we are trying read markstore for --> - <ffdc>RANK</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_X4_SYMBOL_ON_READ memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_X4_SYMBOL_ON_READ</rc> - <description>Symbol mark not allowed in x4 mode.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width (should be x4) --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading markstore for --> - <ffdc>RANK</ffdc> - <!-- FFDC: Markstore with non-zero symbol entry --> - <ffdc>MARKSTORE</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_INVALID_MARKSTORE memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_INVALID_MARKSTORE</rc> - <description>Invalid galois field in markstore.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading markstore for --> - <ffdc>RANK</ffdc> - <!-- FFDC: Markstore with invalid galois field --> - <ffdc>MARKSTORE</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_PUT_MARK_STORE_BAD_INPUT memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_PUT_MARK_STORE_BAD_INPUT</rc> - <description>i_rank input to mss_put_mark_store out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: RANK we are trying write markstore for --> - <ffdc>RANK</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_X4_SYMBOL_ON_WRITE memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_X4_SYMBOL_ON_WRITE</rc> - <description>Symbol mark not allowed in x4 mode.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width (should be x4) --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading markstore for --> - <ffdc>RANK</ffdc> - <!-- FFDC: Symbol mark we are trying to write to markstore --> - <ffdc>SYMBOL_MARK</ffdc> - <!-- FFDC: Chip mark we are trying to write to markstore --> - <ffdc>CHIP_MARK</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_INVALID_SYMBOL_INDEX memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_INVALID_SYMBOL_INDEX</rc> - <description>Symbol index out of range.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading markstore for --> - <ffdc>RANK</ffdc> - <!-- FFDC: Symbol mark we are trying to write to markstore --> - <ffdc>SYMBOL_MARK</ffdc> - <!-- FFDC: Chip mark we are trying to write to markstore --> - <ffdc>CHIP_MARK</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_INVALID_CHIP_INDEX memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_INVALID_CHIP_INDEX</rc> - <description>Not first symbol index of a chip.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading markstore for --> - <ffdc>RANK</ffdc> - <!-- FFDC: Symbol mark we are trying to write to markstore --> - <ffdc>SYMBOL_MARK</ffdc> - <!-- FFDC: Chip mark we are trying to write to markstore --> - <ffdc>CHIP_MARK</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED</rc> - <description>Markstore write may have been blocked due to MPE FIR set.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading markstore for --> - <ffdc>RANK</ffdc> - <!-- FFDC: Symbol mark we are trying to write to markstore --> - <ffdc>SYMBOL_MARK</ffdc> - <!-- FFDC: Chip mark we are trying to write to markstore --> - <ffdc>CHIP_MARK</ffdc> - <!-- FFDC: MBECCFIR showing MPE --> - <ffdc>MBECCFIR</ffdc> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_GET_STEER_MUX_BAD_INPUT memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_GET_STEER_MUX_BAD_INPUT</rc> - <description>i_rank or i_muxType input to mss_get_steer_mux out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: RANK we are reading steer mux for --> - <ffdc>RANK</ffdc> - <!-- FFDC: MUX_TYPE: read or write --> - <ffdc>MUX_TYPE</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_INVALID_STEER_MUX memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_INVALID_STEER_MUX</rc> - <description>Steer mux index out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading steer mux for --> - <ffdc>RANK</ffdc> - <!-- FFDC: MUX_TYPE: read or write --> - <ffdc>MUX_TYPE</ffdc> - <!-- FFDC: Capture steer mux --> - <ffdc>STEER_MUX</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_PUT_STEER_MUX_BAD_INPUT memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_PUT_STEER_MUX_BAD_INPUT</rc> - <description>i_rank or i_muxType or i_steerType or i_symbol input to mss_put_steer_mux out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: RANK we are writing steer mux for --> - <ffdc>RANK</ffdc> - <!-- FFDC: MUX_TYPE: read or write --> - <ffdc>MUX_TYPE</ffdc> - <!-- FFDC: STEER_TYPE: port0 spare, port1 spare or ecc spare --> - <ffdc>STEER_TYPE</ffdc> - <!-- FFDC: SYMBOL: 0-71 --> - <ffdc>SYMBOL</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER</rc> - <description>Trying to steer invalid symbol.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading steer mux for --> - <ffdc>RANK</ffdc> - <!-- FFDC: MUX_TYPE: read or write --> - <ffdc>MUX_TYPE</ffdc> - <!-- FFDC: STEER_TYPE: port0, port1, or ecc spare --> - <ffdc>STEER_TYPE</ffdc> - <!-- FFDC: SYMBOL: Symbol we are trying to steer --> - <ffdc>SYMBOL</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_NO_X8_ECC_SPARE memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_NO_X8_ECC_SPARE</rc> - <description>Invalid to use ECC spare in x8 mode.</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: DRAM width --> - <ffdc>DRAM_WIDTH</ffdc> - <!-- FFDC: RANK we are reading steer mux for --> - <ffdc>RANK</ffdc> - <!-- FFDC: MUX_TYPE: read or write --> - <ffdc>MUX_TYPE</ffdc> - <!-- FFDC: STEER_TYPE: port0, port1, or ecc spare --> - <ffdc>STEER_TYPE</ffdc> - <!-- FFDC: SYMBOL: Symbol we are trying to steer --> - <ffdc>SYMBOL</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_DO_STEER_INPUT_OUT_OF_RANGE memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_DO_STEER_INPUT_OUT_OF_RANGE</rc> - <description>i_rank or i_symbol input to mss_do_steer out of range</description> - <!-- FFDC: MBA target --> - <ffdc>MBA</ffdc> - <!-- FFDC: RANK we are writing steer mux for --> - <ffdc>RANK</ffdc> - <!-- FFDC: SYMBOL: 0-71 --> - <ffdc>SYMBOL</ffdc> - <!-- FFDC: X4ECCSPARE: true or false --> - <ffdc>X4ECCSPARE</ffdc> - <!-- Callout FW HIGH --> - <callout><procedure>CODE</procedure><priority>HIGH</priority></callout> -</hwpError> - -<!-- Original Source for RC_MSS_MAINT_NO_UE_TRAP memory_errors.xml --> - <hwpError> - <rc>RC_MSS_MAINT_NO_UE_TRAP</rc> - <description>IPL UE trapping didn't work.</description> - <!-- FFDC: Capture UE trap contents --> - <ffdc>UE_TRAP0</ffdc> - <ffdc>UE_TRAP1</ffdc> - <!-- FFDC: MBMCT[0:4] contains the cmd type --> - <ffdc>MBMCT</ffdc> - <!-- FFDC: MBMMR[4:7] contains the pattern index --> - <ffdc>MBMMR</ffdc> - <!-- FFDC: MBSTR[59]: UE trap enable bit --> - <ffdc>MBSTR</ffdc> - <!-- Callout MBA HIGH --> - <callout><target>MBA</target><priority>HIGH</priority></callout> - <!-- Deconfigure MBA --> - <deconfigure><target>MBA</target></deconfigure> - <!-- Create GARD record for MBA --> - <gard><target>MBA</target></gard> -</hwpError> - - -</hwpErrors> diff --git a/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C b/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C deleted file mode 100644 index 3b8427b70..000000000 --- a/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C +++ /dev/null @@ -1,7379 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_maint_cmds.C,v 1.39 2015/08/12 17:46:32 lwmulkey Exp $ -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Date: | Author: | Comment: -//---------|----------|---------|----------------------------------------------- -// | 11/02/11 | gollub | Created -// | 12/01/11 | gollub | Fixed problem with end address -// | 03/30/12 | gollub | Made stop condition parm into a mask. -// | | | Added support for both MBAs -// | | | Calculate real start/end address, but run on 2 -// | | | addresses if sim -// | 04/25/12 | gollub | Updated error paths -// | 05/23/12 | gollub | Updates from review. -// | 07/13/12 | gollub | Updates from review. -// 1.8 | 07/16/12 | bellows | added in Id tag -// 1.9 | 07/18/12 | gollub | Updates from review. -// | | | Updates for timebase scrub. -// 1.10 | 07/24/12 | gollub | Fix UE/SUE status bit swap in MBMACA -// | | | Added stop condition enums -// | | | STOP_IMMEDIATE -// | | | ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR -// | | | Now require cleanupCmd() for super fast read -// | | | to disable rrq fifo mode when done. -// 1.11 | 09/07/12 | gollub | Updates from review. -// | | | Support for more patterns. -// 1.12 | 09/29/12 | gollub | Added mss_restore_DRAM_repairs -// 1.13 | 10/08/12 | gollub | Updated with 12h scrub rate calculation -// 1.14 | 11/02/12 | gollub | Updates from review. -// 1.15 | 11/08/12 | gollub | Added timebase steer cleanup -// | | | Updates to traces. -// 1.16 | 11/21/12 | gollub | Updates from review. -// 1.17 | 12/19/12 | gollub | Added UE isolation -// 1.18 | 01/15/13 | gollub | Added check for valid dimm before calling -// | | | dimmGetBadDqBitmap -// 1.19 | 01/31/13 | gollub | Updated MDI bits for random pattern so -// | | | don't get SUEs -// | | | Added mss_check_steering -// | | | Added mss_do_steering -// | | | Added mss_stopCmd -// | | | Removed cleanupCmd for cmds that didn't use it -// 1.20 | 03/08/13 | gollub | Mask MBSPA[0][8] during increment cmd -// 1.21 | 04/19/13 | gollub | Fix: Slow down fast scrub rate. -// | | | Fix: Was skippng reg update for slow scrub rate -// | | | Fix: Clear MBMCC[1] stop bit after forcing a stop -// | | | Add: Added target to FAPI_ERR traces -// 1.22 | 04/30/13 | mjjones | Removed unused variable -// 1.23 | 05/03/13 | gollub | Clear cmd complete attention in mss_stopCmd -// 1.24 | 05/20/13 | gollub | Updates from review. -// 1.25 | 05/24/13 | gollub | Added DDR4 support to mss_get_address_range -// | | | Disabled superfast increment mode if DDR4 - due to DD1 bug -// 1.26 | 08/23/13 | gollub | Added x4 ECC mode support -// | | | Clear inject type: MBECTLQ after atomic inject -// | | | Updated random data seed -// | | | Ordered display output by beat 0-7 -// 1.27 | 09/03/13 | gollub | Removed unused variables -// 1.28 | 10/31/13 | gollub | Removed support for stop condition enum -// | | | ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR -// | | | DD2: enable (fixed) -// | | | DD1: disable (broken) -// 1.29 | 11/19/13 | bellows | Swapped to use ATTR_VPD_DIMM_SPARE -// 1.30 | 02/07/14 |adityamd | Added support to mss_restore_DRAM_repairs to be accessed at Standby -// 1.31 |12-FEB-14 | bellows | Workaround for ENABLE_RCE_WITH_OTHER_ERRORS_HW246685 -// 1.32 |20-FEB-14 | bellows | RAS review updates -// 1.33 |07-MAR-14 | gollub | Code review updates for: -// | | | mss_restore_DRAM_repairs -// | | | mss_restore_DRAM_repairs_asm -// | | | mss_get_dummy_mark_store -// | | | mss_put_dummy_mark_store -// | | | mss_get_dummy_steer_mux -// | | | mss_put_dummy_steer_mux -// | | | SW249600: Adding 1ms delay to allow cmd to stop properly in mss_stopCmd() -// 1.34 |11-MAR-14 | gollub | SW250519: More options for enum TimeBaseSpeed -// 1.35 |07-APR-14 | gollub | Added enable/disable exit point 1 to get/put markstore functions -// | | | Added official x4 and x8 patterns -// | | | Implemented correct scrub interval settings for: -// | | | FAST_MIN_BW_IMPACT -// | | | FAST_MED_BW_IMPACT -// | | | FAST_MAX_BW_IMPACT -// 1.36 |07-AUG-14 | gollub | SW272428: Change delay from 250mSec to 2 Sec in mss_do_steering -// | | | to account for extra time needed with 128G DIMMs -// 1.37 |13-OCT-14 | gollub | SW273790: Change delay from 2 Sec back to 250mSec in mss_do_steering. -// | | | The added delay did not help the steer problem, and added too much -// | | | IPL time to the mnfg IPL when all spares are deployed. -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <mss_maint_cmds.H> -#include <cen_scom_addresses.H> -#include <dimmBadDqBitmapFuncs.H> - -using namespace fapi; - - -//------------------------------------------------------------------------------ -// Constants and enums -//------------------------------------------------------------------------------ - -/** - * @brief Max 8 master ranks per MB - */ -const uint8_t MSS_MAX_RANKS = 8; - -/** - * @brief The number of symbols per rank - */ -const uint8_t MSS_SYMBOLS_PER_RANK = 72; - - -/** - * @brief The used for symbol ranges on port 0: Symbols 71-40, 7-4 - */ -const uint8_t MSS_PORT_0_SYMBOL_71 = 71; -const uint8_t MSS_PORT_0_SYMBOL_40 = 40; -const uint8_t MSS_PORT_0_SYMBOL_7 = 7; -const uint8_t MSS_PORT_0_SYMBOL_4 = 4; - -/** - * @brief The used for symbol ranges on port 1: Symbols 39-8, 3-0 - */ -const uint8_t MSS_PORT_1_SYMBOL_39 = 39; -const uint8_t MSS_PORT_1_SYMBOL_8 = 8; -const uint8_t MSS_PORT_1_SYMBOL_3 = 3; -const uint8_t MSS_PORT_1_SYMBOL_0 = 0; - - - - - -/** - * @brief 9 x8 DRAMs we can steer, plus one for no steer option - */ -const uint8_t MSS_X8_STEER_OPTIONS_PER_PORT = 10; - -/** - * @brief 18 x4 DRAMs we can steer on port0, plus one for no steer option - */ -const uint8_t MSS_X4_STEER_OPTIONS_PER_PORT0 = 19; - -/** - * @brief 17 x4 DRAMs we can steer on port1, plus one no steer option - * NOTE: Only 17 DRAMs we can steer since one DRAM is used for the - * ECC spare. - */ -const uint8_t MSS_X4_STEER_OPTIONS_PER_PORT1 = 18; - -/** - * @brief 18 on port0, 17 on port1, plus one no steer option - * NOTE: Can's use ECC spare to fix bad spare DRAMs - */ -const uint8_t MSS_X4_ECC_STEER_OPTIONS = 36; - -/** - * @brief Max 8 patterns - */ -const uint8_t MSS_MAX_PATTERNS = 9; - - -namespace mss_MemConfig -{ -/** - * @brief DRAM size in gigabits, used to determine address range for maint cmds - */ - enum DramSize - { - GBIT_2 = 0, - GBIT_4 = 1, - GBIT_8 = 2, - }; - -/** - * @brief DRAM width, used to determine address range for maint cmds - */ - enum DramWidth - { - X4 = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4, - X8 = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8, - }; - -/** - * @brief DRAM row, column, and bank bits, used to determine address range - * for maint cmds - */ - enum MemOrg - { - ROW_14 = 0x00003FFF, - ROW_15 = 0x00007FFF, - ROW_16 = 0x0000FFFF, - ROW_17 = 0x0001FFFF, - COL_10 = 0x000003F8, // c2, c1, c0 always 0 - COL_11 = 0x000007F8, // c2, c1, c0 always 0 - COL_12 = 0x00000FF8, // c2, c1, c0 always 0 - BANK_3 = 0x00000007, - BANK_4 = 0x0000000F, - }; - -/** - * @brief Spare DRAM config, used to identify what spares exist - */ - enum SpareDramConfig - { - NO_SPARE = 0, - LOW_NIBBLE = 1, // x4 spare (low nibble: default) - HIGH_NIBBLE = 2, // x4 spare (high nibble: no plan to use) - FULL_BYTE = 3 // x8 dpare - }; - -}; - - - - -static const uint32_t mss_mbaxcr[2]={ - // port0/1 port2/3 - MBAXCR01Q_0x0201140B, MBAXCR23Q_0x0201140C}; - -static const uint32_t mss_mbeccfir[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_0x02011440, MBS_ECC1_MBECCFIR_0x02011480}; - -static const uint32_t mss_mbsecc[2]={ - // port0/1 port2/3 - MBS_ECC0_MBSECCQ_0x0201144A, MBS_ECC1_MBSECCQ_0x0201148A}; - -static const uint32_t mss_markStoreRegs[8][2]={ - // port0/1 port2/3 - {MBS_ECC0_MBMS0_0x0201144B, MBS_ECC1_MBMS0_0x0201148B}, - {MBS_ECC0_MBMS1_0x0201144C, MBS_ECC1_MBMS1_0x0201148C}, - {MBS_ECC0_MBMS2_0x0201144D, MBS_ECC1_MBMS2_0x0201148D}, - {MBS_ECC0_MBMS3_0x0201144E, MBS_ECC1_MBMS3_0x0201148E}, - {MBS_ECC0_MBMS4_0x0201144F, MBS_ECC1_MBMS4_0x0201148F}, - {MBS_ECC0_MBMS5_0x02011450, MBS_ECC1_MBMS5_0x02011490}, - {MBS_ECC0_MBMS6_0x02011451, MBS_ECC1_MBMS6_0x02011491}, - {MBS_ECC0_MBMS7_0x02011452, MBS_ECC1_MBMS7_0x02011492}}; - -static const uint32_t mss_mbstr[2]={ - // port0/1 port2/3 - MBS01_MBSTRQ_0x02011655, MBS23_MBSTRQ_0x02011755}; - -static const uint32_t mss_mbmmr[2]={ - // port0/1 port2/3 - MBS_ECC0_MBMMRQ_0x0201145B, MBS_ECC1_MBMMRQ_0x0201149B}; - -static const uint32_t mss_readMuxRegs[8][2]={ - // port0/1 port2/3 - {MBS_ECC0_MBSBS0_0x0201145E, MBS_ECC1_MBSBS0_0x0201149E}, - {MBS_ECC0_MBSBS1_0x0201145F, MBS_ECC1_MBSBS1_0x0201149F}, - {MBS_ECC0_MBSBS2_0x02011460, MBS_ECC1_MBSBS2_0x020114A0}, - {MBS_ECC0_MBSBS3_0x02011461, MBS_ECC1_MBSBS3_0x020114A1}, - {MBS_ECC0_MBSBS4_0x02011462, MBS_ECC1_MBSBS4_0x020114A2}, - {MBS_ECC0_MBSBS5_0x02011463, MBS_ECC1_MBSBS5_0x020114A3}, - {MBS_ECC0_MBSBS6_0x02011464, MBS_ECC1_MBSBS6_0x020114A4}, - {MBS_ECC0_MBSBS7_0x02011465, MBS_ECC1_MBSBS7_0x020114A5}}; - -static const uint32_t mss_writeMuxRegs[8]={ - - MBA01_MBABS0_0x03010440, - MBA01_MBABS1_0x03010441, - MBA01_MBABS2_0x03010442, - MBA01_MBABS3_0x03010443, - MBA01_MBABS4_0x03010444, - MBA01_MBABS5_0x03010445, - MBA01_MBABS6_0x03010446, - MBA01_MBABS7_0x03010447}; - -//------------------------------------------------------------------------------ -// Conversion from symbol index to galois field stored in markstore -//------------------------------------------------------------------------------ -static const uint8_t mss_symbol2Galois[MSS_SYMBOLS_PER_RANK] = - { - 0x80, 0xa0, 0x90, 0xf0, 0x08, 0x0a, 0x09, 0x0f, // symbols 0- 7 - 0x98, 0xda, 0xb9, 0x7f, 0x91, 0xd7, 0xb2, 0x78, // symbols 8-15 - 0x28, 0xea, 0x49, 0x9f, 0x9a, 0xd4, 0xbd, 0x76, // symbols 16-23 - 0x60, 0xb0, 0xc0, 0x20, 0x06, 0x0b, 0x0c, 0x02, // symbols 24-31 - 0xc6, 0xfb, 0x1c, 0x42, 0xca, 0xf4, 0x1d, 0x46, // symbols 32-39 - 0xd6, 0x8b, 0x3c, 0xc2, 0xcb, 0xf3, 0x1f, 0x4e, // symbols 40-47 - 0xe0, 0x10, 0x50, 0xd0, 0x0e, 0x01, 0x05, 0x0d, // symbols 48-55 - 0x5e, 0x21, 0xa5, 0x3d, 0x5b, 0x23, 0xaf, 0x3e, // symbols 56-63 - 0xfe, 0x61, 0x75, 0x5d, 0x51, 0x27, 0xa2, 0x38, // symbols 64-71 - }; - - - -static const uint8_t mss_x8dramSparePort0Index_to_symbol[MSS_X8_STEER_OPTIONS_PER_PORT]={ - // symbol - MSS_INVALID_SYMBOL, // Port0 DRAM spare not used - 68, // DRAM 17 (x8) - 64, // DRAM 16 (x8) - 60, // DRAM 15 (x8) - 56, // DRAM 14 (x8) - 52, // DRAM 13 (x8) - 48, // DRAM 12 (x8) - 44, // DRAM 11 (x8) - 40, // DRAM 10 (x8) - 4}; // DRAM 1 (x8) - -static const uint8_t mss_x4dramSparePort0Index_to_symbol[MSS_X4_STEER_OPTIONS_PER_PORT0]={ - // symbol - MSS_INVALID_SYMBOL, // Port0 DRAM spare not used - 70, // DRAM 35 (x4) - 68, // DRAM 34 (x4) - 66, // DRAM 33 (x4) - 64, // DRAM 32 (x4) - 62, // DRAM 31 (x4) - 60, // DRAM 30 (x4) - 58, // DRAM 29 (x4) - 56, // DRAM 28 (x4) - 54, // DRAM 27 (x4) - 52, // DRAM 26 (x4) - 50, // DRAM 25 (x4) - 48, // DRAM 24 (x4) - 46, // DRAM 23 (x4) - 44, // DRAM 22 (x4) - 42, // DRAM 21 (x4) - 40, // DRAM 20 (x4) - 6, // DRAM 3 (x4) - 4}; // DRAM 2 (x4) - - - -static const uint8_t mss_x8dramSparePort1Index_to_symbol[MSS_X8_STEER_OPTIONS_PER_PORT]={ - // symbol - MSS_INVALID_SYMBOL, // Port1 DRAM spare not used - 36, // DRAM 9 (x8) - 32, // DRAM 8 (x8) - 28, // DRAM 7 (x8) - 24, // DRAM 6 (x8) - 20, // DRAM 5 (x8) - 16, // DRAM 4 (x8) - 12, // DRAM 3 (x8) - 8, // DRAM 2 (x8) - 0}; // DRAM 0 (x8) - - - -static const uint8_t mss_x4dramSparePort1Index_to_symbol[MSS_X4_STEER_OPTIONS_PER_PORT1]={ - // symbol - MSS_INVALID_SYMBOL, // Port1 DRAM spare not used - 38, // DRAM 19 (x4) - 36, // DRAM 18 (x4) - 34, // DRAM 17 (x4) - 32, // DRAM 16 (x4) - 30, // DRAM 15 (x4) - 28, // DRAM 14 (x4) - 26, // DRAM 13 (x4) - 24, // DRAM 12 (x4) - 22, // DRAM 11 (x4) - 20, // DRAM 10 (x4) - 18, // DRAM 9 (x4) - 16, // DRAM 8 (x4) - 14, // DRAM 7 (x4) - 12, // DRAM 6 (x4) - 10, // DRAM 5 (x4) - 8, // DRAM 4 (x4) - 2}; // DRAM 1 (x4) -// NOTE: DRAM 0 (x4) (symbols 0,1) on Port1 is used for the ECC spare, -// so can't use DRAM spare to fix DRAM 0. - - - -static const uint8_t mss_eccSpareIndex_to_symbol[MSS_X4_ECC_STEER_OPTIONS]={ - // symbol - MSS_INVALID_SYMBOL, // ECC spare not used - 70, // DRAM 35 (x4) - 68, // DRAM 34 (x4) - 66, // DRAM 33 (x4) - 64, // DRAM 32 (x4) - 62, // DRAM 31 (x4) - 60, // DRAM 30 (x4) - 58, // DRAM 29 (x4) - 56, // DRAM 28 (x4) - 54, // DRAM 27 (x4) - 52, // DRAM 26 (x4) - 50, // DRAM 25 (x4) - 48, // DRAM 24 (x4) - 46, // DRAM 23 (x4) - 44, // DRAM 22 (x4) - 42, // DRAM 21 (x4) - 40, // DRAM 20 (x4) - 38, // DRAM 19 (x4) - 36, // DRAM 18 (x4) - 34, // DRAM 17 (x4) - 32, // DRAM 16 (x4) - 30, // DRAM 15 (x4) - 28, // DRAM 14 (x4) - 26, // DRAM 13 (x4) - 24, // DRAM 12 (x4) - 22, // DRAM 11 (x4) - 20, // DRAM 10 (x4) - 18, // DRAM 9 (x4) - 16, // DRAM 8 (x4) - 14, // DRAM 7 (x4) - 12, // DRAM 6 (x4) - 10, // DRAM 5 (x4) - 8, // DRAM 4 (x4) - 6, // DRAM 3 (x4) - 4, // DRAM 2 (x4) - 2}; // DRAM 1 (x4) -// NOTE: DRAM 0 (x4) (symbols 0,1) used for the ECC spare. -// NOTE: Can't use ECC spare to fix bad spare DRAMs on Port0 or Port1 - - -static const uint32_t mss_maintBufferData[2][MSS_MAX_PATTERNS][16][2]={ - -/* ----Pattern 00 -Pattern sent to encoder (x8 mode): - port0,2 port1,3 -t0 0000000000000000 0000000000000000 -t1 0000000000000000 0000000000000000 -t2 0000000000000000 0000000000000000 -t3 0000000000000000 0000000000000000 MDI= (0,0), tag(0,1,2,3) = (0,0,0,0) -t4 0000000000000000 0000000000000000 -t5 0000000000000000 0000000000000000 -t6 0000000000000000 0000000000000000 -t7 0000000000000000 0000000000000000 MDI= (0,0), tag(0,1,2,3) = (0,0,0,0) -*/ - -// PATTERN_0 - // port0,2 - {{{0x00000000, 0x00000000}, // DW0 - {0x00000000, 0x00000000}, // DW2 - {0x00000000, 0x00000000}, // DW4 - {0x00000000, 0x00000000}, // DW6 - {0x00000000, 0x00000000}, // DW8 - {0x00000000, 0x00000000}, // DW10 - {0x00000000, 0x00000000}, // DW12 - {0x00000000, 0x00000000}, // DW14 - // port1,3 - {0x00000000, 0x00000000}, // DW1 - {0x00000000, 0x00000000}, // DW3 - {0x00000000, 0x00000000}, // DW5 - {0x00000000, 0x00000000}, // DW7 - {0x00000000, 0x00000000}, // DW9 - {0x00000000, 0x00000000}, // DW11 - {0x00000000, 0x00000000}, // DW13 - {0x00000000, 0x00000000}},// DW15 - - -/* ----Pattern 1 -Pattern sent to encoder (x8 mode): - port0,2 port1,3 -t0 ffffffffffffffff ffffffffffffffff -t1 ffffffffffffffff ffffffffffffffff -t2 ffffffffffffffff ffffffffffffffff -t3 ffffffffffffffff ffffffffffffffff MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) -t4 ffffffffffffffff ffffffffffffffff -t5 ffffffffffffffff ffffffffffffffff -t6 ffffffffffffffff ffffffffffffffff -t7 ffffffffffffffff ffffffffffffffff MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) -*/ - -// PATTERN_1 - // port0,2 - {{0xffffffff, 0xffffffff}, // DW0 - {0xffffffff, 0xffffffff}, // DW2 - {0xffffffff, 0xffffffff}, // DW4 - {0xffffffff, 0xffffffff}, // DW6 - {0xffffffff, 0xffffffff}, // DW8 - {0xffffffff, 0xffffffff}, // DW10 - {0xffffffff, 0xffffffff}, // DW12 - {0xffffffff, 0xffffffff}, // DW14 - // port1,3 - {0xffffffff, 0xffffffff}, // DW1 - {0xffffffff, 0xffffffff}, // DW3 - {0xffffffff, 0xffffffff}, // DW5 - {0xffffffff, 0xffffffff}, // DW7 - {0xffffffff, 0xffffffff}, // DW9 - {0xffffffff, 0xffffffff}, // DW11 - {0xffffffff, 0xffffffff}, // DW13 - {0xffffffff, 0xffffffff}},// DW15 - - -/*---Pattern 2 -Pattern sent to encoder (x8 mode): - port0,2 port1,3 -t0 6789555555555555 5555555555555555 -t1 6f2eaaaaaaaaaaaa aaaaaaaaaaaaaaaa -t2 ae79555555555555 5555555555555555 -t3 84edaaaaaaaaaaaa aaaaaaaaaaaaaaaa MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) -t4 545eaaaaaaaaaaaa aaaaaaaaaaaaaaaa -t5 a791555555555555 5555555555555555 -t6 6622aaaaaaaaaaaa aaaaaaaaaaaaaaaa -t7 f7f8555555555555 5555555555555555 MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) -*/ - -// PATTERN_2 - // port0,2 - {{0x67895555, 0x55555555}, // DW0 - {0x6f2eaaaa, 0xaaaaaaaa}, // DW2 - {0xae795555, 0x55555555}, // DW4 - {0x84edaaaa, 0xaaaaaaaa}, // DW6 - {0x545eaaaa, 0xaaaaaaaa}, // DW8 - {0xa7915555, 0x55555555}, // DW10 - {0x6622aaaa, 0xaaaaaaaa}, // DW12 - {0xf7f85555, 0x55555555}, // DW14 - // port1,3 - {0x55555555, 0x55555555}, // DW1 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW3 - {0x55555555, 0x55555555}, // DW5 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW7 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW9 - {0x55555555, 0x55555555}, // DW11 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW13 - {0x55555555, 0x55555555}},// DW15 - -/* ----Pattern 3 -Pattern sent to encoder (x8 mode): - port0,2 port1,3 -t0 aaaaaac47aaaaaaa aaaaaaaaaaaaaaaa -t1 555555abf1555555 5555555555555555 -t2 aaaaaa01aeaaaaaa aaaaaaaaaaaaaaaa -t3 5555550c81555555 5555555555555555 MDI= (0,0), tag(0,1,2,3) = (1,1,1,1) -t4 5555557a7f555555 5555555555555555 -t5 aaaaaaccafaaaaaa aaaaaaaaaaaaaaaa -t6 555555456d555555 5555555555555555 -t7 aaaaaa21deaaaaaa aaaaaaaaaaaaaaaa MDI= (1,1), tag(0,1,2,3) = (0,0,0,0) -*/ - -// PATTERN_3 - // port0,2 - {{0xaaaaaac4, 0x7aaaaaaa}, // DW0 - {0x555555ab, 0xf1555555}, // DW2 - {0xaaaaaa01, 0xaeaaaaaa}, // DW4 - {0x5555550c, 0x81555555}, // DW6 - {0x5555557a, 0x7f555555}, // DW8 - {0xaaaaaacc, 0xafaaaaaa}, // DW10 - {0x55555545, 0x6d555555}, // DW12 - {0xaaaaaa21, 0xdeaaaaaa}, // DW14 - // port1,3 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW1 - {0x55555555, 0x55555555}, // DW3 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW5 - {0x55555555, 0x55555555}, // DW7 - {0x55555555, 0x55555555}, // DW9 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW11 - {0x55555555, 0x55555555}, // DW13 - {0xaaaaaaaa, 0xaaaaaaaa}},// DW15 - -/* ----Pattern 4 -Pattern sent to encoder (x8 mode): - port0,2 port1,3 -t0 ffffffffffff8403 ffffffffffffffff -t1 ffffffffffff83d3 ffffffffffffffff -t2 ffffffffffffbf89 ffffffffffffffff -t3 ffffffffffff1133 ffffffffffffffff MDI= (0,0), tag(0,1,2,3) = (0,0,0,0) -t4 000000000000006c 0000000000000000 -t5 000000000000468a 0000000000000000 -t6 000000000000cf7e 0000000000000000 -t7 ffffffffffff6d37 ffffffffffffffff MDI= (1,0), tag(0,1,2,3) = (1,1,1,0) -*/ - -// PATTERN_4 - // port0,2 - {{0xffffffff, 0xffff8403}, // DW0 - {0xffffffff, 0xffff83d3}, // DW2 - {0xffffffff, 0xffffbf89}, // DW4 - {0xffffffff, 0xffff1133}, // DW6 - {0x00000000, 0x0000006c}, // DW8 - {0x00000000, 0x0000468a}, // DW10 - {0x00000000, 0x0000cf7e}, // DW12 - {0xffffffff, 0xffff6d37}, // DW14 - // port1,3 - {0xffffffff, 0xffffffff}, // DW1 - {0xffffffff, 0xffffffff}, // DW3 - {0xffffffff, 0xffffffff}, // DW5 - {0xffffffff, 0xffffffff}, // DW7 - {0x00000000, 0x00000000}, // DW9 - {0x00000000, 0x00000000}, // DW11 - {0x00000000, 0x00000000}, // DW13 - {0xffffffff, 0xffffffff}},// DW15 - -/* ----Pattern 5 -Pattern sent to encoder (x8 mode): - port0,2 port1,3 -t0 0000000000000000 0000000006c00000 -t1 0000000000000000 0000000068f40000 -t2 0000000000000000 00000000701c0000 -t3 0000000000000000 00000000f7640000 MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) -t4 ffffffffffffffff ffffffffe523ffff -t5 ffffffffffffffff ffffffff5603ffff -t6 ffffffffffffffff fffffffffeb5ffff -t7 0000000000000000 0000000098a40000 MDI= (0,1), tag(0,1,2,3) = (0,0,0,1) -*/ - -// PATTERN_5 - // port0,2 - {{0x00000000, 0x00000000}, // DW0 - {0x00000000, 0x00000000}, // DW2 - {0x00000000, 0x00000000}, // DW4 - {0x00000000, 0x00000000}, // DW6 - {0xffffffff, 0xffffffff}, // DW8 - {0xffffffff, 0xffffffff}, // DW10 - {0xffffffff, 0xffffffff}, // DW12 - {0x00000000, 0x00000000}, // DW14 - // port1,3 - {0x00000000, 0x06c00000}, // DW1 - {0x00000000, 0x68f40000}, // DW3 - {0x00000000, 0x701c0000}, // DW5 - {0x00000000, 0xf7640000}, // DW7 - {0xffffffff, 0xe523ffff}, // DW9 - {0xffffffff, 0x5603ffff}, // DW11 - {0xffffffff, 0xfeb5ffff}, // DW13 - {0x00000000, 0x98a40000}},// DW15 - -/* ----Pattern 6 -Pattern sent to encoder (x8 mode): - port0,2 port1,3 -t0 ffffffffffffffff ffffffffceb3ffff -t1 0000000000000000 0000000034460000 -t2 ffffffffffffffff ffffffffb1afffff -t3 0000000000000000 00000000fd080000 MDI= (1,1), tag(0,1,2,3) = (0,1,0,1) -t4 0000000000000000 0000000037540000 -t5 ffffffffffffffff ffffffff3443ffff -t6 0000000000000000 000000001a260000 -t7 ffffffffffffffff ffffffff3f3fffff MDI= (0,0), tag(0,1,2,3) = (1,0,1,0) -*/ - -// PATTERN_6 - // port0,2 - {{0xffffffff, 0xffffffff}, // DW0 - {0x00000000, 0x00000000}, // DW2 - {0xffffffff, 0xffffffff}, // DW4 - {0x00000000, 0x00000000}, // DW6 - {0x00000000, 0x00000000}, // DW8 - {0xffffffff, 0xffffffff}, // DW10 - {0x00000000, 0x00000000}, // DW12 - {0xffffffff, 0xffffffff}, // DW14 - // port1,3 - {0xffffffff, 0xceb3ffff}, // DW1 - {0x00000000, 0x34460000}, // DW3 - {0xffffffff, 0xb1afffff}, // DW5 - {0x00000000, 0xfd080000}, // DW7 - {0x00000000, 0x37540000}, // DW9 - {0xffffffff, 0x3443ffff}, // DW11 - {0x00000000, 0x1a260000}, // DW13 - {0xffffffff, 0x3f3fffff}},// DW15 - -/* ----Pattern 7 -Pattern sent to encoder (x8 mode): - port0,2 port1,3 -t0 83dc000000000000 0000000000000000 -t1 d4b7ffffffffffff ffffffffffffffff -t2 8c2c000000000000 0000000000000000 -t3 5d8affffffffffff ffffffffffffffff MDI= (0,0), tag(0,1,2,3) = (1,0,1,0) -t4 ec57ffffffffffff ffffffffffffffff -t5 a9d4000000000000 0000000000000000 -t6 8447ffffffffffff ffffffffffffffff -t7 eafe000000000000 0000000000000000 MDI= (1,1), tag(0,1,2,3) = (0,1,0,1) -*/ - -// PATTERN_7 - // port0,2 - {{0x83dc0000, 0x00000000}, // DW0 - {0xd4b7ffff, 0xffffffff}, // DW2 - {0x8c2c0000, 0x00000000}, // DW4 - {0x5d8affff, 0xffffffff}, // DW6 - {0xec57ffff, 0xffffffff}, // DW8 - {0xa9d40000, 0x00000000}, // DW10 - {0x8447ffff, 0xffffffff}, // DW12 - {0xeafe0000, 0x00000000}, // DW14 - // port1,3 - {0x00000000, 0x00000000}, // DW1 - {0xffffffff, 0xffffffff}, // DW3 - {0x00000000, 0x00000000}, // DW5 - {0xffffffff, 0xffffffff}, // DW7 - {0xffffffff, 0xffffffff}, // DW9 - {0x00000000, 0x00000000}, // DW11 - {0xffffffff, 0xffffffff}, // DW13 - {0x00000000, 0x00000000}},// DW15 - -// PATTERN_8: random seed - {{0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}}}, - - -/* ----Pattern 00 -Pattern sent to encoder (x4 mode): - port0,2 port1,3 -t0 0000000000000000 0000000000000000 -t1 0000000000000000 0000000000000000 -t2 0000000000000000 0000000000000000 -t3 0000000000000000 0000000000000000 MDI= (0,0), tag(0,1,2,3) = (0,0,0,0) -t4 0000000000000000 0000000000000000 -t5 0000000000000000 0000000000000000 -t6 0000000000000000 0000000000000000 -t7 0000000000000000 0000000000000000 MDI= (0,0), tag(0,1,2,3) = (0,0,0,0) -*/ - -// PATTERN_0 - // port0,2 - {{{0x00000000, 0x00000000}, // DW0 - {0x00000000, 0x00000000}, // DW2 - {0x00000000, 0x00000000}, // DW4 - {0x00000000, 0x00000000}, // DW6 - {0x00000000, 0x00000000}, // DW8 - {0x00000000, 0x00000000}, // DW10 - {0x00000000, 0x00000000}, // DW12 - {0x00000000, 0x00000000}, // DW14 - // port1,3 - {0x00000000, 0x00000000}, // DW1 - {0x00000000, 0x00000000}, // DW3 - {0x00000000, 0x00000000}, // DW5 - {0x00000000, 0x00000000}, // DW7 - {0x00000000, 0x00000000}, // DW9 - {0x00000000, 0x00000000}, // DW11 - {0x00000000, 0x00000000}, // DW13 - {0x00000000, 0x00000000}},// DW15 - - -/* ----Pattern 1 -Pattern sent to encoder (x4 mode): - port0,2 port1,3 -t0 ffffffffffffffff ffffffffffffffff -t1 ffffffffffffffff ffffffffffffffff -t2 ffffffffffffffff ffffffffffffffff -t3 ffffffffffffffff ffffffffffffffff MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) -t4 ffffffffffffffff ffffffffffffffff -t5 ffffffffffffffff ffffffffffffffff -t6 ffffffffffffffff ffffffffffffffff -t7 ffffffffffffffff ffffffffffffffff MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) -*/ - -// PATTERN_1 - // port0,2 - {{0xffffffff, 0xffffffff}, // DW0 - {0xffffffff, 0xffffffff}, // DW2 - {0xffffffff, 0xffffffff}, // DW4 - {0xffffffff, 0xffffffff}, // DW6 - {0xffffffff, 0xffffffff}, // DW8 - {0xffffffff, 0xffffffff}, // DW10 - {0xffffffff, 0xffffffff}, // DW12 - {0xffffffff, 0xffffffff}, // DW14 - // port1,3 - {0xffffffff, 0xffffffff}, // DW1 - {0xffffffff, 0xffffffff}, // DW3 - {0xffffffff, 0xffffffff}, // DW5 - {0xffffffff, 0xffffffff}, // DW7 - {0xffffffff, 0xffffffff}, // DW9 - {0xffffffff, 0xffffffff}, // DW11 - {0xffffffff, 0xffffffff}, // DW13 - {0xffffffff, 0xffffffff}},// DW15 - - -/*---Pattern 2 -Pattern sent to encoder (x4 mode): - port0,2 port1,3 -t0 5055555555555555 5555555555555555 -t1 a96aaaaaaaaaaaaa aaaaaaaaaaaaaaaa -t2 6215555555555555 5555555555555555 -t3 dd5aaaaaaaaaaaaa aaaaaaaaaaaaaaaa MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) -t4 89eaaaaaaaaaaaaa aaaaaaaaaaaaaaaa -t5 7fd5555555555555 5555555555555555 -t6 b32aaaaaaaaaaaaa aaaaaaaaaaaaaaaa -t7 acc5555555555555 5555555555555555 MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) -*/ - -// PATTERN_2 - // port0,2 - {{0x50555555, 0x55555555}, // DW0 - {0xa96aaaaa, 0xaaaaaaaa}, // DW2 - {0x62155555, 0x55555555}, // DW4 - {0xdd5aaaaa, 0xaaaaaaaa}, // DW6 - {0x89eaaaaa, 0xaaaaaaaa}, // DW8 - {0x7fd55555, 0x55555555}, // DW10 - {0xb32aaaaa, 0xaaaaaaaa}, // DW12 - {0xacc55555, 0x55555555}, // DW14 - // port1,3 - {0x55555555, 0x55555555}, // DW1 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW3 - {0x55555555, 0x55555555}, // DW5 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW7 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW9 - {0x55555555, 0x55555555}, // DW11 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW13 - {0x55555555, 0x55555555}},// DW15 - -/* ----Pattern 3 -Pattern sent to encoder (x4 mode): - port0,2 port1,3 -t0 aaaaaab7caaaaaaa aaaaaaaaaaaaaaaa -t1 555555f2d5555555 5555555555555555 -t2 aaaaaad8aaaaaaaa aaaaaaaaaaaaaaaa -t3 5555552495555555 5555555555555555 MDI= (0,0), tag(0,1,2,3) = (1,1,1,1) -t4 55555540b5555555 5555555555555555 -t5 aaaaaa04baaaaaaa aaaaaaaaaaaaaaaa -t6 555555c095555555 5555555555555555 -t7 aaaaaa956aaaaaaa aaaaaaaaaaaaaaaa MDI= (1,1), tag(0,1,2,3) = (0,0,0,0) -*/ - -// PATTERN_3 - // port0,2 - {{0xaaaaaab7, 0xcaaaaaaa}, // DW0 - {0x555555f2, 0xd5555555}, // DW2 - {0xaaaaaad8, 0xaaaaaaaa}, // DW4 - {0x55555524, 0x95555555}, // DW6 - {0x55555540, 0xb5555555}, // DW8 - {0xaaaaaa04, 0xbaaaaaaa}, // DW10 - {0x555555c0, 0x95555555}, // DW12 - {0xaaaaaa95, 0x6aaaaaaa}, // DW14 - // port1,3 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW1 - {0x55555555, 0x55555555}, // DW3 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW5 - {0x55555555, 0x55555555}, // DW7 - {0x55555555, 0x55555555}, // DW9 - {0xaaaaaaaa, 0xaaaaaaaa}, // DW11 - {0x55555555, 0x55555555}, // DW13 - {0xaaaaaaaa, 0xaaaaaaaa}},// DW15 - -/* ----Pattern 4 -Pattern sent to encoder (x4 mode): - port0,2 port1,3 -t0 ffffffffffff93ff ffffffffffffffff -t1 ffffffffffffb5bf ffffffffffffffff -t2 ffffffffffff207f ffffffffffffffff -t3 ffffffffffffb37f ffffffffffffffff MDI= (0,0), tag(0,1,2,3) = (0,0,0,0) -t4 0000000000002340 0000000000000000 -t5 00000000000062e0 0000000000000000 -t6 0000000000006740 0000000000000000 -t7 ffffffffffff6a3f ffffffffffffffff MDI= (1,0), tag(0,1,2,3) = (1,1,1,0) -*/ - -// PATTERN_4 - // port0,2 - {{0xffffffff, 0xffff93ff}, // DW0 - {0xffffffff, 0xffffb5bf}, // DW2 - {0xffffffff, 0xffff207f}, // DW4 - {0xffffffff, 0xffffb37f}, // DW6 - {0x00000000, 0x00002340}, // DW8 - {0x00000000, 0x000062e0}, // DW10 - {0x00000000, 0x00006740}, // DW12 - {0xffffffff, 0xffff6a3f}, // DW14 - // port1,3 - {0xffffffff, 0xffffffff}, // DW1 - {0xffffffff, 0xffffffff}, // DW3 - {0xffffffff, 0xffffffff}, // DW5 - {0xffffffff, 0xffffffff}, // DW7 - {0x00000000, 0x00000000}, // DW9 - {0x00000000, 0x00000000}, // DW11 - {0x00000000, 0x00000000}, // DW13 - {0xffffffff, 0xffffffff}},// DW15 - -/* ----Pattern 5 -Pattern sent to encoder (x4 mode): - port0,2 port1,3 -t0 0000000000000000 0000000090c00000 -t1 0000000000000000 00000000b0400000 -t2 0000000000000000 0000000087a00000 -t3 0000000000000000 0000000033000000 MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) -t4 ffffffffffffffff ffffffff9dbfffff -t5 ffffffffffffffff ffffffffa69fffff -t6 ffffffffffffffff ffffffff257fffff -t7 0000000000000000 00000000c7400000 MDI= (0,1), tag(0,1,2,3) = (0,0,0,1) -*/ - -// PATTERN_5 - // port0,2 - {{0x00000000, 0x00000000}, // DW0 - {0x00000000, 0x00000000}, // DW2 - {0x00000000, 0x00000000}, // DW4 - {0x00000000, 0x00000000}, // DW6 - {0xffffffff, 0xffffffff}, // DW8 - {0xffffffff, 0xffffffff}, // DW10 - {0xffffffff, 0xffffffff}, // DW12 - {0x00000000, 0x00000000}, // DW14 - // port1,3 - {0x00000000, 0x90c00000}, // DW1 - {0x00000000, 0xb0400000}, // DW3 - {0x00000000, 0x87a00000}, // DW5 - {0x00000000, 0x33000000}, // DW7 - {0xffffffff, 0x9dbfffff}, // DW9 - {0xffffffff, 0xa69fffff}, // DW11 - {0xffffffff, 0x257fffff}, // DW13 - {0x00000000, 0xc7400000}},// DW15 - -/* ----Pattern 6 -Pattern sent to encoder (x4 mode): - port0,2 port1,3 -t0 ffffffffffffffff ffffffff7e3fffff -t1 0000000000000000 0000000018c00000 -t2 ffffffffffffffff ffffffffc8bfffff -t3 0000000000000000 000000006b800000 MDI= (1,1), tag(0,1,2,3) = (0,1,0,1) -t4 0000000000000000 00000000f2800000 -t5 ffffffffffffffff ffffffff659fffff -t6 0000000000000000 00000000c5c00000 -t7 ffffffffffffffff ffffffff473fffff MDI= (0,0), tag(0,1,2,3) = (1,0,1,0) -*/ - -// PATTERN_6 - // port0,2 - {{0xffffffff, 0xffffffff}, // DW0 - {0x00000000, 0x00000000}, // DW2 - {0xffffffff, 0xffffffff}, // DW4 - {0x00000000, 0x00000000}, // DW6 - {0x00000000, 0x00000000}, // DW8 - {0xffffffff, 0xffffffff}, // DW10 - {0x00000000, 0x00000000}, // DW12 - {0xffffffff, 0xffffffff}, // DW14 - // port1,3 - {0xffffffff, 0x7e3fffff}, // DW1 - {0x00000000, 0x18c00000}, // DW3 - {0xffffffff, 0xc8bfffff}, // DW5 - {0x00000000, 0x6b800000}, // DW7 - {0x00000000, 0xf2800000}, // DW9 - {0xffffffff, 0x659fffff}, // DW11 - {0x00000000, 0xc5c00000}, // DW13 - {0xffffffff, 0x473fffff}},// DW15 - -/* ----Pattern 7 -Pattern sent to encoder (x4 mode): - port0,2 port1,3 -t0 8200000000000000 0000000000000000 -t1 d3bfffffffffffff ffffffffffffffff -t2 d080000000000000 0000000000000000 -t3 539fffffffffffff ffffffffffffffff MDI= (0,0), tag(0,1,2,3) = (1,0,1,0) -t4 63ffffffffffffff ffffffffffffffff -t5 d640000000000000 0000000000000000 -t6 5c3fffffffffffff ffffffffffffffff -t7 dcb0000000000000 0000000000000000 MDI= (1,1), tag(0,1,2,3) = (0,1,0,1) -*/ - -// PATTERN_7 - // port0,2 - {{0x82000000, 0x00000000}, // DW0 - {0xd3bfffff, 0xffffffff}, // DW2 - {0xd0800000, 0x00000000}, // DW4 - {0x539fffff, 0xffffffff}, // DW6 - {0x63ffffff, 0xffffffff}, // DW8 - {0xd6400000, 0x00000000}, // DW10 - {0x5c3fffff, 0xffffffff}, // DW12 - {0xdcb00000, 0x00000000}, // DW14 - // port1,3 - {0x00000000, 0x00000000}, // DW1 - {0xffffffff, 0xffffffff}, // DW3 - {0x00000000, 0x00000000}, // DW5 - {0xffffffff, 0xffffffff}, // DW7 - {0xffffffff, 0xffffffff}, // DW9 - {0x00000000, 0x00000000}, // DW11 - {0xffffffff, 0xffffffff}, // DW13 - {0x00000000, 0x00000000}},// DW15 - -// PATTERN_8: random seed - {{0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}, - {0x12345678, 0x87654321}, - {0x87654321, 0x12345678}}}}; - - - - - -static const uint8_t mss_65thByte[2][MSS_MAX_PATTERNS][4]={ - - -// bit1=tag0_2, bit2=tag1_3, bit3=MDI - -// PATTERN_0 (x8 mode) - - // MDI= (0,0), tag(0,1,2,3) = (0,0,0,0) - {{0x00, // 1st 64B of cachline: tag0=0, tag1=0, MDI=0 - 0x00, // 1st 64B of cachline: tag2=0, tag3=0, MDI=0 - // MDI= (0,0), tag(0,1,2,3) = (0,0,0,0) - 0x00, // 2nd 64B of cachline: tag0=0, tag1=0, MDI=0 - 0x00}, // 2nd 64B of cachline: tag2=0, tag3=0, MDI=0 - -// PATTERN_1 (x8 mode) - - // MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) - {0xF0, // 1st 64B of cachline: tag0=1, tag1=1, MDI=1 - 0x70, // 1st 64B of cachline: tag2=1, tag3=1, MDI=1 - // MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) - 0x70, // 2nd 64B of cachline: tag0=1, tag1=1, MDI=1 - 0xF0}, // 2nd 64B of cachline: tag2=1, tag3=1, MDI=1 - -// PATTERN_2 (x8 mode) - - // MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) - {0xF0, // 1st 64B of cachline: tag0=1, tag1=1, MDI=1 - 0xF0, // 1st 64B of cachline: tag2=1, tag3=1, MDI=1 - // MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) - 0xF0, // 2nd 64B of cachline: tag0=1, tag1=1, MDI=1 - 0xF0}, // 2nd 64B of cachline: tag2=1, tag3=1, MDI=1 - -// PATTERN_3 (x8 mode) - // MDI= (0,0), tag(0,1,2,3) = (1,1,1,1) - {0x60, // 1st 64B of cachline: tag0=1, tag1=1, MDI=0 - 0x60, // 1st 64B of cachline: tag2=1, tag3=1, MDI=0 - // MDI= (1,1), tag(0,1,2,3) = (0,0,0,0) - 0x90, // 2nd 64B of cachline: tag0=0, tag1=0, MDI=1 - 0x90}, // 2nd 64B of cachline: tag2=0, tag3=0, MDI=1 - -// PATTERN_4 (x8 mode) - // MDI= (0,0), tag(0,1,2,3) = (0,0,0,0) - {0x00, // 1st 64B of cachline: tag0=0, tag1=0, MDI=0 - 0x00, // 1st 64B of cachline: tag2=0, tag3=0, MDI=0 - // MDI= (1,0), tag(0,1,2,3) = (1,1,1,0) - 0xF0, // 2nd 64B of cachline: tag0=1, tag1=1, MDI=1 - 0xC0}, // 2nd 64B of cachline: tag2=1, tag3=0, MDI=0 - -// PATTERN_5 (x8 mode) - // MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) - {0xF0, // 1st 64B of cachline: tag0=1, tag1=1, MDI=1 - 0xF0, // 1st 64B of cachline: tag2=1, tag3=1, MDI=1 - // MDI= (0,1), tag(0,1,2,3) = (0,0,0,1) - 0x00, // 2nd 64B of cachline: tag0=0, tag1=0, MDI=0 - 0x10}, // 2nd 64B of cachline: tag2=0, tag3=1, MDI=1 - -// PATTERN_6 (x8 mode) - // MDI= (1,1), tag(0,1,2,3) = (0,1,0,1) - {0x30, // 1st 64B of cachline: tag0=0, tag1=1, MDI=1 - 0x30, // 1st 64B of cachline: tag2=0, tag3=1, MDI=1 - // MDI= (0,0), tag(0,1,2,3) = (1,0,1,0) - 0xC0, // 2nd 64B of cachline: tag0=1, tag1=0, MDI=0 - 0xC0}, // 2nd 64B of cachline: tag2=1, tag3=0, MDI=0 - -// PATTERN_7 (x8 mode) - // MDI= (0,0), tag(0,1,2,3) = (1,0,1,0) - {0xC0, // 1st 64B of cachline: tag0=1, tag1=0, MDI=0 - 0xC0, // 1st 64B of cachline: tag2=1, tag3=0, MDI=0 - // MDI= (1,1), tag(0,1,2,3) = (0,1,0,1) - 0x30, // 2nd 64B of cachline: tag0=0, tag1=1, MDI=1 - 0x30}, // 2nd 64B of cachline: tag2=0, tag3=1, MDI=1 - -// PATTERN_8: random seed (x8 mode) - {0x20, // 1st 64B of cachline: tag0=0, tag1=1, MDI=0 - 0x60, // 1st 64B of cachline: tag2=1, tag3=1, MDI=0 - 0x30, // 2nd 64B of cachline: tag0=0, tag1=1, MDI=1 - 0x70}}, // 2nd 64B of cachline: tag2=1, tag3=1, MDI=1 - - - - -// bit1=tag0_2, bit2=tag1_3, bit3=MDI - -// PATTERN_0 (x4 mode) - - // MDI= (0,0), tag(0,1,2,3) = (0,0,0,0) - {{0x00, // 1st 64B of cachline: tag0=0, tag1=0, MDI=0 - 0x00, // 1st 64B of cachline: tag2=0, tag3=0, MDI=0 - // MDI= (0,0), tag(0,1,2,3) = (0,0,0,0) - 0x00, // 2nd 64B of cachline: tag0=0, tag1=0, MDI=0 - 0x00}, // 2nd 64B of cachline: tag2=0, tag3=0, MDI=0 - -// PATTERN_1 (x4 mode) - - // MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) - {0xF0, // 1st 64B of cachline: tag0=1, tag1=1, MDI=1 - 0xF0, // 1st 64B of cachline: tag2=1, tag3=1, MDI=1 - // MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) - 0xF0, // 2nd 64B of cachline: tag0=1, tag1=1, MDI=1 - 0xF0}, // 2nd 64B of cachline: tag2=1, tag3=1, MDI=1 - -// PATTERN_2 (x4 mode) - - // MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) - {0xF0, // 1st 64B of cachline: tag0=1, tag1=1, MDI=1 - 0xF0, // 1st 64B of cachline: tag2=1, tag3=1, MDI=1 - // MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) - 0xF0, // 2nd 64B of cachline: tag0=1, tag1=1, MDI=1 - 0xF0}, // 2nd 64B of cachline: tag2=1, tag3=1, MDI=1 - -// PATTERN_3 (x4 mode) - // MDI= (0,0), tag(0,1,2,3) = (1,1,1,1) - {0x60, // 1st 64B of cachline: tag0=1, tag1=1, MDI=0 - 0x60, // 1st 64B of cachline: tag2=1, tag3=1, MDI=0 - // MDI= (1,1), tag(0,1,2,3) = (0,0,0,0) - 0x90, // 2nd 64B of cachline: tag0=0, tag1=0, MDI=1 - 0x90}, // 2nd 64B of cachline: tag2=0, tag3=0, MDI=1 - -// PATTERN_4 (x4 mode) - // MDI= (0,0), tag(0,1,2,3) = (0,0,0,0) - {0x00, // 1st 64B of cachline: tag0=0, tag1=0, MDI=0 - 0x00, // 1st 64B of cachline: tag2=0, tag3=0, MDI=0 - // MDI= (1,0), tag(0,1,2,3) = (1,1,1,0) - 0xF0, // 2nd 64B of cachline: tag0=1, tag1=1, MDI=1 - 0xC0}, // 2nd 64B of cachline: tag2=1, tag3=0, MDI=0 - -// PATTERN_5 (x4 mode) - // MDI= (1,1), tag(0,1,2,3) = (1,1,1,1) - {0xF0, // 1st 64B of cachline: tag0=1, tag1=1, MDI=1 - 0xF0, // 1st 64B of cachline: tag2=1, tag3=1, MDI=1 - // MDI= (0,1), tag(0,1,2,3) = (0,0,0,1) - 0x80, // 2nd 64B of cachline: tag0=0, tag1=0, MDI=0 - 0x10}, // 2nd 64B of cachline: tag2=0, tag3=1, MDI=1 - -// PATTERN_6 (x4 mode) - // MDI= (1,1), tag(0,1,2,3) = (0,1,0,1) - {0x30, // 1st 64B of cachline: tag0=0, tag1=1, MDI=1 - 0x30, // 1st 64B of cachline: tag2=0, tag3=1, MDI=1 - // MDI= (0,0), tag(0,1,2,3) = (1,0,1,0) - 0xC0, // 2nd 64B of cachline: tag0=1, tag1=0, MDI=0 - 0xC0}, // 2nd 64B of cachline: tag2=1, tag3=0, MDI=0 - -// PATTERN_7 (x4 mode) - // MDI= (0,0), tag(0,1,2,3) = (1,0,1,0) - {0xC0, // 1st 64B of cachline: tag0=1, tag1=0, MDI=0 - 0xC0, // 1st 64B of cachline: tag2=1, tag3=0, MDI=0 - // MDI= (1,1), tag(0,1,2,3) = (0,1,0,1) - 0x30, // 2nd 64B of cachline: tag0=0, tag1=1, MDI=1 - 0x30}, // 2nd 64B of cachline: tag2=0, tag3=1, MDI=1 - -// PATTERN_8: random seed (x8 mode) - {0x20, // 1st 64B of cachline: tag0=0, tag1=1, MDI=0 - 0x60, // 1st 64B of cachline: tag2=1, tag3=1, MDI=0 - 0x30, // 2nd 64B of cachline: tag0=0, tag1=1, MDI=1 - 0x70}}};// 2nd 64B of cachline: tag2=1, tag3=1, MDI=1 - - - -static const uint32_t mss_ECC[2][MSS_MAX_PATTERNS][4]={ - -// bit 4:15 ECC_c6_c5_c4, bit 16:31 ECC_c3_c2_c1_c0 - -// PATTERN_0 (x8 mode) - {{0x00000000, // 1st 64B of cachline - 0x00000000, // 1st 64B of cachline - 0x00000000, // 2nd 64B of cachline - 0x00000000}, // 2nd 64B of cachline - -// PATTERN_1 (x8 mode) - {0x0DA49500, // 1st 64B of cachline - 0x0234A60E, // 1st 64B of cachline - 0x0DA49500, // 2nd 64B of cachline - 0x0234A60E}, // 2nd 64B of cachline - -// PATTERN_2 (x8 mode) - {0x0FFFFFFF, // 1st 64B of cachline - 0x0FFFFFFF, // 1st 64B of cachline - 0x0FFFFFFF, // 2nd 64B of cachline - 0x0FFFFFFF}, // 2nd 64B of cachline - -// PATTERN_3 (x8 mode) - {0x056A55AA, // 1st 64B of cachline - 0x056A55AA, // 1st 64B of cachline - 0x0A95AA55, // 2nd 64B of cachline - 0x0A95AA55}, // 2nd 64B of cachline - -// PATTERN_4 (x8 mode) - {0x00000000, // 1st 64B of cachline - 0x00000000, // 1st 64B of cachline - 0x0FFFFFFF, // 2nd 64B of cachline - 0x0FC0FF00}, // 2nd 64B of cachline - -// PATTERN_5 (x8 mode) - {0x0FFFFFFF, // 1st 64B of cachline - 0x0FFFFFFF, // 1st 64B of cachline - 0x0ED81C6A, // 2nd 64B of cachline - 0x0D970552}, // 2nd 64B of cachline - -// PATTERN_6 (x8 mode) - {0x003F00FF, // 1st 64B of cachline - 0x003F00FF, // 1st 64B of cachline - 0x0FC0FF00, // 2nd 64B of cachline - 0x0FC0FF00}, // 2nd 64B of cachline - -// PATTERN_7 (x8 mode) - {0x0FC0FF00, // 1st 64B of cachline - 0x0FC0FF00, // 1st 64B of cachline - 0x003F00FF, // 2nd 64B of cachline - 0x003F00FF}, // 2nd 64B of cachline - -// PATTERN_8: random - {0x00000000, // 1st 64B of cachline - 0x00000000, // 1st 64B of cachline - 0x00000000, // 2nd 64B of cachline - 0x00000000}}, // 2nd 64B of cachline - -// bit 4:15 ECC_c6_c5_c4, bit 16:31 ECC_c3_c2_c1_c0 - -// PATTERN_0 (x4 mode) - {{0x00000000, // 1st 64B of cachline - 0x00000000, // 1st 64B of cachline - 0x00000000, // 2nd 64B of cachline - 0x00000000}, // 2nd 64B of cachline - -// PATTERN_1 (x4 mode) - {0x09978000, // 1st 64B of cachline - 0x03DBC0C0, // 1st 64B of cachline - 0x09978000, // 2nd 64B of cachline - 0x03DBC0C0}, // 2nd 64B of cachline - -// PATTERN_2 (x4 mode) - {0x0FFFF0F0, // 1st 64B of cachline - 0x0FFFF0F0, // 1st 64B of cachline - 0x0FFFF0F0, // 2nd 64B of cachline - 0x0FFFF0F0}, // 2nd 64B of cachline - -// PATTERN_3 (x4 mode) - {0x056A50A0, // 1st 64B of cachline - 0x056A50A0, // 1st 64B of cachline - 0x0A95A050, // 2nd 64B of cachline - 0x0A95A050}, // 2nd 64B of cachline - -// PATTERN_4 (x4 mode) - {0x00000000, // 1st 64B of cachline - 0x00000000, // 1st 64B of cachline - 0x0FFFF0F0, // 2nd 64B of cachline - 0x0FC0F000}, // 2nd 64B of cachline - -// PATTERN_5 (x4 mode) - {0x0FFFF0F0, // 1st 64B of cachline - 0x0FFFF0F0, // 1st 64B of cachline - 0x07BB8020, // 2nd 64B of cachline - 0x07A4A0D0}, // 2nd 64B of cachline - -// PATTERN_6 (x4 mode) - {0x003F00F0, // 1st 64B of cachline - 0x003F00F0, // 1st 64B of cachline - 0x0FC0F000, // 2nd 64B of cachline - 0x0FC0F000}, // 2nd 64B of cachline - -// PATTERN_7 (x4 mode) - {0x0FC0F000, // 1st 64B of cachline - 0x0FC0F000, // 1st 64B of cachline - 0x003F00F0, // 2nd 64B of cachline - 0x003F00F0}, // 2nd 64B of cachline - -// PATTERN_8: random - {0x00000000, // 1st 64B of cachline - 0x00000000, // 1st 64B of cachline - 0x00000000, // 2nd 64B of cachline - 0x00000000}}};// 2nd 64B of cachline - - - - - -//------------------------------------------------------------------------------ -// Function Prototypes - These are not externally called, so per RAS review, they -// go in here -//------------------------------------------------------------------------------ - void mss_get_dummy_mark_store( const fapi::Target & i_target, - uint8_t i_rank, - uint8_t & o_symbolMark, - uint8_t & o_chipMark, - uint8_t mark_store[8][2]); - - - void mss_put_dummy_mark_store( const fapi::Target & i_target, - uint8_t i_rank, - uint8_t i_symbolMark, - uint8_t i_chipMark, - uint8_t mark_store[8][2]); - - void mss_get_dummy_steer_mux( const fapi::Target & i_target, - uint8_t i_rank, - mss_SteerMux::muxType i_muxType, - uint8_t & o_dramSparePort0Symbol, - uint8_t & o_dramSparePort1Symbol, - uint8_t & o_eccSpareSymbol, - uint8_t steer[8][3]); - - void mss_put_dummy_steer_mux( const fapi::Target & i_target, - uint8_t i_rank, - mss_SteerMux::muxType i_muxType, - uint8_t i_steerType, - uint8_t i_symbol, - uint8_t steer[8][3]); - - void mss_check_dummy_steering(const fapi::Target & i_target, - uint8_t i_rank, - uint8_t & o_dramSparePort0Symbol, - uint8_t & o_dramSparePort1Symbol, - uint8_t & o_eccSpareSymbol, - uint8_t steer[8][3]); - -//------------------------------------------------------------------------------ -// Parent class -//------------------------------------------------------------------------------ - - - -//--------------------------------------------------------- -// mss_MaintCmd Constructor -//--------------------------------------------------------- - mss_MaintCmd::mss_MaintCmd(const fapi::Target & i_target, - const ecmdDataBufferBase & i_startAddr, - const ecmdDataBufferBase & i_endAddr, - uint32_t i_stopCondition, - bool i_poll, - CmdType i_cmdType ) : - iv_target( i_target ), - iv_startAddr( i_startAddr ), - iv_endAddr( i_endAddr ), - iv_stopCondition( i_stopCondition), - iv_poll (i_poll), - iv_cmdType(i_cmdType){} - - -//--------------------------------------------------------- -// mss_stopCmd -//--------------------------------------------------------- -fapi::ReturnCode mss_MaintCmd::stopCmd() -{ - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_mbmsrq(64); - ecmdDataBufferBase l_mbmccq(64); - ecmdDataBufferBase l_mbmacaq(64); - ecmdDataBufferBase l_mbspa_mask(64); - ecmdDataBufferBase l_mbspa_mask_original(64); - ecmdDataBufferBase l_mbspa_and(64); - - - // 1 ms delay for HW mode -- LWM changed 100,000,000 to 1,000,000 to match comment - const uint64_t HW_MODE_DELAY = 1000000; - - // 200000 sim cycle delay for SIM mode - const uint64_t SIM_MODE_DELAY = 200000; - - uint32_t l_count = 0; - - uint32_t l_loop_limit = 10; - - FAPI_INF("ENTER mss_MaintCmd::stopCmd()"); - - // Read MBSPA MASK - l_rc = fapiGetScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask); - if(l_rc) return l_rc; - - // Save original mask value so we can restore it when done - l_ecmd_rc |= l_mbspa_mask_original.insert(l_mbspa_mask, 0, 64, 0); - - // Mask bits 0 and 8, to hide the special attentions when the cmd completes - l_ecmd_rc |= l_mbspa_mask.setBit(0); - l_ecmd_rc |= l_mbspa_mask.setBit(8); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write MBSPA MASK - l_rc = fapiPutScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask); - if(l_rc) return l_rc; - - - // Read MBMSRQ - l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_mbmsrq); - if(l_rc) return l_rc; - - - // If MBMSRQ[0], maint_cmd_in_progress, stop the cmd - if (l_mbmsrq.isBitSet(0)) - { - // Read MBMCCQ - l_rc = fapiGetScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_mbmccq); - if(l_rc) return l_rc; - - // Set bit 1 to force the cmd to stop - l_ecmd_rc |= l_mbmccq.setBit(1); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write MBMCCQ - l_rc = fapiPutScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_mbmccq); - if(l_rc) return l_rc; - - // Loop to check for cmd in progress bit to turn off - do - { - // Wait 1ms - fapiDelay(HW_MODE_DELAY, SIM_MODE_DELAY); - - // Read MBMSRQ - l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_mbmsrq); - if(l_rc) return l_rc; - - l_count++; - } - while (l_mbmsrq.isBitSet(0) && (l_count < l_loop_limit)); - - // If cmd didn't stop as expected - if (l_mbmsrq.isBitSet(0)) - { - FAPI_ERR("MBMSRQ[0] = 1, unsuccessful forced maint cmd stop on %s.",iv_target.toEcmdString()); - - // Calling out MBA target high, deconfig, gard - const fapi::Target & MBA = iv_target; - // FFDC: Capture register we used to stop cmd - ecmdDataBufferBase & MBMCC = l_mbmccq; - // FFDC: Capture register we are checking - ecmdDataBufferBase & MBMSR = l_mbmsrq; - // FFDC: Capture command type we are trying to run - const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; - - // Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_UNSUCCESSFUL_FORCED_MAINT_CMD_STOP); - return l_rc; - } - - // Else cmd is stopped - else - { - // Clear MCMCC bit 1, just in case cmd was already stopped - // before we set it, in which case, bit 1 would not have self cleared. - l_ecmd_rc |= l_mbmccq.clearBit(1); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write MBMCCQ - l_rc = fapiPutScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_mbmccq); - if(l_rc) return l_rc; - } - - - } - - // Store the address we stopped at in iv_startAddr - l_rc = fapiGetScom(iv_target, MBA01_MBMACAQ_0x0301060D, iv_startAddr); - if(l_rc) return l_rc; - - // Only 0-36 are valid address bits so clear the rest, 37-63 - l_ecmd_rc |= iv_startAddr.clearBit(37,27); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - - // Clear bits 0 and 8 in MBSPA AND register - l_ecmd_rc |= l_mbspa_and.flushTo1(); - l_ecmd_rc |= l_mbspa_and.clearBit(0); - l_ecmd_rc |= l_mbspa_and.clearBit(8); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write MPSPA AND register - l_rc = fapiPutScom(iv_target, MBA01_MBSPAQ_AND_0x03010612, l_mbspa_and); - if(l_rc) return l_rc; - - // Restore MBSPA MASK - l_rc = fapiPutScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask_original); - if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_MaintCmd::stopCmd()"); - return l_rc; -} - - -//--------------------------------------------------------- -// mss_cleanupCmd -//--------------------------------------------------------- - fapi::ReturnCode mss_MaintCmd::cleanupCmd() - { - fapi::ReturnCode l_rc; - FAPI_INF("ENTER mss_MaintCmd::cleanupCmd()"); - - - - FAPI_INF("EXIT mss_MaintCmd::cleanupCmd()"); - return l_rc; - } - - -//--------------------------------------------------------- -// mss_preConditionCheck -//--------------------------------------------------------- - fapi::ReturnCode mss_MaintCmd::preConditionCheck() - { - fapi::ReturnCode l_rc; - ecmdDataBufferBase l_mbmccq(64); - ecmdDataBufferBase l_mbmsrq(64); - ecmdDataBufferBase l_mbaxcr(64); - ecmdDataBufferBase l_ccs_modeq(64); - ecmdDataBufferBase l_mbsecc(64); - ecmdDataBufferBase l_mbmct(64); - - FAPI_INF("ENTER mss_MaintCmd::preConditionCheck()"); - -// Get Centaur target for the given MBA - l_rc = fapiGetParentChip(iv_target, iv_targetCentaur); - if(l_rc) - { - FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",iv_target.toEcmdString()); - return l_rc; - } - -// Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &iv_target, iv_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position on %s.",iv_target.toEcmdString()); - return l_rc; - } - -// Read MBMCCQ - l_rc = fapiGetScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_mbmccq); - if(l_rc) return l_rc; - -// Read MBMSRQ - l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_mbmsrq); - if(l_rc) return l_rc; - -// Read MBAXCRn - l_rc = fapiGetScom(iv_targetCentaur, mss_mbaxcr[iv_mbaPosition], l_mbaxcr); - if(l_rc) return l_rc; - -// Read CCS_MODEQ - l_rc = fapiGetScom(iv_target, MEM_MBA01_CCS_MODEQ_0x030106A7, l_ccs_modeq); - if(l_rc) return l_rc; - -// Read MBSECC - l_rc = fapiGetScom(iv_targetCentaur, mss_mbsecc[iv_mbaPosition], l_mbsecc); - if(l_rc) return l_rc; - -// Read MBMCT[0:4], cmd type, for FFDC - l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_mbmct); - if(l_rc) return l_rc; - - -// Check for MBMCCQ[0], maint_cmd_start, to be reset by hw. - if (l_mbmccq.isBitSet(0)) - { - - FAPI_ERR("MBMCCQ[0]: maint_cmd_start not reset by hw on %s.",iv_target.toEcmdString()); - -// Calling out MBA target high, deconfig, gard - const fapi::Target & MBA = iv_target; -// FFDC: Capture register we are checking - ecmdDataBufferBase & MBMCC = l_mbmccq; -// FFDC: Capture command type we are trying to run - const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; -// FFDC: MBMCT[0:4] contains the cmd type previously run - ecmdDataBufferBase & MBMCT = l_mbmct; - -// Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_START_NOT_RESET); - } - -// Check for MBMCCQ[1], maint_cmd_stop, to be reset by hw. - if (l_mbmccq.isBitSet(1)) - { -// Log previous error before creating new log - if (l_rc) fapiLogError(l_rc); - - FAPI_ERR("MBMCCQ[1]: maint_cmd_stop not reset by hw on %s.",iv_target.toEcmdString()); - -// Calling out MBA target high, deconfig, gard - const fapi::Target & MBA = iv_target; -// FFDC: Capture register we are checking - ecmdDataBufferBase & MBMCC = l_mbmccq; -// FFDC: Capture command type we are trying to run - const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; -// FFDC: MBMCT[0:4] contains the cmd type previously run - ecmdDataBufferBase & MBMCT = l_mbmct; - -// Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_STOP_NOT_RESET); - } - -// Check for MBMSRQ[0], maint_cmd_in_progress, to be reset. - if (l_mbmsrq.isBitSet(0)) - { -// Log previous error before creating new log - if (l_rc) fapiLogError(l_rc); - - FAPI_ERR("MBMSRQ[0]: Can't start new cmd if previous cmd still in progress on %s.",iv_target.toEcmdString()); - -// Calling out FW high -// Calling out MBA target low, deconfig, gard - const fapi::Target & MBA = iv_target; -// FFDC: Capture register we are checking - ecmdDataBufferBase & MBMSR = l_mbmsrq; -// FFDC: Capture command type we are trying to run - const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; -// FFDC: MBMCT[0:4] contains the cmd type previously run - ecmdDataBufferBase & MBMCT = l_mbmct; - -// Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CMD_IN_PROGRESS); - } - -// Check MBAXCRn, to show memory configured behind this MBA - if (l_mbaxcr.isBitClear(0,4)) - { -// Log previous error before creating new log - if (l_rc) fapiLogError(l_rc); - - FAPI_ERR("MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA on %s.",iv_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = iv_target; -// FFDC: Capture register we are checking - ecmdDataBufferBase & MBAXCR = l_mbaxcr; - -// Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_MEM_CNFG); - } - -// Check CCS_MODEQ[29] to make sure mux switched from CCS to mainline - if (l_ccs_modeq.isBitSet(29)) - { -// Log previous error before creating new log - if (l_rc) fapiLogError(l_rc); - - FAPI_ERR("CCS_MODEQ[29] = 1, meaning mux set for CCS instead of mainline on %s.",iv_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = iv_target; -// FFDC: Capture register we are checking - ecmdDataBufferBase & CCS_MODE = l_ccs_modeq; -// FFDC: Capture command type we are trying to run - const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; - -// Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CCS_MUX_NOT_MAINLINE); - } - -// Check MBSECC[0] = 0, to make sure ECC check/correct is enabled - if (l_mbsecc.isBitSet(0)) - { -// Log previous error before creating new log - if (l_rc) fapiLogError(l_rc); - - FAPI_ERR("MBSECC[0] = 1, meaning ECC check/correct disabled on %s.",iv_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = iv_target; -// FFDC: Capture register we are checking - ecmdDataBufferBase & MBSECC = l_mbsecc; -// FFDC: Capture command type we are trying to run - const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; - -// Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_ECC_DISABLED); - } - - - FAPI_INF("EXIT mss_MaintCmd::preConditionCheck()"); - return l_rc; - } - - -//--------------------------------------------------------- -// mss_loadCmdType -//--------------------------------------------------------- - fapi::ReturnCode mss_MaintCmd::loadCmdType() - { - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_data(64); - uint8_t l_dram_gen; - - FAPI_INF("ENTER mss_MaintCmd::loadCmdType()"); - -// Get DDR3/DDR4: ATTR_EFF_DRAM_GEN -// 0x01 = ENUM_ATTR_EFF_DRAM_GEN_DDR3 -// 0x02 = ENUM_ATTR_EFF_DRAM_GEN_DDR4 - l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &iv_target, l_dram_gen); - if(l_rc) - { - FAPI_ERR("Error getting DDR3/DDR4 on %s.", iv_target.toEcmdString()); - return l_rc; - } - - l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_data); - if(l_rc) return l_rc; - l_ecmd_rc |= l_data.insert( (uint32_t)iv_cmdType, 0, 5, 32-5 ); - -// Setting super fast address increment mode for DDR3, where COL bits are LSB. Valid for all cmds. -// NOTE: Super fast address increment mode is broken for DDR4 due to DD1 bug - if (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) - { - l_ecmd_rc |= l_data.setBit(5); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - } - - l_rc = fapiPutScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_data); - if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_MaintCmd::loadCmdType()"); - return l_rc; - } - - - -//--------------------------------------------------------- -// mss_loadStartAddress -//--------------------------------------------------------- - fapi::ReturnCode mss_MaintCmd::loadStartAddress() - { - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_data(64); - - FAPI_INF("ENTER mss_MaintCmd::loadStartAddress()"); - - l_rc = fapiGetScom(iv_target, MBA01_MBMACAQ_0x0301060D, l_data); - if(l_rc) return l_rc; - -// Load address bits 0:39 - l_ecmd_rc |= l_data.insert( iv_startAddr, 0, 40, 0 ); - -// Clear error status bits 40:46 - l_ecmd_rc |= l_data.clearBit(40,7); - - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(iv_target, MBA01_MBMACAQ_0x0301060D, l_data); - if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_MaintCmd::loadStartAddress()"); - return l_rc; - } - - -//--------------------------------------------------------- -// mss_loadEndAddress -//--------------------------------------------------------- - fapi::ReturnCode mss_MaintCmd::loadEndAddress() - { - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_data(64); - - FAPI_INF("ENTER mss_MaintCmd::loadEndAddress()"); - - l_rc = fapiGetScom(iv_target, MBA01_MBMEAQ_0x0301060E, l_data); - if(l_rc) return l_rc; - - l_ecmd_rc |= l_data.insert( iv_endAddr, 0, 40, 0 ); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(iv_target, MBA01_MBMEAQ_0x0301060E, l_data); - if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_MaintCmd::loadEndAddress()"); - return l_rc; - } - - -//--------------------------------------------------------- -// mss_loadStopCondMask -//--------------------------------------------------------- - fapi::ReturnCode mss_MaintCmd::loadStopCondMask() - { - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_mbasctlq(64); - uint8_t l_mbspa_0_fixed_for_dd2 = 0; - - FAPI_INF("ENTER mss_MaintCmd::loadStopCondMask()"); - -// Get attribute that tells us if mbspa 0 cmd complete attention is fixed for dd2 - l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_HW217608_MBSPA_0_CMD_COMPLETE_ATTN_FIXED, &iv_targetCentaur, l_mbspa_0_fixed_for_dd2); - if(l_rc) - { - FAPI_ERR("Error getting ATTR_CENTAUR_EC_HW217608_MBSPA_0_CMD_COMPLETE_ATTN_FIXED"); - return l_rc; - } - -// Get stop conditions from MBASCTLQ - l_rc = fapiGetScom(iv_target, MBA01_MBASCTLQ_0x0301060F, l_mbasctlq); - if(l_rc) return l_rc; - -// Start by clearing all bits 0:12 and bit 16 - l_ecmd_rc |= l_mbasctlq.clearBit(0,13); - l_ecmd_rc |= l_mbasctlq.clearBit(16); - -// Enable stop immediate - if ( 0 != (iv_stopCondition & STOP_IMMEDIATE) ) - l_ecmd_rc |= l_mbasctlq.setBit(0); - -// Enable stop end of rank - if ( 0 != (iv_stopCondition & STOP_END_OF_RANK) ) - l_ecmd_rc |= l_mbasctlq.setBit(1); - -// Stop on hard NCE ETE - if ( 0 != (iv_stopCondition & STOP_ON_HARD_NCE_ETE) ) - l_ecmd_rc |= l_mbasctlq.setBit(2); - -// Stop on intermittent NCE ETE - if ( 0 != (iv_stopCondition & STOP_ON_INT_NCE_ETE) ) - l_ecmd_rc |= l_mbasctlq.setBit(3); - -// Stop on soft NCE ETE - if ( 0 != (iv_stopCondition & STOP_ON_SOFT_NCE_ETE) ) - l_ecmd_rc |= l_mbasctlq.setBit(4); - -// Stop on SCE - if ( 0 != (iv_stopCondition & STOP_ON_SCE) ) - l_ecmd_rc |= l_mbasctlq.setBit(5); - -// Stop on MCE - if ( 0 != (iv_stopCondition & STOP_ON_MCE) ) - l_ecmd_rc |= l_mbasctlq.setBit(6); - -// Stop on retry CE ETE - if ( 0 != (iv_stopCondition & STOP_ON_RETRY_CE_ETE) ) - l_ecmd_rc |= l_mbasctlq.setBit(7); - -// Stop on MPE - if ( 0 != (iv_stopCondition & STOP_ON_MPE) ) - l_ecmd_rc |= l_mbasctlq.setBit(8); - -// Stop on UE - if ( 0 != (iv_stopCondition & STOP_ON_UE) ) - l_ecmd_rc |= l_mbasctlq.setBit(9); - -// Stop on end address - if ( 0 != (iv_stopCondition & STOP_ON_END_ADDRESS) ) - l_ecmd_rc |= l_mbasctlq.setBit(10); - -// Enable command complete attention - if ( 0 != (iv_stopCondition & ENABLE_CMD_COMPLETE_ATTENTION) ) - l_ecmd_rc |= l_mbasctlq.setBit(11); - -// Stop on SUE - if ( 0 != (iv_stopCondition & STOP_ON_SUE) ) - l_ecmd_rc |= l_mbasctlq.setBit(12); - -// Command complete attention on clean and error -// DD2: enable (fixed) -// DD1: disable (broken) - if (l_mbspa_0_fixed_for_dd2) - { - l_ecmd_rc |= l_mbasctlq.setBit(16); - } - - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - -// Write stop conditions to MBASCTLQ - l_rc = fapiPutScom(iv_target, MBA01_MBASCTLQ_0x0301060F, l_mbasctlq); - if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_MaintCmd::loadStopCondMask()"); - - return l_rc; - } - - -//--------------------------------------------------------- -// mss_startMaintCmd -//--------------------------------------------------------- - fapi::ReturnCode mss_MaintCmd::startMaintCmd() - { - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_data(64); - - FAPI_INF("ENTER mss_MaintCmd::startMaintCmd()"); - - l_rc = fapiGetScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_data); - if(l_rc) return l_rc; - - l_ecmd_rc |= l_data.setBit(0); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_data); - if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_MaintCmd::startMaintCmd()"); - return l_rc; - } - -//--------------------------------------------------------- -// mss_postConditionCheck -//--------------------------------------------------------- - fapi::ReturnCode mss_MaintCmd::postConditionCheck() - { - fapi::ReturnCode l_rc; - ecmdDataBufferBase l_mbmccq(64); - ecmdDataBufferBase l_mbafirq(64); - ecmdDataBufferBase l_mbmct(64); - - FAPI_INF("ENTER mss_MaintCmd::postConditionCheck()"); - -// Read MBMCCQ - l_rc = fapiGetScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_mbmccq); - if(l_rc) return l_rc; - -// Read MBAFIRQ - l_rc = fapiGetScom(iv_target, MBA01_MBAFIRQ_0x03010600, l_mbafirq); - if(l_rc) return l_rc; - -// Read MBMCT[0:4], cmd type, for FFDC - l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_mbmct); - if(l_rc) return l_rc; - -// Check for MBMCCQ[0], maint_cmd_start, to be reset by hw. - if (l_mbmccq.isBitSet(0)) - { - FAPI_ERR("MBMCCQ[0]: maint_cmd_start not reset by hw on %s.",iv_target.toEcmdString()); - -// Calling out MBA target high, deconfig, gard - const fapi::Target & MBA = iv_target; -// FFDC: Capture register we are checking - ecmdDataBufferBase & MBMCC = l_mbmccq; -// FFDC: Capture command type we are trying to run - const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; -// FFDC: MBMCT[0:4] contains the cmd type set in hw - ecmdDataBufferBase & MBMCT = l_mbmct; - -// Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_START_NOT_RESET); - } - -// Check for MBAFIRQ[0], invalid_maint_cmd. - if (l_mbafirq.isBitSet(0)) - { -// Log previous error before creating new log - if (l_rc) fapiLogError(l_rc); - - FAPI_ERR("MBAFIRQ[0], invalid_maint_cmd on %s.",iv_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = iv_target; -// FFDC: Capture register we are checking - ecmdDataBufferBase & MBAFIR = l_mbafirq; -// FFDC: Capture command type we are trying to run - const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; -// FFDC: MBMCT[0:4] contains the cmd type set in hw - ecmdDataBufferBase & MBMCT = l_mbmct; - -// Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_CMD); - } - -// Check for MBAFIRQ[1], invalid_maint_address. - if (l_mbafirq.isBitSet(1)) - { -// Log previous error before creating new log - if (l_rc) fapiLogError(l_rc); - - FAPI_ERR("MBAFIRQ[1], cmd started with invalid_maint_address on %s.",iv_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = iv_target; -// FFDC: Capture register we are checking - ecmdDataBufferBase & MBAFIR = l_mbafirq; -// FFDC: Capture command type we are trying to run - const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; -// FFDC: MBMCT[0:4] contains the cmd type set in hw - ecmdDataBufferBase & MBMCT = l_mbmct; -// NOTE: List of additional FFDC regs specified in memory_errors.xml - -// Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_ADDR); - } - - FAPI_INF("EXIT mss_MaintCmd::postConditionCheck()"); - return l_rc; - } - -//--------------------------------------------------------- -// mss_pollForMaintCmdComplete -//--------------------------------------------------------- - fapi::ReturnCode mss_MaintCmd::pollForMaintCmdComplete() - { - - fapi::ReturnCode l_rc; - ecmdDataBufferBase l_data(64); - - FAPI_INF("ENTER mss_MaintCmd::pollForMaintCmdComplete()"); - - uint32_t count = 0; - -// 1 ms delay for HW mode -- LWM changed 100,000,000 to 1,000,000 to match comment - const uint64_t HW_MODE_DELAY = 1000000; - -// 200000 sim cycle delay for SIM mode - const uint64_t SIM_MODE_DELAY = 200000; - - uint32_t loop_limit = 50000; - - do - { - fapiDelay(HW_MODE_DELAY, SIM_MODE_DELAY); - -// Want to see cmd complete attention - l_rc = fapiGetScom(iv_target, MBA01_MBSPAQ_0x03010611, l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBSPAQ = 0x%.8X 0x%.8X",l_data.getWord(0), l_data.getWord(1)); - -// Read MBMACAQ just to see if it's incrementing - l_rc = fapiGetScom(iv_target, MBA01_MBMACAQ_0x0301060D, l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBMACAQ = 0x%.8X 0x%.8X",l_data.getWord(0), l_data.getWord(1)); - -// Waiting for MBMSRQ[0] maint cmd in progress bit to turn off - l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBMSRQ = 0x%.8X 0x%.8X",l_data.getWord(0), l_data.getWord(1)); - - count++; - - } -// Poll until cmd in progress bit goes off - while (l_data.isBitSet(0) && (count < loop_limit)); - - if (count == loop_limit) - { - FAPI_ERR("Maint cmd timeout on %s.",iv_target.toEcmdString()); - -// Calling out FW high -// Calling out MBA target low, deconfig, gard - const fapi::Target & MBA = iv_target; -// FFDC: Capture command type we are trying to run - const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; -// Specify CENTAUR target so we can read some FFDC regs from MBS - const fapi::Target & CENTAUR = iv_targetCentaur; -// NOTE: List of additional FFDC regs specified in memory_errors.xml - -// Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CMD_TIMEOUT); - } - else - { - FAPI_INF("Maint cmd complete. "); - } - - FAPI_INF("EXIT mss_MaintCmd::pollForMaintCmdComplete()"); - return l_rc; - } - -//--------------------------------------------------------- -// mss_collectFFDC -//--------------------------------------------------------- - fapi::ReturnCode mss_MaintCmd::collectFFDC() - { - fapi::ReturnCode l_rc; - ecmdDataBufferBase l_data(64); - uint8_t l_dramSparePort0Symbol = MSS_INVALID_SYMBOL; - uint8_t l_dramSparePort1Symbol = MSS_INVALID_SYMBOL; - uint8_t l_eccSpareSymbol = MSS_INVALID_SYMBOL; - uint8_t l_symbol_mark = MSS_INVALID_SYMBOL; - uint8_t l_chip_mark = MSS_INVALID_SYMBOL; - - FAPI_INF("ENTER mss_MaintCmd::collectFFDC()"); - - l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBMCTQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - - l_rc = fapiGetScom(iv_target, MBA01_MBMACAQ_0x0301060D, l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBMACAQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - -// Print out error status bits from MBMACAQ - if (l_data.isBitSet(40)) FAPI_DBG("MBMACAQ error status: 40:NCE"); - if (l_data.isBitSet(41)) FAPI_DBG("MBMACAQ error status: 41:SCE"); - if (l_data.isBitSet(42)) FAPI_DBG("MBMACAQ error status: 42:MCE"); - if (l_data.isBitSet(43)) FAPI_DBG("MBMACAQ error status: 43:RCE"); - if (l_data.isBitSet(44)) FAPI_DBG("MBMACAQ error status: 44:MPE"); - if (l_data.isBitSet(45)) FAPI_DBG("MBMACAQ error status: 45:UE"); - if (l_data.isBitSet(46)) FAPI_DBG("MBMACAQ error status: 46:SUE"); - - l_rc = fapiGetScom(iv_target, MBA01_MBMEAQ_0x0301060E, l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBMEAQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - - l_rc = fapiGetScom(iv_target, MBA01_MBASCTLQ_0x0301060F, l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBASCTLQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - - l_rc = fapiGetScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBMCCQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - - l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBMSRQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - - l_rc = fapiGetScom(iv_target, MBA01_MBAFIRQ_0x03010600, l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBAFIRQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - - l_rc = fapiGetScom(iv_target, MBA01_MBSPAQ_0x03010611, l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBSPAQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - - l_rc = fapiGetScom(iv_target, MBA01_MBACALFIR_0x03010400, l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBACALFIR = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - - l_rc = fapiGetScom(iv_targetCentaur, mss_mbeccfir[iv_mbaPosition], l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBECCFIR = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - -// Print out maint ECC FIR bits from MBECCFIR - if (l_data.isBitSet(20)) FAPI_DBG("20:Maint MPE, rank0"); - if (l_data.isBitSet(21)) FAPI_DBG("21:Maint MPE, rank1"); - if (l_data.isBitSet(22)) FAPI_DBG("22:Maint MPE, rank2"); - if (l_data.isBitSet(23)) FAPI_DBG("23:Maint MPE, rank3"); - if (l_data.isBitSet(24)) FAPI_DBG("24:Maint MPE, rank4"); - if (l_data.isBitSet(25)) FAPI_DBG("25:Maint MPE, rank5"); - if (l_data.isBitSet(26)) FAPI_DBG("26:Maint MPE, rank6"); - if (l_data.isBitSet(27)) FAPI_DBG("27:Maint MPE, rank7"); - if (l_data.isBitSet(36)) FAPI_DBG("36: Maint NCE"); - if (l_data.isBitSet(37)) FAPI_DBG("37: Maint SCE"); - if (l_data.isBitSet(38)) FAPI_DBG("38: Maint MCE"); - if (l_data.isBitSet(39)) FAPI_DBG("39: Maint RCE"); - if (l_data.isBitSet(40)) FAPI_DBG("40: Maint SUE"); - if (l_data.isBitSet(41)) FAPI_DBG("41: Maint UE"); - - FAPI_DBG("Markstore"); - for ( uint8_t i = 0; i < MSS_MAX_RANKS; i++ ) - { - l_rc = fapiGetScom(iv_targetCentaur, mss_markStoreRegs[i][iv_mbaPosition], l_data); - if(l_rc) return l_rc; - FAPI_DBG("MBMS%d = 0x%.8X 0x%.8X",i, l_data.getWord(0), l_data.getWord(1)); - } - - for ( uint8_t i = 0; i < MSS_MAX_RANKS; i++ ) - { - l_rc = mss_get_mark_store(iv_target, i, l_symbol_mark, l_chip_mark ); - if (l_rc) - { - FAPI_ERR("Error reading markstore on %s.",iv_target.toEcmdString()); - return l_rc; - } - } - - FAPI_DBG("Steer MUXES"); - for ( uint8_t i = 0; i < MSS_MAX_RANKS; i++ ) - { - l_rc = mss_check_steering(iv_target, - i, - l_dramSparePort0Symbol, - l_dramSparePort1Symbol, - l_eccSpareSymbol); - if(l_rc) return l_rc; - } - - FAPI_INF("EXIT mss_MaintCmd::collectFFDC()"); - return l_rc; - } - - -//--------------------------------------------------------- -// mss_loadPattern -//--------------------------------------------------------- - fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern) - { - - FAPI_INF("ENTER mss_MaintCmd::loadPattern()"); - - static const uint32_t maintBufferDataRegs[2][16][2]={ - // port0 - {{MAINT0_MBS_MAINT_BUFF0_DATA0_0x0201160A, MAINT0_MBS_MAINT_BUFF0_DATA_ECC0_0x02011612},// DW0 - {MAINT0_MBS_MAINT_BUFF2_DATA0_0x0201162A, MAINT0_MBS_MAINT_BUFF2_DATA_ECC0_0x02011632}, // DW2 - {MAINT0_MBS_MAINT_BUFF0_DATA1_0x0201160B, MAINT0_MBS_MAINT_BUFF0_DATA_ECC1_0x02011613}, // DW4 - {MAINT0_MBS_MAINT_BUFF2_DATA1_0x0201162B, MAINT0_MBS_MAINT_BUFF2_DATA_ECC1_0x02011633}, // DW6 - {MAINT0_MBS_MAINT_BUFF0_DATA2_0x0201160C, MAINT0_MBS_MAINT_BUFF0_DATA_ECC2_0x02011614}, // DW8 - {MAINT0_MBS_MAINT_BUFF2_DATA2_0x0201162C, MAINT0_MBS_MAINT_BUFF2_DATA_ECC2_0x02011634}, // DW10 - {MAINT0_MBS_MAINT_BUFF0_DATA3_0x0201160D, MAINT0_MBS_MAINT_BUFF0_DATA_ECC3_0x02011615}, // DW12 - {MAINT0_MBS_MAINT_BUFF2_DATA3_0x0201162D, MAINT0_MBS_MAINT_BUFF2_DATA_ECC3_0x02011635}, // DW14 - - // port1 - {MAINT0_MBS_MAINT_BUFF1_DATA0_0x0201161A, MAINT0_MBS_MAINT_BUFF1_DATA_ECC0_0x02011622}, // DW1 - {MAINT0_MBS_MAINT_BUFF3_DATA0_0x0201163A, MAINT0_MBS_MAINT_BUFF3_DATA_ECC0_0x02011642}, // DW3 - {MAINT0_MBS_MAINT_BUFF1_DATA1_0x0201161B, MAINT0_MBS_MAINT_BUFF1_DATA_ECC1_0x02011623}, // DW5 - {MAINT0_MBS_MAINT_BUFF3_DATA1_0x0201163B, MAINT0_MBS_MAINT_BUFF3_DATA_ECC1_0x02011643}, // DW7 - {MAINT0_MBS_MAINT_BUFF1_DATA2_0x0201161C, MAINT0_MBS_MAINT_BUFF1_DATA_ECC2_0x02011624}, // DW9 - {MAINT0_MBS_MAINT_BUFF3_DATA2_0x0201163C, MAINT0_MBS_MAINT_BUFF3_DATA_ECC2_0x02011644}, // DW11 - {MAINT0_MBS_MAINT_BUFF1_DATA3_0x0201161D, MAINT0_MBS_MAINT_BUFF1_DATA_ECC3_0x02011625}, // DW13 - {MAINT0_MBS_MAINT_BUFF3_DATA3_0x0201163D, MAINT0_MBS_MAINT_BUFF3_DATA_ECC3_0x02011645}},// DW15 - - // port2 - {{MAINT1_MBS_MAINT_BUFF0_DATA0_0x0201170A, MAINT1_MBS_MAINT_BUFF0_DATA_ECC0_0x02011712},// DW0 - {MAINT1_MBS_MAINT_BUFF2_DATA0_0x0201172A, MAINT1_MBS_MAINT_BUFF2_DATA_ECC0_0x02011732}, // DW2 - {MAINT1_MBS_MAINT_BUFF0_DATA1_0x0201170B, MAINT1_MBS_MAINT_BUFF0_DATA_ECC1_0x02011713}, // DW4 - {MAINT1_MBS_MAINT_BUFF2_DATA1_0x0201172B, MAINT1_MBS_MAINT_BUFF2_DATA_ECC1_0x02011733}, // DW6 - {MAINT1_MBS_MAINT_BUFF0_DATA2_0x0201170C, MAINT1_MBS_MAINT_BUFF0_DATA_ECC2_0x02011714}, // DW8 - {MAINT1_MBS_MAINT_BUFF2_DATA2_0x0201172C, MAINT1_MBS_MAINT_BUFF2_DATA_ECC2_0x02011734}, // DW10 - {MAINT1_MBS_MAINT_BUFF0_DATA3_0x0201170D, MAINT1_MBS_MAINT_BUFF0_DATA_ECC3_0x02011715}, // DW12 - {MAINT1_MBS_MAINT_BUFF2_DATA3_0x0201172D, MAINT1_MBS_MAINT_BUFF2_DATA_ECC3_0x02011735}, // DW14 - - // port3 - {MAINT1_MBS_MAINT_BUFF1_DATA0_0x0201171A, MAINT1_MBS_MAINT_BUFF1_DATA_ECC0_0x02011722}, // DW1 - {MAINT1_MBS_MAINT_BUFF3_DATA0_0x0201173A, MAINT1_MBS_MAINT_BUFF3_DATA_ECC0_0x02011742}, // DW3 - {MAINT1_MBS_MAINT_BUFF1_DATA1_0x0201171B, MAINT1_MBS_MAINT_BUFF1_DATA_ECC1_0x02011723}, // DW5 - {MAINT1_MBS_MAINT_BUFF3_DATA1_0x0201173B, MAINT1_MBS_MAINT_BUFF3_DATA_ECC1_0x02011743}, // DW6 - {MAINT1_MBS_MAINT_BUFF1_DATA2_0x0201171C, MAINT1_MBS_MAINT_BUFF1_DATA_ECC2_0x02011724}, // DW9 - {MAINT1_MBS_MAINT_BUFF3_DATA2_0x0201173C, MAINT1_MBS_MAINT_BUFF3_DATA_ECC2_0x02011744}, // DW11 - {MAINT1_MBS_MAINT_BUFF1_DATA3_0x0201171D, MAINT1_MBS_MAINT_BUFF1_DATA_ECC3_0x02011725}, // DW13 - {MAINT1_MBS_MAINT_BUFF3_DATA3_0x0201173D, MAINT1_MBS_MAINT_BUFF3_DATA_ECC3_0x02011745}}};// DW15 - - - static const uint32_t maintBuffer65thRegs[4][2]={ - // MBA01 MBA23 - {MAINT0_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC0_0x0201164A, MAINT1_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC0_0x0201174A}, // 1st 64B of cacheline - {MAINT0_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC1_0x0201164B, MAINT1_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC1_0x0201174B}, // 1st 64B of cacheline - {MAINT0_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC2_0x0201164C, MAINT1_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC2_0x0201174C}, // 2nd 64B of cacheline - {MAINT0_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC3_0x0201164D, MAINT1_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC3_0x0201174D}};// 2nd 64B of cacheline - - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_data(64); - ecmdDataBufferBase l_ecc(64); - ecmdDataBufferBase l_65th(64); - ecmdDataBufferBase l_mbmmr(64); - ecmdDataBufferBase l_mbsecc(64); - uint32_t loop = 0; - uint8_t l_dramWidth = 0; - - FAPI_INF("pattern = 0x%.8X 0x%.8X", - mss_maintBufferData[l_dramWidth][i_initPattern][0][0], - mss_maintBufferData[l_dramWidth][i_initPattern][0][1]); - - //---------------------------------------------------- - // Get l_dramWidth - //---------------------------------------------------- - l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &iv_target, l_dramWidth); - if(l_rc) - { - FAPI_ERR("Error getting DRAM width on %s.",iv_target.toEcmdString()); - return l_rc; - } - - // Convert from attribute enum values: 8,4 to index values: 0,1 - if(l_dramWidth == mss_MemConfig::X8) - { - l_dramWidth = 0; - } - else - { - l_dramWidth = 1; - } - - - //---------------------------------------------------- - // Load the data: 16 loops x 64bits = 128B cacheline - //---------------------------------------------------- - FAPI_INF("Load the data: 16 loops x 64bits = 128B cacheline"); - - // Set bit 9 so that hw will generate the fabric ECC. - // This is an 8B ECC protecting the data moving on internal buses in - // the Centaur. - l_ecmd_rc |= l_ecc.flushTo0(); - l_ecmd_rc |= l_ecc.setBit(9); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - for(loop=0; loop<16; loop++ ) - { - // A write to MAINT_BUFFx_DATAy will not update until the corresponding - // MAINT_BUFFx_DATA_ECCy is written to. - l_ecmd_rc |= l_data.insert(mss_maintBufferData[l_dramWidth][i_initPattern][loop][0], 0, 32, 0); - l_ecmd_rc |= l_data.insert(mss_maintBufferData[l_dramWidth][i_initPattern][loop][1], 32, 32, 0); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][0], l_data); - if(l_rc) return l_rc; - - l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][1], l_ecc); - if(l_rc) return l_rc; - } - - //---------------------------------------------------- - // Load the 65th byte: 4 loops to fill in the two 65th bytes in cacheline - //---------------------------------------------------- - FAPI_INF("Load the 65th byte: 4 loops to fill in the two 65th bytes in the cacheline"); - - l_ecmd_rc |= l_65th.flushTo0(); - - // Set bit 56 so that hw will generate the fabric ECC. - // This is an 8B ECC protecting the data moving on internal buses in Centaur. - l_ecmd_rc |= l_65th.setBit(56); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - for(loop=0; loop<4; loop++ ) - { - l_ecmd_rc |= l_65th.insert(mss_65thByte[l_dramWidth][i_initPattern][loop], 1, 3, 1); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - l_rc = fapiPutScom(iv_targetCentaur, maintBuffer65thRegs[loop][iv_mbaPosition], l_65th); - if(l_rc) return l_rc; - } - - //---------------------------------------------------- - // Save i_initPattern in unused maint mark reg - // so we know what pattern was used when we do - // UE isolation - //---------------------------------------------------- - - // No plans to use maint mark, but make sure it's disabled to be safe - l_rc = fapiGetScom(iv_targetCentaur, mss_mbsecc[iv_mbaPosition], l_mbsecc); - if(l_rc) return l_rc; - l_ecmd_rc |= l_mbsecc.clearBit(4); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - uint8_t l_attr_centaur_ec_enable_rce_with_other_errors_hw246685; - l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685, &iv_targetCentaur, l_attr_centaur_ec_enable_rce_with_other_errors_hw246685); - if(l_rc) return l_rc; - - if(l_attr_centaur_ec_enable_rce_with_other_errors_hw246685) - { - l_ecmd_rc = l_ecmd_rc | l_mbsecc.setBit(16); - } - - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - - l_rc = fapiPutScom(iv_targetCentaur, mss_mbsecc[iv_mbaPosition], l_mbsecc); - if(l_rc) return l_rc; - - - l_ecmd_rc |= l_mbmmr.flushTo0(); - // Store i_initPattern, with range 0-8, in MBMMR bits 4-7 - l_ecmd_rc |= l_mbmmr.insert((uint8_t)i_initPattern, 4, 4, 8-4); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(iv_targetCentaur, mss_mbmmr[iv_mbaPosition] , l_mbmmr); - if(l_rc) return l_rc; - - - FAPI_INF("EXIT mss_MaintCmd::loadPattern()"); - - return l_rc; - } - -//--------------------------------------------------------- -// mss_loadSpeed -//--------------------------------------------------------- - fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) - { - - FAPI_INF("ENTER mss_MaintCmd::loadSpeed()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_data(64); - uint32_t l_ddr_freq = 0; - uint64_t l_step_size = 0; - uint64_t l_num_address_bits = 0; - uint64_t l_num_addresses = 0; - uint64_t l_address_bit = 0; - ecmdDataBufferBase l_start_address(64); - ecmdDataBufferBase l_end_address(64); - uint64_t l_cmd_interval = 0; - - // burst_window_sel - // MBMCTQ[6]: 0 = 512 Maint Clks - // 1 = 536870912 Maint Clks - uint8_t l_burst_window_sel = 0; - - // timebase_sel - // MBMCTQ[9:10]: 00 = 1 Maint Clk - // 01 = 8192 Maint clks - uint8_t l_timebase_sel = 0; - - // timebase_burst_sel - // MBMCTQ[11]: 0 = disable burst mode - // 1 = enable burst mode - uint8_t l_timebase_burst_sel = 0; - - // timebase_interval - // MBMCTQ[12:23]: The operation interval for timebase operations - // equals the timebase_sel x MBMCTQ[12:23]. - // NOTE: Should never be 0, or will hang mainline traffic. - uint32_t l_timebase_interval = 1; - - // burst_window - // MBMCTQ[24:31]: The burst window for timebase operations with burst mode - // enabled equals burst_window_sel x MBMCTQ[24:31] - uint8_t l_burst_window = 0; - - // burst_interval - // MBMCTQ[32:39]: The burst interval for timebase operations with burst mode - // enabled equals the number of burst windows that will have - // no operations occurring in them. - uint8_t l_burst_interval = 0; - - l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_data); - if(l_rc) return l_rc; - - - if (FAST_MAX_BW_IMPACT == i_speed) - { - l_timebase_sel = 0; - l_timebase_interval = 1; - } - - else if (FAST_MED_BW_IMPACT == i_speed) - { - l_timebase_sel = 0; - l_timebase_interval = 512; - } - - else if (FAST_MIN_BW_IMPACT == i_speed) - { - l_timebase_sel = 1; - l_timebase_interval = 12; - } - - else // BG_SCRUB - { - // Get l_ddr_freq from ATTR_MSS_FREQ - // Possible frequencies are 800, 1066, 1333, 1600, 1866, and 2133 MHz - // NOTE: Max 32 address bits using 800 and 1066 result in scrub - // taking longer than 12h, but these is no plan to actually use - // those frequencies. - l_rc = FAPI_ATTR_GET( ATTR_MSS_FREQ, &iv_targetCentaur, l_ddr_freq); - if (l_rc) - { - FAPI_ERR("Failed to get attribute: ATTR_MSS_FREQ on %s.",iv_target.toEcmdString()); - return l_rc; - } - - // Make sure it's non-zero, to avoid divide by 0 - if (l_ddr_freq == 0) - { - FAPI_ERR("ATTR_MSS_FREQ set to zero so can't calculate scrub rate on %s.",iv_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = iv_target; - // FFDC: Capture command type we are trying to run - const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; - - // Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_ZERO_DDR_FREQ); - return l_rc; - } - - // l_timebase_sel - // MBMCTQ[9:10]: 00 = 1 * Maint Clk - // 01 = 8192 * Maint Clk - // Where Maint Clk = 2/1_ddr_freq - l_timebase_sel = 1; - - // Get l_step_size in nSec - l_step_size = 8192*2*1000/l_ddr_freq; - - FAPI_DBG("l_ddr_freq = %d MHz, l_step_size = %d nSec", - (uint32_t)l_ddr_freq, (uint32_t)l_step_size); - - // Get l_end_address - l_rc = mss_get_address_range( iv_target, - MSS_ALL_RANKS, - l_start_address, - l_end_address ); - if (l_rc) - { - FAPI_ERR("mss_get_address_range failed on %s.",iv_target.toEcmdString()); - return l_rc; - } - - // Get l_num_address_bits by counting bits set to 1 in l_end_address. - for(l_address_bit=0; l_address_bit<37; l_address_bit++ ) - { - if(l_end_address.isBitSet(l_address_bit)) - { - l_num_address_bits++; - } - } - - // NOTE: Assumption is max 32 address bits, which can be done - // in 12h (+/- 2h). More than 32 address bits would - // double scrub time for every extra address bit. - if (l_num_address_bits > 32) - { - FAPI_INF("WARNING: l_num_address_bits: %d, is greater than 32, so scrub will take longer than 12h.",(uint32_t)l_num_address_bits); - } - - // NOTE: Smallest number of address bits is supposed to be 25. - // So if for some reason it's less (like in VBU), - // use 25 anyway so the scrub rate calculation still works. - if (l_num_address_bits < 25) - { - FAPI_INF("WARNING: l_num_address_bits: %d, is less than 25, but using 25 in calculation anyway.",(uint32_t)l_num_address_bits); - l_num_address_bits = 25; - } - - // Get l_num_addresses - l_num_addresses = 1; - for(uint32_t i=0; i<l_num_address_bits; i++ ) - { - l_num_addresses *=2; - } - // Convert to M addresses - l_num_addresses /=1000000; - - // Get interval between cmds in order to through l_num_addresses in 12h - l_cmd_interval = (12 * 60 * 60 * 1000)/l_num_addresses; - - // How many times to multiply l_step_size to get l_cmd_interval? - l_timebase_interval = l_cmd_interval/l_step_size; - - // Round up to nearest integer for more accurate number - l_timebase_interval += (l_cmd_interval % l_step_size >= l_step_size/2) ? 1:0; - - // Make sure smallest is 1 - if (l_timebase_interval == 0) l_timebase_interval = 1; - - FAPI_DBG("l_num_address_bits = %d, l_num_addresses = %d (M), l_cmd_interval = %d nSec, l_timebase_interval = %d", - (uint32_t)l_num_address_bits, (uint32_t)l_num_addresses, (uint32_t)l_cmd_interval, (uint32_t)l_timebase_interval); - - } // End BG_SCRUB - - // burst_window_sel - // MBMCTQ[6] - l_ecmd_rc |= l_data.insert( l_burst_window_sel, 6, 1, 8-1 ); - - // timebase_sel - // MBMCTQ[9:10] - l_ecmd_rc |= l_data.insert( l_timebase_sel, 9, 2, 8-2 ); - - // timebase_burst_sel - // MBMCTQ[11] - l_ecmd_rc |= l_data.insert( l_timebase_burst_sel, 11, 1, 8-1 ); - - // timebase_interval - // MBMCTQ[12:23] - l_ecmd_rc |= l_data.insert( l_timebase_interval, 12, 12, 32-12 ); - - // burst_window - // MBMCTQ[24:31] - l_ecmd_rc |= l_data.insert( l_burst_window, 24, 8, 8-8 ); - - // burst_interval - // MBMCTQ[32:39] - l_ecmd_rc |= l_data.insert( l_burst_interval, 32, 8, 8-8 ); - - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - l_rc = fapiPutScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_data); - if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_MaintCmd::loadSpeed()"); - - return l_rc; - } - - - - - - - -//------------------------------------------------------------------------------ -// Child classes -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// SuperFastInit -//------------------------------------------------------------------------------ - - - const mss_MaintCmd::CmdType mss_SuperFastInit::cv_cmdType = SUPERFAST_INIT; - -//--------------------------------------------------------- -// mss_SuperFastInit Constructor -//--------------------------------------------------------- - mss_SuperFastInit::mss_SuperFastInit( const fapi::Target & i_target, - const ecmdDataBufferBase & i_startAddr, - const ecmdDataBufferBase & i_endAddr, - PatternIndex i_initPattern, - uint32_t i_stopCondition, - bool i_poll ) : - mss_MaintCmd( i_target, - i_startAddr, - i_endAddr, - i_stopCondition, - i_poll, - cv_cmdType), - iv_initPattern( i_initPattern ) // NOTE: iv_initPattern is instance -// variable of SuperFastInit, since not -// needed in parent class - {} - - - - - -//--------------------------------------------------------- -// mss_SuperFastInit setupAndExecuteCmd -//--------------------------------------------------------- - fapi::ReturnCode mss_SuperFastInit::setupAndExecuteCmd() - { - - - FAPI_INF("ENTER mss_SuperFastInit::setupAndExecuteCmd()"); - - - fapi::ReturnCode l_rc; - ecmdDataBufferBase l_data(64); - -// Gather data that needs to be stored. For testing purposes we will just -// set an abitrary number. -//l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; -//printf( "Saved data: 0x%08x\n", getSavedData() ); - - -// Make sure maint logic in valid state to run new cmd - l_rc = preConditionCheck(); if(l_rc) return l_rc; - -// Load pattern - l_rc = loadPattern(iv_initPattern); if(l_rc) return l_rc; - -// Load cmd type: MBMCTQ - l_rc = loadCmdType(); if(l_rc) return l_rc; - -// Load start address: MBMACAQ - l_rc = loadStartAddress(); if(l_rc) return l_rc; - -// Load end address: MBMEAQ - l_rc = loadEndAddress(); if(l_rc) return l_rc; - - -// Load stop conditions: MBASCTLQ - l_rc = loadStopCondMask(); if(l_rc) return l_rc; - -// Start the command: MBMCCQ - l_rc = startMaintCmd(); if(l_rc) return l_rc; - -// Check for early problems with maint cmd instead of waiting for -// cmd timeout - l_rc = postConditionCheck(); if(l_rc) return l_rc; - - if(iv_poll == false) - { - FAPI_INF("Cmd has started. Use attentions to detect cmd complete."); - FAPI_INF("EXIT mss_SuperFastInit::setupAndExecuteCmd()"); - return l_rc; - } - -// Poll for command complete: MBMSRQ - l_rc = pollForMaintCmdComplete(); if(l_rc) return l_rc; - -// Collect FFDC - l_rc = collectFFDC(); if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_SuperFastInit::setupAndExecuteCmd()"); - - return l_rc; - } - - - - -//------------------------------------------------------------------------------ -// mss_SuperFastRandomInit -//------------------------------------------------------------------------------ - - - const mss_MaintCmd::CmdType mss_SuperFastRandomInit::cv_cmdType = SUPERFAST_RANDOM_INIT; - -//--------------------------------------------------------- -// mss_SuperFastInit Constructor -//--------------------------------------------------------- - mss_SuperFastRandomInit::mss_SuperFastRandomInit( const fapi::Target & i_target, - const ecmdDataBufferBase & i_startAddr, - const ecmdDataBufferBase & i_endAddr, - PatternIndex i_initPattern, - uint32_t i_stopCondition, - bool i_poll ) : - mss_MaintCmd( i_target, - i_startAddr, - i_endAddr, - i_stopCondition, - i_poll, - cv_cmdType), - iv_initPattern( i_initPattern ) - {} - - - - - -//--------------------------------------------------------- -// mss_SuperFastRandomInit setupAndExecuteCmd -//--------------------------------------------------------- - fapi::ReturnCode mss_SuperFastRandomInit::setupAndExecuteCmd() - { - - - FAPI_INF("ENTER mss_SuperFastRandomInit::setupAndExecuteCmd()"); - - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - -// Gather data that needs to be stored. For testing purposes we will just -// set an abitrary number. -//l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; -//printf( "Saved data: 0x%08x\n", getSavedData() ); - - -// Make sure maint logic in valid state to run new cmd - l_rc = preConditionCheck(); if(l_rc) return l_rc; - -// Load pattern - l_rc = loadPattern(iv_initPattern); if(l_rc) return l_rc; - -// Load cmd type: MBMCTQ - l_rc = loadCmdType(); if(l_rc) return l_rc; - -// Load start address: MBMACAQ - l_rc = loadStartAddress(); if(l_rc) return l_rc; - -// Load end address: MBMEAQ - l_rc = loadEndAddress(); if(l_rc) return l_rc; - -// Load stop conditions: MBASCTLQ - l_rc = loadStopCondMask(); if(l_rc) return l_rc; - -// Disable 8B ECC check/correct on WRD data bus: MBA_WRD_MODE(0:1) = 11 -// before a SuperFastRandomInit command is issued - l_rc = fapiGetScom(iv_target, MBA01_MBA_WRD_MODE_0x03010449, iv_saved_MBA_WRD_MODE); - if(l_rc) return l_rc; - - ecmdDataBufferBase l_data(64); - l_ecmd_rc |= l_data.insert(iv_saved_MBA_WRD_MODE, 0, 64, 0); - l_ecmd_rc |= l_data.setBit(0); - l_ecmd_rc |= l_data.setBit(1); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(iv_target, MBA01_MBA_WRD_MODE_0x03010449, l_data); - if(l_rc) return l_rc; - -// Start the command: MBMCCQ - l_rc = startMaintCmd(); if(l_rc) return l_rc; - -// Check for early problems with maint cmd instead of waiting for -//cmd timeout - l_rc = postConditionCheck(); if(l_rc) return l_rc; - - if(iv_poll == false) - { - FAPI_INF("Cmd has started. Use attentions to detect cmd complete."); - FAPI_INF("EXIT mss_SuperFastRandomInit::setupAndExecuteCmd()"); - return l_rc; - } - -// Poll for command complete: MBMSRQ - l_rc = pollForMaintCmdComplete(); if(l_rc) return l_rc; - -// Collect FFDC - l_rc = collectFFDC(); if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_SuperFastRandomInit::setupAndExecuteCmd()"); - - return l_rc; - } - - - fapi::ReturnCode mss_SuperFastRandomInit::cleanupCmd() - { - - FAPI_INF("ENTER mss_SuperFastRandomInit::cleanupCmd()"); - - fapi::ReturnCode l_rc; - -// Clear maintenance command complete attention, scrub stats, etc... - -// Restore MBA_WRD_MODE - l_rc = fapiPutScom(iv_target, MBA01_MBA_WRD_MODE_0x03010449, iv_saved_MBA_WRD_MODE); - if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_SuperFastRandomInit::cleanupCmd()"); - - return l_rc; - } - - - -//------------------------------------------------------------------------------ -// mss_SuperFastRead -//------------------------------------------------------------------------------ - - const mss_MaintCmd::CmdType mss_SuperFastRead::cv_cmdType = SUPERFAST_READ; - -//--------------------------------------------------------- -// mss_SuperFastRead Constructor -//--------------------------------------------------------- - - mss_SuperFastRead::mss_SuperFastRead( const fapi::Target & i_target, - const ecmdDataBufferBase & i_startAddr, - const ecmdDataBufferBase & i_endAddr, - uint32_t i_stopCondition, - bool i_poll ) : - mss_MaintCmd( i_target, - i_startAddr, - i_endAddr, - i_stopCondition, - i_poll, - cv_cmdType){} - -//--------------------------------------------------------- -// mss_SuperReadInit setupAndExecuteCmd -//--------------------------------------------------------- - - fapi::ReturnCode mss_SuperFastRead::setupAndExecuteCmd() - { - FAPI_INF("ENTER mss_SuperFastRead::setupAndExecuteCmd()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - -// Gather data that needs to be stored. For testing purposes we will just -// set an abitrary number. -//l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; -//printf( "Saved data: 0x%08x\n", getSavedData() ); - -// Make sure maint logic in valid state to run new cmd - l_rc = preConditionCheck(); if(l_rc) return l_rc; - -// Setup required to trap UE actual data needed for IPL UE isolation - l_rc = ueTrappingSetup(); if(l_rc) return l_rc; - -// Load cmd type: MBMCTQ - l_rc = loadCmdType(); if(l_rc) return l_rc; - -// Load start address: MBMACAQ - l_rc = loadStartAddress(); if(l_rc) return l_rc; - -// Load end address: MBMEAQ - l_rc = loadEndAddress(); if(l_rc) return l_rc; - -// Load stop conditions: MBASCTLQ - l_rc = loadStopCondMask(); if(l_rc) return l_rc; - -// Need to set RRQ to fifo mode to ensure super fast read commands -// are done on order. Otherwise, if cmds get out of order we can't be sure -// the trapped address in MBMACA will be correct when we stop -// on error. That means we could unintentionally skip addresses if we just -// try to increment MBMACA and continue. -// NOTE: Cleanup needs to be done to restore settings done. - l_rc = fapiGetScom(iv_target, MBA01_MBA_RRQ0Q_0x0301040E, iv_saved_MBA_RRQ0); - if(l_rc) return l_rc; - - ecmdDataBufferBase l_data(64); - l_ecmd_rc |= l_data.insert(iv_saved_MBA_RRQ0, 0, 64, 0); - l_ecmd_rc |= l_data.clearBit(6,5); // Set 6:10 = 00000 (fifo mode) - l_ecmd_rc |= l_data.setBit(12); // Disable MBA RRQ fastpath - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(iv_target, MBA01_MBA_RRQ0Q_0x0301040E, l_data); - if(l_rc) return l_rc; - - -// Start the command: MBMCCQ - l_rc = startMaintCmd(); if(l_rc) return l_rc; - -// Check for early problems with maint cmd instead of waiting for -// cmd timeout - l_rc = postConditionCheck(); if(l_rc) return l_rc; - - if(iv_poll == false) - { - FAPI_INF("Cmd has started. Use attentions to detect cmd complete."); - FAPI_INF("EXIT mss_SuperFastRead::setupAndExecuteCmd()"); - return l_rc; - } - -// Poll for command complete: MBMSRQ - l_rc = pollForMaintCmdComplete(); if(l_rc) return l_rc; - -// Collect FFDC - l_rc = collectFFDC(); if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_SuperFastRead::setupAndExecuteCmd()"); - - return l_rc; - - } - - fapi::ReturnCode mss_SuperFastRead::ueTrappingSetup() - { - - FAPI_INF("ENTER mss_SuperFastRead::ueTrappingSetup()"); - - fapi::ReturnCode l_rc; - - static const uint32_t maintBufferDataRegs[2][2][2]={ -// port0/1 - {{MAINT0_MBS_MAINT_BUFF0_DATA0_0x0201160A, MAINT0_MBS_MAINT_BUFF0_DATA_ECC0_0x02011612}, - {MAINT0_MBS_MAINT_BUFF0_DATA4_0x0201160E, MAINT0_MBS_MAINT_BUFF0_DATA_ECC4_0x02011616}}, -// port2/3 - {{MAINT1_MBS_MAINT_BUFF0_DATA0_0x0201170A, MAINT1_MBS_MAINT_BUFF0_DATA_ECC0_0x02011712}, - {MAINT1_MBS_MAINT_BUFF0_DATA4_0x0201170E, MAINT1_MBS_MAINT_BUFF0_DATA_ECC4_0x02011716}}}; - - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_data(64); - ecmdDataBufferBase l_ecc(64); - ecmdDataBufferBase l_mbstr(64); - uint32_t loop = 0; - -// Set bit 9 so that hw will generate the fabric ECC. -// This is an 8B ECC protecting the data moving on internal buses in -// the Centaur. - l_ecmd_rc |= l_ecc.setBit(9); - -// Load unique pattern into both halves of the maint buffer, -// so we can tell which half contains a trapped UE. - l_ecmd_rc |= l_data.insert(0xFACEB00C, 0, 32, 0); - l_ecmd_rc |= l_data.insert(0xD15C0DAD, 32, 32, 0); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - for(loop=0; loop<2; loop++ ) - { - l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][0], l_data); - if(l_rc) return l_rc; - -// A write to MAINT_BUFFx_DATAy will not update until the corresponding -// MAINT_BUFFx_DATA_ECCy is written to. - l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][1], l_ecc); - if(l_rc) return l_rc; - } - - -// Enable UE trapping - l_rc = fapiGetScom(iv_targetCentaur, mss_mbstr[iv_mbaPosition], l_mbstr); - if(l_rc) return l_rc; - l_mbstr.setBit(59); - l_rc = fapiPutScom(iv_targetCentaur, mss_mbstr[iv_mbaPosition], l_mbstr); - if(l_rc) return l_rc; - - - FAPI_INF("EXIT mss_SuperFastRead::ueTrappingSetup()"); - - return l_rc; - } - - - fapi::ReturnCode mss_SuperFastRead::cleanupCmd() - { - - FAPI_INF("ENTER mss_SuperFastRead::cleanupCmd()"); - - fapi::ReturnCode l_rc; - ecmdDataBufferBase l_mbstr(64); - -// Clear maintenance command complete attention, scrub stats, etc... - -// Restore the saved data. -//printf( "Saved data: 0x%08x\n", getSavedData() ); - -// Undo rrq fifo mode - l_rc = fapiPutScom(iv_target, MBA01_MBA_RRQ0Q_0x0301040E, iv_saved_MBA_RRQ0); - if(l_rc) return l_rc; - -// Disable UE trapping - l_rc = fapiGetScom(iv_targetCentaur, mss_mbstr[iv_mbaPosition], l_mbstr); - if(l_rc) return l_rc; - l_mbstr.clearBit(59); - l_rc = fapiPutScom(iv_targetCentaur, mss_mbstr[iv_mbaPosition], l_mbstr); - if(l_rc) return l_rc; - - - FAPI_INF("EXIT mss_SuperFastRead::cleanupCmd()"); - - return l_rc; - } - - - -//------------------------------------------------------------------------------ -// AtomicInject -//------------------------------------------------------------------------------ - - const mss_MaintCmd::CmdType mss_AtomicInject::cv_cmdType = ATOMIC_ALTER_ERROR_INJECT; - -//--------------------------------------------------------- -// AtomicInject Constructor -//--------------------------------------------------------- - - mss_AtomicInject::mss_AtomicInject( const fapi::Target & i_target, - const ecmdDataBufferBase & i_startAddr, - InjectType i_injectType ) : - mss_MaintCmd( i_target, - i_startAddr, - ecmdDataBufferBase(64), // i_endAddr not used for this cmd - NO_STOP_CONDITIONS, // i_stopCondition not used for this cmd - true, // i_poll always true for this cmd - cv_cmdType), - - iv_injectType( i_injectType ) // NOTE: iv_injectType is instance variable -// of AtomicInject, since not needed -// in parent class - {} - - -//--------------------------------------------------------- -// mss_AtomicInject setupAndExecuteCmd -//--------------------------------------------------------- - - fapi::ReturnCode mss_AtomicInject::setupAndExecuteCmd() - { - FAPI_INF("ENTER mss_AtomicInject::setupAndExecuteCmd()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - -// Gather data that needs to be stored. For testing purposes we will just -// set an abitrary number. -//l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; -//printf( "Saved data: 0x%08x\n", getSavedData() ); - -// Make sure maint logic in valid state to run new cmd - l_rc = preConditionCheck(); if(l_rc) return l_rc; - -// Load cmd type: MBMCTQ - l_rc = loadCmdType(); if(l_rc) return l_rc; - -// Load start address: MBMACAQ - l_rc = loadStartAddress(); if(l_rc) return l_rc; - -// Load stop conditions: MBASCTLQ - l_rc = loadStopCondMask(); if(l_rc) return l_rc; - -// Load inject type: MBECTLQ - ecmdDataBufferBase l_mbectl(64); - l_rc = fapiGetScom(iv_target, MBA01_MBECTLQ_0x03010610, l_mbectl); - if(l_rc) return l_rc; - l_ecmd_rc |= l_mbectl.flushTo0(); - l_ecmd_rc |= l_mbectl.setBit(iv_injectType); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(iv_target, MBA01_MBECTLQ_0x03010610, l_mbectl); - if(l_rc) return l_rc; - -// Start the command: MBMCCQ - l_rc = startMaintCmd(); if(l_rc) return l_rc; - -// Check for early problems with maint cmd instead of waiting for -// cmd timeout - l_rc = postConditionCheck(); if(l_rc) return l_rc; - -// Poll for command complete: MBMSRQ - l_rc = pollForMaintCmdComplete(); if(l_rc) return l_rc; - -// Clear inject type: MBECTLQ - l_ecmd_rc |= l_mbectl.flushTo0(); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(iv_target, MBA01_MBECTLQ_0x03010610, l_mbectl); - if(l_rc) return l_rc; - -// Collect FFDC - l_rc = collectFFDC(); if(l_rc) return l_rc; - - - FAPI_INF("EXIT mss_AtomicInject::setupAndExecuteCmd()"); - - - return l_rc; - - } - - -//------------------------------------------------------------------------------ -// Display -//------------------------------------------------------------------------------ - - const mss_MaintCmd::CmdType mss_Display::cv_cmdType = MEMORY_DISPLAY; - -//--------------------------------------------------------- -// Display Constructor -//--------------------------------------------------------- - - mss_Display::mss_Display( const fapi::Target & i_target, - const ecmdDataBufferBase & i_startAddr) : - mss_MaintCmd( i_target, - i_startAddr, - ecmdDataBufferBase(64), // i_endAddr not used for this cmd - NO_STOP_CONDITIONS, // i_stopCondition not used for this cmd - true, // i_poll always true for this cmd - cv_cmdType){} - - -//--------------------------------------------------------- -// mss_Display setupAndExecuteCmd -//--------------------------------------------------------- - - fapi::ReturnCode mss_Display::setupAndExecuteCmd() - { - FAPI_INF("ENTER mss_Display::setupAndExecuteCmd()"); - - fapi::ReturnCode l_rc; - -// Gather data that needs to be stored. For testing purposes we will just -// set an abitrary number. -//l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; -//printf( "Saved data: 0x%08x\n", getSavedData() ); - -// Make sure maint logic in valid state to run new cmd - l_rc = preConditionCheck(); if(l_rc) return l_rc; - -// Load cmd type: MBMCTQ - l_rc = loadCmdType(); if(l_rc) return l_rc; - -// Load start address: MBMACAQ - l_rc = loadStartAddress(); if(l_rc) return l_rc; - -// Load stop conditions: MBASCTLQ - l_rc = loadStopCondMask(); if(l_rc) return l_rc; - -// Start the command: MBMCCQ - l_rc = startMaintCmd(); if(l_rc) return l_rc; - -// Check for early problems with maint cmd instead of waiting for -// cmd timeout - l_rc = postConditionCheck(); if(l_rc) return l_rc; - - if(iv_poll == false) - { - FAPI_INF("Cmd has started. Use attentions to detect cmd complete."); - FAPI_INF("EXIT Display::setupAndExecuteCmd()"); - return l_rc; - } - -// Poll for command complete: MBMSRQ - l_rc = pollForMaintCmdComplete(); if(l_rc) return l_rc; - -// Read the data from the display cmd: MBMSRQ - - static const uint32_t maintBufferReadDataRegs[16]={ -// Port0 beat double word - MAINT0_MBA_MAINT_BUFF0_DATA0_0x03010655, // 0 DW0 - MAINT0_MBA_MAINT_BUFF2_DATA0_0x03010675, // 1 DW2 - MAINT0_MBA_MAINT_BUFF0_DATA1_0x03010656, // 2 DW4 - MAINT0_MBA_MAINT_BUFF2_DATA1_0x03010676, // 3 DW6 - MAINT0_MBA_MAINT_BUFF0_DATA2_0x03010657, // 4 DW8 - MAINT0_MBA_MAINT_BUFF2_DATA2_0x03010677, // 5 DW10 - MAINT0_MBA_MAINT_BUFF0_DATA3_0x03010658, // 6 DW12 - MAINT0_MBA_MAINT_BUFF2_DATA3_0x03010678, // 7 DW14 - -// Port1 - MAINT0_MBA_MAINT_BUFF1_DATA0_0x03010665, // 0 DW1 - MAINT0_MBA_MAINT_BUFF3_DATA0_0x03010685, // 1 DW3 - MAINT0_MBA_MAINT_BUFF1_DATA1_0x03010666, // 2 DW5 - MAINT0_MBA_MAINT_BUFF3_DATA1_0x03010686, // 3 DW7 - MAINT0_MBA_MAINT_BUFF1_DATA2_0x03010667, // 4 DW9 - MAINT0_MBA_MAINT_BUFF3_DATA2_0x03010687, // 5 DW11 - MAINT0_MBA_MAINT_BUFF1_DATA3_0x03010668, // 6 DW13 - MAINT0_MBA_MAINT_BUFF3_DATA3_0x03010688};// 7 DW15 - - - static const uint32_t maintBufferRead65thByteRegs[4]={ - MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC0_0x03010695, - MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC1_0x03010696, - MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC2_0x03010697, - MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC3_0x03010698}; - - - uint32_t loop = 0; - ecmdDataBufferBase l_data(64); - -//---------------------------------------------------- -// Read the data: 16 loops x 64bits = 128B cacheline -//---------------------------------------------------- - FAPI_ERR("Read the data: 16 loops x 64bits = 128B cacheline"); - - for(loop=0; loop<16; loop++ ) - { - l_rc = fapiGetScom(iv_target, maintBufferReadDataRegs[loop], l_data); - if(l_rc) return l_rc; - FAPI_ERR("0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - } - -//---------------------------------------------------- -// Read the 65th byte: 4 loops -//---------------------------------------------------- - FAPI_ERR("Read the 65th byte and ECC bits: 4 loops"); - - for(loop=0; loop<4; loop++ ) - { - l_rc = fapiGetScom(iv_target, maintBufferRead65thByteRegs[loop], l_data); - if(l_rc) return l_rc; - FAPI_ERR("0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - } - -// Collect FFDC - l_rc = collectFFDC(); if(l_rc) return l_rc; - - FAPI_INF("EXIT Display::setupAndExecuteCmd()"); - - return l_rc; - - } - - -//------------------------------------------------------------------------------ -// Increment MBMACA Address -//------------------------------------------------------------------------------ - - const mss_MaintCmd::CmdType mss_IncrementAddress::cv_cmdType = INCREMENT_MBMACA_ADDRESS; - -//--------------------------------------------------------- -// IncrementAddress Constructor -//--------------------------------------------------------- - - mss_IncrementAddress::mss_IncrementAddress( const fapi::Target & i_target ): - - mss_MaintCmd( i_target, - ecmdDataBufferBase(64), // i_startAddr not used for this cmd - ecmdDataBufferBase(64), // i_endAddr not used for this cmd - NO_STOP_CONDITIONS, // i_stopCondition not used for this cmd - true, // i_poll always true for this cmd - cv_cmdType){} - -//--------------------------------------------------------- -// mss_IncrementAddress setupAndExecuteCmd -//--------------------------------------------------------- - - fapi::ReturnCode mss_IncrementAddress::setupAndExecuteCmd() - { - - - FAPI_INF("ENTER mss_IncrementAddress::setupAndExecuteCmd()"); - - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_mbspa_mask(64); - ecmdDataBufferBase l_mbspa_mask_original(64); - ecmdDataBufferBase l_mbspa_and(64); - -// Read MBSPA MASK - l_rc = fapiGetScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask); - if(l_rc) return l_rc; - -// Save original mask value so we can restore it when done - l_ecmd_rc |= l_mbspa_mask_original.insert(l_mbspa_mask, 0, 64, 0); - -// Mask bits 0 and 8, to hide the special attentions when the cmd completes - l_ecmd_rc |= l_mbspa_mask.setBit(0); - l_ecmd_rc |= l_mbspa_mask.setBit(8); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - -// Write MBSPA MASK - l_rc = fapiPutScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask); - if(l_rc) return l_rc; - -// Make sure maint logic in valid state to run new cmd - l_rc = preConditionCheck(); if(l_rc) return l_rc; - -// Load cmd type: MBMCTQ - l_rc = loadCmdType(); if(l_rc) return l_rc; - -// Read start address: MBMACAQ - ecmdDataBufferBase l_mbmacaq(64); - l_rc = fapiGetScom(iv_target, MBA01_MBMACAQ_0x0301060D, l_mbmacaq); - if(l_rc) return l_rc; - FAPI_INF("MBMACAQ = 0x%.8X 0x%.8X", l_mbmacaq.getWord(0), l_mbmacaq.getWord(1)); - -// Start the command: MBMCCQ - l_rc = startMaintCmd(); if(l_rc) return l_rc; - -// Check for early problems with maint cmd instead of waiting for -// cmd timeout - l_rc = postConditionCheck(); if(l_rc) return l_rc; - -// Poll for command complete: MBMSRQ - l_rc = pollForMaintCmdComplete(); if(l_rc) return l_rc; - -// Read incremented start address: MBMACAQ - l_rc = fapiGetScom(iv_target, MBA01_MBMACAQ_0x0301060D, l_mbmacaq); - if(l_rc) return l_rc; - - -// Clear bits 0 and 8 in MBSPA AND register - l_ecmd_rc |= l_mbspa_and.flushTo1(); - l_ecmd_rc |= l_mbspa_and.clearBit(0); - l_ecmd_rc |= l_mbspa_and.clearBit(8); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - -// Write MPSPA AND register - l_rc = fapiPutScom(iv_target, MBA01_MBSPAQ_AND_0x03010612, l_mbspa_and); - if(l_rc) return l_rc; - -// Restore MBSPA MASK - l_rc = fapiPutScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask_original); - if(l_rc) return l_rc; - - - FAPI_INF("EXIT mss_IncrementAddress::setupAndExecuteCmd()"); - - return l_rc; - } - - -//------------------------------------------------------------------------------ -// mss_TimeBaseScrub -//------------------------------------------------------------------------------ - - const mss_MaintCmd::CmdType mss_TimeBaseScrub::cv_cmdType = TIMEBASE_SCRUB; - -//--------------------------------------------------------- -// mss_TimeBaseScrub Constructor -//--------------------------------------------------------- - - mss_TimeBaseScrub::mss_TimeBaseScrub( const fapi::Target & i_target, - const ecmdDataBufferBase & i_startAddr, - const ecmdDataBufferBase & i_endAddr, - TimeBaseSpeed i_speed, - uint32_t i_stopCondition, - bool i_poll ) : - mss_MaintCmd( i_target, - i_startAddr, - i_endAddr, - i_stopCondition, - i_poll, - cv_cmdType), - -// NOTE: iv_speed is instance variable of TimeBaseScrub, since not -// needed in parent class - iv_speed( i_speed ) - {} - - - -//--------------------------------------------------------- -// mss_TimeBaseScrub setupAndExecuteCmd -//--------------------------------------------------------- - - fapi::ReturnCode mss_TimeBaseScrub::setupAndExecuteCmd() - { - FAPI_INF("ENTER mss_TimeBaseScrub::setupAndExecuteCmd()"); - - fapi::ReturnCode l_rc; - -// Gather data that needs to be stored. For testing purposes we will just -// set an abitrary number. -//l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; -//printf( "Saved data: 0x%08x\n", getSavedData() ); - -// Make sure maint logic in valid state to run new cmd - l_rc = preConditionCheck(); if(l_rc) return l_rc; - -// Load cmd type: MBMCTQ - l_rc = loadCmdType(); if(l_rc) return l_rc; - -// Load start address: MBMACAQ - l_rc = loadStartAddress(); if(l_rc) return l_rc; - -// Load end address: MBMEAQ - l_rc = loadEndAddress(); if(l_rc) return l_rc; - -// Load speed: MBMCTQ - l_rc = loadSpeed(iv_speed); if(l_rc) return l_rc; - -// Load stop conditions: MBASCTLQ - l_rc = loadStopCondMask(); if(l_rc) return l_rc; - -// Start the command: MBMCCQ - l_rc = startMaintCmd(); if(l_rc) return l_rc; - -// Check for early problems with maint cmd instead of waiting for -// cmd timeout - l_rc = postConditionCheck(); if(l_rc) return l_rc; - - if(iv_poll == false) - { - FAPI_INF("Cmd has started. Use attentions to detect cmd complete."); - FAPI_INF("EXIT mss_TimeBaseScrub::setupAndExecuteCmd()"); - return l_rc; - } - -// Poll for command complete: MBMSRQ - l_rc = pollForMaintCmdComplete(); if(l_rc) return l_rc; - -// Collect FFDC - l_rc = collectFFDC(); if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_TimeBaseScrub::setupAndExecuteCmd()"); - - return l_rc; - - } - - -//------------------------------------------------------------------------------ -// mss_TimeBaseSteerCleanup -//------------------------------------------------------------------------------ - - const mss_MaintCmd::CmdType mss_TimeBaseSteerCleanup::cv_cmdType = TIMEBASE_STEER_CLEANUP; - -//--------------------------------------------------------- -// mss_TimeBaseSteerCleanup Constructor -//--------------------------------------------------------- - - mss_TimeBaseSteerCleanup::mss_TimeBaseSteerCleanup( const fapi::Target & i_target, - const ecmdDataBufferBase & i_startAddr, - const ecmdDataBufferBase & i_endAddr, - TimeBaseSpeed i_speed, - uint32_t i_stopCondition, - bool i_poll ) : - mss_MaintCmd( i_target, - i_startAddr, - i_endAddr, - i_stopCondition, - i_poll, - cv_cmdType), - -// NOTE: iv_speed is instance variable of TimeBaseSteerCleanup, since not -// needed in parent class - iv_speed( i_speed ) - {} - - - -//--------------------------------------------------------- -// mss_TimeBaseSteerCleanup setupAndExecuteCmd -//--------------------------------------------------------- - - fapi::ReturnCode mss_TimeBaseSteerCleanup::setupAndExecuteCmd() - { - FAPI_INF("ENTER mss_TimeBaseSteerCleanup::setupAndExecuteCmd()"); - - fapi::ReturnCode l_rc; - -// Gather data that needs to be stored. For testing purposes we will just -// set an abitrary number. -//l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; -//printf( "Saved data: 0x%08x\n", getSavedData() ); - -// Make sure maint logic in valid state to run new cmd - l_rc = preConditionCheck(); if(l_rc) return l_rc; - -// Load cmd type: MBMCTQ - l_rc = loadCmdType(); if(l_rc) return l_rc; - -// Load start address: MBMACAQ - l_rc = loadStartAddress(); if(l_rc) return l_rc; - -// Load end address: MBMEAQ - l_rc = loadEndAddress(); if(l_rc) return l_rc; - -// Load speed: MBMCTQ - l_rc = loadSpeed(iv_speed); if(l_rc) return l_rc; - -// Load stop conditions: MBASCTLQ - l_rc = loadStopCondMask(); if(l_rc) return l_rc; - -// Start the command: MBMCCQ - l_rc = startMaintCmd(); if(l_rc) return l_rc; - -// Check for early problems with maint cmd instead of waiting for -// cmd timeout - l_rc = postConditionCheck(); if(l_rc) return l_rc; - - if(iv_poll == false) - { - FAPI_INF("Cmd has started. Use attentions to detect cmd complete."); - FAPI_INF("EXIT mss_TimeBaseSteerCleanup::setupAndExecuteCmd()"); - return l_rc; - } - -// Poll for command complete: MBMSRQ - l_rc = pollForMaintCmdComplete(); if(l_rc) return l_rc; - -// Collect FFDC - l_rc = collectFFDC(); if(l_rc) return l_rc; - - FAPI_INF("EXIT mss_TimeBaseSteerCleanup::setupAndExecuteCmd()"); - - return l_rc; - - } - - - -//------------------------------------------------------------------------------ -// Utility funcitons -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// mss_get_address_range -//------------------------------------------------------------------------------ - fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, - uint8_t i_rank, - ecmdDataBufferBase & o_startAddr, - ecmdDataBufferBase & o_endAddr ) - { - - - FAPI_INF("ENTER mss_get_address_range()"); - - static const uint8_t memConfigType[9][4][2]={ - -// Refer to Centaur Workbook: 5.2 Master and Slave Rank Usage -// -// SUBTYPE_A SUBTYPE_B SUBTYPE_C SUBTYPE_D -// -//SLOT_0_ONLY SLOT_0_AND_1 SLOT_0_ONLY SLOT_0_AND_1 SLOT_0_ONLY SLOT_0_AND_1 SLOT_0_ONLY SLOT_0_AND_1 -// -//master slave master slave master slave master slave master slave master slave master slave master slave -// - {{0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff}}, // TYPE_0 - {{0x00, 0x40}, {0x10, 0x50}, {0x30, 0x70}, {0xff, 0xff}}, // TYPE_1 - {{0x01, 0x41}, {0x03, 0x43}, {0x07, 0x47}, {0xff, 0xff}}, // TYPE_2 - {{0x11, 0x51}, {0x13, 0x53}, {0x17, 0x57}, {0xff, 0xff}}, // TYPE_3 - {{0x31, 0x71}, {0x33, 0x73}, {0x37, 0x77}, {0xff, 0xff}}, // TYPE_4 - {{0x00, 0x40}, {0x10, 0x50}, {0x30, 0x70}, {0xff, 0xff}}, // TYPE_5 - {{0x01, 0x41}, {0x03, 0x43}, {0x07, 0x47}, {0xff, 0xff}}, // TYPE_6 - {{0x11, 0x51}, {0x13, 0x53}, {0x17, 0x57}, {0xff, 0xff}}, // TYPE_7 - {{0x31, 0x71}, {0x33, 0x73}, {0x37, 0x77}, {0xff, 0xff}}}; // TYPE_8 - - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_data(64); - mss_MemConfig::MemOrg l_row; - mss_MemConfig::MemOrg l_col; - mss_MemConfig::MemOrg l_bank; - uint32_t l_dramSize = 0; - uint8_t l_dramWidth = 0; - fapi::Target l_targetCentaur; - uint8_t l_mbaPosition = 0; - uint8_t l_isSIM = 1; - - uint8_t l_slotConfig = 0; - uint8_t l_configType = 0; - uint8_t l_configSubType = 0; - uint8_t l_end_master_rank = 0; - uint8_t l_end_slave_rank = 0; - uint8_t l_dram_gen; - -// Get Centaur target for the given MBA - l_rc = fapiGetParentChip(i_target, l_targetCentaur); - if(l_rc) - { - FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",i_target.toEcmdString()); - return l_rc; - } - -// Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); - return l_rc; - } - -// Check system attribute if sim: 1 = Awan/HWSimulator. 0 = Simics/RealHW. - l_rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, l_isSIM); - if(l_rc) - { - FAPI_ERR("Error getting ATTR_IS_SIMULATION on %s.",i_target.toEcmdString()); - return l_rc; - } - -// Get l_dramWidth - l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); - if(l_rc) - { - FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); - return l_rc; - } - -// Get DDR3/DDR4: ATTR_EFF_DRAM_GEN -// 0x01 = ENUM_ATTR_EFF_DRAM_GEN_DDR3 -// 0x02 = ENUM_ATTR_EFF_DRAM_GEN_DDR4 - l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, l_dram_gen); - if(l_rc) - { - FAPI_ERR("Error getting DDR3/DDR4 on %s.",i_target.toEcmdString()); - return l_rc; - } - -// Check MBAXCRn, to show memory configured behind this MBA - l_rc = fapiGetScom(l_targetCentaur, mss_mbaxcr[l_mbaPosition], l_data); - if(l_rc) return l_rc; - if (l_data.isBitClear(0,4)) - { - FAPI_ERR("MBAXCRn[0:3] = 0, meaning no memory configured behind this MBA on %s.",i_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = i_target; -// FFDC: Capture register we are checking - ecmdDataBufferBase & MBAXCR = l_data; - -// Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_MEM_CNFG); - return l_rc; - } - -//******************************************************************** -// Find max row/col/bank, based on l_dramSize and l_dramWidth -//******************************************************************** - -// Get l_dramSize - l_ecmd_rc |= l_data.extractPreserve(&l_dramSize, 6, 2, 32-2); // (6:7) - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_2) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) - { -// For memory part Size = 256Mbx8 (2Gb), row/col/bank = 15/10/3 - FAPI_INF("For memory part Size = 256Mbx8 (2Gb), row/col/bank = 15/10/3, DDR3"); - l_row = mss_MemConfig::ROW_15; - l_col = mss_MemConfig::COL_10; - l_bank = mss_MemConfig::BANK_3; - } - - else if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_2) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)) - { -// For memory part Size = 256Mbx8 (2Gb), row/col/bank = 14/10/4 - FAPI_INF("For memory part Size = 256Mbx8 (2Gb), row/col/bank = 14/10/4, DDR4"); - l_row = mss_MemConfig::ROW_14; - l_col = mss_MemConfig::COL_10; - l_bank = mss_MemConfig::BANK_4; - } - - else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_2) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) - { -// For memory part Size = 512Mbx4 (2Gb), row/col/bank = 15/11/3 - FAPI_INF("For memory part Size = 512Mbx4 (2Gb), row/col/bank = 15/11/3, DDR3"); - l_row = mss_MemConfig::ROW_15; - l_col = mss_MemConfig::COL_11; - l_bank = mss_MemConfig::BANK_3; - } - - else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_2) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)) - { -// For memory part Size = 512Mbx4 (2Gb), row/col/bank = 15/10/4 - FAPI_INF("For memory part Size = 512Mbx4 (2Gb), row/col/bank = 15/10/4, DDR4"); - l_row = mss_MemConfig::ROW_15; - l_col = mss_MemConfig::COL_10; - l_bank = mss_MemConfig::BANK_4; - } - - else if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_4) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) - { -// For memory part Size = 512Mbx8 (4Gb), row/col/bank = 16/10/3 - FAPI_INF("For memory part Size = 512Mbx8 (4Gb), row/col/bank = 16/10/3, DDR3"); - l_row = mss_MemConfig::ROW_16; - l_col = mss_MemConfig::COL_10; - l_bank = mss_MemConfig::BANK_3; - } - - else if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_4) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)) - { -// For memory part Size = 512Mbx8 (4Gb), row/col/bank = 14/10/4 - FAPI_INF("For memory part Size = 512Mbx8 (4Gb), row/col/bank = 14/10/4, DDR4"); - l_row = mss_MemConfig::ROW_15; - l_col = mss_MemConfig::COL_10; - l_bank = mss_MemConfig::BANK_4; - } - - - else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_4) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) - { -// For memory part Size = 1Gbx4 (4Gb), row/col/bank = 16/11/3 - FAPI_INF("For memory part Size = 1Gbx4 (4Gb), row/col/bank = 16/11/3, DDR3"); - l_row = mss_MemConfig::ROW_16; - l_col = mss_MemConfig::COL_11; - l_bank = mss_MemConfig::BANK_3; - } - - else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_4) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)) - { -// For memory part Size = 1Gbx4 (4Gb), row/col/bank = 16/10/4 - FAPI_INF("For memory part Size = 1Gbx4 (4Gb), row/col/bank = 16/10/4, DDR4"); - l_row = mss_MemConfig::ROW_16; - l_col = mss_MemConfig::COL_10; - l_bank = mss_MemConfig::BANK_4; - } - - else if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_8) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) - { -// For memory part Size = 1Gbx8 (8Gb), row/col/bank = 16/11/3 - FAPI_INF("For memory part Size = 1Gbx8 (8Gb), row/col/bank = 16/11/3, DDR3"); - l_row = mss_MemConfig::ROW_16; - l_col = mss_MemConfig::COL_11; - l_bank = mss_MemConfig::BANK_3; - } - - else if((l_dramWidth == mss_MemConfig::X8) && (l_dramSize == mss_MemConfig::GBIT_8) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)) - { -// For memory part Size = 1Gbx8 (8Gb), row/col/bank = 16/10/4 - FAPI_INF("For memory part Size = 1Gbx8 (8Gb), row/col/bank = 16/10/4, DDR4"); - l_row = mss_MemConfig::ROW_16; - l_col = mss_MemConfig::COL_10; - l_bank = mss_MemConfig::BANK_4; - } - - - else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_8) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) - { -// For memory part Size = 2Gbx4 (8Gb), row/col/bank = 16/12/3 - FAPI_INF("For memory part Size = 2Gbx4 (8Gb), row/col/bank = 16/12/3, DDR3"); - l_row = mss_MemConfig::ROW_16; - l_col = mss_MemConfig::COL_12; - l_bank = mss_MemConfig::BANK_3; - } - - else if((l_dramWidth == mss_MemConfig::X4) && (l_dramSize == mss_MemConfig::GBIT_8) && (l_dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)) - { -// For memory part Size = 2Gbx4 (8Gb), row/col/bank = 17/10/4 - FAPI_INF("Forosr memory part Size = 2Gbx4 (8Gb), row/col/bank = 17/10/4, DDR4"); - l_row = mss_MemConfig::ROW_17; - l_col = mss_MemConfig::COL_10; - l_bank = mss_MemConfig::BANK_4; - } - else - { - FAPI_ERR("Invalid l_dramSize = %d or l_dramWidth = %d in MBAXCRn, or l_dram_gen = %d on %s.", - l_dramSize, l_dramWidth, l_dram_gen, i_target.toEcmdString()); - - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = i_target; -// FFDC: Capture register we are checking - ecmdDataBufferBase & MBAXCR = l_data; -// FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; -// FFDC: DRAM width - uint8_t DRAM_GEN = l_dram_gen; -// Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH); - return l_rc; - } - - -//******************************************************************** -// Find l_end_master_rank and l_end_slave_rank based on DIMM configuration -//******************************************************************** - -// (0:3) Configuration type (1-8) - l_ecmd_rc |= l_data.extractPreserve(&l_configType, 0, 4, 8-4); - -// (4:5) Configuration subtype (A, B, C, D) - l_ecmd_rc |= l_data.extractPreserve(&l_configSubType, 4, 2, 8-2); - -// (8) Slot Configuration -// 0 = Centaur DIMM or IS DIMM, slot0 only, 1 = IS DIMM slots 0 and 1 - l_ecmd_rc |= l_data.extractPreserve(&l_slotConfig, 8, 1, 8-1); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - - FAPI_INF("memConfigType[%d][%d][%d] = 0x%02x", - l_configType,l_configSubType,l_slotConfig, - memConfigType[l_configType][l_configSubType][l_slotConfig]); - - l_end_master_rank = (memConfigType[l_configType][l_configSubType][l_slotConfig] & 0xf0) >> 4; - l_end_slave_rank = memConfigType[l_configType][l_configSubType][l_slotConfig] & 0x0f; - - FAPI_INF("end master rank = %d, end slave rank = %d", l_end_master_rank, l_end_slave_rank); - - if ((l_end_master_rank == 0x0f) || (l_end_slave_rank == 0x0f)) - { - FAPI_ERR("MBAXCRn configured with unsupported combination of l_configType, l_configSubType, l_slotConfig on %s.",i_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = i_target; -// FFDC: Capture register we are checking - ecmdDataBufferBase & MBAXCR = l_data; - -// Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_DIMM_CNFG); - return l_rc; - } - -//******************************************************************** -// Get address range for all ranks configured behind this MBA -//******************************************************************** - if (i_rank == MSS_ALL_RANKS) - { - FAPI_INF("Get address range for rank = ALL_RANKS"); - -// Start address is just rank 0 with row/col/bank all 0's - o_startAddr.flushTo0(); - -// If Awan/HWSimulator, end address is just start address +3 - if (l_isSIM) - { - FAPI_INF("ATTR_IS_SIMULATION = 1, Awan/HWSimulator, so use smaller address range."); - - -// Do only rank0, row0, all banks all cols - l_end_master_rank = 0; - l_end_slave_rank = 0; - - uint32_t l_row_zero = 0; - l_ecmd_rc |= o_endAddr.flushTo0(); - -// MASTER RANK = 0:3 - l_ecmd_rc |= o_endAddr.insert( l_end_master_rank, 0, 4, 8-4 ); - -// SLAVE RANK = 4:6 - l_ecmd_rc |= o_endAddr.insert( l_end_slave_rank, 4, 3, 8-3 ); - -// BANK = 7:10 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_bank, 7, 4, 32-4 ); - -// ROW = 11:27 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_row_zero, 11, 17, 32-17 ); - -// COL = 28:39, note: c2, c1, c0 always 0 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_col, 28, 12, 32-12 ); - - - } -// Else, set end address to be last address of l_end_master_rank - else - { - l_ecmd_rc |= o_endAddr.flushTo0(); - -// MASTER RANK = 0:3 - l_ecmd_rc |= o_endAddr.insert( l_end_master_rank, 0, 4, 8-4 ); - -// SLAVE RANK = 4:6 - l_ecmd_rc |= o_endAddr.insert( l_end_slave_rank, 4, 3, 8-3 ); - -// BANK = 7:10 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_bank, 7, 4, 32-4 ); - -// ROW = 11:27 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_row, 11, 17, 32-17 ); - -// COL = 28:39, note: c2, c1, c0 always 0 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_col, 28, 12, 32-12 ); - } - } - -//******************************************************************** -// Get address range for single rank configured behind this MBA -//******************************************************************** - else - { - FAPI_INF("Get address range for master rank = %d\n", i_rank ); - -// Check for i_rank out of range - if (i_rank>=8) - { - FAPI_ERR("i_rank input to mss_get_address_range out of range on %s.",i_target.toEcmdString()); -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = i_target; -// FFDC: Capture i_rank; - uint8_t RANK = i_rank; - -// Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_GET_ADDRESS_RANGE_BAD_INPUT); - return l_rc; - } - -// NOTE: If this rank is not valid, we should see MBAFIR[1]: invalid -// maint address, when cmd started - -// Start address is just i_rank with row/col/bank all 0's - l_ecmd_rc |= o_startAddr.flushTo0(); - -// MASTER RANK = 0:3 - l_ecmd_rc |= o_startAddr.insert( i_rank, 0, 4, 8-4 ); - -// If Awan/HWSimulator, end address is just start address +3 - if (l_isSIM) - { - FAPI_INF("ATTR_IS_SIMULATION = 1, Awan/HWSimulator, so use smaller address range."); - - l_end_slave_rank = 0; - - uint32_t l_row_zero = 0; - l_ecmd_rc |= o_endAddr.flushTo0(); -// MASTER RANK = 0:3 - l_ecmd_rc |= o_endAddr.insert( i_rank, 0, 4, 8-4 ); - -// SLAVE RANK = 4:6 - l_ecmd_rc |= o_endAddr.insert( l_end_slave_rank, 4, 3, 8-3 ); - -// BANK = 7:10 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_bank, 7, 4, 32-4 ); -// ROW = 11:27 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_row_zero, 11, 17, 32-17 ); -// COL = 28:39, note: c2, c1, c0 always 0 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_col, 28, 12, 32-12 ); - - } -// Else, set end address to be last address of i_rank - else - { - l_ecmd_rc |= o_endAddr.flushTo0(); -// MASTER RANK = 0:3 - l_ecmd_rc |= o_endAddr.insert( i_rank, 0, 4, 8-4 ); - -// SLAVE RANK = 4:6 - l_ecmd_rc |= o_endAddr.insert( l_end_slave_rank, 4, 3, 8-3 ); - -// BANK = 7:10 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_bank, 7, 4, 32-4 ); -// ROW = 11:27 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_row, 11, 17, 32-17 ); -// COL = 28:36 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_col, 28, 12, 32-12 ); - } - - } - - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - - - FAPI_INF("EXIT mss_get_address_range()"); - - return l_rc; - } - -//------------------------------------------------------------------------------ -// mss_get_slave_address_range -//------------------------------------------------------------------------------ - fapi::ReturnCode mss_get_slave_address_range( const fapi::Target & i_target, - uint8_t i_master, - uint8_t i_slave, - ecmdDataBufferBase & o_startAddr, - ecmdDataBufferBase & o_endAddr ) - { - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - FAPI_INF("ENTER mss_get_slave_address_range()"); - mss_get_address_range(i_target,i_master,o_startAddr,o_endAddr); - //START SLAVE RANK = 4:6 - l_ecmd_rc |= o_startAddr.insert( i_slave, 4, 3, 8-3 ); - //END SLAVE RANK = 4:6 - l_ecmd_rc |= o_endAddr.insert( i_slave, 4, 3, 8-3 ); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - FAPI_INF("EXIT mss_get_slave_address_range()"); - - return l_rc; - } - -//------------------------------------------------------------------------------ -// mss_get_mark_store -//------------------------------------------------------------------------------ - fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, - uint8_t i_rank, - uint8_t & o_symbolMark, - uint8_t & o_chipMark ) - { - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_markstore(64); - ecmdDataBufferBase l_mbeccfir(64); - ecmdDataBufferBase l_data(64); - uint8_t l_dramWidth = 0; - uint8_t l_symbolMarkGalois = 0; - uint8_t l_chipMarkGalois = 0; - uint8_t l_symbolsPerChip = 4; - fapi::Target l_targetCentaur; - uint8_t l_mbaPosition = 0; - ecmdDataBufferBase l_mbscfg(64); - uint8_t l_dd2_enable_exit_point_1 = 0; - - o_symbolMark = MSS_INVALID_SYMBOL; - o_chipMark = MSS_INVALID_SYMBOL; - - // Get Centaur target for the given MBA - l_rc = fapiGetParentChip(i_target, l_targetCentaur); - if(l_rc) - { - FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",i_target.toEcmdString()); - return l_rc; - } - - - // Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Get l_dramWidth - l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); - if(l_rc) - { - FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Check for i_rank out of range - if (i_rank>=8) - { - FAPI_ERR("i_rank input to mss_get_mark_store out of range on %s.",i_target.toEcmdString()); - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: Capture i_rank; - uint8_t RANK = i_rank; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_GET_MARK_STORE_BAD_INPUT); - return l_rc; - } - - // Read markstore register for the given rank - l_rc = fapiGetScom(l_targetCentaur, mss_markStoreRegs[i_rank][l_mbaPosition], l_markstore); - if(l_rc) return l_rc; - - // If MPE FIR for the given rank (scrub or fetch) is on after the read, - // we will read one more time just to make sure we get latest. - l_rc = fapiGetScom(l_targetCentaur, mss_mbeccfir[l_mbaPosition], l_mbeccfir); - if(l_rc) return l_rc; - if (l_mbeccfir.isBitSet(i_rank) || l_mbeccfir.isBitSet(20 + i_rank)) - { - l_rc = fapiGetScom(l_targetCentaur, mss_markStoreRegs[i_rank][l_mbaPosition], l_markstore); - if(l_rc) return l_rc; - } - - // Get l_symbolMarkGalois - l_ecmd_rc |= l_markstore.extractPreserve(&l_symbolMarkGalois, 0, 8, 8-8); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - if (l_symbolMarkGalois == 0x00) // No symbol mark - { - o_symbolMark = MSS_INVALID_SYMBOL; - } - else if (l_dramWidth == mss_MemConfig::X4) - { - FAPI_ERR("l_symbolMarkGalois invalid: symbol mark not allowed in x4 mode on %s.",i_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; - // FFDC: Capure i_rank; - uint8_t RANK = i_rank; - // FFDC: Capture markstore - ecmdDataBufferBase & MARKSTORE = l_markstore; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_X4_SYMBOL_ON_READ); - return l_rc; - } - else // Converted from galois field to symbol index - { - o_symbolMark = MSS_SYMBOLS_PER_RANK; - for ( uint32_t i = 0; i < MSS_SYMBOLS_PER_RANK; i++ ) - { - if ( l_symbolMarkGalois == mss_symbol2Galois[i] ) - { - o_symbolMark = i; - break; - } - } - - if ( MSS_SYMBOLS_PER_RANK <= o_symbolMark ) - { - FAPI_ERR("Invalid galois field in markstore on %s.",i_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; - // FFDC: Capure i_rank; - uint8_t RANK = i_rank; - // FFDC: Capture markstore - ecmdDataBufferBase & MARKSTORE = l_markstore; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_MARKSTORE); - return l_rc; - } - } - - // Get l_chipMarkGalois - l_ecmd_rc |= l_markstore.extractPreserve(&l_chipMarkGalois, 8, 8, 8-8); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - - if (l_chipMarkGalois == 0x00) // No chip mark - { - o_chipMark = MSS_INVALID_SYMBOL; - } - else // Converted from galois field to chip index - { - - if (l_dramWidth == mss_MemConfig::X4) - { - l_symbolsPerChip = 2; - } - else if (l_dramWidth == mss_MemConfig::X8) - { - l_symbolsPerChip = 4; - } - - o_chipMark = MSS_SYMBOLS_PER_RANK; - for ( uint32_t i = 0; i < MSS_SYMBOLS_PER_RANK; i=i+l_symbolsPerChip) - { - if ( l_chipMarkGalois == mss_symbol2Galois[i] ) - { - o_chipMark = i; - break; - } - } - // TODO: create error if x4 mode and symbol 0,1? - - if ( MSS_SYMBOLS_PER_RANK <= o_chipMark ) - { - FAPI_ERR("Invalid galois field in markstore on %s.",i_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; - // FFDC: Capure i_rank; - uint8_t RANK = i_rank; - // FFDC: Capture markstore - ecmdDataBufferBase & MARKSTORE = l_markstore; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_MARKSTORE); - return l_rc; - } - } - - - // Get attribute that tells we have cen DD2, and can enable exit poing 1 - l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_DD2_ENABLE_EXIT_POINT_1, &i_target, l_dd2_enable_exit_point_1); - if(l_rc) - { - FAPI_ERR("Error getting ATTR_CENTAUR_EC_DD2_ENABLE_EXIT_POINT_1"); - return l_rc; - } - - if(l_dd2_enable_exit_point_1) - { - // If valid chip or symbol mark, enable exit point 1 - if ((o_chipMark != MSS_INVALID_SYMBOL) || (o_symbolMark != MSS_INVALID_SYMBOL)) - { - - // Read MBSCFGQ - l_rc = fapiGetScom(l_targetCentaur, MBSCFGQ_0x02011411, l_mbscfg); - if(l_rc) return l_rc; - - l_ecmd_rc |= l_mbscfg.setBit(0); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write MBSCFGQ - l_rc = fapiPutScom(l_targetCentaur, MBSCFGQ_0x02011411, l_mbscfg); - if(l_rc) return l_rc; - } - } - - - FAPI_INF("mss_get_mark_store(): rank%d, chip mark = %d, symbol mark = %d", - i_rank, o_chipMark, o_symbolMark ); - - return l_rc; - } - - - -//------------------------------------------------------------------------------ -// mss_put_mark_store -//------------------------------------------------------------------------------ - fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, - uint8_t i_rank, - uint8_t i_symbolMark, - uint8_t i_chipMark ) - { - - FAPI_INF("ENTER mss_put_mark_store()"); - - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_markstore(64); - ecmdDataBufferBase l_mbeccfir(64); - ecmdDataBufferBase l_data(64); - uint8_t l_dramWidth = 0; - uint8_t l_symbolMarkGalois = 0; - uint8_t l_chipMarkGalois = 0; - fapi::Target l_targetCentaur; - uint8_t l_mbaPosition = 0; - uint8_t l_rank_index = 0; - bool l_exit_point_1_needed = false; - ecmdDataBufferBase l_mbscfg(64); - uint8_t l_dd2_enable_exit_point_1 = 0; - - - // Get Centaur target for the given MBA - l_rc = fapiGetParentChip(i_target, l_targetCentaur); - if(l_rc) - { - FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",i_target.toEcmdString()); - return l_rc; - } - - - // Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); - return l_rc; - } - - - // Get l_dramWidth - l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); - if(l_rc) - { - FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Check for i_rank out of range - if (i_rank>=8) - { - FAPI_ERR("i_rank input to mss_put_mark_store out of range on %s.",i_target.toEcmdString()); - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: Capture i_rank; - uint8_t RANK = i_rank; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_PUT_MARK_STORE_BAD_INPUT); - return l_rc; - } - - // Get l_symbolMarkGalois - if (i_symbolMark == MSS_INVALID_SYMBOL) // No symbol mark - { - l_symbolMarkGalois = 0x00; - } - else if ( l_dramWidth == mss_MemConfig::X4 ) - { - FAPI_ERR("i_symbolMark invalid: symbol mark not allowed in x4 mode on %s.",i_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; - // FFDC: Capure i_rank; - uint8_t RANK = i_rank; - // FFDC: Capure i_symbolMark; - uint8_t SYMBOL_MARK = i_symbolMark; - // FFDC: Capure i_chipMark; - uint8_t CHIP_MARK = i_chipMark; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_X4_SYMBOL_ON_WRITE); - return l_rc; - } - else if ( MSS_SYMBOLS_PER_RANK <= i_symbolMark ) - { - FAPI_ERR("i_symbolMark invalid: symbol index out of range on %s.",i_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; - // FFDC: Capure i_rank; - uint8_t RANK = i_rank; - // FFDC: Capure i_symbolMark; - uint8_t SYMBOL_MARK = i_symbolMark; - // FFDC: Capure i_chipMark; - uint8_t CHIP_MARK = i_chipMark; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_INDEX); - return l_rc; - } - else // Convert from symbol index to galois field - { - l_symbolMarkGalois = mss_symbol2Galois[i_symbolMark]; - } - l_ecmd_rc |= l_markstore.insert( l_symbolMarkGalois, 0, 8, 0 ); - - - // Get l_chipMarkGalois - if (i_chipMark == MSS_INVALID_SYMBOL) // No chip mark - { - l_chipMarkGalois = 0x00; - } - else if ( MSS_SYMBOLS_PER_RANK <= i_chipMark ) - { - FAPI_ERR("i_chipMark invalid: symbol index out of range on %s.",i_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; - // FFDC: Capure i_rank; - uint8_t RANK = i_rank; - // FFDC: Capure i_symbolMark; - uint8_t SYMBOL_MARK = i_symbolMark; - // FFDC: Capure i_chipMark; - uint8_t CHIP_MARK = i_chipMark; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_INDEX); - return l_rc; - } - else if ((l_dramWidth == mss_MemConfig::X8) && (i_chipMark % 4) ) - { - FAPI_ERR("i_chipMark invalid: not first symbol index of a x8 chip on %s.",i_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; - // FFDC: Capure i_rank; - uint8_t RANK = i_rank; - // FFDC: Capure i_symbolMark; - uint8_t SYMBOL_MARK = i_symbolMark; - // FFDC: Capure i_chipMark; - uint8_t CHIP_MARK = i_chipMark; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_CHIP_INDEX); - return l_rc; - - } - else if ((l_dramWidth == mss_MemConfig::X4) && (i_chipMark % 2) ) - { - FAPI_ERR("i_chipMark invalid: not first symbol index of a x4 chip on %s.",i_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; - // FFDC: Capure i_rank; - uint8_t RANK = i_rank; - // FFDC: Capure i_symbolMark; - uint8_t SYMBOL_MARK = i_symbolMark; - // FFDC: Capure i_chipMark; - uint8_t CHIP_MARK = i_chipMark; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_CHIP_INDEX); - return l_rc; - } - // TODO: create error if x4 mode and symbol 0,1? - else // Convert from symbol index to galois field - { - l_chipMarkGalois = mss_symbol2Galois[i_chipMark]; - } - l_ecmd_rc |= l_markstore.insert( l_chipMarkGalois, 8, 8, 0 ); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write markstore register for the given rank - l_rc = fapiPutScom(l_targetCentaur, mss_markStoreRegs[i_rank][l_mbaPosition], l_markstore); - if(l_rc) return l_rc; - - // If MPE FIR for the given rank (scrub or fetch) is on after the write, - // we will return a fapi::ReturnCode to indicate write may not have worked. - // Up to caller to read again if they want to see what new chip mark is. - l_rc = fapiGetScom(l_targetCentaur, mss_mbeccfir[l_mbaPosition], l_mbeccfir); - if(l_rc) return l_rc; - if (l_mbeccfir.isBitSet(i_rank) || l_mbeccfir.isBitSet(20 + i_rank)) - { - FAPI_ERR("Markstore write may have been blocked due to MPE FIR set on %s.",i_target.toEcmdString()); - - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; - // FFDC: Capure i_rank; - uint8_t RANK = i_rank; - // FFDC: Capure i_symbolMark; - uint8_t SYMBOL_MARK = i_symbolMark; - // FFDC: Capure i_chipMark; - uint8_t CHIP_MARK = i_chipMark; - // FFDC: Capture MBECCFIR - ecmdDataBufferBase & MBECCFIR = l_mbeccfir; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED); - return l_rc; - } - - - // Get attribute that tells we have cen DD2, and can enable exit poing 1 - l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_DD2_ENABLE_EXIT_POINT_1, &i_target, l_dd2_enable_exit_point_1); - if(l_rc) - { - FAPI_ERR("Error getting ATTR_CENTAUR_EC_DD2_ENABLE_EXIT_POINT_1"); - return l_rc; - } - - if(l_dd2_enable_exit_point_1) - { - // Read all mark store for both MBAs - for ( l_mbaPosition = 0; l_mbaPosition < 2; l_mbaPosition++) - { - for ( l_rank_index = 0; l_rank_index < MSS_MAX_RANKS; l_rank_index++ ) - { - l_rc = fapiGetScom(l_targetCentaur, mss_markStoreRegs[l_rank_index][l_mbaPosition], l_markstore); - if(l_rc) return l_rc; - - if (l_markstore.isBitSet(0,16)) - { - // Mark found, so exit point 1 needed - l_exit_point_1_needed = true; - break; - } - } - if (l_exit_point_1_needed) break; - } - - // Read MBSCFGQ - l_rc = fapiGetScom(l_targetCentaur, MBSCFGQ_0x02011411, l_mbscfg); - if(l_rc) return l_rc; - - // Enable exit point 1 - if (l_exit_point_1_needed) - { - l_ecmd_rc |= l_mbscfg.setBit(0); - } - // Else, disable exit point 1 - else - { - l_ecmd_rc |= l_mbscfg.clearBit(0); - } - - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write MBSCFGQ - l_rc = fapiPutScom(l_targetCentaur, MBSCFGQ_0x02011411, l_mbscfg); - if(l_rc) return l_rc; - - } // End if l_dd2_enable_exit_point_1 - - - FAPI_INF("EXIT mss_put_mark_store()"); - return l_rc; - } - - - - -//------------------------------------------------------------------------------ -// mss_get_steer_mux -//------------------------------------------------------------------------------ - - fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, - uint8_t i_rank, - mss_SteerMux::muxType i_muxType, - uint8_t & o_dramSparePort0Symbol, - uint8_t & o_dramSparePort1Symbol, - uint8_t & o_eccSpareSymbol ) - { - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_steerMux(64); - ecmdDataBufferBase l_data(64); - uint8_t l_dramWidth = 0; - uint8_t l_dramSparePort0Index = 0; - uint8_t l_dramSparePort1Index = 0; - uint8_t l_eccSpareIndex = 0; - fapi::Target l_targetCentaur; - uint8_t l_mbaPosition = 0; - - o_dramSparePort0Symbol = MSS_INVALID_SYMBOL; - o_dramSparePort1Symbol = MSS_INVALID_SYMBOL; - o_eccSpareSymbol = MSS_INVALID_SYMBOL; - - // Get Centaur target for the given MBA - l_rc = fapiGetParentChip(i_target, l_targetCentaur); - if(l_rc) - { - FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",i_target.toEcmdString()); - return l_rc; - } - - - // Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Get l_dramWidth - l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); - if(l_rc) - { - FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); - return l_rc; - } - - - // Check for i_rank or i_muxType out of range - if ((i_rank>=8) || - !((i_muxType==mss_SteerMux::READ_MUX) || (i_muxType==mss_SteerMux::WRITE_MUX))) - { - FAPI_ERR("i_rank or i_muxType input to mss_get_steer_mux out of range on %s.",i_target.toEcmdString()); - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: Capture i_rank; - uint8_t RANK = i_rank; - // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_GET_STEER_MUX_BAD_INPUT); - return l_rc; - } - - - // Read steer mux register for the given rank and mux type (read or write). - if (i_muxType == mss_SteerMux::READ_MUX) - { - // Read muxes are in the MBS - l_rc = fapiGetScom(l_targetCentaur, mss_readMuxRegs[i_rank][l_mbaPosition], l_steerMux); - if(l_rc) return l_rc; - } - else - { - // Write muxes are in the MBA - l_rc = fapiGetScom(i_target, mss_writeMuxRegs[i_rank], l_steerMux); - if(l_rc) return l_rc; - } - - - // Get l_dramSparePort0Index - l_ecmd_rc |= l_steerMux.extractPreserve(&l_dramSparePort0Index, 0, 5, 8-5); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Get o_dramSparePort0Symbol if index in valid range - if ((l_dramWidth == mss_MemConfig::X8) && (l_dramSparePort0Index < MSS_X8_STEER_OPTIONS_PER_PORT)) - { - o_dramSparePort0Symbol = mss_x8dramSparePort0Index_to_symbol[l_dramSparePort0Index]; - } - else if ((l_dramWidth == mss_MemConfig::X4) && (l_dramSparePort0Index < MSS_X4_STEER_OPTIONS_PER_PORT0)) - { - o_dramSparePort0Symbol = mss_x4dramSparePort0Index_to_symbol[l_dramSparePort0Index]; - } - else - { - FAPI_ERR("Steer mux l_dramSparePort0Index out of range on %s.",i_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; - // FFDC: Capure i_rank; - uint8_t RANK = i_rank; - // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; - // FFDC: Capture steer mux - ecmdDataBufferBase & STEER_MUX = l_steerMux; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_STEER_MUX); - return l_rc; - } - - - - // Get l_dramSparePort1Index - l_ecmd_rc |= l_steerMux.extractPreserve(&l_dramSparePort1Index, 5, 5, 8-5); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Get o_dramSparePort1Symbol if index in valid range - if ((l_dramWidth == mss_MemConfig::X8) && (l_dramSparePort1Index < MSS_X8_STEER_OPTIONS_PER_PORT)) - { - o_dramSparePort1Symbol = mss_x8dramSparePort1Index_to_symbol[l_dramSparePort1Index]; - } - else if ((l_dramWidth == mss_MemConfig::X4) && (l_dramSparePort1Index < MSS_X4_STEER_OPTIONS_PER_PORT1)) - { - o_dramSparePort1Symbol = mss_x4dramSparePort1Index_to_symbol[l_dramSparePort1Index]; - } - else - { - FAPI_ERR("Steer mux l_dramSparePort1Index out of range on %s.",i_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; - // FFDC: Capure i_rank; - uint8_t RANK = i_rank; - // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; - // FFDC: Capture steer mux - ecmdDataBufferBase & STEER_MUX = l_steerMux; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_STEER_MUX); - return l_rc; - } - - - - // Get l_eccSpareIndex - l_ecmd_rc |= l_steerMux.extractPreserve(&l_eccSpareIndex, 10, 6, 8-6); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Get o_eccSpareSymbol if index in valid range - if (l_eccSpareIndex < MSS_X4_ECC_STEER_OPTIONS) - { - o_eccSpareSymbol = mss_eccSpareIndex_to_symbol[l_eccSpareIndex]; - } - else - { - FAPI_ERR("o_eccSpareSymbol out of range on %s.",i_target.toEcmdString()); - - // Calling out FW high - // FFDC: MBA target - const fapi::Target & MBA = i_target; - // FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; - // FFDC: Capure i_rank; - uint8_t RANK = i_rank; - // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; - // FFDC: Capture steer mux - ecmdDataBufferBase & STEER_MUX = l_steerMux; - - // Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_STEER_MUX); - return l_rc; - } - - FAPI_INF("mss_get_steer_mux(): rank%d, port0 steer = %d, port1 steer = %d, ecc steer = %d", - i_rank, o_dramSparePort0Symbol, o_dramSparePort1Symbol, o_eccSpareSymbol ); - - return l_rc; - - } - - - - - - -//------------------------------------------------------------------------------ -// mss_put_steer_mux -//------------------------------------------------------------------------------ - - fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, - uint8_t i_rank, - mss_SteerMux::muxType i_muxType, - uint8_t i_steerType, - uint8_t i_symbol ) - - - - { - FAPI_INF("ENTER mss_put_steer_mux()"); - - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - ecmdDataBufferBase l_steerMux(64); - ecmdDataBufferBase l_data(64); - uint8_t l_dramWidth = 0; - uint8_t l_dramSparePort0Index = 0; - uint8_t l_dramSparePort1Index = 0; - uint8_t l_eccSpareIndex = 0; - fapi::Target l_targetCentaur; - uint8_t l_mbaPosition = 0; - -// Get Centaur target for the given MBA - l_rc = fapiGetParentChip(i_target, l_targetCentaur); - if(l_rc) - { - FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",i_target.toEcmdString()); - return l_rc; - } - - -// Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); - return l_rc; - } - -// Get l_dramWidth - l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); - if(l_rc) - { - FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); - return l_rc; - } - - -// Check for i_rank or i_muxType or i_steerType or i_symbol out of range - if ((i_rank>=8) || - !((i_muxType==mss_SteerMux::READ_MUX) || (i_muxType==mss_SteerMux::WRITE_MUX)) || - !((i_steerType == mss_SteerMux::DRAM_SPARE_PORT0) || (i_steerType == mss_SteerMux::DRAM_SPARE_PORT1) || (i_steerType == mss_SteerMux::ECC_SPARE)) || - (i_symbol >= 72)) - { - FAPI_ERR("i_rank or i_muxType or i_steerType or i_symbol input to mss_get_steer_mux out of range on %s.",i_target.toEcmdString()); -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = i_target; -// FFDC: Capture i_rank; - uint8_t RANK = i_rank; -// FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; -// FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; -// FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; - -// Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_PUT_STEER_MUX_BAD_INPUT); - return l_rc; - } -// TODO: add error if ecc_spare and symbol is 0 or 1? - - -// Read steer mux register for the given rank and mux type (read or write). - if (i_muxType == mss_SteerMux::READ_MUX) - { -// Read muxes are in the MBS - l_rc = fapiGetScom(l_targetCentaur, mss_readMuxRegs[i_rank][l_mbaPosition], l_steerMux); - if(l_rc) return l_rc; - } - else - { -// Write muxes are in the MBA - l_rc = fapiGetScom(i_target, mss_writeMuxRegs[i_rank], l_steerMux); - if(l_rc) return l_rc; - } - - -// Convert from i_symbol to l_dramSparePort0Index - if (i_steerType == mss_SteerMux::DRAM_SPARE_PORT0) - { - if (l_dramWidth == mss_MemConfig::X8) - { - l_dramSparePort0Index = MSS_X8_STEER_OPTIONS_PER_PORT; - for ( uint32_t i = 0; i < MSS_X8_STEER_OPTIONS_PER_PORT; i++ ) - { - if ( i_symbol == mss_x8dramSparePort0Index_to_symbol[i] ) - { - l_dramSparePort0Index = i; - break; - } - } - - if ( MSS_X8_STEER_OPTIONS_PER_PORT <= l_dramSparePort0Index ) - { - FAPI_ERR("No match for i_symbol = %d in mss_x8dramSparePort0Index_to_symbol[] on %s.", i_symbol, i_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = i_target; -// FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; -// FFDC: Capure i_rank; - uint8_t RANK = i_rank; -// FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; -// FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; -// FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; - -// Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); - return l_rc; - } - } - - else if (l_dramWidth == mss_MemConfig::X4) - { - l_dramSparePort0Index = MSS_X4_STEER_OPTIONS_PER_PORT0; - for ( uint32_t i = 0; i < MSS_X4_STEER_OPTIONS_PER_PORT0; i++ ) - { - if ( i_symbol == mss_x4dramSparePort0Index_to_symbol[i] ) - { - l_dramSparePort0Index = i; - break; - } - } - - if ( MSS_X4_STEER_OPTIONS_PER_PORT0 <= l_dramSparePort0Index ) - { - FAPI_ERR("No match for i_symbol in mss_x4dramSparePort0Index_to_symbol[] on %s.",i_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = i_target; -// FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; -// FFDC: Capure i_rank; - uint8_t RANK = i_rank; -// FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; -// FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; -// FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; - -// Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); - return l_rc; - } - } - - l_ecmd_rc |= l_steerMux.insert( l_dramSparePort0Index, 0, 5, 8-5 ); - } - - -// Convert from i_symbol to l_dramSparePort1Index - if (i_steerType == mss_SteerMux::DRAM_SPARE_PORT1) - { - if (l_dramWidth == mss_MemConfig::X8) - { - l_dramSparePort1Index = MSS_X8_STEER_OPTIONS_PER_PORT; - for ( uint32_t i = 0; i < MSS_X8_STEER_OPTIONS_PER_PORT; i++ ) - { - if ( i_symbol == mss_x8dramSparePort1Index_to_symbol[i] ) - { - l_dramSparePort1Index = i; - break; - } - } - - if ( MSS_X8_STEER_OPTIONS_PER_PORT <= l_dramSparePort1Index ) - { - FAPI_ERR("No match for i_symbol in mss_x8dramSparePort1Index_to_symbol[] on %s.",i_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = i_target; -// FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; -// FFDC: Capure i_rank; - uint8_t RANK = i_rank; -// FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; -// FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; -// FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; - -// Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); - return l_rc; - } - } - - else if (l_dramWidth == mss_MemConfig::X4) - { - l_dramSparePort1Index = MSS_X4_STEER_OPTIONS_PER_PORT1; - for ( uint32_t i = 0; i < MSS_X4_STEER_OPTIONS_PER_PORT1; i++ ) - { - if ( i_symbol == mss_x4dramSparePort1Index_to_symbol[i] ) - { - l_dramSparePort1Index = i; - break; - } - } - - if ( MSS_X4_STEER_OPTIONS_PER_PORT1 <= l_dramSparePort1Index ) - { - FAPI_ERR("No match for i_symbol in mss_x4dramSparePort1Index_to_symbol[] on %s.",i_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = i_target; -// FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; -// FFDC: Capure i_rank; - uint8_t RANK = i_rank; -// FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; -// FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; -// FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; - -// Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); - return l_rc; - } - } - - l_ecmd_rc |= l_steerMux.insert( l_dramSparePort1Index, 5, 5, 8-5 ); - } - - - -// Convert from i_symbol to l_eccSpareIndex - if (i_steerType == mss_SteerMux::ECC_SPARE) - { - if (l_dramWidth == mss_MemConfig::X4) - { - l_eccSpareIndex = MSS_X4_ECC_STEER_OPTIONS; - for ( uint32_t i = 0; i < MSS_X4_ECC_STEER_OPTIONS; i++ ) - { - if ( i_symbol == mss_eccSpareIndex_to_symbol[i] ) - { - l_eccSpareIndex = i; - break; - } - } - - if ( MSS_X4_ECC_STEER_OPTIONS <= l_eccSpareIndex ) - { - FAPI_ERR("No match for i_symbol in mss_eccSpareIndex_to_symbol[] on %s.",i_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = i_target; -// FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; -// FFDC: Capure i_rank; - uint8_t RANK = i_rank; -// FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; -// FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; -// FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; - -// Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); - return l_rc; - } - } - else if (l_dramWidth == mss_MemConfig::X8) - { - FAPI_ERR("ECC_SPARE not valid with x8 mode on %s.",i_target.toEcmdString()); - -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = i_target; -// FFDC: DRAM width - uint8_t DRAM_WIDTH = l_dramWidth; -// FFDC: Capure i_rank; - uint8_t RANK = i_rank; -// FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; -// FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; -// FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; - -// Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_X8_ECC_SPARE); - return l_rc; - } - - l_ecmd_rc |= l_steerMux.insert( l_eccSpareIndex, 10, 6, 8-6 ); - } - - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - -// Write the steer mux register for the given rank and mux -// type (read or write). - if (i_muxType == mss_SteerMux::READ_MUX) - { -// Read muxes are in the MBS - l_rc = fapiPutScom(l_targetCentaur, mss_readMuxRegs[i_rank][l_mbaPosition], l_steerMux); - if(l_rc) return l_rc; - } - else - { -// Write muxes are in the MBA - l_rc = fapiPutScom(i_target, mss_writeMuxRegs[i_rank], l_steerMux); - if(l_rc) return l_rc; - } - - - FAPI_INF("EXIT mss_put_steer_mux()"); - - return l_rc; - - } - - -//------------------------------------------------------------------------------ -// mss_check_steering -//------------------------------------------------------------------------------ - - fapi::ReturnCode mss_check_steering(const fapi::Target & i_target, - uint8_t i_rank, - uint8_t & o_dramSparePort0Symbol, - uint8_t & o_dramSparePort1Symbol, - uint8_t & o_eccSpareSymbol ) - { - -// Get the read steer mux, with the assuption -// that the write mux will be the same. - return mss_get_steer_mux(i_target, - i_rank, - mss_SteerMux::READ_MUX, - o_dramSparePort0Symbol, - o_dramSparePort1Symbol, - o_eccSpareSymbol); - } - - -//------------------------------------------------------------------------------ -// mss_do_steering -//------------------------------------------------------------------------------ - - fapi::ReturnCode mss_do_steering(const fapi::Target & i_target, - uint8_t i_rank, - uint8_t i_symbol, - bool i_x4EccSpare) - { - FAPI_INF("ENTER mss_do_steering()"); - - - fapi::ReturnCode l_rc; - uint8_t l_steerType = 0; // 0 = DRAM_SPARE_PORT0, Spare DRAM on port0 -// 1 = DRAM_SPARE_PORT1, Spare DRAM on port1 -// 2 = ECC_SPARE, ECC spare (used in x4 mode only) - - -// Check for i_rank or i_symbol out of range - if ((i_rank>=MSS_MAX_RANKS) || (i_symbol>=MSS_SYMBOLS_PER_RANK)) - { - FAPI_ERR("i_rank or i_symbol input to mss_do_steer out of range on %s.",i_target.toEcmdString()); -// Calling out FW high -// FFDC: MBA target - const fapi::Target & MBA = i_target; -// FFDC: Capture i_rank; - uint8_t RANK = i_rank; -// FFDC: Capture i_symbol; - uint8_t SYMBOL = i_symbol; -// FFDC: Capture i_x4EccSpare - uint8_t X4ECCSPARE = i_x4EccSpare; - -// Create new log. - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_DO_STEER_INPUT_OUT_OF_RANGE); - return l_rc; - } - -//------------------------------------------------------ -// Determine l_steerType -//------------------------------------------------------ - if (i_x4EccSpare) - { - l_steerType = mss_SteerMux::ECC_SPARE; - } - else - { -// Symbols 71-40, 7-4 come from port0 - if (((i_symbol<=MSS_PORT_0_SYMBOL_71)&&(i_symbol>=MSS_PORT_0_SYMBOL_40)) || - ((i_symbol<=MSS_PORT_0_SYMBOL_7)&&(i_symbol>=MSS_PORT_0_SYMBOL_4))) - { - l_steerType = mss_SteerMux::DRAM_SPARE_PORT0; - } -// Symbols 39-8, 3-0 come from port1 - else - { - l_steerType = mss_SteerMux::DRAM_SPARE_PORT1; - } - } - -//------------------------------------------------------ -// Update write mux -//------------------------------------------------------ - l_rc = mss_put_steer_mux( - - i_target, // MBA - i_rank, // Master rank: 0-7 - mss_SteerMux::WRITE_MUX,// write mux - l_steerType, // DRAM_SPARE_PORT0/DRAM_SPARE_PORT1/ECC_SPARE - i_symbol); // First symbol index of DRAM to steer around - - if (l_rc) - { - FAPI_ERR("Error updating write mux on %s.",i_target.toEcmdString()); - return l_rc; - } - -//------------------------------------------------------ -// Wait for a periodic cal. -//------------------------------------------------------ - - const uint64_t HW_MODE_DELAY = 250000000; // 250mSec delay -// const uint64_t HW_MODE_DELAY = 2000000000; // 2 Sec delay - - -// 200000 sim cycle delay for SIM mode - const uint64_t SIM_MODE_DELAY = 200000; - - fapiDelay(HW_MODE_DELAY, SIM_MODE_DELAY); - - -//------------------------------------------------------ -// Update read mux -//------------------------------------------------------ - l_rc = mss_put_steer_mux( - - i_target, // MBA - i_rank, // Master rank: 0-7 - mss_SteerMux::READ_MUX, // read mux - l_steerType, // DRAM_SPARE_PORT0/DRAM_SPARE_PORT1/ECC_SPARE - i_symbol); // First symbol index of DRAM to steer around - - if (l_rc) - { - FAPI_ERR("Error updating read mux on %s.",i_target.toEcmdString()); - return l_rc; - - } - - FAPI_INF("EXIT mss_do_steering()"); - - return l_rc; - } - - - -//-------------------------------------------------------- -//mss_restore_DRAM_repairs -//--------------------------------------------------------- - - fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, - uint8_t & o_repairs_applied, - uint8_t & o_repairs_exceeded) - - { - fapi::ReturnCode l_rc; - bool l_flag_standby = false; - struct repair_count l_count; - l_rc = mss_restore_DRAM_repairs_asm(i_target,o_repairs_applied,o_repairs_exceeded,l_flag_standby,l_count); - return l_rc; - - } - - - - - - - - -//------------------------------------------------------------------------------ -// mss_restore_DRAM_repairs_asm -//------------------------------------------------------------------------------ - - - - - - - fapi::ReturnCode mss_restore_DRAM_repairs_asm( const fapi::Target & i_target, - uint8_t & o_repairs_applied, - uint8_t & o_repairs_exceeded, - bool i_standby_flag, - struct repair_count &o_repair_count) - - { - - FAPI_INF("ENTER mss_restore_DRAM_repairs()"); - - - fapi::ReturnCode l_rc; - uint8_t l_dramWidth = 0; - uint8_t l_dqBitmap[DIMM_DQ_RANK_BITMAP_SIZE]; // 10 byte array of bad bits - ecmdDataBufferBase l_data(64); - - uint8_t l_port=0; - uint8_t l_dimm=0; - uint8_t l_rank=0; - uint8_t l_byte=0; - uint8_t l_nibble=0; - uint8_t l_dq_pair_index = 0; - uint8_t l_bad_dq_pair_index = 0; - uint8_t l_bad_dq_pair_count=0; - uint8_t l_dq_pair_mask = 0xC0; - uint8_t l_byte_being_steered = 0xff; - uint8_t l_bad_symbol = MSS_INVALID_SYMBOL; - uint8_t l_symbol_mark = MSS_INVALID_SYMBOL; - uint8_t l_chip_mark = MSS_INVALID_SYMBOL; - uint8_t l_dramSparePort0Symbol = MSS_INVALID_SYMBOL; - uint8_t l_dramSparePort1Symbol = MSS_INVALID_SYMBOL; - uint8_t l_eccSpareSymbol = MSS_INVALID_SYMBOL; - bool l_spare_exists = false; - bool l_spare_used = false; - bool l_chip_mark_used = false; - bool l_symbol_mark_used = false; - uint8_t l_valid_dimms = 0; - uint8_t l_valid_dimm[2][2]; - bool l_x4_DRAM_spare_low_exists = false; - bool l_x4_DRAM_spare_high_exists = false; - bool l_x4_DRAM_spare_used = false; - bool l_x4_ECC_spare_used = false; - uint8_t l_index = 0; - // NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3 - uint8_t l_spare_dram[2][2][4]; // Array defining if spare dram exit - //New structures Updated to use for ASMI menu - - uint8_t l_steer[8][3]; - uint8_t l_mark_store[8][2]; - - - - - - enum - { - MSS_REPAIRS_APPLIED = 1, - MSS_REPAIRS_EXCEEDED = 2, - }; - - uint8_t l_repair_status[2][2][4]={ - {{0,0,0,0} , {0,0,0,0}}, - {{0,0,0,0} , {0,0,0,0}}}; - - static const uint8_t l_repairs_applied_translation[8]={ - 0x80, //rank0 (maps to port0_dimm0, port1_dimm0) - 0x40, //rank1 (maps to port0_dimm0, port1_dimm0) - 0x20, //rank2 (maps to port0_dimm0, port1_dimm0) - 0x10, //rank3 (maps to port0_dimm0, port1_dimm0) - 0x08, //rank4 (maps to port0_dimm1, port1_dimm1) - 0x04, //rank5 (maps to port0_dimm1, port1_dimm1) - 0x02, //rank6 (maps to port0_dimm1, port1_dimm1) - 0x01}; //rank7 (maps to port0_dimm1, port1_dimm1) - - static const uint8_t l_repairs_exceeded_translation[2][2]={ - // dimm0 dimm1 - { 0x8, 0x4 }, // port0 - { 0x2, 0x1 }}; // port1 - - - - - // Start with no repairs applies and no repairs exceeded - o_repairs_applied = 0; - o_repairs_exceeded = 0; - - - // Get array attribute that defines if spare dram exits - // l_spare_dram[port][dimm][rank] - // NO_SPARE = 0, LOW_NIBBLE = 1, HIGH_NIBBLE = 2, FULL_BYTE = 3 - // NOTE: Typically will same value for whole Centaur. - l_rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_SPARE, &i_target, l_spare_dram); - if(l_rc) - { - FAPI_ERR("Error reading attribute to see if spare exists on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Get l_dramWidth - l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); - if(l_rc) - { - FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Find out which dimms are functional - l_rc = FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, &i_target, l_valid_dimms); - if (l_rc) - { - FAPI_ERR("Failed to get attribute: ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR on %s.",i_target.toEcmdString()); - return l_rc; - } - l_valid_dimm[0][0] = (l_valid_dimms & 0x80); // port0, dimm0 - l_valid_dimm[0][1] = (l_valid_dimms & 0x40); // port0, dimm1 - l_valid_dimm[1][0] = (l_valid_dimms & 0x08); // port1, dimm0 - l_valid_dimm[1][1] = (l_valid_dimms & 0x04); // port1, dimm1 - - //Initializing the repair count array - for(l_rank =0;l_rank < 8;l_rank++) - { - o_repair_count.symbolmark_count[l_rank] = 0; - o_repair_count.chipmark_count[l_rank] = 0; - o_repair_count.steer_count[l_rank] = 0; - } - - memset(l_steer,MSS_INVALID_SYMBOL,8*3); - - memset(l_mark_store,MSS_INVALID_SYMBOL,8*3); - - // For each port in the given MBA:0,1 - for(l_port=0; l_port<DIMM_DQ_MAX_MBA_PORTS; l_port++ ) - { - // For each DIMM select on the given port:0,1 - for(l_dimm=0; l_dimm<DIMM_DQ_MAX_MBAPORT_DIMMS; l_dimm++ ) - { - if (l_valid_dimm[l_port][l_dimm]) - { - // For each rank select on the given DIMM select:0,1,2,3 - for(l_rank=0; l_rank<DIMM_DQ_MAX_DIMM_RANKS; l_rank++ ) - { - - // Get the bad DQ Bitmap for l_port, l_dimm, l_rank - l_rc = dimmGetBadDqBitmap(i_target, - l_port, - l_dimm, - l_rank, - l_dqBitmap); - if (l_rc) - { - FAPI_ERR("Error from dimmGetBadDqBitmap on %s.",i_target.toEcmdString()); - return l_rc; - } - - // x8 ECC - // x8 bit chip mark, x2 bit symbol mark, spare x8 DRAM if CDIMM - if (l_dramWidth == mss_MemConfig::X8) - { - - // Determine if spare x8 DRAM exists - l_spare_exists = l_spare_dram[l_port][l_dimm][l_rank] == mss_MemConfig::FULL_BYTE; - - // Start with spare not used - l_spare_used = false; - l_byte_being_steered = MSS_INVALID_SYMBOL; - - - if(i_standby_flag) - { - mss_get_dummy_mark_store( - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // MSS_INVALID_SYMBOL if no symbol mark - l_chip_mark, // MSS_INVALID_SYMBOL if no chip mark - l_mark_store); - } - else - { - - // Read mark store - l_rc = mss_get_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // MSS_INVALID_SYMBOL if no symbol mark - l_chip_mark ); // MSS_INVALID_SYMBOL if no chip mark - - } - - if (l_rc) - { - FAPI_ERR("Error reading markstore on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Check if chip mark used (may have been used on other port) - l_chip_mark_used = l_chip_mark != MSS_INVALID_SYMBOL; - - // Check if symbol mark used (may have been used on other port) - l_symbol_mark_used = l_symbol_mark != MSS_INVALID_SYMBOL; - - // For each byte 0-9, where 9 is the spare - for(l_byte=0; l_byte<DIMM_DQ_RANK_BITMAP_SIZE; l_byte++ ) - { - if ((l_byte == 9) && !l_spare_exists) - { - // Don't look at byte 9 if spare doesn't exist - break; - } - - if (l_dqBitmap[l_byte] == 0) - { - // Don't bother analyzing if byte is clean - continue; - } - - // Mask initialized to look at first dq pair in byte - l_dq_pair_mask = 0xC0; - - // Start with no bad dq pairs counted for this byte - l_bad_dq_pair_count = 0; - - // For each of the 4 dq pairs in the byte - for(l_dq_pair_index=0; l_dq_pair_index<4; l_dq_pair_index++ ) - { - - // If any bad bits in this dq pair - if (l_dqBitmap[l_byte] & l_dq_pair_mask) - { - // Increment bad symbol count - l_bad_dq_pair_count++; - - // Record bad dq pair - just most recent if multiple bad - l_bad_dq_pair_index = l_dq_pair_index; - } - - // Shift mask to next symbol - l_dq_pair_mask = l_dq_pair_mask >> 2; - } - - // If spare is bad but not used, not valid to try repair - if ( l_spare_exists && (l_byte==9) && (l_bad_dq_pair_count > 0) && !l_spare_used) - { - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: Bad unused spare - no valid repair on %s", i_target.toEcmdString()); - - - break; - } - - // If more than one dq pair is bad - if(l_bad_dq_pair_count > 1) - { - - // If spare x8 DRAM exists and not used yet, - if (l_spare_exists && !l_spare_used) - { - l_bad_symbol = mss_centaurDQ_to_symbol(8*l_byte,l_port) - 3; - - if(i_standby_flag) - { - mss_put_dummy_steer_mux( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - mss_SteerMux::READ_MUX, // read mux - l_port, // l_port: 0,1 - l_bad_symbol, // First symbol index of byte to steer - l_steer); - } - else - { - - // Update read mux - l_rc = mss_put_steer_mux( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - mss_SteerMux::READ_MUX, // read mux - l_port, // l_port: 0,1 - l_bad_symbol); // First symbol index of byte to steer - } - if (l_rc) - { - FAPI_ERR("Error updating read mux on %s.",i_target.toEcmdString()); - return l_rc; - - } - - // Update write mux - - - - if(i_standby_flag) - { - //do nothing - } - else - { - - l_rc = mss_put_steer_mux( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - mss_SteerMux::WRITE_MUX,// write mux - l_port, // l_port: 0,1 - l_bad_symbol); // First symbol index of byte to steer - } - if (l_rc) - { - FAPI_ERR("Error updating write mux on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Spare now used on this port,dimm,rank - l_spare_used = true; - - // Remember which byte is being steered - // so we know where to apply chip or symbol mark - // if spare turns out to be bad - l_byte_being_steered = l_byte; - - // Update which rank 0-7 has had repairs applied - o_repairs_applied |= l_repairs_applied_translation[4*l_dimm + l_rank]; - - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_APPLIED; - - // If port1 repairs applied and port0 had repairs exceeded, say port1 repairs exceeded too - if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_APPLIED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED)) - { - o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; - } - - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: dq %d-%d, symbols %d-%d, FIXED CHIP WITH X8 STEER on %s", - 8*l_byte, 8*l_byte+7,l_bad_symbol, l_bad_symbol+3, i_target.toEcmdString()); - - - } - - // Else if chip mark not used yet, update mark store with chip mark - else if (!l_chip_mark_used) - { - // NOTE: Have to do a read/modify/write so we - // only update chip mark, and don't overwrite - // symbol mark. - - if(i_standby_flag) - { - mss_get_dummy_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // Reading this just to write it back - l_chip_mark, // Expecting MSS_INVALID_SYMBOL since no chip mark - l_mark_store); - } - - else - { - - - // Read mark store - l_rc = mss_get_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // Reading this just to write it back - l_chip_mark ); // Expecting MSS_INVALID_SYMBOL since no chip mark - } - if (l_rc) - { - FAPI_ERR("Error reading markstore on %s.",i_target.toEcmdString()); - return l_rc; - } - - - // Special case: - // If this is a bad spare byte we are analyzing - // the chip mark goes on the byte being steered - if (l_byte==9) - { - l_chip_mark = mss_centaurDQ_to_symbol(8*l_byte_being_steered,l_port) - 3; - FAPI_ERR("WARNING: Bad spare so chip mark goes on l_byte_being_steered = %d on %s", l_byte_being_steered ,i_target.toEcmdString()); - } - - else - { - l_chip_mark = mss_centaurDQ_to_symbol(8*l_byte,l_port) - 3; - } - - if(i_standby_flag) - { - - mss_put_dummy_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // Writting back exactly what we read - l_chip_mark, // First symbol index of byte getting chip mark - l_mark_store); - - } - else - { - - - // Write mark store - l_rc = mss_put_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // Writting back exactly what we read - l_chip_mark ); // First symbol index of byte getting chip mark - } - if (l_rc) - { - FAPI_ERR("Error updating markstore on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Chip mark now used on this rank - l_chip_mark_used = true; - - // Update which rank 0-7 has had repairs applied - o_repairs_applied |= l_repairs_applied_translation[4*l_dimm + l_rank]; - - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_APPLIED; - - // If port1 repairs applied and port0 had repairs exceeded, say port1 repairs exceeded too - if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_APPLIED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED)) - { - o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; - } - - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: dq %d-%d, symbols %d-%d, FIXED CHIP WITH X8 CHIP MARK on %s", - 8*l_byte, 8*l_byte+7,l_chip_mark, l_chip_mark+3 ,i_target.toEcmdString()); - - - } - - // Else, more bad bits than we can repair so update o_repairs_exceeded - else - { - o_repairs_exceeded |= l_repairs_exceeded_translation[l_port][l_dimm]; - - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_EXCEEDED; - - // If port1 repairs exceeded and port0 had a repair, say port0 repairs exceeded too - if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_APPLIED)) - { - o_repairs_exceeded |= l_repairs_exceeded_translation[0][l_dimm]; - } - - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x",l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: dq %d-%d, REPAIRS EXCEEDED %s", 8*l_byte, 8*l_byte+7, i_target.toEcmdString()); - - - - // Break out of loop on bytes - break; - } - } // End If bad symbol count > 1 - - - //Else if bad symbol count = 1 - else if(l_bad_dq_pair_count == 1) - { - // If symbol mark not used yet, update mark store with symbol mark - if (!l_symbol_mark_used) - { - - // NOTE: Have to do a read/modify/write so we - // only update symbol mark, and don't overwrite - // chip mark. - - // Read mark store - if(i_standby_flag) - { - mss_get_dummy_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // Expecting MSS_INVALID_SYMBOL since no symbol mark - l_chip_mark, // Reading this just to write it back - l_mark_store); - } - else - { - l_rc = mss_get_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // Expecting MSS_INVALID_SYMBOL since no symbol mark - l_chip_mark ); // Reading this just to write it back - } - if (l_rc) - { - FAPI_ERR("Error reading markstore on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Special case: - // If this is a bad spare byte we are analying - // the symbol mark goes on the byte being steered - if (l_byte==9) - { - l_symbol_mark = mss_centaurDQ_to_symbol(8*l_byte_being_steered + 2*l_bad_dq_pair_index,l_port); - FAPI_ERR("WARNING: Bad spare so symbol mark goes on l_byte_being_steered = %d on %s", l_byte_being_steered, i_target.toEcmdString()); - } - - else - { - l_symbol_mark = mss_centaurDQ_to_symbol(8*l_byte + 2*l_bad_dq_pair_index,l_port); - } - - - // Update mark store - - if(i_standby_flag) - { - mss_put_dummy_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // Single bad symbol found on this byte - l_chip_mark, // Writting back exactly what we read - l_mark_store); - - } - else - { - l_rc = mss_put_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // Single bad symbol found on this byte - l_chip_mark ); // Writting back exactly what we read - } - if (l_rc) - { - FAPI_ERR("Error updating markstore on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Symbol mark now used on this rank - l_symbol_mark_used = true; - - // Update which rank 0-7 has had repairs applied - o_repairs_applied |= l_repairs_applied_translation[4*l_dimm + l_rank]; - - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_APPLIED; - - // If port1 repairs applied and port0 had repairs exceeded, say port1 repairs exceeded too - if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_APPLIED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED)) - { - o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; - } - - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: dq %d-%d, symbol %d, FIXED SYMBOL WITH X2 SYMBOL MARK on %s", - 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, l_symbol_mark, i_target.toEcmdString()); - } - - - // Else if spare x8 DRAM exists and not used yet, update steer mux - else if (l_spare_exists && !l_spare_used) - { - - l_bad_symbol = mss_centaurDQ_to_symbol(8*l_byte,l_port) - 3; - - // Update read mux - - if(i_standby_flag) - { - mss_put_dummy_steer_mux( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - mss_SteerMux::READ_MUX, // read mux - l_port, // l_port: 0,1 - l_bad_symbol, // First symbol index of byte to steer - l_steer); - - } - else - { - - l_rc = mss_put_steer_mux( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - mss_SteerMux::READ_MUX, // read mux - l_port, // l_port: 0,1 - l_bad_symbol ); // First symbol index of byte to steer - } - if (l_rc) - { - FAPI_ERR("Error updating read mux on %s.",i_target.toEcmdString()); - return l_rc; - - } - - // Update write mux - if(i_standby_flag) - { - //do nothing - } - else - { - - l_rc = mss_put_steer_mux( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - mss_SteerMux::WRITE_MUX,// write mux - l_port, // l_port: 0,1 - l_bad_symbol ); // First symbol index of byte to steer - } - if (l_rc) - { - FAPI_ERR("Error updating write mux on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Spare now used on this port,dimm,rank - l_spare_used = true; - - // Remember which byte is being steered - // so we where to apply chip or symbol mark - // if spare turns out to be bad - l_byte_being_steered = l_byte; - - // Update which rank 0-7 has had repairs applied - o_repairs_applied |= l_repairs_applied_translation[4*l_dimm + l_rank]; - - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_APPLIED; - - // If port1 repairs applied and port0 had repairs exceeded, say port1 repairs exceeded too - if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_APPLIED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED)) - { - o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; - } - - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: dq %d-%d, symbols %d-%d, FIXED SYMBOL WITH X8 STEER on %s", - 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, l_bad_symbol, l_bad_symbol + 3, i_target.toEcmdString()); - - - - } - - // Else if chip mark not used yet, update mark store with chip mark - else if (!l_chip_mark_used) - { - - // NOTE: Have to do a read/modify/write so we - // only update chip mark, and don't overwrite - // symbol mark. - - // Read mark store - - if(i_standby_flag) - { - mss_get_dummy_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // Reading this just to write it back - l_chip_mark, // Expecting MSS_INVALID_SYMBOL since no chip mark - l_mark_store); - } - else - { - - l_rc = mss_get_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // Reading this just to write it back - l_chip_mark ); // Expecting MSS_INVALID_SYMBOL since no chip mark - } - if (l_rc) - { - FAPI_ERR("Error reading markstore on %s.",i_target.toEcmdString()); - return l_rc; - } - - - // Special case: - // If this is a bad spare byte we are analying - // the chip mark goes on the byte being steered - if (l_byte==9) - { - l_chip_mark = mss_centaurDQ_to_symbol(8*l_byte_being_steered,l_port) - 3; - FAPI_ERR("WARNING: Bad spare so chip mark goes on l_byte_being_steered = %d on %s", l_byte_being_steered, i_target.toEcmdString()); - } - - else - { - l_chip_mark = mss_centaurDQ_to_symbol(8*l_byte,l_port) - 3; - } - - // Update mark store - if(i_standby_flag) - { - mss_put_dummy_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // Writting back exactly what we read - l_chip_mark, // First symbol index of byte getting chip mark - l_mark_store); - } - else - { - - - l_rc = mss_put_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // Writting back exactly what we read - l_chip_mark ); // First symbol index of byte getting chip mark - } - if (l_rc) - { - FAPI_ERR("Error updating markstore on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Chip mark now used on this rank - l_chip_mark_used = true; - - // Update which rank 0-7 has had repairs applied - o_repairs_applied |= l_repairs_applied_translation[4*l_dimm + l_rank]; - - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_APPLIED; - - // If port1 repairs applied and port0 had repairs exceeded, say port1 repairs exceeded too - if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_APPLIED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED)) - { - o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; - } - - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: dq %d-%d, symbols %d-%d, FIXED SYMBOL WITH X8 CHIP MARK on %s", - 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, l_chip_mark, l_chip_mark + 3, i_target.toEcmdString()); - - } - - - // Else, more bad bits than we can repair so update o_repairs_exceeded - else - { - - o_repairs_exceeded |= l_repairs_exceeded_translation[l_port][l_dimm]; - - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_EXCEEDED; - - // If port1 repairs exceeded and port0 had a repair, say port0 repairs exceeded too - if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_APPLIED)) - { - o_repairs_exceeded |= l_repairs_exceeded_translation[0][l_dimm]; - } - - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: dq %d-%d, REPAIRS EXCEEDED on %s", - 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, i_target.toEcmdString()); - - - // Break out of loop on bytes - break; - } - - } // End If bad symbol count = 1 - - } // End For each byte 0-9, where 9 is the spare - - } // End x8 ECC - - // x4 ECC - // x4 chip mark, x4 ECC steer, spare x4 DRAM if CDIMM - else if (l_dramWidth == mss_MemConfig::X4) - { - // Determine if spare x4 DRAM exists - l_x4_DRAM_spare_low_exists = l_spare_dram[l_port][l_dimm][l_rank] == mss_MemConfig::LOW_NIBBLE; - l_x4_DRAM_spare_high_exists = l_spare_dram[l_port][l_dimm][l_rank] == mss_MemConfig::HIGH_NIBBLE; - - // Start with spare x4 DRAM not used - l_x4_DRAM_spare_used = false; - - // Read mark store - - if(i_standby_flag) - { - mss_get_dummy_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // MSS_INVALID_SYMBOL, since no symbol mark in x4 mode - l_chip_mark, // MSS_INVALID_SYMBOL if no chip mark - l_mark_store); - } - else - { - - - l_rc = mss_get_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // MSS_INVALID_SYMBOL, since no symbol mark in x4 mode - l_chip_mark ); // MSS_INVALID_SYMBOL if no chip mark - } - if (l_rc) - { - FAPI_ERR("Error reading markstore on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Check if chip mark used (may have been used on other port) - l_chip_mark_used = l_chip_mark != MSS_INVALID_SYMBOL; - - - // READ steer mux - if(i_standby_flag) - { - - mss_check_dummy_steering( - i_target, - 4*l_dimm + l_rank, - l_dramSparePort0Symbol, - l_dramSparePort1Symbol, - l_eccSpareSymbol, - l_steer); - } - else - { - l_rc = mss_check_steering( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_dramSparePort0Symbol, // Should be MSS_INVALID_SYMBOL since not used yet - l_dramSparePort1Symbol, // Should be MSS_INVALID_SYMBOL since not used yet - l_eccSpareSymbol); // MSS_INVALID_SYMBOL if no ECC steer in place yet - } - if (l_rc) - { - FAPI_ERR("Error reading steer mux %s.",i_target.toEcmdString()); - return l_rc; - } - - // Check if ECC spare used (may have been used on other port) - l_x4_ECC_spare_used = l_eccSpareSymbol != MSS_INVALID_SYMBOL; - - // For each byte 0-9, where 9 is the spare - for(l_byte=0; l_byte<DIMM_DQ_RANK_BITMAP_SIZE; l_byte++ ) - { - // For each nibble - for(l_nibble=0; l_nibble<2; l_nibble++ ) - { - // If nibble bad - if (l_dqBitmap[l_byte] & (0xf0 >> (4 * l_nibble))) - { - // If ECC spare is bad and not used, not valid to try repair - if ((l_port==1) && (l_byte==8) && (l_nibble == 1) && !l_x4_ECC_spare_used) - { - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: Bad unused x4 ECC spare - no valid repair on %s", i_target.toEcmdString()); - } - - // Else if DRAM spare is bad and not used, not valid to try repair - else if (((l_byte==9) && (l_nibble == 0) && l_x4_DRAM_spare_low_exists && !l_x4_DRAM_spare_used) || - ((l_byte==9) && (l_nibble == 1) && l_x4_DRAM_spare_high_exists && !l_x4_DRAM_spare_used)) - { - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: Bad unused x4 DRAM spare - no valid repair on %s", i_target.toEcmdString()); - } - - // Else if on the nibble not connected to a spare - else if (((l_byte==9) && (l_nibble == 0) && !l_x4_DRAM_spare_low_exists) || - ((l_byte==9) && (l_nibble == 1) && !l_x4_DRAM_spare_high_exists)) - { - // Do nothing - //FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - //FAPI_ERR("WARNING: This nibble has no spare x4 DRAM connected on %s", i_target.toEcmdString()); - } - - // Else if spare x4 DRAM exists and not used yet (and not ECC spare) - else if (((l_x4_DRAM_spare_low_exists || l_x4_DRAM_spare_high_exists) && !l_x4_DRAM_spare_used) && - !((l_port==1) && (l_byte==8) && (l_nibble == 1))) - { - // Find first symbol index for this bad nibble - l_bad_symbol = mss_centaurDQ_to_symbol(8*l_byte + 4*l_nibble, l_port) - 1; - - // Update read mux - - if(i_standby_flag) - { - mss_put_dummy_steer_mux( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - mss_SteerMux::READ_MUX, // read mux - l_port, // l_port: 0,1 - l_bad_symbol, // First symbol index of byte to steer - l_steer); - } - else - { - - - l_rc = mss_put_steer_mux( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - mss_SteerMux::READ_MUX, // read mux - l_port, // l_port: 0,1 - l_bad_symbol); // First symbol index of byte to steer - } - if (l_rc) - { - FAPI_ERR("Error updating read mux on %s.",i_target.toEcmdString()); - return l_rc; - - } - - // Update write mux - if(i_standby_flag) - { - //do nothing - } - else - { - - - l_rc = mss_put_steer_mux( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - mss_SteerMux::WRITE_MUX,// write mux - l_port, // l_port: 0,1 - l_bad_symbol); // First symbol index of byte to steer - } - if (l_rc) - { - FAPI_ERR("Error updating write mux on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Spare now used on this port,dimm,rank - l_x4_DRAM_spare_used = true; - - // Update which rank 0-7 has had repairs applied - o_repairs_applied |= l_repairs_applied_translation[4*l_dimm + l_rank]; - - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_APPLIED; - - // If port1 repairs applied and port0 had repairs exceeded, say port1 repairs exceeded too - if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_APPLIED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED)) - { - o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; - } - - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: dq %d-%d, symbols %d-%d, FIXED CHIP WITH X4 DRAM STEER on %s", - 8*l_byte + 4*l_nibble, 8*l_byte + 4*l_nibble + 3,l_bad_symbol, l_bad_symbol+1, i_target.toEcmdString()); - } - - // Else if x4 ECC spare not used yet (and not DRAM spare) - else if (!l_x4_ECC_spare_used && - !(((l_byte==9) && (l_nibble == 0) && l_x4_DRAM_spare_low_exists) || - ((l_byte==9) && (l_nibble == 1) && l_x4_DRAM_spare_high_exists))) - { - // Find first symbol index for this bad nibble - l_bad_symbol = mss_centaurDQ_to_symbol(8*l_byte + 4*l_nibble, l_port) - 1; - - // Update read mux - if(i_standby_flag) - { - mss_put_dummy_steer_mux( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - mss_SteerMux::READ_MUX, // read mux - mss_SteerMux::ECC_SPARE,// Use ECC spare - l_bad_symbol, // First symbol index of byte to steer - l_steer); - } - else - { - - l_rc = mss_put_steer_mux( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - mss_SteerMux::READ_MUX, // read mux - mss_SteerMux::ECC_SPARE,// Use ECC spare - l_bad_symbol); // First symbol index of byte to steer - } - if (l_rc) - { - FAPI_ERR("Error updating read mux on %s.",i_target.toEcmdString()); - return l_rc; - - } - - // Update write mux - if(i_standby_flag) - { - //do nothing - } - else - { - - l_rc = mss_put_steer_mux( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - mss_SteerMux::WRITE_MUX,// write mux - mss_SteerMux::ECC_SPARE,// Use ECC spare - l_bad_symbol); // First symbol index of byte to steer - } - if (l_rc) - { - FAPI_ERR("Error updating write mux on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Spare now used on this port,dimm,rank - l_x4_ECC_spare_used = true; - - // Update which rank 0-7 has had repairs applied - o_repairs_applied |= l_repairs_applied_translation[4*l_dimm + l_rank]; - - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_APPLIED; - - // If port1 repairs applied and port0 had repairs exceeded, say port1 repairs exceeded too - if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_APPLIED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED)) - { - o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; - } - - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: dq %d-%d, symbols %d-%d, FIXED CHIP WITH X4 ECC STEER on %s", - 8*l_byte + 4*l_nibble, 8*l_byte + 4*l_nibble + 3,l_bad_symbol, l_bad_symbol+1, i_target.toEcmdString()); - } - - // Else if x4 chip mark not used yet - else if (!l_chip_mark_used) - { - - // If this is a bad deployed ECC spare, the chip mark goes on the nibble being steered - if ((l_port==1) && (l_byte==8) && (l_nibble == 1) && l_x4_ECC_spare_used) - { - // Find first symbol index of the nibble being steered with the ECC spare - - if(i_standby_flag) - { - mss_check_dummy_steering( - i_target, - 4*l_dimm + l_rank, - l_dramSparePort0Symbol, - l_dramSparePort1Symbol, - l_eccSpareSymbol, - l_steer); - } - else - { - - - l_rc = mss_check_steering( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_dramSparePort0Symbol, // don't care - l_dramSparePort1Symbol, // don't care - l_eccSpareSymbol); // first symbol index of the nibble being steered with the ECC spare - } - if (l_rc) - { - FAPI_ERR("Error reading steer mux %s.",i_target.toEcmdString()); - return l_rc; - } - - l_chip_mark = l_eccSpareSymbol; - FAPI_ERR("WARNING: bad deployed ECC spare, so chip mark goes on the nibble being steered, symbols %d-%d on %s", - l_chip_mark, l_chip_mark+1, i_target.toEcmdString()); - - } - - - // Else if this is a bad deployed DRAM spare, the chip mark goes on the nibble being steered - else if (((l_byte==9) && (l_nibble == 0) && l_x4_DRAM_spare_low_exists && l_x4_DRAM_spare_used) || - ((l_byte==9) && (l_nibble == 1) && l_x4_DRAM_spare_high_exists && l_x4_DRAM_spare_used)) - { - // Find first symbol index of the nibble being steered with the DRAM spare - if(i_standby_flag) - { - mss_check_dummy_steering( - i_target, - 4*l_dimm + l_rank, - l_dramSparePort0Symbol, - l_dramSparePort1Symbol, - l_eccSpareSymbol, - l_steer); - } - else - { - l_rc = mss_check_steering( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_dramSparePort0Symbol, // first symbol index of the nibble being steered with the port0 DRAM spare - l_dramSparePort1Symbol, // first symbol index of the nibble being steered with the port1 DRAM spare - l_eccSpareSymbol); // don't care - } - if (l_rc) - { - FAPI_ERR("Error reading steer mux %s.",i_target.toEcmdString()); - return l_rc; - } - - l_chip_mark = (l_port == 0) ? l_dramSparePort0Symbol:l_dramSparePort1Symbol; - FAPI_ERR("WARNING: bad deployed DRAM spare, so chip mark goes on the nibble being steered, symbols %d-%d on %s", - l_chip_mark, l_chip_mark+1, i_target.toEcmdString()); - } - - // Else this is not a bad deployed ECC or DRAM spare - else - { - l_chip_mark = mss_centaurDQ_to_symbol(8*l_byte + 4*l_nibble, l_port) - 1; - } - - // Update mark store - - if(i_standby_flag) - { - mss_put_dummy_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // MSS_INVALID_SYMBOL, since no symbol mark in x4 mode - l_chip_mark, // First symbol index of byte getting chip mark - l_mark_store); - } - else - { - - - l_rc = mss_put_mark_store( - - i_target, // MBA - 4*l_dimm + l_rank, // Master rank: 0-7 - l_symbol_mark, // MSS_INVALID_SYMBOL, since no symbol mark in x4 mode - l_chip_mark ); // First symbol index of byte getting chip mark - } - if (l_rc) - { - FAPI_ERR("Error updating markstore on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Chip mark now used on this rank - l_chip_mark_used = true; - - // Update which rank 0-7 has had repairs applied - o_repairs_applied |= l_repairs_applied_translation[4*l_dimm + l_rank]; - - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_APPLIED; - - // If port1 repairs applied and port0 had repairs exceeded, say port1 repairs exceeded too - if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_APPLIED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED)) - { - o_repairs_exceeded |= l_repairs_exceeded_translation[1][l_dimm]; - } - - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x", l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: dq %d-%d, symbols %d-%d, FIXED CHIP WITH X4 CHIP MARK on %s", - 8*l_byte + 4*l_nibble, 8*l_byte + 4*l_nibble + 3,l_chip_mark, l_chip_mark+1, i_target.toEcmdString()); - - } - - // Else, more bad bits than we can repair so update o_repairs_exceeded - else - { - o_repairs_exceeded |= l_repairs_exceeded_translation[l_port][l_dimm]; - - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_EXCEEDED; - - // If port1 repairs exceeded and port0 had a repair, say port0 repairs exceeded too - if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_APPLIED)) - { - o_repairs_exceeded |= l_repairs_exceeded_translation[0][l_dimm]; - } - - FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x",l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte]); - FAPI_ERR("WARNING: dq %d-%d, REPAIRS EXCEEDED %s", 8*l_byte + 4*l_nibble, 8*l_byte + 4*l_nibble + 3, i_target.toEcmdString()); - - // Break out of loop on nibbles - break; - } - } // End if nibble bad - } // End for each nibble - - // Break of of loop on bytes is we have already exceeded repairs on this port,dimm,rank - if (l_repair_status[l_port][l_dimm][l_rank]==MSS_REPAIRS_EXCEEDED) break; - - } // End for each byte - } // End x4 ECC - } // End loop on rank - - } // End if valid dimm - } // End loop on dimm - } // End loop on port - - - //Updating steer and mark_store arrays - - if(i_standby_flag) - { - for(l_rank =0;l_rank < 8;l_rank++) - { - for(l_index =0;l_index<3;l_index++) - { - if( l_index == 0) - { - if(l_steer[l_rank][l_index] != MSS_INVALID_SYMBOL) - { - o_repair_count.steer_count[l_rank] = o_repair_count.steer_count[l_rank] + 1; - } - } - if( l_index == 1) - { - if(l_steer[l_rank][l_index] != MSS_INVALID_SYMBOL) - { - o_repair_count.steer_count[l_rank] = o_repair_count.steer_count[l_rank] + 1; - } - - } - if( l_index == 2) - { - if(l_steer[l_rank][l_index] != MSS_INVALID_SYMBOL) - { - o_repair_count.chipmark_count[l_rank] = o_repair_count.chipmark_count[l_rank] + 1; - } - } - } - } - - for(l_rank =0;l_rank < 8;l_rank++) - { - for(l_index =0;l_index<2;l_index++) - { - if(l_index == 0) - { - if(l_mark_store[l_rank][l_index] != MSS_INVALID_SYMBOL) - { - o_repair_count.symbolmark_count[l_rank] = o_repair_count.symbolmark_count[l_rank] + 1; - } - } - if(l_index == 1) - { - if(l_mark_store[l_rank][l_index] != MSS_INVALID_SYMBOL) - { - o_repair_count.chipmark_count[l_rank] = o_repair_count.chipmark_count[l_rank] + 1; - } - } - } - } - } - for(l_rank =0;l_rank < 8;l_rank++) - { - FAPI_INF("\n\n\n RANK %d\n\n\n",l_rank); - FAPI_INF("\n \nSymbol mark count %d",o_repair_count.symbolmark_count[l_rank] ); - FAPI_INF("\n \nchip mark count %d",o_repair_count.chipmark_count[l_rank]) ; - FAPI_INF("\n \nsteer mark count %d",o_repair_count.steer_count[l_rank]) ; - FAPI_INF("_________________________________________________________"); - } - - - FAPI_INF("o_repairs_applied = %02x\n", o_repairs_applied); - FAPI_INF("o_repairs_exceeded = %02x\n", o_repairs_exceeded); - - FAPI_INF("EXIT mss_restore_DRAM_repairs()"); - - return l_rc; - - } - - - //------------------------------------------------------------------------------ - // mss_centaurDQ_to_symbol - //------------------------------------------------------------------------------ - - uint8_t mss_centaurDQ_to_symbol( uint8_t i_dq, uint8_t i_port ) - { - - uint8_t o_symbol = MSS_INVALID_SYMBOL; - - if ( 64 <= i_dq ) // DQs 64 - 71 - { - o_symbol = (71 - i_dq) / 2; // symbols 0 - 3 - if ( 0 == i_port ) o_symbol += 4; // symbols 4 - 7 - } - else // DQs 0 - 63 - { - o_symbol = (71 - i_dq + 8) / 2; // symbols 8 - 39 - if ( 0 == i_port ) o_symbol += 32; // symbols 40 - 71 - } - - return o_symbol; - } - - //------------------------------------------------------------------------------ - // mss_IPL_UE_isolation - //------------------------------------------------------------------------------ - - fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, - uint8_t i_rank, - uint8_t (&o_bad_bits)[2][10]) - - { - FAPI_INF("ENTER mss_IPL_UE_isolation()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - static const uint32_t maintBufferReadDataRegs[2][2][8]={ - - // UE trap 0: - // Port0 beat double word - {{MAINT0_MBA_MAINT_BUFF0_DATA0_0x03010655, // 0 DW0 - MAINT0_MBA_MAINT_BUFF2_DATA0_0x03010675, // 1 DW2 - MAINT0_MBA_MAINT_BUFF0_DATA1_0x03010656, // 2 DW4 - MAINT0_MBA_MAINT_BUFF2_DATA1_0x03010676, // 3 DW6 - MAINT0_MBA_MAINT_BUFF0_DATA2_0x03010657, // 4 DW8 - MAINT0_MBA_MAINT_BUFF2_DATA2_0x03010677, // 5 DW10 - MAINT0_MBA_MAINT_BUFF0_DATA3_0x03010658, // 6 DW12 - MAINT0_MBA_MAINT_BUFF2_DATA3_0x03010678},// 7 DW14 - - // Port1 - {MAINT0_MBA_MAINT_BUFF1_DATA0_0x03010665, // 0 DW1 - MAINT0_MBA_MAINT_BUFF3_DATA0_0x03010685, // 1 DW3 - MAINT0_MBA_MAINT_BUFF1_DATA1_0x03010666, // 2 DW5 - MAINT0_MBA_MAINT_BUFF3_DATA1_0x03010686, // 3 DW7 - MAINT0_MBA_MAINT_BUFF1_DATA2_0x03010667, // 4 DW9 - MAINT0_MBA_MAINT_BUFF3_DATA2_0x03010687, // 5 DW11 - MAINT0_MBA_MAINT_BUFF1_DATA3_0x03010668, // 6 DW13 - MAINT0_MBA_MAINT_BUFF3_DATA3_0x03010688}},//7 DW15 - - // UE trap 1: - // Port0 - {{MAINT0_MBA_MAINT_BUFF0_DATA4_0x03010659, // 0 DW0 - MAINT0_MBA_MAINT_BUFF2_DATA4_0x03010679, // 1 DW2 - MAINT0_MBA_MAINT_BUFF0_DATA5_0x0301065a, // 2 DW4 - MAINT0_MBA_MAINT_BUFF2_DATA5_0x0301067a, // 3 DW6 - MAINT0_MBA_MAINT_BUFF0_DATA6_0x0301065b, // 4 DW8 - MAINT0_MBA_MAINT_BUFF2_DATA6_0x0301067b, // 5 DW10 - MAINT0_MBA_MAINT_BUFF0_DATA7_0x0301065c, // 6 DW12 - MAINT0_MBA_MAINT_BUFF2_DATA7_0x0301067c},// 7 DW14 - - // Port1 - {MAINT0_MBA_MAINT_BUFF1_DATA4_0x03010669, // 0 DW1 - MAINT0_MBA_MAINT_BUFF3_DATA4_0x03010689, // 1 DW3 - MAINT0_MBA_MAINT_BUFF1_DATA5_0x0301066a, // 2 DW5 - MAINT0_MBA_MAINT_BUFF3_DATA5_0x0301068a, // 3 DW7 - MAINT0_MBA_MAINT_BUFF1_DATA6_0x0301066b, // 4 DW9 - MAINT0_MBA_MAINT_BUFF3_DATA6_0x0301068b, // 5 DW11 - MAINT0_MBA_MAINT_BUFF1_DATA7_0x0301066c, // 6 DW13 - MAINT0_MBA_MAINT_BUFF3_DATA7_0x0301068c}}};//7 DW15 - - - static const uint32_t maintBufferRead65thByteRegs[2][4]={ - // UE trap 0 - {MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC0_0x03010695, - MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC1_0x03010696, - MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC2_0x03010697, - MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC3_0x03010698}, - // UE trap 1 - {MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC4_0x03010699, - MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC5_0x0301069a, - MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC6_0x0301069b, - MAINT0_MBA_MAINT_BUFF_65TH_BYTE_64B_ECC7_0x0301069c}}; - - - uint8_t l_UE_trap = 0; // 0,1, since UE can be in 1st or 2nd half of buffer - uint8_t l_port = 0; // 0,1 - uint8_t l_beat = 0; // 0-7 - uint8_t l_byte = 0; // 0-9 - uint8_t l_nibble = 0; // 0-17 - uint8_t l_loop = 0; - ecmdDataBufferBase l_data(64); - ecmdDataBufferBase l_UE_trap0_signature(64); - ecmdDataBufferBase l_UE_trap1_signature(64); - ecmdDataBufferBase l_mbmmr(64); - ecmdDataBufferBase l_mbmct(64); - ecmdDataBufferBase l_mbstr(64); - uint8_t l_initPattern = 0; - uint8_t l_cmd_type = 0; - fapi::Target l_targetCentaur; - uint8_t l_mbaPosition = 0; - uint32_t l_tmp_data_diff[2]; - uint8_t l_tag_MDI = 0; - uint8_t l_tmp_65th_byte_diff = 0; - ecmdDataBufferBase l_diff(64); - uint32_t l_ECC = 0; - uint32_t l_tmp_ECC_diff = 0; - ecmdDataBufferBase l_ECC_diff(32); - uint8_t l_ECC_c6_c5_c4_01 = 0; - uint8_t l_ECC_c6_c5_c4_23 = 0; - uint8_t l_ECC_c3_c2_c1_c0_01 = 0; - uint8_t l_ECC_c3_c2_c1_c0_23 = 0; - uint8_t l_dramSparePort0Symbol = MSS_INVALID_SYMBOL; - uint8_t l_dramSparePort1Symbol = MSS_INVALID_SYMBOL; - uint8_t l_eccSpareSymbol = MSS_INVALID_SYMBOL; - uint8_t l_dramWidth = 0; - - - //---------------------------------------------------- - // Get l_dramWidth - //---------------------------------------------------- - l_rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dramWidth); - if(l_rc) - { - FAPI_ERR("Error getting DRAM width on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Convert from attribute enum values: 8,4 to index values: 0,1 - if(l_dramWidth == mss_MemConfig::X8) - { - l_dramWidth = 0; - } - else - { - l_dramWidth = 1; - } - - //---------------------------------------------------- - // Initialize o_bad_bits - //---------------------------------------------------- - - for(l_port=0; l_port<2; l_port++ ) - { - for(l_byte=0; l_byte<10; l_byte++ ) - { - o_bad_bits[l_port][l_byte] = 0; - } - } - - - //---------------------------------------------------- - // Get the expected pattern (stored in mbmmr reg) - //---------------------------------------------------- - - // Get Centaur target for the given MBA - l_rc = fapiGetParentChip(i_target, l_targetCentaur); - if(l_rc) - { - FAPI_ERR("Error getting Centaur parent target for the given MBA, on %s.",i_target.toEcmdString()); - return l_rc; - } - - // Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString()); - return l_rc; - } - - // MBMMR[4:7] contains the pattern index - l_rc = fapiGetScom(l_targetCentaur, mss_mbmmr[l_mbaPosition], l_mbmmr); - if(l_rc) return l_rc; - l_ecmd_rc |= l_mbmmr.extractPreserve(&l_initPattern, 4, 4, 8-4); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // MBMCT[0:4] contains the cmd type - l_rc = fapiGetScom(i_target, MBA01_MBMCTQ_0x0301060A, l_mbmct); - if(l_rc) return l_rc; - l_ecmd_rc |= l_mbmct.extractPreserve(&l_cmd_type, 0, 5, 8-5); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // No isolation if cmd is timebased steer cleanup - if (l_cmd_type == 2) - { - FAPI_ERR("WARNING: rank%d maint UE during steer cleanup - no bad bit isolation possible on %s.", i_rank, i_target.toEcmdString()); - return l_rc; - } - - // No isolation if pattern is random - if (l_initPattern == 8) - { - FAPI_ERR("WARNING: rank%d maint UE with random pattern - no bad bit isolation possible on %s.", i_rank, i_target.toEcmdString()); - return l_rc; - } - - - FAPI_INF("Expected pattern%d = 0x%.8X 0x%.8X",l_initPattern, - mss_maintBufferData[l_dramWidth][l_initPattern][0][0], - mss_maintBufferData[l_dramWidth][l_initPattern][0][1]); - - //---------------------------------------------------- - // Figure out which half of the buffer has the UE... - // Remember we had to first load the buffers with - // a hex signatue, and whichever gets overwritten - // has a UE trapped - //---------------------------------------------------- - l_rc = fapiGetScom(i_target, MAINT0_MBA_MAINT_BUFF0_DATA0_0x03010655, l_UE_trap0_signature); - if(l_rc) return l_rc; - - l_rc = fapiGetScom(i_target, MAINT0_MBA_MAINT_BUFF0_DATA4_0x03010659, l_UE_trap1_signature); - if(l_rc) return l_rc; - - // UE may be trapped in both halves of the buffer, - // but we will only use one. - if ((l_UE_trap0_signature.getWord(0) != 0xFACEB00C) && - (l_UE_trap0_signature.getWord(0) != 0xD15C0DAD)) - { - FAPI_INF("UE trapped in 1st half of maint buffer"); - l_UE_trap = 0; - } - else if ((l_UE_trap1_signature.getWord(0) != 0xFACEB00C) && - (l_UE_trap1_signature.getWord(0) != 0xD15C0DAD)) - { - FAPI_INF("UE trapped in 2nd half of maint buffer"); - l_UE_trap = 1; - } - else - { - FAPI_ERR("IPL UE trapping didn't work on i_rank = %d on %s.", i_rank, i_target.toEcmdString()); - - // Read for FFDC: MBSTR[59]: UE trap enable bit - l_rc = fapiGetScom(l_targetCentaur, mss_mbstr[l_mbaPosition], l_mbstr); - if(l_rc) return l_rc; - - - // Calling out MBA target high, deconfig, gard - const fapi::Target & MBA = i_target; - // FFDC: Capture UE trap contents - ecmdDataBufferBase & UE_TRAP0 = l_UE_trap0_signature; - ecmdDataBufferBase & UE_TRAP1 = l_UE_trap1_signature; - // FFDC: MBMCT[0:4] contains the cmd type - ecmdDataBufferBase & MBMCT = l_mbmct; - // FFDC: MBMMR[4:7] contains the pattern index - ecmdDataBufferBase & MBMMR = l_mbmmr; - // FFDC: MBSTR[59]: UE trap enable bit - ecmdDataBufferBase & MBSTR = l_mbstr; - - // Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_UE_TRAP); - - return l_rc; - } - - - - //---------------------------------------------------- - // DATA: Do XOR of expected and actual data to find stuck bits - //---------------------------------------------------- - - for(l_port=0; l_port<2; l_port++ ) - { - l_tmp_data_diff[0] = 0; - l_tmp_data_diff[1] = 0; - - FAPI_INF("port%d", l_port); - for(l_beat=0; l_beat<8; l_beat++ ) - { - - l_rc = fapiGetScom(i_target, maintBufferReadDataRegs[l_UE_trap][l_port][l_beat], l_data); - if(l_rc) return l_rc; - FAPI_INF("Actual data, beat%d: 0x%.8X 0x%.8X", l_beat, l_data.getWord(0), l_data.getWord(1)); - - FAPI_INF("Expected pattern%d = 0x%.8X 0x%.8X",l_initPattern, - mss_maintBufferData[l_dramWidth][l_initPattern][l_port*8 + l_beat][0], - mss_maintBufferData[l_dramWidth][l_initPattern][l_port*8 + l_beat][1]); - - // DO XOR of actual and expected data, and OR the result together for all 8 beats - l_tmp_data_diff[0] |= l_data.getWord(0) ^ mss_maintBufferData[l_dramWidth][l_initPattern][l_port*8 + l_beat][0]; - l_tmp_data_diff[1] |= l_data.getWord(1) ^ mss_maintBufferData[l_dramWidth][l_initPattern][l_port*8 + l_beat][1]; - - FAPI_INF("***************************************** l_tmp_diff: 0x%.8X 0x%.8X", l_tmp_data_diff[0], l_tmp_data_diff[1]); - } - - // Put l_tmp_diff into a ecmdDataBufferBase to make it easier - // to get into o_bad_bits - l_ecmd_rc |= l_diff.insert(l_tmp_data_diff[0], 0, 32, 0); - l_ecmd_rc |= l_diff.insert(l_tmp_data_diff[1], 32, 32, 0); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - for(l_byte=0; l_byte<8; l_byte++ ) - { - l_ecmd_rc |= l_diff.extractPreserve(&o_bad_bits[l_port][l_byte], 8*l_byte, 8, 0); - } - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - } // End loop on ports - - - - //---------------------------------------------------- - // 65th byte: Do XOR of expected and actual 65th byte to find stuck bits - //---------------------------------------------------- - - for(l_loop=0; l_loop<4; l_loop++ ) - { - l_tag_MDI = 0; - l_tmp_65th_byte_diff = 0; - - l_rc = fapiGetScom(i_target, maintBufferRead65thByteRegs[l_UE_trap][l_loop], l_data); - if(l_rc) return l_rc; - - // Grab bit 0 = Checkbit0_1 - // Grab bit 1 = Tag0_2 - // Grab bit 2 = Tag1_3 - // Grab bit 3 = MDI - l_ecmd_rc |= l_data.extractPreserve(&l_tag_MDI, 0, 4, 0); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - FAPI_INF("Actual: bit0 (Checkbit0_1), bit1(Tag0_2), bit2(Tag1_3), bit3(MDI) = 0x%.2X", l_tag_MDI); - - FAPI_INF("Expected: bit0 (Checkbit0_1), bit1(Tag0_2), bit2(Tag1_3), bit3(MDI) = 0x%.2X", mss_65thByte[l_dramWidth][l_initPattern][l_loop]); - - // DO XOR of actual and expected data - l_tmp_65th_byte_diff = l_tag_MDI ^ mss_65thByte[l_dramWidth][l_initPattern][l_loop]; - FAPI_INF("***************************************** l_tmp_65th_byte_diff: 0x%.2X", l_tmp_65th_byte_diff); - - - // Check for mismatch in bit 0: Checkbit0_1 - if (l_tmp_65th_byte_diff & 0x80) - { - // Checkbit0_1 maps to port0 bit 64, which is on byte8 - o_bad_bits[0][8] |= 0x80; - } - - // Check for mismatch in bit 1: Tag0_2 - if (l_tmp_65th_byte_diff & 0x40) - { - // Tag0_2 maps to port0 bit 65, which is on byte8 - o_bad_bits[0][8] |= 0x40; - } - - // Check for mismatch in bit 2: Tag1_3 - if (l_tmp_65th_byte_diff & 0x20) - { - // Tag1_3 maps to port0 bit 64, which is on byte8 - o_bad_bits[0][8] |= 0x80; - } - - // Check for mismatch in bit 3: MDI - if (l_tmp_65th_byte_diff & 0x10) - { - // MDI maps to port0 bit 65, which is on byte8 - o_bad_bits[0][8] |= 0x40; - } - } // End loops through trapped 65th byte info - - - //---------------------------------------------------- - // ECC: Do XOR of expected and actual ECC bits to find stuck bits - //---------------------------------------------------- - - for(l_loop=0; l_loop<4; l_loop++ ) - { - l_ECC = 0; - - l_rc = fapiGetScom(i_target, maintBufferRead65thByteRegs[l_UE_trap][l_loop], l_data); - if(l_rc) return l_rc; - - // Grab bits 4:15 = ECC_c6_c5_c4, and bits 16:31 = ECC_c3_c2_c1_c0 - l_ecmd_rc |= l_data.extractPreserve(&l_ECC, 4, 28, 4); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - FAPI_INF("Actual: ECC = 0x%.8X", l_ECC); - - FAPI_INF("Expected: ECC = 0x%.8X", mss_ECC[l_dramWidth][l_initPattern][l_loop]); - - // DO XOR of actual and expected data - l_tmp_ECC_diff |= l_ECC ^ mss_ECC[l_dramWidth][l_initPattern][l_loop]; - FAPI_INF("***************************************** l_tmp_ECC_diff: 0x%.8X", l_tmp_ECC_diff); - } - - // Put l_tmp_ECC_diff into a ecmdDataBufferBase to make it easier - // to get into o_bad_bits - l_ecmd_rc |= l_ECC_diff.insert(l_tmp_ECC_diff, 0, 32, 0); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - l_ecmd_rc |= l_ECC_diff.extractPreserve(&l_ECC_c6_c5_c4_01, 4, 6, 8-6); - l_ecmd_rc |= l_ECC_diff.extractPreserve(&l_ECC_c6_c5_c4_23, 10, 6, 8-6); - l_ecmd_rc |= l_ECC_diff.extractPreserve(&l_ECC_c3_c2_c1_c0_01, 16, 8, 0); - l_ecmd_rc |= l_ECC_diff.extractPreserve(&l_ECC_c3_c2_c1_c0_23, 24, 8, 0); - if(l_ecmd_rc) - { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // The 6 bits of ECC_c6_c5_c4 maps to byte8 on port0 - o_bad_bits[0][8] |= l_ECC_c6_c5_c4_01 | l_ECC_c6_c5_c4_23; - // The 8 bits of ECC_c3_c2_c1_c0 maps to byte8 byte on port1 - o_bad_bits[1][8] |= l_ECC_c3_c2_c1_c0_01 | l_ECC_c3_c2_c1_c0_23; - - - //---------------------------------------------------- - // Spare: Mark byte9 bad if bad bits found in position being steered - //---------------------------------------------------- - - // READ steer mux, which gets me a symbol for port0 and port1 - l_rc = mss_check_steering(i_target, - i_rank, - l_dramSparePort0Symbol, - l_dramSparePort1Symbol, - l_eccSpareSymbol); - if(l_rc) return l_rc; - - - //---------------------------- - // x8 - //---------------------------- - if (l_dramWidth == 0) - { - // If steering on port0 - if ( l_dramSparePort0Symbol != 0xff) - { - // Find the byte being steered - l_byte = mss_x8_chip_mark_to_centaurDQ[l_dramSparePort0Symbol/4][0]/8; - - // If that byte has any bad bits in it, copy them to byte9, - if (o_bad_bits[0][l_byte]) - { - o_bad_bits[0][9] = o_bad_bits[0][l_byte]; - - // Clear byte being steered, since it did not contribute to UE - o_bad_bits[0][l_byte] = 0; - } - } - - // If steering on port1 - if ( l_dramSparePort1Symbol != 0xff) - { - // Find the byte being steered - l_byte = mss_x8_chip_mark_to_centaurDQ[l_dramSparePort1Symbol/4][0]/8; - - // If that byte has any bad bits in it, copy them to byte9, - if (o_bad_bits[1][l_byte]) - { - o_bad_bits[1][9] = o_bad_bits[1][l_byte]; - - // Clear byte being steered, since it did not contribute to UE - o_bad_bits[1][l_byte] = 0; - } - } - } - - //---------------------------- - // x4 - //---------------------------- - else - { - // If steering on port0 - if ( l_dramSparePort0Symbol != 0xff) - { - // Find the nibble being steered (0-17) - l_nibble = mss_x4_chip_mark_to_centaurDQ[l_dramSparePort0Symbol/2][0]/4; - - // If odd nibble (1,3,5,7,9,11,13,15,17) - if (l_nibble % 2) - { - // If that nibble has any bad bits in it, copy them to byte9, - if (o_bad_bits[0][l_nibble/2] & 0x0f) - { - o_bad_bits[0][9] = (o_bad_bits[0][l_nibble/2] << 4) & 0xf0; - - // Clear nibble being steered, since it did not contribute to UE - o_bad_bits[0][l_nibble/2] &= 0xf0; - } - } - - // Else even nibble (0,2,4,6,8,10,12,14,16) - else - { - // If that nibble has any bad bits in it, copy them to byte9, - if (o_bad_bits[0][l_nibble/2] & 0xf0) - { - o_bad_bits[0][9] = o_bad_bits[0][l_nibble/2] & 0xf0; - - // Clear nibble being steered, since it did not contribute to UE - o_bad_bits[0][l_nibble/2] &= 0x0f; - } - } - } - - // If steering on port1 - if ( l_dramSparePort1Symbol != 0xff) - { - // Find the nibble being steered (0-17) - l_nibble = mss_x4_chip_mark_to_centaurDQ[l_dramSparePort1Symbol/2][0]/4; - - // If odd nibble (1,3,5,7,9,11,13,15,17) - if (l_nibble % 2) - { - // If that nibble has any bad bits in it, copy them to byte9, - if (o_bad_bits[1][l_nibble/2] & 0x0f) - { - o_bad_bits[1][9] = (o_bad_bits[1][l_nibble/2] << 4) & 0xf0; - - // Clear nibble being steered, since it did not contribute to UE - o_bad_bits[1][l_nibble/2] &= 0xf0; - } - } - - // Else even nibble (0,2,4,6,8,10,12,14,16) - else - { - // If that nibble has any bad bits in it, copy them to byte9, - if (o_bad_bits[1][l_nibble/2] & 0xf0) - { - o_bad_bits[1][9] = o_bad_bits[1][l_nibble/2] & 0xf0; - - // Clear nibble being steered, since it did not contribute to UE - o_bad_bits[1][l_nibble/2] &= 0x0f; - } - } - } - - - // If ecc spare used - if ( l_eccSpareSymbol != 0xff) - { - // Find the nibble being steered (0-17) - l_nibble = mss_x4_chip_mark_to_centaurDQ[l_eccSpareSymbol/2][0]/4; - - // Find the port being steered (0,1) - l_port = mss_x4_chip_mark_to_centaurDQ[l_eccSpareSymbol/2][1]; - - // If odd nibble (1,3,5,7,9,11,13,15,17) - if (l_nibble % 2) - { - // If that nibble has any bad bits in it, copy them to port1,nibble 17 - if (o_bad_bits[l_port][l_nibble/2] & 0x0f) - { - o_bad_bits[1][8] |= o_bad_bits[l_port][l_nibble/2] & 0x0f; - - // Clear nibble being steered, since it did not contribute to UE - o_bad_bits[l_port][l_nibble/2] &= 0xf0; - } - } - - // Else even nibble (0,2,4,6,8,10,12,14,16) - else - { - // If that nibble has any bad bits in it, copy them to port1,nibble 17 - if (o_bad_bits[l_port][l_nibble/2] & 0xf0) - { - o_bad_bits[1][8] |= (o_bad_bits[l_port][l_nibble/2] >> 4) & 0x0f; - - // Clear nibble being steered, since it did not contribute to UE - o_bad_bits[l_port][l_nibble/2] &= 0x0f; - } - } - } - } - - - - //---------------------------------------------------- - // Show results - //---------------------------------------------------- - - FAPI_ERR("WARNING: IPL UE isolation results for rank = %d on %s.", i_rank, i_target.toEcmdString()); - FAPI_ERR("WARNING: Expected pattern = 0x%.8X", mss_maintBufferData[l_dramWidth][l_initPattern][0][0]); - for(l_port=0; l_port<2; l_port++ ) - { - for(l_byte=0; l_byte<10; l_byte++ ) - { - FAPI_ERR("WARNING: o_bad_bits[port%d][byte%d] = %02x", - l_port, l_byte, o_bad_bits[l_port][l_byte]); - } - } - - - FAPI_INF("EXIT mss_IPL_UE_isolation()"); - - return l_rc; - - - } - - //------------------------------------------------------------------------------ - // mss_get_dummy_mark_store - //------------------------------------------------------------------------------ - void mss_get_dummy_mark_store( const fapi::Target & i_target, - uint8_t i_rank, - uint8_t & o_symbolMark, - uint8_t & o_chipMark, - uint8_t mark_store[8][2]) - { - - FAPI_INF("ENTER mss_get_dummy_mark_store(), i_rank = %d", i_rank); - - o_symbolMark = mark_store[i_rank][0]; - o_chipMark = mark_store[i_rank][1]; - - FAPI_INF("EXIT mss_get_dummy_mark_store(): o_symbolMark = %d, o_chipMark = %d", - o_symbolMark, o_chipMark); - } - - - //------------------------------------------------------------------------------ - // mss_put_dummy_mark_store - //------------------------------------------------------------------------------ - void mss_put_dummy_mark_store( const fapi::Target & i_target, - uint8_t i_rank, - uint8_t i_symbolMark, - uint8_t i_chipMark, - uint8_t mark_store[8][2]) - { - FAPI_INF("ENTER mss_put_dummy_mark_store(): i_rank = %d, i_symbolMark = %d, i_chipMark = %d", - i_rank, i_symbolMark, i_chipMark ); - - mark_store[i_rank][0] = i_symbolMark; - mark_store[i_rank][1] = i_chipMark; - - FAPI_INF("EXIT mss_put_dummy_mark_store()"); - } - - - - //------------------------------------------------------------------------------ - // mss_get_dummy_steer_mux - //------------------------------------------------------------------------------ - void mss_get_dummy_steer_mux( const fapi::Target & i_target, - uint8_t i_rank, - mss_SteerMux::muxType i_muxType, - uint8_t & o_dramSparePort0Symbol, - uint8_t & o_dramSparePort1Symbol, - uint8_t & o_eccSpareSymbol, - uint8_t steer[8][3]) - { - - FAPI_INF("ENTER mss_get_dummy_steer_mux(): i_rank = %d", i_rank ); - - o_dramSparePort0Symbol = steer[i_rank][0]; - o_dramSparePort1Symbol = steer[i_rank][1]; - o_eccSpareSymbol = steer[i_rank][2]; - - FAPI_INF("EXIT mss_get_dummy_steer_mux(): port0 steer = %d, port1 steer = %d, ecc steer = %d", - o_dramSparePort0Symbol, o_dramSparePort1Symbol, o_eccSpareSymbol ); - } - - - //------------------------------------------------------------------------------ - // mss_put_dummy_steer_mux - //------------------------------------------------------------------------------ - void mss_put_dummy_steer_mux( const fapi::Target & i_target, - uint8_t i_rank, - mss_SteerMux::muxType i_muxType, - uint8_t i_steerType, - uint8_t i_symbol, - uint8_t steer[8][3]) - { - FAPI_INF("ENTER mss_put_dummy_steer_mux(): i_rank = %d, i_steerType = %d, i_symbol = %d", - i_rank, i_steerType, i_symbol ); - - steer[i_rank][i_steerType] = i_symbol; - - - FAPI_INF("EXIT mss_put_dummy_steer_mux()"); - } - - - //------------------------------------------------------------------------------ - // mss_check_dummy_steering - //------------------------------------------------------------------------------ - void mss_check_dummy_steering(const fapi::Target & i_target, - uint8_t i_rank, - uint8_t & o_dramSparePort0Symbol, - uint8_t & o_dramSparePort1Symbol, - uint8_t & o_eccSpareSymbol, - uint8_t steer[8][3]) - - { - // Get the read steer mux, with the assuption - // that the write mux will be the same. - mss_get_dummy_steer_mux( i_target, - i_rank, - mss_SteerMux::READ_MUX, - o_dramSparePort0Symbol, - o_dramSparePort1Symbol, - o_eccSpareSymbol, - steer); - - - } - diff --git a/src/usr/hwpf/hwp/utility_procedures/mss_unmask_errors.C b/src/usr/hwpf/hwp/utility_procedures/mss_unmask_errors.C deleted file mode 100644 index 39a625470..000000000 --- a/src/usr/hwpf/hwp/utility_procedures/mss_unmask_errors.C +++ /dev/null @@ -1,3584 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/utility_procedures/mss_unmask_errors.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_unmask_errors.C,v 1.10 2015/02/12 22:07:20 gollub Exp $ -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Date: | Author: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.1 | 09/05/12 | gollub | Created -// 1.2 | 01/31/13 | gollub | Keeping maint UE/MPE, and MBSPA threshold -// | | | errors masked until mss_unmask_fetch_errors, -// | | | so they will be masked during memdiags, and -// | | | unmasked before scrub is started. -// 1.3 | 03/08/13 | gollub | Masking MBSPA[0] for DD1, and using MBSPA[8] instead. -// 1.4 | 10/22/13 | gollub | Keep maint ECC errors masked, since PRD intends -// | | | to use cmd complete attention instead. -// 1.5 | 10/31/13 | gollub | For DD1 use MBSPA[8], for DD2 using MBSPA[0]. -// 1.6 | 10/03/14 | gollub | Unmkask MBS_FIR_REG[15]: dir_ce for DD2 only -// 1.7 |07-APR-14 | gollub | Added mss_unmask_pervasive_errors -// | | | TP_PERV_LFIR: 0,13,14 change to recoverable unmask -// | | | NEST_PERV_LFIR: 0 changed to recoverable unmask -// | | | MEM_PERV_LFIR: 0 changed to recoverable unmask -// | | | -// | | | MBS_FIR_REG: 29,30 change to recoverable unmask -// | | | MBECCFIR: 48,50,51 change to recoverable unmask -// | | | MBSFIR: 15,16 change to recoverable unmask -// | | | SCAC_LFIR: 35,35 change to recoverable unmask -// | | | MBAFIR 7 changed to channel checkstop -// | | | MBAFIR 15,16 change to recoverable unmask -// | | | DDRPHY_FIR_REG 53 change to recoverable unmask -// | | | MBACALFIR 19,20,21 change to recoverable unmask -// | | | -// | | | MBS_FIR_REG 6 changed to channel checkstop -// | | | MBSFIR 0 changed to channel checkstop -// | | | MBAFIR 3,5 changed to channel checkstop -// | | | MBACALFIR 13,18 changed to channel checkstop -// | | | -// | | | New DD2: MBS_FIR_REG 29 recoverable masked -// | | | New DD2: MBS_FIR_REG 30 channel checkstop unmasked -// | | | New DD2: MBSFIR 2 recoverable masked -// | | | New DD2: MBSFIR 3 recoverable masked -// | | | New DD2: MBAFIR 8 channel checkstop unmasked -// | | | New DD2: MBACALFIR 20,21,22 recoverable masked -// 1.8 |08-APR-14 | gollub | Removed debug trace -// 1.9 |29-AUG-14 | gollub | SW275672: Changed MBS_FIR_REG[3][4] from channel checkstop to recoverable -// 1.10 |12-FEB-15 | gollub | Updated mss_unmask_draminit_errors: unmask RCD parity errors if RDIMM or LRDIMM -// | | | Updated mss_unmask_fetch_errors: load max_cfg_rcd_protection_time and enable RCD recovery if RDIMM or LRDIMM - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <mss_unmask_errors.H> -#include <cen_scom_addresses.H> -using namespace fapi; - - -//------------------------------------------------------------------------------ -// Constants and enums -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// mss_unmask_pervasive_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_pervasive_errors( const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - FAPI_INF("ENTER mss_unmask_pervasive_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - //************************* - //************************* - // TP_PERV_LFIR - //************************* - //************************* - - ecmdDataBufferBase l_tp_perv_lfir_mask_or(64); - ecmdDataBufferBase l_tp_perv_lfir_mask_and(64); - ecmdDataBufferBase l_tp_perv_lfir_action0(64); - ecmdDataBufferBase l_tp_perv_lfir_action1(64); - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - - // Read action0 - l_rc = fapiGetScom_w_retry(i_target, TP_PERV_LFIR_ACT0_0x01040010, l_tp_perv_lfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Read action1 - l_rc = fapiGetScom_w_retry(i_target, TP_PERV_LFIR_ACT1_0x01040011, l_tp_perv_lfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - l_ecmd_rc |= l_tp_perv_lfir_mask_or.flushTo0(); - l_ecmd_rc |= l_tp_perv_lfir_mask_and.flushTo1(); - - // 0 CFIR internal parity error recoverable unmask - l_ecmd_rc |= l_tp_perv_lfir_action0.clearBit(0); - l_ecmd_rc |= l_tp_perv_lfir_action1.setBit(0); - l_ecmd_rc |= l_tp_perv_lfir_mask_and.clearBit(0); - - // 1 GPIO (PCB error) recoverable mask (forever) - // 2 CC (PCB error) recoverable mask (forever) - // 3 CC (OPCG, parity, scan collision) recoverable mask (forever) - // 4 PSC (PCB error) recoverable mask (forever) - // 5 PSC (parity error) recoverable mask (forever) - // 6 Thermal (parity error) recoverable mask (forever) - // 7 Thermal (PCB error) recoverable mask (forever) - // 8 Thermal (critical Trip error) recoverable mask (forever) - // 9 Thermal (fatal Trip error) recoverable mask (forever) - // 10 Thermal (Voltage trip error) recoverable mask (forever) - // 11 Trace Array recoverable mask (forever) - // 12 Trace Array recoverable mask (forever) - l_ecmd_rc |= l_tp_perv_lfir_action0.clearBit(1,12); - l_ecmd_rc |= l_tp_perv_lfir_action1.setBit(1,12); - l_ecmd_rc |= l_tp_perv_lfir_mask_or.setBit(1,12); - - // 13 ITR recoverable unmask - l_ecmd_rc |= l_tp_perv_lfir_action0.clearBit(13); - l_ecmd_rc |= l_tp_perv_lfir_action1.setBit(13); - l_ecmd_rc |= l_tp_perv_lfir_mask_and.clearBit(13); - - // 14 ITR recoverable unmask - l_ecmd_rc |= l_tp_perv_lfir_action0.clearBit(14); - l_ecmd_rc |= l_tp_perv_lfir_action1.setBit(14); - l_ecmd_rc |= l_tp_perv_lfir_mask_and.clearBit(14); - - - // 15 ITR (itr_tc_pcbsl_slave_fir_err) recoverable mask (forever) - // 16 PIB recoverable mask (forever) - // 17 PIB recoverable mask (forever) - // 18 PIB recoverable mask (forever) - l_ecmd_rc |= l_tp_perv_lfir_action0.clearBit(15,4); - l_ecmd_rc |= l_tp_perv_lfir_action1.setBit(15,4); - l_ecmd_rc |= l_tp_perv_lfir_mask_or.setBit(15,4); - - - // NOTE: 19 and 20 already cleared and unmasked in cen_mem_pll_setup.C - // 19 nest PLLlock recoverable unmask - // 20 mem PLLlock recoverable unmask - - // 21:39 unused local errors recoverable mask (forever) - // 40 local xstop in another chiplet recoverable mask (forever) - l_ecmd_rc |= l_tp_perv_lfir_action0.clearBit(21,20); - l_ecmd_rc |= l_tp_perv_lfir_action1.setBit(21,20); - l_ecmd_rc |= l_tp_perv_lfir_mask_or.setBit(21,20); - - // 41:63 Reserved not implemented, so won't touch these - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, TP_PERV_LFIR_ACT0_0x01040010, l_tp_perv_lfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, TP_PERV_LFIR_ACT1_0x01040011, l_tp_perv_lfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, TP_PERV_LFIR_MASK_OR_0x0104000F, l_tp_perv_lfir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, TP_PERV_LFIR_MASK_AND_0x0104000E, l_tp_perv_lfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************* - //************************* - // NEST_PERV_LFIR - //************************* - //************************* - - ecmdDataBufferBase l_nest_perv_lfir_mask_or(64); - ecmdDataBufferBase l_nest_perv_lfir_mask_and(64); - ecmdDataBufferBase l_nest_perv_lfir_action0(64); - ecmdDataBufferBase l_nest_perv_lfir_action1(64); - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_nest_perv_lfir_action0.flushTo0(); - l_ecmd_rc |= l_nest_perv_lfir_action1.flushTo0(); - l_ecmd_rc |= l_nest_perv_lfir_mask_or.flushTo0(); - l_ecmd_rc |= l_nest_perv_lfir_mask_and.flushTo1(); - - // 0 CFIR internal parity error recoverable unmask - l_ecmd_rc |= l_nest_perv_lfir_action0.clearBit(0); - l_ecmd_rc |= l_nest_perv_lfir_action1.setBit(0); - l_ecmd_rc |= l_nest_perv_lfir_mask_and.clearBit(0); - - // 1 GPIO (PCB error) recoverable mask (forever) - // 2 CC (PCB error) recoverable mask (forever) - // 3 CC (OPCG, parity, scan collision) recoverable mask (forever) - // 4 PSC (PCB error) recoverable mask (forever) - // 5 PSC (parity error) recoverable mask (forever) - // 6 Thermal (parity error) recoverable mask (forever) - // 7 Thermal (PCB error) recoverable mask (forever) - // 8 Thermal (critical Trip error) recoverable mask (forever) - // 9 Thermal (fatal Trip error) recoverable mask (forever) - // 10 Thermal (Voltage trip error) recoverable mask (forever) - // 11 Trace Array recoverable mask (forever) - // 12 Trace Array recoverable mask (forever) - // 13:39 unused local errors recoverable mask (forever) - // 40 local xstop in another chiplet recoverable mask (forever) - l_ecmd_rc |= l_nest_perv_lfir_action0.clearBit(1,40); - l_ecmd_rc |= l_nest_perv_lfir_action1.setBit(1,40); - l_ecmd_rc |= l_nest_perv_lfir_mask_or.setBit(1,40); - - // 41:63 Reserved not implemented, so won't touch these - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, NEST_PERV_LFIR_ACT0_0x02040010, l_nest_perv_lfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, NEST_PERV_LFIR_ACT1_0x02040011, l_nest_perv_lfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, NEST_PERV_LFIR_MASK_OR_0x0204000F, l_nest_perv_lfir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, NEST_PERV_LFIR_MASK_AND_0x0204000E, l_nest_perv_lfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************* - //************************* - // MEM_PERV_LFIR - //************************* - //************************* - - ecmdDataBufferBase l_mem_perv_lfir_mask_or(64); - ecmdDataBufferBase l_mem_perv_lfir_mask_and(64); - ecmdDataBufferBase l_mem_perv_lfir_action0(64); - ecmdDataBufferBase l_mem_perv_lfir_action1(64); - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mem_perv_lfir_action0.flushTo0(); - l_ecmd_rc |= l_mem_perv_lfir_action1.flushTo0(); - l_ecmd_rc |= l_mem_perv_lfir_mask_or.flushTo0(); - l_ecmd_rc |= l_mem_perv_lfir_mask_and.flushTo1(); - - // 0 CFIR internal parity error recoverable unmask - l_ecmd_rc |= l_mem_perv_lfir_action0.clearBit(0); - l_ecmd_rc |= l_mem_perv_lfir_action1.setBit(0); - l_ecmd_rc |= l_mem_perv_lfir_mask_and.clearBit(0); - - // 1 GPIO (PCB error) recoverable mask (forever) - // 2 CC (PCB error) recoverable mask (forever) - // 3 CC (OPCG, parity, scan collision) recoverable mask (forever) - // 4 PSC (PCB error) recoverable mask (forever) - // 5 PSC (parity error) recoverable mask (forever) - // 6 Thermal (parity error) recoverable mask (forever) - // 7 Thermal (PCB error) recoverable mask (forever) - // 8 Thermal (critical Trip error) recoverable mask (forever) - // 9 Thermal (fatal Trip error) recoverable mask (forever) - // 10 Thermal (Voltage trip error) recoverable mask (forever) - // 11 mba01 Trace Array recoverable mask (forever) - // 12 mba01 Trace Array recoverable mask (forever) - // 13 mba23 Trace Array recoverable mask (forever) - // 14 mba23 Trace Array recoverable mask (forever) - // 15:39 unused local errors recoverable mask (forever) - // 40 local xstop in another chiplet recoverable mask (forever) - l_ecmd_rc |= l_mem_perv_lfir_action0.clearBit(1,40); - l_ecmd_rc |= l_mem_perv_lfir_action1.setBit(1,40); - l_ecmd_rc |= l_mem_perv_lfir_mask_or.setBit(1,40); - - // 41:63 Reserved not implemented, so won't touch these - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, MEM_PERV_LFIR_ACT0_0x03040010, l_mem_perv_lfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, MEM_PERV_LFIR_ACT1_0x03040011, l_mem_perv_lfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, MEM_PERV_LFIR_MASK_OR_0x0304000F, l_mem_perv_lfir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, MEM_PERV_LFIR_MASK_AND_0x0304000E, l_mem_perv_lfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - - - FAPI_INF("EXIT mss_unmask_pervasive_errors()"); - - return i_bad_rc; -} - - - - -//------------------------------------------------------------------------------ -// mss_unmask_inband_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_inband_errors( const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - FAPI_INF("ENTER mss_unmask_inband_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - //************************* - //************************* - // MBS_FIR_REG - //************************* - //************************* - - ecmdDataBufferBase l_mbs_fir_mask(64); - ecmdDataBufferBase l_mbs_fir_mask_or(64); - ecmdDataBufferBase l_mbs_fir_mask_and(64); - ecmdDataBufferBase l_mbs_fir_action0(64); - ecmdDataBufferBase l_mbs_fir_action1(64); - - uint8_t l_dd2_fir_bit_defn_changes = 0; - - // Get attribute that tells us if mbspa 0 cmd complete attention is fixed for dd2 - l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_DD2_FIR_BIT_DEFN_CHANGES, &i_target, l_dd2_fir_bit_defn_changes); - if(l_rc) - { - FAPI_ERR("Error getting ATTR_CENTAUR_EC_DD2_FIR_BIT_DEFN_CHANGES"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbs_fir_action0.flushTo0(); - l_ecmd_rc |= l_mbs_fir_action1.flushTo0(); - l_ecmd_rc |= l_mbs_fir_mask_or.flushTo0(); - l_ecmd_rc |= l_mbs_fir_mask_and.flushTo1(); - - // 0 host_protocol_error channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(0); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(0); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(0); - - // 1 int_protocol_error channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(1); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(1); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(1); - - // 2 invalid_address_error channel checkstop mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(2); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(2); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(2); - - // 3 external_timeout recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(3); - l_ecmd_rc |= l_mbs_fir_action1.setBit(3); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(3); - - // 4 internal_timeout recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(4); - l_ecmd_rc |= l_mbs_fir_action1.setBit(4); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(4); - - // 5 int_buffer_ce recoverable unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(5); - l_ecmd_rc |= l_mbs_fir_action1.setBit(5); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(5); - - // 6 int_buffer_ue channel checkstop unmask - // HW278850: 8B ecc UE from SRB,PFB not transformed to SUE when allocating into L4 - l_ecmd_rc |= l_mbs_fir_action0.clearBit(6); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(6); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(6); - - // 7 int_buffer_sue recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(7); - l_ecmd_rc |= l_mbs_fir_action1.setBit(7); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(7); - - // 8 int_parity_error channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(8); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(8); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(8); - - // 9 cache_srw_ce recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(9); - l_ecmd_rc |= l_mbs_fir_action1.setBit(9); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(9); - - // 10 cache_srw_ue recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(10); - l_ecmd_rc |= l_mbs_fir_action1.setBit(10); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(10); - - // 11 cache_srw_sue recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(11); - l_ecmd_rc |= l_mbs_fir_action1.setBit(11); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(11); - - // 12 cache_co_ce recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(12); - l_ecmd_rc |= l_mbs_fir_action1.setBit(12); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(12); - - // 13 cache_co_ue recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(13); - l_ecmd_rc |= l_mbs_fir_action1.setBit(13); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(13); - - // 14 cache_co_sue recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(14); - l_ecmd_rc |= l_mbs_fir_action1.setBit(14); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(14); - - // 15 dir_ce recoverable DD1: mask (forever) - // 15 dir_ce recoverable DD2: mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(15); - l_ecmd_rc |= l_mbs_fir_action1.setBit(15); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(15); - - // 16 dir_ue channel checkstop mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(16); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(16); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(16); - - // 17 dir_member_deleted recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(17); - l_ecmd_rc |= l_mbs_fir_action1.setBit(17); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(17); - - // 18 dir_all_members_deleted channel checkstop mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(18); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(18); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(18); - - // 19 lru_error recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(19); - l_ecmd_rc |= l_mbs_fir_action1.setBit(19); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(19); - - // 20 eDRAM error channel checkstop mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(20); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(20); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(20); - - // 21 emergency_throttle_set recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(21); - l_ecmd_rc |= l_mbs_fir_action1.setBit(21); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(21); - - // 22 Host Inband Read Error recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(22); - l_ecmd_rc |= l_mbs_fir_action1.setBit(22); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(22); - - // 23 Host Inband Write Error recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(23); - l_ecmd_rc |= l_mbs_fir_action1.setBit(23); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(23); - - // 24 OCC Inband Read Error recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(24); - l_ecmd_rc |= l_mbs_fir_action1.setBit(24); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(24); - - // 25 OCC Inband Write Error recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(25); - l_ecmd_rc |= l_mbs_fir_action1.setBit(25); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(25); - - // 26 srb_buffer_ce recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(26); - l_ecmd_rc |= l_mbs_fir_action1.setBit(26); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(26); - - // 27 srb_buffer_ue recoverable mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(27); - l_ecmd_rc |= l_mbs_fir_action1.setBit(27); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(27); - - // 28 srb_buffer_sue recoverable mask (forever) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(28); - l_ecmd_rc |= l_mbs_fir_action1.setBit(28); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(28); - - if (l_dd2_fir_bit_defn_changes) - { - // 29 dir_purge_ce recoverable mask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(29); - l_ecmd_rc |= l_mbs_fir_action1.setBit(29); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(29); - - // 30 proximal_ce_ue channel checkstop mask (until unmask_fetch_errors) - l_ecmd_rc |= l_mbs_fir_action0.clearBit(30); - l_ecmd_rc |= l_mbs_fir_action1.clearBit(30); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(30); - - // 31 spare recoverable mask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(31); - l_ecmd_rc |= l_mbs_fir_action1.setBit(31); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(31); - - // 32 spare recoverable mask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(32); - l_ecmd_rc |= l_mbs_fir_action1.setBit(32); - l_ecmd_rc |= l_mbs_fir_mask_or.setBit(33); - - // 33 internal_scom_error recoverable unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(33); - l_ecmd_rc |= l_mbs_fir_action1.setBit(33); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(33); - - // 34 internal_scom_error_copy recoverable unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(34); - l_ecmd_rc |= l_mbs_fir_action1.setBit(34); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(34); - - // 35:63 Reserved not implemented, so won't touch these - } - - else - { - // 29 internal_scom_error recoverable unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(29); - l_ecmd_rc |= l_mbs_fir_action1.setBit(29); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(29); - - // 30 internal_scom_error_copy recoverable unmask - l_ecmd_rc |= l_mbs_fir_action0.clearBit(30); - l_ecmd_rc |= l_mbs_fir_action1.setBit(30); - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(30); - - // 31:63 Reserved not implemented, so won't touch these - } - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_ACTION0_REG_0x02011406, l_mbs_fir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_ACTION1_REG_0x02011407, l_mbs_fir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_MASK_REG_OR_0x02011405, l_mbs_fir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_MASK_REG_AND_0x02011404, l_mbs_fir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_ACTION0_REG_0x02011406, l_mbs_fir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_ACTION1_REG_0x02011407, l_mbs_fir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - FAPI_INF("EXIT mss_unmask_inband_errors()"); - - return i_bad_rc; -} - - - -//------------------------------------------------------------------------------ -// mss_unmask_ddrphy_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_ddrphy_errors( const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - FAPI_INF("ENTER mss_unmask ddrphy_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - //************************* - //************************* - // DDRPHY_FIR_REG - //************************* - //************************* - - ecmdDataBufferBase l_ddrphy_fir_mask(64); - ecmdDataBufferBase l_ddrphy_fir_mask_or(64); - ecmdDataBufferBase l_ddrphy_fir_mask_and(64); - ecmdDataBufferBase l_ddrphy_fir_action0(64); - ecmdDataBufferBase l_ddrphy_fir_action1(64); - - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_ddrphy_fir_action0.flushTo0(); - l_ecmd_rc |= l_ddrphy_fir_action1.flushTo0(); - l_ecmd_rc |= l_ddrphy_fir_mask_or.flushTo0(); - l_ecmd_rc |= l_ddrphy_fir_mask_and.flushTo0(); - l_ecmd_rc |= l_ddrphy_fir_mask_and.setBit(48,16); - - // 0:47 Reserved not implemented, so won't touch these - - // 48 ddr0_fsm_ckstp channel checkstop unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(48); - l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(48); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(48); - - // 49 ddr0_parity_ckstp channel checkstop unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(49); - l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(49); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(49); - - // 50 ddr0_calibration_error recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(50); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(50); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(50); - - // 51 ddr0_fsm_err recoverable unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(51); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(51); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(51); - - // 52 ddr0_parity_err recoverable unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(52); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(52); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(52); - - // 53 ddr01_fir_parity_err recoverable unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(53); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(53); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(53); - - // 54 Reserved recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(54); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(54); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(54); - - // 55 Reserved recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(55); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(55); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(55); - - // 56 ddr1_fsm_ckstp channel checkstop unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(56); - l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(56); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(56); - - // 57 ddr1_parity_ckstp channel checkstop unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(57); - l_ecmd_rc |= l_ddrphy_fir_action1.clearBit(57); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(57); - - // 58 ddr1_calibration_error recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(58); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(58); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(58); - - // 59 ddr1_fsm_err recoverable unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(59); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(59); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(59); - - // 60 ddr1_parity_err recoverable unmask - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(60); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(60); - l_ecmd_rc |= l_ddrphy_fir_mask_and.clearBit(60); - - // 61 Reserved recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(61); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(61); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(61); - - // 62 Reserved recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(62); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(62); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(62); - - // 63 Reserved recoverable mask (forever) - l_ecmd_rc |= l_ddrphy_fir_action0.clearBit(63); - l_ecmd_rc |= l_ddrphy_fir_action1.setBit(63); - l_ecmd_rc |= l_ddrphy_fir_mask_or.setBit(63); - - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION0_REG_0x800200960301143f, l_ddrphy_fir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION1_REG_0x800200970301143f, l_ddrphy_fir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_MASK_REG_OR_0x800200950301143f, l_ddrphy_fir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, PHY01_DDRPHY_FIR_MASK_REG_AND_0x800200940301143f, l_ddrphy_fir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION0_REG_0x800200960301143f, l_ddrphy_fir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, PHY01_DDRPHY_FIR_ACTION1_REG_0x800200970301143f, l_ddrphy_fir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, PHY01_DDRPHY_FIR_MASK_REG_0x800200930301143f, l_ddrphy_fir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - //************************* - //************************* - // MBAFIR - //************************* - //************************* - - ecmdDataBufferBase l_mbafir_mask(64); - ecmdDataBufferBase l_mbafir_mask_or(64); - ecmdDataBufferBase l_mbafir_mask_and(64); - ecmdDataBufferBase l_mbafir_action0(64); - ecmdDataBufferBase l_mbafir_action1(64); - - uint8_t l_dd2_fir_bit_defn_changes = 0; - fapi::Target l_targetCentaur; - - // Get Centaur target for the given MBA - l_rc = fapiGetParentChip(i_target, l_targetCentaur); - if(l_rc) - { - FAPI_ERR("Error getting Centaur parent target for the given MBA"); - return l_rc; - } - - // Get attribute that tells us if mbspa 0 cmd complete attention is fixed for dd2 - l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_DD2_FIR_BIT_DEFN_CHANGES, &l_targetCentaur, l_dd2_fir_bit_defn_changes); - if(l_rc) - { - FAPI_ERR("Error getting ATTR_CENTAUR_EC_DD2_FIR_BIT_DEFN_CHANGES"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, - MBA01_MBAFIRMASK_0x03010603, - l_mbafir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbafir_action0.flushTo0(); - l_ecmd_rc |= l_mbafir_action1.flushTo0(); - l_ecmd_rc |= l_mbafir_mask_or.flushTo0(); - l_ecmd_rc |= l_mbafir_mask_and.flushTo1(); - - - // 0 Invalid_Maint_Cmd recoverable masked (forever) - l_ecmd_rc |= l_mbafir_action0.clearBit(0); - l_ecmd_rc |= l_mbafir_action1.setBit(0); - l_ecmd_rc |= l_mbafir_mask_or.setBit(0); - - // 1 Invalid_Maint_Address recoverable masked (forever) - l_ecmd_rc |= l_mbafir_action0.clearBit(1); - l_ecmd_rc |= l_mbafir_action1.setBit(1); - l_ecmd_rc |= l_mbafir_mask_or.setBit(1); - - // 2 Multi_address_Maint_timeout recoverable masked (until mss_unmask_maint_errors) - l_ecmd_rc |= l_mbafir_action0.clearBit(2); - l_ecmd_rc |= l_mbafir_action1.setBit(2); - l_ecmd_rc |= l_mbafir_mask_or.setBit(2); - - // 3 Internal_fsm_error channel checkstop unmask - l_ecmd_rc |= l_mbafir_action0.clearBit(3); - l_ecmd_rc |= l_mbafir_action1.clearBit(3); - l_ecmd_rc |= l_mbafir_mask_and.clearBit(3); - - // 4 MCBIST_Error recoverable mask (forever) - l_ecmd_rc |= l_mbafir_action0.clearBit(4); - l_ecmd_rc |= l_mbafir_action1.setBit(4); - l_ecmd_rc |= l_mbafir_mask_or.setBit(4); - - // 5 scom_cmd_reg_pe channel checkstop unmask - l_ecmd_rc |= l_mbafir_action0.clearBit(5); - l_ecmd_rc |= l_mbafir_action1.clearBit(5); - l_ecmd_rc |= l_mbafir_mask_and.clearBit(5); - - // 6 channel_chkstp_err channel checkstop unmask - l_ecmd_rc |= l_mbafir_action0.clearBit(6); - l_ecmd_rc |= l_mbafir_action1.clearBit(6); - l_ecmd_rc |= l_mbafir_mask_and.clearBit(6); - - // 7 wrd_caw2_data_ce_ue_err channel checkstop masked (until mss_unmask_maint_errors) - l_ecmd_rc |= l_mbafir_action0.clearBit(7); - l_ecmd_rc |= l_mbafir_action1.clearBit(7); - l_ecmd_rc |= l_mbafir_mask_or.setBit(7); - - if (l_dd2_fir_bit_defn_changes) - { - // 8 maint_1hot_st_error_dd2 channel checkstop unmask - l_ecmd_rc |= l_mbafir_action0.clearBit(8); - l_ecmd_rc |= l_mbafir_action1.clearBit(8); - l_ecmd_rc |= l_mbafir_mask_and.clearBit(8); - } - else - { - // 8 RESERVED recoverable mask (forever) - l_ecmd_rc |= l_mbafir_action0.clearBit(8); - l_ecmd_rc |= l_mbafir_action1.setBit(8); - l_ecmd_rc |= l_mbafir_mask_or.setBit(8); - } - - // 9:14 RESERVED recoverable mask (forever) - l_ecmd_rc |= l_mbafir_action0.clearBit(9,6); - l_ecmd_rc |= l_mbafir_action1.setBit(9,6); - l_ecmd_rc |= l_mbafir_mask_or.setBit(9,6); - - // 15 internal scom error recoverable unmask - l_ecmd_rc |= l_mbafir_action0.clearBit(15); - l_ecmd_rc |= l_mbafir_action1.setBit(15); - l_ecmd_rc |= l_mbafir_mask_and.clearBit(15); - - // 16 internal scom error clone recoverable unmask - l_ecmd_rc |= l_mbafir_action0.clearBit(16); - l_ecmd_rc |= l_mbafir_action1.setBit(16); - l_ecmd_rc |= l_mbafir_mask_and.clearBit(16); - - - // 17:63 RESERVED not implemented, so won't touch these - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, - MBA01_MBAFIRACT0_0x03010606, - l_mbafir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, - MBA01_MBAFIRACT1_0x03010607, - l_mbafir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, - MBA01_MBAFIRMASK_OR_0x03010605, - l_mbafir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, - MBA01_MBAFIRMASK_AND_0x03010604, - l_mbafir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, - MBA01_MBAFIRACT0_0x03010606, - l_mbafir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, - MBA01_MBAFIRACT1_0x03010607, - l_mbafir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, - MBA01_MBAFIRMASK_0x03010603, - l_mbafir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - FAPI_INF("EXIT mss_unmask_ddrphy_errors()"); - - return i_bad_rc; -} - - -//------------------------------------------------------------------------------ -// mss_unmask_draminit_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_draminit_errors( const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - FAPI_INF("ENTER mss_unmask_draminit_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - //************************* - //************************* - // MBACALFIR - //************************* - //************************* - - ecmdDataBufferBase l_mbacalfir_mask(64); - ecmdDataBufferBase l_mbacalfir_mask_or(64); - ecmdDataBufferBase l_mbacalfir_mask_and(64); - ecmdDataBufferBase l_mbacalfir_action0(64); - ecmdDataBufferBase l_mbacalfir_action1(64); - - uint8_t l_dd2_fir_bit_defn_changes = 0; - fapi::Target l_targetCentaur; - uint8_t l_dimm_type = 0; - - // Get Centaur target for the given MBA - l_rc = fapiGetParentChip(i_target, l_targetCentaur); - if(l_rc) - { - FAPI_ERR("Error getting Centaur parent target for the given MBA"); - return l_rc; - } - - // Get attribute that tells us if mbspa 0 cmd complete attention is fixed for dd2 - l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_DD2_FIR_BIT_DEFN_CHANGES, &l_targetCentaur, l_dd2_fir_bit_defn_changes); - if(l_rc) - { - FAPI_ERR("Error getting ATTR_CENTAUR_EC_DD2_FIR_BIT_DEFN_CHANGES"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Get DIMM type - l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_dimm_type); - if(l_rc) - { - FAPI_ERR("Error getting ATTR_EFF_DIMM_TYPE"); - return l_rc; - } - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbacalfir_action0.flushTo0(); - l_ecmd_rc |= l_mbacalfir_action1.flushTo0(); - l_ecmd_rc |= l_mbacalfir_mask_or.flushTo0(); - l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1(); - - // 0 MBA Recoverable Error recoverable mask (until after draminit_training) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(0); - l_ecmd_rc |= l_mbacalfir_action1.setBit(0); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(0); - - // 1 MBA Nonrecoverable Error channel checkstop mask (until after draminit_mc) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(1); - l_ecmd_rc |= l_mbacalfir_action1.clearBit(1); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(1); - - // 2 Refresh Overrun recoverable mask (until after draminit_mc) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(2); - l_ecmd_rc |= l_mbacalfir_action1.setBit(2); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(2); - - // 3 WAT error recoverable mask (forever) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(3); - l_ecmd_rc |= l_mbacalfir_action1.setBit(3); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(3); - - // 4 RCD Parity Error 0 recoverable unmask (if RDIMM or LRDIMM) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(4); - l_ecmd_rc |= l_mbacalfir_action1.setBit(4); - if ((l_dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM)||(l_dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)) - { - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(4); - } - else - { - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(4); - } - - // 5 ddr0_cal_timeout_err recoverable mask (until after draminit_mc) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(5); - l_ecmd_rc |= l_mbacalfir_action1.setBit(5); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(5); - - // 6 ddr1_cal_timeout_err recoverable mask (until after draminit_mc) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(6); - l_ecmd_rc |= l_mbacalfir_action1.setBit(6); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(6); - - // 7 RCD Parity Error 1 recoverable unmask (if RDIMM or LRDIMM) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(7); - l_ecmd_rc |= l_mbacalfir_action1.setBit(7); - if ((l_dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM)||(l_dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)) - { - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(7); - } - else - { - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(7); - } - - // 8 mbx to mba par error channel checkstop mask (until after draminit_training_adv) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(8); - l_ecmd_rc |= l_mbacalfir_action1.clearBit(8); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(8); - - // 9 mba_wrd ue recoverable mask (until mainline traffic) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(9); - l_ecmd_rc |= l_mbacalfir_action1.setBit(9); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(9); - - // 10 mba_wrd ce recoverable mask (until mainline traffic) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(10); - l_ecmd_rc |= l_mbacalfir_action1.setBit(10); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(10); - - // 11 mba_maint ue recoverable mask (until after draminit_training_adv) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(11); - l_ecmd_rc |= l_mbacalfir_action1.setBit(11); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(11); - - // 12 mba_maint ce recoverable mask (until after draminit_training_adv) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(12); - l_ecmd_rc |= l_mbacalfir_action1.setBit(12); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(12); - - // 13 ddr_cal_reset_timeout channel checkstop unmask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(13); - l_ecmd_rc |= l_mbacalfir_action1.clearBit(13); - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(13); - - // 14 wrq_data_ce recoverable mask (until mainline traffic) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(14); - l_ecmd_rc |= l_mbacalfir_action1.setBit(14); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(14); - - // 15 wrq_data_ue recoverable mask (until mainline traffic) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(15); - l_ecmd_rc |= l_mbacalfir_action1.setBit(15); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(15); - - // 16 wrq_data_sue recoverable mask (forever) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(16); - l_ecmd_rc |= l_mbacalfir_action1.setBit(16); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(16); - - // 17 wrq_rrq_hang_err recoverable mask (until after draminit_training_adv) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(17); - l_ecmd_rc |= l_mbacalfir_action1.setBit(17); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(17); - - // 18 sm_1hot_err channel checkstop unmask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(18); - l_ecmd_rc |= l_mbacalfir_action1.clearBit(18); - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(18); - - // 19 wrd_scom_error recoverable unmask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(19); - l_ecmd_rc |= l_mbacalfir_action1.setBit(19); - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(19); - - if (l_dd2_fir_bit_defn_changes) - { - // 20 rhmr_prim_reached_max recoverable mask (forever) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(20); - l_ecmd_rc |= l_mbacalfir_action1.setBit(20); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(20); - - // 21 rhmr_sec_reached_max recoverable mask (forever) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(21); - l_ecmd_rc |= l_mbacalfir_action1.setBit(21); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(21); - - // 22 rhmr_sec_already_full recoverable mask (forever) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(22); - l_ecmd_rc |= l_mbacalfir_action1.setBit(22); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(22); - - // 23 Reserved recoverable mask (forever) - l_ecmd_rc |= l_mbacalfir_action0.clearBit(23); - l_ecmd_rc |= l_mbacalfir_action1.setBit(23); - l_ecmd_rc |= l_mbacalfir_mask_or.setBit(23); - - // 24 internal_scom_error recoverable unmask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(24); - l_ecmd_rc |= l_mbacalfir_action1.setBit(24); - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(24); - - // 25 internal_scom_error_copy recoverable unmask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(25); - l_ecmd_rc |= l_mbacalfir_action1.setBit(25); - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(25); - - // 26-63 Reserved not implemented, so won't touch these - } - else - { - // 20 internal_scom_error recoverable unmask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(20); - l_ecmd_rc |= l_mbacalfir_action1.setBit(20); - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(20); - - // 21 internal_scom_error_copy recoverable unmask - l_ecmd_rc |= l_mbacalfir_action0.clearBit(21); - l_ecmd_rc |= l_mbacalfir_action1.setBit(21); - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(21); - - // 22-63 Reserved not implemented, so won't touch these - } - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_ACTION0_0x03010406, l_mbacalfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_ACTION1_0x03010407, l_mbacalfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_OR_0x03010405, l_mbacalfir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_ACTION0_0x03010406, l_mbacalfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_ACTION1_0x03010407, l_mbacalfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - FAPI_INF("EXIT mss_unmask_draminit_errors()"); - - return i_bad_rc; -} - - -//------------------------------------------------------------------------------ -// mss_unmask_draminit_training_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_draminit_training_errors( - const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - FAPI_INF("ENTER mss_unmask_draminit_training_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - //************************* - //************************* - // MBACALFIR - //************************* - //************************* - - ecmdDataBufferBase l_mbacalfir_mask(64); - ecmdDataBufferBase l_mbacalfir_mask_and(64); - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been - // called, which has already set the MBACALFIR action regs to their runtime - // values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been - // called, which has already unmasked the approproiate MBACALFIR errors - // following mss_draminit. So all we will do here is unmask a few more - // errors that would be considered valid after the mss_draminit_training - // procedure. - - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1(); - - // 0 MBA Recoverable Error recoverable umask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(0); - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - FAPI_INF("EXIT mss_unmask_draminit_training_errors()"); - - return i_bad_rc; -} - - -//------------------------------------------------------------------------------ -// mss_unmask_draminit_training_advanced_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_draminit_training_advanced_errors( - const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - FAPI_INF("ENTER mss_unmask_draminit_training_advanced_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - //************************* - //************************* - // MBACALFIR - //************************* - //************************* - - ecmdDataBufferBase l_mbacalfir_mask(64); - ecmdDataBufferBase l_mbacalfir_mask_and(64); - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been - // called, which has already set the MBACALFIR action regs to their runtime - // values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors and - // mss_unmask_draminit_training has already been - // called, which has already unmasked the approproiate MBACALFIR errors - // following mss_draminit and mss_draminit_training. So all we will do here - // is unmask a few more errors that would be considered valid after the - // mss_draminit_training_advanced procedure. - - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1(); - - // 8 mbx to mba par error channel checkstop unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(8); - - // 11 mba_maint ue recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(11); - - // 12 mba_maint ce recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(12); - - // 17 wrq_rrq_hang_err recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(17); - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, MBA01_MBACALFIR_MASK_0x03010403, l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - //************************* - //************************* - // MBSFIR - //************************* - //************************* - - fapi::Target l_targetCentaur; - uint8_t l_mbaPosition; // 0 = mba01, 1 = mba23 - - uint32_t l_mbsfir_mask_address[2]={ - // port0/1 port2/3 - MBS01_MBSFIRMASK_0x02011603, MBS23_MBSFIRMASK_0x02011703}; - - uint32_t l_mbsfir_mask_or_address[2]={ - // port0/1 port2/3 - MBS01_MBSFIRMASK_OR_0x02011605, MBS23_MBSFIRMASK_OR_0x02011705}; - - uint32_t l_mbsfir_mask_and_address[2]={ - // port0/1 port2/3 - MBS01_MBSFIRMASK_AND_0x02011604, MBS23_MBSFIRMASK_AND_0x02011704}; - - uint32_t l_mbsfir_action0_address[2]={ - // port0/1 port2/3 - MBS01_MBSFIRACT0_0x02011606, MBS23_MBSFIRACT0_0x02011706}; - - uint32_t l_mbsfir_action1_address[2]={ - // port0/1 port2/3 - MBS01_MBSFIRACT1_0x02011607, MBS23_MBSFIRACT1_0x02011707}; - - ecmdDataBufferBase l_mbsfir_mask(64); - ecmdDataBufferBase l_mbsfir_mask_or(64); - ecmdDataBufferBase l_mbsfir_mask_and(64); - ecmdDataBufferBase l_mbsfir_action0(64); - ecmdDataBufferBase l_mbsfir_action1(64); - - // Get Centaur target for the given MBA - l_rc = fapiGetParentChip(i_target, l_targetCentaur); - if(l_rc) - { - FAPI_ERR("Error getting Centaur parent target for the given MBA"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Read mask - l_rc = fapiGetScom_w_retry(l_targetCentaur, - l_mbsfir_mask_address[l_mbaPosition], - l_mbsfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbsfir_action0.flushTo0(); - l_ecmd_rc |= l_mbsfir_action1.flushTo0(); - l_ecmd_rc |= l_mbsfir_mask_or.flushTo0(); - l_ecmd_rc |= l_mbsfir_mask_and.flushTo1(); - - // 0 scom_par_errors channel checkstop unmask - l_ecmd_rc |= l_mbsfir_action0.clearBit(0); - l_ecmd_rc |= l_mbsfir_action1.clearBit(0); - l_ecmd_rc |= l_mbsfir_mask_and.clearBit(0); - - // 1 mbx_par_errors channel checkstop unmask - l_ecmd_rc |= l_mbsfir_action0.clearBit(1); - l_ecmd_rc |= l_mbsfir_action1.clearBit(1); - l_ecmd_rc |= l_mbsfir_mask_and.clearBit(1); - - // 2 DD1: reserved recoverable mask (forever) - // 2 DD2: dram_eventn_bit0 recoverable mask (forever) - l_ecmd_rc |= l_mbsfir_action0.clearBit(2); - l_ecmd_rc |= l_mbsfir_action1.setBit(2); - l_ecmd_rc |= l_mbsfir_mask_or.setBit(2); - - // 3 DD1: reserved recoverable mask (forever) - // 3 DD2: dram_eventn_bit1 recoverable mask (forever) - l_ecmd_rc |= l_mbsfir_action0.clearBit(3); - l_ecmd_rc |= l_mbsfir_action1.setBit(3); - l_ecmd_rc |= l_mbsfir_mask_or.setBit(3); - - // 4:14 RESERVED recoverable mask (forever) - l_ecmd_rc |= l_mbsfir_action0.clearBit(4,11); - l_ecmd_rc |= l_mbsfir_action1.setBit(4,11); - l_ecmd_rc |= l_mbsfir_mask_or.setBit(4,11); - - // 2:14 RESERVED recoverable mask (forever) - l_ecmd_rc |= l_mbsfir_action0.clearBit(2,13); - l_ecmd_rc |= l_mbsfir_action1.setBit(2,13); - l_ecmd_rc |= l_mbsfir_mask_or.setBit(2,13); - - // 15 internal scom error recoverable unmask - l_ecmd_rc |= l_mbsfir_action0.clearBit(15); - l_ecmd_rc |= l_mbsfir_action1.setBit(15); - l_ecmd_rc |= l_mbsfir_mask_and.clearBit(15); - - // 16 internal scom error clone recoverable unmask - l_ecmd_rc |= l_mbsfir_action0.clearBit(16); - l_ecmd_rc |= l_mbsfir_action1.setBit(16); - l_ecmd_rc |= l_mbsfir_mask_and.clearBit(16); - - // 17:63 RESERVED not implemented, so won't touch these - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(l_targetCentaur, - l_mbsfir_action0_address[l_mbaPosition], - l_mbsfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(l_targetCentaur, - l_mbsfir_action1_address[l_mbaPosition], - l_mbsfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(l_targetCentaur, - l_mbsfir_mask_or_address[l_mbaPosition], - l_mbsfir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask AND - l_rc = fapiPutScom_w_retry(l_targetCentaur, - l_mbsfir_mask_and_address[l_mbaPosition], - l_mbsfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(l_targetCentaur, - l_mbsfir_action0_address[l_mbaPosition], - l_mbsfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - l_rc = fapiGetScom_w_retry(l_targetCentaur, - l_mbsfir_action1_address[l_mbaPosition], - l_mbsfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - l_rc = fapiGetScom_w_retry(l_targetCentaur, - l_mbsfir_mask_address[l_mbaPosition], - l_mbsfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - FAPI_INF("EXIT mss_unmask_draminit_training_advanced_errors()"); - - return i_bad_rc; -} - - - -//------------------------------------------------------------------------------ -// mss_unmask_maint_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_maint_errors(const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - // Target: Centaur - - FAPI_INF("ENTER mss_unmask_maint_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - std::vector<fapi::Target> l_mbaChiplets; - uint8_t l_mbaPosition; // 0 = mba01, 1 = mba23 - - ecmdDataBufferBase l_mbacalfir_mask(64); - ecmdDataBufferBase l_mbacalfir_mask_and(64); - - ecmdDataBufferBase l_mbafir_mask(64); - ecmdDataBufferBase l_mbafir_mask_and(64); - - ecmdDataBufferBase l_mbaspa_mask(64); - - uint32_t l_mbeccfir_mask_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_MASK_0x02011443, MBS_ECC1_MBECCFIR_MASK_0x02011483}; - - uint32_t l_mbeccfir_mask_or_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_MASK_OR_0x02011445, MBS_ECC1_MBECCFIR_MASK_OR_0x02011485}; - - uint32_t l_mbeccfir_mask_and_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_MASK_AND_0x02011444,MBS_ECC1_MBECCFIR_MASK_AND_0x02011484}; - - uint32_t l_mbeccfir_action0_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_ACTION0_0x02011446, MBS_ECC1_MBECCFIR_ACTION0_0x02011486}; - - uint32_t l_mbeccfir_action1_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_ACTION1_0x02011447, MBS_ECC1_MBECCFIR_ACTION1_0x02011487}; - - ecmdDataBufferBase l_mbeccfir_mask(64); - ecmdDataBufferBase l_mbeccfir_mask_or(64); - ecmdDataBufferBase l_mbeccfir_mask_and(64); - ecmdDataBufferBase l_mbeccfir_action0(64); - ecmdDataBufferBase l_mbeccfir_action1(64); - - uint8_t l_mbspa_0_fixed_for_dd2 = 0; - - // Get attribute that tells us if mbspa 0 cmd complete attention is fixed for dd2 - l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_HW217608_MBSPA_0_CMD_COMPLETE_ATTN_FIXED, &i_target, l_mbspa_0_fixed_for_dd2); - if(l_rc) - { - FAPI_ERR("Error getting ATTR_CENTAUR_EC_HW217608_MBSPA_0_CMD_COMPLETE_ATTN_FIXED"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Get associated functional MBAs on this centaur - l_rc = fapiGetChildChiplets(i_target, - fapi::TARGET_TYPE_MBA_CHIPLET, - l_mbaChiplets); - if(l_rc) - { - FAPI_ERR("Error getting functional MBAs on this Centaur"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Loop through functional MBAs on this Centaur - for (uint32_t i=0; i < l_mbaChiplets.size(); i++) - { - - // Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mbaChiplets[i], l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - - - //************************* - //************************* - // MBACALFIR - //************************* - //************************* - - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been - // called, which has already set the MBACALFIR action regs to their runtime - // values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors, - // mss_unmask_draminit_training and mss_unmask_draminit_training_advanced - // have already been called, which have already unmasked the approproiate - // MBACALFIR errors following mss_draminit, mss_draminit_training, and - // mss_unmask_draminit_training_advanced. So all we will do here - // is unmask a few more errors that would be considered valid after the - // mss_draminit_mc procedure. - - // Read mask - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBACALFIR_MASK_0x03010403, - l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1(); - - // 1 MBA Nonrecoverable Error channel checkstop unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(1); - - // 2 Refresh Overrun recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(2); - - // 5 ddr0_cal_timeout_err recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(5); - - // 6 ddr1_cal_timeout_err recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(6); - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(l_mbaChiplets[i], - MBA01_MBACALFIR_MASK_AND_0x03010404, - l_mbacalfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBACALFIR_MASK_0x03010403, - l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - //************************* - //************************* - // MBAFIR - //************************* - //************************* - - // NOTE: In the IPL sequence, mss_unmask_ddr_phy_errors has already been - // called, which has already set the MBAFIR action regs to their runtime - // values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, mss_unmask_ddr_phy_errors, - // has already been called, which has already unmasked the approproiate - // MBAFIR errors following mss_ddr_phy_reset. So all we will do here - // is unmask a few more errors that would be considered valid after the - // mss_draminit_mc procedure. - - // Read mask - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBAFIRMASK_0x03010603, - l_mbafir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbafir_mask_and.flushTo1(); - - // 2 Multi_address_Maint_timeout recoverable unmask - l_ecmd_rc |= l_mbafir_mask_and.clearBit(2); - - - // 7 wrd_caw2_data_ce_ue_err channel checkstop unmask - l_ecmd_rc |= l_mbafir_mask_and.clearBit(7); - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(l_mbaChiplets[i], - MBA01_MBAFIRMASK_AND_0x03010604, - l_mbafir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBAFIRMASK_0x03010603, - l_mbafir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - //************************* - //************************* - // MBSPA - //************************* - //************************* - - - // Read mask - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBSPAMSKQ_0x03010614, - l_mbaspa_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - // 0 Command_Complete - if (l_mbspa_0_fixed_for_dd2) - { - l_ecmd_rc |= l_mbaspa_mask.clearBit(0); // DD2: unmask (fixed) - } - else - { - l_ecmd_rc |= l_mbaspa_mask.setBit(0); // DD1: masked (broken) - } - - // 1 Hard_CE_ETE_Attn mask (forever) - // NOTE: FW wants to mask these and rely instead on detecting the - // cmd complete attention, then checking these manually to see if - // they cause the cmd to stop - // NOTE: Hards counted during super fast read, but can't be called - // true hard CEs since super fast read doesn't write back and read again. - l_ecmd_rc |= l_mbaspa_mask.setBit(1); - - // 2 Soft_CE_ETE_Attn mask (forever) - // NOTE: FW wants to mask these and rely instead on detecting the - // cmd complete attention, then checking these manually to see if - // they cause the cmd to stop - // NOTE: Softs not counted during super fast read. - l_ecmd_rc |= l_mbaspa_mask.setBit(2); - - // 3 Intermittent_ETE_Attn mask (forever) - // NOTE: FW wants to mask these and rely instead on detecting the - // cmd complete attention, then checking these manually to see if - // they cause the cmd to stop - // NOTE: Intermittents not counted during super fast read. - l_ecmd_rc |= l_mbaspa_mask.setBit(3); - - // 4 RCE_ETE_Attn mask (forever) - // NOTE: FW wants to mask these and rely instead on detecting the - // cmd complete attention, then checking these manually to see if - // they cause the cmd to stop - // NOTE: RCEs not counted during super fast read. - l_ecmd_rc |= l_mbaspa_mask.setBit(4); - - // 5 Emergency_Throttle_Attn masked (forever) - l_ecmd_rc |= l_mbaspa_mask.setBit(5); - - // 6 Firmware_Attn0 masked (forever) - l_ecmd_rc |= l_mbaspa_mask.setBit(6); - - // 7 Firmware_Attn1 masked (forever) - l_ecmd_rc |= l_mbaspa_mask.setBit(7); - - // 8 wat_debug_attn - if (l_mbspa_0_fixed_for_dd2) - { - l_ecmd_rc |= l_mbaspa_mask.setBit(8); // DD2: masked (workaround for mbspa 0 not needed) - } - else - { - l_ecmd_rc |= l_mbaspa_mask.clearBit(8); // DD1: unmasked (workaround for mbspa 0 needed) - } - - // 9 Spare_Attn1 masked (forever) - l_ecmd_rc |= l_mbaspa_mask.setBit(9); - - // 10 MCBIST_Done masked (forever) - l_ecmd_rc |= l_mbaspa_mask.setBit(10); - - // 11:63 RESERVED not implemented, so won't touch these - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask - l_rc = fapiPutScom_w_retry(l_mbaChiplets[i], - MBA01_MBSPAMSKQ_0x03010614, - l_mbaspa_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBSPAMSKQ_0x03010614, - l_mbaspa_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - //************************************************ - - - - //************************* - //************************* - // MBECCFIR - //************************* - //************************* - - // Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mbaChiplets[i], l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, - l_mbeccfir_mask_address[l_mbaPosition], - l_mbeccfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_mbeccfir_action0.flushTo0(); - l_ecmd_rc |= l_mbeccfir_action1.flushTo0(); - l_ecmd_rc |= l_mbeccfir_mask_or.flushTo0(); - l_ecmd_rc |= l_mbeccfir_mask_and.flushTo1(); - - // 0:7 Memory MPE Rank 0:7 recoverable mask (until mainline traffic) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(0,8); - l_ecmd_rc |= l_mbeccfir_action1.setBit(0,8); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(0,8); - - // 8:15 Reserved recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(8,8); - l_ecmd_rc |= l_mbeccfir_action1.setBit(8,8); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(8,8); - - // 16 Memory NCE recoverable mask (until mainline traffic) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(16); - l_ecmd_rc |= l_mbeccfir_action1.setBit(16); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(16); - - // 17 Memory RCE recoverable mask (until mainline traffic) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(17); - l_ecmd_rc |= l_mbeccfir_action1.setBit(17); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(17); - - // 18 Memory SUE recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(18); - l_ecmd_rc |= l_mbeccfir_action1.setBit(18); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(18); - - // 19 Memory UE recoverable mask (until mainline traffic) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(19); - l_ecmd_rc |= l_mbeccfir_action1.setBit(19); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(19); - - // 20:27 Maint MPE Rank 0:7 recoverable mask (forever) - // NOTE: FW wants to mask these and rely instead on detecting the - // cmd complete attention, then checking these manually to see if - // they cause the cmd to stop - l_ecmd_rc |= l_mbeccfir_action0.clearBit(20,8); - l_ecmd_rc |= l_mbeccfir_action1.setBit(20,8); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(20,8); - - // 28:35 Reserved recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(28,8); - l_ecmd_rc |= l_mbeccfir_action1.setBit(28,8); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(28,8); - - // 36 Maintenance NCE recoverable mask (forever) - // NOTE: PRD planning to use maint CE thresholds instead. - l_ecmd_rc |= l_mbeccfir_action0.clearBit(36); - l_ecmd_rc |= l_mbeccfir_action1.setBit(36); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(36); - - // 37 Maintenance SCE recoverable mask (forever) - // NOTE: Don't care if symbol still bad after it's symbol marked. - l_ecmd_rc |= l_mbeccfir_action0.clearBit(37); - l_ecmd_rc |= l_mbeccfir_action1.setBit(37); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(37); - - // 38 Maintenance MCE recoverable mask (forever) - // NOTE: PRD plans to check manually as part of verify chip mark procedure. - l_ecmd_rc |= l_mbeccfir_action0.clearBit(38); - l_ecmd_rc |= l_mbeccfir_action1.setBit(38); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(38); - - // 39 Maintenance RCE recoverable mask (forever) - // NOTE: PRD planning to use maint RCE thresholds instead. - l_ecmd_rc |= l_mbeccfir_action0.clearBit(39); - l_ecmd_rc |= l_mbeccfir_action1.setBit(39); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(39); - - // 40 Maintenance SUE recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(40); - l_ecmd_rc |= l_mbeccfir_action1.setBit(40); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(40); - - // 41 Maintenance UE recoverable mask (forever) - // NOTE: FW wants to mask these and rely instead on detecting the - // cmd complete attention, then checking these manually to see if - // they cause the cmd to stop - l_ecmd_rc |= l_mbeccfir_action0.clearBit(41); - l_ecmd_rc |= l_mbeccfir_action1.setBit(41); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(41); - - // 42 MPE during maintenance mark mode recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(42); - l_ecmd_rc |= l_mbeccfir_action1.setBit(42); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(42); - - // 43 Prefetch Memory UE recoverable mask (until mainline traffic) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(43); - l_ecmd_rc |= l_mbeccfir_action1.setBit(43); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(43); - - // 44 Memory RCD parity error recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(44); - l_ecmd_rc |= l_mbeccfir_action1.setBit(44); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(44); - - // 45 Maint RCD parity error. recoverable mask (forever) - l_ecmd_rc |= l_mbeccfir_action0.clearBit(45); - l_ecmd_rc |= l_mbeccfir_action1.setBit(45); - l_ecmd_rc |= l_mbeccfir_mask_or.setBit(45); - - // 46 Recoverable reg parity recoverable unmask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(46); - l_ecmd_rc |= l_mbeccfir_action1.setBit(46); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(46); - - - // 47 Unrecoverable reg parity channel checkstop unmask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(47); - l_ecmd_rc |= l_mbeccfir_action1.clearBit(47); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(47); - - // 48 Maskable reg parity error recoverable unmask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(48); - l_ecmd_rc |= l_mbeccfir_action1.setBit(48); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(48); - - // 49 ecc datapath parity error channel checkstop unmask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(49); - l_ecmd_rc |= l_mbeccfir_action1.clearBit(49); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(49); - - // 50 internal scom error recovereble unmask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(50); - l_ecmd_rc |= l_mbeccfir_action1.setBit(50); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(50); - - // 51 internal scom error clone recovereble unmask - l_ecmd_rc |= l_mbeccfir_action0.clearBit(51); - l_ecmd_rc |= l_mbeccfir_action1.setBit(51); - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(51); - - // 52:63 Reserved not implemented, so won't touch these - - - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, - l_mbeccfir_action0_address[l_mbaPosition], - l_mbeccfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, - l_mbeccfir_action1_address[l_mbaPosition], - l_mbeccfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, - l_mbeccfir_mask_or_address[l_mbaPosition], - l_mbeccfir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, - l_mbeccfir_mask_and_address[l_mbaPosition], - l_mbeccfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, - l_mbeccfir_action0_address[l_mbaPosition], - l_mbeccfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - l_rc = fapiGetScom_w_retry(i_target, - l_mbeccfir_action1_address[l_mbaPosition], - l_mbeccfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - l_rc = fapiGetScom_w_retry(i_target, - l_mbeccfir_mask_address[l_mbaPosition], - l_mbeccfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - } // End for loop through functional MBAs on this Centaur - - FAPI_INF("EXIT mss_unmask_maint_errors()"); - - return i_bad_rc; -} - - - - -//------------------------------------------------------------------------------ -// mss_unmask_fetch_errors -//------------------------------------------------------------------------------ - -fapi::ReturnCode mss_unmask_fetch_errors(const fapi::Target & i_target, - fapi::ReturnCode i_bad_rc ) - -{ - - // Target: Centaur - - FAPI_INF("ENTER mss_unmask_fetch_errors()"); - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - uint8_t l_dimm_type = 0; - uint8_t l_cfg_wrdone_dly = 0; - uint8_t l_cfg_rdtag_dly = 0; - uint8_t l_max_cfg_rcd_protection_time = 0; - - ecmdDataBufferBase l_mba_dsm0(64); - ecmdDataBufferBase l_mba_farb0(64); - - - //************************* - //************************* - // SCAC_LFIR - //************************* - //************************* - - ecmdDataBufferBase l_scac_lfir_mask(64); - ecmdDataBufferBase l_scac_lfir_mask_or(64); - ecmdDataBufferBase l_scac_lfir_mask_and(64); - ecmdDataBufferBase l_scac_lfir_action0(64); - ecmdDataBufferBase l_scac_lfir_action1(64); - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRMASK_0x020115C3, l_scac_lfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - //(Action0, Action1, Mask) - // - // (0,0,0) = checkstop - // (0,1,0) = recoverable error - // (1,0,0) = report unused - // (1,1,0) = machine check - // (x,x,1) = error is masked - - l_ecmd_rc |= l_scac_lfir_action0.flushTo0(); - l_ecmd_rc |= l_scac_lfir_action1.flushTo0(); - l_ecmd_rc |= l_scac_lfir_mask_or.flushTo0(); - l_ecmd_rc |= l_scac_lfir_mask_and.flushTo1(); - - // 0 I2CMInvAddr recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(0); - l_ecmd_rc |= l_scac_lfir_action1.setBit(0); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(0); - - // 1 I2CMInvWrite recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(1); - l_ecmd_rc |= l_scac_lfir_action1.setBit(1); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(1); - - // 2 I2CMInvRead recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(2); - l_ecmd_rc |= l_scac_lfir_action1.setBit(2); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(2); - - // 3 I2CMApar recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(3); - l_ecmd_rc |= l_scac_lfir_action1.setBit(3); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(3); - - // 4 I2CMPar recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(4); - l_ecmd_rc |= l_scac_lfir_action1.setBit(4); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(4); - - // 5 I2CMLBPar recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(5); - l_ecmd_rc |= l_scac_lfir_action1.setBit(5); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(5); - - // 6:9 Expansion recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(6,4); - l_ecmd_rc |= l_scac_lfir_action1.setBit(6,4); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(6,4); - - // 10 I2CMInvCmd recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(10); - l_ecmd_rc |= l_scac_lfir_action1.setBit(10); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(10); - - // 11 I2CMPErr recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(11); - l_ecmd_rc |= l_scac_lfir_action1.setBit(11); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(11); - - // 12 I2CMOverrun recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(12); - l_ecmd_rc |= l_scac_lfir_action1.setBit(12); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(12); - - // 13 I2CMAccess recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(13); - l_ecmd_rc |= l_scac_lfir_action1.setBit(13); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(13); - - // 14 I2CMArb recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(14); - l_ecmd_rc |= l_scac_lfir_action1.setBit(14); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(14); - - // 15 I2CMNack recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(15); - l_ecmd_rc |= l_scac_lfir_action1.setBit(15); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(15); - - // 16 I2CMStop recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(16); - l_ecmd_rc |= l_scac_lfir_action1.setBit(16); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(16); - - // 17 LocalPib1 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(17); - l_ecmd_rc |= l_scac_lfir_action1.setBit(17); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(17); - - // 18 LocalPib2 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(18); - l_ecmd_rc |= l_scac_lfir_action1.setBit(18); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(18); - - // 19 LocalPib3 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(19); - l_ecmd_rc |= l_scac_lfir_action1.setBit(19); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(19); - - // 20 LocalPib4 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(20); - l_ecmd_rc |= l_scac_lfir_action1.setBit(20); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(20); - - // 21 LocalPib5 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(21); - l_ecmd_rc |= l_scac_lfir_action1.setBit(21); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(21); - - // 22 LocalPib6 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(22); - l_ecmd_rc |= l_scac_lfir_action1.setBit(22); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(22); - - // 23 LocalPib7 recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(23); - l_ecmd_rc |= l_scac_lfir_action1.setBit(23); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(23); - - // 24 StallError recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(24); - l_ecmd_rc |= l_scac_lfir_action1.setBit(24); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(24); - - // 25 RegParErr channel checkstop unmask - l_ecmd_rc |= l_scac_lfir_action0.clearBit(25); - l_ecmd_rc |= l_scac_lfir_action1.clearBit(25); - l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(25); - - // 26 RegParErrX channel checkstop unmask - l_ecmd_rc |= l_scac_lfir_action0.clearBit(26); - l_ecmd_rc |= l_scac_lfir_action1.clearBit(26); - l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(26); - - // 27:31 Reserved recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(27,5); - l_ecmd_rc |= l_scac_lfir_action1.setBit(27,5); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(27,5); - - // 32 SMErr recoverable unmask - l_ecmd_rc |= l_scac_lfir_action0.clearBit(32); - l_ecmd_rc |= l_scac_lfir_action1.setBit(32); - l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(32); - - // 33 RegAccErr recoverable unmask - l_ecmd_rc |= l_scac_lfir_action0.clearBit(33); - l_ecmd_rc |= l_scac_lfir_action1.setBit(33); - l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(33); - - // 34 ResetErr recoverable masked (forever) - l_ecmd_rc |= l_scac_lfir_action0.clearBit(34); - l_ecmd_rc |= l_scac_lfir_action1.setBit(34); - l_ecmd_rc |= l_scac_lfir_mask_or.setBit(34); - - // 35 internal_scom_error recoverable unmask - l_ecmd_rc |= l_scac_lfir_action0.clearBit(35); - l_ecmd_rc |= l_scac_lfir_action1.setBit(35); - l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(35); - - // 36 internal_scom_error_clone recoverable unmask - l_ecmd_rc |= l_scac_lfir_action0.clearBit(36); - l_ecmd_rc |= l_scac_lfir_action1.setBit(36); - l_ecmd_rc |= l_scac_lfir_mask_and.clearBit(36); - - // 37:63 Reserved - // Can we write to these bits? - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write action0 - l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRACTION0_0x020115C6, l_scac_lfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write action1 - l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRACTION1_0x020115C7, l_scac_lfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - // Write mask OR - l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRMASK_OR_0x020115C5, l_scac_lfir_mask_or); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, SCAC_FIRMASK_AND_0x020115C4, l_scac_lfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRACTION0_0x020115C6, l_scac_lfir_action0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRACTION1_0x020115C7, l_scac_lfir_action1); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - l_rc = fapiGetScom_w_retry(i_target, SCAC_FIRMASK_0x020115C3, l_scac_lfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - //************************* - //************************* - // MBS_FIR_REG - //************************* - //************************* - - - // NOTE: In the IPL sequence, mss_unmask_inband_errors has already been - // called, which has already set the MBS_FIR_REG action regs to their - // runtime values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, mss_unmask_inband_errors, - // has already been called, which has already unmasked the approproiate - // MBS_FIR_REG errors following mss_unmask_inband_errors. So all we will do - // here is unmask errors requiring mainline traffic which would be - // considered valid after the mss_thermal_init procedure. - - - ecmdDataBufferBase l_mbs_fir_mask(64); - ecmdDataBufferBase l_mbs_fir_mask_and(64); - uint8_t l_dd2_fir_bit_defn_changes = 0; - std::vector<fapi::Target> l_L4_vector; - bool l_L4_functional = false; - - l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_DD2_FIR_BIT_DEFN_CHANGES, &i_target, l_dd2_fir_bit_defn_changes); - if(l_rc) - { - FAPI_ERR("Error getting ATTR_CENTAUR_EC_DD2_FIR_BIT_DEFN_CHANGES"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Check if L4 is functional - l_rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_L4, l_L4_vector, fapi::TARGET_STATE_FUNCTIONAL); - if (l_rc) - { - FAPI_ERR("Error from fapiGetChildChiplets getting L4 target"); - return l_rc; - } - if (l_L4_vector.size() > 0) - { - l_L4_functional = true; - } - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - l_ecmd_rc |= l_mbs_fir_mask_and.flushTo1(); - - // 2 invalid_address_error channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(2); - - // 3 external_timeout recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(3); - - // 4 internal_timeout recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(4); - - - if (l_L4_functional) - { - // 9 cache_srw_ce recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(9); - - // 10 cache_srw_ue recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(10); - - // 12 cache_co_ce recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(12); - - // 13 cache_co_ue recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(13); - - // 15 dir_ce - if (l_dd2_fir_bit_defn_changes) - { - // NOTE: SW248520: Known DD1 problem - higher temp causes - // L4 Dir CEs. Want to ignore. Unmask for DD2 only - - // recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(15); - } - - // 16 dir_ue channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(16); - - // 18 dir_all_members_deleted channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(18); - - // 19 lru_error recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(19); - - // 20 eDRAM error channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(20); - } - - // 26 srb_buffer_ce recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(26); - - // 27 srb_buffer_ue recoverable unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(27); - - if (l_dd2_fir_bit_defn_changes && l_L4_functional) - { - // 30 proximal_ce_ue channel checkstop unmask - l_ecmd_rc |= l_mbs_fir_mask_and.clearBit(30); - } - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, MBS_FIR_MASK_REG_AND_0x02011404, l_mbs_fir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, MBS_FIR_MASK_REG_0x02011403, l_mbs_fir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - - - - std::vector<fapi::Target> l_mbaChiplets; - uint8_t l_mbaPosition; // 0 = mba01, 1 = mba23 - - - uint32_t l_mbeccfir_mask_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_MASK_0x02011443,MBS_ECC1_MBECCFIR_MASK_0x02011483}; - - uint32_t l_mbeccfir_mask_and_address[2]={ - // port0/1 port2/3 - MBS_ECC0_MBECCFIR_MASK_AND_0x02011444,MBS_ECC1_MBECCFIR_MASK_AND_0x02011484}; - - ecmdDataBufferBase l_mbeccfir_mask(64); - ecmdDataBufferBase l_mbeccfir_mask_and(64); - - //ecmdDataBufferBase l_mbaspa_mask(64); - - // Get associated functional MBAs on this centaur - l_rc = fapiGetChildChiplets(i_target, - fapi::TARGET_TYPE_MBA_CHIPLET, - l_mbaChiplets); - if(l_rc) - { - FAPI_ERR("Error getting functional MBAs on this Centaur"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Loop through functional MBAs on this Centaur - for (uint32_t i=0; i < l_mbaChiplets.size(); i++) - { - - // Get MBA position: 0 = mba01, 1 = mba23 - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mbaChiplets[i], l_mbaPosition); - if(l_rc) - { - FAPI_ERR("Error getting MBA position"); - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Get DIMM type - l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &l_mbaChiplets[i], l_dimm_type); - if(l_rc) - { - FAPI_ERR("Error getting ATTR_EFF_DIMM_TYPE"); - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // If RDIMM or LRDIMM, load max_cfg_rcd_protection_time and enable RCD recovery - if ((l_dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM)||(l_dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)) - { - - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], MBA01_MBA_DSM0_0x0301040a, l_mba_dsm0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Get 24:29 cfg_wrdone_dly - l_ecmd_rc |= l_mba_dsm0.extractPreserve(&l_cfg_wrdone_dly, 24, 6, 8-6); - - // Get 36:41 cfg_rdtag_dly - l_ecmd_rc |= l_mba_dsm0.extractPreserve(&l_cfg_rdtag_dly, 36, 6, 8-6); - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Pick lower of the two: cfg_wrdone_dly and cfg_rdtag_dly, and use that for l_max_cfg_rcd_protection_time - if (l_cfg_wrdone_dly <= l_cfg_rdtag_dly) - { - l_max_cfg_rcd_protection_time = l_cfg_wrdone_dly; - } - else - { - l_max_cfg_rcd_protection_time = l_cfg_rdtag_dly; - } - - // Read FARB0 - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], MBA01_MBA_FARB0Q_0x03010413, l_mba_farb0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // Load l_max_cfg_rcd_protection_time - l_ecmd_rc |= l_mba_farb0.insert( l_max_cfg_rcd_protection_time, 48, 6, 8-6 ); - - // Clear bit 54, cfg_disable_rcd_recovery, to enable RCD recovery - l_ecmd_rc |= l_mba_farb0.clearBit(54); - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - // Write FARB0 - l_rc = fapiPutScom_w_retry(l_mbaChiplets[i], MBA01_MBA_FARB0Q_0x03010413, l_mba_farb0); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - } - - - // NOTE: FW wants to mask these and rely instead on detecting the - // cmd complete attention, then checking these manually to see if - // they cause the cmd to stop - - //************************* - //************************* - // MBASPA - //************************* - //************************* - /* - // Read mask - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBSPAMSKQ_0x03010614, - l_mbaspa_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - - // 1 Hard_CE_ETE_Attn unmask - // NOTE: Unmasking, but PRD responsible for setting and enabling the threshold. - l_ecmd_rc |= l_mbaspa_mask.clearBit(1); - - // 2 Soft_CE_ETE_Attn unmask - // NOTE: Unmasking, but PRD responsible for setting and enabling the threshold. - l_ecmd_rc |= l_mbaspa_mask.clearBit(2); - - // 3 Intermittent_ETE_Attn unmask - // NOTE: Unmasking, but PRD responsible for setting and enabling the threshold. - l_ecmd_rc |= l_mbaspa_mask.clearBit(3); - - // 4 RCE_ETE_Attn unmask - // NOTE: Unmasking, but PRD responsible for setting and enabling the threshold. - l_ecmd_rc |= l_mbaspa_mask.clearBit(4); - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask - l_rc = fapiPutScom_w_retry(l_mbaChiplets[i], - MBA01_MBSPAMSKQ_0x03010614, - l_mbaspa_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - */ - //************************************************ - // DEBUG: read them all back to verify - /* - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBSPAMSKQ_0x03010614, - l_mbaspa_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - */ - //************************************************ - - - - //************************* - //************************* - // MBECCFIR - //************************* - //************************* - - // Read mask - l_rc = fapiGetScom_w_retry(i_target, - l_mbeccfir_mask_address[l_mbaPosition], - l_mbeccfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - // NOTE: In the IPL sequence, mss_unmask_maint_errors has already been - // called, which has already set the MBECCFIR action regs to their runtime - // values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, mss_unmask_maint_errors, - // has already been called, which has already unmasked the approproiate - // MBECCFIR errors following mss_unmask_maint_errors. So all we will do - // here is unmask errors requiring mainline traffic which would be - // considered valid after the mss_thermal_init procedure. - - l_ecmd_rc |= l_mbeccfir_mask_and.flushTo1(); - - // 0:7 Memory MPE Rank 0:7 recoverable unmask - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(0,8); - - // 16 Memory NCE recoverable unmask - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(16); - - // 17 Memory RCE recoverable unmask - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(17); - - // 19 Memory UE recoverable unmask - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(19); - - // NOTE: FW wants to mask these and rely instead on detecting the - // cmd complete attention, then checking these manually to see if - // they cause the cmd to stop - /* - // 20:27 Maint MPE Rank 0:7 recoverable unmask - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(20,8); - - // 41 Maintenance UE recoverable unmask - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(41); - */ - - // 43 Prefetch Memory UE recoverable unmask - l_ecmd_rc |= l_mbeccfir_mask_and.clearBit(43); - - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(i_target, - l_mbeccfir_mask_and_address[l_mbaPosition], - l_mbeccfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(i_target, - l_mbeccfir_mask_address[l_mbaPosition], - l_mbeccfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - } - - - //************************* - //************************* - // MBACALFIR - //************************* - //************************* - - ecmdDataBufferBase l_mbacalfir_mask(64); - ecmdDataBufferBase l_mbacalfir_mask_and(64); - - // NOTE: In the IPL sequence, mss_unmask_draminit_errors has already been - // called, which has already set the MBACALFIR action regs to their runtime - // values, so no need to touch the action regs here. - - // NOTE: In the IPL sequence, various bits have already been unmasked - // after the approproiate procedures. So all we will do here is unmask - // errors requiring mainline traffic which would be considered valid after - // the mss_thermal_init procedure. - - // Loop through functional MBAs on this Centaur - for (uint32_t i=0; i < l_mbaChiplets.size(); i++) - { - - // Read mask - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBACALFIR_MASK_0x03010403, - l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - // TODO: Here is where I could clear bits that were bogus, before I unmask - // them. But typically we are expecting the bit set at this point - // to be valid errors for PRD to log. - - l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1(); - - // 9 mba_wrd ue recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(9); - - // 10 mba_wrd ce recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(10); - - // 14 wrq_data_ce recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(14); - - // 15 wrq_data_ue recoverable unmask - l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(15); - - if(l_ecmd_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - // Write mask AND - l_rc = fapiPutScom_w_retry(l_mbaChiplets[i], - MBA01_MBACALFIR_MASK_AND_0x03010404, - l_mbacalfir_mask_and); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - - //************************************************ - // DEBUG: read them all back to verify - l_rc = fapiGetScom_w_retry(l_mbaChiplets[i], - MBA01_MBACALFIR_MASK_0x03010403, - l_mbacalfir_mask); - if(l_rc) - { - // Log passed in error before returning with new error - if (i_bad_rc) fapiLogError(i_bad_rc); - return l_rc; - } - - //************************************************ - } - - - - - FAPI_INF("EXIT mss_unmask_fetch_errors()"); - - return i_bad_rc; -} - -//------------------------------------------------------------------------------ -// fapiGetScom_w_retry -//------------------------------------------------------------------------------ -fapi::ReturnCode fapiGetScom_w_retry(const fapi::Target& i_target, - const uint64_t i_address, - ecmdDataBufferBase & o_data) -{ - fapi::ReturnCode l_rc; - - l_rc = fapiGetScom(i_target, i_address, o_data); - if(l_rc) - { - FAPI_ERR("1st Centaur fapiGetScom failed, so attempting retry."); - - // Log centaur scom error - fapiLogError(l_rc); - - // Retry centaur scom with assumption that retry is done via FSI, - // which may still work. - // NOTE: If scom fail was due to channel fail a retry via FSI may - // work. But if scom fail was due to PIB error, retry via FSI may - // also fail. - l_rc = fapiGetScom(i_target, i_address, o_data); - if(l_rc) - { - FAPI_ERR("fapiGetScom retry via FSI failed."); - // Retry didn't work either so give up and pass - // back centaur scom error - } - } - - return l_rc; -} - - -//------------------------------------------------------------------------------ -// fapiPutScom_w_retry -//------------------------------------------------------------------------------ -fapi::ReturnCode fapiPutScom_w_retry(const fapi::Target& i_target, - const uint64_t i_address, - ecmdDataBufferBase & i_data) -{ - fapi::ReturnCode l_rc; - - // NOTE: Inband scom device driver takes care of read to special reg after - // an inband scom write in order to detect SUE - l_rc = fapiPutScom(i_target, i_address, i_data); - if(l_rc) - { - FAPI_ERR("1st Centaur fapiPutScom failed, so attempting retry."); - - // Log centaur scom error - fapiLogError(l_rc); - - // Retry centaur scom with assumption that retry is done via FSI, - // which may still work. - // NOTE: If scom fail was due to channel fail a retry via FSI may - // work. But if scom fail was due to PIB error, retry via FSI may - // also fail. - l_rc = fapiPutScom(i_target, i_address, i_data); - if(l_rc) - { - FAPI_ERR("fapiPutScom retry via FSI failed."); - // Retry didn't work either so give up and pass - // back centaur scom error - } - } - - return l_rc; -} diff --git a/src/usr/hwpf/hwp/utility_procedures/p8_cpu_special_wakeup.C b/src/usr/hwpf/hwp/utility_procedures/p8_cpu_special_wakeup.C deleted file mode 100644 index ee59c8066..000000000 --- a/src/usr/hwpf/hwp/utility_procedures/p8_cpu_special_wakeup.C +++ /dev/null @@ -1,835 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/utility_procedures/p8_cpu_special_wakeup.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: p8_cpu_special_wakeup.C,v 1.22 2014/09/19 16:57:22 cmolsen Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_cpu_special_wakeup.C,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! OWNER NAME: Greg Still Email: stillgs@us.ibm.com -// *! -// *! To build - buildfapiprcd -C "p8_inst_pm_state.C" -e "../../xml/error_info/proc_cpu_special_wakeup_errors.xml,../../xml/error_info/p8_slw_registers.xml,../../xml/error_info/proc_mpipl_force_winkle_errors.xml" p8_cpu_special_wakeup.C -// *! -/// \file p8_cpu_special_wakeup.C -/// \brief Put targeted EX chiplets into special wake-up -/// -/// add to required proc ENUM requests -/// -/// High-level procedure flow: -/// \verbatim -/// -/// Based on "entity" parameter (OCC, FSP, PHYP), write the -/// appropriate Special Wakeup bit (different address) -/// -/// Poll for SPECIAL WAKEUP DONE -/// Polling timeouts need to account for the following (future version): -/// 1) All the chiplets are not in a Deep Idle state and will awaken in -/// < 1us (eg no PORE assistance needed) -/// -/// 2) All the chiplets are not in a Deep Sleep or less (run of nap) in -/// which case all can be in special wake-up in ~5ms state -/// -/// 3) Some chiplets are in Deep Sleep and some are in Deep Winkle -/// which case there is a serialization of the two exits (5ms (Sleep) -/// and 10ms (Winkle). -/// -/// Thus, do a progressive poll (in a future version). -/// Wait 1us -/// poll -/// if done, exit -/// pollcount=0 -/// do -/// wait 5ms -/// poll -/// if done, exit -/// pollcount++ -/// while pollcount<5 (eg 25ms) -/// flag timout error /// Timeouts on polling are progressive -/// -/// -/// Procedure Prereq: -/// - System clocks are running -/// - Caller must follow these rules: -/// - On a successful assertion of spwu, deassert afterwards! -/// - On an unsuccessful assertion of spwu, do NOT deassert afterwards! -/// \endverbatim -/// -/// -//------------------------------------------------------------------------------ - - -// ---------------------------------------------------------------------- -// Includes -// ---------------------------------------------------------------------- - -#include "p8_pm.H" -#include "p8_cpu_special_wakeup.H" -#include "p8_pcb_scom_errors.H" -//#include "../../../../../include/usr/hwpf/hwp/utility_procedures/p8_inst_pm_state.H" -#include "p8_inst_pm_state.H" -extern "C" { - -using namespace fapi; - - -/// \param[in] i_ex_target EX Target -/// \param[in] i_operation ENABLE, DISABLE, INIT -/// \param[in] entity Entity bit to use (OCC, PHYP, FSP) - -/// \retval PM_SUCCESS if something good happens, -/// \retval PM_PROCPM_SPCWKUP* otherwise -fapi::ReturnCode -p8_cpu_special_wakeup( const fapi::Target& i_ex_target, - PROC_SPCWKUP_OPS i_operation , - PROC_SPCWKUP_ENTITY i_entity ) - -{ - fapi::ReturnCode rc; - fapi::ReturnCode oha_rc; - uint32_t e_rc = 0; - ecmdDataBufferBase data(64); - ecmdDataBufferBase fsi_data(64); - ecmdDataBufferBase polldata(64); - - fapi::Target l_parentTarget; - uint8_t attr_chip_unit_pos = 0; - - const char* PROC_SPCWKUP_ENTITY_NAMES[] = - { - "HOST", - "FSP", - "OCC", - "PHYP", - "SPW_ALL" - }; - - const char* PROC_SPCWKUP_OPS_NAMES[] = - { - "DISABLE", - "ENABLE", - "INIT" - }; - - uint32_t special_wakeup_max_polls; - - /// Time (binary in milliseconds) for the first poll check (running/nap - /// case. - /// uint32_t special_wakeup_quick_poll_time = 1; - - /// Get an attribute that defines the maximum special wake-up polling - /// timing (binary in milliseconds). - /// Increased timeout to 200ms - 6/10/13 - - uint32_t special_wakeup_timeout = 200; - - /// Get an attribute that defines the special wake-up polling interval - /// (binary in milliseconds). - uint32_t special_wakeup_poll_interval = 5; - - uint32_t pollcount = 0; - uint32_t count = 0; - - std::vector<fapi::Target> l_chiplets; - std::vector<Target>::iterator itr; - - uint8_t oha_spwkup_flag = 0; - uint8_t ignore_xstop_flag = 0; - bool poll_during_xstop_flag = false; - bool xstop_flag = false; - bool bSpwuSetOnEntry = false; - - uint8_t inst_pm_state = INST_PM_STATE_UNDEFINED; - - //-------------------------------------------------------------------------- - // Read the counts of different ENTITY (FSP,OCC,PHYP) from the Attributes - //-------------------------------------------------------------------------- - - uint32_t phyp_spwkup_count = 0; - uint32_t fsp_spwkup_count = 0; - uint32_t occ_spwkup_count = 0; - - uint64_t spwkup_address = 0; - uint64_t history_address = 0; - - // detect AISS capaiblity - uint8_t chipHasAISSSWUP = 0; - - do - { - - FAPI_INF("Executing p8_cpu_special_wakeup %s for %s ...", - PROC_SPCWKUP_OPS_NAMES[i_operation], - PROC_SPCWKUP_ENTITY_NAMES[i_entity]); - - // Initialize the attributes to 0. - if (i_operation == SPCWKUP_INIT) - { - FAPI_INF("Processing target %s", i_ex_target.toEcmdString()); - FAPI_INF("Initializing ATTR_PM_SPWUP_FSP"); - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_FSP, &i_ex_target, fsp_spwkup_count); - if (rc) - { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_FSP with rc = 0x%x", (uint32_t)rc); - break ; - } - - FAPI_INF("Initializing ATTR_PM_SPWUP_OCC"); - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OCC, &i_ex_target, occ_spwkup_count); - if (rc) - { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OCC with rc = 0x%x", (uint32_t)rc); - break; - } - - FAPI_INF("Initializing ATTR_PM_SPWUP_PHYP"); - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_PHYP, &i_ex_target, phyp_spwkup_count); - if (rc) - { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_PHYP with rc = 0x%x", (uint32_t)rc); - break; - } - - FAPI_INF("Initializing ATTR_PM_SPWUP_OHA_FLAG"); - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_ex_target, oha_spwkup_flag); - if (rc) - { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); - break; - } - - FAPI_INF("Initializing ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG"); - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG, &i_ex_target, ignore_xstop_flag); - if (rc) - { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG with rc = 0x%x", (uint32_t)rc); - break ; - } - - // Leave the procedure - break; - } - - //-------------------------------------------------------------------------- - // Checking the ENTITY who raised this OPERATION - //-------------------------------------------------------------------------- - - // Get the parent chip to target the registers - rc = fapiGetParentChip(i_ex_target, l_parentTarget); - if (rc) - { - break; // throw error - } - - // Get the core number - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_ex_target, attr_chip_unit_pos); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc); - break; - } - - FAPI_DBG("Core number = %d", attr_chip_unit_pos); - - // Read the Attributes to know the Special_wake counts from each entity - // This should be different for different EX chiplets. - rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_FSP, &i_ex_target, fsp_spwkup_count); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_FSP with rc = 0x%x", (uint32_t)rc); - break; - } - - rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_OCC, &i_ex_target, occ_spwkup_count ); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_OCC with rc = 0x%x", (uint32_t)rc); - break; - } - - rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_PHYP,&i_ex_target , phyp_spwkup_count ); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_PHYP with rc = 0x%x", (uint32_t)rc); - break; - } - - /// Calculate the maximum number of polls until a timeout is thrown - special_wakeup_max_polls = special_wakeup_timeout / special_wakeup_poll_interval; - - // Process counts based on the calling entity - if (i_entity == OCC) - { - count = occ_spwkup_count ; - FAPI_INF("OCC count before = %d" , count); - spwkup_address = PM_SPECIAL_WKUP_OCC_0x100F010C; - history_address = EX_PMSTATEHISTOCC_REG_0x100F0112; - } - else if (i_entity == FSP) - { - count = fsp_spwkup_count ; - FAPI_INF("FSP count before = %d" , count); - spwkup_address = PM_SPECIAL_WKUP_FSP_0x100F010B; - history_address = EX_PMSTATEHISTFSP_REG_0x100F0111; - } - else if (i_entity == PHYP) - { - count = phyp_spwkup_count ; - FAPI_INF("PHYP count before = %d" , count); - spwkup_address = PM_SPECIAL_WKUP_PHYP_0x100F010D; - history_address = EX_PMSTATEHISTPHYP_REG_0x100F0110; - } - else - { - FAPI_ERR("Unknown entity passed to proc_special_wakeup. Entity %x ....", i_entity); - // I_ENTITY = i_entity; - PROC_SPCWKUP_ENTITY & I_ENTITY = i_entity ; - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SPCWKUP_CODE_BAD_ENTITY); - break; - } - - ///////////////////////////////////////////////////////////////////////////// - // Checking the type of OPERATION and process the request - ///////////////////////////////////////////////////////////////////////////// - - rc=fapiGetScom(i_ex_target, EX_PMGP0_0x100F0100, data); - if(rc) - { - break; - } - - if (i_operation == SPCWKUP_ENABLE) - { - - // If the OHA flag is set, then any subsequent calls to the this - // procedure must return a "good" response or else an infinite - // loop results for any calling algorithm that first sets - // special wake-up, does a SCOM, and then clears special - // wake-up. - rc = FAPI_ATTR_GET( ATTR_PM_SPWUP_OHA_FLAG, - &i_ex_target, - oha_spwkup_flag); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); - break; - } - - if (oha_spwkup_flag) - { - FAPI_INF("OHA special wakeup flag is set so returning with good response to break recursion. Counts are NOT updated."); - // This is a purposeful mid-procedure return - return rc; - } - - // Determine if xstop checking should be ignored base on a caller - // set attribute. - // - // This is used during MPIPL clean-up to a core to clear FIRs that - // will eventually clear the xstop condition. However, to do so - // needs the xstop check to not keep the special wake-up operation - // from happening. - rc = FAPI_ATTR_GET( ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG, - &i_ex_target, - ignore_xstop_flag); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG with rc = 0x%x", (uint32_t)rc); - break ; - } - - FAPI_INF("Ignore XSTOP: %s", (ignore_xstop_flag ? "YES" : "NO")); - - // Read system checkstop indicator - GETSCOM(rc, l_parentTarget, PCBMS_INTERRUPT_TYPE_REG_0x000F001A, data); - - if( data.isBitSet( 2 ) ) - { - FAPI_INF( "Checkstop present" ); - xstop_flag = true; - } - - // Error out if system is checkstopped and not told to ignore it - if (!ignore_xstop_flag && xstop_flag) - { - FAPI_ERR( "This chip is xstopped and the attribute ATTR_PM_SPWUP_IGNORE_XSTOP_FLAG is NOT set" ); - const uint64_t& PCBSINTRTYPE = data.getDoubleWord(0); - const uint8_t & ATTRIGNOREXSTOP = ignore_xstop_flag; - const fapi::Target & EX_TARGET = i_ex_target; - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_CHKSTOP); - break; - } - - // Proceed - FAPI_INF("Setting Special Wake-up ...") ; - - if (count == 0) - { - - GETSCOM(rc, i_ex_target, spwkup_address, data); - - //cmo-20140710: Make a note of spwu is already asserted. - if (data.isBitSet(0)) - bSpwuSetOnEntry = true; // Due to rogue direct hw access. - else - bSpwuSetOnEntry = false; // Just goodness.. - - e_rc = data.flushTo0(); - e_rc |= data.setBit(0); - E_RC_CHECK(e_rc, rc); - - PUTSCOM(rc, i_ex_target, spwkup_address, data); - - // Determine whether to poll for completion of Special wake-up. - // Running and Nap - can alsways be polled as these are not - // dependent on an xstop condition. - // Sleep and Winkle - poll only if not in an xstop condition - - // Get the IPMS state - rc = ex_determine_inst_pm_state(i_ex_target, 10000, 1, inst_pm_state); - if (!rc.ok() && inst_pm_state!=INST_PM_STATE_UNRESOLVED) - { - FAPI_ERR("ex_determine_inst_pm_state() failed w/rc=0x%x", (uint32_t)rc); - break; - } - FAPI_DBG("IPMS State = 0x%x", inst_pm_state); - - switch(inst_pm_state) - { - case INST_PM_STATE_RUN : // Running - case INST_PM_STATE_RUN_OHA_ENTRY : // OHA purging idle entry - case INST_PM_STATE_NAP_STATIC : // Nap - poll_during_xstop_flag = true; - break; - - default : // Any other IPMS state - poll_during_xstop_flag = false; - break; - } - - // Poll for completion if conditions are right - if ( (!xstop_flag) || (xstop_flag && poll_during_xstop_flag) ) - { - // poll for the set completion - pollcount = 0; - e_rc=data.flushTo0(); - E_RC_CHECK(e_rc, rc); - - while (data.isBitClear(31) && pollcount < special_wakeup_max_polls) - { - GETSCOM(rc, i_ex_target, EX_PMGP0_0x100F0100, data); - FAPI_DBG(" Loop get for PMGP0(31) to goto 1 => 0x%016llx", data.getDoubleWord(0)); - - rc = fapiDelay(special_wakeup_poll_interval*1000, 1000000); - if (rc) - { - break; - } - pollcount ++ ; - } - if (!rc.ok()) - { - break; - } - - - rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_AISS_SPECIAL_WAKEUP, - &i_ex_target, - chipHasAISSSWUP); - if (rc) - { - FAPI_ERR("Error querying Chip EC feature: " - "ATTR_CHIP_EC_FEATURE_PCBS_ERR_RESET"); - break; - } - - FAPI_INF("AISS Special Wake-up fix is %sbeing performed", - (chipHasAISSSWUP ? "NOT " : "")); - - - if (!chipHasAISSSWUP) - { - // Workaround for HW255321 start here - // at timeout time: - // - check for existing external interrupts or malf alerts pending : PMGP0 bit52 - // AND if OHA is in the AISS-FSM-state P7_SEQ_WAIT_INT_PENDING EX_OHA_RO_STATUS_REG_0x1002000B - // If yes - then OHA hangs - // To leave this FSM state: - // - Set Bit 9 of OHA_ARCH_IDLE_STATE_REG( RESET_IDLE_STATE_SEQUENCER). EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 - // This resets the idle sequencer and force OHA into the DO_NOTHING_STATE ...should be completed in the next cycle - // - // Continue further down and check special_wakeup completion by checking bit31 of EX_PMGP0_0x100F0100 - // If set then is OHA awake else error - - - GETSCOM(rc, i_ex_target, EX_PMGP0_0x100F0100, data); - - if (data.isBitClear(31) && data.isBitSet(52) ) - { - FAPI_DBG("Timed out setting Special wakeup with regular wake-up available, the logical OR of external interrupt and malfunction alert ... "); - FAPI_DBG("Checking for Hang-Situation in AISS-FSM-State P7_SEQ_WAIT_INT_PENDING ... "); - FAPI_DBG("Special Wake-up Done NOT asserted (PMGP0(31,52)!! =>0x%016llx", data.getDoubleWord(0)); - - oha_spwkup_flag = 1; - - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_ex_target, oha_spwkup_flag); - if (rc) - { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); - break; - } - FAPI_INF("Set OHA special wakeup flag"); - - // Check now if OHA is in the AISS-FSM-state P7_SEQ_WAIT_INT_PENDING EX_OHA_RO_STATUS_REG_0x1002000B (bit 13-19) 0b0011100 - GETSCOM(rc, i_ex_target, EX_OHA_RO_STATUS_REG_0x1002000B, data); - - FAPI_DBG("\tCURRENT_AISS_FSM_STATE_VECTOR (OHA_RO_STATUS(13:19) => 0x%016llx", data.getDoubleWord(0)); - - if (data.isBitClear(13) && // 0 - data.isBitClear(14) && // 0 - data.isBitSet(15) && // 1 - data.isBitSet(16) && // 1 - data.isBitSet(17) && // 1 - data.isBitClear(18) && // 0 - data.isBitClear(19) ) // 0 - { - FAPI_DBG("OHA hanging in AISS-FSM-state P7_SEQ_WAIT_INT_PENDING (0b11100) (OHA_RO_STATUS_REG(13:19) => 0x%016llx", data.getDoubleWord(0)); - FAPI_DBG("Start reset of IDLE STATE SEQUENCER: Set OHA_ARCH_IDLE_STATE_REG(9)"); - - GETSCOM(rc, i_ex_target, EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); - FAPI_DBG("\tEX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : 0x%016llx", data.getDoubleWord(0)); - - //Set RESET_IDLE_STATE_SEQUENCER ... Bit 9 of OHA_ARCH_IDLE_STATE_REG - e_rc=data.setBit(9); - E_RC_CHECK(e_rc, rc); - - PUTSCOM(rc, i_ex_target, EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); - - // This resets the idle sequencer and force OHA into the - // DO_NOTHING_STATE ... should be completed in the next - // cycle since special wakeup is still asserted, OHA should - // not leave the DO_NOTHING_STATE - - // Check again for AISS-FSM-state P7_SEQ_WAIT_INT_PENDING EX_OHA_RO_STATUS_REG_0x1002000B (bit 13-19) 0b11100 - GETSCOM(rc, i_ex_target, EX_OHA_RO_STATUS_REG_0x1002000B, data); - FAPI_DBG("\tCURRENT_AISS_FSM_STATE_VECTOR (OHA_RO_STATUS(13:19) => 0x%016llx", data.getDoubleWord(0)); - - // We're done accessing the OHA so clear the flag - oha_spwkup_flag = 0; - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_ex_target, oha_spwkup_flag); - if (rc) - { - FAPI_ERR("fapiSetAttribute to clear ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); - // This is a purposeful mid-procedure return - return rc; - } - FAPI_INF("Cleared OHA special wakeup flag"); - } - } - - // Check again if special_wakeup completed - GETSCOM(rc, i_ex_target, EX_PMGP0_0x100F0100, data); - - } // Workaround for HW255321 ends here - - if (data.isBitClear(31)) - { - FAPI_ERR("Timed out in setting the CPU in Special wakeup ... "); - - GETSCOM(rc, i_ex_target, EX_PMGP0_0x100F0100, data); - FAPI_DBG("Special Wake-up Done NOT asserted (PMGP0(31)!! =>0x%016llx", data.getDoubleWord(0)); - const uint64_t& PMGP0 = data.getDoubleWord(0); - - // The following are put in the procedure (vs the XML) to capture - // for Cronus debug - - GETSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" After set of SPWKUP_REG (0x%08llx) => 0x%016llx", spwkup_address, data.getDoubleWord(0)); - const uint64_t& SP_WKUP_REG_ADDRESS = spwkup_address; - const uint64_t& SP_WKUP_REG_VALUE = data.getDoubleWord(0); - - GETSCOM(rc, i_ex_target, history_address , data); - FAPI_DBG(" History addreess (0x%08llx) => 0x%016llx", history_address, data.getDoubleWord(0)); - const uint64_t& HISTORY_ADDRESS = history_address; - const uint64_t& HISTORY_VALUE = data.getDoubleWord(0); - - //cmo-20140710: We can't leave a latent spwu bit in 0x100f010b/c/d. Even though - // we gave it a very long time to complete, we can't take the chance that it - // fires later. So, lets clear it now. This will do no harm since the presumption - // at this point, anyway, is that it failed and so therefore it should be cleared - // too. - // Note, we only want to do this for count=0 and if bSpwuSetOnEntry==false as - // this would be an indication that we, right now, just asserted the spwu - // from a deasserted state. Therefore, we can safely also deassert it. - // Question is though, do we also wanna do the following if count>0, which - // would be a pretty messed up situation? - if (!bSpwuSetOnEntry) - { - e_rc=data.flushTo0(); - E_RC_CHECK(e_rc, rc); - PUTSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" Clearing SPWKUP_REG (0x%08llx) => 0x%016llx", spwkup_address, data.getDoubleWord(0)); - GETSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" After read (delay) of SPWKUP_REG (0x%08llx) 0x%016llx", spwkup_address, data.getDoubleWord(0)); - } - - const uint64_t& POLLCOUNT = (uint64_t)pollcount; - const uint64_t& EX = (uint64_t)attr_chip_unit_pos; - const uint64_t& ENTITY = (uint64_t)i_entity; - PROC_SPCWKUP_OPS& I_OPERATION = i_operation ; - - const fapi::Target & EX_IN_ERROR = i_ex_target; - const fapi::Target & CHIP = l_parentTarget; - - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SPCWKUP_TIMEOUT); - break; - - } - else - { - count++ ; - FAPI_INF("Special wakeup done is set. SUCCESS! ... "); - } - } // Done checking - else - { - FAPI_INF("Special wakeup with a checkstop active was attempted to a chiplet in an idle state that cannot succeed"); - const fapi::Target & EX_TARGET = i_ex_target; - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SPCWKUP_SLW_IN_CHKSTOP); - break; - } - } - // Count > 0 - else - { - // Check that we really are in special wakeup. - // If not, the counts are messed up - GETSCOM(rc, i_ex_target, EX_PMGP0_0x100F0100, data); - if (data.isBitSet(31)) - { - count++ ; - } - else - { - FAPI_ERR("Enabling special wakeup failed."); - FAPI_ERR("--> Reason is that %s COUNT > 0 but PMGP0(31) is not set", PROC_SPCWKUP_ENTITY_NAMES[i_entity]); - FAPI_ERR(" FSP_COUNT = %d , OCC_COUNT = %d , PHYP_COUNT = %d ", fsp_spwkup_count ,occ_spwkup_count ,phyp_spwkup_count); - const fapi::Target & EX_TARGET = i_ex_target; - const uint64_t & PMGP0 = data.getDoubleWord(0); - const uint32_t & ENTITY_COUNT = count; - const PROC_SPCWKUP_ENTITY & I_ENTITY = i_entity ; - FAPI_SET_HWP_ERROR( rc, RC_PROCPM_SPCWKUP_NOT_SET); - break; - } - } - } - else if (i_operation == SPCWKUP_DISABLE) - { - - FAPI_INF("Clearing Special Wake-up..."); - - // If the OHA flag is set, then any subsequent calls to the this - // procedure must return a "good" response or elso an infinite - // loop results for any calling algorithm that first sets - // special wake-up, does a SCOM, and then clears special - // wake-up. - - rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_OHA_FLAG, &i_ex_target, oha_spwkup_flag); - if (rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); - break; - } - - if (oha_spwkup_flag) - { - FAPI_INF("OHA special wakeup flag is set so returning with good response to break recursion. Counts are NOT updated."); - // This is a purposeful mid-procedure return - return rc; - } - - - if ( count == 1 ) - { - GETSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" Before clear of SPWKUP_REG (0x%08llx) => =>0x%016llx", spwkup_address, data.getDoubleWord(0)); - - e_rc=data.flushTo0(); - E_RC_CHECK(e_rc, rc); - - PUTSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" After clear putscom of SPWKUP_REG (0x%08llx) => 0x%016llx", spwkup_address, data.getDoubleWord(0)); - - // This puts an inherent delay in the propagation of the reset transition. - GETSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" After read (delay) of SPWKUP_REG (0x%08llx) 0x%016llx", spwkup_address, data.getDoubleWord(0)); - - count -- ; - } - else if ( count > 1 ) - { - FAPI_INF("Other processes have clear Special Wake-up pending. Chiplet is still in Special Wake-up state."); - count -- ; - } - else // Equal 0 - { - - // Check that we really are NOT in special wakeup. - // If not, clear that platform bit. This can occur in Cronus startup - GETSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" Checking of SPWKUP_REG disable (0x%08llx) => =>0x%016llx", spwkup_address, data.getDoubleWord(0)); - - if (data.isBitSet(0)) - { - e_rc=data.flushTo0(); - E_RC_CHECK(e_rc, rc); - - PUTSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" Clearing SPWKUP_REG (0x%08llx) => 0x%016llx", spwkup_address, data.getDoubleWord(0)); - - // This puts an inherent delay in the propagation of the reset transition. - GETSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" After read (delay) of SPWKUP_REG (0x%08llx) 0x%016llx", spwkup_address, data.getDoubleWord(0)); - } - } - - GETSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" After configuring SPWKUP_REG value =>0x%016llx", data.getDoubleWord(0)); - - } - else if (i_operation == SPCWKUP_FORCE_DEASSERT) - { - - GETSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" Before clear of SPWKUP_REG (0x%08llx) => =>0x%016llx", spwkup_address, data.getDoubleWord(0)); - - e_rc=data.flushTo0(); - E_RC_CHECK(e_rc, rc); - - PUTSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" After clear putscom of SPWKUP_REG (0x%08llx) => 0x%016llx", spwkup_address, data.getDoubleWord(0)); - - // This puts an inherent delay in the propagation of the reset transition. - GETSCOM(rc, i_ex_target, spwkup_address , data); - FAPI_DBG(" After read (delay) of SPWKUP_REG (0x%08llx) 0x%016llx", spwkup_address, data.getDoubleWord(0)); - - count = 0; - } - else - { - FAPI_ERR("ENABLE, DISABLE or INIT must be specified. Operation %x", i_operation ); - PROC_SPCWKUP_OPS & I_OPERATION = i_operation ; - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SPCWKUP_CODE_BAD_OP); - break; - } - - ///////////////////////////////////////////////// - // Update the attributes - ///////////////////////////////////////////////// - - if ( i_entity == OCC ) - { - occ_spwkup_count = count ; - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OCC, &i_ex_target, occ_spwkup_count ); - if (rc) - { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OCC with rc = 0x%x", (uint32_t)rc); - break; - } - } - else if (i_entity == FSP) - { - fsp_spwkup_count = count ; - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_FSP, &i_ex_target, fsp_spwkup_count ); - if (rc) - { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_FSP with rc = 0x%x", (uint32_t)rc); - break; - } - } - else if (i_entity == PHYP) - { - phyp_spwkup_count = count; - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_PHYP, &i_ex_target, phyp_spwkup_count ); - if (rc) - { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_PHYP with rc = 0x%x", (uint32_t)rc); - break; - } - } - - FAPI_INF (" FSP_COUNT = %d , OCC_COUNT = %d , PHYP_COUNT = %d ", fsp_spwkup_count ,occ_spwkup_count ,phyp_spwkup_count); - - - } while (0); - - // Clean up the OHA flag as it should not be set out of this exit (normal - // and error) path. Note: there is ia mid-procedure return above. - oha_rc = FAPI_ATTR_GET(ATTR_PM_SPWUP_OHA_FLAG, &i_ex_target, oha_spwkup_flag); - if (oha_rc) - { - FAPI_ERR("fapiGetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)oha_rc); - } - else - { - if (oha_spwkup_flag) - { - oha_spwkup_flag = 0; - - oha_rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_ex_target, oha_spwkup_flag); - if (oha_rc) - { - FAPI_ERR("fapiSetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)oha_rc); - } - - FAPI_ERR("Clearing OHA flag attribute upon procedure exit. This is NOT expected"); - PROC_SPCWKUP_OPS& I_OPERATION = i_operation ; - const uint64_t& EX = (uint64_t)attr_chip_unit_pos; - const uint64_t& ENTITY = (uint64_t)i_entity; - const uint64_t& PHYP_SPCWKUP_COUNT = (uint64_t)phyp_spwkup_count; - const uint64_t& FSP_SPCWKUP_COUNT = (uint64_t)fsp_spwkup_count; - const uint64_t& OCC_SPCWKUP_COUNT = (uint64_t)occ_spwkup_count; - FAPI_SET_HWP_ERROR(oha_rc, RC_PROCPM_SPCWKUP_OHA_FLAG_SET_ON_EXIT); - } - } - - // Exit with the proper return code. rc has priority over oha_rc as it indicates - // the first failure. - if (!rc.ok()) - { - return rc ; - } - else if (!oha_rc.ok()) - { - return oha_rc ; - } - else - { - return rc; - } -} - - -} //end extern C diff --git a/src/usr/hwpf/hwp/utility_procedures/p8_inst_pm_state.C b/src/usr/hwpf/hwp/utility_procedures/p8_inst_pm_state.C deleted file mode 100644 index efdf53914..000000000 --- a/src/usr/hwpf/hwp/utility_procedures/p8_inst_pm_state.C +++ /dev/null @@ -1,1151 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/utility_procedures/p8_inst_pm_state.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -//$Id: p8_inst_pm_state.C,v 1.20 2015/02/03 16:00:37 cswenson Exp $ -//$Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/p8_inst_pm_state.C,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2014 -// *! All Rights Reserved -- Property of IBM -/* - * @owner: Michael Olsen Email: cmolsen@us.ibm.com - * - * @file p8_inst_pm_state.C - * @brief Calculates the instantaneous PM state (IPMS) - * - */ -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <p8_inst_pm_state.H> -#include <p8_scom_addresses.H> - - -extern "C" -{ - -using namespace fapi; - -//------------------------------------------------------------------------------ -// @proc_name ex_determine_inst_pm_state() -//------------------------------------------------------------------------------ -// @brief Determine the Instantaneous PM State (IPMS) from PCBS FSM, PMC SV and PM HIST. -// -// @param[in] i_ex_target the EX chiplet target -// @param[in] i_pm_settle_usec the time to give the PM system to stabilize [usec] -// @param[in] i_pm_polls the number of times to poll the PM states -// @param[out] o_inst_pm_state the returned instantaneous pm state -// -// @return ReturnCode FAPI_RC_SUCCESS, platform error or FFDC specified error -// -//------------------------------------------------------------------------------ -fapi::ReturnCode ex_determine_inst_pm_state( const fapi::Target &i_ex_target, - uint32_t i_pm_settle_usec, - uint32_t i_pm_polls, - uint8_t &o_inst_pm_state) -{ - fapi::ReturnCode rc, rc_eco; //fapi return code value - uint32_t rc_ecmd=0; //ecmd return code value - fapi::Target l_parentTarget; - - ecmdDataBufferBase data(64); - ecmdDataBufferBase dataETR(64); - ecmdDataBufferBase dataPORRR0(64), dataPORRR1(64); - ecmdDataBufferBase dataPIRR0(64),dataPIRR1(64),dataPIRR2(64),dataPIRR3(64); - ecmdDataBufferBase dataPMGP1(64); - ecmdDataBufferBase dataSTATUS(64),dataDEBUG0(64),dataDEBUG1(64),dataPMCLFIR(64); - - uint64_t address=0x0; - uint64_t address_oha_status=0x0; - uint8_t ex_number=0xff; - - uint8_t oha_spwkup_flag = 0; - - uint32_t pcbs_fsm=0xff, pcbs_fsm_prev=0xff; - uint32_t trans_sv=0xff, trans_sv_etr=0xff; - uint32_t slw_chiplet_vec=0xff, slw_chiplet_vec_etr=0xff; - uint32_t pmhist_state=0xff; - uint32_t aiss_fsm=0xff; - uint32_t pmc_queue_state=0xff; - - uint32_t iFsmPoll=0; - uint64_t fsm_poll_interval_nsec=0; - - bool bPmcIsStuck=false; // False until we determine PM state regs unstable - bool bGoodState=true; // True until condition found deeming this False - bool bStateFound=false; // False until we have found valid IPMS state - - FAPI_INF("Determining the Instantaneous PM State (IPMS)"); - - o_inst_pm_state = INST_PM_STATE_UNDEFINED; - - do - { - - // Get the parent chip to target non-EX registers - rc = fapiGetParentChip( i_ex_target, l_parentTarget); - if (rc) - { - FAPI_ERR("fapiGetParentChip failed w/rc = 0x%x", (uint32_t)rc); - return rc; - } - - // Get the core number - rc = FAPI_ATTR_GET( ATTR_CHIP_UNIT_POS, &i_ex_target, ex_number); - if (rc) - { - FAPI_ERR("fapiGetAttribute(ATTR_CHIP_UNIT_POS) failed w/rc = 0x%x", (uint32_t)rc); - return rc; - } - - FAPI_INF(" Processing core number = %d", ex_number); - - // Just in case the state machines are still moving or to accomodate FSM - // transaction lags, let's monitor the ETR and PCBS for about 25ms. - // - - // Extract the PCB-slave FSM state. (Initial snapshot) - // - address = EX_PCBS_FSM_MONITOR2_REG_0x100F0171; - rc = fapiGetScom( i_ex_target, address, data); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - return rc; - } - rc_ecmd = data.extractToRight(&pcbs_fsm, 23, 7); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return rc; - } - pcbs_fsm_prev = pcbs_fsm; - - if (i_pm_polls == 0) // Can't allow zero denominator. - i_pm_polls = 1; - fsm_poll_interval_nsec = i_pm_settle_usec * 1000 / i_pm_polls; - - // Start monitoring the PM states - for (iFsmPoll=0; iFsmPoll<i_pm_polls; iFsmPoll++) - { - - //FAPI_INF("\tiFsmPoll=%d",iFsmPoll); - // Extract the PMC (PORRR0) start_vector. - // - address = PMC_PORRR0_REG_0x0006208E; - rc = fapiGetScom( l_parentTarget, address, dataPORRR0); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - return rc; - } - rc_ecmd = dataPORRR0.extractToRight(&trans_sv, 8, 4); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return rc; - } - - // Extract the SLW (PORRR1) chiplet vector - // - address = PMC_PORRR1_REG_0x0006208F; - rc = fapiGetScom( l_parentTarget, address, dataPORRR1); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - return rc; - } - rc_ecmd = dataPORRR1.extractToRight(&slw_chiplet_vec, 0, 16); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return rc; - } - slw_chiplet_vec = slw_chiplet_vec<<16; - - // Delay before looking at PCBS FSM again and ETR. - // - rc = fapiDelay( fsm_poll_interval_nsec, 100000); - if (rc) - { - FAPI_ERR("fapiDelay() error"); - return rc; - } - - // Extract the start_vector and the chiplet vector from the ETR and - // double check against content of PMC's PORRR0 and PORRR1. - // - address = PORE_SLW_EXE_TRIGGER_0x00068009; - rc = fapiGetScom( l_parentTarget, address, dataETR); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - return rc; - } - rc_ecmd = dataETR.extractToRight(&trans_sv_etr, 8, 4); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return rc; - } - rc_ecmd = dataETR.extractToRight(&slw_chiplet_vec_etr, 32, 16); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return rc; - } - slw_chiplet_vec_etr = slw_chiplet_vec_etr<<16; - - // Extract the PCB-slave FSM state. - // - address = EX_PCBS_FSM_MONITOR2_REG_0x100F0171; - rc = fapiGetScom( i_ex_target, address, data); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - return rc; - } - rc_ecmd = data.extractToRight(&pcbs_fsm, 23, 7); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return rc; - } - - // Compare now - if ( pcbs_fsm!=pcbs_fsm_prev || - ( slw_chiplet_vec!=0 && - ( (slw_chiplet_vec & ((uint32_t)0x80000000>>ex_number)) || - (slw_chiplet_vec_etr & ((uint32_t)0x80000000>>ex_number)) ) && - ( trans_sv!=trans_sv_etr || slw_chiplet_vec!=slw_chiplet_vec_etr ) ) ) - { - FAPI_INF(" PORRR register, ETR or PCBS FSM seem to be unstable (@iFsmPoll=%d):",iFsmPoll); - FAPI_INF(" Core: 0x%x", ex_number); - FAPI_INF(" PORRR0: 0x%016llx",dataPORRR0.getDoubleWord(0)); - FAPI_INF(" PORRR1: 0x%016llx",dataPORRR1.getDoubleWord(0)); - FAPI_INF(" ETR: 0x%016llx",dataETR.getDoubleWord(0)); - FAPI_INF(" PCBS-FSM (prev): 0x%x",pcbs_fsm_prev); - FAPI_INF(" PCBS-FSM (new): 0x%x",pcbs_fsm); - } - else if (iFsmPoll==(i_pm_polls-1)) - { - FAPI_INF(" PORRR register, ETR or PCBS FSM seem stable at last poll (@iFsmPoll=%d):",iFsmPoll); - FAPI_INF(" Core: 0x%x", ex_number); - FAPI_INF(" PORRR0: 0x%016llx",dataPORRR0.getDoubleWord(0)); - FAPI_INF(" PORRR1: 0x%016llx",dataPORRR1.getDoubleWord(0)); - FAPI_INF(" ETR: 0x%016llx",dataETR.getDoubleWord(0)); - FAPI_INF(" PCBS-FSM (prev): 0x%x",pcbs_fsm_prev); - FAPI_INF(" PCBS-FSM (new): 0x%x",pcbs_fsm); - } - - pcbs_fsm_prev = pcbs_fsm; - - } // End of for(iFsmPoll) - // End of monitoring the PM states - - // Deal with any unstable situation up front, but only those that relate to the current EX chiplet - // since the trans_sv can only be used to determine IPMS if it's related to the current EX chiplet. - // (Note, we can have an unstable situation where the PMC is stuck but with a request from another - // EX chiplet. But we'll deal with that when that other EX chiplet is/was the current EX chiplet.) - // - bPmcIsStuck = false; - if ( trans_sv!=trans_sv_etr && (slw_chiplet_vec & ((uint32_t)0x80000000>>ex_number)) ) - { - // This strongly suggests that we're stuck in the PMC. I.e., the PMC - // has arbitrated a request to the PORE but the PORE hasn't accepted - // it. In such a case, the PORE's ETR content will contain the most - // recently processed SV request but the PORRR0 will contain the new - // SV request. Note that the request, in principle, could be from the - // same chiplet. But there's no way the same chiplet would request - // the same idle transition which is why we only compare trans_svs. - FAPI_INF(" PMC is stuck - Request has been arbitrated but PORE isn't processing it"); - bPmcIsStuck = true; - } - - // Extract the PM HIST state. - // - address = EX_PMSTATEHISTPHYP_REG_0x100F0110; - rc = fapiGetScom( i_ex_target, address, data); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - return rc; - } - rc_ecmd = data.extractToRight(&pmhist_state, 0, 3); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return rc; - } - - // Extract the PMC Queue state from the PIRRx registers - // - address = PMC_PIRR0_REG_0x00062080 + ex_number/4; - rc = fapiGetScom( l_parentTarget, address, data); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - return rc; - } - rc_ecmd = data.extractToRight(&pmc_queue_state, (ex_number-(ex_number/4)*4)*8, 8); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return rc; - } - - - // Now we can determine the IPMS state from one of the five cases following below - // - bStateFound = false; - bGoodState = true; - - - // --------------------------------------------------------------------- - // 0. PMC-stuck window - // - // IPMS = f(trans_sv) if "trans_sv != trans_sv_etr - // --------------------------------------------------------------------- - // Determine if this is the PMC-stuck window where the PMC has arbitrated - // a request into the PORRR regs but, for whatever reason, the PORE has - // not accepted the request and thus the trans_sv_etr contains the most - // recently handled SV. - // Even though impossible, lets just make sure there is no queued - // request. - // Note that this state, from a chiplet PM perspective, is identical to - // a QUEUED state. - if (bPmcIsStuck && (pmc_queue_state & 0x80)==0) - { - FAPI_INF(" trans_sv=0x%x and trans_sv_etr=0x%x : Using PORRR0 to determine IPMS", trans_sv, trans_sv_etr); - - bStateFound = true; // Will get set false of no state found. - switch (trans_sv) - { - case PORRR_SV_FS_ENTRY : - o_inst_pm_state = INST_PM_STATE_QUEUED_FS_ENTRY; - break; - - case PORRR_SV_DS_ENTRY : - o_inst_pm_state = INST_PM_STATE_QUEUED_DS_ENTRY; - break; - - case PORRR_SV_FS_EXIT : - o_inst_pm_state = INST_PM_STATE_QUEUED_FS_EXIT; - break; - - case PORRR_SV_DS_EXIT : - o_inst_pm_state = INST_PM_STATE_QUEUED_DS_EXIT; - break; - - case PORRR_SV_FW_ENTRY : - o_inst_pm_state = INST_PM_STATE_QUEUED_FW_ENTRY; - break; - - case PORRR_SV_DW_ENTRY : - o_inst_pm_state = INST_PM_STATE_QUEUED_DW_ENTRY; - break; - - case PORRR_SV_FW_EXIT : - o_inst_pm_state = INST_PM_STATE_QUEUED_FW_EXIT; - break; - - case PORRR_SV_DW_EXIT : - o_inst_pm_state = INST_PM_STATE_QUEUED_DW_EXIT; - break; - - default : - FAPI_ERR("trans_sv=0x%x is an unsupported value", trans_sv); - o_inst_pm_state = INST_PM_STATE_UNRESOLVED; - const uint64_t & PCBS_FSM = pcbs_fsm; - const uint64_t & PMHIST_STATE = pmhist_state; - const uint64_t & PMC_QUEUE_STATE = pmc_queue_state; - const uint64_t & TRANS_SV = trans_sv; - const uint64_t & TRANS_SV_ETR = trans_sv_etr; - const fapi::Target & EX_TARGET = i_ex_target; - FAPI_SET_HWP_ERROR(rc, RC_IPMS_UNSUPPORTED_SV_VALUE); - return rc; - } - } - - if (bStateFound || !bGoodState) - break; - - - // --------------------------------------------------------------------- - // 1. OHA-entry window - // - // IPMS = f(aiss_fsm) if (pcbs_fsm,pmhist_state) = (IDLE, RUN) - // --------------------------------------------------------------------- - // Determine if this is an OHA-entry window case, i.e. before the - // PCB-slave has been pinged by the OHA. If so, #2, #3 and #4 below can - // be skipped as it's irrelevant whether the current ex chiplet is, or - // was, most recently processed by the SLW engine. Because in both cases - // the chiplet will be in the RUN state and it will have an idling PCBS. - // We need to examine the OHA status reg using these decision rules: - // - If OHA status is reachable and aiss_fsm==AISS_FSM_IDLE, then we're in RUN. - // - If OHA status is reachable and aiss_fsm!=AISS_FSM_IDLE, then we're in OHA window. - // - If OHA status is not reachable and PCB fence is up, then we're in OHA window. (I'm not sure about this one.) - // - if ( pcbs_fsm==PCBS_FSM_IDLE && - pmhist_state==PMHIST_STATE_RUN ) - { - FAPI_INF(" pcbs_fsm=0x%x and pmhist_state=0x%x : Using AISS FSM to determine IPMS", pcbs_fsm, pmhist_state); - - //----------------------------------- - // Spwu disable wrapper - SET FLAG - // (Make sure we don't recursively call spwu->inst_pm->spwu->etc.) - oha_spwkup_flag = 1; - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_ex_target, oha_spwkup_flag); - if (rc) - { - FAPI_ERR("p8_inst_pm_state(): fapiSetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); - return rc; - } - FAPI_INF("Set OHA special wakeup flag"); - //----------------------------------- - - // Determine clock status of OHA region - uint8_t oha_clk_status = 0x7; - rc = fapiGetScom( i_ex_target, EX_CLK_STATUS_0x10030008, data); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", EX_CLK_STATUS_0x10030008); - return rc; - } - - //----------------------------------- - // Spwu disable wrapper - CLEAR FLAG - oha_spwkup_flag = 0; - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_ex_target, oha_spwkup_flag); - if (rc) - { - FAPI_ERR("p8_inst_pm_state(): fapiSetAttribute to clear ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); - return rc; - } - FAPI_INF("Cleared OHA special wakeup flag"); - //----------------------------------- - - rc_ecmd = data.extractToRight(&oha_clk_status, 0, 3); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return rc; - } - - if (oha_clk_status) - { - o_inst_pm_state = INST_PM_STATE_UNDEFINED; - bStateFound = true; - break; - } - - //----------------------------------- - // Spwu disable wrapper - SET FLAG - // (Make sure we don't recursively call spwu->inst_pm->spwu->etc.) - oha_spwkup_flag = 1; - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_ex_target, oha_spwkup_flag); - if (rc) - { - FAPI_ERR("p8_inst_pm_state(): fapiSetAttribute of ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); - return rc; - } - FAPI_INF("Set OHA special wakeup flag"); - //----------------------------------- - - address_oha_status = EX_OHA_RO_STATUS_REG_0x1002000B; - rc_eco = fapiGetScom( i_ex_target, address_oha_status, data); - - //----------------------------------- - // Spwu disable wrapper - CLEAR FLAG - oha_spwkup_flag = 0; - rc = FAPI_ATTR_SET(ATTR_PM_SPWUP_OHA_FLAG, &i_ex_target, oha_spwkup_flag); - if (rc) - { - FAPI_ERR("p8_inst_pm_state(): fapiSetAttribute to clear ATTR_PM_SPWUP_OHA_FLAG with rc = 0x%x", (uint32_t)rc); - return rc; - } - FAPI_INF("Cleared OHA special wakeup flag"); - //----------------------------------- - - // Reacting to this rc_eco as follows.. - if (rc_eco.ok()) // ECO region still accessible - { - rc_ecmd = data.extractToRight(&aiss_fsm, 13, 7); - if (rc_ecmd) - { - rc.setEcmdError(rc_ecmd); - return rc; - } - if (aiss_fsm==0) - o_inst_pm_state = INST_PM_STATE_RUN; - else - o_inst_pm_state = INST_PM_STATE_RUN_OHA_ENTRY; - bStateFound = true; - break; - } - else - { // ECO region not accessible - // Determine if the likely reason for the scom failure is that the PCB - // fence is up and that the reason behind this is that the OHA has - // a hold on the PCB fence while in the OHA-window. - // cmo-20140511: I have never ended up here yet. Maybe it isn't the OHA - // that controls the PCB fence, but rather the PCBS? - address = EX_GP3_0x100F0012; - rc = fapiGetScom( i_ex_target, address, data); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - return rc; - } - - if (data.isBitSet(26)) - { // OHA-window - o_inst_pm_state = INST_PM_STATE_RUN_OHA_ENTRY; - bStateFound = true; - break; - } - else - { // All other Scom error - o_inst_pm_state = INST_PM_STATE_UNDEFINED; - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address_oha_status); - return rc_eco; - } - } - } - - if (bStateFound || !bGoodState) - break; - - - // --------------------------------------------------------------------------------- - // 2. Static state or Queued request for a chiplet that WAS NOT most recently processed. - // - // IPMS = f(pmhist_state,pmc_queue_state) if "ex_number NOT in slw_chiplet_vec" - // && "pending bit on" - // --------------------------------------------------------------------------------- - // If the current ex chiplet IS/WAS NOT being processed by the SLW - // engine's most recent idle assist, according to the PORRR0 SV, then we - // can determine its IPMS as follows: - // 1) If pcbs_fsm==IDLE, then chiplet's state is static (except for the case #1 - // above) and thus can be extracted from the PM HIST reg. - // 2) If pcbs_fsm==0x2e (idle entry), this can only mean that it's a queued - // idle entry request which has already completed the OHA-window in case #1 - // above and is now waiting for the PMC/SLW engine to complete their - // currently executing idle transition (for another chiplet). - // 3) If pcbs_fsm=={0x50,0x51,0x57} (idle exit), this can only mean that it's a - // queued idle exit request and is now waiting for the PMC/SLW engine to - // complete their currently executing idle transition (for another chiplet). - // 4) If pcbs_fsm==anything else, we don't know what this means and we give - // up. - if ((slw_chiplet_vec & ((uint32_t)0x80000000>>ex_number))==0) - { - FAPI_INF(" This EX chiplet WAS NOT most recently processed by the SLW engine => Checking if STATIC or QUEUED state."); - if ( pcbs_fsm == PCBS_FSM_IDLE ) - { - FAPI_INF(" pcbs_fsm=0x%x : In a STATIC state : Using PM HIST to determine IPMS", pcbs_fsm); - rc = ex_determine_ipms_from_pmhist( i_ex_target, pmhist_state, o_inst_pm_state, bGoodState); - if (rc.ok()) - { - bStateFound = true; - break; - } - else - { - FAPI_ERR("ex_determine_ipms_from_pmhist() failed w/rc=0x%08x", (uint32_t)rc); - return rc; - } - } - else if ( pcbs_fsm == PCBS_FSM_ANY_IDLE_ENTRY || - pcbs_fsm == PCBS_FSM_ANY_SLEEP_EXIT || - pcbs_fsm == PCBS_FSM_ANY_WINKLE_EXIT || - pcbs_fsm == PCBS_FSM_DEEP_WINKLE_EXIT ) - { - FAPI_INF(" pcbs_fsm=0x%x : Checking if in a QUEUED_{ENTRY,EXIT} state : Using PMC PIRRx to determine IPMS", pcbs_fsm); - rc = ex_determine_ipms_from_pirrx( i_ex_target, pcbs_fsm, pmc_queue_state, o_inst_pm_state, bGoodState); - if (rc.ok()) - { - FAPI_INF(" Yes, this is a queued request"); - bStateFound = true; - break; - } - else if (rc==fapi::RC_IPMS_PIRRX_NO_QUEUE_REQUEST) - { - FAPI_INF(" No, this is NOT a queued request"); - rc = fapi::FAPI_RC_SUCCESS; - bStateFound = false; - } - else - { - FAPI_ERR("ex_determine_ipms_from_pirrx() failed w/rc=0x%08x", (uint32_t)rc); - return rc; - } - } - else - { - o_inst_pm_state = INST_PM_STATE_UNRESOLVED; - FAPI_ERR("pcbs_fsm=0x%x in conjunction with pmc_queue_state=0x%x is an unsupported state", pcbs_fsm, pmc_queue_state); - FAPI_ERR(" PORRR0 reg: 0x%016llx",dataPORRR0.getDoubleWord(0)); - FAPI_ERR(" PORRR1 reg: 0x%016llx",dataPORRR1.getDoubleWord(0)); - FAPI_ERR(" ETR reg: 0x%016llx",dataETR.getDoubleWord(0)); - FAPI_ERR(" PCBS_FSM (prev): 0x%x",pcbs_fsm_prev); - FAPI_ERR(" PCBS_FSM (new): 0x%x",pcbs_fsm); - FAPI_ERR(" PMHIST: 0x%x",pmhist_state); - FAPI_ERR(" PMC_QUEUE_STATE: 0x%x",pmc_queue_state); - const uint64_t & PCBS_FSM = pcbs_fsm; - const uint64_t & PMHIST_STATE = pmhist_state; - const uint64_t & PMC_QUEUE_STATE = pmc_queue_state; - const fapi::Target & EX_TARGET = i_ex_target; - FAPI_SET_HWP_ERROR(rc, RC_IPMS_SUSPICIOUS_PCBS_FSM); - return rc; - } - } - - if (bStateFound || !bGoodState) - break; - - - // --------------------------------------------------------------------- - // 3. Active (non-queued) request - // - // IPMS = f(pcbs_fsm,trans_sv) if "ex_number in slw_chiplet_vec" - // --------------------------------------------------------------------- - // OK, so the ex chiplet is, or was, being processed by the SLW engine's - // current, or most recent, idle assist. The IPMS state can be deduced - // from the PCBS state in conjunction with the PMC's start_vector which - // indicates the idle transition. - if ((slw_chiplet_vec & ((uint32_t)0x80000000>>ex_number))!=0) - { - FAPI_INF(" This EX chiplet WAS MOST RECENTLY PROCESSED by the SLW engine => Checking PMC active events."); - - bStateFound = true; // Will get set false of no state found. - switch (pcbs_fsm) - { - case PCBS_FSM_IDLE: - FAPI_INF(" pcbs_fsm=0x%x : Using PM HIST to determine IPMS", pcbs_fsm); - rc = ex_determine_ipms_from_pmhist( i_ex_target, pmhist_state, o_inst_pm_state, bGoodState); - if (rc) - { - FAPI_ERR("ex_determine_ipms_from_pmhist() failed w/rc=0x%08x", (uint32_t)rc); - return rc; - } - break; - - case PCBS_FSM_ANY_IDLE_ENTRY: - FAPI_INF(" pcbs_fsm=0x%x : Using PMC SV to determine IPMS", pcbs_fsm); - if (trans_sv == PORRR_SV_FS_ENTRY) - o_inst_pm_state = INST_PM_STATE_FS_ENTRY; - else if (trans_sv == PORRR_SV_DS_ENTRY) - o_inst_pm_state = INST_PM_STATE_DS_ENTRY; - else if (trans_sv == PORRR_SV_FW_ENTRY) - o_inst_pm_state = INST_PM_STATE_FW_ENTRY; - else if (trans_sv == PORRR_SV_DW_ENTRY) - o_inst_pm_state = INST_PM_STATE_DW_ENTRY; - else - bStateFound = false; - break; - - case PCBS_FSM_ANY_SLEEP_EXIT: - FAPI_INF(" pcbs_fsm=0x%x : Using PMC SV to determine IPMS", pcbs_fsm); - if (trans_sv == PORRR_SV_FS_EXIT) - o_inst_pm_state = INST_PM_STATE_FS_EXIT; - else if (trans_sv == PORRR_SV_DS_EXIT) - o_inst_pm_state = INST_PM_STATE_DS_EXIT; - else - bStateFound = false; - break; - - case PCBS_FSM_ANY_WINKLE_EXIT: - FAPI_INF(" pcbs_fsm=0x%x : Using PMC SV to determine IPMS", pcbs_fsm); - if (trans_sv == PORRR_SV_FW_EXIT) - o_inst_pm_state = INST_PM_STATE_FW_EXIT; - else if (trans_sv == PORRR_SV_DW_EXIT) - o_inst_pm_state = INST_PM_STATE_DW_EXIT; - else - bStateFound = false; - break; - - case PCBS_FSM_DEEP_WINKLE_EXIT: - FAPI_INF(" pcbs_fsm=0x%x : Using PMC SV to determine IPMS", pcbs_fsm); - if (trans_sv == PORRR_SV_DW_EXIT) - o_inst_pm_state = INST_PM_STATE_DW_EXIT; - else - bStateFound = false; - break; - - default: - FAPI_INF(" pcbs_fsm=0x%x was not recognized",pcbs_fsm); - bGoodState = false; - break; - } - if (!bStateFound) - { - FAPI_INF(" No active event found"); - } - } - - if (bStateFound || !bGoodState) - break; - - - // ---------------------------------------------------------------------------------- - // 4. Queued request for a chiplet that WAS most recently processed. - // - // IPMS = f(pmhist_state,pmc_queue_state) if "not an active request" - // && "ex_number is in slw_chiplet_vec" - // && "trans_sv doesn't agree w/pcbs_fsm" - // && "pending bit on" - // ---------------------------------------------------------------------------------- - // If the current ex chiplet IS/WAS being processed by the SLW - // engine's most recent idle assist, according to the PORRR0 SV, then we - // can determine its IPMS as follows: - // 1) If pcbs_fsm==IDLE, then chiplet's state is static (except for the case #1 - // above) and thus can be extracted from the PM HIST reg. - // 2) If pcbs_fsm==0x2e (idle entry), this can only mean that it's a queued - // idle ENTRY request (for the SAME chiplet that most recently EXITED - // an idle state) and which has already completed the OHA-window in case #1 - // above. However, the ENTRY request has been caught by a xstop in the PCBS - // before the request had a chance to be arbitrated into the PMC master and - // it is now sitting in the PMC queue. - // 3) If pcbs_fsm=={0x50,0x51,0x57} (idle exit), this can only mean that it's a - // queued idle EXIT request(for the SAME chiplet that most recently ENTERED - // an idle state). However, the EXIT request has been caught by a xstop in - // the PCBS before the request had a chance to be arbitrated into the PMC - // master and is now sitting in the PMC queue. - // 4) If pcbs_fsm==anything else, we don't know what this means and we give - // up. - // - // Note that if we're here in step $3, we have bGoodState==true and bStateFound==false. The - // later means that step #3 failed because trans_sv and pscb_fsm disagree and that this is - // therefore a possible queued request for the same chiplet that was most recently - // processed by the SLW engine. - // - if ( (slw_chiplet_vec & ((uint32_t)0x80000000>>ex_number))!=0 ) - { - FAPI_INF(" This EX chiplet WAS most recently processed by the SLW engine, but it's NOT an active event => Checking PMC Queue."); - if ( pcbs_fsm == PCBS_FSM_ANY_IDLE_ENTRY || - pcbs_fsm == PCBS_FSM_ANY_SLEEP_EXIT || - pcbs_fsm == PCBS_FSM_ANY_WINKLE_EXIT || - pcbs_fsm == PCBS_FSM_DEEP_WINKLE_EXIT ) - { - FAPI_INF(" pcbs_fsm=0x%x : Should be in a QUEUED_{ENTRY,EXIT} state : Using PMC PIRRx to determine IPMS", pcbs_fsm); - rc = ex_determine_ipms_from_pirrx( i_ex_target, pcbs_fsm, pmc_queue_state, o_inst_pm_state, bGoodState); - if (rc.ok()) - { - FAPI_INF(" Yes, this is a queued request"); - bStateFound = true; - break; - } - else if (rc==fapi::RC_IPMS_PIRRX_NO_QUEUE_REQUEST) - { - FAPI_INF(" No, this is NOT a queued request"); - rc = fapi::FAPI_RC_SUCCESS; - bStateFound = false; - } - else - { - FAPI_ERR("ex_determine_ipms_from_pirrx() failed w/rc=0x%08x", (uint32_t)rc); - return rc; - } - } - else - { - o_inst_pm_state = INST_PM_STATE_UNRESOLVED; - FAPI_ERR("pcbs_fsm=0x%x in conjunction with pmc_queue_state=0x%x is an unsupported state", pcbs_fsm, pmc_queue_state); - FAPI_ERR(" PORRR0 reg: 0x%016llx",dataPORRR0.getDoubleWord(0)); - FAPI_ERR(" PORRR1 reg: 0x%016llx",dataPORRR1.getDoubleWord(0)); - FAPI_ERR(" ETR reg: 0x%016llx",dataETR.getDoubleWord(0)); - FAPI_ERR(" PCBS_FSM (prev): 0x%x",pcbs_fsm_prev); - FAPI_ERR(" PCBS_FSM (new): 0x%x",pcbs_fsm); - FAPI_ERR(" PMHIST: 0x%x",pmhist_state); - FAPI_ERR(" PMC_QUEUE_STATE: 0x%x",pmc_queue_state); - const uint64_t & PCBS_FSM = pcbs_fsm; - const uint64_t & PMHIST_STATE = pmhist_state; - const uint64_t & PMC_QUEUE_STATE = pmc_queue_state; - const fapi::Target & EX_TARGET = i_ex_target; - FAPI_SET_HWP_ERROR(rc, RC_IPMS_SUSPICIOUS_PCBS_FSM); - return rc; - } - } - - if (bStateFound || !bGoodState) - break; - - - // ---------------------------------------------------------------------------------- - // 5. PCBS active but request has not yet been queued. - // - // IPMS = f(pmhist_state,pmgp3_state) if "not an active event" - // && "not a static state" - // && "not a queued request" - // - // - // In order to be here, at case #5, it has been determined that above that - // - this is not in the OHA-window - // - this is not an active event - // - this is not a static state - // - this is not a queued request - // Thus, this is probably the INST_PM_STATE_PCBS_xyz state. - // - FAPI_INF(" This is probably the INST_PM_STATE_PCBS_xyz. Determine which of the five possible states it might be."); - - // Extract FAST/DEEP status from PM GP1 - // - address = EX_PMGP1_0x100F0103; - rc = fapiGetScom( i_ex_target, address, dataPMGP1); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - return rc; - } - - switch (pcbs_fsm) - { - - case PCBS_FSM_ANY_IDLE_ENTRY : - o_inst_pm_state = INST_PM_STATE_PCBS_ANY_ENTRY; - bStateFound = true; - break; - - case PCBS_FSM_ANY_SLEEP_EXIT : - if (dataPMGP1.getDoubleWord(0)&((uint64_t)0x20000000)<<32) - { - o_inst_pm_state = INST_PM_STATE_PCBS_DS_EXIT; - } - else - { - o_inst_pm_state = INST_PM_STATE_PCBS_FS_EXIT; - } - bStateFound = true; - break; - - case PCBS_FSM_ANY_WINKLE_EXIT : - if (dataPMGP1.getDoubleWord(0)&((uint64_t)0x04000000)<<32) - { - o_inst_pm_state = INST_PM_STATE_PCBS_DW_EXIT; - } - else - { - o_inst_pm_state = INST_PM_STATE_PCBS_FW_EXIT; - } - bStateFound = true; - break; - - case PCBS_FSM_DEEP_WINKLE_EXIT : - o_inst_pm_state = INST_PM_STATE_PCBS_DW_EXIT; - bStateFound = true; - break; - - default: - FAPI_ERR("pcbs_fsm=0x%x is unsupported for identification in this context.", pcbs_fsm); - o_inst_pm_state = INST_PM_STATE_UNRESOLVED; - bStateFound = false; - break; - - } - - - } while(0); - - - if (!bGoodState) - { - address = PMC_PIRR0_REG_0x00062080; - fapiGetScom( l_parentTarget, address, dataPIRR0); - address = PMC_PIRR0_REG_0x00062081; - fapiGetScom( l_parentTarget, address, dataPIRR1); - address = PMC_PIRR0_REG_0x00062082; - fapiGetScom( l_parentTarget, address, dataPIRR2); - address = PMC_PIRR0_REG_0x00062083; - fapiGetScom( l_parentTarget, address, dataPIRR3); - address = PORE_SLW_STATUS_0x00068000; - fapiGetScom( l_parentTarget, address, dataSTATUS); - address = PORE_SLW_DBG0_0x0006800F; - fapiGetScom( l_parentTarget, address, dataDEBUG0); - address = PORE_SLW_DBG1_0x00068010; - fapiGetScom( l_parentTarget, address, dataDEBUG1); - address = PMC_LFIR_0x01010840; - fapiGetScom( l_parentTarget, address, dataPMCLFIR); - FAPI_ERR("Conflicting PM state values for core=0x%x:", ex_number); - FAPI_ERR(" PORRR0 reg: 0x%016llx",dataPORRR0.getDoubleWord(0)); - FAPI_ERR(" PORRR1 reg: 0x%016llx",dataPORRR1.getDoubleWord(0)); - FAPI_ERR(" ETR reg: 0x%016llx",dataETR.getDoubleWord(0)); - FAPI_ERR(" PCBS_FSM (prev): 0x%x",pcbs_fsm_prev); - FAPI_ERR(" PCBS_FSM (new): 0x%x",pcbs_fsm); - FAPI_ERR(" PMHIST: 0x%x",pmhist_state); - FAPI_ERR(" PMC_QUEUE_STATE: 0x%x",pmc_queue_state); - FAPI_ERR(" IPMS_STATE: 0x%x", o_inst_pm_state); - FAPI_ERR(" PIRR0 reg: 0x%016llx",dataPIRR0.getDoubleWord(0)); - FAPI_ERR(" PIRR1 reg: 0x%016llx",dataPIRR1.getDoubleWord(0)); - FAPI_ERR(" PIRR2 reg: 0x%016llx",dataPIRR2.getDoubleWord(0)); - FAPI_ERR(" PIRR3 reg: 0x%016llx",dataPIRR3.getDoubleWord(0)); - FAPI_ERR(" PORE STATUS reg: 0x%016llx",dataSTATUS.getDoubleWord(0)); - FAPI_ERR(" PORE DEBUG0 reg: 0x%016llx",dataDEBUG0.getDoubleWord(0)); - FAPI_ERR(" PORE DEBUG1 reg: 0x%016llx",dataDEBUG1.getDoubleWord(0)); - FAPI_ERR(" PMC_LFIR_0x01010840: 0x%016llx",dataPMCLFIR.getDoubleWord(0)); - const uint64_t & PORRR0_REG = dataPORRR0.getDoubleWord(0); - const uint64_t & PORRR1_REG = dataPORRR1.getDoubleWord(0); - const uint64_t & ETR_REG = dataETR.getDoubleWord(0); - const uint64_t & PCBS_FSM_PREV = pcbs_fsm_prev; - const uint64_t & PCBS_FSM = pcbs_fsm; - const uint64_t & PMHIST_STATE = pmhist_state; - const uint64_t & PMC_QUEUE_STATE = pmc_queue_state; - const uint64_t & IPMS_STATE = o_inst_pm_state; - const uint64_t & PIRR0_REG = dataPIRR0.getDoubleWord(0); - const uint64_t & PIRR1_REG = dataPIRR1.getDoubleWord(0); - const uint64_t & PIRR2_REG = dataPIRR2.getDoubleWord(0); - const uint64_t & PIRR3_REG = dataPIRR3.getDoubleWord(0); - const fapi::Target & EX_TARGET = i_ex_target; - FAPI_SET_HWP_ERROR(rc, RC_IPMS_CONFLICTING_IDLE_STATES); - o_inst_pm_state = INST_PM_STATE_UNRESOLVED; - return rc; - } - - if (bStateFound) - { - FAPI_INF("\tp8_inst_pm_state() successful - Final IPMS state: 0x%x => %s", o_inst_pm_state, INST_PM_STATE_NAMES[o_inst_pm_state]); - } - else - { - address = PMC_PIRR0_REG_0x00062080; - fapiGetScom( l_parentTarget, address, dataPIRR0); - address = PMC_PIRR0_REG_0x00062081; - fapiGetScom( l_parentTarget, address, dataPIRR1); - address = PMC_PIRR0_REG_0x00062082; - fapiGetScom( l_parentTarget, address, dataPIRR2); - address = PMC_PIRR0_REG_0x00062083; - fapiGetScom( l_parentTarget, address, dataPIRR3); - address = PORE_SLW_STATUS_0x00068000; - fapiGetScom( l_parentTarget, address, dataSTATUS); - address = PORE_SLW_DBG0_0x0006800F; - fapiGetScom( l_parentTarget, address, dataDEBUG0); - address = PORE_SLW_DBG1_0x00068010; - fapiGetScom( l_parentTarget, address, dataDEBUG1); - address = PMC_LFIR_0x01010840; - fapiGetScom( l_parentTarget, address, dataPMCLFIR); - FAPI_ERR("p8_inst_pm_state() unsuccessful - Shouldn't be here - Could be a code error"); - FAPI_ERR(" PORRR0 reg: 0x%016llx",dataPORRR0.getDoubleWord(0)); - FAPI_ERR(" PORRR1 reg: 0x%016llx",dataPORRR1.getDoubleWord(0)); - FAPI_ERR(" ETR reg: 0x%016llx",dataETR.getDoubleWord(0)); - FAPI_ERR(" PCBS_FSM (prev): 0x%x",pcbs_fsm_prev); - FAPI_ERR(" PCBS_FSM (new): 0x%x",pcbs_fsm); - FAPI_ERR(" PMHIST: 0x%x",pmhist_state); - FAPI_ERR(" PMC_QUEUE_STATE: 0x%x",pmc_queue_state); - FAPI_ERR(" IPMS_STATE: 0x%x", o_inst_pm_state); - FAPI_ERR(" PIRR0 reg: 0x%016llx",dataPIRR0.getDoubleWord(0)); - FAPI_ERR(" PIRR1 reg: 0x%016llx",dataPIRR1.getDoubleWord(0)); - FAPI_ERR(" PIRR2 reg: 0x%016llx",dataPIRR2.getDoubleWord(0)); - FAPI_ERR(" PIRR3 reg: 0x%016llx",dataPIRR3.getDoubleWord(0)); - FAPI_ERR(" PORE STATUS reg: 0x%016llx",dataSTATUS.getDoubleWord(0)); - FAPI_ERR(" PORE DEBUG0 reg: 0x%016llx",dataDEBUG0.getDoubleWord(0)); - FAPI_ERR(" PORE DEBUG1 reg: 0x%016llx",dataDEBUG1.getDoubleWord(0)); - FAPI_ERR(" PMC_LFIR_0x01010840: 0x%016llx",dataPMCLFIR.getDoubleWord(0)); - const uint64_t & PORRR0_REG = dataPORRR0.getDoubleWord(0); - const uint64_t & PORRR1_REG = dataPORRR1.getDoubleWord(0); - const uint64_t & ETR_REG = dataETR.getDoubleWord(0); - const uint64_t & PCBS_FSM_PREV = pcbs_fsm_prev; - const uint64_t & PCBS_FSM = pcbs_fsm; - const uint64_t & PMHIST_STATE = pmhist_state; - const uint64_t & PMC_QUEUE_STATE = pmc_queue_state; - const uint64_t & IPMS_STATE = o_inst_pm_state; - const uint64_t & PIRR0_REG = dataPIRR0.getDoubleWord(0); - const uint64_t & PIRR1_REG = dataPIRR1.getDoubleWord(0); - const uint64_t & PIRR2_REG = dataPIRR2.getDoubleWord(0); - const uint64_t & PIRR3_REG = dataPIRR3.getDoubleWord(0); - const fapi::Target & EX_TARGET = i_ex_target; - FAPI_SET_HWP_ERROR(rc, RC_IPMS_STATE_NOT_FOUND_BUG); - o_inst_pm_state = INST_PM_STATE_UNRESOLVED; - return rc; - } - - return rc; -} - - -//------------------------------------------------------------------------------ -// @proc_name ex_determine_ipms_from_pmhist() -//------------------------------------------------------------------------------ -// @brief Determine the Instantaneous PM State (IPMS) strictly from the PM HIST register. -// -// @param[in] i_ex_target' the EX chiplet target -// @param[in] i_pmhist_state' the PM HIST state -// @param[out] o_inst_pm_state' the returned instantaneous pm state -// @param[out] o_bGoodState' the returned IPMS state qualifier -// -// @return ReturnCode FAPI_RC_SUCCESS, platform error or FFDC specified error -// -//------------------------------------------------------------------------------ -fapi::ReturnCode ex_determine_ipms_from_pmhist( const fapi::Target &i_ex_target, - uint32_t i_pmhist_state, - uint8_t &o_inst_pm_state, - bool &o_bGoodState ) -{ - fapi::ReturnCode rc; //fapi return code value - - bool bCodeBug=false; - - o_bGoodState = true; - bCodeBug = false; - - switch (i_pmhist_state) - { - case PMHIST_STATE_RUN: - o_inst_pm_state = INST_PM_STATE_RUN; - break; - - case PMHIST_STATE_SPECIAL_WAKEUP: - o_inst_pm_state = INST_PM_STATE_SPECIAL_WAKEUP; - break; - - case PMHIST_STATE_NAP: - o_inst_pm_state = INST_PM_STATE_NAP_STATIC; - break; - - case PMHIST_STATE_LEGACY_SLEEP: // No hw support for this state in p8 - FAPI_ERR("pmhist_state = 0x%x = %s not supported. Check code.", - i_pmhist_state, PMHIST_STATE_NAMES[i_pmhist_state]); - o_inst_pm_state = INST_PM_STATE_UNRESOLVED; - o_bGoodState = false; - bCodeBug = true; - break; - - case PMHIST_STATE_FAST_SLEEP: - o_inst_pm_state = INST_PM_STATE_FS_STATIC; - break; - - case PMHIST_STATE_DEEP_SLEEP: - o_inst_pm_state = INST_PM_STATE_DS_STATIC; - break; - - case PMHIST_STATE_FAST_WINKLE: - o_inst_pm_state = INST_PM_STATE_FW_STATIC; - break; - - case PMHIST_STATE_DEEP_WINKLE: - o_inst_pm_state = INST_PM_STATE_DW_STATIC; - break; - - default: - FAPI_ERR("pmhist_state = 0x%x is impossible. Check code.", i_pmhist_state); - o_inst_pm_state = INST_PM_STATE_UNRESOLVED; - o_bGoodState = false; - bCodeBug = true; - break; - } - - if (bCodeBug) - { - FAPI_ERR("bCodeBug==true should never happen. Check code."); - const uint64_t & PMHIST_STATE = i_pmhist_state; - const fapi::Target & EX_TARGET = i_ex_target; - FAPI_SET_HWP_ERROR(rc, RC_IPMS_PMHIST_CODE_BUG); - return rc; - } - - return rc; -} // ex_determine_ipms_from_pmhist() - - -//------------------------------------------------------------------------------ -// @proc_name ex_determine_ipms_from_pirrx() -//------------------------------------------------------------------------------ -// @brief Determine the Instantaneous PM State (IPMS) strictly from the PMC PIRRx registers. -// -// @param[in] i_ex_target' the EX chiplet target -// @param[out] o_inst_pm_state' the returned instantaneous pm state -// @param[out] o_bGoodState' the returned IPMS state qualifier -// -// @return ReturnCode FAPI_RC_SUCCESS, platform error or FFDC specified error -// -//------------------------------------------------------------------------------ -fapi::ReturnCode ex_determine_ipms_from_pirrx( const fapi::Target &i_ex_target, - uint32_t i_pcbs_fsm, - uint32_t i_pmc_queue_state, - uint8_t &o_inst_pm_state, - bool &o_bGoodState ) -{ - fapi::ReturnCode rc; //fapi return code value - - o_bGoodState = true; - - if ( i_pmc_queue_state & PMC_QUEUE_PENDING_MASK ) - { - switch (i_pmc_queue_state & PMC_QUEUE_OP_TYPE_SCOPE_MASK) - { - case PMC_QUEUE_FS_ENTRY : - o_inst_pm_state = INST_PM_STATE_QUEUED_FS_ENTRY; - break; - - case PMC_QUEUE_DS_ENTRY : - o_inst_pm_state = INST_PM_STATE_QUEUED_DS_ENTRY; - break; - - case PMC_QUEUE_FS_EXIT : - o_inst_pm_state = INST_PM_STATE_QUEUED_FS_EXIT; - break; - - case PMC_QUEUE_DS_EXIT : - o_inst_pm_state = INST_PM_STATE_QUEUED_DS_EXIT; - break; - - case PMC_QUEUE_FW_ENTRY : - o_inst_pm_state = INST_PM_STATE_QUEUED_FW_ENTRY; - break; - - case PMC_QUEUE_DW_ENTRY : - o_inst_pm_state = INST_PM_STATE_QUEUED_DW_ENTRY; - break; - - case PMC_QUEUE_FW_EXIT : - o_inst_pm_state = INST_PM_STATE_QUEUED_FW_EXIT; - break; - - case PMC_QUEUE_DW_EXIT : - o_inst_pm_state = INST_PM_STATE_QUEUED_DW_EXIT; - break; - - default : - FAPI_ERR("There is an unsupported request on the PMC queue (pmc_queue_state=0x%x). Code bug.", - i_pmc_queue_state); - o_inst_pm_state = INST_PM_STATE_UNRESOLVED; - const uint64_t & PMC_QUEUE_STATE = i_pmc_queue_state; - const fapi::Target & EX_TARGET = i_ex_target; - FAPI_SET_HWP_ERROR(rc, RC_IPMS_PIRRX_UNSUPPORTED_IDLE_REQUEST); - return rc; - } - } - else - { - FAPI_INF("\tThere is no queueing request for this chiplet."); - o_inst_pm_state = INST_PM_STATE_UNRESOLVED; - FAPI_SET_HWP_ERROR(rc, RC_IPMS_PIRRX_NO_QUEUE_REQUEST); - return rc; - } - - return rc; -} // ex_determine_ipms_from_pirrx() - - -} // extern "C" diff --git a/src/usr/hwpf/hwp/utility_procedures/proc_cpu_special_wakeup.C b/src/usr/hwpf/hwp/utility_procedures/proc_cpu_special_wakeup.C deleted file mode 100644 index e911d0343..000000000 --- a/src/usr/hwpf/hwp/utility_procedures/proc_cpu_special_wakeup.C +++ /dev/null @@ -1,133 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/utility_procedures/proc_cpu_special_wakeup.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_cpu_special_wakeup.C,v 1.25 2012/10/09 11:04:29 pchatnah Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cpu_special_wakeup.C,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! OWNER NAME: Pradeep CN Email: pradeepcn@in.ibm.com -// *! -/// \file p8_pm_init.C -/// \brief Calls each PM unit firinit procedrues to configure the FIRs to -/// predefined types : -/// -/// -/// -/// -/// -// *! -// *! Procedure Prereq: -// *! o System clocks are running -// *! -//------------------------------------------------------------------------------ -/// -/// \todo Review -/// -/// -/// High-level procedure flow: -/// -/// \verbatim -/// - call p8_pm_pmc_firinit.C *chiptarget -/// - evaluate RC -/// -/// - call p8_pm_pba_firinit.C *chiptarget -/// - evaluate RC -/// -/// -/// \endverbatim -/// -// ---------------------------------------------------------------------- -// Includes -// ---------------------------------------------------------------------- - - -#include <fapi.H> -#include <p8_cpu_special_wakeup.H> - - - -// #ifdef FAPIECMD -extern "C" { - // #endif - - -using namespace fapi; - -// ---------------------------------------------------------------------- -// Constant definitions -// ---------------------------------------------------------------------- - - -// ---------------------------------------------------------------------- -// Global variables -// ---------------------------------------------------------------------- - - -// ---------------------------------------------------------------------- -// Function prototypes -// ---------------------------------------------------------------------- - - -// ---------------------------------------------------------------------- -// Function definitions -// ---------------------------------------------------------------------- -/// \ input ex_target -// ---------------------------------------------------------------------- -// p8_pm_init -// ---------------------------------------------------------------------- - -fapi::ReturnCode -proc_cpu_special_wakeup(const fapi::Target &i_ex_target, PROC_SPCWKUP_OPS i_operation , PROC_SPCWKUP_ENTITY i_entity ) -{ - - fapi::ReturnCode l_fapi_rc; - - - - // ****************************************************************** - // PMC_FIRS - // ****************************************************************** - - FAPI_DBG(""); - FAPI_EXEC_HWP(l_fapi_rc, p8_cpu_special_wakeup , i_ex_target, i_operation , i_entity ); - if (l_fapi_rc) - { - FAPI_ERR("ERROR: p8_cpu_special_wakeup detected failed result"); - return l_fapi_rc; - } - - - - - return l_fapi_rc; - -} - - - //#ifdef FAPIECMD -} //end extern C -//#endif diff --git a/src/usr/hwpf/hwp/utility_procedures/proc_mpipl_force_winkle_errors.xml b/src/usr/hwpf/hwp/utility_procedures/proc_mpipl_force_winkle_errors.xml deleted file mode 100644 index e7faf8924..000000000 --- a/src/usr/hwpf/hwp/utility_procedures/proc_mpipl_force_winkle_errors.xml +++ /dev/null @@ -1,248 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/utility_procedures/proc_mpipl_force_winkle_errors.xml $ --> -<!-- --> -<!-- OpenPOWER HostBoot Project --> -<!-- --> -<!-- Contributors Listed Below - COPYRIGHT 2014 --> -<!-- [+] International Business Machines Corp. --> -<!-- --> -<!-- --> -<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> -<!-- you may not use this file except in compliance with the License. --> -<!-- You may obtain a copy of the License at --> -<!-- --> -<!-- http://www.apache.org/licenses/LICENSE-2.0 --> -<!-- --> -<!-- Unless required by applicable law or agreed to in writing, software --> -<!-- distributed under the License is distributed on an "AS IS" BASIS, --> -<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> -<!-- implied. See the License for the specific language governing --> -<!-- permissions and limitations under the License. --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_mpipl_force_winkle_errors.xml,v 1.18 2014/06/26 14:43:51 cmolsen Exp $ --> -<!-- Error codes for proc_mpipl_force_winkle --> -<hwpErrors> - <!-- ******************************************************************** --> - <hwpError> - <rc>RC_PROC_MPIPL_FORCE_WINKLE_TARGET_TYPE_ERR</rc> - <description>Invalid target type passed to proc_mpipl_force_winkle HWP</description> - <ffdc>TARGET</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <hwpError> - <rc>RC_PROC_MPIPL_FORCE_WINKLE_CANNOT_UNLOCK_IPMS_STATE</rc> - <description>Chiplet is in a Winkle entry/exit state that cannot be unlocked</description> - <ffdc>IPMS_STATE</ffdc> - <callout> - <target>EX_TARGET</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <hwpError> - <rc>RC_EX_CHIPLET_AISS_WA_L2_PURGE_TIMEOUT</rc> - <description>EX chiplet timed out waiting for L2 purge to complete</description> - <ffdc>OHAMODEADDR</ffdc> - <ffdc>OHAMODEREG</ffdc> - <ffdc>OHAROADDR</ffdc> - <ffdc>OHAROREG</ffdc> - <ffdc>OHAAISSIOADDR</ffdc> - <ffdc>OHAAISSIOREG</ffdc> - <callout> - <target>EX_TARGET</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <gard> - <target>EX_TARGET</target> - </gard> - </hwpError> - <hwpError> - <rc>RC_EX_CHIPLET_AISS_WA_L3_PURGE_TIMEOUT</rc> - <description>EX chiplet timed out waiting for L3 purge to complete</description> - <ffdc>OHAMODEADDR</ffdc> - <ffdc>OHAMODEREG</ffdc> - <ffdc>OHAROADDR</ffdc> - <ffdc>OHAROREG</ffdc> - <ffdc>OHAAISSIOADDR</ffdc> - <ffdc>OHAAISSIOREG</ffdc> - <callout> - <target>EX_TARGET</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <gard> - <target>EX_TARGET</target> - </gard> - </hwpError> - <hwpError> - <rc>RC_EX_CHIPLET_AISS_WA_PB_PURGE_TIMEOUT</rc> - <description>EX chiplet timed out waiting for PB purge to complete</description> - <ffdc>OHAMODEADDR</ffdc> - <ffdc>OHAMODEREG</ffdc> - <ffdc>OHAROADDR</ffdc> - <ffdc>OHAROREG</ffdc> - <ffdc>OHAAISSIOADDR</ffdc> - <ffdc>OHAAISSIOREG</ffdc> - <callout> - <target>EX_TARGET</target> - <priority>HIGH</priority> - </callout> - <callout> - <procedure>CODE</procedure> - <priority>LOW</priority> - </callout> - <gard> - <target>EX_TARGET</target> - </gard> - </hwpError> - <hwpError> - <rc>RC_EX_CHIPLET_AISS_WA_INACCESSIBLE</rc> - <description>EX chiplet PCB Fence is up</description> - <ffdc>GP3ADDR</ffdc> - <ffdc>GP3REG</ffdc> - <ffdc>PMGP0ADDR</ffdc> - <ffdc>PMGP0REG</ffdc> - <ffdc>CHIP_TARGET</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - </hwpError> - <hwpError> - <rc>RC_IPMS_EXNUMBER_CODE_BUG</rc> - <description>Impossible value for ex_number</description> - <ffdc>EX_NUMBER</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <target>EX_TARGET</target> - <priority>LOW</priority> - </callout> - </hwpError> - <hwpError> - <rc>RC_IPMS_PMHIST_CODE_BUG</rc> - <description>Impossible value for pmhist_state</description> - <ffdc>PMHIST_STATE</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <target>EX_TARGET</target> - <priority>LOW</priority> - </callout> - </hwpError> - <hwpError> - <rc>RC_IPMS_PIRRX_NO_QUEUE_REQUEST</rc> - <description>There is not an idle request in the PMC queue for this chiplet</description> - </hwpError> - <hwpError> - <rc>RC_IPMS_PIRRX_CODE_BUG</rc> - <description>Impossible value for pmc_queue_state</description> - <ffdc>PCBS_FSM</ffdc> - <ffdc>PMC_QUEUE_STATE</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <target>EX_TARGET</target> - <priority>LOW</priority> - </callout> - </hwpError> - <hwpError> - <rc>RC_IPMS_UNSUPPORTED_SV_VALUE</rc> - <description>trans_sv has an unsupported value</description> - <ffdc>PCBS_FSM</ffdc> - <ffdc>PMHIST_STATE</ffdc> - <ffdc>PMC_QUEUE_STATE</ffdc> - <ffdc>TRANS_SV</ffdc> - <ffdc>TRANS_SV_ETR</ffdc> - <callout> - <target>EX_TARGET</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <hwpError> - <rc>RC_IPMS_SUSPICIOUS_PCBS_FSM</rc> - <description>Value of PCB-slave FSM suggest a problem in the core PM section</description> - <ffdc>PCBS_FSM</ffdc> - <ffdc>PMHIST_STATE</ffdc> - <ffdc>PMC_QUEUE_STATE</ffdc> - <callout> - <target>EX_TARGET</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <hwpError> - <rc>RC_IPMS_PIRRX_UNSUPPORTED_IDLE_REQUEST</rc> - <description>There is an unsupported idle request on the PMC queue.</description> - <ffdc>PMC_QUEUE_STATE</ffdc> - <callout> - <target>EX_TARGET</target> - <priority>HIGH</priority> - </callout> - </hwpError> - <hwpError> - <rc>RC_IPMS_STATE_NOT_FOUND_BUG</rc> - <description>An IPMS state was NOT found. This should never happen. Code bug.</description> - <ffdc>PORRR0_REG</ffdc> - <ffdc>PORRR1_REG</ffdc> - <ffdc>ETR_REG</ffdc> - <ffdc>PCBS_FSM_PREV</ffdc> - <ffdc>PCBS_FSM</ffdc> - <ffdc>PMHIST_STATE</ffdc> - <ffdc>PMC_QUEUE_STATE</ffdc> - <ffdc>IPMS_STATE</ffdc> - <ffdc>PIRR0_REG</ffdc> - <ffdc>PIRR1_REG</ffdc> - <ffdc>PIRR2_REG</ffdc> - <ffdc>PIRR3_REG</ffdc> - <callout> - <procedure>CODE</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <target>EX_TARGET</target> - <priority>LOW</priority> - </callout> - </hwpError> - <hwpError> - <rc>RC_IPMS_CONFLICTING_IDLE_STATES</rc> - <description>Conflicting values between PM state registers</description> - <ffdc>PORRR0_REG</ffdc> - <ffdc>PORRR1_REG</ffdc> - <ffdc>ETR_REG</ffdc> - <ffdc>PCBS_FSM_PREV</ffdc> - <ffdc>PCBS_FSM</ffdc> - <ffdc>PMHIST_STATE</ffdc> - <ffdc>PMC_QUEUE_STATE</ffdc> - <ffdc>IPMS_STATE</ffdc> - <ffdc>PIRR0_REG</ffdc> - <ffdc>PIRR1_REG</ffdc> - <ffdc>PIRR2_REG</ffdc> - <ffdc>PIRR3_REG</ffdc> - <callout> - <procedure>LVL_SUPPORT</procedure> - <priority>HIGH</priority> - </callout> - <callout> - <target>EX_TARGET</target> - <priority>LOW</priority> - </callout> - </hwpError> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/utility_procedures/utils.mk b/src/usr/hwpf/hwp/utility_procedures/utils.mk deleted file mode 100644 index 36f25b8d3..000000000 --- a/src/usr/hwpf/hwp/utility_procedures/utils.mk +++ /dev/null @@ -1,38 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/hwpf/hwp/utility_procedures/utils.mk $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2014 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/utility_procedures -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/utility_procedures -EXTRAINCDIR += ${ROOTPATH}/usr/hwpf/hwp/include -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar - -VPATH += ${HWPPATH}/utility_procedures - -OBJS += mss_unmask_errors.o -OBJS += mss_maint_cmds.o - -OBJS += p8_cpu_special_wakeup.o -OBJS += proc_cpu_special_wakeup.o -OBJS += p8_inst_pm_state.o diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index cf3e35a15..cb7cc6249 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -168,41 +168,6 @@ HWP_ERROR_XML_FILES += hwp/tp_dbg_data_accessors/proc_tp_dbg_data_errors.xml HWP_ERROR_XML_FILES += hwp/secure_boot/proc_sbe_scan_service_errors.xml HWP_ERROR_XML_FILES += hwp/secure_boot/proc_stop_sbe_scan_service_errors.xml -## these get generated into obj/genfiles/AttributeIds.H -HWP_ATTR_XML_FILES += hwp/memory_attributes.xml -HWP_ATTR_XML_FILES += hwp/L2_L3_attributes.xml -HWP_ATTR_XML_FILES += hwp/scratch_attributes.xml -HWP_ATTR_XML_FILES += hwp/system_attributes.xml -HWP_ATTR_XML_FILES += hwp/chip_attributes.xml -HWP_ATTR_XML_FILES += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), hwp/lab_dimm_spd_attributes.xml, hwp/dimm_spd_attributes.xml) -HWP_ATTR_XML_FILES += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), hwp/lab_dimm_attributes.xml, hwp/dimm_attributes.xml) -HWP_ATTR_XML_FILES += hwp/unit_attributes.xml -HWP_ATTR_XML_FILES += hwp/freq_attributes.xml -HWP_ATTR_XML_FILES += hwp/ei_bus_attributes.xml -HWP_ATTR_XML_FILES += hwp/chip_ec_attributes.xml -HWP_ATTR_XML_FILES += hwp/centaur_ec_attributes.xml -HWP_ATTR_XML_FILES += hwp/common_attributes.xml -HWP_ATTR_XML_FILES += hwp/sync_attributes.xml -HWP_ATTR_XML_FILES += hwp/dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml -HWP_ATTR_XML_FILES += hwp/dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml -HWP_ATTR_XML_FILES += hwp/activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml -HWP_ATTR_XML_FILES += hwp/runtime_attributes/pm_plat_attributes.xml -HWP_ATTR_XML_FILES += hwp/runtime_attributes/pm_hwp_attributes.xml -HWP_ATTR_XML_FILES += hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml -HWP_ATTR_XML_FILES += hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml -HWP_ATTR_XML_FILES += hwp/build_winkle_images/p8_slw_build/proc_pll_ring_attributes.xml -HWP_ATTR_XML_FILES += hwp/build_winkle_images/p8_slw_build/p8_xip_customize_attributes.xml -HWP_ATTR_XML_FILES += hwp/poreve_memory_attributes.xml -HWP_ATTR_XML_FILES += hwp/mcbist_attributes.xml -HWP_ATTR_XML_FILES += hwp/proc_winkle_scan_override_attributes.xml -HWP_ATTR_XML_FILES += hwp/erepair_thresholds.xml -HWP_ATTR_XML_FILES += hwp/dram_training/mem_pll_setup/memb_pll_ring_attributes.xml -HWP_ATTR_XML_FILES += hwp/proc_chip_ec_feature.xml -HWP_ATTR_XML_FILES += hwp/proc_abus_dmi_xbus_scominit_attributes.xml -HWP_ATTR_XML_FILES += hwp/runtime_attributes/memory_occ_attributes.xml -HWP_ATTR_XML_FILES += hwp/pstate_attributes.xml -HWP_ATTR_XML_FILES += hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data_attributes.xml - #------------------------------------------------------------------------------ # PLL Ring Data files #------------------------------------------------------------------------------ diff --git a/src/usr/initservice/istepdispatcher/istepdispatcher.C b/src/usr/initservice/istepdispatcher/istepdispatcher.C index c3f4aacaf..1233247e8 100644 --- a/src/usr/initservice/istepdispatcher/istepdispatcher.C +++ b/src/usr/initservice/istepdispatcher/istepdispatcher.C @@ -47,7 +47,6 @@ #include <initservice/taskargs.H> // TASK_ENTRY_MACRO #include <targeting/common/targetservice.H> #include <targeting/attrsync.H> -#include <establish_system_smp.H> //@TODO RTC:128106 port to fapi2 plat attribute service //#include <hwpf/plat/fapiPlatAttributeService.H> #include <mbox/mbox_queues.H> // HB_ISTEP_MSGQ diff --git a/src/usr/hwpf/hwp/tod_init/TodAssert.H b/src/usr/isteps/istep18/TodAssert.H index ac4706b24..a3609f5a1 100644 --- a/src/usr/hwpf/hwp/tod_init/TodAssert.H +++ b/src/usr/isteps/istep18/TodAssert.H @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodAssert.H $ */ +/* $Source: src/usr/isteps/istep18/TodAssert.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodControls.C b/src/usr/isteps/istep18/TodControls.C index d3cb2e751..20c87c13d 100755 --- a/src/usr/hwpf/hwp/tod_init/TodControls.C +++ b/src/usr/isteps/istep18/TodControls.C @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodControls.C $ */ +/* $Source: src/usr/isteps/istep18/TodControls.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodControls.H b/src/usr/isteps/istep18/TodControls.H index 922a58f0b..d072f5ff5 100755 --- a/src/usr/hwpf/hwp/tod_init/TodControls.H +++ b/src/usr/isteps/istep18/TodControls.H @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodControls.H $ */ +/* $Source: src/usr/isteps/istep18/TodControls.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodDrawer.C b/src/usr/isteps/istep18/TodDrawer.C index c78a75194..caaac1e5b 100755 --- a/src/usr/hwpf/hwp/tod_init/TodDrawer.C +++ b/src/usr/isteps/istep18/TodDrawer.C @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodDrawer.C $ */ +/* $Source: src/usr/isteps/istep18/TodDrawer.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodDrawer.H b/src/usr/isteps/istep18/TodDrawer.H index ef1c52863..80257d836 100755 --- a/src/usr/hwpf/hwp/tod_init/TodDrawer.H +++ b/src/usr/isteps/istep18/TodDrawer.H @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodDrawer.H $ */ +/* $Source: src/usr/isteps/istep18/TodDrawer.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodHwpIntf.C b/src/usr/isteps/istep18/TodHwpIntf.C index d2dde150f..b66f379ad 100755 --- a/src/usr/hwpf/hwp/tod_init/TodHwpIntf.C +++ b/src/usr/isteps/istep18/TodHwpIntf.C @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodHwpIntf.C $ */ +/* $Source: src/usr/isteps/istep18/TodHwpIntf.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodHwpIntf.H b/src/usr/isteps/istep18/TodHwpIntf.H index 7beba7cfe..94f15cb80 100755 --- a/src/usr/hwpf/hwp/tod_init/TodHwpIntf.H +++ b/src/usr/isteps/istep18/TodHwpIntf.H @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodHwpIntf.H $ */ +/* $Source: src/usr/isteps/istep18/TodHwpIntf.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodProc.C b/src/usr/isteps/istep18/TodProc.C index e3c31929d..656b19fb6 100755 --- a/src/usr/hwpf/hwp/tod_init/TodProc.C +++ b/src/usr/isteps/istep18/TodProc.C @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodProc.C $ */ +/* $Source: src/usr/isteps/istep18/TodProc.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodProc.H b/src/usr/isteps/istep18/TodProc.H index 5b93505ce..b020378f2 100755 --- a/src/usr/hwpf/hwp/tod_init/TodProc.H +++ b/src/usr/isteps/istep18/TodProc.H @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodProc.H $ */ +/* $Source: src/usr/isteps/istep18/TodProc.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodSvc.C b/src/usr/isteps/istep18/TodSvc.C index f76efe846..6b03e0355 100755 --- a/src/usr/hwpf/hwp/tod_init/TodSvc.C +++ b/src/usr/isteps/istep18/TodSvc.C @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodSvc.C $ */ +/* $Source: src/usr/isteps/istep18/TodSvc.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodSvc.H b/src/usr/isteps/istep18/TodSvc.H index 10e7c6216..11b052857 100755 --- a/src/usr/hwpf/hwp/tod_init/TodSvc.H +++ b/src/usr/isteps/istep18/TodSvc.H @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodSvc.H $ */ +/* $Source: src/usr/isteps/istep18/TodSvc.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodSvcUtil.C b/src/usr/isteps/istep18/TodSvcUtil.C index 962af46e1..ea00ca90e 100755 --- a/src/usr/hwpf/hwp/tod_init/TodSvcUtil.C +++ b/src/usr/isteps/istep18/TodSvcUtil.C @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodSvcUtil.C $ */ +/* $Source: src/usr/isteps/istep18/TodSvcUtil.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodSvcUtil.H b/src/usr/isteps/istep18/TodSvcUtil.H index b87a973a3..aca27ae52 100755 --- a/src/usr/hwpf/hwp/tod_init/TodSvcUtil.H +++ b/src/usr/isteps/istep18/TodSvcUtil.H @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodSvcUtil.H $ */ +/* $Source: src/usr/isteps/istep18/TodSvcUtil.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodTopologyManager.C b/src/usr/isteps/istep18/TodTopologyManager.C index 6febabc77..4a7d09435 100755 --- a/src/usr/hwpf/hwp/tod_init/TodTopologyManager.C +++ b/src/usr/isteps/istep18/TodTopologyManager.C @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodTopologyManager.C $ */ +/* $Source: src/usr/isteps/istep18/TodTopologyManager.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodTopologyManager.H b/src/usr/isteps/istep18/TodTopologyManager.H index a3b1844f7..447fe4432 100755 --- a/src/usr/hwpf/hwp/tod_init/TodTopologyManager.H +++ b/src/usr/isteps/istep18/TodTopologyManager.H @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodTopologyManager.H $ */ +/* $Source: src/usr/isteps/istep18/TodTopologyManager.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodTrace.H b/src/usr/isteps/istep18/TodTrace.H index c41e966bc..6bb2a9031 100644 --- a/src/usr/hwpf/hwp/tod_init/TodTrace.H +++ b/src/usr/isteps/istep18/TodTrace.H @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodTrace.H $ */ +/* $Source: src/usr/isteps/istep18/TodTrace.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/TodTypes.H b/src/usr/isteps/istep18/TodTypes.H index aacb21bdb..e94a1d2d7 100755 --- a/src/usr/hwpf/hwp/tod_init/TodTypes.H +++ b/src/usr/isteps/istep18/TodTypes.H @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/TodTypes.H $ */ +/* $Source: src/usr/isteps/istep18/TodTypes.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/makefile b/src/usr/isteps/istep18/makefile index fa8137de3..d411bdcec 100644 --- a/src/usr/hwpf/hwp/tod_init/makefile +++ b/src/usr/isteps/istep18/makefile @@ -1,11 +1,13 @@ # IBM_PROLOG_BEGIN_TAG # This is an automatically generated prolog. # -# $Source: src/usr/hwpf/hwp/tod_init/makefile $ +# $Source: src/usr/isteps/istep18/makefile $ # # OpenPOWER HostBoot Project # -# COPYRIGHT International Business Machines Corp. 2013,2014 +# Contributors Listed Below - COPYRIGHT 2016 +# [+] International Business Machines Corp. +# # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/src/usr/hwpf/hwp/tod_init/tod_init.C b/src/usr/isteps/istep18/tod_init.C index 8eeb14446..2fb12a7fe 100644 --- a/src/usr/hwpf/hwp/tod_init/tod_init.C +++ b/src/usr/isteps/istep18/tod_init.C @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/tod_init.C $ */ +/* $Source: src/usr/isteps/istep18/tod_init.C $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/hwpf/hwp/tod_init/tod_init.H b/src/usr/isteps/istep18/tod_init.H index 98b5bbea9..0ff41aba4 100644 --- a/src/usr/hwpf/hwp/tod_init/tod_init.H +++ b/src/usr/isteps/istep18/tod_init.H @@ -1,11 +1,13 @@ /* IBM_PROLOG_BEGIN_TAG */ /* This is an automatically generated prolog. */ /* */ -/* $Source: src/usr/hwpf/hwp/tod_init/tod_init.H $ */ +/* $Source: src/usr/isteps/istep18/tod_init.H $ */ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2016 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ diff --git a/src/usr/targeting/common/xmltohb/common.mk b/src/usr/targeting/common/xmltohb/common.mk index c0ff7a2fe..05bd45beb 100755 --- a/src/usr/targeting/common/xmltohb/common.mk +++ b/src/usr/targeting/common/xmltohb/common.mk @@ -54,33 +54,6 @@ XMLTOHB_SYSTEM_BINARIES += simics_NIMBUS_targeting.bin XMLTOHB_TARGETS += ${XMLTOHB_HEADER_TARGETS} XMLTOHB_TARGETS += ${XMLTOHB_SOURCE_TARGETS} -FAPI_ATTR_SOURCES += memory_attributes.xml -FAPI_ATTR_SOURCES += L2_L3_attributes.xml -FAPI_ATTR_SOURCES += scratch_attributes.xml -FAPI_ATTR_SOURCES += system_attributes.xml -FAPI_ATTR_SOURCES += chip_attributes.xml -FAPI_ATTR_SOURCES += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), lab_dimm_spd_attributes.xml, dimm_spd_attributes.xml) -FAPI_ATTR_SOURCES += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), lab_dimm_attributes.xml, dimm_attributes.xml) -FAPI_ATTR_SOURCES += unit_attributes.xml -FAPI_ATTR_SOURCES += ei_bus_attributes.xml -FAPI_ATTR_SOURCES += dram_initialization/proc_setup_bars/proc_setup_bars_l3_attributes.xml -FAPI_ATTR_SOURCES += dram_initialization/proc_setup_bars/proc_setup_bars_mmio_attributes.xml -FAPI_ATTR_SOURCES += activate_powerbus/proc_build_smp/proc_fab_smp_fabric_attributes.xml -FAPI_ATTR_SOURCES += nest_chiplets/proc_pcie_scominit/proc_pcie_scominit_attributes.xml -FAPI_ATTR_SOURCES += dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr_attributes.xml -FAPI_ATTR_SOURCES += common_attributes.xml -FAPI_ATTR_SOURCES += build_winkle_images/p8_slw_build/proc_pll_ring_attributes.xml -FAPI_ATTR_SOURCES += build_winkle_images/p8_slw_build/p8_xip_customize_attributes.xml -FAPI_ATTR_SOURCES += sync_attributes.xml -FAPI_ATTR_SOURCES += poreve_memory_attributes.xml -FAPI_ATTR_SOURCES += mcbist_attributes.xml -FAPI_ATTR_SOURCES += proc_winkle_scan_override_attributes.xml -FAPI_ATTR_SOURCES += erepair_thresholds.xml -FAPI_ATTR_SOURCES += dram_training/mem_pll_setup/memb_pll_ring_attributes.xml -FAPI_ATTR_SOURCES += runtime_attributes/memory_occ_attributes.xml -FAPI_ATTR_SOURCES += proc_abus_dmi_xbus_scominit_attributes.xml -FAPI_ATTR_SOURCES += pstate_attributes.xml - # Temp defaults XML sources used by updatetempsxml.pl script TEMP_DEFAULTS_XML += tempdefaults.xml HB_TEMP_DEFAULTS_XML += hb_temp_defaults.xml diff --git a/src/usr/util/runtime/utillidmgr_rt.C b/src/usr/util/runtime/utillidmgr_rt.C index 2c5c80a30..c3dcb1ec8 100644 --- a/src/usr/util/runtime/utillidmgr_rt.C +++ b/src/usr/util/runtime/utillidmgr_rt.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ +/* Contributors Listed Below - COPYRIGHT 2013,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -30,7 +30,6 @@ #include <errl/errlmanager.H> #include <vfs/vfs.H> #include <runtime/interface.h> -#include <hwpf/hwp/occ/occ_common.H> #include <initservice/initserviceif.H> UtilLidMgr::UtilLidMgr(uint32_t i_lidId) : |
