Changes related to model 31, attr changes for sim latencies

  Fix bug in ODT write config, using read config values
  Turn off WL RTT Swap
  Change VBU attribute file to include all sim cal steps

Change-Id: I63d2d47309bc41c761cabb5047e1fef8dcdea2fb
Original-Change-Id: I75aa17dcc46cecd120cdcd1847ea7e28b82c4dc8
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23418
Tested-by: Jenkins Server
Reviewed-by: Craig C. Hamilton <cchamilt@us.ibm.com>
Reviewed-by: Andre A. Marin <aamarin@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22761
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

2 files changed, 45 insertions, 4 deletions

diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
index b8a9917cf..979d9da49 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.C
@@ -7,7 +7,7 @@
 /*                                                                        */
 /* EKB Project                                                            */
 /*                                                                        */
-/* COPYRIGHT 2015                                                         */
+/* COPYRIGHT 2015,2016                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -161,6 +161,9 @@ fapi_try_exit:
 ///
 fapi2::ReturnCode toggle_zctl( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target )
 {
+// With model 31 (Drop X) this became unecessary. Not removing it as it's unclear what
+// the final algorithm(s) will be. BRS
+#if 0
     fapi2::buffer<uint64_t> l_data;
 
     auto l_ports = i_target.getChildren<TARGET_TYPE_MCA>();
@@ -187,6 +190,7 @@ fapi2::ReturnCode toggle_zctl( const fapi2::Target<TARGET_TYPE_MCBIST>& i_target
     FAPI_TRY( mss::scom_blastah(l_ports, MCA_DDRPHY_PC_IO_PVT_FET_CONTROL_P0, l_data) );
 
 fapi_try_exit:
+#endif
     return fapi2::current_err;
 }
 
@@ -829,7 +833,9 @@ fapi2::ReturnCode set_pc_config1(const fapi2::Target<TARGET_TYPE_MCA>& i_target)
     l_data.insertFromRight<MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET,
                            MCA_DDRPHY_PC_CONFIG1_P0_WRITE_LATENCY_OFFSET_LEN>(l_wlo);
 
-    l_data.setBit<MCA_DDRPHY_PC_CONFIG1_P0_DDR4_LATENCY_SW>();
+    // Model 31 changed the MCA_DDRPHY_PC_CONFIG1_P0_DDR4_LATENCY_SW bit to '0' for DDR4
+    // and '1' for 'extended 3ds.' We need to check an attribute here when we get to 3ds BRS
+    l_data.clearBit<MCA_DDRPHY_PC_CONFIG1_P0_DDR4_LATENCY_SW>();
 
     FAPI_DBG("phy pc_config1 0x%0llx", l_data);
     FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_PC_CONFIG1_P0, l_data) );
diff --git a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
index eff335982..3eef70a2c 100644
--- a/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
+++ b/src/import/chips/p9/procedures/hwp/memory/lib/phy/ddr_phy.H
@@ -7,7 +7,7 @@
 /*                                                                        */
 /* EKB Project                                                            */
 /*                                                                        */
-/* COPYRIGHT 2015                                                         */
+/* COPYRIGHT 2015,2016                                                    */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -576,6 +576,41 @@ fapi_try_exit:
 }
 
 
+///
+/// @brief Setup WC RTT Write Swap Enable Register
+/// @tparam T, the target type of the MCA/MBA
+/// @param[in] the target
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+template< fapi2::TargetType T >
+inline fapi2::ReturnCode reset_wc_rtt_wr_swap_enable( const fapi2::Target<T>& i_target );
+
+///
+/// @brief Setup WC RTT Write Swap Enable Register
+/// @param[in] the MCA target
+/// @return FAPI2_RC_SUCCESS iff setup was successful
+///
+template<>
+inline fapi2::ReturnCode reset_wc_rtt_wr_swap_enable( const fapi2::Target<fapi2::TARGET_TYPE_MCA>& i_target )
+{
+    fapi2::buffer<uint64_t> l_data;
+
+    FAPI_TRY( mss::getScom(i_target, MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0, l_data) );
+
+    // Per John Bialas 1/16: The enable RTT_SWAP bit is causing problems in sim.
+    l_data.clearBit<MCA_DDRPHY_WC_RTT_WL_SWAP_ENABLE_P0>();
+    l_data.setBit<MCA_DDRPHY_WC_RTT_WR_CTL_SWAP_ENABLE_P0>();
+
+    FAPI_DBG("wc_swap_enable 0x%llx", l_data);
+    FAPI_TRY( mss::putScom(i_target, MCA_DDRPHY_WC_RTT_WR_SWAP_ENABLE_P0, l_data) );
+
+fapi_try_exit:
+    return fapi2::current_err;
+}
+
+
+
+
 
 
 ///
@@ -630,7 +665,7 @@ inline fapi2::ReturnCode reset_odt_config( const fapi2::Target<fapi2::TARGET_TYP
     uint8_t l_odt_wr[MAX_DIMM_PER_PORT][MAX_RANK_PER_DIMM];
 
     FAPI_TRY( mss::eff_odt_rd(i_target, &(l_odt_rd[0][0])) );
-    FAPI_TRY( mss::eff_odt_wr(i_target, &(l_odt_rd[0][0])) );
+    FAPI_TRY( mss::eff_odt_wr(i_target, &(l_odt_wr[0][0])) );
 
     // Nimbus PHY is more or less hard-wired for 2 DIMM/port 4R/DIMM
     // So there's not much point in looping over DIMM or ranks.