blackbird-hostboot/src/usr/lpc, branch 07-25-2019

Automatically include config.h

2019-12-06T16:28:47+00:00

Rather than having to remember to include config.h anywhere we reference a CONFIG variable (and usually forgetting), this adds it to the default compiler flags so that it gets included in every source file we build. Change-Id: I53622ab4d46c55d942e98cae6ec03049fd5b3d08 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87475 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Zachary Clark Reviewed-by: Roland Veloz Reviewed-by: Christian R Geddes Reviewed-by: Nicholas E Bofferding

Remove Redundant LPC Bus Check

2019-04-16T19:45:44+00:00

Current implementation of lpcWrite contains a check for errors on LPC bus before the attempt to writeLPC, and writeLPC is not attempted if an error is found on the bus. However, the error check performs bus reset, and the same check is performed in writeLPC with the difference that the lpcWrite is still attempted after the bus reset, and only if the write fails is the error returned. This commit removes the first check for LPC errors to give lpcWrite a chance to run after the LPC bus reset due to errors. Change-Id: I6375e6575f771e33bd3b866534eb3cd8656d38d8 CQ: SW455075 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75931 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Nicholas E. Bofferding Reviewed-by: Michael Baiocchi Reviewed-by: Daniel M. Crowell

HBBL LPC Error Checking

2019-02-08T21:42:06+00:00

- To avoid IPL delays, the LPC status register should be checked prior to loading the entire PNOR image (done via LPC). If an error condition occurs, HBBL should fail out. Change-Id: I5d716213f468e28191db794bf3e5480af547b26e CQ: SW446254 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68442 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes Reviewed-by: Nicholas E. Bofferding Reviewed-by: Daniel M. Crowell

Add missing mutex in LPC error path

2018-11-14T03:51:11+00:00

There is a pre-check to look for errors before every LPC read or write operation. This check was running outside of the mutex, which meant that if an operation caused an error and then another thread attempted a separate LPC op, the second thread would end up reporting the error from the first operation, This would typically just result in a double log, but there are cases where an error is expected (the SIO problem for the hiomap protocol) and is deleted by the caller. Because of the second thread seeing the error, the error condition ends up being a visible log. The change here is to move the pre-check inside the mutex so that only 1 thread can ever be checking the LPC status at a time. Change-Id: I9ce0ce48252b7d2b271aa5dd6e0a819dfb728a25 CQ: SW450825 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68609 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Corey V. Swenson Reviewed-by: Christian R. Geddes Reviewed-by: William G. Hoffa Tested-by: Jenkins OP HW Reviewed-by: Nicholas E. Bofferding

sio: Add test for availability

2018-10-15T21:11:08+00:00

Some components can continue to operate in the face of the SuperIO controller being unavailable on the LPC bus (specifically, the UART and boot flag processing). Other components require it present (AST-based SFC implementations and the AST mailbox). Components in the latter category can just fail with an errl when they attempt to access the controller, but for those in the former category we add an isAvailable() function in the SIO namespace to sidestep dealing with errors. Specifically, isAvailable() tests for the expected error when the SuperIO controller is disabled, and returns an errlHndl_t if any other error occurs. This way true LPC errors are propagated to the caller to commit as desired. For the moment *all* errors produced by the SIO::isAvailable() LPC bus access will result in the SIO code assuming the device is absent. We should be more precise about this, but the hardware behaviour seen under hostboot currently prevents us from being more specific. This problem is highlighted by a FIXME block in the implementation of SIO::isAvailable(). Change-Id: Id30a09b48586d2054e0cdae625ee23df68ac2aa3 Signed-off-by: Andrew Jeffery Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67460 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Corey V. Swenson Reviewed-by: Daniel M. Crowell

Revert "sio: Add test for availability - LPC error tweak"

2018-10-15T21:11:03+00:00

This reverts commit 627379aeaa27e30d66ebb0aecf218708d465162c, which incorrectly attempted to account for LPC errors during testing for SIO absence. The broken patch interprets the OPBM status as LPCHC status and expects an LPCHC SYNC Abnormal error, however as it's the OPBM status that indicates the error we never hit the LPCHC error path to populate the errl with the error RC expected by the SIO driver. Change-Id: Ib993d4a2b9b4e5018d9273a1c82f8b5c21ec9a25 Signed-off-by: Andrew Jeffery Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67459 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

sio: Add test for availability - LPC error tweak

2018-10-11T22:53:08+00:00

Some components can continue to operate in the face of the SuperIO controller being unavailable on the LPC bus (specifically, the UART and boot flag processing). Other components require it present (AST-based SFC implementations and the AST mailbox). Components in the latter category can just fail with an errl when they attempt to access the controller, but for those in the former category we add an isAvailable() function in the SIO namespace to sidestep dealing with errors. Specifically, isAvailable() tests for the expected error when the SuperIO controller is disabled, and returns an errlHndl_t if any other error occurs. This way true LPC errors are propagated to the caller to commit as desired. Change-Id: Ib94ceabfd4f4e9c63c114cfe3db3c954dbb6d6e5 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67315 Tested-by: Jenkins Server Reviewed-by: ANDREW R. JEFFERY Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Corey V. Swenson Reviewed-by: William G. Hoffa

Add support for LPC error detection and recovery

2017-09-18T19:50:35+00:00

Change-Id: Iea9bd4425aeb798acd85484402c627fb623cae94 Also-By: Matt Ploetz RTC: 133649 RTC: 134582 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45397 Reviewed-by: Christian R. Geddes Reviewed-by: Prachi Gupta Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Fix off-by-one error in LPC driver for pnor mbox windows

2017-08-17T15:32:59+00:00

Found a bug where we fail if we use a window all the way up to the edge of the allocated window. Change-Id: I1e663089a3ba6b2e4d9a7dbc67ae98db0fd2524e CQ: SW398471 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44703 Reviewed-by: Prachi Gupta Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell

Bringup memory remapping Fix LPC and XSCOM BAR asserts

2017-07-26T04:10:10+00:00

The LPC and XSCOM BAR values are checked and an assert coded in the failure leg. The condition for these asserts is being fixed. Also the LPC BAR check is being fixed to subtract out the start offset. Change-Id: I09f9989a51f6581c5b12a4a5057a4fcfa3412566 RTC:149250 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43286 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Matt Derksen Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell