blackbird-hostboot/src/usr/isteps/pm/runtime, branch 07-25-2019

Make RT_TARG id generation code common between IPL time and runtime

2020-01-22T15:45:00+00:00

For axone we are writing the OMI mmio bars into hdat so the hypervisor know how to talk to the devices. IPL code needs to be able to lookup the hbrt-style ids so we can use them to make hdat entries that the hypervisor will be able to associate targets with. This commit also move rt_targeting.H to the correct include directory and updates everywhere that it is included. Change-Id: I31deaa1a9c5a7523622a8b3b12ad459e2b2feed3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80419 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M Crowell

Unit test for the firmware request sendAttributes

2019-07-02T18:44:57+00:00

Added a unit test for the firmware request sendAttributes. The unit test exercises and verifies the correctness of the sendAttribute firmware request method. Did some massive cleanup of the testing framework/harness. It was becoming unwieldy and cumbersome to update. I create methods for the individual firmware request test instead of having the test reside in over bloated method. Added a section, in the README file, on how to test new interfaces that are added for firmware request lineup. Change-Id: I0ff7c0e48211b12d81be1f179ad3ee08e4d254af RTC: 208343 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78934 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Glenn Miles Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell

SMF: Logic For Creating Non-Secure HOMER Memory Space

2019-04-12T17:12:11+00:00

For SMF to be enabled, HOMER requires a small amount of non-SMF (unsecure) memory where the "jump to Ultravisor" instruction can be put (to transition to UV mode). This commit sets up a region of non-secure memory space for that purpose. Change-Id: Ib91ec69f49a4e174e65f3c2aad337a68eaa0803b RTC: 205986 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70699 Reviewed-by: Prem Shanker Jha Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Nicholas E. Bofferding Reviewed-by: Daniel M. Crowell

Disable NVDIMM Trigger Before Draminit and Deassert DDR_RESETn During MPIPL

2019-02-12T16:50:42+00:00

- Per the JEDEC spec, DDR_RESETn is masked from the DRAM when the NVDIMM is armed. This could cause the training to fail if the trigger is not disabled before training. Two scenarios where this can happen are warm reboot and cold boot before the backup power module can deplete the charge - Deassert DDR_RESETn in MPIPL before triggering the restore. - Fix the config flag to enable NVDIMM code Change-Id: I9d25c2f653fc54d379f0dbab49218f5b59a407a0 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70035 Reviewed-by: Matt Derksen Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Inform PHYP of NVDIMM protection by OCC

2019-01-24T19:12:08+00:00

The OCC is responsible for detecting the EPOW signal and triggering the save operation on the NVDIMM. Therefore, if the OCC is not running we are unprotected from a poweroff event. PHYP needs to inform the LPARs using the NV (non-volatile) memory of this state so they can behave accordingly. HBRT is responsible for telling PHYP when we get into this state. There are two ways we can detect this state: a) HBRT explicitly puts the PM complex into reset b) PRD detects a specific FIR bit The message should include this data: - what state we are in (protected or unprotected) - which processor is affected Work for this story will include: - Definition of the new message - Creating a utility function to send the message - Calling utility function to send 'unprotected' message inside of all pm reset paths at runtime Change-Id: Ib015d001d47883a247faedabedb0705ba0f1b215 RTC:201181 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68870 Reviewed-by: Christian R. Geddes Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: TSUNG K. YEUNG Reviewed-by: Roland Veloz Reviewed-by: Daniel M. Crowell

Move NVDIMM operations under NVDIMM modules

2019-01-21T14:50:48+00:00

Makes it easier to find and include NVDIMM operations. Also makes it easier to exclude from non-nvdimm supported systems. Change-Id: I870c2246e1bb9201e6e8032f1868e6e4e6a2b91a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70489 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Roland Veloz Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell

Move NVDIMM Erase and Arm to Runtime

2019-01-09T18:41:27+00:00

-Move erase and arm to after OCC has started -Address several TODOs in I2d68123ceb0b8e7a33b54f9acad0968670a67ea9 -Combine arm and erase into an atomic operation with ATOMIC_SAVE_AND_ERASE Change-Id: Iad06f6fe7128df3defc4ded57b0151f9c4b9d15e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68197 Reviewed-by: Daniel M. Crowell Tested-by: Daniel M. Crowell

Add consistent enter-exit traces for all runtime interfaces

2018-10-02T13:57:58+00:00

Created a new 'HBRT' trace buffer that is exclusively used to bound the external calls into our runtime image. Modified the return code values to be the reasoncode of the error log we commit instead of a generic '-1' value that is not very helpful. Change-Id: Id41288ea1903bf6d11e967fcb10a8184153943c8 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64871 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Brian J. Stegmiller Reviewed-by: Matt Derksen Reviewed-by: William G. Hoffa

Forcibly clear all previous wakeups when the PM Complex starts

2018-09-19T14:50:03+00:00

The power management logic was designed with the assumption that the external callers would manage the state machine such that the order of operations is always: load->start->reset->load->start->reset->etc. However, we have discovered edge cases where a reset can happen before the first load or after a previous reset. In either case we will end up with our wakeup counter being off by one and thus never releasing wakeup. The solution is to add logic to the start path that will explicitly clear the counter out completely, regardless of its current value. This will ensure that wakeup is released once the complex is alive. Change-Id: Ifb436335090ff910b9ee0f083d9a550b81833287 CQ: SW442639 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65518 Reviewed-by: Matt Derksen Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: William G. Hoffa

Centaur Channel Checkstop (runtime)

2018-06-19T13:57:22+00:00

Add back Simics tests that were removed. Change-Id: I3b4e1555784931083922ad9ff08bc5d78b594afa RTC:189294 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60759 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell