blackbird-hostboot/src/usr/hwas/common, branch 07-25-2019

Enhancements to default console output

2020-01-07T19:22:21+00:00

Added the following pieces of extra information to the default console output: -- Attribute Overrides -- 3.49165|**Found 24 attribute overrides in Tank FAPI(1) 3.49169|- PEC:n0:p0:c0 3.49171| ATTR 0EB604DF [1] = 00 3.49174| ATTR 085F1C7E [1] = 00 3.49177| ATTR 048A8902 [1] = 01 3.49180| ATTR 04D8DF8D [2] = 0000 3.49182|- PEC:n0:p0:c1 3.49185| ATTR 0EB604DF [1] = 00 3.49188| ATTR 085F1C7E [1] = 00 3.49191| ATTR 048A8902 [1] = 03 -- New part detection -- 4.97449|Detected new part : 00030002 (Physical:/Sys0/Node0/DIMM2) -- Applying GARD records -- 8.78767|HWAS|Applying GARD record for HUID=0x000E0000 (Physical:/Sys0/Node0/Pr oc0/XBUS0) due to 0x90000135 8.78912|HWAS|Deconfig HUID 0x000E0000, Physical:/Sys0/Node0/Proc0/XBUS0 Change-Id: Ic2ae04515453dbb49e359abff952c87c83e23b72 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/88388 Tested-by: Jenkins Server Reviewed-by: Nicholas E Bofferding Reviewed-by: Roland Veloz Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: William G Hoffa

Automatically include config.h

2019-12-06T16:28:47+00:00

Rather than having to remember to include config.h anywhere we reference a CONFIG variable (and usually forgetting), this adds it to the default compiler flags so that it gets included in every source file we build. Change-Id: I53622ab4d46c55d942e98cae6ec03049fd5b3d08 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/87475 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Zachary Clark Reviewed-by: Roland Veloz Reviewed-by: Christian R Geddes Reviewed-by: Nicholas E Bofferding

Allow dynmic i2c device addresses and set up PMIC targets to do this

2019-11-01T20:41:41+00:00

Depending on which vendor made a given OCMB the i2c device address of the PMIC targets on the OCMB will be different. To account for this we have added a new DYNAMIC_DEVICE_ADDRESS attribute. This attribute is filled out on the PMIC target by looking at the SPD on parent OCMB chip. This means that we must do presence detection on the OCMB prior to the the PMIC targets. While doing i2c operations if a given target has the DYNAMIC_DEVICE_ADDRESS we will use that over the devAddr in the any complex i2c attribute for that target. Change-Id: I22a185a65c064a1514751dd5828547c57af98df1 RTC: 209714 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/85394 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M Crowell Reviewed-by: Roland Veloz Reviewed-by: William G Hoffa

Fix NVDIMM update error log comments

2019-08-20T17:35:45+00:00

First line of error log comment must include /*@ or error log will not be documented. Also fixed in other HB files. Change-Id: Ifa5eba6d6abd7f8565a4cc8d62a25a2b833725f2 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82497 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Nicholas E Bofferding Reviewed-by: Matt Derksen Reviewed-by: Daniel M Crowell

Document Axone NPU configuration

2019-05-29T15:47:06+00:00

- Updated simics_AXONE.system.xml with the valid target configuration that we should be using for NPUs in Axone. - Updated target xml files as well - Corrected 1 PG rule that no longer applies - Also modified the OBUS_BRICK layout in simics_AXONE as well Change-Id: I05c68be027cd4da39afabee04fefbb266b87c5fb RTC: 208518 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76510 Reviewed-by: Christian R. Geddes Reviewed-by: Glenn Miles Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Force Axone simics to read all VPD from HW with config flags

2019-05-14T19:54:03+00:00

This commit will set the config flags to always read from HW rather than the old VPD cache in PNOR. Until this point in Axone we were still using an old copy of MVPD that we write into PNOR during the startup simics scripts. From this commit onward we will use the actual VPD simics provides. To handle this, some updates we needed to the PG rules for Axone. Change-Id: Ie06cefe1aec37edfc4c379ee1173bc51fc6bbe1f Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76519 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Matt Derksen Reviewed-by: Daniel M. Crowell

Add Axone to RISK_LEVEL logic

2019-05-08T21:45:47+00:00

Axone reuses the RISK_LEVEL settings for Nimbus DD2.3 so changes are made to reflect that. This is primarily a documentation exercise but there is logic now to normalize the RISK_LEVEl up to 4,5 versus 0,1 just to stay sane and reduce the test matrix. Change-Id: I5410d1bf7b12fc7f771e2c9826fcd086b2520091 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76757 Reviewed-by: Matt Derksen Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Matthew Raybuck Reviewed-by: Jayashankar Padath Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Gemini vs Explorer Presence Detection via SPD

2019-05-01T14:05:04+00:00

Since the OCMB chip is held in reset until after presence detection the IDEC register cannot be read to differentiate between Gemini and Explorer chip types. To work around this issue, during the early part of IPL when presence detection is occurring the OCMB IDEC function will instead read the SPD and populate the necessary attributes with what is found there. That will be used to determine the difference between Gemini and Explorer until later when the OCMB IDEC register can be read from. At that point the IDEC read will be executed again and the data read from the OCMB IDEC register will be used to cross-check the data read from the SPD. Any discrepancies will be handled with predictive error logs. Change-Id: Ica664b06ff3488f48253d3ef02eff2d49c5d240d RTC: 208696 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76108 Reviewed-by: Christian R. Geddes Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Collect IDEC for Explorer chip

2019-04-30T14:37:07+00:00

The OCMB Explorer Chip doesn't read for IDEC but instead assumes hardcoded values. Since the Explorer chip is held in reset until iStep 10.4, this commit will prevent IDEC reads during discoverTargets and instead perform the read when exp_check_for_ready() is successful. Change-Id: I4ef5a01badb195acca0c2187ef76ea55f58eafe4 RTC:201996 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75881 Reviewed-by: Matt Derksen Reviewed-by: Christian R. Geddes Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell Tested-by: Daniel M. Crowell

Add new PMIC target for Axone

2019-04-18T21:34:18+00:00

PMIC is a voltage regulator for the DDIMM. It supplies power to the OCMB and DIMM targets. Change-Id: I10c1b03169f53b070f521ec9cd60cdbd15c4a268 RTC:206184 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75136 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Glenn Miles Reviewed-by: Christian R. Geddes Reviewed-by: Daniel M. Crowell