blackbird-hostboot/src/usr/hdat, branch 07-25-2019

Update MPIPL Supported Bit

2020-02-06T14:48:13+00:00

- MPIPL Supported bit in HDAT System attribute moved to bit-5 from bit-4 Change-Id: Id49a02e867dcd163fba89bfa243b57654c97a4e3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/90821 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: VASANT HEGDE Reviewed-by: Daniel M Crowell

Handle automatic interleaving between OMI sub-channels

2020-01-10T16:22:27+00:00

The memory channel is defined as a single MCC, and all of the memory on that channel is part of a single address space. That means that both OCMBs on the same MCC share an address space. While this isn't the same mechanism as true interleaving, it looks the same to the code consuming HDAT, so we need to set the sharing flags appropriately. Change-Id: Ic270582ced92614cf21ff7be0ef6f97c93ab2514 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/89340 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Jayashankar Padath Reviewed-by: Christian R Geddes Reviewed-by: Daniel M Crowell

Filter out i2c slaves that are not associated with a given master

2019-12-06T21:41:07+00:00

During axone bringup a workaround was put in place to avoid some of the logic that was used in witherspoon systems. It turns out for axone we want the same behavior. This commit reverts the behavior of the hdatGetI2cDeviceInfo to what is was previous to the workaround. Change-Id: I64ab0a28fda22d1709c5658ea36ce69d88c1deba RTC: 213230 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/88178 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Jayashankar Padath Reviewed-by: Daniel M Crowell Reviewed-by: Nicholas E Bofferding

HDAT: Add SMF Memory Region

2019-09-10T15:24:42+00:00

The SMF memory region was not being populated in HDAT, causing skiboot to not find any secure memory. This commit adds changes to include the SMF memory range into HDAT. Change-Id: I67cfc2787d90604e3da0f61844776c8704ea2640 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82180 Reviewed-by: Nicholas E Bofferding Reviewed-by: Jayashankar Padath Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Reviewed-by: Daniel M Crowell

Update SYS's ATTR_XSCOM_BASE_ADDRESS in SMF Paths

2019-09-03T18:41:22+00:00

The correct value of ATTR_XSCOM_BASE_ADDRESS was not being propagated to HDAT when SMF is enabled. The problem is that the system target has a copy of said attribute that needs to be updated with the SMF bit (bit 15) to reflect the fact that XSCOM BAR is in SMF memory. The attribute under the system target was not being updated accordingly (only those attributes under proc targets were). This commit adds a fix to update ATTR_XSCOM_BASE_ADDRESS under the system target in SMF mode. Change-Id: Icac5bb7023ac0ecc521a961681420bfc21a46eac Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/83057 Reviewed-by: Nicholas E Bofferding Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: Michael Baiocchi Reviewed-by: Christian R Geddes

Use REL_POS of OMI and not OCMB for calculating hdat DIMM ID's

2019-08-14T14:35:01+00:00

There is a bug in the code where we are attempting to lookup the REL_POS of an ocmb target while trying to generate the id hdat will use to uniquely identify a given dimm target. OCMB targets do not have the REL_POS attribute and if they did it would always be 0, or it would match the associated DIMM's REL_POS (for single dimm ocmbs at least). Instead we will use the OMI's REL_POS which should work because OMI's are 1-1 with OCMB targets. Change-Id: Ib22307c7f4c2d97a5368fd507fe7b4965135c76e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/82120 Tested-by: Jenkins Server Reviewed-by: Jayashankar Padath Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: William G Hoffa Reviewed-by: Daniel M Crowell

HDAT: Support for Swift/Axone memory sub system

2019-08-08T14:35:23+00:00

Added support to scan the dimms using OCMB chip target path and fetched the memory related data using the new targeting model. Updated PVPD and MVPD keywords for axone chip. Change-Id: I2c7288dd57d60243569b4648a309dfcb11baf9d8 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80591 Reviewed-by: Sampa Misra Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Daniel M Crowell

Correctly form LX record/keyword for OpenPOWER

2019-07-16T15:15:03+00:00

Current OpenPOWER code doesn't properly form the LX VPD record and instead tacks it into the VINI record. This causes PowerVM to fail to boot. Correct this by fully forming a LXR0 record, populate the LX keyword from the value in the system MRW, and then append the fully formed LXR0 record to the HDAT VPD. Change-Id: I2128e4ddef8e3c5c1373fd4c6b5bf6de50901ef1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78489 Tested-by: Jenkins Server Reviewed-by: Daniel M Crowell

Add Axone to RISK_LEVEL logic

2019-05-08T21:45:47+00:00

Axone reuses the RISK_LEVEL settings for Nimbus DD2.3 so changes are made to reflect that. This is primarily a documentation exercise but there is logic now to normalize the RISK_LEVEl up to 4,5 versus 0,1 just to stay sane and reduce the test matrix. Change-Id: I5410d1bf7b12fc7f771e2c9826fcd086b2520091 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76757 Reviewed-by: Matt Derksen Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Matthew Raybuck Reviewed-by: Jayashankar Padath Tested-by: Jenkins OP HW Reviewed-by: Daniel M. Crowell

Handle DD2.3 mode properly when setting elevated risk in HDAT

2019-05-02T18:10:21+00:00

When running in native (DD2.3) mode, the value of ATTR_RISK_LEVEL is always greater than zero. The code needs to handle the higher values when setting the elevated risk level bit in the HDAT structures that go up to the OS. Change-Id: Ib8d9c4f885ad84cf2b0344e38d6e3c74b7c21ef8 CQ: SW464159 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76728 Tested-by: Jenkins Server Reviewed-by: Matt Derksen Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Jayashankar Padath Tested-by: Jenkins OP HW Reviewed-by: Nicholas E. Bofferding