blackbird-hostboot/src/HBconfig, branch 07-25-2019

Setup CONFIG_AXONE env variable correctly

2019-04-06T23:14:32+00:00

In previous attempt to use CONFIG_AXONE env variable as a flag to decided whether or not to compile certain AXONE only features we forgot to add in the config variable to HBconfig. Worse is we were using the wrong env var in the make files as a flag. As a result, without this change we are not running any Axone HWPs in axone simics. Change-Id: I82dd7f86c5ad390a23eab2d2123d1d10ca9edea3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/75568 Reviewed-by: Matthew Raybuck Reviewed-by: Matt Derksen Tested-by: Jenkins Server Reviewed-by: Daniel M. Crowell Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Christian R. Geddes

Add EEPROM caching device op

2019-02-13T20:41:48+00:00

This commit introduces a new EEPROM_CACHE deviceOp and registers the OCMB_CHIP, PROC, and DIMM targets to it. This is part of the larger effort to transition for a "VPD" cache to an "EEPROM" cache in pnor. The deviceOp is currently called in hwasPlat's platPresenceDetect if the target in question has a ATTR_EEPROM_VPD_PRIMARY_INFO associated with it. The layout for the new EECACHE section in pnor is defined in eepromCache_const.H. Essentially it is a header that contains an array of record headers that tell where in the EECACHE pnor section a given cached EEPROM can be found. All EEPROM targets will be allocated space in the EECACHE section but only present targets will have their cache filled in. RTC: 196805 Change-Id: I49c341c9784be04ddf0259bd444f06c9baf8c6f1 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70520 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Matt Derksen Reviewed-by: Roland Veloz Reviewed-by: Daniel M. Crowell

Add temporary Axone simics workarounds to progress IPL

2019-02-05T22:55:41+00:00

Currently there is no VRM hooked up to the other side of the AVSbus in simics. The simics team is working on this but for now we need to skip the istep that calls setup evid to set voltages. This can be removed when Simics gets this working. Also for now we are will skip starting checkstop handling early on in the IPL because the OCC model is not finished. This also can be changed when the model starts working. Change-Id: Ia0df49fedae97acceefe07e3f3c903bbe6aac83d Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/71097 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Matt Derksen Reviewed-by: Corey V. Swenson Reviewed-by: Daniel M. Crowell

wrap test: Use MNFG_FLAGS instead of compile time flag

2018-05-07T15:51:15+00:00

Change-Id: I347075dd2424ee8b96805456b3d7d9962f428b64 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58347 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: William G. Hoffa Reviewed-by: Roland Veloz Reviewed-by: Daniel M. Crowell

wrap_test: OBUS deconfiguration

2018-04-27T18:54:07+00:00

Due to fabric limitations, we can only have 2 OBUSes enabled at a time. This commit deconfigures the OBUSes that do not belong the set of links to enable in this boot based on attributes. Change-Id: I15f5e9f3ea186367b9c4d55f4dc2e9b32b251f6d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57836 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Tested-by: Jenkins OP HW Reviewed-by: Elizabeth K. Liner Reviewed-by: Roland Veloz Reviewed-by: Martin Gloff Reviewed-by: William G. Hoffa

Default to full cache usage during early Hostboot

2018-02-09T21:27:29+00:00

Early hardware had to support a partial cache config which is inefficient. Placing this code behind a config option, defaulting to full cache usage Change-Id: I521a1d9644d754a2657993603e3e2b2aab90112a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53606 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Reviewed-by: Prachi Gupta Tested-by: Jenkins OP HW Reviewed-by: Dean Sanner

Resolve istep mode issue with istep 18 on FSP systems

2017-08-03T21:48:55+00:00

Resolves the situation on FSP in istep mode where the high watermark is unable to advance beyond step 18 due to an empty non-null entry the steps array. Change-Id: If1a20aac114625c4b166b92594ad4dd83af82e02 CQ:SW397912 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44163 Reviewed-by: Stephen M. Cprek Tested-by: Jenkins Server Reviewed-by: Michael Baiocchi Tested-by: Jenkins OP Build CI Tested-by: Jenkins OP HW Tested-by: FSP CI Jenkins Reviewed-by: William G. Hoffa

Relocate ROM code after HBBL has been verified

2017-03-10T18:44:11+00:00

Create Bootloader to hostboot data manager to control how the shared data is accessed and modified. Change-Id: I54cb543ed289810ab6afb07d333313f5662bce0e RTC: 166848 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35617 Reviewed-by: Michael Baiocchi Reviewed-by: Daniel M. Crowell Tested-by: Daniel M. Crowell

HDAT changes for Witherspoon

2016-11-15T02:29:58+00:00

Change-Id: I942362604938fe4f7511e21da9246236a939c176 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30905 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Daniel M. Crowell

Add uartif include to ast2400

2016-11-06T03:47:56+00:00

Change-Id: Ica065fb2dd4402c0fa71466055bcccb573d48101 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31877 Tested-by: Jenkins Server Tested-by: Jenkins OP Build CI Tested-by: FSP CI Jenkins Reviewed-by: Elizabeth K. Liner Reviewed-by: William G. Hoffa Reviewed-by: Daniel M. Crowell