meklort <PROJECT> NVM Register Definitions 1.0 NVM Device Registers NVM Device Registers 0xC0007000 register false COMMAND 0x0 32 true Reset When set, the entire NVM state machine is reset. This bit is self- clearing. 1 1 read-write Done Sequence completion bit that is asserted when the command requested by assertion of the doit bit has completed. 3 1 read-write Doit Command from software to start the defined command. The done bit must be clear before setting this bit. This bit is self clearing and will remain set while the command is active. 4 1 read-write Wr The write/not read command bit. Set to execute write or erase. 5 1 read-write Erase The erase command bit. Set high to execute an erase. This bit is ignored if the wr is clear. 6 1 read-write First This bit is passed to the SEE_FSM or SPI_FSM if the pass_mode bit is set 7 1 read-write Last When this bit is set, the next command sequence is interpreted as the last one of a burst and any cleanup work is done. 8 1 read-write Write Enable Command The write enable command bit. Set '1' will make the flash interface state machine generate a write enable command cycle to the flash device to set the write enable bit in the device status register. This command is used for devices with a write protection function. 16 1 read-write Write Disable Command The write disable command bit. Set '1' will make the flash interface state machine generate a write disable command cycle to the flash device to clear the write enable bit in the device status register. This command is used for devices with a write protection function. 17 1 read-write WRITE 32bits of write data are used when write commands are executed. 0x8 32 true SCLK Output Value When in bit-bang mode, this bit controls the SCLK output value. 2 1 read-write CSb Output Value When in bit-bang mode, this bit controls the CSb output value. 3 1 read-write SI Output Value When in bit-bang mode, this bit controls the SI output value. 4 1 read-write SO Output Value When in bit-bang mode, this bit controls the SO output value. 5 1 read-write ADDR The 24 bit address for a read or write operation (must be 4 byte aligned). 0xc 32 true SCLK Output Disable When in bit-bang mode, this bit controls the SCLK output enable. 2 1 read-write CSb Output Disable When in bit-bang mode, this bit controls the CSb output enable. 3 1 read-write SI Output Disable When in bit-bang mode, this bit controls the SI output enable. 4 1 read-write SO Output Disable When in bit-bang mode, this bit controls the SO output enable. 5 1 read-write READ 32bits of read data are used when read commands are executed. 0x10 32 true SCLK Input Value When in bit-bang mode, this bit reads the current SCLK input value. 2 1 read-write CSb Input Value When in bit-bang mode, this bit reads the current CSb input value. 3 1 read-write SI Input Value When in bit-bang mode, this bit reads the current SI input value. 4 1 read-write SO Input Value When in bit-bang mode, this bit reads the current SO input value. 5 1 read-write NVM_CFG_1 0x14 32 true Flash Mode Enable Flash Interface mode. 0 1 read-write Buffer Mode Enable SSRAM Buffered Interface mode. 1 1 read-write Pass Mode Enable pass-thorough mode to the byte level SPI and SEE state machines. 2 1 read-write Bitbang Mode Enable bit-bang mode to control pins. 3 1 read-write Status Bit Bit Offset in status command response to interpret as the ready flag. 4 3 read-write SPI CLK DIV The equation to calculate the clock freq. for SCK is: CORE_CLK / ((SPI_CLK_DIV + 1) * 2) 7 4 read-write Protect Mode 24 1 read-write Flash Size Enables 1-Mbit devices as opposed to 512 Kbit. At CORE reset, this pin is set to the value of the SO pin. 25 1 read-write Page Size These bits indicate the page size of the attached flash device. They are set automatically depending on the chosen flash as indicated by the strapping option pins. 28 3 read-write 256 bytes 0 512 bytes 1 1024 bytes 2 2048 bytes 3 4096 bytes 4 264 bytes 5 NVM_CFG_2 0x18 32 true Erase Command This is the Flash page erase command. 0 8 read-write Status Command This is the Flash status register read command. 16 8 read-write NVM_CFG_3 0x1c 32 true Write Command Command to write a series of bytes into a selected page in the Flash device. Note: this write command wraps around to the beginning of the page after the internal address counter in the Flash device reaches the end of the page. 8 8 read-write Read Command This is the Flash/SEEPROM read command. Following this command, any number of bytes may be read up to the end of the flash memory. 24 8 read-write SOFTWARE_ARBITRATION 0x20 32 true Req Set0 Set Software Arbitration request Bit 0. This bit is set by writing a 1 to this bit position. 0 1 read-write Req Set1 Set Software Arbitration request Bit 1. This bit is set by writing a 1 to this bit position. 1 1 read-write Req Set2 Set Software Arbitration request Bit 2. This bit is set by writing a 1 to this bit position. 2 1 read-write Req Set3 Set Software Arbitration request Bit 3. This bit is set by writing a 1 to this bit position. 3 1 read-write Req Clr0 Clear Software Arbitration request Bit 0. This bit is cleared by writing a 1 to this bit position. 4 1 read-write Req Clr1 Clear Software Arbitration request Bit 1. This bit is cleared by writing a 1 to this bit position. 5 1 read-write Req Clr2 Clear Software Arbitration request Bit 2. This bit is cleared by writing a 1 to this bit position. 6 1 read-write Req Clr3 Clear Software Arbitration request Bit 3. This bit is cleared by writing a 1 to this bit position. 7 1 read-write Arb Won0 When arbitration is won, this bit will be read as 1, when an operation is complete, then the Req Clr0 must be written to clear this bit. 8 1 read-write Arb Won1 When arbitration is won, this bit will be read as 1, when an operation is complete, then the Req Clr1 must be written to clear this bit. 9 1 read-write Arb Won2 When arbitration is won, this bit will be read as 1, when an operation is complete, then the Req Clr2 must be written to clear this bit. 10 1 read-write Arb Won3 When arbitration is won, this bit will be read as 1, when an operation is complete, then the Req Clr3 must be written to clear this bit. 11 1 read-write Req0 This is the status of requester 0. When this bit is one, it means that Req Set0 has been set since Req Clr0. 12 1 read-write Req1 This is the status of requester 1. When this bit is one, it means that Req Set1 has been set since Req Clr1. 13 1 read-write Req2 This is the status of requester 2. When this bit is one, it means that Req Set2 has been set since Req Clr2. 14 1 read-write Req3 This is the status of requester 3. When this bit is one, it means that Req Set3 has been set since Req Clr3. 15 1 read-write ACCESS 0x24 32 true Enable When 1, allows the NVRAM write command to be issued even if the NVRAM write enable bit 21 of the mode control register 0x6800. 0 1 read-write Write Enable When 0, prevents write access to all other NVRAM registers, except for the Software arbitration register. 1 1 read-write NVM_WRITE_1 0x28 32 true Write Enable Command Flash write enable command when device with protection function is used. This command will be issued by the flash interface state machine through SPI interface. 0 8 read-write Write Disable Command Flash write disable command when device with protection function is used. This command will be issued by the flash interface state machine through SPI interface. 8 8 read-write ARBITRATION_WATCHDOG 0x2C 32 true reserved Reserved 0 32 read-write AUTO_SENSE_STATUS 0x38 32 true Auto Config Busy Auto Configuration Busy 0 1 read-write Auto Config Enable Auto config feature is enabled through pin strap. 4 1 read-write Auto Config Successful Auto config is successful. 5 1 read-write Auto Config State Auto Config FSM state. 8 5 read-write Auto Detected Device ID Auto detected device ID. 16 5 read-write AT45DB011D 4 AT45DB021D 3 AT45DB041D 0 STM25PE10 11 STM25PE20 10 STM25PE40 8 STM45PE10 12 STM45PE20 13 STM45PE40 14