meklort <PROJECT> NVIC Register Definitions 1.0 NVIC Nested Vectored Interrupt Controller NVIC Nested Vectored Interrupt Controller 0xE000E000 register false Interrupt Control Type Read the Interrupt Controller Type Register to see the number of interrupt lines that the NVIC supports. 0x4 32 true INTLINESNUM 0 4 0 to 32 0 33 to 64 1 65 to 96 2 SysTick Control and Status Use the SysTick Control and Status Register to enable the SysTick features. 0x10 32 true ENABLE It set, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting. 0 1 read-write TICKINT If set, counting down to 0 pends the SysTick handler. 1 1 read-write CLKSOURCE If no reference clock is provided, it is held at 1 and so gives the same time as the core clock. The core clock must be at least 2.5 times faster than the reference clock. If it is not, the count values are Unpredictable. 2 1 read-write COUNTFLAG Returns 1 if timer counted to 0 since last time this was read. Clears on read by application of any part of the SysTick Control and Status Register. If read by the debugger using the DAP, this bit is cleared on read-only if the MasterType bit in the AHB-AP Control Register is set to 0. Otherwise, the COUNTFLAG bit is not changed by the debugger read. 16 1 read-write SysTick Reload Value Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 1 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. 0x14 32 true RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0. 0 24 read-write SysTick Current Value Use the SysTick Current Value Register to find the current value in the register. 0x18 32 true CURRENT Current value at the time the register is accessed. No read-modify-write protection is provided, so change with care. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register. 0 24 read-write SysTick Calibration Value Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply. 0x1c 32 true TENMS This value is the Reload value to use for 10ms timing. Depending on the value of SKEW, this might be exactly 10ms or might be the closest value. If this reads as 0, then the calibration value is not known. This is probably because the reference clock is an unknown input from the system or scalable dynamically. 0 24 read-write SKEW 1 = the calibration value is not exactly 10ms because of clock frequency. This could affect its suitability as a software real time clock. 30 1 read-write NOREF 1 = the reference clock is not provided. 31 1 read-write Interrupt Set-Enable Each bit in the register corresponds to one of 32 interrupts. Setting a bit in the Interrupt Set-Enable Register enables the corresponding interrupt. When the enable bit of a pending interrupt is set, the processor activates the interrupt based on its priority. When the enable bit is clear, asserting its interrupt signal pends the interrupt, but it is not possible to activate the interrupt, regardless of its priority. Therefore, a disabled interrupt can serve as a latched general-purpose I/O bit. You can read it and clear it without invoking an interrupt. 0x100 32 true SETENA Writing 0 to a SETENA bit has no effect. Reading the bit returns its current enable state. Reset clears the SETENA fields. 0 32 read-write H2B 0x100 RX Packet Even Port 0 or 2 received a packet. 0x800 SMBUS 0 0x4000 SMBUS 1 0x10000 RMU Egress A packet was transmitted via the RMU 0x20000 General Reset 0x100000 VMain The Vmain port state has changed. 0x1000000 Link State Even Port 0 or 2 has had a link state event. 0x2000000 Link State Odd Port 1 or 3 has had a link state event. 0x4000000 RX Packet Odd Port 1 or 3 received a packet. 0x8000000 Interrupt Clear-Enable Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Clear-Enable Register bit disables the corresponding interrupt. 0x180 32 true CLRENA Writing 0 to a CLRENA bit has no effect. Reading the bit returns its current enable state. 0 32 read-write H2B 0x100 RX Packet Even Port 0 or 2 received a packet. 0x800 SMBUS 0 0x4000 SMBUS 1 0x10000 RMU Egress A packet was transmitted via the RMU 0x20000 General Reset 0x100000 VMain The Vmain port state has changed. 0x1000000 Link State Even Port 0 or 2 has had a link state event. 0x2000000 Link State Odd Port 1 or 3 has had a link state event. 0x4000000 RX Packet Odd Port 1 or 3 received a packet. 0x8000000 Interrupt Set-Pending Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Set-Pending Register bit pends the corresponding interrupt. 0x200 32 true SETPEND Writing 0 to a SETPEND bit has no effect. Reading the bit returns its current state. 0 32 read-write H2B 0x100 RX Packet Even Port 0 or 2 received a packet. 0x800 SMBUS 0 0x4000 SMBUS 1 0x10000 RMU Egress A packet was transmitted via the RMU 0x20000 General Reset 0x100000 VMain The Vmain port state has changed. 0x1000000 Link State Even Port 0 or 2 has had a link state event. 0x2000000 Link State Odd Port 1 or 3 has had a link state event. 0x4000000 RX Packet Odd Port 1 or 3 received a packet. 0x8000000 Interrupt Clear-Pending Each bit in the register corresponds to one of the 32 interrupts. Setting an Interrupt Clear-Pending Register bit puts the corresponding pending interrupt in the inactive state. 0x280 32 true CLRPEND Writing 0 to a CLRPEND bit has no effect. Reading the bit returns its current state. 0 32 read-write H2B 0x100 RX Packet Even Port 0 or 2 received a packet. 0x800 SMBUS 0 0x4000 SMBUS 1 0x10000 RMU Egress A packet was transmitted via the RMU 0x20000 General Reset 0x100000 VMain The Vmain port state has changed. 0x1000000 Link State Even Port 0 or 2 has had a link state event. 0x2000000 Link State Odd Port 1 or 3 has had a link state event. 0x4000000 RX Packet Odd Port 1 or 3 received a packet. 0x8000000 Active Bit Read the Active Bit Register to determine which interrupts are active. Each flag in the register corresponds to one of the 32 interrupts. 0x300 32 true ACTIVE Interrupt active flags. 0 32 read-write Interrupt Priority 0 Use the Interrupt Priority Registers to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. 0x400 32 true PRI_0 Priority of Interrupt 0. 0 8 read-write PRI_1 Priority of Interrupt 1. 8 8 read-write PRI_2 Priority of Interrupt 2. 16 8 read-write PRI_3 Priority of Interrupt 3. 24 8 read-write Interrupt Priority 1 Use the Interrupt Priority Registers to assign a priority from 0 to 255 to each of the available interrupts. 0 is the highest priority, and 255 is the lowest. 0x404 32 true PRI_4 Priority of Interrupt 4. 0 8 read-write PRI_5 Priority of Interrupt 5. 8 8 read-write PRI_6 Priority of Interrupt 6. 16 8 read-write PRI_7 Priority of Interrupt 7. 24 8 read-write CPU ID Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core. 0xd00 32 true REVISION Implementation defined revision number. 0 4 read-write PARTNO Reads as 0xF 4 12 read-write Constant Priority of Interrupt 6. 16 4 read-write VARIANT Implementation defined variant number. 20 4 read-write IMPLEMENTER Implementer code. ARM is 0x41. 24 8 read-write Interrupt Control State Use the Interrupt Control State Register to: set a pending Non-Maskable Interrupt (NMI), set or clear a pending SVC, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception. 0xd04 32 true VECTACTIVE Active ISR number field. VECTACTIVE contains the interrupt number of the currently running ISR, including NMI and Hard Fault. A shared handler can use VECTACTIVE to determine which interrupt invoked it. You can subtract 16 from the VECTACTIVE field to index into the Interrupt Clear/Set Enable, Interrupt Clear Pending/SetPending and Interrupt Priority Registers. INTISR[0] has vector number 16. 0 9 read-Only RETTOBASE This bit is 1 when the set of all active exceptions minus the IPSR_current_exception yields the empty set. 11 1 read-Only VECTPENDING Pending ISR number field. VECTPENDING contains the interrupt number of the highest priority pending ISR. 12 10 read-Only ISRPENDING Interrupt pending flag. Excludes NMI and Faults. 22 1 read-Only ISRPREEMPT You must only use this at debug time. It indicates that a pending interrupt becomes active in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced. 23 1 read-Only PENDSTCLR Clear pending SysTick bit. 25 1 write-Only PENDSTSET Set a pending SysTick bit. 26 1 read-write PENDSVCLR Clear pending pendSV bit. 27 1 write-Only PENDSVSET Set pending pendSV bit. 28 1 read-write NMIPENDSET NMIPENDSET pends and activates an NMI. Because NMI is the highest-priority interrupt, it takes effect as soon as it registers. 31 1 read-write Vector Table Offset Use the Vector Table Offset Register to determine: if the vector table is in RAM or code memory, the vector table offset. 0xd08 32 true TBLOFF Vector table base offset field. Contains the offset of the table base from the bottom of the SRAM or CODE space. 7 22 read-write TBLBASE Table base is in Code (0) or RAM (1). 29 1 read-write Application Interrupt and Reset Control the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information for debug or to recover from a hard failure, execute a system reset, alter the priority grouping position (binary point). 0xd0c 32 true VECTRESET System Reset bit. Resets the system, with the exception of debug components. 0 1 read-write VECTCLRACTIVE Clear active vector bit. 1 1 read-write SYSRESETREQ Causes a signal to be asserted to the outer system that indicates a reset is requested. Intended to force a large system reset of all major components except for debug. Setting this bit does not prevent Halting Debug from running. 2 1 read-write PRIGROUP PRIGROUP field is a binary point position indicator for creating subpriorities for exceptions that share the same pre-emption level. It divides the PRI_n field in the Interrupt Priority Register into a pre-emption level and a subpriority level. The binary point is a left-of value. This means that the PRIGROUP value represents a point starting at the left of the Least Significant Bit (LSB). This is bit [0] of 7:0. The lowest value might not be 0 depending on the number of bits allocated for priorities, and implementation choices. 8 3 read-write ENDIANESS Data endianness bit: 1 = big endian. 15 1 read-write VECTKEY Register key. Writing to this register requires 0x5FA in the VECTKEY field. Otherwise the write value is ignored. Reads as 0xFA05. 16 16 read-write System Control Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states. 0xd10 32 true SLEEPONEXIT Sleep on exit when returning from Handler mode to Thread mode: 1 = sleep on ISR exit. 1 1 read-write SLEEPDEEP 1 = indicates to the system that Cortex-M3 clock can be stopped. Setting this bit causes the SLEEPDEEP port to be asserted when the processor can be stopped. 2 1 read-write SEVONPEND When enabled, this causes WFE to wake up when an interrupt moves from inactive to pended. Otherwise, WFE only wakes up from an event signal, external and SEV instruction generated. The event input, RXEV, is registered even when not waiting for an event, and so effects the next WFE. 4 1 read-write Configuration Control Use the Configuration Control Register to: enable NMI, Hard Fault and FAULTMASK to ignore bus fault, trap divide by zero, and unaligned accesses, enable user access to the Software Trigger Exception Register, control entry to Thread Mode. 0xd14 32 true NONEBASETHRDENA When 0, default, It is only possible to enter Thread mode when returning from the last exception. When set to 1, Thread mode can be entered from any level in Handler mode by controlled return value. 0 1 read-write USERSETMPEND If written as 1, enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception, which is one associated with the Main stack pointer. 1 1 read-write UNALIGN_TRP Trap for unaligned access. This enables faulting/halting on any unaligned half or full word access. Unaligned load-store multiples always fault. The relevant Usage Fault Status Register bit is UNALIGNED, see Usage Fault Status Register. 3 1 read-write DIV_0_TRP Trap on Divide by 0. This enables faulting/halting when an attempt is made to divide by 0. The relevant Usage Fault Status Register bit is DIVBYZERO, see Usage Fault Status Register. 4 1 read-write BFHFNMIGN When enabled, this causes handlers running at priority -1 and -2 (Hard Fault, NMI, and FAULTMASK escalated handlers) to ignore Data Bus faults caused by load and store instructions. When disabled, these bus faults cause a lock-up. You must only use this enable with extreme caution. All data bus faults are ignored – you must only use it when the handler and its data are in absolutely safe memory. Its normal use is to probe system devices and bridges to detect control path problems and fix them. 8 1 read-write STKALIGN 1 = on exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned and the context to restore it is saved. The SP is restored on the associated exception return. 0 = only 4-byte alignment is guaranteed for the SP used prior to the exception on exception entry. 9 1 read-write System Handler Priority 4 System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault. 0xd18 32 true PRI_4 Priority of Mem Manage. 0 8 read-write PRI_5 Priority of Bus Fault. 8 8 read-write PRI_6 Priority of Usage Fault. 16 8 read-write PRI_7 Reserved. 24 8 read-write System Handler Priority 8 System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault. 0xd1c 32 true PRI_8 Reserved. 0 8 read-write PRI_9 Reserved. 8 8 read-write PRI_10 Reserved. 16 8 read-write PRI_11 Priority of SVCall. 24 8 read-write System Handler Priority 12 System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Most can be masked on (enabled) or off (disabled). When disabled, the fault is always treated as a Hard Fault. 0xd20 32 true PRI_12 Priority of Debug Monitor. 0 8 read-write PRI_13 Reserved. 8 8 read-write PRI_14 Priority of PendSV. 16 8 read-write PRI_15 Priority of SysTick. 24 8 read-write System Handler Control and State Use the System Handler Control and State Register to: enable or disable the system handlers, determine the pending status of bus fault, mem manage fault, and SVC, determine the active status of the system handlers. 0xd24 32 true MEMFAULTACT Reads as 1 if MemManage is active. 0 1 read-write BUSFAULTACT Reads as 1 if BusFault is active. 1 1 read-write USGFAULTACT Reads as 1 if UsageFault is active. 3 1 read-write SVCALLACT Reads as 1 if SVCall is active. 7 1 read-write MONITORACT Reads as 1 if the Monitor is active. 8 1 read-write PENDSVACT Reads as 1 if PendSV is active. 10 1 read-write SYSTICKACT Reads as 1 if SysTick is active. 11 1 read-write USGFAULTPENDED Read as 1 if usage fault is pended. 12 1 read-write MEMFAULTPENDED Reads as 1 if MemManage is pended. 13 1 read-write BUSFAULTPENDED Reads as 1 if BusFault is pended. 14 1 read-write SVCALLPENDED Reads as 1 if SVCall is pended. 15 1 read-write MEMFAULTENA Set to 0 to disable, else 1 for enabled. 16 1 read-write BUSFAULTENA Set to 0 to disable, else 1 for enabled. 17 1 read-write USGFAULTENA Set to 0 to disable, else 1 for enabled. 18 1 read-write Fault Status The flags in these registers indicate the causes of local faults. Multiple flags can be set if more than one fault occurs. These register are read/write-clear. This means that they can be read normally, but writing a 1 to any bit clears that bit. 0xd28 32 true Memory Manage Fault Status The flags in the Memory Manage Fault Status Register indicate the cause of memory access faults. 0 8 read-write Bus Fault Status The flags in the Bus Fault Status Register indicate the cause of bus access faults. 8 8 read-write Usage Fault Status The flags in the Bus Fault Status Register indicate the cause of usage faults. 16 8 read-write Reserved Reserved. 24 8 read-write Hard Fault Status Use the Hard Fault Status Register (HFSR) to obtain information about events that activate the Hard Fault handler. 0xd2c 32 true VECTTBL This bit is set if there is a fault because of vector table read on exception processing (Bus Fault). This case is always a Hard Fault. The return PC points to the pre-empted instruction. 1 1 read-write FORCED Hard Fault activated because a Configurable Fault was received and cannot activate because of priority or because the Configurable Fault is disabled. The Hard Fault handler then has to read the other fault status registers to determine cause. 30 1 read-write DEBUGEVT This bit is set if there is a fault related to debug. This is only possible when halting debug is not enabled. For monitor enabled debug, it only happens for BKPT when the current priority is higher than the monitor. When both halting and monitor debug are disabled, it only happens for debug events that are not ignored (minimally, BKPT). The Debug Fault Status Register is updated. 31 1 read-write Debug Fault Status Use the Debug Fault Status Register to monitor: external debug requests, vector catches, data watchpoint match, BKPT instruction execution, halt requests. 0xd30 32 true HALTED 1 = halt requested by NVIC, including step. The processor is halted on the next instruction. 0 1 read-write BKPT The BKPT flag is set by a BKPT instruction in flash patch code, and also by normal code. Return PC points to breakpoint containing instruction. 1 1 read-write DWTTRAP Data Watchpoint and Trace (DWT) flag. 2 1 read-write VCATCH Vector catch flag. 3 1 read-write EXTERNAL External debug request flag. 4 1 read-write Memory Manage Fault Address Use the Memory Manage Fault Address Register to read the address of the location that caused a Memory Manage Fault. 0xd34 32 true ADDRESS Mem Manage fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the actual address that faulted. Because an access can be split into multiple parts, each aligned, this address can be any offset in the range of the requested size. Flags in the Memory Manage Fault Status Register indicate the cause of the fault. 0 32 read-write Bus Fault Address Use the Bus Fault Address Register to read the address of the location that generated a Bus Fault. 0xd38 32 true ADDRESS Bus fault address field. ADDRESS is the data address of a faulted load or store attempt. When an unaligned access faults, the address is the address requested by the instruction, even if that is not the address that faulted. Flags in the Bus Fault Status Register indicate the cause of the fault. 0 32 read-write Auxiliary Fault Address Use the Auxiliary Fault Status Register (AFSR) to determine additional system fault information to software. The AFSR flags map directly onto the AUXFAULT inputs of the processor, and a single-cycle high level on an external pin causes the corresponding AFSR bit to become latched as one. The bit can only be cleared by writing a one to the corresponding AFSR bit. When an AFSR bit is written or latched as one, an exception does not occur. If you require an exception, you must use an interrupt. 0xd3c 32 true IMPDEF Implementation defined. The bits map directly onto the signal assignment to the AUXFAULT inputs. 0 32 read-write Software Trigger Interrupt Use the Software Trigger Interrupt Register to pend an interrupt to trigger. 0xf00 32 true INTID Interrupt ID field. Writing a value to the INTID field is the same as manually pending an interrupt by setting the corresponding interrupt bit in an Interrupt Set Pending Register. 0 8 read-write 8