meklort
<PROJECT>
Register Definitions
1.0
DEVICE
Device Registers
DEVICE
DEVICE>
Device Registers
0xC0000000
register
false
MISCELLANEOUS_HOST_CONTROL
0x68
32
true
Clear Interrupt
Setting this bit will clear interrupt as long as the mask interrupt bit is not set.
0
1
read-write
Mask Interrupt
Setting this bit will mask future interrupt events from being generated.
1
1
read-write
Enable Endian Byte Swap
Set this bit to enable endian byte swapping when accessing through PCIE target interface.
2
1
read-write
Enable Endian Word Swap
Set this bit to enable endian word swapping when accessing through PCIE target interface.
3
1
read-write
Enable PCI State Register Read/Write Capability
Set this bit to enable PCI state register read/ write capability, otherwise the register is read only.
4
1
read-write
Enable Clock Control Register Read/Write Capability
Set this bit enable clock control register read/ write capability, otherwise, the clock control register is read only.
5
1
read-write
Enable Register Word Swap
Set this bit to enable word swapping when accessing registers through the PCI target device.
6
1
read-write
Enable Indirect Access
Set this bit to enable indirect addressing mode.
7
1
read-write
Mask Interrupt Mode
When set, the interrupt is masked.
8
1
read-write
Enable Tagged Status Mode
When set, an unique 8-bit tag value will be inserted into the Status block status tag.
9
1
read-write
RCB Check
Set this bit to enable RCB check.
10
1
read-write
Interrupt Check
Set this bit to enable the interrupt check.
11
1
read-write
Byte Enable Rule Check
Set this bit to enable the byte enable rule check.
12
1
read-write
Boundary Check
Set this bit to enable crossing 4 KB boundary check.
13
1
read-write
Log Header Overflow
Set this bit to enable log header due to overflow.
14
1
read-write
Enable TLP Minor Error Tolerance
Set this bit to enable TLP minor error tolerance (ATTR/TC/LOCK command).
15
1
read-write
Metal Rev ID
Metal Rev Number
16
8
read-write
0
0
1
1
2
2
All Layer ID
External All Layer Revision ID.
24
4
read-write
A
0
B
1
C
2
Product ID
Product ID.
28
4
read-write
New Product Mapping
0xf
PCI_STATE
0x70
32
true
PCI Expansion ROM Desired
Enable PCI ROM base address register to be visible to the PCI host
5
1
read-write
PCI Expansion ROM Retry
Force PCI Retry for accesses to Expansion ROM region if enabled
6
1
read-write
VPD Available
This bit reads as 1 if the VPD region of the NVRAM can be accessed by the host
7
1
read-write
Flat View
Asserted if the Base Address register presents a 32 MB PCI Address map flat view, otherwise, indicates a 64 KB PCI Address map in standard view
8
1
read-write
Max PCI Target Retry
Indicates the number of PCI clock cycles before Retry occurs, in multiple of 8.
9
3
read-write
Config Retry
When asserted, forces all config access to be retried.
15
1
read-write
APE Control Register Write Enable
When this bit is set the APE control registers may be written.
16
1
read-write
APE Shared Memory Write Enable
When this bit is set the APE shared memory region may be written.
17
1
read-write
APE Program Space Write Enable
When this bit is set the APE program space may be written.
18
1
read-write
Generate Reset Plus
19
1
read-write
REGISTER_BASE
Local controller memory address of a register than can be written or read by writing to the register data register.
0x78
32
true
MEMORY_BASE
Local controller memory address of the NIC memory region that can be accessed via Memory Window data register.
0x7c
32
true
REGISTER_DATA
Register Data at the location pointed by the Register Base Register.
0x80
32
true
MEMORY_DATA
Memory value at the location pointed by the Memory Base Register.
0x84
32
true
UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX
UNDI Receive Return Ring Consumer Index Mailbox
0x88
32
true
UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOW
UNDI Receive Return Ring Consumer Index Mailbox
0x8c
32
true
LINK_STATUS_CONTROL
PCIe standard register.
0xbc
32
true
Negotiated Link Speed
16
4
read-write
PCIe 1.0
1
PCIe 2.0
2
Negotiated Link Width
20
6
read-write
APE_MEMORY_BASE
APE Memory address to read/write using the APE Memory Data register..
0xf8
32
true
APE_MEMORY_DATA
APE Memory value at the location pointed by the Memory Base Register.
0xfc
32
true
160
Unknown register.
0x160
32
true
EMAC_MODE
0x400
32
true
Global Reset
When this bit is set to 1, the MAC state machine is reset. This is a self-clearing bit.
0
1
read-write
Half Duplex
When set, the MII/GMII interface is configured to operate in half-duplex mode and the CSMA/ CD state machines in the MAC are set to half-duplex mode.
1
1
read-write
Port Mode
2
2
read-write
None
0
10/100
1
1000
2
TBI
3
Loopback Mode
When set, an internal loopback path is enabled from the transmit MAC to the receive MAC. This bit is provided for diagnostic purposes only.
4
1
read-write
Tagged MAC Control
Allow the MAC to receive tagged MAC control packets.
7
1
read-write
Enable TX Bursting
Enable transmit bursting in gigabit half-duplex mode.
8
1
read-write
Max Defer
Enable Max Deferral checking statistic.
9
1
read-write
Enable RX Statistics
Enable receive statistics external updates.
11
1
read-write
Clear RX Statistics
Clear receive statistics internal RAM. This bit is self-clearing.
12
1
read-write
Flush RX Statistics
Write receive statistics to external memory. This bit is self-clearing.
13
1
read-write
Enable TX Statistics
Enable transmit statistics external updates.
14
1
read-write
Clear TX Statistics
Clear transmit statistics internal RAM. This bit is self-clearing.
15
1
read-write
Flush TX Statistics
Write transmit statistics to external memory. This bit is self-clearing.
16
1
read-write
Send Config Command
Send config commands when in TBI mode.
17
1
read-write
Magic Packet Detection Enable
Enable Magic Packet detection.
18
1
read-write
ACPI Power On Enable
Enable Wake on LAN filters when in powerdown mode.
19
1
read-write
Enable TCE
Enable Transmit DMA engine.
21
1
read-write
Enable RDE
Enable RDMA engine. Must be set for normal operation.
22
1
read-write
Enable FHDE
Enable receive Frame Header DMA engine. Must be set for normal operation.
23
1
read-write
Keep Frame In WOL
24
1
read-write
Halt Interesting Packet PME
When this bit is set, the WOL signal will not be asserted on an interesting packet match.
25
1
read-write
Free-Running ACPI
When this bit is set, the ACPI state machine will continue running when a match is found. When this bit is clear, the ACPI state machine will halt when a match is found.
26
1
read-write
Enable APE RX Path
This bit must be written a 1 for APE subsystem to receive packets from the EMAC.
27
1
read-write
Enable APE TX Path
This bit must be written a 1 for the EMAC to transmit APE packets.
28
1
read-write
MAC Loopback Mode Control
29
1
read-write
EMAC_STATUS
0x404
32
true
PCS Synced
0
1
read-write
Signal Detect
1
1
read-write
Received Configuration
2
1
read-write
Configuration Changed
3
1
read-write
Sync Changed
4
1
read-write
Port Detect Error
10
1
read-write
Link State Changed
12
1
read-write
MI Completion
22
1
read-write
MI Interrupt
23
1
read-write
AP Error
24
1
read-write
ODI Error
25
1
read-write
RX Stat Overrun
26
1
read-write
TX Stat Overrun
27
1
read-write
EMAC_EVENT
0x408
32
true
Port Detect Error
10
1
read-write
Link State Changed
12
1
read-write
MI Completion
22
1
read-write
MI Interrupt
23
1
read-write
AP Error
24
1
read-write
ODI Error
25
1
read-write
RX Stat Overrun
26
1
read-write
TX Stat Overrun
27
1
read-write
LED_CONTROL
0x40c
32
true
Override Link
If set, overrides hardware control of the three link LEDs. The LEDs will be controlled via bits [3:1].
0
1
read-write
LED 1000
If set along with the LED Override bit, turns on the 1000 Mbps LED.
1
1
read-write
LED 100
If set along with the LED Override bit, turns on the 100 Mbps LED.
2
1
read-write
LED 10
If set along with the LED Override bit, turns on the 10 Mbps LED.
3
1
read-write
Override Traffic
If set, overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bits [6:5].
4
1
read-write
LED Traffic Blink
If set along with the Override Traffic bit and Traffic LED bit, the Traffic LED will blink with the blink rate specified in Override Blink Rate (bit 31) and Blink Period (bits [30:19]) fields.
5
1
read-write
LED Traffic
If set along with the Override Traffic bit, the Traffic LED is turned on.
6
1
read-write
LED Status 1000
7
1
readOnly
LED Status 100
8
1
readOnly
LED Status 10
9
1
readOnly
LED Status Traffic
10
1
readOnly
LED Mode
11
2
read-write
MAC
LED signal is in active low (on) when link is established and is in high (off) when link is not established.
0
PHY Mode 1
LED signal is in active low (on) when link is established and is in tristate (off) when link is not established.
1
PHY Mode 2
LED signal is in active low (on) when link is established and is in high (off) when link is not established.
2
PHY Mode 3
Same as PHY mode 1
3
MAC Mode
When this bit is set, the traffic LED blinks only when traffic is addressed for the device (The LED_MODE field must be set to 00 before enabling this bit).
13
1
read-write
Shared Traffic/Link LED Mode
When this bit is set, the Link LED is solid green when there is a link and blinks when there is traffic. (The LED_MODE field must be set to 00 before enabling this bit).
14
1
read-write
Blink Period
Specifies the period of each blink cycle (on+off) for Traffic LED in milliseconds. Must be a nonzero value. This 12-bit field is reset to 0x040, giving a default blink period of approximately 15.9Hz.
19
12
read-write
Override Blink Rate
If set, the blink rate for the Traffic LED is determined by the Blink Period field (bit 30 to bit 19). This bit is rest to 1.
31
1
read-write
EMAC_MAC_ADDRESSES_0_HIGH
Upper 2-bytes of this node's MAC address.
0x410
32
true
EMAC_MAC_ADDRESSES_0_LOW
Lower 4-byte of this node's MAC address.
0x414
32
true
EMAC_MAC_ADDRESSES_1_HIGH
Upper 2-bytes of this node's MAC address.
0x418
32
true
EMAC_MAC_ADDRESSES_1_LOW
Lower 4-byte of this node's MAC address.
0x41c
32
true
EMAC_MAC_ADDRESSES_2_HIGH
Upper 2-bytes of this node's MAC address.
0x420
32
true
EMAC_MAC_ADDRESSES_2_LOW
Lower 4-byte of this node's MAC address.
0x424
32
true
EMAC_MAC_ADDRESSES_3_HIGH
Upper 2-bytes of this node's MAC address.
0x428
32
true
EMAC_MAC_ADDRESSES_3_LOW
Lower 4-byte of this node's MAC address.
0x42c
32
true
WOL_PATTERN_POINTER
Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary).
0x430
32
true
WOL_PATTERN_CFG
0x434
32
true
438
Unknown register.
0x438
32
true
MTU_SIZE
2-byte field which is the largest size frame that will be accepted without being marked as oversize.
0x43c
32
true
MTU
2-byte field which is the largest size frame that will be accepted without being marked as oversize.
0
16
read-write
MII_COMMUNICATION
0x44c
32
true
Transaction Data
When configured for a write command, the data stored at this location is written to the PHY at the specified PHY and register address. During a read command, the data returned by the PHY is stored at this location.
0
16
read-write
Register Address
Address of the register to be read or written.
16
5
read-write
PHY Address
21
5
read-write
PHY 0
1
PHY 1
2
PHY 2
3
PHY 3
4
SGMII 0
8
SGMII 1
9
SGMII 2
10
SGMII 3
11
Command
26
2
read-write
Write
1
Read
2
Read Failed
When set, the transceiver device did not drive the bus during the attempted read transaction. Valid after the Start/Busy bit is cleared.
28
1
readOnly
Start/Busy
Set this bit to start a transaction. While it is high, it indicates that the current transaction is still ongoing. If enabled, generates an attention via EMAC Status Register MI Completion bit (bit 22).
29
1
read-write
MII_MODE
0x454
32
true
PHY Address
This field specifies the PHY Address.
5
5
read-write
Constant MDIO/MDC Clock Speed
Enable ~500Khz constant MII management interface (MDIO/MDC) frequency regardless core clock frequency.
15
1
read-write
MII Clock Count
Counter to divide CORE_CLK (62.5 MHz) to generate the MI clock. CORE_CLK/2/(MII Clock Count + 1).
16
5
read-write
TRANSMIT_MAC_MODE
0x45c
32
true
Reset
When this bit is set to 1, the Transmit MAC state machine will be reset. This is a self-clearing bit.
0
1
read-write
Enable TDE
Used to be enable TDE in legacy-same purpose.
1
1
read-write
Enable Flow Control
MAC will send 802.3x flow control frames.
4
1
read-write
Enable Big Backoff
MAC will use larger than normal back-off algorithm.
5
1
read-write
Enable Long Pause
When set, the Pause time value set in the transmitted PAUSE frames is 0xFFFF.
6
1
read-write
Link Aware Enable
When set, transmission of packets by the MAC is enabled only when link is up.
7
1
read-write
TxMBUF Corruption Lockup Fix Enable
When set, TXMBUF corruption lockup fix is enabled.
8
1
read-write
Enable TX ESP Offload
A value 1 enables the TX ESP offload feature. When 0, offloaded ESP packet gets dropped. This value must be static.
9
1
read-write
Enable TX AH Offload
A value 1 enables the TX AH offload feature. When 0, offloaded AH packet gets dropped. This value must be static.
10
1
read-write
TRANSMIT_MAC_STATUS
0x460
32
true
XOFFED
0
1
read-write
Sent XOFF
1
1
read-write
Sent XON
2
1
read-write
Link Up
3
1
read-write
ODI Underrun
4
1
read-write
ODI Overrun
5
1
read-write
TRANSMIT_MAC_LENGTHS
0x464
32
true
Slot Time Length
When multiplied by 2, this field indicates the number of bytes in the slot time.
0
8
read-write
IPG Length
When multiplied by 2, this field indicates the number of bytes in the entire IPG.
8
4
read-write
IPG CRS Length
When multiplied by 2, this field indicates the number of bytes from the end of the interpacket gap (IPG) during which incoming carrier is ignored.
12
2
read-write
HTX2B Jumbo Frame Length
This value + 1500 is used by hardware as the maximum standard frame length for HTX2B. A frame with a length larger than that is a jumbo frame for HTX2B. The length is the effective length of a composed L2 frame as seen from the wire, including the L2 header, L2 payload, and the FCS (CRC) field.
16
8
read-write
HTX2B Count Down Value
HT2XB Count Down Value
24
8
read-write
RECEIVE_MAC_MODE
0x468
32
true
Reset
When this bit is set to 1, the Receive MAC state machine will be reset. This is a self-clearing bit.
0
1
read-write
Enable
This bit controls whether the Receive MAC state machine is active or not.
1
1
read-write
Promiscuous Mode
When set, no source address or MC hashing checking will be performed on incoming frames.
8
1
read-write
APE Promiscuous Mode
When set, no source address or MC hashing checking will be performed on incoming frames on APE filter path.
25
1
read-write
RECEIVE_MAC_STATUS
0x46c
32
true
Remote TX XOFFED
0
1
read-write
XOFF Received
1
1
read-write
XON Received
2
1
read-write
PERFECT_MATCH1_HIGH
0x540
32
true
High
Upper two bytes of the MAC
0
16
read-write
PERFECT_MATCH1_LOW
0x544
32
true
Low
Lower four bytes of the MAC
0
32
read-write
PERFECT_MATCH2_HIGH
0x548
32
true
High
Upper two bytes of the MAC
0
16
read-write
PERFECT_MATCH2_LOW
0x54c
32
true
Low
Lower four bytes of the MAC
0
32
read-write
PERFECT_MATCH3_HIGH
0x550
32
true
High
Upper two bytes of the MAC
0
16
read-write
PERFECT_MATCH3_LOW
0x554
32
true
Low
Lower four bytes of the MAC
0
32
read-write
PERFECT_MATCH4_HIGH
0x558
32
true
High
Upper two bytes of the MAC
0
16
read-write
PERFECT_MATCH4_LOW
0x55c
32
true
Low
Lower four bytes of the MAC
0
32
read-write
SGMII_STATUS
This register reflects various status of the respective SGMII port when enabled.
0x5b4
32
true
Autonegotiation Complete
Auto-negotiation process has completed.
0
1
readOnly
Link Status
1
1
readOnly
Duplex Status
2
1
readOnly
Speed 1000
The SGMII Link currently operable at 1 Gbps data speed.
3
1
readOnly
Speed 100
The SGMII Link currently operable at 100mbps data speed.
4
1
readOnly
Next Page RX
5
1
readOnly
Pause RX
6
1
readOnly
Pause TX
7
1
readOnly
Media Selection Mode
8
1
readOnly
Copper
0
SGMII
1
PCS CRS Detect
9
1
read-write
External CRS Detect
10
1
read-write
Link Partner Autonegotiation Capability
16
16
read-write
Receive List Placement Mode
0x2000
32
true
Reset
When this bit is set to 1, the Receive List Placement state machine is reset. This is a self clearing bit.
0
1
read-write
Enable
This bit controls whether the Receive List Placement state machine is active or not. When set to 0, it completes the current operation and cleanly halts. Until it is completely halted, it remains one when read.
1
1
read-write
Class Zero Attention Enable
Enable attention for zero class field.
2
1
read-write
Mapping out of Range Attention Enable
Enable attention for mapping out of range error.
3
1
read-write
Stats Overflow Attention Enable
Enable attention for statistics overflow.
4
1
read-write
Receive List Placement Status
0x2004
32
true
Class Zero Attention
Class field extracted from frame descriptor is zero.
2
1
read-write
Mapping out of Range Attention
Class of service mapping is out of the range of the active queue number.
3
1
read-write
Stats Overflow Attention
A statistics managed by Receive List Placement has overflowed.
4
1
read-write
CPMU_CONTROL
0x3600
32
true
CPMU Software Reset
0
1
read-write
CPMU Register Software Reset
1
1
read-write
Power Down
2
1
read-write
APE Sleep Mode Enable
4
1
read-write
APE Deep Sleep Mode Enable
5
1
read-write
Link Idle Power Mode Enable
9
1
read-write
Link Aware Power Mode Enable
10
1
read-write
Link Speed Power Mode Enable
14
1
read-write
GPHY 10MB Receive Only Mode Enable
16
1
read-write
Legacy Timer Enable
18
1
read-write
SGMII/PCS Power Down
19
1
read-write
Software Controlled GPHY Force DLL On
28
1
read-write
NO_LINK_POWER_MODE_CLOCK_POLICY
0x3604
32
true
MAC Clock Switch
Software Controlled MAC Core Clock Speed Select.
16
5
read-write
62.5MHz
0
60.0MHz
1
30.0MHz
3
15.0MHz
5
7.5MHz
7
3.75MHz
9
CK25/2
12.5MHz
17
CK25/4
6.25MHz
19
CK25/8
3.125MHz
21
CK25/16
1.563MHz
23
MII_CLK/2
12.5MHz/1.25MHz
31
LINK_AWARE_POWER_MODE_CLOCK_POLICY
0x3610
32
true
MAC Clock Switch
Software Controlled MAC Core Clock Speed Select.
16
5
read-write
60.0MHz
1
30.0MHz
3
15.0MHz
5
7.5MHz
7
3.75MHz
9
12.5MHz
17
6.25MHz
19
3.125MHz
21
1.563MHz
23
781kHz
25
12.5MHz/1.25MHz
31
D0U_CLOCK_POLICY
0x3614
32
true
MAC Clock Switch
Software Controlled MAC Core Clock Speed Select.
16
5
read-write
60.0MHz
1
30.0MHz
3
15.0MHz
5
7.5MHz
7
3.75MHz
9
12.5MHz
17
6.25MHz
19
3.125MHz
21
1.563MHz
23
781kHz
25
12.5MHz/1.25MHz
31
APE_CLK_POLICY
0x361C
32
true
LAPM APE Clock Switch
Software Controlled APE Clock Speed Select in
Link Aware Power mode
0
5
read-write
25 MHz
17
12.5 MHz
19
6.25 MHz
21
3.125 MHz
23
1.563 MHz
25
APE Clock Switch
Software Controlled APE Clock Speed Select
8
5
read-write
125 MHz
30
62.5 MHz
0
25 MHz
9
12.5 MHz
19
6.25 MHz
21
3.125 MHz
23
1.563 MHz
25
Clock Override APE Clock Switch
Software Controlled APE Clock Speed Select for Clock Override.
16
5
read-write
125 MHz
30
62.5 MHz
0
25 MHz
9
12.5 MHz
19
6.25 MHz
21
3.125 MHz
23
1.563 MHz
25
Force APE HCLK Disable
27
1
read-write
Force APE FCLK Disable
28
1
read-write
APE Clock Speed Override Enable
29
1
read-write
APE Deep Sleep mode Enable
30
1
read-write
APE Sleep mode Enable
31
1
read-write
APE_SLEEP_STATE_CLOCK_POLICY
0x3620
32
true
APE Sleep FCLK Switch
Software Controlled APE Clock Speed Select
0
5
read-write
APE Deep Sleep FCLK Switch
Software Controlled APE Clock Speed Select
16
5
read-write
APE Sleep HCLK Disable
Software Controlled APE HCLK shutoff in sleep and deep sleep state
31
1
read-write
CLOCK_SPEED_OVERRIDE_POLICY
0x3624
32
true
MAC Clock Switch
Software Controlled MAC Core Clock Speed Select
16
5
read-write
MAC Clock Speed Override Enabled
Enable MAC clock speed override
31
1
read-write
STATUS
0x362c
32
true
Power Management State Machine State
0
4
readOnly
CPMU Power State
4
3
readOnly
Energy Detect Status
7
1
readOnly
Power State
8
2
readOnly
VMAIN Power Status
13
1
readOnly
WOL Magic Packet Detection Enable Port 0
14
1
readOnly
WOL ACPI Detection Enable Port 0
15
1
readOnly
NCSI DLL Lock Status
16
1
readOnly
GPHY DLL Lock Status
17
1
readOnly
Link Idle Status
18
1
readOnly
Ethernet Link Status
EthernetLink Status
19
2
readOnly
1000 Mb
0
100 Mb
1
10 Mb
2
No Link
3
WOL Magic Packet Detection Enable Port 1
21
1
readOnly
WOL ACPI Detection Enable Port 1
22
1
readOnly
APE Status
APE Engine Status
23
2
readOnly
Active
0
Sleep
1
Deep Sleep
2
Function Enable
Function Enable input from System BIOS
25
5
readOnly
Function Number
PCIE function number
30
2
readOnly
CLOCK_STATUS
0x3630
32
true
GPHY_CONTROL_STATUS
0x3638
32
true
GPHY IDDQ
When this bit is set, GPHY will be powered down.
0
1
read-write
BIAS IDDQ
When this bit is set, BIAS will be powered down.
1
1
read-write
CPMU Software Reset
Software reset for all the CPMU logic expect for registers.
2
1
read-write
CPMU Register Software Reset
Software reset for resetting all the registers to default.
3
1
read-write
Power Down
Force CPMU into Low Power State, LAN function will be powered down (GPHY, PCIE, IPSEC, APE). This bit is cleared by a rising edge of PERST_L.
4
1
read-write
SGMII/PCS Power Down
Setting this bit will powerdown SGMII-PCS module.
15
1
read-write
PCIe PLL Lock Status
22
1
read-write
GPHY PLL Lock Status
23
1
read-write
NCSI PLL Lock Status
25
1
read-write
TLP Clock Source
26
1
read-write
Switching Regulator Power Down
27
1
read-write
Keep NCSI PLL on during low power mode.
28
1
read-write
CHIP_ID
0x3658
32
true
MUTEX_REQUEST
Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect.
0x365c
32
true
Request
Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect.
0
16
read-write
MUTEX_GRANT
Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared.
0x3660
32
true
Granted
Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared.
0
16
read-write
GPHY_STRAP
0x3664
32
true
TXMBUF ECC Enable
Enable TXMBUF ECC.
2
1
read-write
RXMBUF ECC Enable
Enable RXMBUF ECC.
3
1
read-write
RXCPU SPAD ECC Enable
Enable ECC for rxcpu scratchpad.
4
1
read-write
APE CM3 Big Endian Enable
Enable APE CM3 Big Endian Setting
8
1
read-write
FLASH_CLOCK_CONTROL_POLICY
0x366c
32
true
Override Flash Clock Switch
Software Controlled Flash Clock Speed
0
2
read-write
62.5 MHz NCSI DLL
0
25 MHz
3
Flash Clock Policy
Software Controlled Flash Clock Speed
4
3
read-write
62.5 MHz NCSI DLL
0
25 MHz
3
Flash Idle Clock Policy
Software Controlled Flash Clock Speed
8
3
read-write
62.5 MHz NCSI DLL
0
25 MHz
3
EAV Clock Policy
Software Controlled EAV Clock Speed Select
12
8
read-write
4.8MHz
0
1250 MHz
1
125 MHz
10
Force EAV Clock Disable
28
1
read-write
Flash Idle mode Enable
29
1
read-write
Force Flash Clock Disable
30
1
read-write
Flash Clock Speed Override
31
1
read-write
TOP_LEVEL_MISCELLANEOUS_CONTROL_1
0x367c
32
true
NCSI Clock Output Disable
4
1
read-write
Low Power IDDQ Mode
5
1
read-write
EEE_MODE
0x36b0
32
true
RX CPU Allow LPI
0
1
read-write
Drive Allow LPI
1
1
read-write
APE TX Detection Enable
2
1
read-write
EEE Link Idle Detection Enable
3
1
read-write
PCIe L1 Exit Detection Enable
4
1
read-write
RX CPU Allow LPI Enable
5
1
read-write
Send Index Detection Enable
6
1
read-write
User LPI Enable
7
1
read-write
TX LPI Enable
8
1
read-write
RX LPI Enable
9
1
read-write
Auto Wake Enable
10
1
read-write
Block Time
11
8
read-write
Drive Allow LPI Enable
19
1
read-write
EEE_LINK_IDLE_CONTROL
0x36bc
32
true
Debug UART Idle
2
1
read-write
EEE_CONTROL
0x36d0
32
true
Exit Time
0
16
read-write
16.5 us
0x19d
20.1 us
0x1f8
36 us
0x384
Minimum Assert
16
16
read-write
GLOBAL_MUTEX_REQUEST
0x36f0
32
true
Request
Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect.
0
16
read-write
GLOBAL_MUTEX_GRANT
0x36f4
32
true
Granted
Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared.
0
16
read-write
TEMPERATURE_MONITOR_CONTROL
0x36fc
32
true
ADC Test Enable
0
1
read-write
Bias Adjust
1
7
read-write
Temperature Data
8
8
read-write
Temperature Monitor Hold
17
1
read-write
Temperature Monitor Power Down
18
1
read-write
MEMORY_ARBITER_MODE
0x4000
32
true
Enable
1
1
read-write
BUFFER_MANAGER_MODE
0x4400
32
true
Enable
This bit controls whether the Buffer Manager is active or not.
1
1
read-write
Attention Enable
When this bit is set to 1, an internal attention is generated when an error occurs.
2
1
read-write
Reset RXMBUF Pointer
When this bit is set, it will cause the RXMBUF allocation and deallocation pointer to reset back to the RXMBUF base.
5
1
read-write
LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL
0x4910
32
true
PCI Request Burst Length for BD RDMA Engine
16
2
read-write
128B
0
256B
1
512B
2
4K
3
PCI Request Burst Length for NonLSO RDMA Engine
18
2
read-write
128B
0
256B
1
512B
2
4K
3
RX_RISC_MODE
0x5000
32
true
Reset
Self-clearing bit which resets only the RX RISC.
0
1
writeOnly
Single Step
Advances the RX RISC's PC for one cycle. If halting condition still exists, the RX RISC will again halt; otherwise, it will resume normal operation.
1
1
read-write
Page 0 Data Halt
When set, data references to the first 256 bytes of SRAM force the RX RISC to halt and cause bit 3 in the RX RISC state register to be latched. Cleared on reset and Watchdog interrupt.
2
1
writeOnly
Page 0 Instr Halt
When set, instruction references to the first 256 bytes of SRAM force the RX RISC to halt and cause bit 4 in the RX RISC state register to be latched. Cleared on reset and Watchdog interrupt.
3
1
writeOnly
Enable Data Cache
Enables the data cache. Cleared on reset. Note: Firmware developers should take care to clear this bit before polling internal SRAM memory locations, because the RX RISC processor uses a two-element LRU caching algorithm, which is not affected by writes from the PCI interface.
5
1
read-write
ROM Fail
Asserted on reset. Cleared by ROM code after it successfully loads code from NVRAM. Afterwards, this bit can be used by software for any purpose.
6
1
read-write
Enable Watchdog
Enables watchdog interrupt state machine. Used in conjunction with Watchdog Clear register, Watchdog Saved PC register and Watchdog Vector register. Cleared on reset and Watchdog interrupt.
7
1
read-write
Enable Instruction Cache
Enables prefetch logic within the instruction cache. When disabled only a single cache line is read on a cache miss. Cleared on reset.
8
1
read-write
Flush Instruction Cache
Self-clearing bit which forces the instruction cache to flush.
9
1
read-write
Halt
Set by TX RISC or the host to halt the RX RISC. Cleared on reset and Watchdog interrupt.
10
1
read-write
Invalid Data Access Halt
When set, the condition that causes RX RISC state bit 5 to be set, also halts the RX RISC. Set by reset.
11
1
read-write
Invalid Instruction Access Halt
When set, the condition that causes RX RISC state bit 6 to be set, also halts the RX RISC. Set by reset.
12
1
read-write
Enable Memory Address Trap Halt
When set, if the MA raises the trap signal to this processor, it will halt. CLeared on reset and Watchdog interrupt.
13
1
read-write
Enable Register Address Trap Halt
When set, if the GRC raises the trap signal to this processor, it will halt. CLeared on reset and Watchdog interrupt.
14
1
read-write
RX_RISC_STATUS
0x5004
32
true
Hardware Breakpoint
When enabled in mode register, indicates hardware breakpoint has been reached.
0
1
read-write
Halt Instruction Executed
When enabled in mode register, indicates hardware breakpoint has been reached.
1
1
read-write
Invalid Instruction
Invalid instruction fetched.
2
1
read-write
Page 0 Data Refeence
When enabled in mode register, indicates data reference within lower 256 bytes of SRAM.
3
1
read-write
Page 0 Instruction Reference
When enabled in mode register, indicates the address in the PC is within the lower 256 bytes of SRAM.
4
1
read-write
Invalid Data Access
Data reference to illegal location.
5
1
read-write
Invalid Instruction Fetch
Program Counter (PC) is set to invalid location in processor address space.
6
1
read-write
Bad Memory Alignment
Load or Store instruction was executed with the least significant two address bits not valid for the width of the operation (e.g., Load word or Load Half-word from an odd byte address).
7
1
read-write
Memory Address Trap
A signal was received from the Memory Arbiter indicating that some BCM5700 block, possibly this processor, accessed a memory location that triggered a software trap. The MA registers are used to configure memory address trapping.
8
1
read-write
Register Address Trap
A signal was received from the Global Resources block indicating that this processor accessed a register location that triggered a software trap. The GRC registers are used to configure register address trapping.
9
1
read-write
Halted
The RX RISC was explicitly halted via bit 10 in the RX RISC Mode register.
10
1
read-write
Unknown
11
1
read-write
Data Access Stall
The processor is currently stalled due to a data access.
14
1
read-write
Instruction Fetch Stall
The processor is currently stalled due to an instruction fetch.
15
1
read-write
Blocking Read
A blocking data cache miss occurred, causing the RX RISC to stall while data is fetched from external (to the RX RISC) memory. This is intended as a debugging tool. No state is saved other than the fact that the miss occurred.
31
1
read-write
RX_RISC_EVENT_MASK
0x5008
32
true
RX_RISC_PROGRAM_COUNTER
The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored.
0x501c
32
true
RX_RISC_CURRENT_INSTRUCTION
This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed.
0x5020
32
true
RX_RISC_INTERRUPT_ENABLE
Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can’t respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero.
0x5028
32
true
RX_RISC_INTERRUPT_VECTOR
This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input.
0x502c
32
true
RX_RISC_HARDWARE_BREAKPOINT
This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit.
0x5034
32
true
RX_RISC_LAST_BRANCH_ADDRESS
This register indicates that address and branch type of the last branch that was taken. This register is for debug use only.
0x5048
32
true
Type
This indicates the jump or branch type.
1
1
read-write
Jump
4 bytes must be subtracted from the LBA value to determine the actual address of the branch instruction that caused this register to load.
0
Branch
1
8 bytes must be subtracted from the LBA value to determine the actual address of the branch instruction that caused this register to load.
Last Branch Address
This value indicates the address of the last branch that was taken. An offset as indicated by the type field must be subtracted from this value.
2
30
read-write
RX_RISC_REGISTER_0
$zero (R0)
0x5200
32
true
RX_RISC_REGISTER_1
$at (R1)
0x5204
32
true
RX_RISC_REGISTER_2
$v0 (R2)
0x5208
32
true
RX_RISC_REGISTER_3
$v1 (R3)
0x520c
32
true
RX_RISC_REGISTER_4
$a0 (R4)
0x5210
32
true
RX_RISC_REGISTER_5
$a1 (R5)
0x5214
32
true
RX_RISC_REGISTER_6
$a2 (R6)
0x5218
32
true
RX_RISC_REGISTER_7
$a3 (R7)
0x521c
32
true
RX_RISC_REGISTER_8
$t0 (R8)
0x5220
32
true
RX_RISC_REGISTER_9
$t1 (R9)
0x5224
32
true
RX_RISC_REGISTER_10
$t2 (R10)
0x5228
32
true
RX_RISC_REGISTER_11
$t3 (R11)
0x522c
32
true
RX_RISC_REGISTER_12
$t4 (R12)
0x5230
32
true
RX_RISC_REGISTER_13
$t5 (R13)
0x5234
32
true
RX_RISC_REGISTER_14
$t6 (R14)
0x5238
32
true
RX_RISC_REGISTER_15
$t7 (R15)
0x523c
32
true
RX_RISC_REGISTER_16
$s0 (R16)
0x5240
32
true
RX_RISC_REGISTER_17
$s1 (R17)
0x5244
32
true
RX_RISC_REGISTER_18
$s2 (R18)
0x5248
32
true
RX_RISC_REGISTER_19
$s3 (R19)
0x524c
32
true
RX_RISC_REGISTER_20
$s4 (R20)
0x5250
32
true
RX_RISC_REGISTER_21
$s5 (R21)
0x5254
32
true
RX_RISC_REGISTER_22
$s6 (R22)
0x5258
32
true
RX_RISC_REGISTER_23
$s7 (R23)
0x525c
32
true
RX_RISC_REGISTER_24
$t8 (R24)
0x5260
32
true
RX_RISC_REGISTER_25
$t9 (R25)
0x5264
32
true
RX_RISC_REGISTER_26
$k0 (R26)
0x5268
32
true
RX_RISC_REGISTER_27
$k1 (R27)
0x526c
32
true
RX_RISC_REGISTER_28
$gp (R28)
0x5270
32
true
RX_RISC_REGISTER_29
$sp (R29)
0x5274
32
true
RX_RISC_REGISTER_30
$fp (R30)
0x5278
32
true
RX_RISC_REGISTER_31
$ra (R31)
0x527c
32
true
6408
0x6408
32
true
PCI_POWER_CONSUMPTION_INFO
This undocumented register is used to set PCIe Power Consumption information as reported in configuration space. It is loaded from NVM configuration data.
0x6410
32
true
PCI_POWER_DISSIPATED_INFO
This undocumented register is used to set PCIe Power Dissipated information as reported in configuration space. It is loaded from NVM configuration data.
0x6414
32
true
PCI_VPD_REQUEST
This undocumented register appears to be used to implement the PCI VPD capability. It is set to the VPD offset which was requested by the host by writing to the VPD register.
0x642c
32
true
Requested VPD Offset
16
15
read-write
PCI_VPD_RESPONSE
This undocumented register appears to be used to implement the PCI VPD capability. Bootcode writes the 32 bits of data loaded from the word requested by
0x6430
32
true
PCI_VENDOR_DEVICE_ID
This is the undocumented register used to set the PCI Vendor/Device ID, which is configurable from NVM.
0x6434
32
true
Device ID
0
16
read-write
Vendor ID
16
16
read-write
PCI_SUBSYSTEM_ID
This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM.
0x6438
32
true
Subsystem Vendor ID
0
16
read-write
Subsystem ID
16
16
read-write
PCI_CLASS_CODE_REVISION
This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed.
0x643c
32
true
64C0
0x64c0
32
true
64C4
0x64c4
32
true
64C8
0x64c8
32
true
64DC
0x64dc
32
true
PCI_SERIAL_NUMBER_LOW
This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space.
0x6504
32
true
PCI_SERIAL_NUMBER_HIGH
This sets the high 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space.
0x6508
32
true
PCI_POWER_BUDGET_0
Used to report power budget capability data to the host. The values are loaded from NVM, and up to eight values may be specified.
0x6510
32
true
Base Power
Specifies in watts the base power value in the given operating condition.
0
8
read-write
Data Scale
Specifies the scale to apply to the Base Power value.
8
2
read-write
1.0x
0
0.1x
1
0.01x
2
0.001x
3
PM Sub State
Specifies the power management sub state of the operating condition being described.
10
3
read-write
PM State
Specifies the power management state of the operating condition being described.
13
2
read-write
D0
0
D1
1
D2
2
D3
3
Type
Specifies the power management state of the operating condition being described.
15
3
read-write
PME Aux
0
Auxiliary
1
Idle
2
Sustained
3
Maximum
7
Power Rail
Specifies the thermal load or power rail of the operating condition being described.
18
3
read-write
Power 12V
0
Power 3.3V
1
Power 1.5V or 1.8V
2
Thermal
7
PCI_POWER_BUDGET_1
See
0x6514
32
true
Base Power
Specifies in watts the base power value in the given operating condition.
0
8
read-write
Data Scale
Specifies the scale to apply to the Base Power value.
8
2
read-write
1.0x
0
0.1x
1
0.01x
2
0.001x
3
PM Sub State
Specifies the power management sub state of the operating condition being described.
10
3
read-write
PM State
Specifies the power management state of the operating condition being described.
13
2
read-write
D0
0
D1
1
D2
2
D3
3
Type
Specifies the power management state of the operating condition being described.
15
3
read-write
PME Aux
0
Auxiliary
1
Idle
2
Sustained
3
Maximum
7
Power Rail
Specifies the thermal load or power rail of the operating condition being described.
18
3
read-write
Power 12V
0
Power 3.3V
1
Power 1.5V or 1.8V
2
Thermal
7
PCI_POWER_BUDGET_2
See
0x6518
32
true
Base Power
Specifies in watts the base power value in the given operating condition.
0
8
read-write
Data Scale
Specifies the scale to apply to the Base Power value.
8
2
read-write
1.0x
0
0.1x
1
0.01x
2
0.001x
3
PM Sub State
Specifies the power management sub state of the operating condition being described.
10
3
read-write
PM State
Specifies the power management state of the operating condition being described.
13
2
read-write
D0
0
D1
1
D2
2
D3
3
Type
Specifies the power management state of the operating condition being described.
15
3
read-write
PME Aux
0
Auxiliary
1
Idle
2
Sustained
3
Maximum
7
Power Rail
Specifies the thermal load or power rail of the operating condition being described.
18
3
read-write
Power 12V
0
Power 3.3V
1
Power 1.5V or 1.8V
2
Thermal
7
PCI_POWER_BUDGET_3
See
0x651c
32
true
Base Power
Specifies in watts the base power value in the given operating condition.
0
8
read-write
Data Scale
Specifies the scale to apply to the Base Power value.
8
2
read-write
1.0x
0
0.1x
1
0.01x
2
0.001x
3
PM Sub State
Specifies the power management sub state of the operating condition being described.
10
3
read-write
PM State
Specifies the power management state of the operating condition being described.
13
2
read-write
D0
0
D1
1
D2
2
D3
3
Type
Specifies the power management state of the operating condition being described.
15
3
read-write
PME Aux
0
Auxiliary
1
Idle
2
Sustained
3
Maximum
7
Power Rail
Specifies the thermal load or power rail of the operating condition being described.
18
3
read-write
Power 12V
0
Power 3.3V
1
Power 1.5V or 1.8V
2
Thermal
7
PCI_POWER_BUDGET_4
See
0x6520
32
true
Base Power
Specifies in watts the base power value in the given operating condition.
0
8
read-write
Data Scale
Specifies the scale to apply to the Base Power value.
8
2
read-write
1.0x
0
0.1x
1
0.01x
2
0.001x
3
PM Sub State
Specifies the power management sub state of the operating condition being described.
10
3
read-write
PM State
Specifies the power management state of the operating condition being described.
13
2
read-write
D0
0
D1
1
D2
2
D3
3
Type
Specifies the power management state of the operating condition being described.
15
3
read-write
PME Aux
0
Auxiliary
1
Idle
2
Sustained
3
Maximum
7
Power Rail
Specifies the thermal load or power rail of the operating condition being described.
18
3
read-write
Power 12V
0
Power 3.3V
1
Power 1.5V or 1.8V
2
Thermal
7
PCI_POWER_BUDGET_5
See
0x6524
32
true
Base Power
Specifies in watts the base power value in the given operating condition.
0
8
read-write
Data Scale
Specifies the scale to apply to the Base Power value.
8
2
read-write
1.0x
0
0.1x
1
0.01x
2
0.001x
3
PM Sub State
Specifies the power management sub state of the operating condition being described.
10
3
read-write
PM State
Specifies the power management state of the operating condition being described.
13
2
read-write
D0
0
D1
1
D2
2
D3
3
Type
Specifies the power management state of the operating condition being described.
15
3
read-write
PME Aux
0
Auxiliary
1
Idle
2
Sustained
3
Maximum
7
Power Rail
Specifies the thermal load or power rail of the operating condition being described.
18
3
read-write
Power 12V
0
Power 3.3V
1
Power 1.5V or 1.8V
2
Thermal
7
PCI_POWER_BUDGET_6
See
0x6528
32
true
Base Power
Specifies in watts the base power value in the given operating condition.
0
8
read-write
Data Scale
Specifies the scale to apply to the Base Power value.
8
2
read-write
1.0x
0
0.1x
1
0.01x
2
0.001x
3
PM Sub State
Specifies the power management sub state of the operating condition being described.
10
3
read-write
PM State
Specifies the power management state of the operating condition being described.
13
2
read-write
D0
0
D1
1
D2
2
D3
3
Type
Specifies the power management state of the operating condition being described.
15
3
read-write
PME Aux
0
Auxiliary
1
Idle
2
Sustained
3
Maximum
7
Power Rail
Specifies the thermal load or power rail of the operating condition being described.
18
3
read-write
Power 12V
0
Power 3.3V
1
Power 1.5V or 1.8V
2
Thermal
7
PCI_POWER_BUDGET_7
See
0x652c
32
true
Base Power
Specifies in watts the base power value in the given operating condition.
0
8
read-write
Data Scale
Specifies the scale to apply to the Base Power value.
8
2
read-write
1.0x
0
0.1x
1
0.01x
2
0.001x
3
PM Sub State
Specifies the power management sub state of the operating condition being described.
10
3
read-write
PM State
Specifies the power management state of the operating condition being described.
13
2
read-write
D0
0
D1
1
D2
2
D3
3
Type
Specifies the power management state of the operating condition being described.
15
3
read-write
PME Aux
0
Auxiliary
1
Idle
2
Sustained
3
Maximum
7
Power Rail
Specifies the thermal load or power rail of the operating condition being described.
18
3
read-write
Power 12V
0
Power 3.3V
1
Power 1.5V or 1.8V
2
Thermal
7
6530
0x6530
32
true
6550
The LSB in this undocumented and unknown register is set if the device is a LOM (LAN-on-Motherboard) design (i.e., builtin to a system and not an expansion card).
0x6550
32
true
65F4
0x65f4
32
true
GRC_MODE_CONTROL
0x6800
32
true
Host Stack Up
The host stack is ready to receive data from the NIC.
16
1
read-write
Time Sync Mode Enable
Write 1 to this bit to enable Time Sync Mode.
19
1
read-write
NVRAM Write Enable
The host must set this bit before attempting to update the Flash or SEEPROM.
21
1
read-write
PCIe TL/DL/PL Mapping 1
22
1
read-write
PCIe TL/DL/PL Mapping 2
29
1
read-write
PCIe TL/DL/PL Mapping 3
31
1
read-write
MISCELLANEOUS_CONFIG
0x6804
32
true
GRC Reset
Write 1 to this bit resets the CORE_CLK blocks in the device. This is a self-clearing bit.
0
1
read-write
Timer Prescaler
Local Core clock frequency in MHz, minus 1, which should correspond to each advance of the timer. Reset to all 1.
1
7
read-write
Bond ID
13
4
read-write
Power State
Indicates the current power state of the device.
17
2
read-write
D0
0
D1
1
D2
2
D3
3
PME EN State
State of PME Enable for this device.
19
1
read-write
Powerdown
Setting this bit will power down the device (power consumption is ~20 mW). This bit is cleared by PCI reset.
20
1
read-write
Disable GRC Reset
Setting this bit will prevent reset to PCIE block.
29
1
read-write
MISCELLANEOUS_LOCAL_CONTROL
0x6808
32
true
GPIO 3 Input
5
1
read-write
GPIO 3 Output Enable
6
1
read-write
GPIO 3 Output
7
1
read-write
GPIO 0 Input
8
1
read-write
GPIO 1 Input
9
1
read-write
GPIO 2 Input
10
1
read-write
GPIO 0 Output Enable
11
1
read-write
GPIO 1 Output Enable
12
1
read-write
GPIO 2 Output Enable
13
1
read-write
GPIO 0 Output
14
1
read-write
GPIO 1 Output
15
1
read-write
GPIO 2 Output
16
1
read-write
APE GPIO In
17
7
read-write
Auto SEEPROM Access
24
1
read-write
TIMER
32-bit free-running counter
0x680c
32
true
RX_CPU_EVENT
0x6810
32
true
MAC Attention
25
1
read-write
RX CPU Attention
26
1
read-write
Timer
29
1
read-write
VPD Attention
30
1
read-write
6838
Unknown. Used by PXE agent.
0x6838
32
true
MDI_CONTROL
The register manual only mentions this in the changelog; it was removed from the manual in a previous revision. :|
0x6844
32
true
RX_CPU_EVENT_ENABLE
0x684c
32
true
VPD Attention
30
1
read-write
FAST_BOOT_PROGRAM_COUNTER
0x6894
32
true
Program Counter
This field is used by the CPU to keep track of the location of the phase 1 boot code in RX MBUF.
0
31
read-write
Enable
This bit is used by the CPU to keep track of whether or not there is valid phase 1 boot code stored in the RX MBUF. If the bit is set, then RXMBUF contains valid boot code. Otherwise, it is assumed that RXMBUF does not contain valid boot code.
31
1
read-write
EXPANSION_ROM_ADDR
Expansion ROM base address, expect to be d- word aligned.
0x68ec
32
true
68F0
0x68f0
32
true
EAV_REF_CLOCK_CONTROL
0x6908
32
true
Timesync GPIO Mapping
The MAC/Port dedicated TimeSync_GPIO pin is mapped via this field
16
2
read-write
Snap-Shot[0]
0
Snap-Shot[1]
1
Time Watchdog[0]
2
Time Watchdog[1]
3
APE GPIO 0 Mapping
APE_GPIO[0] pin is mapped to 1588 input/ output via this field
18
3
read-write
Not Used
0
Snap-Shot[0]
4
Snap-Shot[1]
5
Time Watchdog[0]
6
Time Watchdog[1]
7
APE GPIO 1 Mapping
APE_GPIO[1] pin is mapped to 1588 input/ output via this field
21
3
read-write
Not Used
0
Snap-Shot[0]
4
Snap-Shot[1]
5
Time Watchdog[0]
6
Time Watchdog[1]
7
APE GPIO 2 Mapping
APE_GPIO[2] pin is mapped to 1588 input/ output via this field
24
3
read-write
Not Used
0
Snap-Shot[0]
4
Snap-Shot[1]
5
Time Watchdog[0]
6
Time Watchdog[1]
7
APE GPIO 3 Mapping
APE_GPIO[3] pin is mapped to 1588 input/ output via this field
27
3
read-write
Not Used
0
Snap-Shot[0]
4
Snap-Shot[1]
5
Time Watchdog[0]
6
Time Watchdog[1]
7
7C04
PCIe Transaction Cfg
0x7c04
32
true
8