meklort <PROJECT> Register Definitions 1.0 APE Device APE Registers APE Device APE Registers APE> 0xC0010000 register false MODE More of these bits can be found in diagnostic utilities, but they don't seem too interesting. 0x0 32 true Reset Used to reset the APE block. 0 1 read-write Halt APE is halted if set. Setting then unsetting this bit resets the APE to its reset vector, etc. 1 1 read-write Fast Boot Can be used to boot from RAM instead of NVM. Takes a full APE image with section headers, etc. so you still need to form a proper image. 2 1 read-write Host Diag 3 1 read-write Event 1 Used to signal the APE that an event from the host is ready for processing in SHM. 5 1 read-write Event 2 6 1 read-write GRCint 7 1 read-write Swap ATB dword 9 1 read-write Swap ARB dword 11 1 read-write Channel 0 Enable 14 1 read-write Channel 2 Enable 15 1 read-write Memory ECC 18 1 read-write ICode PIP Rd Disable 19 1 read-write Channel 1 Enable 30 1 read-write Channel 3 Enable 31 1 read-write STATUS 0x4 32 true PCIe Reset 0 1 read-write Port 0 GRC Reset 1 1 read-write NVRAM Control Reset 3 1 read-write Port 0 D State Indicates port is in D3 if set, otherwise the port is in D0-D2. 4 1 read-write Boot Mode 5 1 read-write NVRAM 0 Fast 1 Port 1 GRC Reset 7 1 read-write Port 1 D State Indicates port is in D3 if set, otherwise the port is in D0-D2. 9 1 read-write Boot Status B 24 4 read-write Prog 0 0 Prog 1 1 BPC Enter 2 Decode 3 Read NVRAM Header 4 Read Code 5 Jump 6 Prog 7 7 BPC Success 8 Boot Status A 28 4 read-write None 0 NMI Exception 1 Fault Exception 2 Memory Check 3 Unknown 4 4 Romloader Disabled 5 Magic Number 6 APE Init Code 7 Header Checksum 8 APE Header 9 Image Checksum 10 NVRAM Checksum 11 Invalid Type 12 ROM Loader Checksum 13 Invalid Unzip Len 14 Unknown F 15 GPIO_MESSAGE Related to APE fastboot. In that case the value of it is an APE memory address in the code region. If Fast Boot is set, and the low two bits of this are not 0b10, ROM hangs (you have to OR 0x2 into the address). Otherwise, they are masked off and the resulting value is used as the reset vector. The resulting value is also stored in this register (i.e., the low two bits are cleared). 0x8 32 true EVENT 0xc 32 true 1 Event 1 0 1 read-write RXBufOffset Func0 RXBufOffset This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. The fields are block numbers (block size 128 bytes). 0x14 32 true Tail 0 12 read-write Head 12 12 read-write To Host 24 1 read-write IP Frag 25 1 read-write Count 26 4 read-write Valid 30 1 read-write Finished 31 1 read-write RXBufOffset Func1 RXBufOffset This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. 0x18 TX To Net Doorbell Func0 TX To Net Doorbell Written on APE TX to network after filling 0xA002 buffer with packet. 0x1c 32 true Tail 0 12 read-write Head 12 12 read-write Length 24 4 read-write TX Queue Full 28 1 read-write TX State0 TX State APE TX Status Port0 0x20 32 true Tail 0 12 read-write Head 12 12 read-write TXError 24 1 read-write Error Code 25 3 read-write Frame Length Mismatch 1 MBuf Count Mismatch 2 TX State1 TX State APE TX State Port1 0x24 MODE_2 Expansion for MODE 0x2c 32 true Channel 0 Enable 14 1 read-write Channel 2 Enable 15 1 read-write Channel 1 Enable 30 1 read-write Channel 3 Enable 31 1 read-write STATUS_2 0x30 32 true Port 2 GRC Reset 1 1 read-write Port 2 D State Indicates port is in D3 if set, otherwise the port is in D0-D2. 2 1 read-write Port 3 GRC Reset Indicates port is in D3 if set, otherwise the port is in D0-D2. 7 1 read-write Port 3 D State 8 1 read-write LOCK_GRANT__OBSOLETE_ See 0x4c 32 true RX Pool Mode Status 0 RX Pool Mode Status> 0x78 32 true Halt 0 1 read-write Halt Done 1 1 read-write Enable 2 1 read-write Empty 4 1 read-write Error 5 1 read-write Reset 6 1 read-write Full Count 8 16 read-write RX Pool Mode Status 1 0x7c RX Pool Mode Status RX Pool Retire 0 RX Pool Retire Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. 0x80 32 true Tail 0 12 read-write Head 12 12 read-write Retire 24 1 read-write State 25 2 read-write Processing 0 Retired OK 1 Error: Full 2 Error: In Halt 3 Count 27 4 read-write RX Pool Free Pointer 0 RX Pool Free Pointer 0x84 32 true Tail 0 12 read-write Head 12 12 read-write Free Count 24 7 read-write Max 0x7f RX Pool Retire 1 RX Pool Retire Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. 0x88 TX To Net Pool Mode Status 0 TX To Net Pool Mode Status 0x8c 32 true Halt 0 1 read-write Halt Done 1 1 read-write Enable Must set Enable before the APE TX To Net Buffer Allocator will work. 2 1 read-write Empty 4 1 read-write Error 5 1 read-write Reset 6 1 read-write Full Count 8 16 read-write TX To Net Buffer Allocator 0 TX To Net Buffer Allocator 0x90 32 true Index 0 12 read-write Block Size 128 Request Allocation 12 1 read-write State 13 2 read-write Processing 0 Allocation OK 1 Error: Empty 2 Error: In Halt 3 TX To Net Buffer Return 0 TX To Net Buffer Return 0x94 32 true TX To Net Buffer Ring 0 TX To Net Buffer Ring 0x98 32 true Tail 0 12 read-write Head 12 12 read-write Free 24 6 read-write Max 0x3f RX Pool Free Pointer 1 RX Pool Free Pointer 0x9c Tick 1MHz Unknown, monotonically increasing value. Increases at a rate of 1MHz. 0xa8 32 true Tick 1KHz Unknown, monotonically increasing value. Increases at a rate of 1KHz. 0xac 32 true Tick 10Hz Unknown, monotonically increasing value. Increases at a rate of 10Hz. 0xb0 32 true GPIO 0xb8 32 true PIN0 Unknown 0 1 read-write PIN1 Unknown 1 1 read-write PIN2 Unknown 2 1 read-write PIN3 Unknown 3 1 read-write PIN0 Unknown Out 8 1 read-write PIN1 Unknown Out 9 1 read-write PIN2 Unknown Out 10 1 read-write PIN3 Unknown Out 11 1 read-write PIN0 Mode Output 16 1 read-write PIN1 Mode Output 17 1 read-write PIN2 Mode Output 18 1 read-write PIN3 Mode Output 19 1 read-write GINT TODO: See diag for field info. 0xbc 32 true OTP_CONTROL 0xe8 32 true Start 0 1 read-write Init 0x3 0x1 read-write Prog Enable 21 1 read-write OTP_STATUS 0xec 32 true Command Done 0 1 read-write OTP_ADDR 0xf0 32 true Address 0 31 read-write CPU Enable 31 1 read-write OTP_READ_DATA 0xf8 32 true CPU Status Seems CPU control related. 0x108 32 true Status 0 4 read-write Running 0 Halted 1 Locked Out 2 Sleeping 3 Deep Sleep 4 Interrupt Pending 8 Interrupt Entry 9 Interrupt Exit 10 Interrupt Return 11 Active Interrupt 24 8 read-write TX To Net Pool Mode Status 1 TX To Net Pool Mode Status 0x110 TX To Net Buffer Allocator 1 TX To Net Buffer Allocator 0x114 TX To Net Buffer Return 1 TX To Net Buffer Return 0x118 TX To Net Buffer Ring 1 TX To Net Buffer Ring 0x11c TX To Net Doorbell Func1 TX To Net Doorbell Written on APE TX to network after filling 0xA002 buffer with packet. 0x120 RXBufOffset Func2 RXBufOffset This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. 0x200 TX To Net Doorbell Func2 TX To Net Doorbell Written on APE TX to network after filling 0xA002 buffer with packet. 0x204 TX State2 TX State APE TX State Port2 0x208 RX Pool Mode Status 2 0x214 RX Pool Mode Status> RX Pool Retire 2 RX Pool Retire Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. 0x218 RX Pool Free Pointer 2 RX Pool Free Pointer 0x21c TX To Net Pool Mode Status 2 TX To Net Pool Mode Status 0x220 TX To Net Buffer Allocator 2 TX To Net Buffer Allocator 0x224 TX To Net Buffer Return 2 TX To Net Buffer Return 0x228 TX To Net Buffer Ring 2 TX To Net Buffer Ring 0x22c RXBufOffset Func3 RXBufOffset This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. 0x300 TX To Net Doorbell Func3 TX To Net Doorbell Written on APE TX to network after filling 0xA002 buffer with packet. 0x304 TX State3 TX State APE TX State Port3 0x308 RX Pool Mode Status 3 0x314 RX Pool Mode Status> RX Pool Retire 3 RX Pool Retire Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. 0x318 RX Pool Free Pointer 3 RX Pool Free Pointer 0x31c TX To Net Pool Mode Status 3 TX To Net Pool Mode Status 0x320 TX To Net Buffer Allocator 3 TX To Net Buffer Allocator 0x324 TX To Net Buffer Return 3 TX To Net Buffer Return 0x328 TX To Net Buffer Ring 3 TX To Net Buffer Ring 0x32c 8 APE_PERI Device APE Peripheral Registers APE_PERI Device APE Peripheral Registers APE_PERI> 0xC0018000 BMC to NC RX Status 0x300 32 true New 0 1 read-write Bad 1 1 read-write Passthru 2 1 read-write SA Hit Valid 3 1 read-write VLAN 4 1 read-write Underflow 5 1 read-write EndOfFrame 6 1 read-write In Progress 7 1 read-write Flushing 8 1 read-write Flush Done 9 1 read-write SA hit 10 5 read-write Packet Length 16 11 read-write BMC to NC Source MAC High Upper four bytes of the MAC 0x304 32 true High Upper four bytes of the MAC 0 32 read-write BMC to NC Source MAC Low Lower two bytes of the MAC 0x308 32 true Low Lower two bytes of the MAC 16 16 read-write BMC to NC Source MAC Match 0 High Upper four bytes of the MAC 0x30c 32 true High Upper four bytes of the MAC 0 32 read-write BMC to NC Source MAC Match 0 Low Lower two bytes of the MAC 0x310 32 true Low Lower two bytes of the MAC 16 16 read-write BMC to NC Source MAC Match 1 High Upper four bytes of the MAC 0x314 32 true High Upper four bytes of the MAC 0 32 read-write BMC to NC Source MAC Match 1 Low Lower two bytes of the MAC 0x318 32 true Low Lower two bytes of the MAC 16 16 read-write BMC to NC Source MAC Match 2 High Upper four bytes of the MAC 0x31c 32 true High Upper four bytes of the MAC 0 32 read-write BMC to NC Source MAC Match 2 Low Lower two bytes of the MAC 0x320 32 true Low Lower two bytes of the MAC 16 16 read-write BMC to NC Source MAC Match 3 High Upper four bytes of the MAC 0x324 32 true High Upper four bytes of the MAC 0 32 read-write BMC to NC Source MAC Match 3 Low Lower two bytes of the MAC 0x328 32 true Low Lower two bytes of the MAC 16 16 read-write BMC to NC Source MAC Match 4 High Upper four bytes of the MAC 0x32c 32 true High Upper four bytes of the MAC 0 32 read-write BMC to NC Source MAC Match 4 Low Lower two bytes of the MAC 0x330 32 true Low Lower two bytes of the MAC 16 16 read-write BMC to NC Source MAC Match 5 High Upper four bytes of the MAC 0x334 32 true High Upper four bytes of the MAC 0 32 read-write BMC to NC Source MAC Match 5 Low Lower two bytes of the MAC 0x338 32 true Low Lower two bytes of the MAC 16 16 read-write BMC to NC Source MAC Match 6 High Upper four bytes of the MAC 0x33c 32 true High Upper four bytes of the MAC 0 32 read-write BMC to NC Source MAC Match 6 Low Lower two bytes of the MAC 0x340 32 true Low Lower two bytes of the MAC 16 16 read-write BMC to NC Source MAC Match 7 High Upper four bytes of the MAC 0x344 32 true High Upper four bytes of the MAC 0 32 read-write BMC to NC Source MAC Match 7 Low Lower two bytes of the MAC 0x348 32 true Low Lower two bytes of the MAC 16 16 read-write BMC to NC RX VLAN 0x34c 32 true VLAN 16 16 read-write BMC to NC Read Buffer 0x350 32 true BMC to NC RX Control 0x354 32 true HWM 0 11 read-write Flow Control 24 1 read-write Reset Bad Or'd after receiving Status.Bad frame 25 1 read-write BMC to NC RX Status 1 0x358 32 true BMC to NC RX Status 2 0x35c 32 true BMC to NC TX Status 0x370 32 true Underrun 0 1 read-write Hit LWM 1 1 read-write Empty 2 1 read-write Full 3 1 read-write Last Full Count 4 1 read-write In Fifo 16 11 read-write BMC to NC TX Control 0x374 32 true Underrun 0 1 read-write Hit LWM 1 1 read-write Empty 2 1 read-write Full 3 1 read-write Last Full Count 4 1 read-write Store Forward 8 1 read-write Poison 9 1 read-write XOFF 10 1 read-write Last Byte Count 11 2 read-write LWM 16 11 read-write BMC to NC TX Buffer 0x378 32 true BMC to NC TX Buffer Last 0x37c 32 true BMC to NC TX Status 1 0x380 32 true RMU Control 0x3a0 32 true Reset TX 0 1 read-write Reset RX 1 1 read-write Auto Drv 2 1 read-write TX Drv 3 1 read-write LPBK 4 1 read-write TX 5 1 read-write RX 6 1 read-write ARB Control 0x3a4 32 true Package ID NC-SI Package ID 0 3 read-write Disable 3 1 read-write Start 4 1 read-write Bypass 5 1 read-write ARB Bypass 6 1 read-write XOFF Disable 7 1 read-write TKNREL 8 5 read-write TO 16 16 read-write PER_LOCK_REQUEST_PHY0 This register, and the following Per Lock Request registers work the same. The tg3 driver uses 0x0000_1000 (APELOCK_PER_REQ_DRIVER) for PHY ports (or always for function 0). 0x400 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_REQUEST_GRC 0x404 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_REQUEST_PHY1 0x408 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_REQUEST_PHY2 0x40c 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_REQUEST_MEM 0x410 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_REQUEST_PHY3 0x414 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_REQUEST_PORT6 0x418 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_REQUEST_GPIO 0x41c 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_GRANT_PHY0 0x420 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_GRANT_GRC 0x424 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_GRANT_PHY1 0x428 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_GRANT_PHY2 0x42c 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_GRANT_MEM 0x430 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_GRANT_PHY3 0x434 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_GRANT_PORT6 0x438 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write PER_LOCK_GRANT_GPIO 0x43c 32 true APE 0 1 read-write Function 1 1 1 read-write Function 2 2 1 read-write Function 3 3 1 read-write Bootcode 4 1 read-write Driver 12 1 read-write 8