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* Add some initial support for pretty-printing registers.Evan Lojewski2019-02-232-0/+356
* Add checking stage1 / stage2 crc and reporting if an error exists.Evan Lojewski2019-02-231-1/+1
* Add bootcode location to ipxact and regenerate.Evan Lojewski2019-02-231-5/+17
* Add generation of various memoriesEvan Lojewski2019-02-182-0/+2
* Update MII init code to match latest description for port 0.Evan Lojewski2019-02-182-1/+12
* Fix MII register addresses and impliment accessing paged blocks.Evan Lojewski2019-02-163-20/+41
* Begin adding parsing of MII registers.Evan Lojewski2019-02-163-202/+225
* Update MII library to properly read/write registers.Evan Lojewski2019-02-161-2/+6
* Clean up a few mem leaks - simulation support doesn't need to be on the heap.Evan Lojewski2019-02-141-0/+49
* Import option parsing library from https://github.com/weisslj/cpp-optparseEvan Lojewski2019-02-129-0/+1398
* Add an initial linker script and crt file for stage1Evan Lojewski2019-02-101-0/+4
* Update ipxact headers to include sim prototypes.Evan Lojewski2019-02-092-0/+6
* Do a manual clang-format runEvan Lojewski2019-02-097-107/+120
* Import initial bcm flash tool.Evan Lojewski2019-02-097-2/+407
* Update NVM API to use words instead of bytes.Evan Lojewski2019-02-092-13/+16
* Remove usage of ExternalProjectsEvan Lojewski2019-02-094-11/+214
* Add initial bcm5719 library with various component addresses. Ensure ASM file...Evan Lojewski2018-06-153-4/+4
* Begin enabling building for mips targets.Evan Lojewski2018-06-131-31/+8
* Begin setting up buidl system to build fw, tests, and utils.Evan Lojewski2018-05-171-0/+7
* Update cxx register wraper to only copy base register. Ensure write callback ...Evan Lojewski2018-05-153-700/+1196
* Initial source code import.Evan Lojewski2018-05-139-0/+2249
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