summaryrefslogtreecommitdiffstats
path: root/libs
Commit message (Expand)AuthorAgeFilesLines
...
* Don't include printf when building for arm/mips.Lojewski, Evan2019-05-111-0/+4
* Refactor network tx/rx code to allow a port structure allowing more ports tha...Lojewski, Evan2019-05-114-74/+151
* Update register generation to use type identifieres for port0 - 3.Lojewski, Evan2019-05-111-6/+6
* More cleanup - headers.Evan Lojewski2019-05-054-40/+34
* Run a few more files through clean-format.Evan Lojewski2019-05-055-165/+184
* First pass through clang-format.Evan Lojewski2019-05-056-109/+144
* Add retire bit to RegAPERxPoolRetire0_tEvan Lojewski2019-05-051-1/+2
* Fix Network_TX_transmitPassthroughPacket to drop the FCS word.Evan Lojewski2019-05-051-0/+7
* Fix Network_PassthroughRxPatcket to drop the FCS word.Evan Lojewski2019-05-051-12/+27
* Clean up rounding in Network/rx.cEvan Lojewski2019-05-051-4/+6
* Ignore packets of length 0.Evan Lojewski2019-05-051-1/+11
* All BMC packets to be tramsitted without an additional buffer.Evan Lojewski2019-05-042-61/+166
* Reset NCSI state on reloading firmware.Evan Lojewski2019-05-043-3/+12
* Add a passthrough rx routine bypassing any buffers.Evan Lojewski2019-05-043-5/+232
* Add prototype for NCSI_TxPacketEvan Lojewski2019-05-041-0/+2
* Cleanup DEVICE.ReceiveMacMode initializationEvan Lojewski2019-05-041-3/+6
* Fix transmitting multi-block frames to the network.Evan Lojewski2019-05-041-11/+14
* Begin cleaning up tx/rx codeEvan Lojewski2019-05-048-59/+171
* Add both a big and little endian tx routine.Evan Lojewski2019-05-031-48/+99
* Clean up be32toh routine in tx.c slightly.Evan Lojewski2019-05-031-8/+5
* Update TX/RX sim generationEvan Lojewski2019-05-021-1/+1
* Begin moving APE tx code from the host to the APE.Evan Lojewski2019-05-025-0/+1130
* Add additional packet geenration checking - test the IID, channel, package, a...Evan Lojewski2019-04-281-0/+2
* Update tx port ipxact definition and regen.Evan Lojewski2019-04-281-4/+4
* Begin adding support for testing the NCSI library.Evan Lojewski2019-04-284-0/+361
* Add RX queue information and fix symbols sizes.Evan Lojewski2019-04-201-7/+7
* Begin adding support for sending the link status response.Evan Lojewski2019-04-162-28/+239
* Add handling for the AEN Enable command.Evan Lojewski2019-04-142-40/+67
* Begin adding support for setting ape statistics in the SHM region.Evan Lojewski2019-04-143-61/+138
* WIP: check in initial NC-SI handler.Evan Lojewski2019-04-135-0/+829
* Split APE register region into two - mapped in different places based on host...Evan Lojewski2019-04-133-26/+34
* Regenerate header with properly component offsets.Evan Lojewski2019-04-092-363/+55
* Update APE registers to exist in the APE code.Evan Lojewski2019-04-091-0/+4
* Add initial indeirect APE read support for the host cxxsim code.Evan Lojewski2019-04-062-2/+2
* Clean up CXXregister code slightly to prepare for initial APE-indirect access...Evan Lojewski2019-04-062-12/+443
* Begin adding registers for APE tx/rx from netwokr.Evan Lojewski2019-04-041-0/+48
* Regenerate headers + simulation code to allow arbitrary read/writes from the ...Evan Lojewski2019-04-032-0/+24
* Updated APE symbol sizes.Evan Lojewski2019-04-011-3/+3
* Add arm versions of the MII and APE libraries.Evan Lojewski2019-03-302-0/+10
* nvram: Fix prototype for NVRam_crc to mark input buffer as constant.Evan Lojewski2019-03-302-2/+2
* Add initial compression/decompression library.Evan Lojewski2019-03-305-0/+640
* Move elfio to a standalone library.Evan Lojewski2019-03-30214-0/+24982
* Split APE SHM out of the APE register area. Instantiate 4x in the APE, one pe...Evan Lojewski2019-03-232-0/+20
* Split out DEVICE registers and add 4x instances for the APE.Evan Lojewski2019-03-231-0/+16
* Start adding in APE register generation.Evan Lojewski2019-03-232-2/+57
* SPlit NVM registers out of bcm5719 xml.Evan Lojewski2019-03-234-14/+24
* Fix the APE library to release locks properly.Evan Lojewski2019-03-161-18/+18
* Update APE library to use new register definitions and add a releaseAllLocks(...Evan Lojewski2019-03-162-13/+39
* Add initial support for reading/writing shadowed MII registers. Untested.Evan Lojewski2019-03-131-2/+131
* Add additional shadowed MII regisers and APE registers.Evan Lojewski2019-03-132-72/+1834
OpenPOWER on IntegriCloud