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* Add missing header.Evan Lojewski2019-04-061-0/+514
* Add initial indeirect APE read support for the host cxxsim code.Evan Lojewski2019-04-0610-19/+15
* Clean up CXXregister code slightly to prepare for initial APE-indirect access...Evan Lojewski2019-04-0610-60/+5219
* Add initial ape loade rbinary to allow the bcmregtool to read/write arbitrary...Evan Lojewski2019-04-032-4/+252
* Regenerate headers + simulation code to allow arbitrary read/writes from the ...Evan Lojewski2019-04-0310-0/+120
* Check in missing APE_SHM.h file.Evan Lojewski2019-04-011-0/+1908
* Fix NVIC register definitions.Evan Lojewski2019-04-011-26/+22
* Update ipxact definition an regen.Evan Lojewski2019-04-011-1/+24
* Update ape header to work with new utilities.Evan Lojewski2019-03-301-2/+5
* Update APE section flags.Evan Lojewski2019-03-301-0/+2
* Check in missing SHM file.Evan Lojewski2019-03-261-0/+1908
* Add ape format information.Evan Lojewski2019-03-241-1/+33
* Split APE SHM out of the APE register area. Instantiate 4x in the APE, one pe...Evan Lojewski2019-03-231-1808/+1
* Start adding in APE register generation.Evan Lojewski2019-03-231-0/+2354
* SPlit NVM registers out of bcm5719 xml.Evan Lojewski2019-03-231-12/+12
* Update ipxact to include remaining lock bits for the APE.Evan Lojewski2019-03-161-0/+95
* Update ipxact to include addtional APE registers.Evan Lojewski2019-03-162-18/+2491
* Add som additional attention register information from the manual.Evan Lojewski2019-03-161-3/+95
* Add additional shadowed MII regisers and APE registers.Evan Lojewski2019-03-132-93/+458
* Add in additional NVM configuration registers to the ipxact and regenerate.Evan Lojewski2019-03-111-2/+46
* REmove packed keywords from NVRamContents - causes MIPS compiler to attemp mi...Evan Lojewski2019-02-241-11/+12
* Fix MiscellaneousHostControl definitionEvan Lojewski2019-02-231-16/+12
* Fix padding geneartion in registers.Evan Lojewski2019-02-233-88/+36
* Add updated bitmap definitions when compiling for big endian.Evan Lojewski2019-02-233-0/+1445
* Update stage1 to load stage2 and report the status.Evan Lojewski2019-02-232-0/+70
* Add some initial support for pretty-printing registers.Evan Lojewski2019-02-233-0/+816
* Add checking stage1 / stage2 crc and reporting if an error exists.Evan Lojewski2019-02-231-0/+6
* Add bootcode location to ipxact and regenerate.Evan Lojewski2019-02-231-0/+104
* Add additional init-from-NVM code.Evan Lojewski2019-02-191-9/+19
* Add generation of various memoriesEvan Lojewski2019-02-186-0/+315
* Fix parsing of the power budget from nvm.Evan Lojewski2019-02-161-114/+506
* Add missing register definitions for power budget 1-7Evan Lojewski2019-02-161-0/+203
* Update nvrma format to more closely match ortega spec.Evan Lojewski2019-02-111-126/+100
* Add an iniital WIP version of stage1 main.Evan Lojewski2019-02-111-3/+1
* Update ipxact headers to include sim prototypes.Evan Lojewski2019-02-093-0/+9
* Import initial bcm flash tool.Evan Lojewski2019-02-092-0/+274
* Add initial bcm5719 library with various component addresses. Ensure ASM file...Evan Lojewski2018-06-153-6/+3
* Begin enabling building for mips targets.Evan Lojewski2018-06-133-3/+86
* Update cxx register wraper to only copy base register. Ensure write callback ...Evan Lojewski2018-05-153-0/+6021
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