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-rw-r--r--include/APE_APE.h172
-rw-r--r--include/APE_APE_PERI.h118
-rw-r--r--include/APE_DEVICE.h1014
-rw-r--r--include/APE_DEVICE1.h6
-rw-r--r--include/APE_DEVICE2.h6
-rw-r--r--include/APE_DEVICE3.h6
-rw-r--r--include/APE_FILTERS0.h4
-rw-r--r--include/APE_NVIC.h116
-rw-r--r--include/APE_SHM.h102
-rw-r--r--include/APE_SHM_CHANNEL0.h28
-rw-r--r--include/bcm5719_APE.h172
-rw-r--r--include/bcm5719_APE_PERI.h118
-rw-r--r--include/bcm5719_DEVICE.h1014
-rw-r--r--include/bcm5719_GEN.h40
-rw-r--r--include/bcm5719_SHM.h102
-rw-r--r--include/bcm5719_SHM_CHANNEL0.h28
16 files changed, 2880 insertions, 166 deletions
diff --git a/include/APE_APE.h b/include/APE_APE.h
index 0ce97e1..9c6857a 100644
--- a/include/APE_APE.h
+++ b/include/APE_APE.h
@@ -1089,6 +1089,74 @@ typedef register_container RegAPERxPoolRetire_t {
#endif /* CXX_SIMULATOR */
} RegAPERxPoolRetire_t;
+#define REG_APE_RX_POOL_FREE_POINTER_0 ((volatile APE_APE_H_uint32_t*)0x60200084) /* */
+#define APE_RX_POOL_FREE_POINTER_0_TAIL_SHIFT 0u
+#define APE_RX_POOL_FREE_POINTER_0_TAIL_MASK 0xfffu
+#define GET_APE_RX_POOL_FREE_POINTER_0_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u)
+#define SET_APE_RX_POOL_FREE_POINTER_0_TAIL(__val__) (((__val__) << 0u) & 0xfffu)
+#define APE_RX_POOL_FREE_POINTER_0_HEAD_SHIFT 12u
+#define APE_RX_POOL_FREE_POINTER_0_HEAD_MASK 0xfff000u
+#define GET_APE_RX_POOL_FREE_POINTER_0_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u)
+#define SET_APE_RX_POOL_FREE_POINTER_0_HEAD(__val__) (((__val__) << 12u) & 0xfff000u)
+#define APE_RX_POOL_FREE_POINTER_0_FREE_COUNT_SHIFT 24u
+#define APE_RX_POOL_FREE_POINTER_0_FREE_COUNT_MASK 0x3f000000u
+#define GET_APE_RX_POOL_FREE_POINTER_0_FREE_COUNT(__reg__) (((__reg__) & 0x3f000000) >> 24u)
+#define SET_APE_RX_POOL_FREE_POINTER_0_FREE_COUNT(__val__) (((__val__) << 24u) & 0x3f000000u)
+
+/** @brief Register definition for @ref APE_t.RxPoolFreePointer0. */
+typedef register_container RegAPERxPoolFreePointer_t {
+ /** @brief 32bit direct register access. */
+ APE_APE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(APE_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief */
+ BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12)
+ /** @brief */
+ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12)
+ /** @brief */
+ BITFIELD_MEMBER(APE_APE_H_uint32_t, FreeCount, 24, 6)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_30, 30, 2)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_30, 30, 2)
+ /** @brief */
+ BITFIELD_MEMBER(APE_APE_H_uint32_t, FreeCount, 24, 6)
+ /** @brief */
+ BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12)
+ /** @brief */
+ BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(APE_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "RxPoolFreePointer0"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegAPERxPoolFreePointer_t()
+ {
+ /** @brief constructor for @ref APE_t.RxPoolFreePointer0. */
+ r32.setName("RxPoolFreePointer0");
+ bits.Tail.setBaseRegister(&r32);
+ bits.Tail.setName("Tail");
+ bits.Head.setBaseRegister(&r32);
+ bits.Head.setName("Head");
+ bits.FreeCount.setBaseRegister(&r32);
+ bits.FreeCount.setName("FreeCount");
+ }
+ RegAPERxPoolFreePointer_t& operator=(const RegAPERxPoolFreePointer_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegAPERxPoolFreePointer_t;
+
#define REG_APE_RX_POOL_RETIRE_1 ((volatile APE_APE_H_uint32_t*)0x60200088) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
#define REG_APE_TX_TO_NET_POOL_MODE_STATUS_0 ((volatile APE_APE_H_uint32_t*)0x6020008c) /* */
#define APE_TX_TO_NET_POOL_MODE_STATUS_0_HALT_SHIFT 0u
@@ -1338,6 +1406,7 @@ typedef register_container RegAPETxToNetBufferRing_t {
#endif /* CXX_SIMULATOR */
} RegAPETxToNetBufferRing_t;
+#define REG_APE_RX_POOL_FREE_POINTER_1 ((volatile APE_APE_H_uint32_t*)0x6020009c) /* */
#define REG_APE_TICK_1MHZ ((volatile APE_APE_H_uint32_t*)0x602000a8) /* Unknown, monotonically increasing value. Increases at a rate of 1MHz. */
/** @brief Register definition for @ref APE_t.Tick1mhz. */
typedef register_container RegAPETick1mhz_t {
@@ -1894,6 +1963,7 @@ typedef register_container RegAPECpuStatus_t {
#define REG_APE_TX_TO_NET_DOORBELL_FUNC2 ((volatile APE_APE_H_uint32_t*)0x60200204) /* Written on APE TX to network after filling 0xA002 buffer with packet. */
#define REG_APE_RX_POOL_MODE_STATUS_2 ((volatile APE_APE_H_uint32_t*)0x60200214) /* */
#define REG_APE_RX_POOL_RETIRE_2 ((volatile APE_APE_H_uint32_t*)0x60200218) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
+#define REG_APE_RX_POOL_FREE_POINTER_2 ((volatile APE_APE_H_uint32_t*)0x6020021c) /* */
#define REG_APE_TX_TO_NET_POOL_MODE_STATUS_2 ((volatile APE_APE_H_uint32_t*)0x60200220) /* */
#define REG_APE_TX_TO_NET_BUFFER_ALLOCATOR_2 ((volatile APE_APE_H_uint32_t*)0x60200224) /* */
#define REG_APE_TX_TO_NET_BUFFER_RETURN_2 ((volatile APE_APE_H_uint32_t*)0x60200228) /* */
@@ -1902,6 +1972,7 @@ typedef register_container RegAPECpuStatus_t {
#define REG_APE_TX_TO_NET_DOORBELL_FUNC3 ((volatile APE_APE_H_uint32_t*)0x60200304) /* Written on APE TX to network after filling 0xA002 buffer with packet. */
#define REG_APE_RX_POOL_MODE_STATUS_3 ((volatile APE_APE_H_uint32_t*)0x60200314) /* */
#define REG_APE_RX_POOL_RETIRE_3 ((volatile APE_APE_H_uint32_t*)0x60200318) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
+#define REG_APE_RX_POOL_FREE_POINTER_3 ((volatile APE_APE_H_uint32_t*)0x6020031c) /* */
#define REG_APE_TX_TO_NET_POOL_MODE_STATUS_3 ((volatile APE_APE_H_uint32_t*)0x60200320) /* */
#define REG_APE_TX_TO_NET_BUFFER_ALLOCATOR_3 ((volatile APE_APE_H_uint32_t*)0x60200324) /* */
#define REG_APE_TX_TO_NET_BUFFER_RETURN_3 ((volatile APE_APE_H_uint32_t*)0x60200328) /* */
@@ -1962,8 +2033,8 @@ typedef struct APE_t {
/** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
RegAPERxPoolRetire_t RxPoolRetire0;
- /** @brief Reserved bytes to pad out data structure. */
- APE_APE_H_uint32_t reserved_132[1];
+ /** @brief */
+ RegAPERxPoolFreePointer_t RxPoolFreePointer0;
/** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
RegAPERxPoolRetire_t RxPoolRetire1;
@@ -1980,8 +2051,11 @@ typedef struct APE_t {
/** @brief */
RegAPETxToNetBufferRing_t TxToNetBufferRing0;
+ /** @brief */
+ RegAPERxPoolFreePointer_t RxPoolFreePointer1;
+
/** @brief Reserved bytes to pad out data structure. */
- APE_APE_H_uint32_t reserved_156[3];
+ APE_APE_H_uint32_t reserved_160[2];
/** @brief Unknown, monotonically increasing value. Increases at a rate of 1MHz. */
RegAPETick1mhz_t Tick1mhz;
@@ -2061,8 +2135,8 @@ typedef struct APE_t {
/** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
RegAPERxPoolRetire_t RxPoolRetire2;
- /** @brief Reserved bytes to pad out data structure. */
- APE_APE_H_uint32_t reserved_540[1];
+ /** @brief */
+ RegAPERxPoolFreePointer_t RxPoolFreePointer2;
/** @brief */
RegAPETxToNetPoolModeStatus_t TxToNetPoolModeStatus2;
@@ -2094,8 +2168,8 @@ typedef struct APE_t {
/** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
RegAPERxPoolRetire_t RxPoolRetire3;
- /** @brief Reserved bytes to pad out data structure. */
- APE_APE_H_uint32_t reserved_796[1];
+ /** @brief */
+ RegAPERxPoolFreePointer_t RxPoolFreePointer3;
/** @brief */
RegAPETxToNetPoolModeStatus_t TxToNetPoolModeStatus3;
@@ -2116,6 +2190,10 @@ typedef struct APE_t {
Status.r32.setComponentOffset(0x4);
GpioMessage.r32.setComponentOffset(0x8);
Event.r32.setComponentOffset(0xc);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_16[i].setComponentOffset(0x10 + (i * 4));
+ }
RxbufoffsetFunc0.r32.setName("RxbufoffsetFunc0");
RxbufoffsetFunc0.r32.setComponentOffset(0x14);
RxbufoffsetFunc1.r32.setName("RxbufoffsetFunc1");
@@ -2123,15 +2201,29 @@ typedef struct APE_t {
TxToNetDoorbellFunc0.r32.setName("TxToNetDoorbellFunc0");
TxToNetDoorbellFunc0.r32.setComponentOffset(0x1c);
TxState0.r32.setComponentOffset(0x20);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_36[i].setComponentOffset(0x24 + (i * 4));
+ }
Mode2.r32.setComponentOffset(0x2c);
Status2.r32.setComponentOffset(0x30);
+ for(int i = 0; i < 6; i++)
+ {
+ reserved_52[i].setComponentOffset(0x34 + (i * 4));
+ }
LockGrantObsolete.r32.setComponentOffset(0x4c);
+ for(int i = 0; i < 10; i++)
+ {
+ reserved_80[i].setComponentOffset(0x50 + (i * 4));
+ }
RxPoolModeStatus0.r32.setName("RxPoolModeStatus0");
RxPoolModeStatus0.r32.setComponentOffset(0x78);
RxPoolModeStatus1.r32.setName("RxPoolModeStatus1");
RxPoolModeStatus1.r32.setComponentOffset(0x7c);
RxPoolRetire0.r32.setName("RxPoolRetire0");
RxPoolRetire0.r32.setComponentOffset(0x80);
+ RxPoolFreePointer0.r32.setName("RxPoolFreePointer0");
+ RxPoolFreePointer0.r32.setComponentOffset(0x84);
RxPoolRetire1.r32.setName("RxPoolRetire1");
RxPoolRetire1.r32.setComponentOffset(0x88);
TxToNetPoolModeStatus0.r32.setName("TxToNetPoolModeStatus0");
@@ -2142,16 +2234,42 @@ typedef struct APE_t {
TxToNetBufferReturn0.r32.setComponentOffset(0x94);
TxToNetBufferRing0.r32.setName("TxToNetBufferRing0");
TxToNetBufferRing0.r32.setComponentOffset(0x98);
+ RxPoolFreePointer1.r32.setName("RxPoolFreePointer1");
+ RxPoolFreePointer1.r32.setComponentOffset(0x9c);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_160[i].setComponentOffset(0xa0 + (i * 4));
+ }
Tick1mhz.r32.setComponentOffset(0xa8);
Tick1khz.r32.setComponentOffset(0xac);
Tick10hz.r32.setComponentOffset(0xb0);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_180[i].setComponentOffset(0xb4 + (i * 4));
+ }
Gpio.r32.setComponentOffset(0xb8);
Gint.r32.setComponentOffset(0xbc);
+ for(int i = 0; i < 10; i++)
+ {
+ reserved_192[i].setComponentOffset(0xc0 + (i * 4));
+ }
OtpControl.r32.setComponentOffset(0xe8);
OtpStatus.r32.setComponentOffset(0xec);
OtpAddr.r32.setComponentOffset(0xf0);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_244[i].setComponentOffset(0xf4 + (i * 4));
+ }
OtpReadData.r32.setComponentOffset(0xf8);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_252[i].setComponentOffset(0xfc + (i * 4));
+ }
CpuStatus.r32.setComponentOffset(0x108);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_268[i].setComponentOffset(0x10c + (i * 4));
+ }
TxToNetPoolModeStatus1.r32.setName("TxToNetPoolModeStatus1");
TxToNetPoolModeStatus1.r32.setComponentOffset(0x110);
TxToNetBufferAllocator1.r32.setName("TxToNetBufferAllocator1");
@@ -2162,14 +2280,24 @@ typedef struct APE_t {
TxToNetBufferRing1.r32.setComponentOffset(0x11c);
TxToNetDoorbellFunc1.r32.setName("TxToNetDoorbellFunc1");
TxToNetDoorbellFunc1.r32.setComponentOffset(0x120);
+ for(int i = 0; i < 55; i++)
+ {
+ reserved_292[i].setComponentOffset(0x124 + (i * 4));
+ }
RxbufoffsetFunc2.r32.setName("RxbufoffsetFunc2");
RxbufoffsetFunc2.r32.setComponentOffset(0x200);
TxToNetDoorbellFunc2.r32.setName("TxToNetDoorbellFunc2");
TxToNetDoorbellFunc2.r32.setComponentOffset(0x204);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_520[i].setComponentOffset(0x208 + (i * 4));
+ }
RxPoolModeStatus2.r32.setName("RxPoolModeStatus2");
RxPoolModeStatus2.r32.setComponentOffset(0x214);
RxPoolRetire2.r32.setName("RxPoolRetire2");
RxPoolRetire2.r32.setComponentOffset(0x218);
+ RxPoolFreePointer2.r32.setName("RxPoolFreePointer2");
+ RxPoolFreePointer2.r32.setComponentOffset(0x21c);
TxToNetPoolModeStatus2.r32.setName("TxToNetPoolModeStatus2");
TxToNetPoolModeStatus2.r32.setComponentOffset(0x220);
TxToNetBufferAllocator2.r32.setName("TxToNetBufferAllocator2");
@@ -2178,14 +2306,24 @@ typedef struct APE_t {
TxToNetBufferReturn2.r32.setComponentOffset(0x228);
TxToNetBufferRing2.r32.setName("TxToNetBufferRing2");
TxToNetBufferRing2.r32.setComponentOffset(0x22c);
+ for(int i = 0; i < 52; i++)
+ {
+ reserved_560[i].setComponentOffset(0x230 + (i * 4));
+ }
RxbufoffsetFunc3.r32.setName("RxbufoffsetFunc3");
RxbufoffsetFunc3.r32.setComponentOffset(0x300);
TxToNetDoorbellFunc3.r32.setName("TxToNetDoorbellFunc3");
TxToNetDoorbellFunc3.r32.setComponentOffset(0x304);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_776[i].setComponentOffset(0x308 + (i * 4));
+ }
RxPoolModeStatus3.r32.setName("RxPoolModeStatus3");
RxPoolModeStatus3.r32.setComponentOffset(0x314);
RxPoolRetire3.r32.setName("RxPoolRetire3");
RxPoolRetire3.r32.setComponentOffset(0x318);
+ RxPoolFreePointer3.r32.setName("RxPoolFreePointer3");
+ RxPoolFreePointer3.r32.setComponentOffset(0x31c);
TxToNetPoolModeStatus3.r32.setName("TxToNetPoolModeStatus3");
TxToNetPoolModeStatus3.r32.setComponentOffset(0x320);
TxToNetBufferAllocator3.r32.setName("TxToNetBufferAllocator3");
@@ -2227,18 +2365,16 @@ typedef struct APE_t {
RxPoolModeStatus0.print();
RxPoolModeStatus1.print();
RxPoolRetire0.print();
- for(int i = 0; i < 1; i++)
- {
- reserved_132[i].print();
- }
+ RxPoolFreePointer0.print();
RxPoolRetire1.print();
TxToNetPoolModeStatus0.print();
TxToNetBufferAllocator0.print();
TxToNetBufferReturn0.print();
TxToNetBufferRing0.print();
- for(int i = 0; i < 3; i++)
+ RxPoolFreePointer1.print();
+ for(int i = 0; i < 2; i++)
{
- reserved_156[i].print();
+ reserved_160[i].print();
}
Tick1mhz.print();
Tick1khz.print();
@@ -2287,10 +2423,7 @@ typedef struct APE_t {
}
RxPoolModeStatus2.print();
RxPoolRetire2.print();
- for(int i = 0; i < 1; i++)
- {
- reserved_540[i].print();
- }
+ RxPoolFreePointer2.print();
TxToNetPoolModeStatus2.print();
TxToNetBufferAllocator2.print();
TxToNetBufferReturn2.print();
@@ -2307,10 +2440,7 @@ typedef struct APE_t {
}
RxPoolModeStatus3.print();
RxPoolRetire3.print();
- for(int i = 0; i < 1; i++)
- {
- reserved_796[i].print();
- }
+ RxPoolFreePointer3.print();
TxToNetPoolModeStatus3.print();
TxToNetBufferAllocator3.print();
TxToNetBufferReturn3.print();
diff --git a/include/APE_APE_PERI.h b/include/APE_APE_PERI.h
index bd7fa8e..0eabba6 100644
--- a/include/APE_APE_PERI.h
+++ b/include/APE_APE_PERI.h
@@ -1216,6 +1216,56 @@ typedef register_container RegAPE_PERIBmcToNcRxControl_t {
#endif /* CXX_SIMULATOR */
} RegAPE_PERIBmcToNcRxControl_t;
+#define REG_APE_PERI_BMC_TO_NC_RX_STATUS_1 ((volatile APE_APE_PERI_H_uint32_t*)0x60240358) /* */
+/** @brief Register definition for @ref APE_PERI_t.BmcToNcRxStatus1. */
+typedef register_container RegAPE_PERIBmcToNcRxStatus1_t {
+ /** @brief 32bit direct register access. */
+ APE_APE_PERI_H_uint32_t r32;
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "BmcToNcRxStatus1"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegAPE_PERIBmcToNcRxStatus1_t()
+ {
+ /** @brief constructor for @ref APE_PERI_t.BmcToNcRxStatus1. */
+ r32.setName("BmcToNcRxStatus1");
+ }
+ RegAPE_PERIBmcToNcRxStatus1_t& operator=(const RegAPE_PERIBmcToNcRxStatus1_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegAPE_PERIBmcToNcRxStatus1_t;
+
+#define REG_APE_PERI_BMC_TO_NC_RX_STATUS_2 ((volatile APE_APE_PERI_H_uint32_t*)0x6024035c) /* */
+/** @brief Register definition for @ref APE_PERI_t.BmcToNcRxStatus2. */
+typedef register_container RegAPE_PERIBmcToNcRxStatus2_t {
+ /** @brief 32bit direct register access. */
+ APE_APE_PERI_H_uint32_t r32;
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "BmcToNcRxStatus2"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegAPE_PERIBmcToNcRxStatus2_t()
+ {
+ /** @brief constructor for @ref APE_PERI_t.BmcToNcRxStatus2. */
+ r32.setName("BmcToNcRxStatus2");
+ }
+ RegAPE_PERIBmcToNcRxStatus2_t& operator=(const RegAPE_PERIBmcToNcRxStatus2_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegAPE_PERIBmcToNcRxStatus2_t;
+
#define REG_APE_PERI_BMC_TO_NC_TX_STATUS ((volatile APE_APE_PERI_H_uint32_t*)0x60240370) /* */
#define APE_PERI_BMC_TO_NC_TX_STATUS_UNDERRUN_SHIFT 0u
#define APE_PERI_BMC_TO_NC_TX_STATUS_UNDERRUN_MASK 0x1u
@@ -1514,6 +1564,31 @@ typedef register_container RegAPE_PERIBmcToNcTxBufferLast_t {
#endif /* CXX_SIMULATOR */
} RegAPE_PERIBmcToNcTxBufferLast_t;
+#define REG_APE_PERI_BMC_TO_NC_TX_STATUS_1 ((volatile APE_APE_PERI_H_uint32_t*)0x60240380) /* */
+/** @brief Register definition for @ref APE_PERI_t.BmcToNcTxStatus1. */
+typedef register_container RegAPE_PERIBmcToNcTxStatus1_t {
+ /** @brief 32bit direct register access. */
+ APE_APE_PERI_H_uint32_t r32;
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "BmcToNcTxStatus1"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegAPE_PERIBmcToNcTxStatus1_t()
+ {
+ /** @brief constructor for @ref APE_PERI_t.BmcToNcTxStatus1. */
+ r32.setName("BmcToNcTxStatus1");
+ }
+ RegAPE_PERIBmcToNcTxStatus1_t& operator=(const RegAPE_PERIBmcToNcTxStatus1_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegAPE_PERIBmcToNcTxStatus1_t;
+
#define REG_APE_PERI_RMU_CONTROL ((volatile APE_APE_PERI_H_uint32_t*)0x602403a0) /* */
#define APE_PERI_RMU_CONTROL_RESET_TX_SHIFT 0u
#define APE_PERI_RMU_CONTROL_RESET_TX_MASK 0x1u
@@ -3443,8 +3518,14 @@ typedef struct APE_PERI_t {
/** @brief */
RegAPE_PERIBmcToNcRxControl_t BmcToNcRxControl;
+ /** @brief */
+ RegAPE_PERIBmcToNcRxStatus1_t BmcToNcRxStatus1;
+
+ /** @brief */
+ RegAPE_PERIBmcToNcRxStatus2_t BmcToNcRxStatus2;
+
/** @brief Reserved bytes to pad out data structure. */
- APE_APE_PERI_H_uint32_t reserved_856[6];
+ APE_APE_PERI_H_uint32_t reserved_864[4];
/** @brief */
RegAPE_PERIBmcToNcTxStatus_t BmcToNcTxStatus;
@@ -3458,8 +3539,11 @@ typedef struct APE_PERI_t {
/** @brief */
RegAPE_PERIBmcToNcTxBufferLast_t BmcToNcTxBufferLast;
+ /** @brief */
+ RegAPE_PERIBmcToNcTxStatus1_t BmcToNcTxStatus1;
+
/** @brief Reserved bytes to pad out data structure. */
- APE_APE_PERI_H_uint32_t reserved_896[8];
+ APE_APE_PERI_H_uint32_t reserved_900[7];
/** @brief */
RegAPE_PERIRmuControl_t RmuControl;
@@ -3521,6 +3605,10 @@ typedef struct APE_PERI_t {
#ifdef CXX_SIMULATOR
APE_PERI_t()
{
+ for(int i = 0; i < 192; i++)
+ {
+ reserved_0[i].setComponentOffset(0x0 + (i * 4));
+ }
BmcToNcRxStatus.r32.setComponentOffset(0x300);
BmcToNcSourceMacHigh.r32.setComponentOffset(0x304);
BmcToNcSourceMacLow.r32.setComponentOffset(0x308);
@@ -3543,12 +3631,27 @@ typedef struct APE_PERI_t {
BmcToNcRxVlan.r32.setComponentOffset(0x34c);
BmcToNcReadBuffer.r32.setComponentOffset(0x350);
BmcToNcRxControl.r32.setComponentOffset(0x354);
+ BmcToNcRxStatus1.r32.setComponentOffset(0x358);
+ BmcToNcRxStatus2.r32.setComponentOffset(0x35c);
+ for(int i = 0; i < 4; i++)
+ {
+ reserved_864[i].setComponentOffset(0x360 + (i * 4));
+ }
BmcToNcTxStatus.r32.setComponentOffset(0x370);
BmcToNcTxControl.r32.setComponentOffset(0x374);
BmcToNcTxBuffer.r32.setComponentOffset(0x378);
BmcToNcTxBufferLast.r32.setComponentOffset(0x37c);
+ BmcToNcTxStatus1.r32.setComponentOffset(0x380);
+ for(int i = 0; i < 7; i++)
+ {
+ reserved_900[i].setComponentOffset(0x384 + (i * 4));
+ }
RmuControl.r32.setComponentOffset(0x3a0);
ArbControl.r32.setComponentOffset(0x3a4);
+ for(int i = 0; i < 22; i++)
+ {
+ reserved_936[i].setComponentOffset(0x3a8 + (i * 4));
+ }
PerLockRequestPhy0.r32.setComponentOffset(0x400);
PerLockRequestGrc.r32.setComponentOffset(0x404);
PerLockRequestPhy1.r32.setComponentOffset(0x408);
@@ -3594,17 +3697,20 @@ typedef struct APE_PERI_t {
BmcToNcRxVlan.print();
BmcToNcReadBuffer.print();
BmcToNcRxControl.print();
- for(int i = 0; i < 6; i++)
+ BmcToNcRxStatus1.print();
+ BmcToNcRxStatus2.print();
+ for(int i = 0; i < 4; i++)
{
- reserved_856[i].print();
+ reserved_864[i].print();
}
BmcToNcTxStatus.print();
BmcToNcTxControl.print();
BmcToNcTxBuffer.print();
BmcToNcTxBufferLast.print();
- for(int i = 0; i < 8; i++)
+ BmcToNcTxStatus1.print();
+ for(int i = 0; i < 7; i++)
{
- reserved_896[i].print();
+ reserved_900[i].print();
}
RmuControl.print();
ArbControl.print();
diff --git a/include/APE_DEVICE.h b/include/APE_DEVICE.h
index a771b0a..8eea796 100644
--- a/include/APE_DEVICE.h
+++ b/include/APE_DEVICE.h
@@ -714,6 +714,31 @@ typedef register_container RegDEVICEApeMemoryData_t {
#endif /* CXX_SIMULATOR */
} RegDEVICEApeMemoryData_t;
+#define REG_DEVICE_160 ((volatile APE_DEVICE_H_uint32_t*)0xa0040160) /* Unknown register. */
+/** @brief Register definition for @ref DEVICE_t.160. */
+typedef register_container RegDEVICE160_t {
+ /** @brief 32bit direct register access. */
+ APE_DEVICE_H_uint32_t r32;
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "160"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegDEVICE160_t()
+ {
+ /** @brief constructor for @ref DEVICE_t.160. */
+ r32.setName("160");
+ }
+ RegDEVICE160_t& operator=(const RegDEVICE160_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegDEVICE160_t;
+
#define REG_DEVICE_EMAC_MODE ((volatile APE_DEVICE_H_uint32_t*)0xa0040400) /* */
#define DEVICE_EMAC_MODE_GLOBAL_RESET_SHIFT 0u
#define DEVICE_EMAC_MODE_GLOBAL_RESET_MASK 0x1u
@@ -1792,6 +1817,31 @@ typedef register_container RegDEVICEWolPatternCfg_t {
#endif /* CXX_SIMULATOR */
} RegDEVICEWolPatternCfg_t;
+#define REG_DEVICE_438 ((volatile APE_DEVICE_H_uint32_t*)0xa0040438) /* Unknown register. */
+/** @brief Register definition for @ref DEVICE_t.438. */
+typedef register_container RegDEVICE438_t {
+ /** @brief 32bit direct register access. */
+ APE_DEVICE_H_uint32_t r32;
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "438"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegDEVICE438_t()
+ {
+ /** @brief constructor for @ref DEVICE_t.438. */
+ r32.setName("438");
+ }
+ RegDEVICE438_t& operator=(const RegDEVICE438_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegDEVICE438_t;
+
#define REG_DEVICE_MTU_SIZE ((volatile APE_DEVICE_H_uint32_t*)0xa004043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */
#define DEVICE_MTU_SIZE_MTU_SHIFT 0u
#define DEVICE_MTU_SIZE_MTU_MASK 0xffffu
@@ -3136,6 +3186,82 @@ typedef register_container RegDEVICECpmuControl_t {
#endif /* CXX_SIMULATOR */
} RegDEVICECpmuControl_t;
+#define REG_DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE_H_uint32_t*)0xa0043604) /* */
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u
+#define GET_DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u)
+#define SET_DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u)
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_62_5MHZ 0x0u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_60_0MHZ 0x1u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_30_0MHZ 0x3u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_15_0MHZ 0x5u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_7_5MHZ 0x7u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_75MHZ 0x9u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ 0x11u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_6_25MHZ 0x13u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_125MHZ 0x15u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_1_563MHZ 0x17u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ_DIV_1_25MHZ 0x1fu
+
+
+/** @brief Register definition for @ref DEVICE_t.NoLinkPowerModeClockPolicy. */
+typedef register_container RegDEVICENoLinkPowerModeClockPolicy_t {
+ /** @brief 32bit direct register access. */
+ APE_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16)
+ /** @brief Software Controlled MAC Core Clock Speed Select. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACClockSwitch, 16, 5)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_21, 21, 11)
+ /** @brief Software Controlled MAC Core Clock Speed Select. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, MACClockSwitch, 16, 5)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(APE_DEVICE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "NoLinkPowerModeClockPolicy"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegDEVICENoLinkPowerModeClockPolicy_t()
+ {
+ /** @brief constructor for @ref DEVICE_t.NoLinkPowerModeClockPolicy. */
+ r32.setName("NoLinkPowerModeClockPolicy");
+ bits.MACClockSwitch.setBaseRegister(&r32);
+ bits.MACClockSwitch.setName("MACClockSwitch");
+ bits.MACClockSwitch.addEnum("62.5MHz", 0x0);
+ bits.MACClockSwitch.addEnum("60.0MHz", 0x1);
+ bits.MACClockSwitch.addEnum("30.0MHz", 0x3);
+ bits.MACClockSwitch.addEnum("15.0MHz", 0x5);
+ bits.MACClockSwitch.addEnum("7.5MHz", 0x7);
+ bits.MACClockSwitch.addEnum("3.75MHz", 0x9);
+ bits.MACClockSwitch.addEnum("12.5MHz", 0x11);
+ bits.MACClockSwitch.addEnum("6.25MHz", 0x13);
+ bits.MACClockSwitch.addEnum("3.125MHz", 0x15);
+ bits.MACClockSwitch.addEnum("1.563MHz", 0x17);
+ bits.MACClockSwitch.addEnum("12.5MHz/1.25MHz", 0x1f);
+
+ }
+ RegDEVICENoLinkPowerModeClockPolicy_t& operator=(const RegDEVICENoLinkPowerModeClockPolicy_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegDEVICENoLinkPowerModeClockPolicy_t;
+
#define REG_DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE_H_uint32_t*)0xa0043610) /* */
#define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u
#define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u
@@ -3540,6 +3666,14 @@ typedef register_container RegDEVICEClockStatus_t {
#define DEVICE_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_MASK 0x8000u
#define GET_DEVICE_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x8000) >> 15u)
#define SET_DEVICE_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 15u) & 0x8000u)
+#define DEVICE_GPHY_CONTROL_STATUS_PCIE_PLL_LOCK_STATUS_SHIFT 22u
+#define DEVICE_GPHY_CONTROL_STATUS_PCIE_PLL_LOCK_STATUS_MASK 0x400000u
+#define GET_DEVICE_GPHY_CONTROL_STATUS_PCIE_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x400000) >> 22u)
+#define SET_DEVICE_GPHY_CONTROL_STATUS_PCIE_PLL_LOCK_STATUS(__val__) (((__val__) << 22u) & 0x400000u)
+#define DEVICE_GPHY_CONTROL_STATUS_GPHY_PLL_LOCK_STATUS_SHIFT 23u
+#define DEVICE_GPHY_CONTROL_STATUS_GPHY_PLL_LOCK_STATUS_MASK 0x800000u
+#define GET_DEVICE_GPHY_CONTROL_STATUS_GPHY_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x800000) >> 23u)
+#define SET_DEVICE_GPHY_CONTROL_STATUS_GPHY_PLL_LOCK_STATUS(__val__) (((__val__) << 23u) & 0x800000u)
#define DEVICE_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_SHIFT 25u
#define DEVICE_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_MASK 0x2000000u
#define GET_DEVICE_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x2000000) >> 25u)
@@ -3552,6 +3686,10 @@ typedef register_container RegDEVICEClockStatus_t {
#define DEVICE_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_MASK 0x8000000u
#define GET_DEVICE_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__reg__) (((__reg__) & 0x8000000) >> 27u)
#define SET_DEVICE_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__val__) (((__val__) << 27u) & 0x8000000u)
+#define DEVICE_GPHY_CONTROL_STATUS_KEEP_NCSI_PLL_ON_DURING_LOW_POWER_MODE__SHIFT 28u
+#define DEVICE_GPHY_CONTROL_STATUS_KEEP_NCSI_PLL_ON_DURING_LOW_POWER_MODE__MASK 0x10000000u
+#define GET_DEVICE_GPHY_CONTROL_STATUS_KEEP_NCSI_PLL_ON_DURING_LOW_POWER_MODE_(__reg__) (((__reg__) & 0x10000000) >> 28u)
+#define SET_DEVICE_GPHY_CONTROL_STATUS_KEEP_NCSI_PLL_ON_DURING_LOW_POWER_MODE_(__val__) (((__val__) << 28u) & 0x10000000u)
/** @brief Register definition for @ref DEVICE_t.GphyControlStatus. */
typedef register_container RegDEVICEGphyControlStatus_t {
@@ -3568,25 +3706,35 @@ typedef register_container RegDEVICEGphyControlStatus_t {
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMUSoftwareReset, 2, 1)
/** @brief Software reset for resetting all the registers to default. */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMURegisterSoftwareReset, 3, 1)
- /** @brief */
+ /** @brief Force CPMU into Low Power State, LAN function will be powered down (GPHY, PCIE, IPSEC, APE). This bit is cleared by a rising edge of PERST_L. */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerDown, 4, 1)
/** @brief Padding */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_14_5, 5, 10)
/** @brief Setting this bit will powerdown SGMII-PCS module. */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SGMII_DIV_PCSPowerDown, 15, 1)
/** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_24_16, 16, 9)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_21_16, 16, 6)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIePLLLockStatus, 22, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPHYPLLLockStatus, 23, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_24_24, 24, 1)
/** @brief */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NCSIPLLLockStatus, 25, 1)
/** @brief */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TLPClockSource, 26, 1)
/** @brief */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SwitchingRegulatorPowerDown, 27, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, KeepNCSIPLLonduringlowpowermode_, 28, 1)
/** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_28, 28, 4)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_29, 29, 3)
#elif defined(__BIG_ENDIAN__)
/** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_28, 28, 4)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_29, 29, 3)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, KeepNCSIPLLonduringlowpowermode_, 28, 1)
/** @brief */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SwitchingRegulatorPowerDown, 27, 1)
/** @brief */
@@ -3594,12 +3742,18 @@ typedef register_container RegDEVICEGphyControlStatus_t {
/** @brief */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, NCSIPLLLockStatus, 25, 1)
/** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_24_16, 16, 9)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_24_24, 24, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPHYPLLLockStatus, 23, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PCIePLLLockStatus, 22, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_21_16, 16, 6)
/** @brief Setting this bit will powerdown SGMII-PCS module. */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, SGMII_DIV_PCSPowerDown, 15, 1)
/** @brief Padding */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_14_5, 5, 10)
- /** @brief */
+ /** @brief Force CPMU into Low Power State, LAN function will be powered down (GPHY, PCIE, IPSEC, APE). This bit is cleared by a rising edge of PERST_L. */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerDown, 4, 1)
/** @brief Software reset for resetting all the registers to default. */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, CPMURegisterSoftwareReset, 3, 1)
@@ -3636,12 +3790,18 @@ typedef register_container RegDEVICEGphyControlStatus_t {
bits.PowerDown.setName("PowerDown");
bits.SGMII_DIV_PCSPowerDown.setBaseRegister(&r32);
bits.SGMII_DIV_PCSPowerDown.setName("SGMII_DIV_PCSPowerDown");
+ bits.PCIePLLLockStatus.setBaseRegister(&r32);
+ bits.PCIePLLLockStatus.setName("PCIePLLLockStatus");
+ bits.GPHYPLLLockStatus.setBaseRegister(&r32);
+ bits.GPHYPLLLockStatus.setName("GPHYPLLLockStatus");
bits.NCSIPLLLockStatus.setBaseRegister(&r32);
bits.NCSIPLLLockStatus.setName("NCSIPLLLockStatus");
bits.TLPClockSource.setBaseRegister(&r32);
bits.TLPClockSource.setName("TLPClockSource");
bits.SwitchingRegulatorPowerDown.setBaseRegister(&r32);
bits.SwitchingRegulatorPowerDown.setName("SwitchingRegulatorPowerDown");
+ bits.KeepNCSIPLLonduringlowpowermode_.setBaseRegister(&r32);
+ bits.KeepNCSIPLLonduringlowpowermode_.setName("KeepNCSIPLLonduringlowpowermode_");
}
RegDEVICEGphyControlStatus_t& operator=(const RegDEVICEGphyControlStatus_t& other)
{
@@ -3677,10 +3837,31 @@ typedef register_container RegDEVICEChipId_t {
} RegDEVICEChipId_t;
#define REG_DEVICE_MUTEX_REQUEST ((volatile APE_DEVICE_H_uint32_t*)0xa004365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
+#define DEVICE_MUTEX_REQUEST_REQUEST_SHIFT 0u
+#define DEVICE_MUTEX_REQUEST_REQUEST_MASK 0xffffu
+#define GET_DEVICE_MUTEX_REQUEST_REQUEST(__reg__) (((__reg__) & 0xffff) >> 0u)
+#define SET_DEVICE_MUTEX_REQUEST_REQUEST(__val__) (((__val__) << 0u) & 0xffffu)
+
/** @brief Register definition for @ref DEVICE_t.MutexRequest. */
typedef register_container RegDEVICEMutexRequest_t {
/** @brief 32bit direct register access. */
APE_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Request, 0, 16)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+ /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Request, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(APE_DEVICE_H_uint32_t, bits)
#ifdef CXX_SIMULATOR
/** @brief Register name for use with the simulator. */
const char* getName(void) { return "MutexRequest"; }
@@ -3692,6 +3873,8 @@ typedef register_container RegDEVICEMutexRequest_t {
{
/** @brief constructor for @ref DEVICE_t.MutexRequest. */
r32.setName("MutexRequest");
+ bits.Request.setBaseRegister(&r32);
+ bits.Request.setName("Request");
}
RegDEVICEMutexRequest_t& operator=(const RegDEVICEMutexRequest_t& other)
{
@@ -3702,10 +3885,31 @@ typedef register_container RegDEVICEMutexRequest_t {
} RegDEVICEMutexRequest_t;
#define REG_DEVICE_MUTEX_GRANT ((volatile APE_DEVICE_H_uint32_t*)0xa0043660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
+#define DEVICE_MUTEX_GRANT_GRANTED_SHIFT 0u
+#define DEVICE_MUTEX_GRANT_GRANTED_MASK 0xffffu
+#define GET_DEVICE_MUTEX_GRANT_GRANTED(__reg__) (((__reg__) & 0xffff) >> 0u)
+#define SET_DEVICE_MUTEX_GRANT_GRANTED(__val__) (((__val__) << 0u) & 0xffffu)
+
/** @brief Register definition for @ref DEVICE_t.MutexGrant. */
typedef register_container RegDEVICEMutexGrant_t {
/** @brief 32bit direct register access. */
APE_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Granted, 0, 16)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+ /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Granted, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(APE_DEVICE_H_uint32_t, bits)
#ifdef CXX_SIMULATOR
/** @brief Register name for use with the simulator. */
const char* getName(void) { return "MutexGrant"; }
@@ -3717,6 +3921,8 @@ typedef register_container RegDEVICEMutexGrant_t {
{
/** @brief constructor for @ref DEVICE_t.MutexGrant. */
r32.setName("MutexGrant");
+ bits.Granted.setBaseRegister(&r32);
+ bits.Granted.setName("Granted");
}
RegDEVICEMutexGrant_t& operator=(const RegDEVICEMutexGrant_t& other)
{
@@ -3739,6 +3945,10 @@ typedef register_container RegDEVICEMutexGrant_t {
#define DEVICE_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_MASK 0x10u
#define GET_DEVICE_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__val__) (((__val__) << 4u) & 0x10u)
+#define DEVICE_GPHY_STRAP_APE_CM3_BIG_ENDIAN_ENABLE_SHIFT 8u
+#define DEVICE_GPHY_STRAP_APE_CM3_BIG_ENDIAN_ENABLE_MASK 0x100u
+#define GET_DEVICE_GPHY_STRAP_APE_CM3_BIG_ENDIAN_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u)
+#define SET_DEVICE_GPHY_STRAP_APE_CM3_BIG_ENDIAN_ENABLE(__val__) (((__val__) << 8u) & 0x100u)
/** @brief Register definition for @ref DEVICE_t.GphyStrap. */
typedef register_container RegDEVICEGphyStrap_t {
@@ -3756,10 +3966,18 @@ typedef register_container RegDEVICEGphyStrap_t {
/** @brief Enable ECC for rxcpu scratchpad. */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXCPUSPADECCEnable, 4, 1)
/** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_5, 5, 27)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_5, 5, 3)
+ /** @brief Enable APE CM3 Big Endian Setting */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APECM3BigEndianEnable, 8, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_9, 9, 23)
#elif defined(__BIG_ENDIAN__)
/** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_5, 5, 27)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_9, 9, 23)
+ /** @brief Enable APE CM3 Big Endian Setting */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APECM3BigEndianEnable, 8, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_5, 5, 3)
/** @brief Enable ECC for rxcpu scratchpad. */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, RXCPUSPADECCEnable, 4, 1)
/** @brief Enable RXMBUF ECC. */
@@ -3789,6 +4007,8 @@ typedef register_container RegDEVICEGphyStrap_t {
bits.RXMBUFECCEnable.setName("RXMBUFECCEnable");
bits.RXCPUSPADECCEnable.setBaseRegister(&r32);
bits.RXCPUSPADECCEnable.setName("RXCPUSPADECCEnable");
+ bits.APECM3BigEndianEnable.setBaseRegister(&r32);
+ bits.APECM3BigEndianEnable.setName("APECM3BigEndianEnable");
}
RegDEVICEGphyStrap_t& operator=(const RegDEVICEGphyStrap_t& other)
{
@@ -3798,6 +4018,166 @@ typedef register_container RegDEVICEGphyStrap_t {
#endif /* CXX_SIMULATOR */
} RegDEVICEGphyStrap_t;
+#define REG_DEVICE_FLASH_CLOCK_CONTROL_POLICY ((volatile APE_DEVICE_H_uint32_t*)0xa004366c) /* */
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH_SHIFT 0u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH_MASK 0x3u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH(__reg__) (((__reg__) & 0x3) >> 0u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH(__val__) (((__val__) << 0u) & 0x3u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH_62_5_MHZ_NCSI_DLL 0x0u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH_25_MHZ 0x3u
+
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY_SHIFT 4u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY_MASK 0x70u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY(__reg__) (((__reg__) & 0x70) >> 4u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY(__val__) (((__val__) << 4u) & 0x70u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY_62_5_MHZ_NCSI_DLL 0x0u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY_25_MHZ 0x3u
+
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY_SHIFT 8u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY_MASK 0x700u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY(__reg__) (((__reg__) & 0x700) >> 8u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY(__val__) (((__val__) << 8u) & 0x700u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY_62_5_MHZ_NCSI_DLL 0x0u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY_25_MHZ 0x3u
+
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_SHIFT 12u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_MASK 0xff000u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY(__reg__) (((__reg__) & 0xff000) >> 12u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY(__val__) (((__val__) << 12u) & 0xff000u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_4_8MHZ 0x0u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_1250_MHZ 0x1u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_125_MHZ 0xau
+
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_EAV_CLOCK_DISABLE_SHIFT 28u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_EAV_CLOCK_DISABLE_MASK 0x10000000u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_EAV_CLOCK_DISABLE(__reg__) (((__reg__) & 0x10000000) >> 28u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_EAV_CLOCK_DISABLE(__val__) (((__val__) << 28u) & 0x10000000u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_MODE_ENABLE_SHIFT 29u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_MODE_ENABLE_MASK 0x20000000u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_MODE_ENABLE(__reg__) (((__reg__) & 0x20000000) >> 29u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_MODE_ENABLE(__val__) (((__val__) << 29u) & 0x20000000u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_FLASH_CLOCK_DISABLE_SHIFT 30u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_FLASH_CLOCK_DISABLE_MASK 0x40000000u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_FLASH_CLOCK_DISABLE(__reg__) (((__reg__) & 0x40000000) >> 30u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_FLASH_CLOCK_DISABLE(__val__) (((__val__) << 30u) & 0x40000000u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_SPEED_OVERRIDE_SHIFT 30u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_SPEED_OVERRIDE_MASK 0x40000000u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_SPEED_OVERRIDE(__reg__) (((__reg__) & 0x40000000) >> 30u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_SPEED_OVERRIDE(__val__) (((__val__) << 30u) & 0x40000000u)
+
+/** @brief Register definition for @ref DEVICE_t.FlashClockControlPolicy. */
+typedef register_container RegDEVICEFlashClockControlPolicy_t {
+ /** @brief 32bit direct register access. */
+ APE_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief Software Controlled Flash Clock Speed */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, OverrideFlashClockSwitch, 0, 2)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_3_2, 2, 2)
+ /** @brief Software Controlled Flash Clock Speed */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashClockPolicy, 4, 3)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_7, 7, 1)
+ /** @brief Software Controlled Flash Clock Speed */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashIdleClockPolicy, 8, 3)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_11_11, 11, 1)
+ /** @brief Software Controlled EAV Clock Speed Select */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EAVClockPolicy, 12, 8)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_27_20, 20, 8)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ForceEAVClockDisable, 28, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashIdlemodeEnable, 29, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ForceFlashClockDisable, 30, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashClockSpeedOverride, 30, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_31, 31, 1)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_31, 31, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashClockSpeedOverride, 30, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ForceFlashClockDisable, 30, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashIdlemodeEnable, 29, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ForceEAVClockDisable, 28, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_27_20, 20, 8)
+ /** @brief Software Controlled EAV Clock Speed Select */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, EAVClockPolicy, 12, 8)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_11_11, 11, 1)
+ /** @brief Software Controlled Flash Clock Speed */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashIdleClockPolicy, 8, 3)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_7, 7, 1)
+ /** @brief Software Controlled Flash Clock Speed */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, FlashClockPolicy, 4, 3)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_3_2, 2, 2)
+ /** @brief Software Controlled Flash Clock Speed */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, OverrideFlashClockSwitch, 0, 2)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(APE_DEVICE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "FlashClockControlPolicy"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegDEVICEFlashClockControlPolicy_t()
+ {
+ /** @brief constructor for @ref DEVICE_t.FlashClockControlPolicy. */
+ r32.setName("FlashClockControlPolicy");
+ bits.OverrideFlashClockSwitch.setBaseRegister(&r32);
+ bits.OverrideFlashClockSwitch.setName("OverrideFlashClockSwitch");
+ bits.OverrideFlashClockSwitch.addEnum("62.5 MHz NCSI DLL", 0x0);
+ bits.OverrideFlashClockSwitch.addEnum("25 MHz", 0x3);
+
+ bits.FlashClockPolicy.setBaseRegister(&r32);
+ bits.FlashClockPolicy.setName("FlashClockPolicy");
+ bits.FlashClockPolicy.addEnum("62.5 MHz NCSI DLL", 0x0);
+ bits.FlashClockPolicy.addEnum("25 MHz", 0x3);
+
+ bits.FlashIdleClockPolicy.setBaseRegister(&r32);
+ bits.FlashIdleClockPolicy.setName("FlashIdleClockPolicy");
+ bits.FlashIdleClockPolicy.addEnum("62.5 MHz NCSI DLL", 0x0);
+ bits.FlashIdleClockPolicy.addEnum("25 MHz", 0x3);
+
+ bits.EAVClockPolicy.setBaseRegister(&r32);
+ bits.EAVClockPolicy.setName("EAVClockPolicy");
+ bits.EAVClockPolicy.addEnum("4.8MHz", 0x0);
+ bits.EAVClockPolicy.addEnum("1250 MHz", 0x1);
+ bits.EAVClockPolicy.addEnum("125 MHz", 0xa);
+
+ bits.ForceEAVClockDisable.setBaseRegister(&r32);
+ bits.ForceEAVClockDisable.setName("ForceEAVClockDisable");
+ bits.FlashIdlemodeEnable.setBaseRegister(&r32);
+ bits.FlashIdlemodeEnable.setName("FlashIdlemodeEnable");
+ bits.ForceFlashClockDisable.setBaseRegister(&r32);
+ bits.ForceFlashClockDisable.setName("ForceFlashClockDisable");
+ bits.FlashClockSpeedOverride.setBaseRegister(&r32);
+ bits.FlashClockSpeedOverride.setName("FlashClockSpeedOverride");
+ }
+ RegDEVICEFlashClockControlPolicy_t& operator=(const RegDEVICEFlashClockControlPolicy_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegDEVICEFlashClockControlPolicy_t;
+
#define REG_DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile APE_DEVICE_H_uint32_t*)0xa004367c) /* */
#define DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_SHIFT 4u
#define DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_MASK 0x10u
@@ -4135,10 +4515,31 @@ typedef register_container RegDEVICEEeeControl_t {
} RegDEVICEEeeControl_t;
#define REG_DEVICE_GLOBAL_MUTEX_REQUEST ((volatile APE_DEVICE_H_uint32_t*)0xa00436f0) /* */
+#define DEVICE_GLOBAL_MUTEX_REQUEST_REQUEST_SHIFT 0u
+#define DEVICE_GLOBAL_MUTEX_REQUEST_REQUEST_MASK 0xffffu
+#define GET_DEVICE_GLOBAL_MUTEX_REQUEST_REQUEST(__reg__) (((__reg__) & 0xffff) >> 0u)
+#define SET_DEVICE_GLOBAL_MUTEX_REQUEST_REQUEST(__val__) (((__val__) << 0u) & 0xffffu)
+
/** @brief Register definition for @ref DEVICE_t.GlobalMutexRequest. */
typedef register_container RegDEVICEGlobalMutexRequest_t {
/** @brief 32bit direct register access. */
APE_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Request, 0, 16)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+ /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Request, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(APE_DEVICE_H_uint32_t, bits)
#ifdef CXX_SIMULATOR
/** @brief Register name for use with the simulator. */
const char* getName(void) { return "GlobalMutexRequest"; }
@@ -4150,6 +4551,8 @@ typedef register_container RegDEVICEGlobalMutexRequest_t {
{
/** @brief constructor for @ref DEVICE_t.GlobalMutexRequest. */
r32.setName("GlobalMutexRequest");
+ bits.Request.setBaseRegister(&r32);
+ bits.Request.setName("Request");
}
RegDEVICEGlobalMutexRequest_t& operator=(const RegDEVICEGlobalMutexRequest_t& other)
{
@@ -4160,10 +4563,31 @@ typedef register_container RegDEVICEGlobalMutexRequest_t {
} RegDEVICEGlobalMutexRequest_t;
#define REG_DEVICE_GLOBAL_MUTEX_GRANT ((volatile APE_DEVICE_H_uint32_t*)0xa00436f4) /* */
+#define DEVICE_GLOBAL_MUTEX_GRANT_GRANTED_SHIFT 0u
+#define DEVICE_GLOBAL_MUTEX_GRANT_GRANTED_MASK 0xffffu
+#define GET_DEVICE_GLOBAL_MUTEX_GRANT_GRANTED(__reg__) (((__reg__) & 0xffff) >> 0u)
+#define SET_DEVICE_GLOBAL_MUTEX_GRANT_GRANTED(__val__) (((__val__) << 0u) & 0xffffu)
+
/** @brief Register definition for @ref DEVICE_t.GlobalMutexGrant. */
typedef register_container RegDEVICEGlobalMutexGrant_t {
/** @brief 32bit direct register access. */
APE_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Granted, 0, 16)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+ /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Granted, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(APE_DEVICE_H_uint32_t, bits)
#ifdef CXX_SIMULATOR
/** @brief Register name for use with the simulator. */
const char* getName(void) { return "GlobalMutexGrant"; }
@@ -4175,6 +4599,8 @@ typedef register_container RegDEVICEGlobalMutexGrant_t {
{
/** @brief constructor for @ref DEVICE_t.GlobalMutexGrant. */
r32.setName("GlobalMutexGrant");
+ bits.Granted.setBaseRegister(&r32);
+ bits.Granted.setName("Granted");
}
RegDEVICEGlobalMutexGrant_t& operator=(const RegDEVICEGlobalMutexGrant_t& other)
{
@@ -4184,6 +4610,98 @@ typedef register_container RegDEVICEGlobalMutexGrant_t {
#endif /* CXX_SIMULATOR */
} RegDEVICEGlobalMutexGrant_t;
+#define REG_DEVICE_TEMPERATURE_MONITOR_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa00436fc) /* */
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_ADC_TEST_ENABLE_SHIFT 0u
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_ADC_TEST_ENABLE_MASK 0x1u
+#define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_ADC_TEST_ENABLE(__reg__) (((__reg__) & 0x1) >> 0u)
+#define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_ADC_TEST_ENABLE(__val__) (((__val__) << 0u) & 0x1u)
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_BIAS_ADJUST_SHIFT 1u
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_BIAS_ADJUST_MASK 0xfeu
+#define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_BIAS_ADJUST(__reg__) (((__reg__) & 0xfe) >> 1u)
+#define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_BIAS_ADJUST(__val__) (((__val__) << 1u) & 0xfeu)
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_DATA_SHIFT 8u
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_DATA_MASK 0xff00u
+#define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_DATA(__reg__) (((__reg__) & 0xff00) >> 8u)
+#define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_DATA(__val__) (((__val__) << 8u) & 0xff00u)
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_HOLD_SHIFT 17u
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_HOLD_MASK 0x20000u
+#define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_HOLD(__reg__) (((__reg__) & 0x20000) >> 17u)
+#define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_HOLD(__val__) (((__val__) << 17u) & 0x20000u)
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_POWER_DOWN_SHIFT 18u
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_POWER_DOWN_MASK 0x40000u
+#define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_POWER_DOWN(__reg__) (((__reg__) & 0x40000) >> 18u)
+#define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_POWER_DOWN(__val__) (((__val__) << 18u) & 0x40000u)
+
+/** @brief Register definition for @ref DEVICE_t.TemperatureMonitorControl. */
+typedef register_container RegDEVICETemperatureMonitorControl_t {
+ /** @brief 32bit direct register access. */
+ APE_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ADCTestEnable, 0, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BiasAdjust, 1, 7)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TemperatureData, 8, 8)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_16_16, 16, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TemperatureMonitorHold, 17, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TemperatureMonitorPowerDown, 18, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_19, 19, 13)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_19, 19, 13)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TemperatureMonitorPowerDown, 18, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TemperatureMonitorHold, 17, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_16_16, 16, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TemperatureData, 8, 8)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BiasAdjust, 1, 7)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, ADCTestEnable, 0, 1)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(APE_DEVICE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "TemperatureMonitorControl"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegDEVICETemperatureMonitorControl_t()
+ {
+ /** @brief constructor for @ref DEVICE_t.TemperatureMonitorControl. */
+ r32.setName("TemperatureMonitorControl");
+ bits.ADCTestEnable.setBaseRegister(&r32);
+ bits.ADCTestEnable.setName("ADCTestEnable");
+ bits.BiasAdjust.setBaseRegister(&r32);
+ bits.BiasAdjust.setName("BiasAdjust");
+ bits.TemperatureData.setBaseRegister(&r32);
+ bits.TemperatureData.setName("TemperatureData");
+ bits.TemperatureMonitorHold.setBaseRegister(&r32);
+ bits.TemperatureMonitorHold.setName("TemperatureMonitorHold");
+ bits.TemperatureMonitorPowerDown.setBaseRegister(&r32);
+ bits.TemperatureMonitorPowerDown.setName("TemperatureMonitorPowerDown");
+ }
+ RegDEVICETemperatureMonitorControl_t& operator=(const RegDEVICETemperatureMonitorControl_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegDEVICETemperatureMonitorControl_t;
+
#define REG_DEVICE_MEMORY_ARBITER_MODE ((volatile APE_DEVICE_H_uint32_t*)0xa0044000) /* */
#define DEVICE_MEMORY_ARBITER_MODE_ENABLE_SHIFT 1u
#define DEVICE_MEMORY_ARBITER_MODE_ENABLE_MASK 0x2u
@@ -5953,6 +6471,31 @@ typedef register_container RegDEVICE64c0_t {
#endif /* CXX_SIMULATOR */
} RegDEVICE64c0_t;
+#define REG_DEVICE_64C4 ((volatile APE_DEVICE_H_uint32_t*)0xa00464c4) /* */
+/** @brief Register definition for @ref DEVICE_t.64c4. */
+typedef register_container RegDEVICE64c4_t {
+ /** @brief 32bit direct register access. */
+ APE_DEVICE_H_uint32_t r32;
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "64c4"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegDEVICE64c4_t()
+ {
+ /** @brief constructor for @ref DEVICE_t.64c4. */
+ r32.setName("64c4");
+ }
+ RegDEVICE64c4_t& operator=(const RegDEVICE64c4_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegDEVICE64c4_t;
+
#define REG_DEVICE_64C8 ((volatile APE_DEVICE_H_uint32_t*)0xa00464c8) /* */
/** @brief Register definition for @ref DEVICE_t.64c8. */
typedef register_container RegDEVICE64c8_t {
@@ -7249,6 +7792,10 @@ typedef register_container RegDEVICE65f4_t {
} RegDEVICE65f4_t;
#define REG_DEVICE_GRC_MODE_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa0046800) /* */
+#define DEVICE_GRC_MODE_CONTROL_HOST_STACK_UP_SHIFT 16u
+#define DEVICE_GRC_MODE_CONTROL_HOST_STACK_UP_MASK 0x10000u
+#define GET_DEVICE_GRC_MODE_CONTROL_HOST_STACK_UP(__reg__) (((__reg__) & 0x10000) >> 16u)
+#define SET_DEVICE_GRC_MODE_CONTROL_HOST_STACK_UP(__val__) (((__val__) << 16u) & 0x10000u)
#define DEVICE_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_SHIFT 19u
#define DEVICE_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_MASK 0x80000u
#define GET_DEVICE_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u)
@@ -7278,7 +7825,11 @@ typedef register_container RegDEVICEGrcModeControl_t {
BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits)
#if defined(__LITTLE_ENDIAN__)
/** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_18_0, 0, 19)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16)
+ /** @brief The host stack is ready to receive data from the NIC. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HostStackUp, 16, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_18_17, 17, 2)
/** @brief Write 1 to this bit to enable Time Sync Mode. */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TimeSyncModeEnable, 19, 1)
/** @brief Padding */
@@ -7313,7 +7864,11 @@ typedef register_container RegDEVICEGrcModeControl_t {
/** @brief Write 1 to this bit to enable Time Sync Mode. */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TimeSyncModeEnable, 19, 1)
/** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_18_0, 0, 19)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_18_17, 17, 2)
+ /** @brief The host stack is ready to receive data from the NIC. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, HostStackUp, 16, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_15_0, 0, 16)
#else
#error Unknown Endian
#endif
@@ -7329,6 +7884,8 @@ typedef register_container RegDEVICEGrcModeControl_t {
{
/** @brief constructor for @ref DEVICE_t.GrcModeControl. */
r32.setName("GrcModeControl");
+ bits.HostStackUp.setBaseRegister(&r32);
+ bits.HostStackUp.setName("HostStackUp");
bits.TimeSyncModeEnable.setBaseRegister(&r32);
bits.TimeSyncModeEnable.setName("TimeSyncModeEnable");
bits.NVRAMWriteEnable.setBaseRegister(&r32);
@@ -7349,14 +7906,39 @@ typedef register_container RegDEVICEGrcModeControl_t {
} RegDEVICEGrcModeControl_t;
#define REG_DEVICE_MISCELLANEOUS_CONFIG ((volatile APE_DEVICE_H_uint32_t*)0xa0046804) /* */
-#define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 1u
-#define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x2u
-#define GET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x2) >> 1u)
-#define SET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 1u) & 0x2u)
-#define DEVICE_MISCELLANEOUS_CONFIG_ALL_SHIFT 1u
-#define DEVICE_MISCELLANEOUS_CONFIG_ALL_MASK 0xfffffffeu
-#define GET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__reg__) (((__reg__) & 0xfffffffe) >> 1u)
-#define SET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__val__) (((__val__) << 1u) & 0xfffffffeu)
+#define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 0u
+#define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x1u
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x1) >> 0u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 0u) & 0x1u)
+#define DEVICE_MISCELLANEOUS_CONFIG_TIMER_PRESCALER_SHIFT 1u
+#define DEVICE_MISCELLANEOUS_CONFIG_TIMER_PRESCALER_MASK 0xfeu
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_TIMER_PRESCALER(__reg__) (((__reg__) & 0xfe) >> 1u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_TIMER_PRESCALER(__val__) (((__val__) << 1u) & 0xfeu)
+#define DEVICE_MISCELLANEOUS_CONFIG_BOND_ID_SHIFT 13u
+#define DEVICE_MISCELLANEOUS_CONFIG_BOND_ID_MASK 0x1e000u
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_BOND_ID(__reg__) (((__reg__) & 0x1e000) >> 13u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_BOND_ID(__val__) (((__val__) << 13u) & 0x1e000u)
+#define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_SHIFT 17u
+#define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_MASK 0x60000u
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE(__reg__) (((__reg__) & 0x60000) >> 17u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE(__val__) (((__val__) << 17u) & 0x60000u)
+#define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_D0 0x0u
+#define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_D1 0x1u
+#define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_D2 0x2u
+#define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_D3 0x3u
+
+#define DEVICE_MISCELLANEOUS_CONFIG_PME_EN_STATE_SHIFT 19u
+#define DEVICE_MISCELLANEOUS_CONFIG_PME_EN_STATE_MASK 0x80000u
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_PME_EN_STATE(__reg__) (((__reg__) & 0x80000) >> 19u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_PME_EN_STATE(__val__) (((__val__) << 19u) & 0x80000u)
+#define DEVICE_MISCELLANEOUS_CONFIG_POWERDOWN_SHIFT 20u
+#define DEVICE_MISCELLANEOUS_CONFIG_POWERDOWN_MASK 0x100000u
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_POWERDOWN(__reg__) (((__reg__) & 0x100000) >> 20u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_POWERDOWN(__val__) (((__val__) << 20u) & 0x100000u)
+#define DEVICE_MISCELLANEOUS_CONFIG_DISABLE_GRC_RESET_SHIFT 29u
+#define DEVICE_MISCELLANEOUS_CONFIG_DISABLE_GRC_RESET_MASK 0x20000000u
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_DISABLE_GRC_RESET(__reg__) (((__reg__) & 0x20000000) >> 29u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_DISABLE_GRC_RESET(__val__) (((__val__) << 29u) & 0x20000000u)
/** @brief Register definition for @ref DEVICE_t.MiscellaneousConfig. */
typedef register_container RegDEVICEMiscellaneousConfig_t {
@@ -7365,19 +7947,47 @@ typedef register_container RegDEVICEMiscellaneousConfig_t {
BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits)
#if defined(__LITTLE_ENDIAN__)
+ /** @brief Write 1 to this bit resets the CORE_CLK blocks in the device. This is a self-clearing bit. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GRCReset, 0, 1)
+ /** @brief Local Core clock frequency in MHz, minus 1, which should correspond to each advance of the timer. Reset to all 1. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TimerPrescaler, 1, 7)
/** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_0_0, 0, 1)
- /** @brief */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GRCReset, 1, 1)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_12_8, 8, 5)
/** @brief */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, all, 1, 31)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BondID, 13, 4)
+ /** @brief Indicates the current power state of the device. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerState, 17, 2)
+ /** @brief State of PME Enable for this device. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMEENState, 19, 1)
+ /** @brief Setting this bit will power down the device (power consumption is ~20 mW). This bit is cleared by PCI reset. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Powerdown, 20, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_28_21, 21, 8)
+ /** @brief Setting this bit will prevent reset to PCIE block. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DisableGRCReset, 29, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_30, 30, 2)
#elif defined(__BIG_ENDIAN__)
- /** @brief */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, all, 1, 31)
- /** @brief */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GRCReset, 1, 1)
/** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_0_0, 0, 1)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_30, 30, 2)
+ /** @brief Setting this bit will prevent reset to PCIE block. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, DisableGRCReset, 29, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_28_21, 21, 8)
+ /** @brief Setting this bit will power down the device (power consumption is ~20 mW). This bit is cleared by PCI reset. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, Powerdown, 20, 1)
+ /** @brief State of PME Enable for this device. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PMEENState, 19, 1)
+ /** @brief Indicates the current power state of the device. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, PowerState, 17, 2)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, BondID, 13, 4)
+ /** @brief Padding */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_12_8, 8, 5)
+ /** @brief Local Core clock frequency in MHz, minus 1, which should correspond to each advance of the timer. Reset to all 1. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, TimerPrescaler, 1, 7)
+ /** @brief Write 1 to this bit resets the CORE_CLK blocks in the device. This is a self-clearing bit. */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GRCReset, 0, 1)
#else
#error Unknown Endian
#endif
@@ -7395,8 +8005,23 @@ typedef register_container RegDEVICEMiscellaneousConfig_t {
r32.setName("MiscellaneousConfig");
bits.GRCReset.setBaseRegister(&r32);
bits.GRCReset.setName("GRCReset");
- bits.all.setBaseRegister(&r32);
- bits.all.setName("all");
+ bits.TimerPrescaler.setBaseRegister(&r32);
+ bits.TimerPrescaler.setName("TimerPrescaler");
+ bits.BondID.setBaseRegister(&r32);
+ bits.BondID.setName("BondID");
+ bits.PowerState.setBaseRegister(&r32);
+ bits.PowerState.setName("PowerState");
+ bits.PowerState.addEnum("D0", 0x0);
+ bits.PowerState.addEnum("D1", 0x1);
+ bits.PowerState.addEnum("D2", 0x2);
+ bits.PowerState.addEnum("D3", 0x3);
+
+ bits.PMEENState.setBaseRegister(&r32);
+ bits.PMEENState.setName("PMEENState");
+ bits.Powerdown.setBaseRegister(&r32);
+ bits.Powerdown.setName("Powerdown");
+ bits.DisableGRCReset.setBaseRegister(&r32);
+ bits.DisableGRCReset.setName("DisableGRCReset");
}
RegDEVICEMiscellaneousConfig_t& operator=(const RegDEVICEMiscellaneousConfig_t& other)
{
@@ -7407,6 +8032,18 @@ typedef register_container RegDEVICEMiscellaneousConfig_t {
} RegDEVICEMiscellaneousConfig_t;
#define REG_DEVICE_MISCELLANEOUS_LOCAL_CONTROL ((volatile APE_DEVICE_H_uint32_t*)0xa0046808) /* */
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_INPUT_SHIFT 5u
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_INPUT_MASK 0x20u
+#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_INPUT(__reg__) (((__reg__) & 0x20) >> 5u)
+#define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_INPUT(__val__) (((__val__) << 5u) & 0x20u)
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_ENABLE_SHIFT 6u
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_ENABLE_MASK 0x40u
+#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x40) >> 6u)
+#define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_ENABLE(__val__) (((__val__) << 6u) & 0x40u)
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_SHIFT 7u
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_MASK 0x80u
+#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT(__reg__) (((__reg__) & 0x80) >> 7u)
+#define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT(__val__) (((__val__) << 7u) & 0x80u)
#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_SHIFT 8u
#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_MASK 0x100u
#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__reg__) (((__reg__) & 0x100) >> 8u)
@@ -7443,6 +8080,10 @@ typedef register_container RegDEVICEMiscellaneousConfig_t {
#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_MASK 0x10000u
#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__reg__) (((__reg__) & 0x10000) >> 16u)
#define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__val__) (((__val__) << 16u) & 0x10000u)
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_APE_GPIO_IN_SHIFT 17u
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_APE_GPIO_IN_MASK 0xfe0000u
+#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_APE_GPIO_IN(__reg__) (((__reg__) & 0xfe0000) >> 17u)
+#define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_APE_GPIO_IN(__val__) (((__val__) << 17u) & 0xfe0000u)
#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_SHIFT 24u
#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_MASK 0x1000000u
#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__reg__) (((__reg__) & 0x1000000) >> 24u)
@@ -7456,7 +8097,13 @@ typedef register_container RegDEVICEMiscellaneousLocalControl_t {
BITFIELD_BEGIN(APE_DEVICE_H_uint32_t, bits)
#if defined(__LITTLE_ENDIAN__)
/** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_0, 0, 8)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_4_0, 0, 5)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO3Input, 5, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO3OutputEnable, 6, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO3Output, 7, 1)
/** @brief */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO0Input, 8, 1)
/** @brief */
@@ -7475,8 +8122,8 @@ typedef register_container RegDEVICEMiscellaneousLocalControl_t {
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO1Output, 15, 1)
/** @brief */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO2Output, 16, 1)
- /** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_23_17, 17, 7)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEGPIOIn, 17, 7)
/** @brief */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, AutoSEEPROMAccess, 24, 1)
/** @brief Padding */
@@ -7486,8 +8133,8 @@ typedef register_container RegDEVICEMiscellaneousLocalControl_t {
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_31_25, 25, 7)
/** @brief */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, AutoSEEPROMAccess, 24, 1)
- /** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_23_17, 17, 7)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, APEGPIOIn, 17, 7)
/** @brief */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO2Output, 16, 1)
/** @brief */
@@ -7506,8 +8153,14 @@ typedef register_container RegDEVICEMiscellaneousLocalControl_t {
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO1Input, 9, 1)
/** @brief */
BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO0Input, 8, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO3Output, 7, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO3OutputEnable, 6, 1)
+ /** @brief */
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, GPIO3Input, 5, 1)
/** @brief Padding */
- BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_7_0, 0, 8)
+ BITFIELD_MEMBER(APE_DEVICE_H_uint32_t, reserved_4_0, 0, 5)
#else
#error Unknown Endian
#endif
@@ -7523,6 +8176,12 @@ typedef register_container RegDEVICEMiscellaneousLocalControl_t {
{
/** @brief constructor for @ref DEVICE_t.MiscellaneousLocalControl. */
r32.setName("MiscellaneousLocalControl");
+ bits.GPIO3Input.setBaseRegister(&r32);
+ bits.GPIO3Input.setName("GPIO3Input");
+ bits.GPIO3OutputEnable.setBaseRegister(&r32);
+ bits.GPIO3OutputEnable.setName("GPIO3OutputEnable");
+ bits.GPIO3Output.setBaseRegister(&r32);
+ bits.GPIO3Output.setName("GPIO3Output");
bits.GPIO0Input.setBaseRegister(&r32);
bits.GPIO0Input.setName("GPIO0Input");
bits.GPIO1Input.setBaseRegister(&r32);
@@ -7541,6 +8200,8 @@ typedef register_container RegDEVICEMiscellaneousLocalControl_t {
bits.GPIO1Output.setName("GPIO1Output");
bits.GPIO2Output.setBaseRegister(&r32);
bits.GPIO2Output.setName("GPIO2Output");
+ bits.APEGPIOIn.setBaseRegister(&r32);
+ bits.APEGPIOIn.setName("APEGPIOIn");
bits.AutoSEEPROMAccess.setBaseRegister(&r32);
bits.AutoSEEPROMAccess.setName("AutoSEEPROMAccess");
}
@@ -8095,7 +8756,13 @@ typedef struct DEVICE_t {
RegDEVICEApeMemoryData_t ApeMemoryData;
/** @brief Reserved bytes to pad out data structure. */
- APE_DEVICE_H_uint32_t reserved_256[192];
+ APE_DEVICE_H_uint32_t reserved_256[24];
+
+ /** @brief Unknown register. */
+ RegDEVICE160_t _160;
+
+ /** @brief Reserved bytes to pad out data structure. */
+ APE_DEVICE_H_uint32_t reserved_356[167];
/** @brief */
RegDEVICEEmacMode_t EmacMode;
@@ -8139,8 +8806,8 @@ typedef struct DEVICE_t {
/** @brief */
RegDEVICEWolPatternCfg_t WolPatternCfg;
- /** @brief Reserved bytes to pad out data structure. */
- APE_DEVICE_H_uint32_t reserved_1080[1];
+ /** @brief Unknown register. */
+ RegDEVICE438_t _438;
/** @brief 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */
RegDEVICEMtuSize_t MtuSize;
@@ -8214,8 +8881,11 @@ typedef struct DEVICE_t {
/** @brief */
RegDEVICECpmuControl_t CpmuControl;
+ /** @brief */
+ RegDEVICENoLinkPowerModeClockPolicy_t NoLinkPowerModeClockPolicy;
+
/** @brief Reserved bytes to pad out data structure. */
- APE_DEVICE_H_uint32_t reserved_13828[3];
+ APE_DEVICE_H_uint32_t reserved_13832[2];
/** @brief */
RegDEVICELinkAwarePowerModeClockPolicy_t LinkAwarePowerModeClockPolicy;
@@ -8257,7 +8927,13 @@ typedef struct DEVICE_t {
RegDEVICEGphyStrap_t GphyStrap;
/** @brief Reserved bytes to pad out data structure. */
- APE_DEVICE_H_uint32_t reserved_13928[5];
+ APE_DEVICE_H_uint32_t reserved_13928[1];
+
+ /** @brief */
+ RegDEVICEFlashClockControlPolicy_t FlashClockControlPolicy;
+
+ /** @brief Reserved bytes to pad out data structure. */
+ APE_DEVICE_H_uint32_t reserved_13936[3];
/** @brief */
RegDEVICETopLevelMiscellaneousControl1_t TopLevelMiscellaneousControl1;
@@ -8290,7 +8966,13 @@ typedef struct DEVICE_t {
RegDEVICEGlobalMutexGrant_t GlobalMutexGrant;
/** @brief Reserved bytes to pad out data structure. */
- APE_DEVICE_H_uint32_t reserved_14072[578];
+ APE_DEVICE_H_uint32_t reserved_14072[1];
+
+ /** @brief */
+ RegDEVICETemperatureMonitorControl_t TemperatureMonitorControl;
+
+ /** @brief Reserved bytes to pad out data structure. */
+ APE_DEVICE_H_uint32_t reserved_14080[576];
/** @brief */
RegDEVICEMemoryArbiterMode_t MemoryArbiterMode;
@@ -8469,8 +9151,8 @@ typedef struct DEVICE_t {
/** @brief */
RegDEVICE64c0_t _64c0;
- /** @brief Reserved bytes to pad out data structure. */
- APE_DEVICE_H_uint32_t reserved_25796[1];
+ /** @brief */
+ RegDEVICE64c4_t _64c4;
/** @brief */
RegDEVICE64c8_t _64c8;
@@ -8598,16 +9280,49 @@ typedef struct DEVICE_t {
#ifdef CXX_SIMULATOR
DEVICE_t()
{
+ for(int i = 0; i < 26; i++)
+ {
+ reserved_0[i].setComponentOffset(0x0 + (i * 4));
+ }
MiscellaneousHostControl.r32.setComponentOffset(0x68);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_108[i].setComponentOffset(0x6c + (i * 4));
+ }
PciState.r32.setComponentOffset(0x70);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_116[i].setComponentOffset(0x74 + (i * 4));
+ }
RegisterBase.r32.setComponentOffset(0x78);
MemoryBase.r32.setComponentOffset(0x7c);
RegisterData.r32.setComponentOffset(0x80);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_132[i].setComponentOffset(0x84 + (i * 4));
+ }
UndiReceiveReturnRingConsumerIndex.r32.setComponentOffset(0x88);
UndiReceiveReturnRingConsumerIndexLow.r32.setComponentOffset(0x8c);
+ for(int i = 0; i < 11; i++)
+ {
+ reserved_144[i].setComponentOffset(0x90 + (i * 4));
+ }
LinkStatusControl.r32.setComponentOffset(0xbc);
+ for(int i = 0; i < 14; i++)
+ {
+ reserved_192[i].setComponentOffset(0xc0 + (i * 4));
+ }
ApeMemoryBase.r32.setComponentOffset(0xf8);
ApeMemoryData.r32.setComponentOffset(0xfc);
+ for(int i = 0; i < 24; i++)
+ {
+ reserved_256[i].setComponentOffset(0x100 + (i * 4));
+ }
+ _160.r32.setComponentOffset(0x160);
+ for(int i = 0; i < 167; i++)
+ {
+ reserved_356[i].setComponentOffset(0x164 + (i * 4));
+ }
EmacMode.r32.setComponentOffset(0x400);
EmacStatus.r32.setComponentOffset(0x404);
EmacEvent.r32.setComponentOffset(0x408);
@@ -8622,13 +9337,34 @@ typedef struct DEVICE_t {
EmacMacAddresses3Low.r32.setComponentOffset(0x42c);
WolPatternPointer.r32.setComponentOffset(0x430);
WolPatternCfg.r32.setComponentOffset(0x434);
+ _438.r32.setComponentOffset(0x438);
MtuSize.r32.setComponentOffset(0x43c);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_1088[i].setComponentOffset(0x440 + (i * 4));
+ }
MiiCommunication.r32.setComponentOffset(0x44c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_1104[i].setComponentOffset(0x450 + (i * 4));
+ }
MiiMode.r32.setComponentOffset(0x454);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_1112[i].setComponentOffset(0x458 + (i * 4));
+ }
TransmitMacMode.r32.setComponentOffset(0x45c);
TransmitMacStatus.r32.setComponentOffset(0x460);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_1124[i].setComponentOffset(0x464 + (i * 4));
+ }
ReceiveMacMode.r32.setComponentOffset(0x468);
ReceiveMacStatus.r32.setComponentOffset(0x46c);
+ for(int i = 0; i < 52; i++)
+ {
+ reserved_1136[i].setComponentOffset(0x470 + (i * 4));
+ }
PerfectMatch1High.r32.setComponentOffset(0x540);
PerfectMatch1Low.r32.setComponentOffset(0x544);
PerfectMatch2High.r32.setComponentOffset(0x548);
@@ -8637,31 +9373,118 @@ typedef struct DEVICE_t {
PerfectMatch3Low.r32.setComponentOffset(0x554);
PerfectMatch4High.r32.setComponentOffset(0x558);
PerfectMatch4Low.r32.setComponentOffset(0x55c);
+ for(int i = 0; i < 21; i++)
+ {
+ reserved_1376[i].setComponentOffset(0x560 + (i * 4));
+ }
SgmiiStatus.r32.setComponentOffset(0x5b4);
+ for(int i = 0; i < 3090; i++)
+ {
+ reserved_1464[i].setComponentOffset(0x5b8 + (i * 4));
+ }
CpmuControl.r32.setComponentOffset(0x3600);
+ NoLinkPowerModeClockPolicy.r32.setComponentOffset(0x3604);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_13832[i].setComponentOffset(0x3608 + (i * 4));
+ }
LinkAwarePowerModeClockPolicy.r32.setComponentOffset(0x3610);
+ for(int i = 0; i < 4; i++)
+ {
+ reserved_13844[i].setComponentOffset(0x3614 + (i * 4));
+ }
ClockSpeedOverridePolicy.r32.setComponentOffset(0x3624);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_13864[i].setComponentOffset(0x3628 + (i * 4));
+ }
Status.r32.setComponentOffset(0x362c);
ClockStatus.r32.setComponentOffset(0x3630);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_13876[i].setComponentOffset(0x3634 + (i * 4));
+ }
GphyControlStatus.r32.setComponentOffset(0x3638);
+ for(int i = 0; i < 7; i++)
+ {
+ reserved_13884[i].setComponentOffset(0x363c + (i * 4));
+ }
ChipId.r32.setComponentOffset(0x3658);
MutexRequest.r32.setComponentOffset(0x365c);
MutexGrant.r32.setComponentOffset(0x3660);
GphyStrap.r32.setComponentOffset(0x3664);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_13928[i].setComponentOffset(0x3668 + (i * 4));
+ }
+ FlashClockControlPolicy.r32.setComponentOffset(0x366c);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_13936[i].setComponentOffset(0x3670 + (i * 4));
+ }
TopLevelMiscellaneousControl1.r32.setComponentOffset(0x367c);
+ for(int i = 0; i < 12; i++)
+ {
+ reserved_13952[i].setComponentOffset(0x3680 + (i * 4));
+ }
EeeMode.r32.setComponentOffset(0x36b0);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_14004[i].setComponentOffset(0x36b4 + (i * 4));
+ }
EeeLinkIdleControl.r32.setComponentOffset(0x36bc);
+ for(int i = 0; i < 4; i++)
+ {
+ reserved_14016[i].setComponentOffset(0x36c0 + (i * 4));
+ }
EeeControl.r32.setComponentOffset(0x36d0);
+ for(int i = 0; i < 7; i++)
+ {
+ reserved_14036[i].setComponentOffset(0x36d4 + (i * 4));
+ }
GlobalMutexRequest.r32.setComponentOffset(0x36f0);
GlobalMutexGrant.r32.setComponentOffset(0x36f4);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_14072[i].setComponentOffset(0x36f8 + (i * 4));
+ }
+ TemperatureMonitorControl.r32.setComponentOffset(0x36fc);
+ for(int i = 0; i < 576; i++)
+ {
+ reserved_14080[i].setComponentOffset(0x3700 + (i * 4));
+ }
MemoryArbiterMode.r32.setComponentOffset(0x4000);
+ for(int i = 0; i < 255; i++)
+ {
+ reserved_16388[i].setComponentOffset(0x4004 + (i * 4));
+ }
BufferManagerMode.r32.setComponentOffset(0x4400);
+ for(int i = 0; i < 323; i++)
+ {
+ reserved_17412[i].setComponentOffset(0x4404 + (i * 4));
+ }
LsoNonlsoBdReadDmaCorruptionEnableControl.r32.setComponentOffset(0x4910);
+ for(int i = 0; i < 443; i++)
+ {
+ reserved_18708[i].setComponentOffset(0x4914 + (i * 4));
+ }
RxRiscMode.r32.setComponentOffset(0x5000);
RxRiscStatus.r32.setComponentOffset(0x5004);
+ for(int i = 0; i < 5; i++)
+ {
+ reserved_20488[i].setComponentOffset(0x5008 + (i * 4));
+ }
RxRiscProgramCounter.r32.setComponentOffset(0x501c);
RxRiscCurrentInstruction.r32.setComponentOffset(0x5020);
+ for(int i = 0; i < 4; i++)
+ {
+ reserved_20516[i].setComponentOffset(0x5024 + (i * 4));
+ }
RxRiscHardwareBreakpoint.r32.setComponentOffset(0x5034);
+ for(int i = 0; i < 114; i++)
+ {
+ reserved_20536[i].setComponentOffset(0x5038 + (i * 4));
+ }
RxRiscRegister0.r32.setComponentOffset(0x5200);
RxRiscRegister1.r32.setComponentOffset(0x5204);
RxRiscRegister2.r32.setComponentOffset(0x5208);
@@ -8694,19 +9517,48 @@ typedef struct DEVICE_t {
RxRiscRegister29.r32.setComponentOffset(0x5274);
RxRiscRegister30.r32.setComponentOffset(0x5278);
RxRiscRegister31.r32.setComponentOffset(0x527c);
+ for(int i = 0; i < 1122; i++)
+ {
+ reserved_21120[i].setComponentOffset(0x5280 + (i * 4));
+ }
_6408.r32.setComponentOffset(0x6408);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_25612[i].setComponentOffset(0x640c + (i * 4));
+ }
PciPowerConsumptionInfo.r32.setComponentOffset(0x6410);
PciPowerDissipatedInfo.r32.setComponentOffset(0x6414);
+ for(int i = 0; i < 5; i++)
+ {
+ reserved_25624[i].setComponentOffset(0x6418 + (i * 4));
+ }
PciVpdRequest.r32.setComponentOffset(0x642c);
PciVpdResponse.r32.setComponentOffset(0x6430);
PciVendorDeviceId.r32.setComponentOffset(0x6434);
PciSubsystemId.r32.setComponentOffset(0x6438);
PciClassCodeRevision.r32.setComponentOffset(0x643c);
+ for(int i = 0; i < 32; i++)
+ {
+ reserved_25664[i].setComponentOffset(0x6440 + (i * 4));
+ }
_64c0.r32.setComponentOffset(0x64c0);
+ _64c4.r32.setComponentOffset(0x64c4);
_64c8.r32.setComponentOffset(0x64c8);
+ for(int i = 0; i < 4; i++)
+ {
+ reserved_25804[i].setComponentOffset(0x64cc + (i * 4));
+ }
_64dc.r32.setComponentOffset(0x64dc);
+ for(int i = 0; i < 9; i++)
+ {
+ reserved_25824[i].setComponentOffset(0x64e0 + (i * 4));
+ }
PciSerialNumberLow.r32.setComponentOffset(0x6504);
PciSerialNumberHigh.r32.setComponentOffset(0x6508);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_25868[i].setComponentOffset(0x650c + (i * 4));
+ }
PciPowerBudget0.r32.setComponentOffset(0x6510);
PciPowerBudget1.r32.setComponentOffset(0x6514);
PciPowerBudget2.r32.setComponentOffset(0x6518);
@@ -8716,20 +9568,60 @@ typedef struct DEVICE_t {
PciPowerBudget6.r32.setComponentOffset(0x6528);
PciPowerBudget7.r32.setComponentOffset(0x652c);
_6530.r32.setComponentOffset(0x6530);
+ for(int i = 0; i < 7; i++)
+ {
+ reserved_25908[i].setComponentOffset(0x6534 + (i * 4));
+ }
_6550.r32.setComponentOffset(0x6550);
+ for(int i = 0; i < 40; i++)
+ {
+ reserved_25940[i].setComponentOffset(0x6554 + (i * 4));
+ }
_65f4.r32.setComponentOffset(0x65f4);
+ for(int i = 0; i < 130; i++)
+ {
+ reserved_26104[i].setComponentOffset(0x65f8 + (i * 4));
+ }
GrcModeControl.r32.setComponentOffset(0x6800);
MiscellaneousConfig.r32.setComponentOffset(0x6804);
MiscellaneousLocalControl.r32.setComponentOffset(0x6808);
Timer.r32.setComponentOffset(0x680c);
RxCpuEvent.r32.setComponentOffset(0x6810);
+ for(int i = 0; i < 9; i++)
+ {
+ reserved_26644[i].setComponentOffset(0x6814 + (i * 4));
+ }
_6838.r32.setComponentOffset(0x6838);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_26684[i].setComponentOffset(0x683c + (i * 4));
+ }
MdiControl.r32.setComponentOffset(0x6844);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_26696[i].setComponentOffset(0x6848 + (i * 4));
+ }
RxCpuEventEnable.r32.setComponentOffset(0x684c);
+ for(int i = 0; i < 17; i++)
+ {
+ reserved_26704[i].setComponentOffset(0x6850 + (i * 4));
+ }
FastBootProgramCounter.r32.setComponentOffset(0x6894);
+ for(int i = 0; i < 21; i++)
+ {
+ reserved_26776[i].setComponentOffset(0x6898 + (i * 4));
+ }
ExpansionRomAddr.r32.setComponentOffset(0x68ec);
_68f0.r32.setComponentOffset(0x68f0);
+ for(int i = 0; i < 5; i++)
+ {
+ reserved_26868[i].setComponentOffset(0x68f4 + (i * 4));
+ }
EavRefClockControl.r32.setComponentOffset(0x6908);
+ for(int i = 0; i < 1214; i++)
+ {
+ reserved_26892[i].setComponentOffset(0x690c + (i * 4));
+ }
_7c04.r32.setComponentOffset(0x7c04);
}
void print()
@@ -8768,10 +9660,15 @@ typedef struct DEVICE_t {
}
ApeMemoryBase.print();
ApeMemoryData.print();
- for(int i = 0; i < 192; i++)
+ for(int i = 0; i < 24; i++)
{
reserved_256[i].print();
}
+ _160.print();
+ for(int i = 0; i < 167; i++)
+ {
+ reserved_356[i].print();
+ }
EmacMode.print();
EmacStatus.print();
EmacEvent.print();
@@ -8786,10 +9683,7 @@ typedef struct DEVICE_t {
EmacMacAddresses3Low.print();
WolPatternPointer.print();
WolPatternCfg.print();
- for(int i = 0; i < 1; i++)
- {
- reserved_1080[i].print();
- }
+ _438.print();
MtuSize.print();
for(int i = 0; i < 3; i++)
{
@@ -8835,9 +9729,10 @@ typedef struct DEVICE_t {
reserved_1464[i].print();
}
CpmuControl.print();
- for(int i = 0; i < 3; i++)
+ NoLinkPowerModeClockPolicy.print();
+ for(int i = 0; i < 2; i++)
{
- reserved_13828[i].print();
+ reserved_13832[i].print();
}
LinkAwarePowerModeClockPolicy.print();
for(int i = 0; i < 4; i++)
@@ -8864,10 +9759,15 @@ typedef struct DEVICE_t {
MutexRequest.print();
MutexGrant.print();
GphyStrap.print();
- for(int i = 0; i < 5; i++)
+ for(int i = 0; i < 1; i++)
{
reserved_13928[i].print();
}
+ FlashClockControlPolicy.print();
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_13936[i].print();
+ }
TopLevelMiscellaneousControl1.print();
for(int i = 0; i < 12; i++)
{
@@ -8890,10 +9790,15 @@ typedef struct DEVICE_t {
}
GlobalMutexRequest.print();
GlobalMutexGrant.print();
- for(int i = 0; i < 578; i++)
+ for(int i = 0; i < 1; i++)
{
reserved_14072[i].print();
}
+ TemperatureMonitorControl.print();
+ for(int i = 0; i < 576; i++)
+ {
+ reserved_14080[i].print();
+ }
MemoryArbiterMode.print();
for(int i = 0; i < 255; i++)
{
@@ -8983,10 +9888,7 @@ typedef struct DEVICE_t {
reserved_25664[i].print();
}
_64c0.print();
- for(int i = 0; i < 1; i++)
- {
- reserved_25796[i].print();
- }
+ _64c4.print();
_64c8.print();
for(int i = 0; i < 4; i++)
{
diff --git a/include/APE_DEVICE1.h b/include/APE_DEVICE1.h
index 3a215e6..2134685 100644
--- a/include/APE_DEVICE1.h
+++ b/include/APE_DEVICE1.h
@@ -92,6 +92,7 @@ typedef uint32_t APE_DEVICE1_H_uint32_t;
#define REG_DEVICE1_LINK_STATUS_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa00500bc) /* PCIe standard register. */
#define REG_DEVICE1_APE_MEMORY_BASE ((volatile APE_DEVICE1_H_uint32_t*)0xa00500f8) /* APE Memory address to read/write using the APE Memory Data register.. */
#define REG_DEVICE1_APE_MEMORY_DATA ((volatile APE_DEVICE1_H_uint32_t*)0xa00500fc) /* APE Memory value at the location pointed by the Memory Base Register. */
+#define REG_DEVICE1_160 ((volatile APE_DEVICE1_H_uint32_t*)0xa0050160) /* Unknown register. */
#define REG_DEVICE1_EMAC_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0050400) /* */
#define REG_DEVICE1_EMAC_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa0050404) /* */
#define REG_DEVICE1_EMAC_EVENT ((volatile APE_DEVICE1_H_uint32_t*)0xa0050408) /* */
@@ -106,6 +107,7 @@ typedef uint32_t APE_DEVICE1_H_uint32_t;
#define REG_DEVICE1_EMAC_MAC_ADDRESSES_3_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa005042c) /* Lower 4-byte of this node's MAC address. */
#define REG_DEVICE1_WOL_PATTERN_POINTER ((volatile APE_DEVICE1_H_uint32_t*)0xa0050430) /* Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary). */
#define REG_DEVICE1_WOL_PATTERN_CFG ((volatile APE_DEVICE1_H_uint32_t*)0xa0050434) /* */
+#define REG_DEVICE1_438 ((volatile APE_DEVICE1_H_uint32_t*)0xa0050438) /* Unknown register. */
#define REG_DEVICE1_MTU_SIZE ((volatile APE_DEVICE1_H_uint32_t*)0xa005043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */
#define REG_DEVICE1_MII_COMMUNICATION ((volatile APE_DEVICE1_H_uint32_t*)0xa005044c) /* */
#define REG_DEVICE1_MII_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0050454) /* */
@@ -123,6 +125,7 @@ typedef uint32_t APE_DEVICE1_H_uint32_t;
#define REG_DEVICE1_PERFECT_MATCH4_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa005055c) /* */
#define REG_DEVICE1_SGMII_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa00505b4) /* This register reflects various status of the respective SGMII port when enabled. */
#define REG_DEVICE1_CPMU_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0053600) /* */
+#define REG_DEVICE1_NO_LINK_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE1_H_uint32_t*)0xa0053604) /* */
#define REG_DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE1_H_uint32_t*)0xa0053610) /* */
#define REG_DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY ((volatile APE_DEVICE1_H_uint32_t*)0xa0053624) /* */
#define REG_DEVICE1_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa005362c) /* */
@@ -132,12 +135,14 @@ typedef uint32_t APE_DEVICE1_H_uint32_t;
#define REG_DEVICE1_MUTEX_REQUEST ((volatile APE_DEVICE1_H_uint32_t*)0xa005365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
#define REG_DEVICE1_MUTEX_GRANT ((volatile APE_DEVICE1_H_uint32_t*)0xa0053660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
#define REG_DEVICE1_GPHY_STRAP ((volatile APE_DEVICE1_H_uint32_t*)0xa0053664) /* */
+#define REG_DEVICE1_FLASH_CLOCK_CONTROL_POLICY ((volatile APE_DEVICE1_H_uint32_t*)0xa005366c) /* */
#define REG_DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile APE_DEVICE1_H_uint32_t*)0xa005367c) /* */
#define REG_DEVICE1_EEE_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa00536b0) /* */
#define REG_DEVICE1_EEE_LINK_IDLE_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa00536bc) /* */
#define REG_DEVICE1_EEE_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa00536d0) /* */
#define REG_DEVICE1_GLOBAL_MUTEX_REQUEST ((volatile APE_DEVICE1_H_uint32_t*)0xa00536f0) /* */
#define REG_DEVICE1_GLOBAL_MUTEX_GRANT ((volatile APE_DEVICE1_H_uint32_t*)0xa00536f4) /* */
+#define REG_DEVICE1_TEMPERATURE_MONITOR_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa00536fc) /* */
#define REG_DEVICE1_MEMORY_ARBITER_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0054000) /* */
#define REG_DEVICE1_BUFFER_MANAGER_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0054400) /* */
#define REG_DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0054910) /* */
@@ -187,6 +192,7 @@ typedef uint32_t APE_DEVICE1_H_uint32_t;
#define REG_DEVICE1_PCI_SUBSYSTEM_ID ((volatile APE_DEVICE1_H_uint32_t*)0xa0056438) /* This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM. */
#define REG_DEVICE1_PCI_CLASS_CODE_REVISION ((volatile APE_DEVICE1_H_uint32_t*)0xa005643c) /* This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed. */
#define REG_DEVICE1_64C0 ((volatile APE_DEVICE1_H_uint32_t*)0xa00564c0) /* */
+#define REG_DEVICE1_64C4 ((volatile APE_DEVICE1_H_uint32_t*)0xa00564c4) /* */
#define REG_DEVICE1_64C8 ((volatile APE_DEVICE1_H_uint32_t*)0xa00564c8) /* */
#define REG_DEVICE1_64DC ((volatile APE_DEVICE1_H_uint32_t*)0xa00564dc) /* */
#define REG_DEVICE1_PCI_SERIAL_NUMBER_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa0056504) /* This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */
diff --git a/include/APE_DEVICE2.h b/include/APE_DEVICE2.h
index 11427d5..4001800 100644
--- a/include/APE_DEVICE2.h
+++ b/include/APE_DEVICE2.h
@@ -92,6 +92,7 @@ typedef uint32_t APE_DEVICE2_H_uint32_t;
#define REG_DEVICE2_LINK_STATUS_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00600bc) /* PCIe standard register. */
#define REG_DEVICE2_APE_MEMORY_BASE ((volatile APE_DEVICE2_H_uint32_t*)0xa00600f8) /* APE Memory address to read/write using the APE Memory Data register.. */
#define REG_DEVICE2_APE_MEMORY_DATA ((volatile APE_DEVICE2_H_uint32_t*)0xa00600fc) /* APE Memory value at the location pointed by the Memory Base Register. */
+#define REG_DEVICE2_160 ((volatile APE_DEVICE2_H_uint32_t*)0xa0060160) /* Unknown register. */
#define REG_DEVICE2_EMAC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060400) /* */
#define REG_DEVICE2_EMAC_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa0060404) /* */
#define REG_DEVICE2_EMAC_EVENT ((volatile APE_DEVICE2_H_uint32_t*)0xa0060408) /* */
@@ -106,6 +107,7 @@ typedef uint32_t APE_DEVICE2_H_uint32_t;
#define REG_DEVICE2_EMAC_MAC_ADDRESSES_3_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006042c) /* Lower 4-byte of this node's MAC address. */
#define REG_DEVICE2_WOL_PATTERN_POINTER ((volatile APE_DEVICE2_H_uint32_t*)0xa0060430) /* Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary). */
#define REG_DEVICE2_WOL_PATTERN_CFG ((volatile APE_DEVICE2_H_uint32_t*)0xa0060434) /* */
+#define REG_DEVICE2_438 ((volatile APE_DEVICE2_H_uint32_t*)0xa0060438) /* Unknown register. */
#define REG_DEVICE2_MTU_SIZE ((volatile APE_DEVICE2_H_uint32_t*)0xa006043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */
#define REG_DEVICE2_MII_COMMUNICATION ((volatile APE_DEVICE2_H_uint32_t*)0xa006044c) /* */
#define REG_DEVICE2_MII_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060454) /* */
@@ -123,6 +125,7 @@ typedef uint32_t APE_DEVICE2_H_uint32_t;
#define REG_DEVICE2_PERFECT_MATCH4_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006055c) /* */
#define REG_DEVICE2_SGMII_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa00605b4) /* This register reflects various status of the respective SGMII port when enabled. */
#define REG_DEVICE2_CPMU_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0063600) /* */
+#define REG_DEVICE2_NO_LINK_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE2_H_uint32_t*)0xa0063604) /* */
#define REG_DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE2_H_uint32_t*)0xa0063610) /* */
#define REG_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY ((volatile APE_DEVICE2_H_uint32_t*)0xa0063624) /* */
#define REG_DEVICE2_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa006362c) /* */
@@ -132,12 +135,14 @@ typedef uint32_t APE_DEVICE2_H_uint32_t;
#define REG_DEVICE2_MUTEX_REQUEST ((volatile APE_DEVICE2_H_uint32_t*)0xa006365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
#define REG_DEVICE2_MUTEX_GRANT ((volatile APE_DEVICE2_H_uint32_t*)0xa0063660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
#define REG_DEVICE2_GPHY_STRAP ((volatile APE_DEVICE2_H_uint32_t*)0xa0063664) /* */
+#define REG_DEVICE2_FLASH_CLOCK_CONTROL_POLICY ((volatile APE_DEVICE2_H_uint32_t*)0xa006366c) /* */
#define REG_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile APE_DEVICE2_H_uint32_t*)0xa006367c) /* */
#define REG_DEVICE2_EEE_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa00636b0) /* */
#define REG_DEVICE2_EEE_LINK_IDLE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00636bc) /* */
#define REG_DEVICE2_EEE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00636d0) /* */
#define REG_DEVICE2_GLOBAL_MUTEX_REQUEST ((volatile APE_DEVICE2_H_uint32_t*)0xa00636f0) /* */
#define REG_DEVICE2_GLOBAL_MUTEX_GRANT ((volatile APE_DEVICE2_H_uint32_t*)0xa00636f4) /* */
+#define REG_DEVICE2_TEMPERATURE_MONITOR_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00636fc) /* */
#define REG_DEVICE2_MEMORY_ARBITER_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0064000) /* */
#define REG_DEVICE2_BUFFER_MANAGER_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0064400) /* */
#define REG_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0064910) /* */
@@ -187,6 +192,7 @@ typedef uint32_t APE_DEVICE2_H_uint32_t;
#define REG_DEVICE2_PCI_SUBSYSTEM_ID ((volatile APE_DEVICE2_H_uint32_t*)0xa0066438) /* This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM. */
#define REG_DEVICE2_PCI_CLASS_CODE_REVISION ((volatile APE_DEVICE2_H_uint32_t*)0xa006643c) /* This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed. */
#define REG_DEVICE2_64C0 ((volatile APE_DEVICE2_H_uint32_t*)0xa00664c0) /* */
+#define REG_DEVICE2_64C4 ((volatile APE_DEVICE2_H_uint32_t*)0xa00664c4) /* */
#define REG_DEVICE2_64C8 ((volatile APE_DEVICE2_H_uint32_t*)0xa00664c8) /* */
#define REG_DEVICE2_64DC ((volatile APE_DEVICE2_H_uint32_t*)0xa00664dc) /* */
#define REG_DEVICE2_PCI_SERIAL_NUMBER_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0066504) /* This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */
diff --git a/include/APE_DEVICE3.h b/include/APE_DEVICE3.h
index d72bf50..38589d2 100644
--- a/include/APE_DEVICE3.h
+++ b/include/APE_DEVICE3.h
@@ -92,6 +92,7 @@ typedef uint32_t APE_DEVICE3_H_uint32_t;
#define REG_DEVICE3_LINK_STATUS_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa00700bc) /* PCIe standard register. */
#define REG_DEVICE3_APE_MEMORY_BASE ((volatile APE_DEVICE3_H_uint32_t*)0xa00700f8) /* APE Memory address to read/write using the APE Memory Data register.. */
#define REG_DEVICE3_APE_MEMORY_DATA ((volatile APE_DEVICE3_H_uint32_t*)0xa00700fc) /* APE Memory value at the location pointed by the Memory Base Register. */
+#define REG_DEVICE3_160 ((volatile APE_DEVICE3_H_uint32_t*)0xa0070160) /* Unknown register. */
#define REG_DEVICE3_EMAC_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0070400) /* */
#define REG_DEVICE3_EMAC_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa0070404) /* */
#define REG_DEVICE3_EMAC_EVENT ((volatile APE_DEVICE3_H_uint32_t*)0xa0070408) /* */
@@ -106,6 +107,7 @@ typedef uint32_t APE_DEVICE3_H_uint32_t;
#define REG_DEVICE3_EMAC_MAC_ADDRESSES_3_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa007042c) /* Lower 4-byte of this node's MAC address. */
#define REG_DEVICE3_WOL_PATTERN_POINTER ((volatile APE_DEVICE3_H_uint32_t*)0xa0070430) /* Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary). */
#define REG_DEVICE3_WOL_PATTERN_CFG ((volatile APE_DEVICE3_H_uint32_t*)0xa0070434) /* */
+#define REG_DEVICE3_438 ((volatile APE_DEVICE3_H_uint32_t*)0xa0070438) /* Unknown register. */
#define REG_DEVICE3_MTU_SIZE ((volatile APE_DEVICE3_H_uint32_t*)0xa007043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */
#define REG_DEVICE3_MII_COMMUNICATION ((volatile APE_DEVICE3_H_uint32_t*)0xa007044c) /* */
#define REG_DEVICE3_MII_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0070454) /* */
@@ -123,6 +125,7 @@ typedef uint32_t APE_DEVICE3_H_uint32_t;
#define REG_DEVICE3_PERFECT_MATCH4_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa007055c) /* */
#define REG_DEVICE3_SGMII_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa00705b4) /* This register reflects various status of the respective SGMII port when enabled. */
#define REG_DEVICE3_CPMU_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0073600) /* */
+#define REG_DEVICE3_NO_LINK_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE3_H_uint32_t*)0xa0073604) /* */
#define REG_DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE3_H_uint32_t*)0xa0073610) /* */
#define REG_DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY ((volatile APE_DEVICE3_H_uint32_t*)0xa0073624) /* */
#define REG_DEVICE3_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa007362c) /* */
@@ -132,12 +135,14 @@ typedef uint32_t APE_DEVICE3_H_uint32_t;
#define REG_DEVICE3_MUTEX_REQUEST ((volatile APE_DEVICE3_H_uint32_t*)0xa007365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
#define REG_DEVICE3_MUTEX_GRANT ((volatile APE_DEVICE3_H_uint32_t*)0xa0073660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
#define REG_DEVICE3_GPHY_STRAP ((volatile APE_DEVICE3_H_uint32_t*)0xa0073664) /* */
+#define REG_DEVICE3_FLASH_CLOCK_CONTROL_POLICY ((volatile APE_DEVICE3_H_uint32_t*)0xa007366c) /* */
#define REG_DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile APE_DEVICE3_H_uint32_t*)0xa007367c) /* */
#define REG_DEVICE3_EEE_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa00736b0) /* */
#define REG_DEVICE3_EEE_LINK_IDLE_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa00736bc) /* */
#define REG_DEVICE3_EEE_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa00736d0) /* */
#define REG_DEVICE3_GLOBAL_MUTEX_REQUEST ((volatile APE_DEVICE3_H_uint32_t*)0xa00736f0) /* */
#define REG_DEVICE3_GLOBAL_MUTEX_GRANT ((volatile APE_DEVICE3_H_uint32_t*)0xa00736f4) /* */
+#define REG_DEVICE3_TEMPERATURE_MONITOR_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa00736fc) /* */
#define REG_DEVICE3_MEMORY_ARBITER_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0074000) /* */
#define REG_DEVICE3_BUFFER_MANAGER_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0074400) /* */
#define REG_DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0074910) /* */
@@ -187,6 +192,7 @@ typedef uint32_t APE_DEVICE3_H_uint32_t;
#define REG_DEVICE3_PCI_SUBSYSTEM_ID ((volatile APE_DEVICE3_H_uint32_t*)0xa0076438) /* This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM. */
#define REG_DEVICE3_PCI_CLASS_CODE_REVISION ((volatile APE_DEVICE3_H_uint32_t*)0xa007643c) /* This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed. */
#define REG_DEVICE3_64C0 ((volatile APE_DEVICE3_H_uint32_t*)0xa00764c0) /* */
+#define REG_DEVICE3_64C4 ((volatile APE_DEVICE3_H_uint32_t*)0xa00764c4) /* */
#define REG_DEVICE3_64C8 ((volatile APE_DEVICE3_H_uint32_t*)0xa00764c8) /* */
#define REG_DEVICE3_64DC ((volatile APE_DEVICE3_H_uint32_t*)0xa00764dc) /* */
#define REG_DEVICE3_PCI_SERIAL_NUMBER_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa0076504) /* This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */
diff --git a/include/APE_FILTERS0.h b/include/APE_FILTERS0.h
index a10fa18..4c4ae99 100644
--- a/include/APE_FILTERS0.h
+++ b/include/APE_FILTERS0.h
@@ -491,6 +491,10 @@ typedef struct FILTERS_t {
{
RuleSet[i].r32.setComponentOffset(0x104 + (i * 4));
}
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_384[i].setComponentOffset(0x180 + (i * 4));
+ }
for(int i = 0; i < 31; i++)
{
RuleMask[i].r32.setComponentOffset(0x184 + (i * 4));
diff --git a/include/APE_NVIC.h b/include/APE_NVIC.h
index 5dde48d..35c786a 100644
--- a/include/APE_NVIC.h
+++ b/include/APE_NVIC.h
@@ -2332,34 +2332,150 @@ typedef struct NVIC_t {
#ifdef CXX_SIMULATOR
NVIC_t()
{
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_0[i].setComponentOffset(0x0 + (i * 4));
+ }
InterruptControlType.r32.setComponentOffset(0x4);
+ for(int i = 0; i < 11; i++)
+ {
+ reserved_5[i].setComponentOffset(0x5 + (i * 4));
+ }
SystickControlAndStatus.r32.setComponentOffset(0x10);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_17[i].setComponentOffset(0x11 + (i * 4));
+ }
SystickReloadValue.r32.setComponentOffset(0x14);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_21[i].setComponentOffset(0x15 + (i * 4));
+ }
SystickCurrentValue.r32.setComponentOffset(0x18);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_25[i].setComponentOffset(0x19 + (i * 4));
+ }
SystickCalibrationValue.r32.setComponentOffset(0x1c);
+ for(int i = 0; i < 227; i++)
+ {
+ reserved_29[i].setComponentOffset(0x1d + (i * 4));
+ }
InterruptSetEnable.r32.setComponentOffset(0x100);
+ for(int i = 0; i < 127; i++)
+ {
+ reserved_257[i].setComponentOffset(0x101 + (i * 4));
+ }
InterruptClearEnable.r32.setComponentOffset(0x180);
+ for(int i = 0; i < 127; i++)
+ {
+ reserved_385[i].setComponentOffset(0x181 + (i * 4));
+ }
InterruptSetPending.r32.setComponentOffset(0x200);
+ for(int i = 0; i < 127; i++)
+ {
+ reserved_513[i].setComponentOffset(0x201 + (i * 4));
+ }
InterruptClearPending.r32.setComponentOffset(0x280);
+ for(int i = 0; i < 127; i++)
+ {
+ reserved_641[i].setComponentOffset(0x281 + (i * 4));
+ }
ActiveBit.r32.setComponentOffset(0x300);
+ for(int i = 0; i < 255; i++)
+ {
+ reserved_769[i].setComponentOffset(0x301 + (i * 4));
+ }
InterruptPriority0.r32.setComponentOffset(0x400);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_1025[i].setComponentOffset(0x401 + (i * 4));
+ }
InterruptPriority1.r32.setComponentOffset(0x404);
+ for(int i = 0; i < 2299; i++)
+ {
+ reserved_1029[i].setComponentOffset(0x405 + (i * 4));
+ }
CpuId.r32.setComponentOffset(0xd00);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3329[i].setComponentOffset(0xd01 + (i * 4));
+ }
InterruptControlState.r32.setComponentOffset(0xd04);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3333[i].setComponentOffset(0xd05 + (i * 4));
+ }
VectorTableOffset.r32.setComponentOffset(0xd08);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3337[i].setComponentOffset(0xd09 + (i * 4));
+ }
ApplicationInterruptAndResetControl.r32.setComponentOffset(0xd0c);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3341[i].setComponentOffset(0xd0d + (i * 4));
+ }
SystemControl.r32.setComponentOffset(0xd10);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3345[i].setComponentOffset(0xd11 + (i * 4));
+ }
ConfigurationControl.r32.setComponentOffset(0xd14);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3349[i].setComponentOffset(0xd15 + (i * 4));
+ }
SystemHandlerPriority4.r32.setComponentOffset(0xd18);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3353[i].setComponentOffset(0xd19 + (i * 4));
+ }
SystemHandlerPriority8.r32.setComponentOffset(0xd1c);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3357[i].setComponentOffset(0xd1d + (i * 4));
+ }
SystemHandlerPriority12.r32.setComponentOffset(0xd20);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3361[i].setComponentOffset(0xd21 + (i * 4));
+ }
SystemHandlerControlAndState.r32.setComponentOffset(0xd24);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3365[i].setComponentOffset(0xd25 + (i * 4));
+ }
FaultStatus.r32.setComponentOffset(0xd28);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3369[i].setComponentOffset(0xd29 + (i * 4));
+ }
HardFaultStatus.r32.setComponentOffset(0xd2c);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3373[i].setComponentOffset(0xd2d + (i * 4));
+ }
DebugFaultStatus.r32.setComponentOffset(0xd30);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3377[i].setComponentOffset(0xd31 + (i * 4));
+ }
MemoryManageFaultAddress.r32.setComponentOffset(0xd34);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3381[i].setComponentOffset(0xd35 + (i * 4));
+ }
BusFaultAddress.r32.setComponentOffset(0xd38);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_3385[i].setComponentOffset(0xd39 + (i * 4));
+ }
AuxiliaryFaultAddress.r32.setComponentOffset(0xd3c);
+ for(int i = 0; i < 451; i++)
+ {
+ reserved_3389[i].setComponentOffset(0xd3d + (i * 4));
+ }
SoftwareTriggerInterrupt.r32.setComponentOffset(0xf00);
}
void print()
diff --git a/include/APE_SHM.h b/include/APE_SHM.h
index 13cc624..491083e 100644
--- a/include/APE_SHM.h
+++ b/include/APE_SHM.h
@@ -720,10 +720,35 @@ typedef register_container RegSHMRcpuCfgFeature_t {
} RegSHMRcpuCfgFeature_t;
#define REG_SHM_RCPU_PCI_VENDOR_DEVICE_ID ((volatile APE_SHM_H_uint32_t*)0x60220114) /* Set to PCI Vendor/Device ID by S2. */
+#define SHM_RCPU_PCI_VENDOR_DEVICE_ID_DEVICE_ID_SHIFT 0u
+#define SHM_RCPU_PCI_VENDOR_DEVICE_ID_DEVICE_ID_MASK 0xffffu
+#define GET_SHM_RCPU_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__reg__) (((__reg__) & 0xffff) >> 0u)
+#define SET_SHM_RCPU_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__val__) (((__val__) << 0u) & 0xffffu)
+#define SHM_RCPU_PCI_VENDOR_DEVICE_ID_VENDOR_ID_SHIFT 16u
+#define SHM_RCPU_PCI_VENDOR_DEVICE_ID_VENDOR_ID_MASK 0xffff0000u
+#define GET_SHM_RCPU_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u)
+#define SET_SHM_RCPU_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__val__) (((__val__) << 16u) & 0xffff0000u)
+
/** @brief Register definition for @ref SHM_t.RcpuPciVendorDeviceId. */
typedef register_container RegSHMRcpuPciVendorDeviceId_t {
/** @brief 32bit direct register access. */
APE_SHM_H_uint32_t r32;
+
+ BITFIELD_BEGIN(APE_SHM_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief */
+ BITFIELD_MEMBER(APE_SHM_H_uint32_t, DeviceID, 0, 16)
+ /** @brief */
+ BITFIELD_MEMBER(APE_SHM_H_uint32_t, VendorID, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief */
+ BITFIELD_MEMBER(APE_SHM_H_uint32_t, VendorID, 16, 16)
+ /** @brief */
+ BITFIELD_MEMBER(APE_SHM_H_uint32_t, DeviceID, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(APE_SHM_H_uint32_t, bits)
#ifdef CXX_SIMULATOR
/** @brief Register name for use with the simulator. */
const char* getName(void) { return "RcpuPciVendorDeviceId"; }
@@ -735,6 +760,10 @@ typedef register_container RegSHMRcpuPciVendorDeviceId_t {
{
/** @brief constructor for @ref SHM_t.RcpuPciVendorDeviceId. */
r32.setName("RcpuPciVendorDeviceId");
+ bits.DeviceID.setBaseRegister(&r32);
+ bits.DeviceID.setName("DeviceID");
+ bits.VendorID.setBaseRegister(&r32);
+ bits.VendorID.setName("VendorID");
}
RegSHMRcpuPciVendorDeviceId_t& operator=(const RegSHMRcpuPciVendorDeviceId_t& other)
{
@@ -745,10 +774,35 @@ typedef register_container RegSHMRcpuPciVendorDeviceId_t {
} RegSHMRcpuPciVendorDeviceId_t;
#define REG_SHM_RCPU_PCI_SUBSYSTEM_ID ((volatile APE_SHM_H_uint32_t*)0x60220118) /* Set to PCI Subsystem Vendor/Subsystem ID by S2. */
+#define SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0u
+#define SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_MASK 0xffffu
+#define GET_SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__reg__) (((__reg__) & 0xffff) >> 0u)
+#define SET_SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__val__) (((__val__) << 0u) & 0xffffu)
+#define SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_SHIFT 16u
+#define SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_MASK 0xffff0000u
+#define GET_SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u)
+#define SET_SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__val__) (((__val__) << 16u) & 0xffff0000u)
+
/** @brief Register definition for @ref SHM_t.RcpuPciSubsystemId. */
typedef register_container RegSHMRcpuPciSubsystemId_t {
/** @brief 32bit direct register access. */
APE_SHM_H_uint32_t r32;
+
+ BITFIELD_BEGIN(APE_SHM_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief */
+ BITFIELD_MEMBER(APE_SHM_H_uint32_t, SubsystemVendorID, 0, 16)
+ /** @brief */
+ BITFIELD_MEMBER(APE_SHM_H_uint32_t, SubsystemID, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief */
+ BITFIELD_MEMBER(APE_SHM_H_uint32_t, SubsystemID, 16, 16)
+ /** @brief */
+ BITFIELD_MEMBER(APE_SHM_H_uint32_t, SubsystemVendorID, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(APE_SHM_H_uint32_t, bits)
#ifdef CXX_SIMULATOR
/** @brief Register name for use with the simulator. */
const char* getName(void) { return "RcpuPciSubsystemId"; }
@@ -760,6 +814,10 @@ typedef register_container RegSHMRcpuPciSubsystemId_t {
{
/** @brief constructor for @ref SHM_t.RcpuPciSubsystemId. */
r32.setName("RcpuPciSubsystemId");
+ bits.SubsystemVendorID.setBaseRegister(&r32);
+ bits.SubsystemVendorID.setName("SubsystemVendorID");
+ bits.SubsystemID.setBaseRegister(&r32);
+ bits.SubsystemID.setName("SubsystemID");
}
RegSHMRcpuPciSubsystemId_t& operator=(const RegSHMRcpuPciSubsystemId_t& other)
{
@@ -1760,6 +1818,10 @@ typedef struct SHM_t {
{
SegSig.r32.setComponentOffset(0x0);
ApeSegLength.r32.setComponentOffset(0x4);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_8[i].setComponentOffset(0x8 + (i * 4));
+ }
FwStatus.r32.setComponentOffset(0xc);
FwFeatures.r32.setComponentOffset(0x10);
_4014.r32.setComponentOffset(0x14);
@@ -1768,9 +1830,17 @@ typedef struct SHM_t {
SegMessageBufferLength.r32.setComponentOffset(0x20);
_4024.r32.setComponentOffset(0x24);
_4028.r32.setComponentOffset(0x28);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_44[i].setComponentOffset(0x2c + (i * 4));
+ }
LoaderCommand.r32.setComponentOffset(0x38);
LoaderArg0.r32.setComponentOffset(0x3c);
LoaderArg1.r32.setComponentOffset(0x40);
+ for(int i = 0; i < 47; i++)
+ {
+ reserved_68[i].setComponentOffset(0x44 + (i * 4));
+ }
RcpuSegSig.r32.setComponentOffset(0x100);
RcpuSegLength.r32.setComponentOffset(0x104);
RcpuInitCount.r32.setComponentOffset(0x108);
@@ -1784,6 +1854,10 @@ typedef struct SHM_t {
RcpuCfgHw.r32.setComponentOffset(0x128);
RcpuCfgHw2.r32.setComponentOffset(0x12c);
RcpuCpmuStatus.r32.setComponentOffset(0x130);
+ for(int i = 0; i < 51; i++)
+ {
+ reserved_308[i].setComponentOffset(0x134 + (i * 4));
+ }
HostSegSig.r32.setComponentOffset(0x200);
HostSegLen.r32.setComponentOffset(0x204);
HostInitCount.r32.setComponentOffset(0x208);
@@ -1792,18 +1866,46 @@ typedef struct SHM_t {
HeartbeatInterval.r32.setComponentOffset(0x214);
HeartbeatCount.r32.setComponentOffset(0x218);
HostDriverState.r32.setComponentOffset(0x21c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_544[i].setComponentOffset(0x220 + (i * 4));
+ }
WolSpeed.r32.setComponentOffset(0x224);
+ for(int i = 0; i < 54; i++)
+ {
+ reserved_552[i].setComponentOffset(0x228 + (i * 4));
+ }
EventStatus.r32.setComponentOffset(0x300);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_772[i].setComponentOffset(0x304 + (i * 4));
+ }
ProtMagic.r32.setComponentOffset(0x308);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_780[i].setComponentOffset(0x30c + (i * 4));
+ }
ProtMac0High.r32.setComponentOffset(0x314);
ProtMac0Low.r32.setComponentOffset(0x318);
+ for(int i = 0; i < 313; i++)
+ {
+ reserved_796[i].setComponentOffset(0x31c + (i * 4));
+ }
NcsiSig.r32.setComponentOffset(0x800);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_2052[i].setComponentOffset(0x804 + (i * 4));
+ }
NcsiBuildTime.r32.setComponentOffset(0x810);
NcsiBuildTime2.r32.setComponentOffset(0x814);
NcsiBuildTime3.r32.setComponentOffset(0x818);
NcsiBuildDate.r32.setComponentOffset(0x81c);
NcsiBuildDate2.r32.setComponentOffset(0x820);
NcsiBuildDate3.r32.setComponentOffset(0x824);
+ for(int i = 0; i < 26; i++)
+ {
+ reserved_2088[i].setComponentOffset(0x828 + (i * 4));
+ }
ChipId.r32.setComponentOffset(0x890);
}
void print()
diff --git a/include/APE_SHM_CHANNEL0.h b/include/APE_SHM_CHANNEL0.h
index cbc6d74..7cecce4 100644
--- a/include/APE_SHM_CHANNEL0.h
+++ b/include/APE_SHM_CHANNEL0.h
@@ -1863,18 +1863,38 @@ typedef struct SHM_CHANNEL_t {
NcsiChannelSetting1.r32.setComponentOffset(0x14);
NcsiChannelSetting2.r32.setComponentOffset(0x18);
NcsiChannelVlan.r32.setComponentOffset(0x1c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_32[i].setComponentOffset(0x20 + (i * 4));
+ }
NcsiChannelAltHostMacHigh.r32.setComponentOffset(0x24);
NcsiChannelAltHostMacMid.r32.setComponentOffset(0x28);
NcsiChannelAltHostMacLow.r32.setComponentOffset(0x2c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_48[i].setComponentOffset(0x30 + (i * 4));
+ }
NcsiChannelMac0High.r32.setComponentOffset(0x34);
NcsiChannelMac0Mid.r32.setComponentOffset(0x38);
NcsiChannelMac0Low.r32.setComponentOffset(0x3c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_64[i].setComponentOffset(0x40 + (i * 4));
+ }
NcsiChannelMac1High.r32.setComponentOffset(0x44);
NcsiChannelMac1Mid.r32.setComponentOffset(0x48);
NcsiChannelMac1Low.r32.setComponentOffset(0x4c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_80[i].setComponentOffset(0x50 + (i * 4));
+ }
NcsiChannelMac2High.r32.setComponentOffset(0x54);
NcsiChannelMac2Mid.r32.setComponentOffset(0x58);
NcsiChannelMac2Low.r32.setComponentOffset(0x5c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_96[i].setComponentOffset(0x60 + (i * 4));
+ }
NcsiChannelMac3High.r32.setComponentOffset(0x64);
NcsiChannelMac3Mid.r32.setComponentOffset(0x68);
NcsiChannelMac3Low.r32.setComponentOffset(0x6c);
@@ -1887,7 +1907,15 @@ typedef struct SHM_CHANNEL_t {
NcsiChannelPxe.r32.setComponentOffset(0x88);
NcsiChannelDropfil.r32.setComponentOffset(0x8c);
NcsiChannelSlink.r32.setComponentOffset(0x90);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_148[i].setComponentOffset(0x94 + (i * 4));
+ }
NcsiChannelDbg.r32.setComponentOffset(0xa0);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_164[i].setComponentOffset(0xa4 + (i * 4));
+ }
NcsiChannelCtrlstatRx.r32.setComponentOffset(0xb0);
NcsiChannelCtrlstatDropped.r32.setComponentOffset(0xb4);
NcsiChannelCtrlstatTypeErr.r32.setComponentOffset(0xb8);
diff --git a/include/bcm5719_APE.h b/include/bcm5719_APE.h
index 0ca359e..d11d2bf 100644
--- a/include/bcm5719_APE.h
+++ b/include/bcm5719_APE.h
@@ -1089,6 +1089,74 @@ typedef register_container RegAPERxPoolRetire_t {
#endif /* CXX_SIMULATOR */
} RegAPERxPoolRetire_t;
+#define REG_APE_RX_POOL_FREE_POINTER_0 ((volatile BCM5719_APE_H_uint32_t*)0xc0010084) /* */
+#define APE_RX_POOL_FREE_POINTER_0_TAIL_SHIFT 0u
+#define APE_RX_POOL_FREE_POINTER_0_TAIL_MASK 0xfffu
+#define GET_APE_RX_POOL_FREE_POINTER_0_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u)
+#define SET_APE_RX_POOL_FREE_POINTER_0_TAIL(__val__) (((__val__) << 0u) & 0xfffu)
+#define APE_RX_POOL_FREE_POINTER_0_HEAD_SHIFT 12u
+#define APE_RX_POOL_FREE_POINTER_0_HEAD_MASK 0xfff000u
+#define GET_APE_RX_POOL_FREE_POINTER_0_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u)
+#define SET_APE_RX_POOL_FREE_POINTER_0_HEAD(__val__) (((__val__) << 12u) & 0xfff000u)
+#define APE_RX_POOL_FREE_POINTER_0_FREE_COUNT_SHIFT 24u
+#define APE_RX_POOL_FREE_POINTER_0_FREE_COUNT_MASK 0x3f000000u
+#define GET_APE_RX_POOL_FREE_POINTER_0_FREE_COUNT(__reg__) (((__reg__) & 0x3f000000) >> 24u)
+#define SET_APE_RX_POOL_FREE_POINTER_0_FREE_COUNT(__val__) (((__val__) << 24u) & 0x3f000000u)
+
+/** @brief Register definition for @ref APE_t.RxPoolFreePointer0. */
+typedef register_container RegAPERxPoolFreePointer_t {
+ /** @brief 32bit direct register access. */
+ BCM5719_APE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FreeCount, 24, 6)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_30, 30, 2)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_30, 30, 2)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FreeCount, 24, 6)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(BCM5719_APE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "RxPoolFreePointer0"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegAPERxPoolFreePointer_t()
+ {
+ /** @brief constructor for @ref APE_t.RxPoolFreePointer0. */
+ r32.setName("RxPoolFreePointer0");
+ bits.Tail.setBaseRegister(&r32);
+ bits.Tail.setName("Tail");
+ bits.Head.setBaseRegister(&r32);
+ bits.Head.setName("Head");
+ bits.FreeCount.setBaseRegister(&r32);
+ bits.FreeCount.setName("FreeCount");
+ }
+ RegAPERxPoolFreePointer_t& operator=(const RegAPERxPoolFreePointer_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegAPERxPoolFreePointer_t;
+
#define REG_APE_RX_POOL_RETIRE_1 ((volatile BCM5719_APE_H_uint32_t*)0xc0010088) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
#define REG_APE_TX_TO_NET_POOL_MODE_STATUS_0 ((volatile BCM5719_APE_H_uint32_t*)0xc001008c) /* */
#define APE_TX_TO_NET_POOL_MODE_STATUS_0_HALT_SHIFT 0u
@@ -1338,6 +1406,7 @@ typedef register_container RegAPETxToNetBufferRing_t {
#endif /* CXX_SIMULATOR */
} RegAPETxToNetBufferRing_t;
+#define REG_APE_RX_POOL_FREE_POINTER_1 ((volatile BCM5719_APE_H_uint32_t*)0xc001009c) /* */
#define REG_APE_TICK_1MHZ ((volatile BCM5719_APE_H_uint32_t*)0xc00100a8) /* Unknown, monotonically increasing value. Increases at a rate of 1MHz. */
/** @brief Register definition for @ref APE_t.Tick1mhz. */
typedef register_container RegAPETick1mhz_t {
@@ -1894,6 +1963,7 @@ typedef register_container RegAPECpuStatus_t {
#define REG_APE_TX_TO_NET_DOORBELL_FUNC2 ((volatile BCM5719_APE_H_uint32_t*)0xc0010204) /* Written on APE TX to network after filling 0xA002 buffer with packet. */
#define REG_APE_RX_POOL_MODE_STATUS_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0010214) /* */
#define REG_APE_RX_POOL_RETIRE_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0010218) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
+#define REG_APE_RX_POOL_FREE_POINTER_2 ((volatile BCM5719_APE_H_uint32_t*)0xc001021c) /* */
#define REG_APE_TX_TO_NET_POOL_MODE_STATUS_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0010220) /* */
#define REG_APE_TX_TO_NET_BUFFER_ALLOCATOR_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0010224) /* */
#define REG_APE_TX_TO_NET_BUFFER_RETURN_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0010228) /* */
@@ -1902,6 +1972,7 @@ typedef register_container RegAPECpuStatus_t {
#define REG_APE_TX_TO_NET_DOORBELL_FUNC3 ((volatile BCM5719_APE_H_uint32_t*)0xc0010304) /* Written on APE TX to network after filling 0xA002 buffer with packet. */
#define REG_APE_RX_POOL_MODE_STATUS_3 ((volatile BCM5719_APE_H_uint32_t*)0xc0010314) /* */
#define REG_APE_RX_POOL_RETIRE_3 ((volatile BCM5719_APE_H_uint32_t*)0xc0010318) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
+#define REG_APE_RX_POOL_FREE_POINTER_3 ((volatile BCM5719_APE_H_uint32_t*)0xc001031c) /* */
#define REG_APE_TX_TO_NET_POOL_MODE_STATUS_3 ((volatile BCM5719_APE_H_uint32_t*)0xc0010320) /* */
#define REG_APE_TX_TO_NET_BUFFER_ALLOCATOR_3 ((volatile BCM5719_APE_H_uint32_t*)0xc0010324) /* */
#define REG_APE_TX_TO_NET_BUFFER_RETURN_3 ((volatile BCM5719_APE_H_uint32_t*)0xc0010328) /* */
@@ -1962,8 +2033,8 @@ typedef struct APE_t {
/** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
RegAPERxPoolRetire_t RxPoolRetire0;
- /** @brief Reserved bytes to pad out data structure. */
- BCM5719_APE_H_uint32_t reserved_132[1];
+ /** @brief */
+ RegAPERxPoolFreePointer_t RxPoolFreePointer0;
/** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
RegAPERxPoolRetire_t RxPoolRetire1;
@@ -1980,8 +2051,11 @@ typedef struct APE_t {
/** @brief */
RegAPETxToNetBufferRing_t TxToNetBufferRing0;
+ /** @brief */
+ RegAPERxPoolFreePointer_t RxPoolFreePointer1;
+
/** @brief Reserved bytes to pad out data structure. */
- BCM5719_APE_H_uint32_t reserved_156[3];
+ BCM5719_APE_H_uint32_t reserved_160[2];
/** @brief Unknown, monotonically increasing value. Increases at a rate of 1MHz. */
RegAPETick1mhz_t Tick1mhz;
@@ -2061,8 +2135,8 @@ typedef struct APE_t {
/** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
RegAPERxPoolRetire_t RxPoolRetire2;
- /** @brief Reserved bytes to pad out data structure. */
- BCM5719_APE_H_uint32_t reserved_540[1];
+ /** @brief */
+ RegAPERxPoolFreePointer_t RxPoolFreePointer2;
/** @brief */
RegAPETxToNetPoolModeStatus_t TxToNetPoolModeStatus2;
@@ -2094,8 +2168,8 @@ typedef struct APE_t {
/** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */
RegAPERxPoolRetire_t RxPoolRetire3;
- /** @brief Reserved bytes to pad out data structure. */
- BCM5719_APE_H_uint32_t reserved_796[1];
+ /** @brief */
+ RegAPERxPoolFreePointer_t RxPoolFreePointer3;
/** @brief */
RegAPETxToNetPoolModeStatus_t TxToNetPoolModeStatus3;
@@ -2116,6 +2190,10 @@ typedef struct APE_t {
Status.r32.setComponentOffset(0x4);
GpioMessage.r32.setComponentOffset(0x8);
Event.r32.setComponentOffset(0xc);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_16[i].setComponentOffset(0x10 + (i * 4));
+ }
RxbufoffsetFunc0.r32.setName("RxbufoffsetFunc0");
RxbufoffsetFunc0.r32.setComponentOffset(0x14);
RxbufoffsetFunc1.r32.setName("RxbufoffsetFunc1");
@@ -2123,15 +2201,29 @@ typedef struct APE_t {
TxToNetDoorbellFunc0.r32.setName("TxToNetDoorbellFunc0");
TxToNetDoorbellFunc0.r32.setComponentOffset(0x1c);
TxState0.r32.setComponentOffset(0x20);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_36[i].setComponentOffset(0x24 + (i * 4));
+ }
Mode2.r32.setComponentOffset(0x2c);
Status2.r32.setComponentOffset(0x30);
+ for(int i = 0; i < 6; i++)
+ {
+ reserved_52[i].setComponentOffset(0x34 + (i * 4));
+ }
LockGrantObsolete.r32.setComponentOffset(0x4c);
+ for(int i = 0; i < 10; i++)
+ {
+ reserved_80[i].setComponentOffset(0x50 + (i * 4));
+ }
RxPoolModeStatus0.r32.setName("RxPoolModeStatus0");
RxPoolModeStatus0.r32.setComponentOffset(0x78);
RxPoolModeStatus1.r32.setName("RxPoolModeStatus1");
RxPoolModeStatus1.r32.setComponentOffset(0x7c);
RxPoolRetire0.r32.setName("RxPoolRetire0");
RxPoolRetire0.r32.setComponentOffset(0x80);
+ RxPoolFreePointer0.r32.setName("RxPoolFreePointer0");
+ RxPoolFreePointer0.r32.setComponentOffset(0x84);
RxPoolRetire1.r32.setName("RxPoolRetire1");
RxPoolRetire1.r32.setComponentOffset(0x88);
TxToNetPoolModeStatus0.r32.setName("TxToNetPoolModeStatus0");
@@ -2142,16 +2234,42 @@ typedef struct APE_t {
TxToNetBufferReturn0.r32.setComponentOffset(0x94);
TxToNetBufferRing0.r32.setName("TxToNetBufferRing0");
TxToNetBufferRing0.r32.setComponentOffset(0x98);
+ RxPoolFreePointer1.r32.setName("RxPoolFreePointer1");
+ RxPoolFreePointer1.r32.setComponentOffset(0x9c);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_160[i].setComponentOffset(0xa0 + (i * 4));
+ }
Tick1mhz.r32.setComponentOffset(0xa8);
Tick1khz.r32.setComponentOffset(0xac);
Tick10hz.r32.setComponentOffset(0xb0);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_180[i].setComponentOffset(0xb4 + (i * 4));
+ }
Gpio.r32.setComponentOffset(0xb8);
Gint.r32.setComponentOffset(0xbc);
+ for(int i = 0; i < 10; i++)
+ {
+ reserved_192[i].setComponentOffset(0xc0 + (i * 4));
+ }
OtpControl.r32.setComponentOffset(0xe8);
OtpStatus.r32.setComponentOffset(0xec);
OtpAddr.r32.setComponentOffset(0xf0);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_244[i].setComponentOffset(0xf4 + (i * 4));
+ }
OtpReadData.r32.setComponentOffset(0xf8);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_252[i].setComponentOffset(0xfc + (i * 4));
+ }
CpuStatus.r32.setComponentOffset(0x108);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_268[i].setComponentOffset(0x10c + (i * 4));
+ }
TxToNetPoolModeStatus1.r32.setName("TxToNetPoolModeStatus1");
TxToNetPoolModeStatus1.r32.setComponentOffset(0x110);
TxToNetBufferAllocator1.r32.setName("TxToNetBufferAllocator1");
@@ -2162,14 +2280,24 @@ typedef struct APE_t {
TxToNetBufferRing1.r32.setComponentOffset(0x11c);
TxToNetDoorbellFunc1.r32.setName("TxToNetDoorbellFunc1");
TxToNetDoorbellFunc1.r32.setComponentOffset(0x120);
+ for(int i = 0; i < 55; i++)
+ {
+ reserved_292[i].setComponentOffset(0x124 + (i * 4));
+ }
RxbufoffsetFunc2.r32.setName("RxbufoffsetFunc2");
RxbufoffsetFunc2.r32.setComponentOffset(0x200);
TxToNetDoorbellFunc2.r32.setName("TxToNetDoorbellFunc2");
TxToNetDoorbellFunc2.r32.setComponentOffset(0x204);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_520[i].setComponentOffset(0x208 + (i * 4));
+ }
RxPoolModeStatus2.r32.setName("RxPoolModeStatus2");
RxPoolModeStatus2.r32.setComponentOffset(0x214);
RxPoolRetire2.r32.setName("RxPoolRetire2");
RxPoolRetire2.r32.setComponentOffset(0x218);
+ RxPoolFreePointer2.r32.setName("RxPoolFreePointer2");
+ RxPoolFreePointer2.r32.setComponentOffset(0x21c);
TxToNetPoolModeStatus2.r32.setName("TxToNetPoolModeStatus2");
TxToNetPoolModeStatus2.r32.setComponentOffset(0x220);
TxToNetBufferAllocator2.r32.setName("TxToNetBufferAllocator2");
@@ -2178,14 +2306,24 @@ typedef struct APE_t {
TxToNetBufferReturn2.r32.setComponentOffset(0x228);
TxToNetBufferRing2.r32.setName("TxToNetBufferRing2");
TxToNetBufferRing2.r32.setComponentOffset(0x22c);
+ for(int i = 0; i < 52; i++)
+ {
+ reserved_560[i].setComponentOffset(0x230 + (i * 4));
+ }
RxbufoffsetFunc3.r32.setName("RxbufoffsetFunc3");
RxbufoffsetFunc3.r32.setComponentOffset(0x300);
TxToNetDoorbellFunc3.r32.setName("TxToNetDoorbellFunc3");
TxToNetDoorbellFunc3.r32.setComponentOffset(0x304);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_776[i].setComponentOffset(0x308 + (i * 4));
+ }
RxPoolModeStatus3.r32.setName("RxPoolModeStatus3");
RxPoolModeStatus3.r32.setComponentOffset(0x314);
RxPoolRetire3.r32.setName("RxPoolRetire3");
RxPoolRetire3.r32.setComponentOffset(0x318);
+ RxPoolFreePointer3.r32.setName("RxPoolFreePointer3");
+ RxPoolFreePointer3.r32.setComponentOffset(0x31c);
TxToNetPoolModeStatus3.r32.setName("TxToNetPoolModeStatus3");
TxToNetPoolModeStatus3.r32.setComponentOffset(0x320);
TxToNetBufferAllocator3.r32.setName("TxToNetBufferAllocator3");
@@ -2227,18 +2365,16 @@ typedef struct APE_t {
RxPoolModeStatus0.print();
RxPoolModeStatus1.print();
RxPoolRetire0.print();
- for(int i = 0; i < 1; i++)
- {
- reserved_132[i].print();
- }
+ RxPoolFreePointer0.print();
RxPoolRetire1.print();
TxToNetPoolModeStatus0.print();
TxToNetBufferAllocator0.print();
TxToNetBufferReturn0.print();
TxToNetBufferRing0.print();
- for(int i = 0; i < 3; i++)
+ RxPoolFreePointer1.print();
+ for(int i = 0; i < 2; i++)
{
- reserved_156[i].print();
+ reserved_160[i].print();
}
Tick1mhz.print();
Tick1khz.print();
@@ -2287,10 +2423,7 @@ typedef struct APE_t {
}
RxPoolModeStatus2.print();
RxPoolRetire2.print();
- for(int i = 0; i < 1; i++)
- {
- reserved_540[i].print();
- }
+ RxPoolFreePointer2.print();
TxToNetPoolModeStatus2.print();
TxToNetBufferAllocator2.print();
TxToNetBufferReturn2.print();
@@ -2307,10 +2440,7 @@ typedef struct APE_t {
}
RxPoolModeStatus3.print();
RxPoolRetire3.print();
- for(int i = 0; i < 1; i++)
- {
- reserved_796[i].print();
- }
+ RxPoolFreePointer3.print();
TxToNetPoolModeStatus3.print();
TxToNetBufferAllocator3.print();
TxToNetBufferReturn3.print();
diff --git a/include/bcm5719_APE_PERI.h b/include/bcm5719_APE_PERI.h
index 148b721..2d4c67f 100644
--- a/include/bcm5719_APE_PERI.h
+++ b/include/bcm5719_APE_PERI.h
@@ -1216,6 +1216,56 @@ typedef register_container RegAPE_PERIBmcToNcRxControl_t {
#endif /* CXX_SIMULATOR */
} RegAPE_PERIBmcToNcRxControl_t;
+#define REG_APE_PERI_BMC_TO_NC_RX_STATUS_1 ((volatile BCM5719_APE_PERI_H_uint32_t*)0xc0018358) /* */
+/** @brief Register definition for @ref APE_PERI_t.BmcToNcRxStatus1. */
+typedef register_container RegAPE_PERIBmcToNcRxStatus1_t {
+ /** @brief 32bit direct register access. */
+ BCM5719_APE_PERI_H_uint32_t r32;
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "BmcToNcRxStatus1"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegAPE_PERIBmcToNcRxStatus1_t()
+ {
+ /** @brief constructor for @ref APE_PERI_t.BmcToNcRxStatus1. */
+ r32.setName("BmcToNcRxStatus1");
+ }
+ RegAPE_PERIBmcToNcRxStatus1_t& operator=(const RegAPE_PERIBmcToNcRxStatus1_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegAPE_PERIBmcToNcRxStatus1_t;
+
+#define REG_APE_PERI_BMC_TO_NC_RX_STATUS_2 ((volatile BCM5719_APE_PERI_H_uint32_t*)0xc001835c) /* */
+/** @brief Register definition for @ref APE_PERI_t.BmcToNcRxStatus2. */
+typedef register_container RegAPE_PERIBmcToNcRxStatus2_t {
+ /** @brief 32bit direct register access. */
+ BCM5719_APE_PERI_H_uint32_t r32;
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "BmcToNcRxStatus2"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegAPE_PERIBmcToNcRxStatus2_t()
+ {
+ /** @brief constructor for @ref APE_PERI_t.BmcToNcRxStatus2. */
+ r32.setName("BmcToNcRxStatus2");
+ }
+ RegAPE_PERIBmcToNcRxStatus2_t& operator=(const RegAPE_PERIBmcToNcRxStatus2_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegAPE_PERIBmcToNcRxStatus2_t;
+
#define REG_APE_PERI_BMC_TO_NC_TX_STATUS ((volatile BCM5719_APE_PERI_H_uint32_t*)0xc0018370) /* */
#define APE_PERI_BMC_TO_NC_TX_STATUS_UNDERRUN_SHIFT 0u
#define APE_PERI_BMC_TO_NC_TX_STATUS_UNDERRUN_MASK 0x1u
@@ -1514,6 +1564,31 @@ typedef register_container RegAPE_PERIBmcToNcTxBufferLast_t {
#endif /* CXX_SIMULATOR */
} RegAPE_PERIBmcToNcTxBufferLast_t;
+#define REG_APE_PERI_BMC_TO_NC_TX_STATUS_1 ((volatile BCM5719_APE_PERI_H_uint32_t*)0xc0018380) /* */
+/** @brief Register definition for @ref APE_PERI_t.BmcToNcTxStatus1. */
+typedef register_container RegAPE_PERIBmcToNcTxStatus1_t {
+ /** @brief 32bit direct register access. */
+ BCM5719_APE_PERI_H_uint32_t r32;
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "BmcToNcTxStatus1"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegAPE_PERIBmcToNcTxStatus1_t()
+ {
+ /** @brief constructor for @ref APE_PERI_t.BmcToNcTxStatus1. */
+ r32.setName("BmcToNcTxStatus1");
+ }
+ RegAPE_PERIBmcToNcTxStatus1_t& operator=(const RegAPE_PERIBmcToNcTxStatus1_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegAPE_PERIBmcToNcTxStatus1_t;
+
#define REG_APE_PERI_RMU_CONTROL ((volatile BCM5719_APE_PERI_H_uint32_t*)0xc00183a0) /* */
#define APE_PERI_RMU_CONTROL_RESET_TX_SHIFT 0u
#define APE_PERI_RMU_CONTROL_RESET_TX_MASK 0x1u
@@ -3443,8 +3518,14 @@ typedef struct APE_PERI_t {
/** @brief */
RegAPE_PERIBmcToNcRxControl_t BmcToNcRxControl;
+ /** @brief */
+ RegAPE_PERIBmcToNcRxStatus1_t BmcToNcRxStatus1;
+
+ /** @brief */
+ RegAPE_PERIBmcToNcRxStatus2_t BmcToNcRxStatus2;
+
/** @brief Reserved bytes to pad out data structure. */
- BCM5719_APE_PERI_H_uint32_t reserved_856[6];
+ BCM5719_APE_PERI_H_uint32_t reserved_864[4];
/** @brief */
RegAPE_PERIBmcToNcTxStatus_t BmcToNcTxStatus;
@@ -3458,8 +3539,11 @@ typedef struct APE_PERI_t {
/** @brief */
RegAPE_PERIBmcToNcTxBufferLast_t BmcToNcTxBufferLast;
+ /** @brief */
+ RegAPE_PERIBmcToNcTxStatus1_t BmcToNcTxStatus1;
+
/** @brief Reserved bytes to pad out data structure. */
- BCM5719_APE_PERI_H_uint32_t reserved_896[8];
+ BCM5719_APE_PERI_H_uint32_t reserved_900[7];
/** @brief */
RegAPE_PERIRmuControl_t RmuControl;
@@ -3521,6 +3605,10 @@ typedef struct APE_PERI_t {
#ifdef CXX_SIMULATOR
APE_PERI_t()
{
+ for(int i = 0; i < 192; i++)
+ {
+ reserved_0[i].setComponentOffset(0x0 + (i * 4));
+ }
BmcToNcRxStatus.r32.setComponentOffset(0x300);
BmcToNcSourceMacHigh.r32.setComponentOffset(0x304);
BmcToNcSourceMacLow.r32.setComponentOffset(0x308);
@@ -3543,12 +3631,27 @@ typedef struct APE_PERI_t {
BmcToNcRxVlan.r32.setComponentOffset(0x34c);
BmcToNcReadBuffer.r32.setComponentOffset(0x350);
BmcToNcRxControl.r32.setComponentOffset(0x354);
+ BmcToNcRxStatus1.r32.setComponentOffset(0x358);
+ BmcToNcRxStatus2.r32.setComponentOffset(0x35c);
+ for(int i = 0; i < 4; i++)
+ {
+ reserved_864[i].setComponentOffset(0x360 + (i * 4));
+ }
BmcToNcTxStatus.r32.setComponentOffset(0x370);
BmcToNcTxControl.r32.setComponentOffset(0x374);
BmcToNcTxBuffer.r32.setComponentOffset(0x378);
BmcToNcTxBufferLast.r32.setComponentOffset(0x37c);
+ BmcToNcTxStatus1.r32.setComponentOffset(0x380);
+ for(int i = 0; i < 7; i++)
+ {
+ reserved_900[i].setComponentOffset(0x384 + (i * 4));
+ }
RmuControl.r32.setComponentOffset(0x3a0);
ArbControl.r32.setComponentOffset(0x3a4);
+ for(int i = 0; i < 22; i++)
+ {
+ reserved_936[i].setComponentOffset(0x3a8 + (i * 4));
+ }
PerLockRequestPhy0.r32.setComponentOffset(0x400);
PerLockRequestGrc.r32.setComponentOffset(0x404);
PerLockRequestPhy1.r32.setComponentOffset(0x408);
@@ -3594,17 +3697,20 @@ typedef struct APE_PERI_t {
BmcToNcRxVlan.print();
BmcToNcReadBuffer.print();
BmcToNcRxControl.print();
- for(int i = 0; i < 6; i++)
+ BmcToNcRxStatus1.print();
+ BmcToNcRxStatus2.print();
+ for(int i = 0; i < 4; i++)
{
- reserved_856[i].print();
+ reserved_864[i].print();
}
BmcToNcTxStatus.print();
BmcToNcTxControl.print();
BmcToNcTxBuffer.print();
BmcToNcTxBufferLast.print();
- for(int i = 0; i < 8; i++)
+ BmcToNcTxStatus1.print();
+ for(int i = 0; i < 7; i++)
{
- reserved_896[i].print();
+ reserved_900[i].print();
}
RmuControl.print();
ArbControl.print();
diff --git a/include/bcm5719_DEVICE.h b/include/bcm5719_DEVICE.h
index e5a6a17..bf16a68 100644
--- a/include/bcm5719_DEVICE.h
+++ b/include/bcm5719_DEVICE.h
@@ -714,6 +714,31 @@ typedef register_container RegDEVICEApeMemoryData_t {
#endif /* CXX_SIMULATOR */
} RegDEVICEApeMemoryData_t;
+#define REG_DEVICE_160 ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0000160) /* Unknown register. */
+/** @brief Register definition for @ref DEVICE_t.160. */
+typedef register_container RegDEVICE160_t {
+ /** @brief 32bit direct register access. */
+ BCM5719_DEVICE_H_uint32_t r32;
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "160"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegDEVICE160_t()
+ {
+ /** @brief constructor for @ref DEVICE_t.160. */
+ r32.setName("160");
+ }
+ RegDEVICE160_t& operator=(const RegDEVICE160_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegDEVICE160_t;
+
#define REG_DEVICE_EMAC_MODE ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0000400) /* */
#define DEVICE_EMAC_MODE_GLOBAL_RESET_SHIFT 0u
#define DEVICE_EMAC_MODE_GLOBAL_RESET_MASK 0x1u
@@ -1792,6 +1817,31 @@ typedef register_container RegDEVICEWolPatternCfg_t {
#endif /* CXX_SIMULATOR */
} RegDEVICEWolPatternCfg_t;
+#define REG_DEVICE_438 ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0000438) /* Unknown register. */
+/** @brief Register definition for @ref DEVICE_t.438. */
+typedef register_container RegDEVICE438_t {
+ /** @brief 32bit direct register access. */
+ BCM5719_DEVICE_H_uint32_t r32;
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "438"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegDEVICE438_t()
+ {
+ /** @brief constructor for @ref DEVICE_t.438. */
+ r32.setName("438");
+ }
+ RegDEVICE438_t& operator=(const RegDEVICE438_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegDEVICE438_t;
+
#define REG_DEVICE_MTU_SIZE ((volatile BCM5719_DEVICE_H_uint32_t*)0xc000043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */
#define DEVICE_MTU_SIZE_MTU_SHIFT 0u
#define DEVICE_MTU_SIZE_MTU_MASK 0xffffu
@@ -3136,6 +3186,82 @@ typedef register_container RegDEVICECpmuControl_t {
#endif /* CXX_SIMULATOR */
} RegDEVICECpmuControl_t;
+#define REG_DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0003604) /* */
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u
+#define GET_DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u)
+#define SET_DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u)
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_62_5MHZ 0x0u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_60_0MHZ 0x1u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_30_0MHZ 0x3u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_15_0MHZ 0x5u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_7_5MHZ 0x7u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_75MHZ 0x9u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ 0x11u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_6_25MHZ 0x13u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_125MHZ 0x15u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_1_563MHZ 0x17u
+#define DEVICE_NO_LINK_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ_DIV_1_25MHZ 0x1fu
+
+
+/** @brief Register definition for @ref DEVICE_t.NoLinkPowerModeClockPolicy. */
+typedef register_container RegDEVICENoLinkPowerModeClockPolicy_t {
+ /** @brief 32bit direct register access. */
+ BCM5719_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_15_0, 0, 16)
+ /** @brief Software Controlled MAC Core Clock Speed Select. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, MACClockSwitch, 16, 5)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_21, 21, 11)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_21, 21, 11)
+ /** @brief Software Controlled MAC Core Clock Speed Select. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, MACClockSwitch, 16, 5)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_15_0, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(BCM5719_DEVICE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "NoLinkPowerModeClockPolicy"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegDEVICENoLinkPowerModeClockPolicy_t()
+ {
+ /** @brief constructor for @ref DEVICE_t.NoLinkPowerModeClockPolicy. */
+ r32.setName("NoLinkPowerModeClockPolicy");
+ bits.MACClockSwitch.setBaseRegister(&r32);
+ bits.MACClockSwitch.setName("MACClockSwitch");
+ bits.MACClockSwitch.addEnum("62.5MHz", 0x0);
+ bits.MACClockSwitch.addEnum("60.0MHz", 0x1);
+ bits.MACClockSwitch.addEnum("30.0MHz", 0x3);
+ bits.MACClockSwitch.addEnum("15.0MHz", 0x5);
+ bits.MACClockSwitch.addEnum("7.5MHz", 0x7);
+ bits.MACClockSwitch.addEnum("3.75MHz", 0x9);
+ bits.MACClockSwitch.addEnum("12.5MHz", 0x11);
+ bits.MACClockSwitch.addEnum("6.25MHz", 0x13);
+ bits.MACClockSwitch.addEnum("3.125MHz", 0x15);
+ bits.MACClockSwitch.addEnum("1.563MHz", 0x17);
+ bits.MACClockSwitch.addEnum("12.5MHz/1.25MHz", 0x1f);
+
+ }
+ RegDEVICENoLinkPowerModeClockPolicy_t& operator=(const RegDEVICENoLinkPowerModeClockPolicy_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegDEVICENoLinkPowerModeClockPolicy_t;
+
#define REG_DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0003610) /* */
#define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u
#define DEVICE_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u
@@ -3540,6 +3666,14 @@ typedef register_container RegDEVICEClockStatus_t {
#define DEVICE_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_MASK 0x8000u
#define GET_DEVICE_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x8000) >> 15u)
#define SET_DEVICE_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 15u) & 0x8000u)
+#define DEVICE_GPHY_CONTROL_STATUS_PCIE_PLL_LOCK_STATUS_SHIFT 22u
+#define DEVICE_GPHY_CONTROL_STATUS_PCIE_PLL_LOCK_STATUS_MASK 0x400000u
+#define GET_DEVICE_GPHY_CONTROL_STATUS_PCIE_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x400000) >> 22u)
+#define SET_DEVICE_GPHY_CONTROL_STATUS_PCIE_PLL_LOCK_STATUS(__val__) (((__val__) << 22u) & 0x400000u)
+#define DEVICE_GPHY_CONTROL_STATUS_GPHY_PLL_LOCK_STATUS_SHIFT 23u
+#define DEVICE_GPHY_CONTROL_STATUS_GPHY_PLL_LOCK_STATUS_MASK 0x800000u
+#define GET_DEVICE_GPHY_CONTROL_STATUS_GPHY_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x800000) >> 23u)
+#define SET_DEVICE_GPHY_CONTROL_STATUS_GPHY_PLL_LOCK_STATUS(__val__) (((__val__) << 23u) & 0x800000u)
#define DEVICE_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_SHIFT 25u
#define DEVICE_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_MASK 0x2000000u
#define GET_DEVICE_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x2000000) >> 25u)
@@ -3552,6 +3686,10 @@ typedef register_container RegDEVICEClockStatus_t {
#define DEVICE_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_MASK 0x8000000u
#define GET_DEVICE_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__reg__) (((__reg__) & 0x8000000) >> 27u)
#define SET_DEVICE_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__val__) (((__val__) << 27u) & 0x8000000u)
+#define DEVICE_GPHY_CONTROL_STATUS_KEEP_NCSI_PLL_ON_DURING_LOW_POWER_MODE__SHIFT 28u
+#define DEVICE_GPHY_CONTROL_STATUS_KEEP_NCSI_PLL_ON_DURING_LOW_POWER_MODE__MASK 0x10000000u
+#define GET_DEVICE_GPHY_CONTROL_STATUS_KEEP_NCSI_PLL_ON_DURING_LOW_POWER_MODE_(__reg__) (((__reg__) & 0x10000000) >> 28u)
+#define SET_DEVICE_GPHY_CONTROL_STATUS_KEEP_NCSI_PLL_ON_DURING_LOW_POWER_MODE_(__val__) (((__val__) << 28u) & 0x10000000u)
/** @brief Register definition for @ref DEVICE_t.GphyControlStatus. */
typedef register_container RegDEVICEGphyControlStatus_t {
@@ -3568,25 +3706,35 @@ typedef register_container RegDEVICEGphyControlStatus_t {
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, CPMUSoftwareReset, 2, 1)
/** @brief Software reset for resetting all the registers to default. */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, CPMURegisterSoftwareReset, 3, 1)
- /** @brief */
+ /** @brief Force CPMU into Low Power State, LAN function will be powered down (GPHY, PCIE, IPSEC, APE). This bit is cleared by a rising edge of PERST_L. */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, PowerDown, 4, 1)
/** @brief Padding */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_14_5, 5, 10)
/** @brief Setting this bit will powerdown SGMII-PCS module. */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, SGMII_DIV_PCSPowerDown, 15, 1)
/** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_24_16, 16, 9)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_21_16, 16, 6)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, PCIePLLLockStatus, 22, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPHYPLLLockStatus, 23, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_24_24, 24, 1)
/** @brief */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, NCSIPLLLockStatus, 25, 1)
/** @brief */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, TLPClockSource, 26, 1)
/** @brief */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, SwitchingRegulatorPowerDown, 27, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, KeepNCSIPLLonduringlowpowermode_, 28, 1)
/** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_28, 28, 4)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_29, 29, 3)
#elif defined(__BIG_ENDIAN__)
/** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_28, 28, 4)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_29, 29, 3)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, KeepNCSIPLLonduringlowpowermode_, 28, 1)
/** @brief */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, SwitchingRegulatorPowerDown, 27, 1)
/** @brief */
@@ -3594,12 +3742,18 @@ typedef register_container RegDEVICEGphyControlStatus_t {
/** @brief */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, NCSIPLLLockStatus, 25, 1)
/** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_24_16, 16, 9)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_24_24, 24, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPHYPLLLockStatus, 23, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, PCIePLLLockStatus, 22, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_21_16, 16, 6)
/** @brief Setting this bit will powerdown SGMII-PCS module. */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, SGMII_DIV_PCSPowerDown, 15, 1)
/** @brief Padding */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_14_5, 5, 10)
- /** @brief */
+ /** @brief Force CPMU into Low Power State, LAN function will be powered down (GPHY, PCIE, IPSEC, APE). This bit is cleared by a rising edge of PERST_L. */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, PowerDown, 4, 1)
/** @brief Software reset for resetting all the registers to default. */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, CPMURegisterSoftwareReset, 3, 1)
@@ -3636,12 +3790,18 @@ typedef register_container RegDEVICEGphyControlStatus_t {
bits.PowerDown.setName("PowerDown");
bits.SGMII_DIV_PCSPowerDown.setBaseRegister(&r32);
bits.SGMII_DIV_PCSPowerDown.setName("SGMII_DIV_PCSPowerDown");
+ bits.PCIePLLLockStatus.setBaseRegister(&r32);
+ bits.PCIePLLLockStatus.setName("PCIePLLLockStatus");
+ bits.GPHYPLLLockStatus.setBaseRegister(&r32);
+ bits.GPHYPLLLockStatus.setName("GPHYPLLLockStatus");
bits.NCSIPLLLockStatus.setBaseRegister(&r32);
bits.NCSIPLLLockStatus.setName("NCSIPLLLockStatus");
bits.TLPClockSource.setBaseRegister(&r32);
bits.TLPClockSource.setName("TLPClockSource");
bits.SwitchingRegulatorPowerDown.setBaseRegister(&r32);
bits.SwitchingRegulatorPowerDown.setName("SwitchingRegulatorPowerDown");
+ bits.KeepNCSIPLLonduringlowpowermode_.setBaseRegister(&r32);
+ bits.KeepNCSIPLLonduringlowpowermode_.setName("KeepNCSIPLLonduringlowpowermode_");
}
RegDEVICEGphyControlStatus_t& operator=(const RegDEVICEGphyControlStatus_t& other)
{
@@ -3677,10 +3837,31 @@ typedef register_container RegDEVICEChipId_t {
} RegDEVICEChipId_t;
#define REG_DEVICE_MUTEX_REQUEST ((volatile BCM5719_DEVICE_H_uint32_t*)0xc000365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
+#define DEVICE_MUTEX_REQUEST_REQUEST_SHIFT 0u
+#define DEVICE_MUTEX_REQUEST_REQUEST_MASK 0xffffu
+#define GET_DEVICE_MUTEX_REQUEST_REQUEST(__reg__) (((__reg__) & 0xffff) >> 0u)
+#define SET_DEVICE_MUTEX_REQUEST_REQUEST(__val__) (((__val__) << 0u) & 0xffffu)
+
/** @brief Register definition for @ref DEVICE_t.MutexRequest. */
typedef register_container RegDEVICEMutexRequest_t {
/** @brief 32bit direct register access. */
BCM5719_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, Request, 0, 16)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+ /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, Request, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(BCM5719_DEVICE_H_uint32_t, bits)
#ifdef CXX_SIMULATOR
/** @brief Register name for use with the simulator. */
const char* getName(void) { return "MutexRequest"; }
@@ -3692,6 +3873,8 @@ typedef register_container RegDEVICEMutexRequest_t {
{
/** @brief constructor for @ref DEVICE_t.MutexRequest. */
r32.setName("MutexRequest");
+ bits.Request.setBaseRegister(&r32);
+ bits.Request.setName("Request");
}
RegDEVICEMutexRequest_t& operator=(const RegDEVICEMutexRequest_t& other)
{
@@ -3702,10 +3885,31 @@ typedef register_container RegDEVICEMutexRequest_t {
} RegDEVICEMutexRequest_t;
#define REG_DEVICE_MUTEX_GRANT ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0003660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
+#define DEVICE_MUTEX_GRANT_GRANTED_SHIFT 0u
+#define DEVICE_MUTEX_GRANT_GRANTED_MASK 0xffffu
+#define GET_DEVICE_MUTEX_GRANT_GRANTED(__reg__) (((__reg__) & 0xffff) >> 0u)
+#define SET_DEVICE_MUTEX_GRANT_GRANTED(__val__) (((__val__) << 0u) & 0xffffu)
+
/** @brief Register definition for @ref DEVICE_t.MutexGrant. */
typedef register_container RegDEVICEMutexGrant_t {
/** @brief 32bit direct register access. */
BCM5719_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, Granted, 0, 16)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+ /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, Granted, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(BCM5719_DEVICE_H_uint32_t, bits)
#ifdef CXX_SIMULATOR
/** @brief Register name for use with the simulator. */
const char* getName(void) { return "MutexGrant"; }
@@ -3717,6 +3921,8 @@ typedef register_container RegDEVICEMutexGrant_t {
{
/** @brief constructor for @ref DEVICE_t.MutexGrant. */
r32.setName("MutexGrant");
+ bits.Granted.setBaseRegister(&r32);
+ bits.Granted.setName("Granted");
}
RegDEVICEMutexGrant_t& operator=(const RegDEVICEMutexGrant_t& other)
{
@@ -3739,6 +3945,10 @@ typedef register_container RegDEVICEMutexGrant_t {
#define DEVICE_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_MASK 0x10u
#define GET_DEVICE_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u)
#define SET_DEVICE_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__val__) (((__val__) << 4u) & 0x10u)
+#define DEVICE_GPHY_STRAP_APE_CM3_BIG_ENDIAN_ENABLE_SHIFT 8u
+#define DEVICE_GPHY_STRAP_APE_CM3_BIG_ENDIAN_ENABLE_MASK 0x100u
+#define GET_DEVICE_GPHY_STRAP_APE_CM3_BIG_ENDIAN_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u)
+#define SET_DEVICE_GPHY_STRAP_APE_CM3_BIG_ENDIAN_ENABLE(__val__) (((__val__) << 8u) & 0x100u)
/** @brief Register definition for @ref DEVICE_t.GphyStrap. */
typedef register_container RegDEVICEGphyStrap_t {
@@ -3756,10 +3966,18 @@ typedef register_container RegDEVICEGphyStrap_t {
/** @brief Enable ECC for rxcpu scratchpad. */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, RXCPUSPADECCEnable, 4, 1)
/** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_5, 5, 27)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_7_5, 5, 3)
+ /** @brief Enable APE CM3 Big Endian Setting */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, APECM3BigEndianEnable, 8, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_9, 9, 23)
#elif defined(__BIG_ENDIAN__)
/** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_5, 5, 27)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_9, 9, 23)
+ /** @brief Enable APE CM3 Big Endian Setting */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, APECM3BigEndianEnable, 8, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_7_5, 5, 3)
/** @brief Enable ECC for rxcpu scratchpad. */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, RXCPUSPADECCEnable, 4, 1)
/** @brief Enable RXMBUF ECC. */
@@ -3789,6 +4007,8 @@ typedef register_container RegDEVICEGphyStrap_t {
bits.RXMBUFECCEnable.setName("RXMBUFECCEnable");
bits.RXCPUSPADECCEnable.setBaseRegister(&r32);
bits.RXCPUSPADECCEnable.setName("RXCPUSPADECCEnable");
+ bits.APECM3BigEndianEnable.setBaseRegister(&r32);
+ bits.APECM3BigEndianEnable.setName("APECM3BigEndianEnable");
}
RegDEVICEGphyStrap_t& operator=(const RegDEVICEGphyStrap_t& other)
{
@@ -3798,6 +4018,166 @@ typedef register_container RegDEVICEGphyStrap_t {
#endif /* CXX_SIMULATOR */
} RegDEVICEGphyStrap_t;
+#define REG_DEVICE_FLASH_CLOCK_CONTROL_POLICY ((volatile BCM5719_DEVICE_H_uint32_t*)0xc000366c) /* */
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH_SHIFT 0u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH_MASK 0x3u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH(__reg__) (((__reg__) & 0x3) >> 0u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH(__val__) (((__val__) << 0u) & 0x3u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH_62_5_MHZ_NCSI_DLL 0x0u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_OVERRIDE_FLASH_CLOCK_SWITCH_25_MHZ 0x3u
+
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY_SHIFT 4u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY_MASK 0x70u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY(__reg__) (((__reg__) & 0x70) >> 4u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY(__val__) (((__val__) << 4u) & 0x70u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY_62_5_MHZ_NCSI_DLL 0x0u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_POLICY_25_MHZ 0x3u
+
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY_SHIFT 8u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY_MASK 0x700u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY(__reg__) (((__reg__) & 0x700) >> 8u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY(__val__) (((__val__) << 8u) & 0x700u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY_62_5_MHZ_NCSI_DLL 0x0u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_CLOCK_POLICY_25_MHZ 0x3u
+
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_SHIFT 12u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_MASK 0xff000u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY(__reg__) (((__reg__) & 0xff000) >> 12u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY(__val__) (((__val__) << 12u) & 0xff000u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_4_8MHZ 0x0u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_1250_MHZ 0x1u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_EAV_CLOCK_POLICY_125_MHZ 0xau
+
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_EAV_CLOCK_DISABLE_SHIFT 28u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_EAV_CLOCK_DISABLE_MASK 0x10000000u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_EAV_CLOCK_DISABLE(__reg__) (((__reg__) & 0x10000000) >> 28u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_EAV_CLOCK_DISABLE(__val__) (((__val__) << 28u) & 0x10000000u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_MODE_ENABLE_SHIFT 29u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_MODE_ENABLE_MASK 0x20000000u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_MODE_ENABLE(__reg__) (((__reg__) & 0x20000000) >> 29u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_IDLE_MODE_ENABLE(__val__) (((__val__) << 29u) & 0x20000000u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_FLASH_CLOCK_DISABLE_SHIFT 30u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_FLASH_CLOCK_DISABLE_MASK 0x40000000u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_FLASH_CLOCK_DISABLE(__reg__) (((__reg__) & 0x40000000) >> 30u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FORCE_FLASH_CLOCK_DISABLE(__val__) (((__val__) << 30u) & 0x40000000u)
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_SPEED_OVERRIDE_SHIFT 30u
+#define DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_SPEED_OVERRIDE_MASK 0x40000000u
+#define GET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_SPEED_OVERRIDE(__reg__) (((__reg__) & 0x40000000) >> 30u)
+#define SET_DEVICE_FLASH_CLOCK_CONTROL_POLICY_FLASH_CLOCK_SPEED_OVERRIDE(__val__) (((__val__) << 30u) & 0x40000000u)
+
+/** @brief Register definition for @ref DEVICE_t.FlashClockControlPolicy. */
+typedef register_container RegDEVICEFlashClockControlPolicy_t {
+ /** @brief 32bit direct register access. */
+ BCM5719_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief Software Controlled Flash Clock Speed */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, OverrideFlashClockSwitch, 0, 2)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_3_2, 2, 2)
+ /** @brief Software Controlled Flash Clock Speed */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, FlashClockPolicy, 4, 3)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_7_7, 7, 1)
+ /** @brief Software Controlled Flash Clock Speed */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, FlashIdleClockPolicy, 8, 3)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_11_11, 11, 1)
+ /** @brief Software Controlled EAV Clock Speed Select */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, EAVClockPolicy, 12, 8)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_27_20, 20, 8)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, ForceEAVClockDisable, 28, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, FlashIdlemodeEnable, 29, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, ForceFlashClockDisable, 30, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, FlashClockSpeedOverride, 30, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_31, 31, 1)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_31, 31, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, FlashClockSpeedOverride, 30, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, ForceFlashClockDisable, 30, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, FlashIdlemodeEnable, 29, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, ForceEAVClockDisable, 28, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_27_20, 20, 8)
+ /** @brief Software Controlled EAV Clock Speed Select */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, EAVClockPolicy, 12, 8)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_11_11, 11, 1)
+ /** @brief Software Controlled Flash Clock Speed */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, FlashIdleClockPolicy, 8, 3)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_7_7, 7, 1)
+ /** @brief Software Controlled Flash Clock Speed */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, FlashClockPolicy, 4, 3)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_3_2, 2, 2)
+ /** @brief Software Controlled Flash Clock Speed */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, OverrideFlashClockSwitch, 0, 2)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(BCM5719_DEVICE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "FlashClockControlPolicy"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegDEVICEFlashClockControlPolicy_t()
+ {
+ /** @brief constructor for @ref DEVICE_t.FlashClockControlPolicy. */
+ r32.setName("FlashClockControlPolicy");
+ bits.OverrideFlashClockSwitch.setBaseRegister(&r32);
+ bits.OverrideFlashClockSwitch.setName("OverrideFlashClockSwitch");
+ bits.OverrideFlashClockSwitch.addEnum("62.5 MHz NCSI DLL", 0x0);
+ bits.OverrideFlashClockSwitch.addEnum("25 MHz", 0x3);
+
+ bits.FlashClockPolicy.setBaseRegister(&r32);
+ bits.FlashClockPolicy.setName("FlashClockPolicy");
+ bits.FlashClockPolicy.addEnum("62.5 MHz NCSI DLL", 0x0);
+ bits.FlashClockPolicy.addEnum("25 MHz", 0x3);
+
+ bits.FlashIdleClockPolicy.setBaseRegister(&r32);
+ bits.FlashIdleClockPolicy.setName("FlashIdleClockPolicy");
+ bits.FlashIdleClockPolicy.addEnum("62.5 MHz NCSI DLL", 0x0);
+ bits.FlashIdleClockPolicy.addEnum("25 MHz", 0x3);
+
+ bits.EAVClockPolicy.setBaseRegister(&r32);
+ bits.EAVClockPolicy.setName("EAVClockPolicy");
+ bits.EAVClockPolicy.addEnum("4.8MHz", 0x0);
+ bits.EAVClockPolicy.addEnum("1250 MHz", 0x1);
+ bits.EAVClockPolicy.addEnum("125 MHz", 0xa);
+
+ bits.ForceEAVClockDisable.setBaseRegister(&r32);
+ bits.ForceEAVClockDisable.setName("ForceEAVClockDisable");
+ bits.FlashIdlemodeEnable.setBaseRegister(&r32);
+ bits.FlashIdlemodeEnable.setName("FlashIdlemodeEnable");
+ bits.ForceFlashClockDisable.setBaseRegister(&r32);
+ bits.ForceFlashClockDisable.setName("ForceFlashClockDisable");
+ bits.FlashClockSpeedOverride.setBaseRegister(&r32);
+ bits.FlashClockSpeedOverride.setName("FlashClockSpeedOverride");
+ }
+ RegDEVICEFlashClockControlPolicy_t& operator=(const RegDEVICEFlashClockControlPolicy_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegDEVICEFlashClockControlPolicy_t;
+
#define REG_DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile BCM5719_DEVICE_H_uint32_t*)0xc000367c) /* */
#define DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_SHIFT 4u
#define DEVICE_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_MASK 0x10u
@@ -4135,10 +4515,31 @@ typedef register_container RegDEVICEEeeControl_t {
} RegDEVICEEeeControl_t;
#define REG_DEVICE_GLOBAL_MUTEX_REQUEST ((volatile BCM5719_DEVICE_H_uint32_t*)0xc00036f0) /* */
+#define DEVICE_GLOBAL_MUTEX_REQUEST_REQUEST_SHIFT 0u
+#define DEVICE_GLOBAL_MUTEX_REQUEST_REQUEST_MASK 0xffffu
+#define GET_DEVICE_GLOBAL_MUTEX_REQUEST_REQUEST(__reg__) (((__reg__) & 0xffff) >> 0u)
+#define SET_DEVICE_GLOBAL_MUTEX_REQUEST_REQUEST(__val__) (((__val__) << 0u) & 0xffffu)
+
/** @brief Register definition for @ref DEVICE_t.GlobalMutexRequest. */
typedef register_container RegDEVICEGlobalMutexRequest_t {
/** @brief 32bit direct register access. */
BCM5719_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, Request, 0, 16)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+ /** @brief Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, Request, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(BCM5719_DEVICE_H_uint32_t, bits)
#ifdef CXX_SIMULATOR
/** @brief Register name for use with the simulator. */
const char* getName(void) { return "GlobalMutexRequest"; }
@@ -4150,6 +4551,8 @@ typedef register_container RegDEVICEGlobalMutexRequest_t {
{
/** @brief constructor for @ref DEVICE_t.GlobalMutexRequest. */
r32.setName("GlobalMutexRequest");
+ bits.Request.setBaseRegister(&r32);
+ bits.Request.setName("Request");
}
RegDEVICEGlobalMutexRequest_t& operator=(const RegDEVICEGlobalMutexRequest_t& other)
{
@@ -4160,10 +4563,31 @@ typedef register_container RegDEVICEGlobalMutexRequest_t {
} RegDEVICEGlobalMutexRequest_t;
#define REG_DEVICE_GLOBAL_MUTEX_GRANT ((volatile BCM5719_DEVICE_H_uint32_t*)0xc00036f4) /* */
+#define DEVICE_GLOBAL_MUTEX_GRANT_GRANTED_SHIFT 0u
+#define DEVICE_GLOBAL_MUTEX_GRANT_GRANTED_MASK 0xffffu
+#define GET_DEVICE_GLOBAL_MUTEX_GRANT_GRANTED(__reg__) (((__reg__) & 0xffff) >> 0u)
+#define SET_DEVICE_GLOBAL_MUTEX_GRANT_GRANTED(__val__) (((__val__) << 0u) & 0xffffu)
+
/** @brief Register definition for @ref DEVICE_t.GlobalMutexGrant. */
typedef register_container RegDEVICEGlobalMutexGrant_t {
/** @brief 32bit direct register access. */
BCM5719_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, Granted, 0, 16)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_16, 16, 16)
+ /** @brief Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, Granted, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(BCM5719_DEVICE_H_uint32_t, bits)
#ifdef CXX_SIMULATOR
/** @brief Register name for use with the simulator. */
const char* getName(void) { return "GlobalMutexGrant"; }
@@ -4175,6 +4599,8 @@ typedef register_container RegDEVICEGlobalMutexGrant_t {
{
/** @brief constructor for @ref DEVICE_t.GlobalMutexGrant. */
r32.setName("GlobalMutexGrant");
+ bits.Granted.setBaseRegister(&r32);
+ bits.Granted.setName("Granted");
}
RegDEVICEGlobalMutexGrant_t& operator=(const RegDEVICEGlobalMutexGrant_t& other)
{
@@ -4184,6 +4610,98 @@ typedef register_container RegDEVICEGlobalMutexGrant_t {
#endif /* CXX_SIMULATOR */
} RegDEVICEGlobalMutexGrant_t;
+#define REG_DEVICE_TEMPERATURE_MONITOR_CONTROL ((volatile BCM5719_DEVICE_H_uint32_t*)0xc00036fc) /* */
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_ADC_TEST_ENABLE_SHIFT 0u
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_ADC_TEST_ENABLE_MASK 0x1u
+#define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_ADC_TEST_ENABLE(__reg__) (((__reg__) & 0x1) >> 0u)
+#define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_ADC_TEST_ENABLE(__val__) (((__val__) << 0u) & 0x1u)
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_BIAS_ADJUST_SHIFT 1u
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_BIAS_ADJUST_MASK 0xfeu
+#define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_BIAS_ADJUST(__reg__) (((__reg__) & 0xfe) >> 1u)
+#define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_BIAS_ADJUST(__val__) (((__val__) << 1u) & 0xfeu)
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_DATA_SHIFT 8u
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_DATA_MASK 0xff00u
+#define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_DATA(__reg__) (((__reg__) & 0xff00) >> 8u)
+#define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_DATA(__val__) (((__val__) << 8u) & 0xff00u)
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_HOLD_SHIFT 17u
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_HOLD_MASK 0x20000u
+#define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_HOLD(__reg__) (((__reg__) & 0x20000) >> 17u)
+#define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_HOLD(__val__) (((__val__) << 17u) & 0x20000u)
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_POWER_DOWN_SHIFT 18u
+#define DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_POWER_DOWN_MASK 0x40000u
+#define GET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_POWER_DOWN(__reg__) (((__reg__) & 0x40000) >> 18u)
+#define SET_DEVICE_TEMPERATURE_MONITOR_CONTROL_TEMPERATURE_MONITOR_POWER_DOWN(__val__) (((__val__) << 18u) & 0x40000u)
+
+/** @brief Register definition for @ref DEVICE_t.TemperatureMonitorControl. */
+typedef register_container RegDEVICETemperatureMonitorControl_t {
+ /** @brief 32bit direct register access. */
+ BCM5719_DEVICE_H_uint32_t r32;
+
+ BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, ADCTestEnable, 0, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, BiasAdjust, 1, 7)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, TemperatureData, 8, 8)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_16_16, 16, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, TemperatureMonitorHold, 17, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, TemperatureMonitorPowerDown, 18, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_19, 19, 13)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_19, 19, 13)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, TemperatureMonitorPowerDown, 18, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, TemperatureMonitorHold, 17, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_16_16, 16, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, TemperatureData, 8, 8)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, BiasAdjust, 1, 7)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, ADCTestEnable, 0, 1)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(BCM5719_DEVICE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "TemperatureMonitorControl"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegDEVICETemperatureMonitorControl_t()
+ {
+ /** @brief constructor for @ref DEVICE_t.TemperatureMonitorControl. */
+ r32.setName("TemperatureMonitorControl");
+ bits.ADCTestEnable.setBaseRegister(&r32);
+ bits.ADCTestEnable.setName("ADCTestEnable");
+ bits.BiasAdjust.setBaseRegister(&r32);
+ bits.BiasAdjust.setName("BiasAdjust");
+ bits.TemperatureData.setBaseRegister(&r32);
+ bits.TemperatureData.setName("TemperatureData");
+ bits.TemperatureMonitorHold.setBaseRegister(&r32);
+ bits.TemperatureMonitorHold.setName("TemperatureMonitorHold");
+ bits.TemperatureMonitorPowerDown.setBaseRegister(&r32);
+ bits.TemperatureMonitorPowerDown.setName("TemperatureMonitorPowerDown");
+ }
+ RegDEVICETemperatureMonitorControl_t& operator=(const RegDEVICETemperatureMonitorControl_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegDEVICETemperatureMonitorControl_t;
+
#define REG_DEVICE_MEMORY_ARBITER_MODE ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0004000) /* */
#define DEVICE_MEMORY_ARBITER_MODE_ENABLE_SHIFT 1u
#define DEVICE_MEMORY_ARBITER_MODE_ENABLE_MASK 0x2u
@@ -5953,6 +6471,31 @@ typedef register_container RegDEVICE64c0_t {
#endif /* CXX_SIMULATOR */
} RegDEVICE64c0_t;
+#define REG_DEVICE_64C4 ((volatile BCM5719_DEVICE_H_uint32_t*)0xc00064c4) /* */
+/** @brief Register definition for @ref DEVICE_t.64c4. */
+typedef register_container RegDEVICE64c4_t {
+ /** @brief 32bit direct register access. */
+ BCM5719_DEVICE_H_uint32_t r32;
+#ifdef CXX_SIMULATOR
+ /** @brief Register name for use with the simulator. */
+ const char* getName(void) { return "64c4"; }
+
+ /** @brief Print register value. */
+ void print(void) { r32.print(); }
+
+ RegDEVICE64c4_t()
+ {
+ /** @brief constructor for @ref DEVICE_t.64c4. */
+ r32.setName("64c4");
+ }
+ RegDEVICE64c4_t& operator=(const RegDEVICE64c4_t& other)
+ {
+ r32 = other.r32;
+ return *this;
+ }
+#endif /* CXX_SIMULATOR */
+} RegDEVICE64c4_t;
+
#define REG_DEVICE_64C8 ((volatile BCM5719_DEVICE_H_uint32_t*)0xc00064c8) /* */
/** @brief Register definition for @ref DEVICE_t.64c8. */
typedef register_container RegDEVICE64c8_t {
@@ -7249,6 +7792,10 @@ typedef register_container RegDEVICE65f4_t {
} RegDEVICE65f4_t;
#define REG_DEVICE_GRC_MODE_CONTROL ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0006800) /* */
+#define DEVICE_GRC_MODE_CONTROL_HOST_STACK_UP_SHIFT 16u
+#define DEVICE_GRC_MODE_CONTROL_HOST_STACK_UP_MASK 0x10000u
+#define GET_DEVICE_GRC_MODE_CONTROL_HOST_STACK_UP(__reg__) (((__reg__) & 0x10000) >> 16u)
+#define SET_DEVICE_GRC_MODE_CONTROL_HOST_STACK_UP(__val__) (((__val__) << 16u) & 0x10000u)
#define DEVICE_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_SHIFT 19u
#define DEVICE_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_MASK 0x80000u
#define GET_DEVICE_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u)
@@ -7278,7 +7825,11 @@ typedef register_container RegDEVICEGrcModeControl_t {
BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits)
#if defined(__LITTLE_ENDIAN__)
/** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_18_0, 0, 19)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_15_0, 0, 16)
+ /** @brief The host stack is ready to receive data from the NIC. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, HostStackUp, 16, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_18_17, 17, 2)
/** @brief Write 1 to this bit to enable Time Sync Mode. */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, TimeSyncModeEnable, 19, 1)
/** @brief Padding */
@@ -7313,7 +7864,11 @@ typedef register_container RegDEVICEGrcModeControl_t {
/** @brief Write 1 to this bit to enable Time Sync Mode. */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, TimeSyncModeEnable, 19, 1)
/** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_18_0, 0, 19)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_18_17, 17, 2)
+ /** @brief The host stack is ready to receive data from the NIC. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, HostStackUp, 16, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_15_0, 0, 16)
#else
#error Unknown Endian
#endif
@@ -7329,6 +7884,8 @@ typedef register_container RegDEVICEGrcModeControl_t {
{
/** @brief constructor for @ref DEVICE_t.GrcModeControl. */
r32.setName("GrcModeControl");
+ bits.HostStackUp.setBaseRegister(&r32);
+ bits.HostStackUp.setName("HostStackUp");
bits.TimeSyncModeEnable.setBaseRegister(&r32);
bits.TimeSyncModeEnable.setName("TimeSyncModeEnable");
bits.NVRAMWriteEnable.setBaseRegister(&r32);
@@ -7349,14 +7906,39 @@ typedef register_container RegDEVICEGrcModeControl_t {
} RegDEVICEGrcModeControl_t;
#define REG_DEVICE_MISCELLANEOUS_CONFIG ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0006804) /* */
-#define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 1u
-#define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x2u
-#define GET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x2) >> 1u)
-#define SET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 1u) & 0x2u)
-#define DEVICE_MISCELLANEOUS_CONFIG_ALL_SHIFT 1u
-#define DEVICE_MISCELLANEOUS_CONFIG_ALL_MASK 0xfffffffeu
-#define GET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__reg__) (((__reg__) & 0xfffffffe) >> 1u)
-#define SET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__val__) (((__val__) << 1u) & 0xfffffffeu)
+#define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 0u
+#define DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x1u
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x1) >> 0u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 0u) & 0x1u)
+#define DEVICE_MISCELLANEOUS_CONFIG_TIMER_PRESCALER_SHIFT 1u
+#define DEVICE_MISCELLANEOUS_CONFIG_TIMER_PRESCALER_MASK 0xfeu
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_TIMER_PRESCALER(__reg__) (((__reg__) & 0xfe) >> 1u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_TIMER_PRESCALER(__val__) (((__val__) << 1u) & 0xfeu)
+#define DEVICE_MISCELLANEOUS_CONFIG_BOND_ID_SHIFT 13u
+#define DEVICE_MISCELLANEOUS_CONFIG_BOND_ID_MASK 0x1e000u
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_BOND_ID(__reg__) (((__reg__) & 0x1e000) >> 13u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_BOND_ID(__val__) (((__val__) << 13u) & 0x1e000u)
+#define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_SHIFT 17u
+#define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_MASK 0x60000u
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE(__reg__) (((__reg__) & 0x60000) >> 17u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE(__val__) (((__val__) << 17u) & 0x60000u)
+#define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_D0 0x0u
+#define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_D1 0x1u
+#define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_D2 0x2u
+#define DEVICE_MISCELLANEOUS_CONFIG_POWER_STATE_D3 0x3u
+
+#define DEVICE_MISCELLANEOUS_CONFIG_PME_EN_STATE_SHIFT 19u
+#define DEVICE_MISCELLANEOUS_CONFIG_PME_EN_STATE_MASK 0x80000u
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_PME_EN_STATE(__reg__) (((__reg__) & 0x80000) >> 19u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_PME_EN_STATE(__val__) (((__val__) << 19u) & 0x80000u)
+#define DEVICE_MISCELLANEOUS_CONFIG_POWERDOWN_SHIFT 20u
+#define DEVICE_MISCELLANEOUS_CONFIG_POWERDOWN_MASK 0x100000u
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_POWERDOWN(__reg__) (((__reg__) & 0x100000) >> 20u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_POWERDOWN(__val__) (((__val__) << 20u) & 0x100000u)
+#define DEVICE_MISCELLANEOUS_CONFIG_DISABLE_GRC_RESET_SHIFT 29u
+#define DEVICE_MISCELLANEOUS_CONFIG_DISABLE_GRC_RESET_MASK 0x20000000u
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_DISABLE_GRC_RESET(__reg__) (((__reg__) & 0x20000000) >> 29u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_DISABLE_GRC_RESET(__val__) (((__val__) << 29u) & 0x20000000u)
/** @brief Register definition for @ref DEVICE_t.MiscellaneousConfig. */
typedef register_container RegDEVICEMiscellaneousConfig_t {
@@ -7365,19 +7947,47 @@ typedef register_container RegDEVICEMiscellaneousConfig_t {
BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits)
#if defined(__LITTLE_ENDIAN__)
+ /** @brief Write 1 to this bit resets the CORE_CLK blocks in the device. This is a self-clearing bit. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GRCReset, 0, 1)
+ /** @brief Local Core clock frequency in MHz, minus 1, which should correspond to each advance of the timer. Reset to all 1. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, TimerPrescaler, 1, 7)
/** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_0_0, 0, 1)
- /** @brief */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GRCReset, 1, 1)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_12_8, 8, 5)
/** @brief */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, all, 1, 31)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, BondID, 13, 4)
+ /** @brief Indicates the current power state of the device. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, PowerState, 17, 2)
+ /** @brief State of PME Enable for this device. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, PMEENState, 19, 1)
+ /** @brief Setting this bit will power down the device (power consumption is ~20 mW). This bit is cleared by PCI reset. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, Powerdown, 20, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_28_21, 21, 8)
+ /** @brief Setting this bit will prevent reset to PCIE block. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, DisableGRCReset, 29, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_30, 30, 2)
#elif defined(__BIG_ENDIAN__)
- /** @brief */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, all, 1, 31)
- /** @brief */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GRCReset, 1, 1)
/** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_0_0, 0, 1)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_30, 30, 2)
+ /** @brief Setting this bit will prevent reset to PCIE block. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, DisableGRCReset, 29, 1)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_28_21, 21, 8)
+ /** @brief Setting this bit will power down the device (power consumption is ~20 mW). This bit is cleared by PCI reset. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, Powerdown, 20, 1)
+ /** @brief State of PME Enable for this device. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, PMEENState, 19, 1)
+ /** @brief Indicates the current power state of the device. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, PowerState, 17, 2)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, BondID, 13, 4)
+ /** @brief Padding */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_12_8, 8, 5)
+ /** @brief Local Core clock frequency in MHz, minus 1, which should correspond to each advance of the timer. Reset to all 1. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, TimerPrescaler, 1, 7)
+ /** @brief Write 1 to this bit resets the CORE_CLK blocks in the device. This is a self-clearing bit. */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GRCReset, 0, 1)
#else
#error Unknown Endian
#endif
@@ -7395,8 +8005,23 @@ typedef register_container RegDEVICEMiscellaneousConfig_t {
r32.setName("MiscellaneousConfig");
bits.GRCReset.setBaseRegister(&r32);
bits.GRCReset.setName("GRCReset");
- bits.all.setBaseRegister(&r32);
- bits.all.setName("all");
+ bits.TimerPrescaler.setBaseRegister(&r32);
+ bits.TimerPrescaler.setName("TimerPrescaler");
+ bits.BondID.setBaseRegister(&r32);
+ bits.BondID.setName("BondID");
+ bits.PowerState.setBaseRegister(&r32);
+ bits.PowerState.setName("PowerState");
+ bits.PowerState.addEnum("D0", 0x0);
+ bits.PowerState.addEnum("D1", 0x1);
+ bits.PowerState.addEnum("D2", 0x2);
+ bits.PowerState.addEnum("D3", 0x3);
+
+ bits.PMEENState.setBaseRegister(&r32);
+ bits.PMEENState.setName("PMEENState");
+ bits.Powerdown.setBaseRegister(&r32);
+ bits.Powerdown.setName("Powerdown");
+ bits.DisableGRCReset.setBaseRegister(&r32);
+ bits.DisableGRCReset.setName("DisableGRCReset");
}
RegDEVICEMiscellaneousConfig_t& operator=(const RegDEVICEMiscellaneousConfig_t& other)
{
@@ -7407,6 +8032,18 @@ typedef register_container RegDEVICEMiscellaneousConfig_t {
} RegDEVICEMiscellaneousConfig_t;
#define REG_DEVICE_MISCELLANEOUS_LOCAL_CONTROL ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0006808) /* */
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_INPUT_SHIFT 5u
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_INPUT_MASK 0x20u
+#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_INPUT(__reg__) (((__reg__) & 0x20) >> 5u)
+#define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_INPUT(__val__) (((__val__) << 5u) & 0x20u)
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_ENABLE_SHIFT 6u
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_ENABLE_MASK 0x40u
+#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x40) >> 6u)
+#define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_ENABLE(__val__) (((__val__) << 6u) & 0x40u)
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_SHIFT 7u
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT_MASK 0x80u
+#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT(__reg__) (((__reg__) & 0x80) >> 7u)
+#define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_3_OUTPUT(__val__) (((__val__) << 7u) & 0x80u)
#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_SHIFT 8u
#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_MASK 0x100u
#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__reg__) (((__reg__) & 0x100) >> 8u)
@@ -7443,6 +8080,10 @@ typedef register_container RegDEVICEMiscellaneousConfig_t {
#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_MASK 0x10000u
#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__reg__) (((__reg__) & 0x10000) >> 16u)
#define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__val__) (((__val__) << 16u) & 0x10000u)
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_APE_GPIO_IN_SHIFT 17u
+#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_APE_GPIO_IN_MASK 0xfe0000u
+#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_APE_GPIO_IN(__reg__) (((__reg__) & 0xfe0000) >> 17u)
+#define SET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_APE_GPIO_IN(__val__) (((__val__) << 17u) & 0xfe0000u)
#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_SHIFT 24u
#define DEVICE_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_MASK 0x1000000u
#define GET_DEVICE_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__reg__) (((__reg__) & 0x1000000) >> 24u)
@@ -7456,7 +8097,13 @@ typedef register_container RegDEVICEMiscellaneousLocalControl_t {
BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits)
#if defined(__LITTLE_ENDIAN__)
/** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_7_0, 0, 8)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_4_0, 0, 5)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPIO3Input, 5, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPIO3OutputEnable, 6, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPIO3Output, 7, 1)
/** @brief */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPIO0Input, 8, 1)
/** @brief */
@@ -7475,8 +8122,8 @@ typedef register_container RegDEVICEMiscellaneousLocalControl_t {
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPIO1Output, 15, 1)
/** @brief */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPIO2Output, 16, 1)
- /** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_23_17, 17, 7)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, APEGPIOIn, 17, 7)
/** @brief */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, AutoSEEPROMAccess, 24, 1)
/** @brief Padding */
@@ -7486,8 +8133,8 @@ typedef register_container RegDEVICEMiscellaneousLocalControl_t {
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_31_25, 25, 7)
/** @brief */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, AutoSEEPROMAccess, 24, 1)
- /** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_23_17, 17, 7)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, APEGPIOIn, 17, 7)
/** @brief */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPIO2Output, 16, 1)
/** @brief */
@@ -7506,8 +8153,14 @@ typedef register_container RegDEVICEMiscellaneousLocalControl_t {
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPIO1Input, 9, 1)
/** @brief */
BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPIO0Input, 8, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPIO3Output, 7, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPIO3OutputEnable, 6, 1)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, GPIO3Input, 5, 1)
/** @brief Padding */
- BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_7_0, 0, 8)
+ BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, reserved_4_0, 0, 5)
#else
#error Unknown Endian
#endif
@@ -7523,6 +8176,12 @@ typedef register_container RegDEVICEMiscellaneousLocalControl_t {
{
/** @brief constructor for @ref DEVICE_t.MiscellaneousLocalControl. */
r32.setName("MiscellaneousLocalControl");
+ bits.GPIO3Input.setBaseRegister(&r32);
+ bits.GPIO3Input.setName("GPIO3Input");
+ bits.GPIO3OutputEnable.setBaseRegister(&r32);
+ bits.GPIO3OutputEnable.setName("GPIO3OutputEnable");
+ bits.GPIO3Output.setBaseRegister(&r32);
+ bits.GPIO3Output.setName("GPIO3Output");
bits.GPIO0Input.setBaseRegister(&r32);
bits.GPIO0Input.setName("GPIO0Input");
bits.GPIO1Input.setBaseRegister(&r32);
@@ -7541,6 +8200,8 @@ typedef register_container RegDEVICEMiscellaneousLocalControl_t {
bits.GPIO1Output.setName("GPIO1Output");
bits.GPIO2Output.setBaseRegister(&r32);
bits.GPIO2Output.setName("GPIO2Output");
+ bits.APEGPIOIn.setBaseRegister(&r32);
+ bits.APEGPIOIn.setName("APEGPIOIn");
bits.AutoSEEPROMAccess.setBaseRegister(&r32);
bits.AutoSEEPROMAccess.setName("AutoSEEPROMAccess");
}
@@ -8095,7 +8756,13 @@ typedef struct DEVICE_t {
RegDEVICEApeMemoryData_t ApeMemoryData;
/** @brief Reserved bytes to pad out data structure. */
- BCM5719_DEVICE_H_uint32_t reserved_256[192];
+ BCM5719_DEVICE_H_uint32_t reserved_256[24];
+
+ /** @brief Unknown register. */
+ RegDEVICE160_t _160;
+
+ /** @brief Reserved bytes to pad out data structure. */
+ BCM5719_DEVICE_H_uint32_t reserved_356[167];
/** @brief */
RegDEVICEEmacMode_t EmacMode;
@@ -8139,8 +8806,8 @@ typedef struct DEVICE_t {
/** @brief */
RegDEVICEWolPatternCfg_t WolPatternCfg;
- /** @brief Reserved bytes to pad out data structure. */
- BCM5719_DEVICE_H_uint32_t reserved_1080[1];
+ /** @brief Unknown register. */
+ RegDEVICE438_t _438;
/** @brief 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */
RegDEVICEMtuSize_t MtuSize;
@@ -8214,8 +8881,11 @@ typedef struct DEVICE_t {
/** @brief */
RegDEVICECpmuControl_t CpmuControl;
+ /** @brief */
+ RegDEVICENoLinkPowerModeClockPolicy_t NoLinkPowerModeClockPolicy;
+
/** @brief Reserved bytes to pad out data structure. */
- BCM5719_DEVICE_H_uint32_t reserved_13828[3];
+ BCM5719_DEVICE_H_uint32_t reserved_13832[2];
/** @brief */
RegDEVICELinkAwarePowerModeClockPolicy_t LinkAwarePowerModeClockPolicy;
@@ -8257,7 +8927,13 @@ typedef struct DEVICE_t {
RegDEVICEGphyStrap_t GphyStrap;
/** @brief Reserved bytes to pad out data structure. */
- BCM5719_DEVICE_H_uint32_t reserved_13928[5];
+ BCM5719_DEVICE_H_uint32_t reserved_13928[1];
+
+ /** @brief */
+ RegDEVICEFlashClockControlPolicy_t FlashClockControlPolicy;
+
+ /** @brief Reserved bytes to pad out data structure. */
+ BCM5719_DEVICE_H_uint32_t reserved_13936[3];
/** @brief */
RegDEVICETopLevelMiscellaneousControl1_t TopLevelMiscellaneousControl1;
@@ -8290,7 +8966,13 @@ typedef struct DEVICE_t {
RegDEVICEGlobalMutexGrant_t GlobalMutexGrant;
/** @brief Reserved bytes to pad out data structure. */
- BCM5719_DEVICE_H_uint32_t reserved_14072[578];
+ BCM5719_DEVICE_H_uint32_t reserved_14072[1];
+
+ /** @brief */
+ RegDEVICETemperatureMonitorControl_t TemperatureMonitorControl;
+
+ /** @brief Reserved bytes to pad out data structure. */
+ BCM5719_DEVICE_H_uint32_t reserved_14080[576];
/** @brief */
RegDEVICEMemoryArbiterMode_t MemoryArbiterMode;
@@ -8469,8 +9151,8 @@ typedef struct DEVICE_t {
/** @brief */
RegDEVICE64c0_t _64c0;
- /** @brief Reserved bytes to pad out data structure. */
- BCM5719_DEVICE_H_uint32_t reserved_25796[1];
+ /** @brief */
+ RegDEVICE64c4_t _64c4;
/** @brief */
RegDEVICE64c8_t _64c8;
@@ -8598,16 +9280,49 @@ typedef struct DEVICE_t {
#ifdef CXX_SIMULATOR
DEVICE_t()
{
+ for(int i = 0; i < 26; i++)
+ {
+ reserved_0[i].setComponentOffset(0x0 + (i * 4));
+ }
MiscellaneousHostControl.r32.setComponentOffset(0x68);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_108[i].setComponentOffset(0x6c + (i * 4));
+ }
PciState.r32.setComponentOffset(0x70);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_116[i].setComponentOffset(0x74 + (i * 4));
+ }
RegisterBase.r32.setComponentOffset(0x78);
MemoryBase.r32.setComponentOffset(0x7c);
RegisterData.r32.setComponentOffset(0x80);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_132[i].setComponentOffset(0x84 + (i * 4));
+ }
UndiReceiveReturnRingConsumerIndex.r32.setComponentOffset(0x88);
UndiReceiveReturnRingConsumerIndexLow.r32.setComponentOffset(0x8c);
+ for(int i = 0; i < 11; i++)
+ {
+ reserved_144[i].setComponentOffset(0x90 + (i * 4));
+ }
LinkStatusControl.r32.setComponentOffset(0xbc);
+ for(int i = 0; i < 14; i++)
+ {
+ reserved_192[i].setComponentOffset(0xc0 + (i * 4));
+ }
ApeMemoryBase.r32.setComponentOffset(0xf8);
ApeMemoryData.r32.setComponentOffset(0xfc);
+ for(int i = 0; i < 24; i++)
+ {
+ reserved_256[i].setComponentOffset(0x100 + (i * 4));
+ }
+ _160.r32.setComponentOffset(0x160);
+ for(int i = 0; i < 167; i++)
+ {
+ reserved_356[i].setComponentOffset(0x164 + (i * 4));
+ }
EmacMode.r32.setComponentOffset(0x400);
EmacStatus.r32.setComponentOffset(0x404);
EmacEvent.r32.setComponentOffset(0x408);
@@ -8622,13 +9337,34 @@ typedef struct DEVICE_t {
EmacMacAddresses3Low.r32.setComponentOffset(0x42c);
WolPatternPointer.r32.setComponentOffset(0x430);
WolPatternCfg.r32.setComponentOffset(0x434);
+ _438.r32.setComponentOffset(0x438);
MtuSize.r32.setComponentOffset(0x43c);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_1088[i].setComponentOffset(0x440 + (i * 4));
+ }
MiiCommunication.r32.setComponentOffset(0x44c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_1104[i].setComponentOffset(0x450 + (i * 4));
+ }
MiiMode.r32.setComponentOffset(0x454);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_1112[i].setComponentOffset(0x458 + (i * 4));
+ }
TransmitMacMode.r32.setComponentOffset(0x45c);
TransmitMacStatus.r32.setComponentOffset(0x460);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_1124[i].setComponentOffset(0x464 + (i * 4));
+ }
ReceiveMacMode.r32.setComponentOffset(0x468);
ReceiveMacStatus.r32.setComponentOffset(0x46c);
+ for(int i = 0; i < 52; i++)
+ {
+ reserved_1136[i].setComponentOffset(0x470 + (i * 4));
+ }
PerfectMatch1High.r32.setComponentOffset(0x540);
PerfectMatch1Low.r32.setComponentOffset(0x544);
PerfectMatch2High.r32.setComponentOffset(0x548);
@@ -8637,31 +9373,118 @@ typedef struct DEVICE_t {
PerfectMatch3Low.r32.setComponentOffset(0x554);
PerfectMatch4High.r32.setComponentOffset(0x558);
PerfectMatch4Low.r32.setComponentOffset(0x55c);
+ for(int i = 0; i < 21; i++)
+ {
+ reserved_1376[i].setComponentOffset(0x560 + (i * 4));
+ }
SgmiiStatus.r32.setComponentOffset(0x5b4);
+ for(int i = 0; i < 3090; i++)
+ {
+ reserved_1464[i].setComponentOffset(0x5b8 + (i * 4));
+ }
CpmuControl.r32.setComponentOffset(0x3600);
+ NoLinkPowerModeClockPolicy.r32.setComponentOffset(0x3604);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_13832[i].setComponentOffset(0x3608 + (i * 4));
+ }
LinkAwarePowerModeClockPolicy.r32.setComponentOffset(0x3610);
+ for(int i = 0; i < 4; i++)
+ {
+ reserved_13844[i].setComponentOffset(0x3614 + (i * 4));
+ }
ClockSpeedOverridePolicy.r32.setComponentOffset(0x3624);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_13864[i].setComponentOffset(0x3628 + (i * 4));
+ }
Status.r32.setComponentOffset(0x362c);
ClockStatus.r32.setComponentOffset(0x3630);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_13876[i].setComponentOffset(0x3634 + (i * 4));
+ }
GphyControlStatus.r32.setComponentOffset(0x3638);
+ for(int i = 0; i < 7; i++)
+ {
+ reserved_13884[i].setComponentOffset(0x363c + (i * 4));
+ }
ChipId.r32.setComponentOffset(0x3658);
MutexRequest.r32.setComponentOffset(0x365c);
MutexGrant.r32.setComponentOffset(0x3660);
GphyStrap.r32.setComponentOffset(0x3664);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_13928[i].setComponentOffset(0x3668 + (i * 4));
+ }
+ FlashClockControlPolicy.r32.setComponentOffset(0x366c);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_13936[i].setComponentOffset(0x3670 + (i * 4));
+ }
TopLevelMiscellaneousControl1.r32.setComponentOffset(0x367c);
+ for(int i = 0; i < 12; i++)
+ {
+ reserved_13952[i].setComponentOffset(0x3680 + (i * 4));
+ }
EeeMode.r32.setComponentOffset(0x36b0);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_14004[i].setComponentOffset(0x36b4 + (i * 4));
+ }
EeeLinkIdleControl.r32.setComponentOffset(0x36bc);
+ for(int i = 0; i < 4; i++)
+ {
+ reserved_14016[i].setComponentOffset(0x36c0 + (i * 4));
+ }
EeeControl.r32.setComponentOffset(0x36d0);
+ for(int i = 0; i < 7; i++)
+ {
+ reserved_14036[i].setComponentOffset(0x36d4 + (i * 4));
+ }
GlobalMutexRequest.r32.setComponentOffset(0x36f0);
GlobalMutexGrant.r32.setComponentOffset(0x36f4);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_14072[i].setComponentOffset(0x36f8 + (i * 4));
+ }
+ TemperatureMonitorControl.r32.setComponentOffset(0x36fc);
+ for(int i = 0; i < 576; i++)
+ {
+ reserved_14080[i].setComponentOffset(0x3700 + (i * 4));
+ }
MemoryArbiterMode.r32.setComponentOffset(0x4000);
+ for(int i = 0; i < 255; i++)
+ {
+ reserved_16388[i].setComponentOffset(0x4004 + (i * 4));
+ }
BufferManagerMode.r32.setComponentOffset(0x4400);
+ for(int i = 0; i < 323; i++)
+ {
+ reserved_17412[i].setComponentOffset(0x4404 + (i * 4));
+ }
LsoNonlsoBdReadDmaCorruptionEnableControl.r32.setComponentOffset(0x4910);
+ for(int i = 0; i < 443; i++)
+ {
+ reserved_18708[i].setComponentOffset(0x4914 + (i * 4));
+ }
RxRiscMode.r32.setComponentOffset(0x5000);
RxRiscStatus.r32.setComponentOffset(0x5004);
+ for(int i = 0; i < 5; i++)
+ {
+ reserved_20488[i].setComponentOffset(0x5008 + (i * 4));
+ }
RxRiscProgramCounter.r32.setComponentOffset(0x501c);
RxRiscCurrentInstruction.r32.setComponentOffset(0x5020);
+ for(int i = 0; i < 4; i++)
+ {
+ reserved_20516[i].setComponentOffset(0x5024 + (i * 4));
+ }
RxRiscHardwareBreakpoint.r32.setComponentOffset(0x5034);
+ for(int i = 0; i < 114; i++)
+ {
+ reserved_20536[i].setComponentOffset(0x5038 + (i * 4));
+ }
RxRiscRegister0.r32.setComponentOffset(0x5200);
RxRiscRegister1.r32.setComponentOffset(0x5204);
RxRiscRegister2.r32.setComponentOffset(0x5208);
@@ -8694,19 +9517,48 @@ typedef struct DEVICE_t {
RxRiscRegister29.r32.setComponentOffset(0x5274);
RxRiscRegister30.r32.setComponentOffset(0x5278);
RxRiscRegister31.r32.setComponentOffset(0x527c);
+ for(int i = 0; i < 1122; i++)
+ {
+ reserved_21120[i].setComponentOffset(0x5280 + (i * 4));
+ }
_6408.r32.setComponentOffset(0x6408);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_25612[i].setComponentOffset(0x640c + (i * 4));
+ }
PciPowerConsumptionInfo.r32.setComponentOffset(0x6410);
PciPowerDissipatedInfo.r32.setComponentOffset(0x6414);
+ for(int i = 0; i < 5; i++)
+ {
+ reserved_25624[i].setComponentOffset(0x6418 + (i * 4));
+ }
PciVpdRequest.r32.setComponentOffset(0x642c);
PciVpdResponse.r32.setComponentOffset(0x6430);
PciVendorDeviceId.r32.setComponentOffset(0x6434);
PciSubsystemId.r32.setComponentOffset(0x6438);
PciClassCodeRevision.r32.setComponentOffset(0x643c);
+ for(int i = 0; i < 32; i++)
+ {
+ reserved_25664[i].setComponentOffset(0x6440 + (i * 4));
+ }
_64c0.r32.setComponentOffset(0x64c0);
+ _64c4.r32.setComponentOffset(0x64c4);
_64c8.r32.setComponentOffset(0x64c8);
+ for(int i = 0; i < 4; i++)
+ {
+ reserved_25804[i].setComponentOffset(0x64cc + (i * 4));
+ }
_64dc.r32.setComponentOffset(0x64dc);
+ for(int i = 0; i < 9; i++)
+ {
+ reserved_25824[i].setComponentOffset(0x64e0 + (i * 4));
+ }
PciSerialNumberLow.r32.setComponentOffset(0x6504);
PciSerialNumberHigh.r32.setComponentOffset(0x6508);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_25868[i].setComponentOffset(0x650c + (i * 4));
+ }
PciPowerBudget0.r32.setComponentOffset(0x6510);
PciPowerBudget1.r32.setComponentOffset(0x6514);
PciPowerBudget2.r32.setComponentOffset(0x6518);
@@ -8716,20 +9568,60 @@ typedef struct DEVICE_t {
PciPowerBudget6.r32.setComponentOffset(0x6528);
PciPowerBudget7.r32.setComponentOffset(0x652c);
_6530.r32.setComponentOffset(0x6530);
+ for(int i = 0; i < 7; i++)
+ {
+ reserved_25908[i].setComponentOffset(0x6534 + (i * 4));
+ }
_6550.r32.setComponentOffset(0x6550);
+ for(int i = 0; i < 40; i++)
+ {
+ reserved_25940[i].setComponentOffset(0x6554 + (i * 4));
+ }
_65f4.r32.setComponentOffset(0x65f4);
+ for(int i = 0; i < 130; i++)
+ {
+ reserved_26104[i].setComponentOffset(0x65f8 + (i * 4));
+ }
GrcModeControl.r32.setComponentOffset(0x6800);
MiscellaneousConfig.r32.setComponentOffset(0x6804);
MiscellaneousLocalControl.r32.setComponentOffset(0x6808);
Timer.r32.setComponentOffset(0x680c);
RxCpuEvent.r32.setComponentOffset(0x6810);
+ for(int i = 0; i < 9; i++)
+ {
+ reserved_26644[i].setComponentOffset(0x6814 + (i * 4));
+ }
_6838.r32.setComponentOffset(0x6838);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_26684[i].setComponentOffset(0x683c + (i * 4));
+ }
MdiControl.r32.setComponentOffset(0x6844);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_26696[i].setComponentOffset(0x6848 + (i * 4));
+ }
RxCpuEventEnable.r32.setComponentOffset(0x684c);
+ for(int i = 0; i < 17; i++)
+ {
+ reserved_26704[i].setComponentOffset(0x6850 + (i * 4));
+ }
FastBootProgramCounter.r32.setComponentOffset(0x6894);
+ for(int i = 0; i < 21; i++)
+ {
+ reserved_26776[i].setComponentOffset(0x6898 + (i * 4));
+ }
ExpansionRomAddr.r32.setComponentOffset(0x68ec);
_68f0.r32.setComponentOffset(0x68f0);
+ for(int i = 0; i < 5; i++)
+ {
+ reserved_26868[i].setComponentOffset(0x68f4 + (i * 4));
+ }
EavRefClockControl.r32.setComponentOffset(0x6908);
+ for(int i = 0; i < 1214; i++)
+ {
+ reserved_26892[i].setComponentOffset(0x690c + (i * 4));
+ }
_7c04.r32.setComponentOffset(0x7c04);
}
void print()
@@ -8768,10 +9660,15 @@ typedef struct DEVICE_t {
}
ApeMemoryBase.print();
ApeMemoryData.print();
- for(int i = 0; i < 192; i++)
+ for(int i = 0; i < 24; i++)
{
reserved_256[i].print();
}
+ _160.print();
+ for(int i = 0; i < 167; i++)
+ {
+ reserved_356[i].print();
+ }
EmacMode.print();
EmacStatus.print();
EmacEvent.print();
@@ -8786,10 +9683,7 @@ typedef struct DEVICE_t {
EmacMacAddresses3Low.print();
WolPatternPointer.print();
WolPatternCfg.print();
- for(int i = 0; i < 1; i++)
- {
- reserved_1080[i].print();
- }
+ _438.print();
MtuSize.print();
for(int i = 0; i < 3; i++)
{
@@ -8835,9 +9729,10 @@ typedef struct DEVICE_t {
reserved_1464[i].print();
}
CpmuControl.print();
- for(int i = 0; i < 3; i++)
+ NoLinkPowerModeClockPolicy.print();
+ for(int i = 0; i < 2; i++)
{
- reserved_13828[i].print();
+ reserved_13832[i].print();
}
LinkAwarePowerModeClockPolicy.print();
for(int i = 0; i < 4; i++)
@@ -8864,10 +9759,15 @@ typedef struct DEVICE_t {
MutexRequest.print();
MutexGrant.print();
GphyStrap.print();
- for(int i = 0; i < 5; i++)
+ for(int i = 0; i < 1; i++)
{
reserved_13928[i].print();
}
+ FlashClockControlPolicy.print();
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_13936[i].print();
+ }
TopLevelMiscellaneousControl1.print();
for(int i = 0; i < 12; i++)
{
@@ -8890,10 +9790,15 @@ typedef struct DEVICE_t {
}
GlobalMutexRequest.print();
GlobalMutexGrant.print();
- for(int i = 0; i < 578; i++)
+ for(int i = 0; i < 1; i++)
{
reserved_14072[i].print();
}
+ TemperatureMonitorControl.print();
+ for(int i = 0; i < 576; i++)
+ {
+ reserved_14080[i].print();
+ }
MemoryArbiterMode.print();
for(int i = 0; i < 255; i++)
{
@@ -8983,10 +9888,7 @@ typedef struct DEVICE_t {
reserved_25664[i].print();
}
_64c0.print();
- for(int i = 0; i < 1; i++)
- {
- reserved_25796[i].print();
- }
+ _64c4.print();
_64c8.print();
for(int i = 0; i < 4; i++)
{
diff --git a/include/bcm5719_GEN.h b/include/bcm5719_GEN.h
index 4d3d028..9d26924 100644
--- a/include/bcm5719_GEN.h
+++ b/include/bcm5719_GEN.h
@@ -1617,23 +1617,63 @@ typedef struct GEN_t {
GenDataSig.r32.setComponentOffset(0x4);
GenCfg.r32.setComponentOffset(0x8);
GenVersion.r32.setComponentOffset(0xc);
+ for(int i = 0; i < 5; i++)
+ {
+ reserved_16[i].setComponentOffset(0x10 + (i * 4));
+ }
GenPhyId.r32.setComponentOffset(0x24);
+ for(int i = 0; i < 34; i++)
+ {
+ reserved_40[i].setComponentOffset(0x28 + (i * 4));
+ }
GenAsfStatusMbox.r32.setComponentOffset(0xb0);
GenFwDriverStateMbox.r32.setComponentOffset(0xb4);
GenFwResetTypeMbox.r32.setComponentOffset(0xb8);
GenBc.r32.setComponentOffset(0xbc);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_192[i].setComponentOffset(0xc0 + (i * 4));
+ }
GenMacAddrHighMbox.r32.setComponentOffset(0xc4);
GenMacAddrLowMbox.r32.setComponentOffset(0xc8);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_204[i].setComponentOffset(0xcc + (i * 4));
+ }
GenD8.r32.setComponentOffset(0xd8);
+ for(int i = 0; i < 64; i++)
+ {
+ reserved_220[i].setComponentOffset(0xdc + (i * 4));
+ }
Gen1dc.r32.setComponentOffset(0x1dc);
GenWolMbox.r32.setComponentOffset(0x1e0);
GenCfgFeature.r32.setComponentOffset(0x1e4);
GenCfgHw.r32.setComponentOffset(0x1e8);
GenCfgShared.r32.setComponentOffset(0x1ec);
+ for(int i = 0; i < 9; i++)
+ {
+ reserved_496[i].setComponentOffset(0x1f0 + (i * 4));
+ }
GenFwVersion.r32.setComponentOffset(0x214);
+ for(int i = 0; i < 36; i++)
+ {
+ reserved_536[i].setComponentOffset(0x218 + (i * 4));
+ }
GenCfgHw2.r32.setComponentOffset(0x2a8);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_684[i].setComponentOffset(0x2ac + (i * 4));
+ }
GenCpmuStatus.r32.setComponentOffset(0x2b0);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_692[i].setComponentOffset(0x2b4 + (i * 4));
+ }
GenCfg5.r32.setComponentOffset(0x2bc);
+ for(int i = 0; i < 40; i++)
+ {
+ reserved_704[i].setComponentOffset(0x2c0 + (i * 4));
+ }
GenDbgControlStatus.r32.setComponentOffset(0x360);
GenDbgData.r32.setComponentOffset(0x364);
}
diff --git a/include/bcm5719_SHM.h b/include/bcm5719_SHM.h
index c22beb8..0636175 100644
--- a/include/bcm5719_SHM.h
+++ b/include/bcm5719_SHM.h
@@ -720,10 +720,35 @@ typedef register_container RegSHMRcpuCfgFeature_t {
} RegSHMRcpuCfgFeature_t;
#define REG_SHM_RCPU_PCI_VENDOR_DEVICE_ID ((volatile BCM5719_SHM_H_uint32_t*)0xc0014114) /* Set to PCI Vendor/Device ID by S2. */
+#define SHM_RCPU_PCI_VENDOR_DEVICE_ID_DEVICE_ID_SHIFT 0u
+#define SHM_RCPU_PCI_VENDOR_DEVICE_ID_DEVICE_ID_MASK 0xffffu
+#define GET_SHM_RCPU_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__reg__) (((__reg__) & 0xffff) >> 0u)
+#define SET_SHM_RCPU_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__val__) (((__val__) << 0u) & 0xffffu)
+#define SHM_RCPU_PCI_VENDOR_DEVICE_ID_VENDOR_ID_SHIFT 16u
+#define SHM_RCPU_PCI_VENDOR_DEVICE_ID_VENDOR_ID_MASK 0xffff0000u
+#define GET_SHM_RCPU_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u)
+#define SET_SHM_RCPU_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__val__) (((__val__) << 16u) & 0xffff0000u)
+
/** @brief Register definition for @ref SHM_t.RcpuPciVendorDeviceId. */
typedef register_container RegSHMRcpuPciVendorDeviceId_t {
/** @brief 32bit direct register access. */
BCM5719_SHM_H_uint32_t r32;
+
+ BITFIELD_BEGIN(BCM5719_SHM_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_SHM_H_uint32_t, DeviceID, 0, 16)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_SHM_H_uint32_t, VendorID, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_SHM_H_uint32_t, VendorID, 16, 16)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_SHM_H_uint32_t, DeviceID, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(BCM5719_SHM_H_uint32_t, bits)
#ifdef CXX_SIMULATOR
/** @brief Register name for use with the simulator. */
const char* getName(void) { return "RcpuPciVendorDeviceId"; }
@@ -735,6 +760,10 @@ typedef register_container RegSHMRcpuPciVendorDeviceId_t {
{
/** @brief constructor for @ref SHM_t.RcpuPciVendorDeviceId. */
r32.setName("RcpuPciVendorDeviceId");
+ bits.DeviceID.setBaseRegister(&r32);
+ bits.DeviceID.setName("DeviceID");
+ bits.VendorID.setBaseRegister(&r32);
+ bits.VendorID.setName("VendorID");
}
RegSHMRcpuPciVendorDeviceId_t& operator=(const RegSHMRcpuPciVendorDeviceId_t& other)
{
@@ -745,10 +774,35 @@ typedef register_container RegSHMRcpuPciVendorDeviceId_t {
} RegSHMRcpuPciVendorDeviceId_t;
#define REG_SHM_RCPU_PCI_SUBSYSTEM_ID ((volatile BCM5719_SHM_H_uint32_t*)0xc0014118) /* Set to PCI Subsystem Vendor/Subsystem ID by S2. */
+#define SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0u
+#define SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_MASK 0xffffu
+#define GET_SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__reg__) (((__reg__) & 0xffff) >> 0u)
+#define SET_SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__val__) (((__val__) << 0u) & 0xffffu)
+#define SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_SHIFT 16u
+#define SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_MASK 0xffff0000u
+#define GET_SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u)
+#define SET_SHM_RCPU_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__val__) (((__val__) << 16u) & 0xffff0000u)
+
/** @brief Register definition for @ref SHM_t.RcpuPciSubsystemId. */
typedef register_container RegSHMRcpuPciSubsystemId_t {
/** @brief 32bit direct register access. */
BCM5719_SHM_H_uint32_t r32;
+
+ BITFIELD_BEGIN(BCM5719_SHM_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_SHM_H_uint32_t, SubsystemVendorID, 0, 16)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_SHM_H_uint32_t, SubsystemID, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_SHM_H_uint32_t, SubsystemID, 16, 16)
+ /** @brief */
+ BITFIELD_MEMBER(BCM5719_SHM_H_uint32_t, SubsystemVendorID, 0, 16)
+#else
+#error Unknown Endian
+#endif
+ BITFIELD_END(BCM5719_SHM_H_uint32_t, bits)
#ifdef CXX_SIMULATOR
/** @brief Register name for use with the simulator. */
const char* getName(void) { return "RcpuPciSubsystemId"; }
@@ -760,6 +814,10 @@ typedef register_container RegSHMRcpuPciSubsystemId_t {
{
/** @brief constructor for @ref SHM_t.RcpuPciSubsystemId. */
r32.setName("RcpuPciSubsystemId");
+ bits.SubsystemVendorID.setBaseRegister(&r32);
+ bits.SubsystemVendorID.setName("SubsystemVendorID");
+ bits.SubsystemID.setBaseRegister(&r32);
+ bits.SubsystemID.setName("SubsystemID");
}
RegSHMRcpuPciSubsystemId_t& operator=(const RegSHMRcpuPciSubsystemId_t& other)
{
@@ -1760,6 +1818,10 @@ typedef struct SHM_t {
{
SegSig.r32.setComponentOffset(0x0);
ApeSegLength.r32.setComponentOffset(0x4);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_8[i].setComponentOffset(0x8 + (i * 4));
+ }
FwStatus.r32.setComponentOffset(0xc);
FwFeatures.r32.setComponentOffset(0x10);
_4014.r32.setComponentOffset(0x14);
@@ -1768,9 +1830,17 @@ typedef struct SHM_t {
SegMessageBufferLength.r32.setComponentOffset(0x20);
_4024.r32.setComponentOffset(0x24);
_4028.r32.setComponentOffset(0x28);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_44[i].setComponentOffset(0x2c + (i * 4));
+ }
LoaderCommand.r32.setComponentOffset(0x38);
LoaderArg0.r32.setComponentOffset(0x3c);
LoaderArg1.r32.setComponentOffset(0x40);
+ for(int i = 0; i < 47; i++)
+ {
+ reserved_68[i].setComponentOffset(0x44 + (i * 4));
+ }
RcpuSegSig.r32.setComponentOffset(0x100);
RcpuSegLength.r32.setComponentOffset(0x104);
RcpuInitCount.r32.setComponentOffset(0x108);
@@ -1784,6 +1854,10 @@ typedef struct SHM_t {
RcpuCfgHw.r32.setComponentOffset(0x128);
RcpuCfgHw2.r32.setComponentOffset(0x12c);
RcpuCpmuStatus.r32.setComponentOffset(0x130);
+ for(int i = 0; i < 51; i++)
+ {
+ reserved_308[i].setComponentOffset(0x134 + (i * 4));
+ }
HostSegSig.r32.setComponentOffset(0x200);
HostSegLen.r32.setComponentOffset(0x204);
HostInitCount.r32.setComponentOffset(0x208);
@@ -1792,18 +1866,46 @@ typedef struct SHM_t {
HeartbeatInterval.r32.setComponentOffset(0x214);
HeartbeatCount.r32.setComponentOffset(0x218);
HostDriverState.r32.setComponentOffset(0x21c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_544[i].setComponentOffset(0x220 + (i * 4));
+ }
WolSpeed.r32.setComponentOffset(0x224);
+ for(int i = 0; i < 54; i++)
+ {
+ reserved_552[i].setComponentOffset(0x228 + (i * 4));
+ }
EventStatus.r32.setComponentOffset(0x300);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_772[i].setComponentOffset(0x304 + (i * 4));
+ }
ProtMagic.r32.setComponentOffset(0x308);
+ for(int i = 0; i < 2; i++)
+ {
+ reserved_780[i].setComponentOffset(0x30c + (i * 4));
+ }
ProtMac0High.r32.setComponentOffset(0x314);
ProtMac0Low.r32.setComponentOffset(0x318);
+ for(int i = 0; i < 313; i++)
+ {
+ reserved_796[i].setComponentOffset(0x31c + (i * 4));
+ }
NcsiSig.r32.setComponentOffset(0x800);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_2052[i].setComponentOffset(0x804 + (i * 4));
+ }
NcsiBuildTime.r32.setComponentOffset(0x810);
NcsiBuildTime2.r32.setComponentOffset(0x814);
NcsiBuildTime3.r32.setComponentOffset(0x818);
NcsiBuildDate.r32.setComponentOffset(0x81c);
NcsiBuildDate2.r32.setComponentOffset(0x820);
NcsiBuildDate3.r32.setComponentOffset(0x824);
+ for(int i = 0; i < 26; i++)
+ {
+ reserved_2088[i].setComponentOffset(0x828 + (i * 4));
+ }
ChipId.r32.setComponentOffset(0x890);
}
void print()
diff --git a/include/bcm5719_SHM_CHANNEL0.h b/include/bcm5719_SHM_CHANNEL0.h
index 7aa6b09..54a8aa4 100644
--- a/include/bcm5719_SHM_CHANNEL0.h
+++ b/include/bcm5719_SHM_CHANNEL0.h
@@ -1863,18 +1863,38 @@ typedef struct SHM_CHANNEL_t {
NcsiChannelSetting1.r32.setComponentOffset(0x14);
NcsiChannelSetting2.r32.setComponentOffset(0x18);
NcsiChannelVlan.r32.setComponentOffset(0x1c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_32[i].setComponentOffset(0x20 + (i * 4));
+ }
NcsiChannelAltHostMacHigh.r32.setComponentOffset(0x24);
NcsiChannelAltHostMacMid.r32.setComponentOffset(0x28);
NcsiChannelAltHostMacLow.r32.setComponentOffset(0x2c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_48[i].setComponentOffset(0x30 + (i * 4));
+ }
NcsiChannelMac0High.r32.setComponentOffset(0x34);
NcsiChannelMac0Mid.r32.setComponentOffset(0x38);
NcsiChannelMac0Low.r32.setComponentOffset(0x3c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_64[i].setComponentOffset(0x40 + (i * 4));
+ }
NcsiChannelMac1High.r32.setComponentOffset(0x44);
NcsiChannelMac1Mid.r32.setComponentOffset(0x48);
NcsiChannelMac1Low.r32.setComponentOffset(0x4c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_80[i].setComponentOffset(0x50 + (i * 4));
+ }
NcsiChannelMac2High.r32.setComponentOffset(0x54);
NcsiChannelMac2Mid.r32.setComponentOffset(0x58);
NcsiChannelMac2Low.r32.setComponentOffset(0x5c);
+ for(int i = 0; i < 1; i++)
+ {
+ reserved_96[i].setComponentOffset(0x60 + (i * 4));
+ }
NcsiChannelMac3High.r32.setComponentOffset(0x64);
NcsiChannelMac3Mid.r32.setComponentOffset(0x68);
NcsiChannelMac3Low.r32.setComponentOffset(0x6c);
@@ -1887,7 +1907,15 @@ typedef struct SHM_CHANNEL_t {
NcsiChannelPxe.r32.setComponentOffset(0x88);
NcsiChannelDropfil.r32.setComponentOffset(0x8c);
NcsiChannelSlink.r32.setComponentOffset(0x90);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_148[i].setComponentOffset(0x94 + (i * 4));
+ }
NcsiChannelDbg.r32.setComponentOffset(0xa0);
+ for(int i = 0; i < 3; i++)
+ {
+ reserved_164[i].setComponentOffset(0xa4 + (i * 4));
+ }
NcsiChannelCtrlstatRx.r32.setComponentOffset(0xb0);
NcsiChannelCtrlstatDropped.r32.setComponentOffset(0xb4);
NcsiChannelCtrlstatTypeErr.r32.setComponentOffset(0xb8);
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