diff options
| -rw-r--r-- | include/bcm5719_APE.h | 1809 | ||||
| -rw-r--r-- | ipxact/APE.xml | 68 | ||||
| -rw-r--r-- | ipxact/SHM.xml | 1077 | ||||
| -rw-r--r-- | ipxact/bcm5719.xml | 1069 | ||||
| -rwxr-xr-x | ipxact/regen.sh | 5 | ||||
| -rw-r--r-- | libs/bcm5719/APE_sym.s | 16 | ||||
| -rw-r--r-- | libs/bcm5719/bcm5719_sym.s | 4 | ||||
| -rw-r--r-- | simulator/CMakeLists.txt | 4 | ||||
| -rw-r--r-- | simulator/HAL.cpp | 9 | ||||
| -rw-r--r-- | simulator/bcm5719_APE.cpp | 154 | ||||
| -rw-r--r-- | simulator/bcm5719_APE_mmap.cpp | 385 | ||||
| -rw-r--r-- | simulator/bcm5719_SHM.cpp | 207 | ||||
| -rw-r--r-- | simulator/bcm5719_SHM_mmap.cpp | 470 | ||||
| -rw-r--r-- | stage1/main.c | 37 |
14 files changed, 1891 insertions, 3423 deletions
diff --git a/include/bcm5719_APE.h b/include/bcm5719_APE.h index fc989f6..999ad89 100644 --- a/include/bcm5719_APE.h +++ b/include/bcm5719_APE.h @@ -1002,1525 +1002,6 @@ typedef register_container RegAPECm3_t { #endif /* CXX_SIMULATOR */ } RegAPECm3_t; -#define REG_APE_SEG_SIG ((volatile BCM5719_APE_H_uint32_t*)0xc0014000) /* APE_APE_MAGIC ('APE!') when all is well. */ -/** @brief Register definition for @ref APE_t.SegSig. */ -typedef register_container RegAPESegSig_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPESegSig_t; - -#define REG_APE_FW_STATUS ((volatile BCM5719_APE_H_uint32_t*)0xc001400c) /* */ -#define APE_FW_STATUS_READY_SHIFT 8u -#define APE_FW_STATUS_READY_MASK 0x100u -#define GET_APE_FW_STATUS_READY(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_APE_FW_STATUS_READY(__val__) (((__val__) << 8u) & 0x100u) -#define APE_FW_STATUS_UNKNOWN_31_28_SHIFT 28u -#define APE_FW_STATUS_UNKNOWN_31_28_MASK 0xf0000000u -#define GET_APE_FW_STATUS_UNKNOWN_31_28(__reg__) (((__reg__) & 0xf0000000) >> 28u) -#define SET_APE_FW_STATUS_UNKNOWN_31_28(__val__) (((__val__) << 28u) & 0xf0000000u) - -/** @brief Register definition for @ref APE_t.FwStatus. */ -typedef register_container RegAPEFwStatus_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_0, 0, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Ready, 8, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_27_9, 9, 19) - /** @brief If this is all-ones, it appears to mean the APE FW is halted. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, unknown_31_28, 28, 4) -#elif defined(__BIG_ENDIAN__) - /** @brief If this is all-ones, it appears to mean the APE FW is halted. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, unknown_31_28, 28, 4) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_27_9, 9, 19) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Ready, 8, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_0, 0, 8) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "FwStatus"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPEFwStatus_t() - { - /** @brief constructor for @ref APE_t.FwStatus. */ - r32.setName("FwStatus"); - bits.Ready.setBaseRegister(&r32); - bits.Ready.setName("Ready"); - bits.unknown_31_28.setBaseRegister(&r32); - bits.unknown_31_28.setName("unknown_31_28"); - } - RegAPEFwStatus_t& operator=(const RegAPEFwStatus_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPEFwStatus_t; - -#define REG_APE_FW_FEATURES ((volatile BCM5719_APE_H_uint32_t*)0xc0014010) /* */ -#define APE_FW_FEATURES_NCSI_SHIFT 1u -#define APE_FW_FEATURES_NCSI_MASK 0x2u -#define GET_APE_FW_FEATURES_NCSI(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_FW_FEATURES_NCSI(__val__) (((__val__) << 1u) & 0x2u) - -/** @brief Register definition for @ref APE_t.FwFeatures. */ -typedef register_container RegAPEFwFeatures_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_0_0, 0, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, NCSI, 1, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_2, 2, 30) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_2, 2, 30) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, NCSI, 1, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_0_0, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "FwFeatures"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPEFwFeatures_t() - { - /** @brief constructor for @ref APE_t.FwFeatures. */ - r32.setName("FwFeatures"); - bits.NCSI.setBaseRegister(&r32); - bits.NCSI.setName("NCSI"); - } - RegAPEFwFeatures_t& operator=(const RegAPEFwFeatures_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPEFwFeatures_t; - -#define REG_APE_4014 ((volatile BCM5719_APE_H_uint32_t*)0xc0014014) /* Unknown. */ -/** @brief Register definition for @ref APE_t.4014. */ -typedef register_container RegAPE4014_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPE4014_t; - -#define REG_APE_FW_VERSION ((volatile BCM5719_APE_H_uint32_t*)0xc0014018) /* */ -#define APE_FW_VERSION_BUILD_SHIFT 0u -#define APE_FW_VERSION_BUILD_MASK 0xffu -#define GET_APE_FW_VERSION_BUILD(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_APE_FW_VERSION_BUILD(__val__) (((__val__) << 0u) & 0xffu) -#define APE_FW_VERSION_REVISION_SHIFT 8u -#define APE_FW_VERSION_REVISION_MASK 0xff00u -#define GET_APE_FW_VERSION_REVISION(__reg__) (((__reg__) & 0xff00) >> 8u) -#define SET_APE_FW_VERSION_REVISION(__val__) (((__val__) << 8u) & 0xff00u) -#define APE_FW_VERSION_MINOR_SHIFT 16u -#define APE_FW_VERSION_MINOR_MASK 0xff0000u -#define GET_APE_FW_VERSION_MINOR(__reg__) (((__reg__) & 0xff0000) >> 16u) -#define SET_APE_FW_VERSION_MINOR(__val__) (((__val__) << 16u) & 0xff0000u) -#define APE_FW_VERSION_MAJOR_SHIFT 24u -#define APE_FW_VERSION_MAJOR_MASK 0xff000000u -#define GET_APE_FW_VERSION_MAJOR(__reg__) (((__reg__) & 0xff000000) >> 24u) -#define SET_APE_FW_VERSION_MAJOR(__val__) (((__val__) << 24u) & 0xff000000u) - -/** @brief Register definition for @ref APE_t.FwVersion. */ -typedef register_container RegAPEFwVersion_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Build, 0, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Revision, 8, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Minor, 16, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Major, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Major, 24, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Minor, 16, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Revision, 8, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Build, 0, 8) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "FwVersion"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPEFwVersion_t() - { - /** @brief constructor for @ref APE_t.FwVersion. */ - r32.setName("FwVersion"); - bits.Build.setBaseRegister(&r32); - bits.Build.setName("Build"); - bits.Revision.setBaseRegister(&r32); - bits.Revision.setName("Revision"); - bits.Minor.setBaseRegister(&r32); - bits.Minor.setName("Minor"); - bits.Major.setBaseRegister(&r32); - bits.Major.setName("Major"); - } - RegAPEFwVersion_t& operator=(const RegAPEFwVersion_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPEFwVersion_t; - -#define REG_APE_SEG_MESSAGE_BUFFER_OFFSET ((volatile BCM5719_APE_H_uint32_t*)0xc001401c) /* Specifies the offset of a scratchpad area, relative to the start of the APE SHM area (i.e., relative to APE_REG(0x4000)). */ -/** @brief Register definition for @ref APE_t.SegMessageBufferOffset. */ -typedef register_container RegAPESegMessageBufferOffset_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPESegMessageBufferOffset_t; - -#define REG_APE_SEG_MESSAGE_BUFFER_LENGTH ((volatile BCM5719_APE_H_uint32_t*)0xc0014020) /* Specifies the size of the scratchpad area in bytes. */ -/** @brief Register definition for @ref APE_t.SegMessageBufferLength. */ -typedef register_container RegAPESegMessageBufferLength_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPESegMessageBufferLength_t; - -#define REG_APE_4024 ((volatile BCM5719_APE_H_uint32_t*)0xc0014024) /* Unknown. Bootcode related. */ -/** @brief Register definition for @ref APE_t.4024. */ -typedef register_container RegAPE4024_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPE4024_t; - -#define REG_APE_4028 ((volatile BCM5719_APE_H_uint32_t*)0xc0014028) /* Unknown. Bootcode related. */ -/** @brief Register definition for @ref APE_t.4028. */ -typedef register_container RegAPE4028_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPE4028_t; - -#define REG_APE_RCPU_SEG_SIG ((volatile BCM5719_APE_H_uint32_t*)0xc0014100) /* Set to APE_RCPU_MAGIC ('RCPU') by RX CPU. */ -#define APE_RCPU_SEG_SIG_SIG_SHIFT 0u -#define APE_RCPU_SEG_SIG_SIG_MASK 0xffffffffu -#define GET_APE_RCPU_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_APE_RCPU_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) -#define APE_RCPU_SEG_SIG_SIG_RCPU_MAGIC 0x52435055u - - -/** @brief Register definition for @ref APE_t.RcpuSegSig. */ -typedef register_container RegAPERcpuSegSig_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Sig, 0, 32) -#elif defined(__BIG_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Sig, 0, 32) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RcpuSegSig"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERcpuSegSig_t() - { - /** @brief constructor for @ref APE_t.RcpuSegSig. */ - r32.setName("RcpuSegSig"); - bits.Sig.setBaseRegister(&r32); - bits.Sig.setName("Sig"); - } - RegAPERcpuSegSig_t& operator=(const RegAPERcpuSegSig_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERcpuSegSig_t; - -#define REG_APE_RCPU_SEG_LENGTH ((volatile BCM5719_APE_H_uint32_t*)0xc0014104) /* Set to 0x34. */ -/** @brief Register definition for @ref APE_t.RcpuSegLength. */ -typedef register_container RegAPERcpuSegLength_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPERcpuSegLength_t; - -#define REG_APE_RCPU_INIT_COUNT ((volatile BCM5719_APE_H_uint32_t*)0xc0014108) /* Incremented by RX CPU every boot. */ -/** @brief Register definition for @ref APE_t.RcpuInitCount. */ -typedef register_container RegAPERcpuInitCount_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPERcpuInitCount_t; - -#define REG_APE_RCPU_FW_VERSION ((volatile BCM5719_APE_H_uint32_t*)0xc001410c) /* Set to the bootcode version. e.g. 0x0127 -> v1.39. */ -/** @brief Register definition for @ref APE_t.RcpuFwVersion. */ -typedef register_container RegAPERcpuFwVersion_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPERcpuFwVersion_t; - -#define REG_APE_RCPU_CFG_FEATURE ((volatile BCM5719_APE_H_uint32_t*)0xc0014110) /* Set to */ -/** @brief Register definition for @ref APE_t.RcpuCfgFeature. */ -typedef register_container RegAPERcpuCfgFeature_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPERcpuCfgFeature_t; - -#define REG_APE_RCPU_PCI_VENDOR_DEVICE_ID ((volatile BCM5719_APE_H_uint32_t*)0xc0014114) /* Set to PCI Vendor/Device ID by S2. */ -/** @brief Register definition for @ref APE_t.RcpuPciVendorDeviceId. */ -typedef register_container RegAPERcpuPciVendorDeviceId_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPERcpuPciVendorDeviceId_t; - -#define REG_APE_RCPU_PCI_SUBSYSTEM_ID ((volatile BCM5719_APE_H_uint32_t*)0xc0014118) /* Set to PCI Subsystem Vendor/Subsystem ID by S2. */ -/** @brief Register definition for @ref APE_t.RcpuPciSubsystemId. */ -typedef register_container RegAPERcpuPciSubsystemId_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPERcpuPciSubsystemId_t; - -#define REG_APE_RCPU_APE_RESET_COUNT ((volatile BCM5719_APE_H_uint32_t*)0xc001411c) /* Unknown. Incremented by frobnicating routine. */ -/** @brief Register definition for @ref APE_t.RcpuApeResetCount. */ -typedef register_container RegAPERcpuApeResetCount_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPERcpuApeResetCount_t; - -#define REG_APE_RCPU_LAST_APE_STATUS ((volatile BCM5719_APE_H_uint32_t*)0xc0014120) /* Unknown. Written by frobnicating routine. */ -/** @brief Register definition for @ref APE_t.RcpuLastApeStatus. */ -typedef register_container RegAPERcpuLastApeStatus_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPERcpuLastApeStatus_t; - -#define REG_APE_RCPU_LAST_APE_FW_STATUS ((volatile BCM5719_APE_H_uint32_t*)0xc0014124) /* Unknown. */ -/** @brief Register definition for @ref APE_t.RcpuLastApeFwStatus. */ -typedef register_container RegAPERcpuLastApeFwStatus_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPERcpuLastApeFwStatus_t; - -#define REG_APE_RCPU_CFG_HW ((volatile BCM5719_APE_H_uint32_t*)0xc0014128) /* Set from */ -/** @brief Register definition for @ref APE_t.RcpuCfgHw. */ -typedef register_container RegAPERcpuCfgHw_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPERcpuCfgHw_t; - -#define REG_APE_RCPU_CFG_HW_2 ((volatile BCM5719_APE_H_uint32_t*)0xc001412c) /* Set from */ -/** @brief Register definition for @ref APE_t.RcpuCfgHw2. */ -typedef register_container RegAPERcpuCfgHw2_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPERcpuCfgHw2_t; - -#define REG_APE_RCPU_CPMU_STATUS ((volatile BCM5719_APE_H_uint32_t*)0xc0014130) /* Set from */ -#define APE_RCPU_CPMU_STATUS_ADDRESS_SHIFT 0u -#define APE_RCPU_CPMU_STATUS_ADDRESS_MASK 0xffffu -#define GET_APE_RCPU_CPMU_STATUS_ADDRESS(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_APE_RCPU_CPMU_STATUS_ADDRESS(__val__) (((__val__) << 0u) & 0xffffu) -#define APE_RCPU_CPMU_STATUS_ADDRESS_ADDRESS 0x362cu - -#define APE_RCPU_CPMU_STATUS_STATUS_SHIFT 16u -#define APE_RCPU_CPMU_STATUS_STATUS_MASK 0xffff0000u -#define GET_APE_RCPU_CPMU_STATUS_STATUS(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_APE_RCPU_CPMU_STATUS_STATUS(__val__) (((__val__) << 16u) & 0xffff0000u) - -/** @brief Register definition for @ref APE_t.RcpuCpmuStatus. */ -typedef register_container RegAPERcpuCpmuStatus_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Address, 0, 16) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Status, 16, 16) -#elif defined(__BIG_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Status, 16, 16) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Address, 0, 16) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RcpuCpmuStatus"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERcpuCpmuStatus_t() - { - /** @brief constructor for @ref APE_t.RcpuCpmuStatus. */ - r32.setName("RcpuCpmuStatus"); - bits.Address.setBaseRegister(&r32); - bits.Address.setName("Address"); - bits.Status.setBaseRegister(&r32); - bits.Status.setName("Status"); - } - RegAPERcpuCpmuStatus_t& operator=(const RegAPERcpuCpmuStatus_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERcpuCpmuStatus_t; - -#define REG_APE_HOST_SEG_SIG ((volatile BCM5719_APE_H_uint32_t*)0xc0014200) /* Set to APE_HOST_MAGIC ('HOST') to indicate the section is valid. */ -/** @brief Register definition for @ref APE_t.HostSegSig. */ -typedef register_container RegAPEHostSegSig_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPEHostSegSig_t; - -#define REG_APE_HOST_SEG_LEN ((volatile BCM5719_APE_H_uint32_t*)0xc0014204) /* Set to 0x20. */ -/** @brief Register definition for @ref APE_t.HostSegLen. */ -typedef register_container RegAPEHostSegLen_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPEHostSegLen_t; - -#define REG_APE_HOST_INIT_COUNT ((volatile BCM5719_APE_H_uint32_t*)0xc0014208) /* Incremented by host on every initialization. */ -/** @brief Register definition for @ref APE_t.HostInitCount. */ -typedef register_container RegAPEHostInitCount_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPEHostInitCount_t; - -#define REG_APE_HOST_DRIVER_ID ((volatile BCM5719_APE_H_uint32_t*)0xc001420c) /* Linux sets this to 0xF0MM_mm00, where M is the major version of Linux and m is the minor version. */ -/** @brief Register definition for @ref APE_t.HostDriverId. */ -typedef register_container RegAPEHostDriverId_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPEHostDriverId_t; - -#define REG_APE_HOST_BEHAVIOR ((volatile BCM5719_APE_H_uint32_t*)0xc0014210) /* */ -#define APE_HOST_BEHAVIOR_NO_PHYLOCK_SHIFT 0u -#define APE_HOST_BEHAVIOR_NO_PHYLOCK_MASK 0x1u -#define GET_APE_HOST_BEHAVIOR_NO_PHYLOCK(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_HOST_BEHAVIOR_NO_PHYLOCK(__val__) (((__val__) << 0u) & 0x1u) - -/** @brief Register definition for @ref APE_t.HostBehavior. */ -typedef register_container RegAPEHostBehavior_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, NoPHYLock, 0, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_1, 1, 31) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_1, 1, 31) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, NoPHYLock, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "HostBehavior"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPEHostBehavior_t() - { - /** @brief constructor for @ref APE_t.HostBehavior. */ - r32.setName("HostBehavior"); - bits.NoPHYLock.setBaseRegister(&r32); - bits.NoPHYLock.setName("NoPHYLock"); - } - RegAPEHostBehavior_t& operator=(const RegAPEHostBehavior_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPEHostBehavior_t; - -#define REG_APE_HEARTBEAT_INTERVAL ((volatile BCM5719_APE_H_uint32_t*)0xc0014214) /* In milliseconds. Set to 0 to disable heartbeating. */ -/** @brief Register definition for @ref APE_t.HeartbeatInterval. */ -typedef register_container RegAPEHeartbeatInterval_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPEHeartbeatInterval_t; - -#define REG_APE_HEARTBEAT_COUNT ((volatile BCM5719_APE_H_uint32_t*)0xc0014218) /* */ -/** @brief Register definition for @ref APE_t.HeartbeatCount. */ -typedef register_container RegAPEHeartbeatCount_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPEHeartbeatCount_t; - -#define REG_APE_HOST_DRIVER_STATE ((volatile BCM5719_APE_H_uint32_t*)0xc001421c) /* */ -/** @brief Register definition for @ref APE_t.HostDriverState. */ -typedef register_container RegAPEHostDriverState_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPEHostDriverState_t; - -#define REG_APE_WOL_SPEED ((volatile BCM5719_APE_H_uint32_t*)0xc0014224) /* */ -/** @brief Register definition for @ref APE_t.WolSpeed. */ -typedef register_container RegAPEWolSpeed_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPEWolSpeed_t; - -#define REG_APE_EVENT_STATUS ((volatile BCM5719_APE_H_uint32_t*)0xc0014300) /* */ -#define APE_EVENT_STATUS_DRIVER_EVENT_SHIFT 4u -#define APE_EVENT_STATUS_DRIVER_EVENT_MASK 0x10u -#define GET_APE_EVENT_STATUS_DRIVER_EVENT(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_EVENT_STATUS_DRIVER_EVENT(__val__) (((__val__) << 4u) & 0x10u) -#define APE_EVENT_STATUS_COMMAND_SHIFT 8u -#define APE_EVENT_STATUS_COMMAND_MASK 0xff00u -#define GET_APE_EVENT_STATUS_COMMAND(__reg__) (((__reg__) & 0xff00) >> 8u) -#define SET_APE_EVENT_STATUS_COMMAND(__val__) (((__val__) << 8u) & 0xff00u) -#define APE_EVENT_STATUS_COMMAND_STATE_CHANGE 0x5u -#define APE_EVENT_STATUS_COMMAND_SCRATCHPAD_READ 0x16u -#define APE_EVENT_STATUS_COMMAND_SCRATCHPAD_WRITE 0x17u - -#define APE_EVENT_STATUS_STATE_SHIFT 16u -#define APE_EVENT_STATUS_STATE_MASK 0x70000u -#define GET_APE_EVENT_STATUS_STATE(__reg__) (((__reg__) & 0x70000) >> 16u) -#define SET_APE_EVENT_STATUS_STATE(__val__) (((__val__) << 16u) & 0x70000u) -#define APE_EVENT_STATUS_STATE_START 0x1u -#define APE_EVENT_STATUS_STATE_UNLOAD 0x2u -#define APE_EVENT_STATUS_STATE_WOL 0x3u -#define APE_EVENT_STATUS_STATE_SUSPEND 0x4u - -#define APE_EVENT_STATUS_PENDING_SHIFT 31u -#define APE_EVENT_STATUS_PENDING_MASK 0x80000000u -#define GET_APE_EVENT_STATUS_PENDING(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_APE_EVENT_STATUS_PENDING(__val__) (((__val__) << 31u) & 0x80000000u) - -/** @brief Register definition for @ref APE_t.EventStatus. */ -typedef register_container RegAPEEventStatus_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_0, 0, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DriverEvent, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_5, 5, 3) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Command, 8, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 16, 3) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_30_19, 19, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Pending, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Pending, 31, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_30_19, 19, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 16, 3) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Command, 8, 8) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_5, 5, 3) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DriverEvent, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_0, 0, 4) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "EventStatus"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPEEventStatus_t() - { - /** @brief constructor for @ref APE_t.EventStatus. */ - r32.setName("EventStatus"); - bits.DriverEvent.setBaseRegister(&r32); - bits.DriverEvent.setName("DriverEvent"); - bits.Command.setBaseRegister(&r32); - bits.Command.setName("Command"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - bits.Pending.setBaseRegister(&r32); - bits.Pending.setName("Pending"); - } - RegAPEEventStatus_t& operator=(const RegAPEEventStatus_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPEEventStatus_t; - -#define REG_APE_PROT_MAGIC ((volatile BCM5719_APE_H_uint32_t*)0xc0014308) /* This is set to APE_PROT_MAGIC ('PROT') on all functions. If it is 'PROT', the following fields (MAC0_HIGH/LOW) are valid */ -/** @brief Register definition for @ref APE_t.ProtMagic. */ -typedef register_container RegAPEProtMagic_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPEProtMagic_t; - -#define REG_APE_PROT_MAC0_HIGH ((volatile BCM5719_APE_H_uint32_t*)0xc0014314) /* High 16 bits of MAC address 0. Only valid if */ -/** @brief Register definition for @ref APE_t.ProtMac0High. */ -typedef register_container RegAPEProtMac0High_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPEProtMac0High_t; - -#define REG_APE_PROT_MAC0_LOW ((volatile BCM5719_APE_H_uint32_t*)0xc0014318) /* Low 16 bits of MAC address 0. */ -/** @brief Register definition for @ref APE_t.ProtMac0Low. */ -typedef register_container RegAPEProtMac0Low_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPEProtMac0Low_t; - -#define REG_APE_NCSI_SIG ((volatile BCM5719_APE_H_uint32_t*)0xc0014800) /* Set to NCSI_MAGIC ('NCSI') by APE firmware. NOTE: all words in the NCSI section are available in the function 0 SHM area only. */ -/** @brief Register definition for @ref APE_t.NcsiSig. */ -typedef register_container RegAPENcsiSig_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiSig_t; - -#define REG_APE_NCSI_BUILD_TIME ((volatile BCM5719_APE_H_uint32_t*)0xc0014810) /* ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero. */ -/** @brief Register definition for @ref APE_t.NcsiBuildTime. */ -typedef register_container RegAPENcsiBuildTime_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiBuildTime_t; - -#define REG_APE_NCSI_BUILD_TIME_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0014814) /* */ -/** @brief Register definition for @ref APE_t.NcsiBuildTime2. */ -typedef register_container RegAPENcsiBuildTime2_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiBuildTime2_t; - -#define REG_APE_NCSI_BUILD_TIME_3 ((volatile BCM5719_APE_H_uint32_t*)0xc0014818) /* */ -/** @brief Register definition for @ref APE_t.NcsiBuildTime3. */ -typedef register_container RegAPENcsiBuildTime3_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiBuildTime3_t; - -#define REG_APE_NCSI_BUILD_DATE ((volatile BCM5719_APE_H_uint32_t*)0xc001481c) /* ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero. */ -/** @brief Register definition for @ref APE_t.NcsiBuildDate. */ -typedef register_container RegAPENcsiBuildDate_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiBuildDate_t; - -#define REG_APE_NCSI_BUILD_DATE_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0014820) /* */ -/** @brief Register definition for @ref APE_t.NcsiBuildDate2. */ -typedef register_container RegAPENcsiBuildDate2_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiBuildDate2_t; - -#define REG_APE_NCSI_BUILD_DATE_3 ((volatile BCM5719_APE_H_uint32_t*)0xc0014824) /* */ -/** @brief Register definition for @ref APE_t.NcsiBuildDate3. */ -typedef register_container RegAPENcsiBuildDate3_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiBuildDate3_t; - -#define REG_APE_CHIP_ID ((volatile BCM5719_APE_H_uint32_t*)0xc0014890) /* The APE code copies the contents of Chip ID to this word */ -/** @brief Register definition for @ref APE_t.ChipId. */ -typedef register_container RegAPEChipId_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPEChipId_t; - -#define REG_APE_NCSI_CHANNEL0_INFO ((volatile BCM5719_APE_H_uint32_t*)0xc0014900) /* */ -#define APE_NCSI_CHANNEL0_INFO_ENABLED_SHIFT 0u -#define APE_NCSI_CHANNEL0_INFO_ENABLED_MASK 0x1u -#define GET_APE_NCSI_CHANNEL0_INFO_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_NCSI_CHANNEL0_INFO_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define APE_NCSI_CHANNEL0_INFO_TX_PASSTHROUGH_SHIFT 1u -#define APE_NCSI_CHANNEL0_INFO_TX_PASSTHROUGH_MASK 0x2u -#define GET_APE_NCSI_CHANNEL0_INFO_TX_PASSTHROUGH(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_NCSI_CHANNEL0_INFO_TX_PASSTHROUGH(__val__) (((__val__) << 1u) & 0x2u) -#define APE_NCSI_CHANNEL0_INFO_READY_SHIFT 2u -#define APE_NCSI_CHANNEL0_INFO_READY_MASK 0x4u -#define GET_APE_NCSI_CHANNEL0_INFO_READY(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_NCSI_CHANNEL0_INFO_READY(__val__) (((__val__) << 2u) & 0x4u) -#define APE_NCSI_CHANNEL0_INFO_INIT_SHIFT 3u -#define APE_NCSI_CHANNEL0_INFO_INIT_MASK 0x8u -#define GET_APE_NCSI_CHANNEL0_INFO_INIT(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_APE_NCSI_CHANNEL0_INFO_INIT(__val__) (((__val__) << 3u) & 0x8u) -#define APE_NCSI_CHANNEL0_INFO_MFILT_SHIFT 4u -#define APE_NCSI_CHANNEL0_INFO_MFILT_MASK 0x10u -#define GET_APE_NCSI_CHANNEL0_INFO_MFILT(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_NCSI_CHANNEL0_INFO_MFILT(__val__) (((__val__) << 4u) & 0x10u) -#define APE_NCSI_CHANNEL0_INFO_BFILT_SHIFT 5u -#define APE_NCSI_CHANNEL0_INFO_BFILT_MASK 0x20u -#define GET_APE_NCSI_CHANNEL0_INFO_BFILT(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_NCSI_CHANNEL0_INFO_BFILT(__val__) (((__val__) << 5u) & 0x20u) -#define APE_NCSI_CHANNEL0_INFO_SERDES_SHIFT 6u -#define APE_NCSI_CHANNEL0_INFO_SERDES_MASK 0x40u -#define GET_APE_NCSI_CHANNEL0_INFO_SERDES(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_NCSI_CHANNEL0_INFO_SERDES(__val__) (((__val__) << 6u) & 0x40u) -#define APE_NCSI_CHANNEL0_INFO_VLAN_SHIFT 8u -#define APE_NCSI_CHANNEL0_INFO_VLAN_MASK 0x100u -#define GET_APE_NCSI_CHANNEL0_INFO_VLAN(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_APE_NCSI_CHANNEL0_INFO_VLAN(__val__) (((__val__) << 8u) & 0x100u) -#define APE_NCSI_CHANNEL0_INFO_B2H_SHIFT 10u -#define APE_NCSI_CHANNEL0_INFO_B2H_MASK 0x400u -#define GET_APE_NCSI_CHANNEL0_INFO_B2H(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_APE_NCSI_CHANNEL0_INFO_B2H(__val__) (((__val__) << 10u) & 0x400u) -#define APE_NCSI_CHANNEL0_INFO_B2N_SHIFT 11u -#define APE_NCSI_CHANNEL0_INFO_B2N_MASK 0x800u -#define GET_APE_NCSI_CHANNEL0_INFO_B2N(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_APE_NCSI_CHANNEL0_INFO_B2N(__val__) (((__val__) << 11u) & 0x800u) -#define APE_NCSI_CHANNEL0_INFO_EEE_SHIFT 12u -#define APE_NCSI_CHANNEL0_INFO_EEE_MASK 0x1000u -#define GET_APE_NCSI_CHANNEL0_INFO_EEE(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_APE_NCSI_CHANNEL0_INFO_EEE(__val__) (((__val__) << 12u) & 0x1000u) -#define APE_NCSI_CHANNEL0_INFO_DRIVER_SHIFT 14u -#define APE_NCSI_CHANNEL0_INFO_DRIVER_MASK 0x4000u -#define GET_APE_NCSI_CHANNEL0_INFO_DRIVER(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_APE_NCSI_CHANNEL0_INFO_DRIVER(__val__) (((__val__) << 14u) & 0x4000u) -#define APE_NCSI_CHANNEL0_INFO_PDEAD_SHIFT 15u -#define APE_NCSI_CHANNEL0_INFO_PDEAD_MASK 0x8000u -#define GET_APE_NCSI_CHANNEL0_INFO_PDEAD(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_APE_NCSI_CHANNEL0_INFO_PDEAD(__val__) (((__val__) << 15u) & 0x8000u) - -/** @brief Register definition for @ref APE_t.NcsiChannel0Info. */ -typedef register_container RegAPENcsiChannel0Info_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief This can be modified via NCSI SELECT PACKAGE and NCSI DESELECT PACKAGE. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enabled, 0, 1) - /** @brief TX passthrough has been enabled by BMC NCSI command. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXPassthrough, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Ready, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Init, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, MFILT, 4, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, BFILT, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, SERDES, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, VLAN, 8, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_9_9, 9, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, B2H, 10, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, B2N, 11, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EEE, 12, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_13_13, 13, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 14, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, PDead, 15, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_16, 16, 16) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_16, 16, 16) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, PDead, 15, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Driver, 14, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_13_13, 13, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EEE, 12, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, B2N, 11, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, B2H, 10, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_9_9, 9, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, VLAN, 8, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, SERDES, 6, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, BFILT, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, MFILT, 4, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Init, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Ready, 2, 1) - /** @brief TX passthrough has been enabled by BMC NCSI command. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXPassthrough, 1, 1) - /** @brief This can be modified via NCSI SELECT PACKAGE and NCSI DESELECT PACKAGE. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enabled, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "NcsiChannel0Info"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPENcsiChannel0Info_t() - { - /** @brief constructor for @ref APE_t.NcsiChannel0Info. */ - r32.setName("NcsiChannel0Info"); - bits.Enabled.setBaseRegister(&r32); - bits.Enabled.setName("Enabled"); - bits.TXPassthrough.setBaseRegister(&r32); - bits.TXPassthrough.setName("TXPassthrough"); - bits.Ready.setBaseRegister(&r32); - bits.Ready.setName("Ready"); - bits.Init.setBaseRegister(&r32); - bits.Init.setName("Init"); - bits.MFILT.setBaseRegister(&r32); - bits.MFILT.setName("MFILT"); - bits.BFILT.setBaseRegister(&r32); - bits.BFILT.setName("BFILT"); - bits.SERDES.setBaseRegister(&r32); - bits.SERDES.setName("SERDES"); - bits.VLAN.setBaseRegister(&r32); - bits.VLAN.setName("VLAN"); - bits.B2H.setBaseRegister(&r32); - bits.B2H.setName("B2H"); - bits.B2N.setBaseRegister(&r32); - bits.B2N.setName("B2N"); - bits.EEE.setBaseRegister(&r32); - bits.EEE.setName("EEE"); - bits.Driver.setBaseRegister(&r32); - bits.Driver.setName("Driver"); - bits.PDead.setBaseRegister(&r32); - bits.PDead.setName("PDead"); - } - RegAPENcsiChannel0Info_t& operator=(const RegAPENcsiChannel0Info_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPENcsiChannel0Info_t; - -#define REG_APE_NCSI_CHANNEL0_MCID ((volatile BCM5719_APE_H_uint32_t*)0xc0014904) /* AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mcid. */ -typedef register_container RegAPENcsiChannel0Mcid_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mcid_t; - -#define REG_APE_NCSI_CHANNEL0_AEN ((volatile BCM5719_APE_H_uint32_t*)0xc0014908) /* Set via NCSI ENABLE AEN. */ -#define APE_NCSI_CHANNEL0_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_SHIFT 0u -#define APE_NCSI_CHANNEL0_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_MASK 0x1u -#define GET_APE_NCSI_CHANNEL0_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_NCSI_CHANNEL0_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__val__) (((__val__) << 0u) & 0x1u) -#define APE_NCSI_CHANNEL0_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_SHIFT 1u -#define APE_NCSI_CHANNEL0_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_MASK 0x2u -#define GET_APE_NCSI_CHANNEL0_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_NCSI_CHANNEL0_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__val__) (((__val__) << 1u) & 0x2u) -#define APE_NCSI_CHANNEL0_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_SHIFT 2u -#define APE_NCSI_CHANNEL0_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_MASK 0x4u -#define GET_APE_NCSI_CHANNEL0_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_NCSI_CHANNEL0_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__val__) (((__val__) << 2u) & 0x4u) - -/** @brief Register definition for @ref APE_t.NcsiChannel0Aen. */ -typedef register_container RegAPENcsiChannel0Aen_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EnableLinkStatusChangeAEN, 0, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EnableConfigurationRequiredAEN, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EnableHostNCDriverStatusChangeAEN, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_3, 3, 29) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_3, 3, 29) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EnableHostNCDriverStatusChangeAEN, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EnableConfigurationRequiredAEN, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, EnableLinkStatusChangeAEN, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "NcsiChannel0Aen"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPENcsiChannel0Aen_t() - { - /** @brief constructor for @ref APE_t.NcsiChannel0Aen. */ - r32.setName("NcsiChannel0Aen"); - bits.EnableLinkStatusChangeAEN.setBaseRegister(&r32); - bits.EnableLinkStatusChangeAEN.setName("EnableLinkStatusChangeAEN"); - bits.EnableConfigurationRequiredAEN.setBaseRegister(&r32); - bits.EnableConfigurationRequiredAEN.setName("EnableConfigurationRequiredAEN"); - bits.EnableHostNCDriverStatusChangeAEN.setBaseRegister(&r32); - bits.EnableHostNCDriverStatusChangeAEN.setName("EnableHostNCDriverStatusChangeAEN"); - } - RegAPENcsiChannel0Aen_t& operator=(const RegAPENcsiChannel0Aen_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPENcsiChannel0Aen_t; - -#define REG_APE_NCSI_CHANNEL0_BFILT ((volatile BCM5719_APE_H_uint32_t*)0xc001490c) /* */ -#define APE_NCSI_CHANNEL0_BFILT_ARP_PACKET_SHIFT 0u -#define APE_NCSI_CHANNEL0_BFILT_ARP_PACKET_MASK 0x1u -#define GET_APE_NCSI_CHANNEL0_BFILT_ARP_PACKET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_NCSI_CHANNEL0_BFILT_ARP_PACKET(__val__) (((__val__) << 0u) & 0x1u) -#define APE_NCSI_CHANNEL0_BFILT_DHCP_CLIENT_PACKET_SHIFT 1u -#define APE_NCSI_CHANNEL0_BFILT_DHCP_CLIENT_PACKET_MASK 0x2u -#define GET_APE_NCSI_CHANNEL0_BFILT_DHCP_CLIENT_PACKET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_NCSI_CHANNEL0_BFILT_DHCP_CLIENT_PACKET(__val__) (((__val__) << 1u) & 0x2u) -#define APE_NCSI_CHANNEL0_BFILT_DHCP_SERVER_PACKET_SHIFT 2u -#define APE_NCSI_CHANNEL0_BFILT_DHCP_SERVER_PACKET_MASK 0x4u -#define GET_APE_NCSI_CHANNEL0_BFILT_DHCP_SERVER_PACKET(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_NCSI_CHANNEL0_BFILT_DHCP_SERVER_PACKET(__val__) (((__val__) << 2u) & 0x4u) -#define APE_NCSI_CHANNEL0_BFILT_NETBIOS_PACKET_SHIFT 3u -#define APE_NCSI_CHANNEL0_BFILT_NETBIOS_PACKET_MASK 0x8u -#define GET_APE_NCSI_CHANNEL0_BFILT_NETBIOS_PACKET(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_APE_NCSI_CHANNEL0_BFILT_NETBIOS_PACKET(__val__) (((__val__) << 3u) & 0x8u) - -/** @brief Register definition for @ref APE_t.NcsiChannel0Bfilt. */ -typedef register_container RegAPENcsiChannel0Bfilt_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ARPPacket, 0, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DHCPClientPacket, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DHCPServerPacket, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, NetBIOSPacket, 3, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_4, 4, 28) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_4, 4, 28) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, NetBIOSPacket, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DHCPServerPacket, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DHCPClientPacket, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ARPPacket, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "NcsiChannel0Bfilt"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPENcsiChannel0Bfilt_t() - { - /** @brief constructor for @ref APE_t.NcsiChannel0Bfilt. */ - r32.setName("NcsiChannel0Bfilt"); - bits.ARPPacket.setBaseRegister(&r32); - bits.ARPPacket.setName("ARPPacket"); - bits.DHCPClientPacket.setBaseRegister(&r32); - bits.DHCPClientPacket.setName("DHCPClientPacket"); - bits.DHCPServerPacket.setBaseRegister(&r32); - bits.DHCPServerPacket.setName("DHCPServerPacket"); - bits.NetBIOSPacket.setBaseRegister(&r32); - bits.NetBIOSPacket.setName("NetBIOSPacket"); - } - RegAPENcsiChannel0Bfilt_t& operator=(const RegAPENcsiChannel0Bfilt_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPENcsiChannel0Bfilt_t; - -#define REG_APE_NCSI_CHANNEL0_MFILT ((volatile BCM5719_APE_H_uint32_t*)0xc0014910) /* */ -#define APE_NCSI_CHANNEL0_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_SHIFT 0u -#define APE_NCSI_CHANNEL0_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_MASK 0x1u -#define GET_APE_NCSI_CHANNEL0_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_NCSI_CHANNEL0_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_NCSI_CHANNEL0_MFILT_IPV6_ROUTER_ADVERTISEMENT_SHIFT 1u -#define APE_NCSI_CHANNEL0_MFILT_IPV6_ROUTER_ADVERTISEMENT_MASK 0x2u -#define GET_APE_NCSI_CHANNEL0_MFILT_IPV6_ROUTER_ADVERTISEMENT(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_NCSI_CHANNEL0_MFILT_IPV6_ROUTER_ADVERTISEMENT(__val__) (((__val__) << 1u) & 0x2u) -#define APE_NCSI_CHANNEL0_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_SHIFT 2u -#define APE_NCSI_CHANNEL0_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_MASK 0x4u -#define GET_APE_NCSI_CHANNEL0_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_NCSI_CHANNEL0_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__val__) (((__val__) << 2u) & 0x4u) - -/** @brief Register definition for @ref APE_t.NcsiChannel0Mfilt. */ -typedef register_container RegAPENcsiChannel0Mfilt_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPv6NeighbourAdvertisement, 0, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPv6RouterAdvertisement, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DHCPv6RelayandServerMulticast, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_3, 3, 29) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_3, 3, 29) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, DHCPv6RelayandServerMulticast, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPv6RouterAdvertisement, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPv6NeighbourAdvertisement, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "NcsiChannel0Mfilt"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPENcsiChannel0Mfilt_t() - { - /** @brief constructor for @ref APE_t.NcsiChannel0Mfilt. */ - r32.setName("NcsiChannel0Mfilt"); - bits.IPv6NeighbourAdvertisement.setBaseRegister(&r32); - bits.IPv6NeighbourAdvertisement.setName("IPv6NeighbourAdvertisement"); - bits.IPv6RouterAdvertisement.setBaseRegister(&r32); - bits.IPv6RouterAdvertisement.setName("IPv6RouterAdvertisement"); - bits.DHCPv6RelayandServerMulticast.setBaseRegister(&r32); - bits.DHCPv6RelayandServerMulticast.setName("DHCPv6RelayandServerMulticast"); - } - RegAPENcsiChannel0Mfilt_t& operator=(const RegAPENcsiChannel0Mfilt_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPENcsiChannel0Mfilt_t; - -#define REG_APE_NCSI_CHANNEL0_SETTING_1 ((volatile BCM5719_APE_H_uint32_t*)0xc0014914) /* This is the "Link Settings" value from NCSI Set Link. */ -#define APE_NCSI_CHANNEL0_SETTING_1_AUTONEGOTIATION_ENABLED_SHIFT 0u -#define APE_NCSI_CHANNEL0_SETTING_1_AUTONEGOTIATION_ENABLED_MASK 0x1u -#define GET_APE_NCSI_CHANNEL0_SETTING_1_AUTONEGOTIATION_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_NCSI_CHANNEL0_SETTING_1_AUTONEGOTIATION_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10M_ENABLE_SHIFT 1u -#define APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10M_ENABLE_MASK 0x2u -#define GET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10M_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10M_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_100M_ENABLE_SHIFT 2u -#define APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_100M_ENABLE_MASK 0x4u -#define GET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_100M_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_100M_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_1000M_ENABLE_SHIFT 3u -#define APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_1000M_ENABLE_MASK 0x8u -#define GET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_1000M_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_1000M_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10G_ENABLE_SHIFT 4u -#define APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10G_ENABLE_MASK 0x10u -#define GET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10G_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_NCSI_CHANNEL0_SETTING_1_LINK_SPEED_10G_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define APE_NCSI_CHANNEL0_SETTING_1_HALF_DUPLEX_ENABLE_SHIFT 8u -#define APE_NCSI_CHANNEL0_SETTING_1_HALF_DUPLEX_ENABLE_MASK 0x100u -#define GET_APE_NCSI_CHANNEL0_SETTING_1_HALF_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_APE_NCSI_CHANNEL0_SETTING_1_HALF_DUPLEX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define APE_NCSI_CHANNEL0_SETTING_1_FULL_DUPLEX_ENABLE_SHIFT 9u -#define APE_NCSI_CHANNEL0_SETTING_1_FULL_DUPLEX_ENABLE_MASK 0x200u -#define GET_APE_NCSI_CHANNEL0_SETTING_1_FULL_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_APE_NCSI_CHANNEL0_SETTING_1_FULL_DUPLEX_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define APE_NCSI_CHANNEL0_SETTING_1_PAUSE_CAPABILITY_ENABLE_SHIFT 10u -#define APE_NCSI_CHANNEL0_SETTING_1_PAUSE_CAPABILITY_ENABLE_MASK 0x400u -#define GET_APE_NCSI_CHANNEL0_SETTING_1_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_APE_NCSI_CHANNEL0_SETTING_1_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define APE_NCSI_CHANNEL0_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_SHIFT 11u -#define APE_NCSI_CHANNEL0_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_MASK 0x800u -#define GET_APE_NCSI_CHANNEL0_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_APE_NCSI_CHANNEL0_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 11u) & 0x800u) -#define APE_NCSI_CHANNEL0_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_SHIFT 12u -#define APE_NCSI_CHANNEL0_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_MASK 0x1000u -#define GET_APE_NCSI_CHANNEL0_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_APE_NCSI_CHANNEL0_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__val__) (((__val__) << 12u) & 0x1000u) - -/** @brief Register definition for @ref APE_t.NcsiChannel0Setting1. */ -typedef register_container RegAPENcsiChannel0Setting1_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Autonegotiationenabled, 0, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed10Menable, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed100Menable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed1000Menable, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed10Genable, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_5, 5, 3) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halfduplexenable, 8, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Fullduplexenable, 9, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Pausecapabilityenable, 10, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Asymmetricpausecapabilityenable, 11, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, OEMlinksettingsfieldvalid, 12, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_13, 13, 19) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, OEMlinksettingsfieldvalid, 12, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Asymmetricpausecapabilityenable, 11, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Pausecapabilityenable, 10, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Fullduplexenable, 9, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halfduplexenable, 8, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_5, 5, 3) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed10Genable, 4, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed1000Menable, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed100Menable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed10Menable, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Autonegotiationenabled, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "NcsiChannel0Setting1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPENcsiChannel0Setting1_t() - { - /** @brief constructor for @ref APE_t.NcsiChannel0Setting1. */ - r32.setName("NcsiChannel0Setting1"); - bits.Autonegotiationenabled.setBaseRegister(&r32); - bits.Autonegotiationenabled.setName("Autonegotiationenabled"); - bits.LinkSpeed10Menable.setBaseRegister(&r32); - bits.LinkSpeed10Menable.setName("LinkSpeed10Menable"); - bits.LinkSpeed100Menable.setBaseRegister(&r32); - bits.LinkSpeed100Menable.setName("LinkSpeed100Menable"); - bits.LinkSpeed1000Menable.setBaseRegister(&r32); - bits.LinkSpeed1000Menable.setName("LinkSpeed1000Menable"); - bits.LinkSpeed10Genable.setBaseRegister(&r32); - bits.LinkSpeed10Genable.setName("LinkSpeed10Genable"); - bits.Halfduplexenable.setBaseRegister(&r32); - bits.Halfduplexenable.setName("Halfduplexenable"); - bits.Fullduplexenable.setBaseRegister(&r32); - bits.Fullduplexenable.setName("Fullduplexenable"); - bits.Pausecapabilityenable.setBaseRegister(&r32); - bits.Pausecapabilityenable.setName("Pausecapabilityenable"); - bits.Asymmetricpausecapabilityenable.setBaseRegister(&r32); - bits.Asymmetricpausecapabilityenable.setName("Asymmetricpausecapabilityenable"); - bits.OEMlinksettingsfieldvalid.setBaseRegister(&r32); - bits.OEMlinksettingsfieldvalid.setName("OEMlinksettingsfieldvalid"); - } - RegAPENcsiChannel0Setting1_t& operator=(const RegAPENcsiChannel0Setting1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPENcsiChannel0Setting1_t; - -#define REG_APE_NCSI_CHANNEL0_SETTING_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0014918) /* This is the "OEM Settings" value from NCSI Set Link. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Setting2. */ -typedef register_container RegAPENcsiChannel0Setting2_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Setting2_t; - -#define REG_APE_NCSI_CHANNEL0_VLAN ((volatile BCM5719_APE_H_uint32_t*)0xc001491c) /* Receives VLAN mode from NCSI specification "Enable VLAN" command. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Vlan. */ -typedef register_container RegAPENcsiChannel0Vlan_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Vlan_t; - -#define REG_APE_NCSI_CHANNEL0_ALT_HOST_MAC_HIGH ((volatile BCM5719_APE_H_uint32_t*)0xc0014924) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0AltHostMacHigh. */ -typedef register_container RegAPENcsiChannel0AltHostMacHigh_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0AltHostMacHigh_t; - -#define REG_APE_NCSI_CHANNEL0_ALT_HOST_MAC_MID ((volatile BCM5719_APE_H_uint32_t*)0xc0014928) /* Lower 16 bits of this word contains mid 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0AltHostMacMid. */ -typedef register_container RegAPENcsiChannel0AltHostMacMid_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0AltHostMacMid_t; - -#define REG_APE_NCSI_CHANNEL0_ALT_HOST_MAC_LOW ((volatile BCM5719_APE_H_uint32_t*)0xc001492c) /* Lower 16 bits of this word contains low 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0AltHostMacLow. */ -typedef register_container RegAPENcsiChannel0AltHostMacLow_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0AltHostMacLow_t; - -#define REG_APE_NCSI_CHANNEL0_MAC0_HIGH ((volatile BCM5719_APE_H_uint32_t*)0xc0014934) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac0High. */ -typedef register_container RegAPENcsiChannel0Mac0High_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac0High_t; - -#define REG_APE_NCSI_CHANNEL0_MAC0_MID ((volatile BCM5719_APE_H_uint32_t*)0xc0014938) /* Lower 16 bits of this word contains mid 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac0Mid. */ -typedef register_container RegAPENcsiChannel0Mac0Mid_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac0Mid_t; - -#define REG_APE_NCSI_CHANNEL0_MAC0_LOW ((volatile BCM5719_APE_H_uint32_t*)0xc001493c) /* Lower 16 bits of this word contains low 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac0Low. */ -typedef register_container RegAPENcsiChannel0Mac0Low_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac0Low_t; - -#define REG_APE_NCSI_CHANNEL0_MAC1_HIGH ((volatile BCM5719_APE_H_uint32_t*)0xc0014944) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac1High. */ -typedef register_container RegAPENcsiChannel0Mac1High_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac1High_t; - -#define REG_APE_NCSI_CHANNEL0_MAC1_MID ((volatile BCM5719_APE_H_uint32_t*)0xc0014948) /* Lower 16 bits of this word contains mid 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac1Mid. */ -typedef register_container RegAPENcsiChannel0Mac1Mid_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac1Mid_t; - -#define REG_APE_NCSI_CHANNEL0_MAC1_LOW ((volatile BCM5719_APE_H_uint32_t*)0xc001494c) /* Lower 16 bits of this word contains low 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac1Low. */ -typedef register_container RegAPENcsiChannel0Mac1Low_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac1Low_t; - -#define REG_APE_NCSI_CHANNEL0_MAC2_HIGH ((volatile BCM5719_APE_H_uint32_t*)0xc0014954) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac2High. */ -typedef register_container RegAPENcsiChannel0Mac2High_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac2High_t; - -#define REG_APE_NCSI_CHANNEL0_MAC2_MID ((volatile BCM5719_APE_H_uint32_t*)0xc0014958) /* Lower 16 bits of this word contains mid 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac2Mid. */ -typedef register_container RegAPENcsiChannel0Mac2Mid_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac2Mid_t; - -#define REG_APE_NCSI_CHANNEL0_MAC2_LOW ((volatile BCM5719_APE_H_uint32_t*)0xc001495c) /* Lower 16 bits of this word contains low 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac2Low. */ -typedef register_container RegAPENcsiChannel0Mac2Low_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac2Low_t; - -#define REG_APE_NCSI_CHANNEL0_MAC3_HIGH ((volatile BCM5719_APE_H_uint32_t*)0xc0014964) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac3High. */ -typedef register_container RegAPENcsiChannel0Mac3High_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac3High_t; - -#define REG_APE_NCSI_CHANNEL0_MAC3_MID ((volatile BCM5719_APE_H_uint32_t*)0xc0014968) /* Lower 16 bits of this word contains mid 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac3Mid. */ -typedef register_container RegAPENcsiChannel0Mac3Mid_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac3Mid_t; - -#define REG_APE_NCSI_CHANNEL0_MAC3_LOW ((volatile BCM5719_APE_H_uint32_t*)0xc001496c) /* Lower 16 bits of this word contains low 16 bits of the MAC. */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac3Low. */ -typedef register_container RegAPENcsiChannel0Mac3Low_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac3Low_t; - -#define REG_APE_NCSI_CHANNEL0_MAC0_VLAN_VALID ((volatile BCM5719_APE_H_uint32_t*)0xc0014970) /* Nonzero indicates VLAN field is valid */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac0VlanValid. */ -typedef register_container RegAPENcsiChannel0Mac0VlanValid_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac0VlanValid_t; - -#define REG_APE_NCSI_CHANNEL0_MAC0_VLAN ((volatile BCM5719_APE_H_uint32_t*)0xc0014974) /* */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac0Vlan. */ -typedef register_container RegAPENcsiChannel0Mac0Vlan_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac0Vlan_t; - -#define REG_APE_NCSI_CHANNEL0_MAC1_VLAN_VALID ((volatile BCM5719_APE_H_uint32_t*)0xc0014978) /* Nonzero indicates VLAN field is valid */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac1VlanValid. */ -typedef register_container RegAPENcsiChannel0Mac1VlanValid_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac1VlanValid_t; - -#define REG_APE_NCSI_CHANNEL0_MAC1_VLAN ((volatile BCM5719_APE_H_uint32_t*)0xc001497c) /* */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Mac1Vlan. */ -typedef register_container RegAPENcsiChannel0Mac1Vlan_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Mac1Vlan_t; - -#define REG_APE_NCSI_CHANNEL0_STATUS ((volatile BCM5719_APE_H_uint32_t*)0xc0014980) /* */ -#define APE_NCSI_CHANNEL0_STATUS_LINK_UP_SHIFT 0u -#define APE_NCSI_CHANNEL0_STATUS_LINK_UP_MASK 0x1u -#define GET_APE_NCSI_CHANNEL0_STATUS_LINK_UP(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_NCSI_CHANNEL0_STATUS_LINK_UP(__val__) (((__val__) << 0u) & 0x1u) -#define APE_NCSI_CHANNEL0_STATUS_LINK_STATUS_SHIFT 1u -#define APE_NCSI_CHANNEL0_STATUS_LINK_STATUS_MASK 0x1eu -#define GET_APE_NCSI_CHANNEL0_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x1e) >> 1u) -#define SET_APE_NCSI_CHANNEL0_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x1eu) -#define APE_NCSI_CHANNEL0_STATUS_SERDES_SHIFT 5u -#define APE_NCSI_CHANNEL0_STATUS_SERDES_MASK 0x20u -#define GET_APE_NCSI_CHANNEL0_STATUS_SERDES(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_NCSI_CHANNEL0_STATUS_SERDES(__val__) (((__val__) << 5u) & 0x20u) -#define APE_NCSI_CHANNEL0_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 6u -#define APE_NCSI_CHANNEL0_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x40u -#define GET_APE_NCSI_CHANNEL0_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_NCSI_CHANNEL0_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 6u) & 0x40u) -#define APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_SHIFT 9u -#define APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_MASK 0x200u -#define GET_APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__val__) (((__val__) << 9u) & 0x200u) -#define APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_SHIFT 10u -#define APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_MASK 0x400u -#define GET_APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_APE_NCSI_CHANNEL0_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__val__) (((__val__) << 10u) & 0x400u) - -/** @brief Register definition for @ref APE_t.NcsiChannel0Status. */ -typedef register_container RegAPENcsiChannel0Status_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Linkup, 0, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkStatus, 1, 4) - /** @brief Set from MII_REG_CONTROL__AUTO_NEGOTIATION_ENABLE. Set unconditionally in SERDES case. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, SERDES, 5, 1) - /** @brief Set if autonegotiation is complete. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, AutonegotiationComplete, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_8_7, 7, 2) - /** @brief Link partner 1000BASE-T full duplex capable */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed1000MFullDuplexCapable, 9, 1) - /** @brief Link partner 1000BASE-T half duplex capable */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed1000MHalsDuplexCapable, 10, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_11, 11, 21) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_11, 11, 21) - /** @brief Link partner 1000BASE-T half duplex capable */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed1000MHalsDuplexCapable, 10, 1) - /** @brief Link partner 1000BASE-T full duplex capable */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkSpeed1000MFullDuplexCapable, 9, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_8_7, 7, 2) - /** @brief Set if autonegotiation is complete. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, AutonegotiationComplete, 6, 1) - /** @brief Set from MII_REG_CONTROL__AUTO_NEGOTIATION_ENABLE. Set unconditionally in SERDES case. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, SERDES, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, LinkStatus, 1, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Linkup, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "NcsiChannel0Status"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPENcsiChannel0Status_t() - { - /** @brief constructor for @ref APE_t.NcsiChannel0Status. */ - r32.setName("NcsiChannel0Status"); - bits.Linkup.setBaseRegister(&r32); - bits.Linkup.setName("Linkup"); - bits.LinkStatus.setBaseRegister(&r32); - bits.LinkStatus.setName("LinkStatus"); - bits.SERDES.setBaseRegister(&r32); - bits.SERDES.setName("SERDES"); - bits.AutonegotiationComplete.setBaseRegister(&r32); - bits.AutonegotiationComplete.setName("AutonegotiationComplete"); - bits.LinkSpeed1000MFullDuplexCapable.setBaseRegister(&r32); - bits.LinkSpeed1000MFullDuplexCapable.setName("LinkSpeed1000MFullDuplexCapable"); - bits.LinkSpeed1000MHalsDuplexCapable.setBaseRegister(&r32); - bits.LinkSpeed1000MHalsDuplexCapable.setName("LinkSpeed1000MHalsDuplexCapable"); - } - RegAPENcsiChannel0Status_t& operator=(const RegAPENcsiChannel0Status_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPENcsiChannel0Status_t; - -#define REG_APE_NCSI_CHANNEL0_RESET_COUNT ((volatile BCM5719_APE_H_uint32_t*)0xc0014984) /* */ -/** @brief Register definition for @ref APE_t.NcsiChannel0ResetCount. */ -typedef register_container RegAPENcsiChannel0ResetCount_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0ResetCount_t; - -#define REG_APE_NCSI_CHANNEL0_PXE ((volatile BCM5719_APE_H_uint32_t*)0xc0014988) /* */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Pxe. */ -typedef register_container RegAPENcsiChannel0Pxe_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Pxe_t; - -#define REG_APE_NCSI_CHANNEL0_DROPFIL ((volatile BCM5719_APE_H_uint32_t*)0xc001498c) /* */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Dropfil. */ -typedef register_container RegAPENcsiChannel0Dropfil_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Dropfil_t; - -#define REG_APE_NCSI_CHANNEL0_SLINK ((volatile BCM5719_APE_H_uint32_t*)0xc0014990) /* */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Slink. */ -typedef register_container RegAPENcsiChannel0Slink_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Slink_t; - -#define REG_APE_NCSI_CHANNEL0_DBG ((volatile BCM5719_APE_H_uint32_t*)0xc00149a0) /* */ -/** @brief Register definition for @ref APE_t.NcsiChannel0Dbg. */ -typedef register_container RegAPENcsiChannel0Dbg_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0Dbg_t; - -#define REG_APE_NCSI_CHANNEL0_CTRLSTAT_RX ((volatile BCM5719_APE_H_uint32_t*)0xc00149b0) /* */ -/** @brief Register definition for @ref APE_t.NcsiChannel0CtrlstatRx. */ -typedef register_container RegAPENcsiChannel0CtrlstatRx_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; -} RegAPENcsiChannel0CtrlstatRx_t; - #define REG_APE_PER_LOCK_REQUEST_PHY0 ((volatile BCM5719_APE_H_uint32_t*)0xc0018400) /* This register, and the following Per Lock Request registers work the same. The tg3 driver uses 0x0000_1000 (APELOCK_PER_REQ_DRIVER) for PHY ports (or always for function 0). */ #define APE_PER_LOCK_REQUEST_PHY0_APE_SHIFT 0u #define APE_PER_LOCK_REQUEST_PHY0_APE_MASK 0x1u @@ -4231,295 +2712,7 @@ typedef struct { RegAPECm3_t Cm3; /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_268[4029]; - - /** @brief APE_APE_MAGIC ('APE!') when all is well. */ - RegAPESegSig_t SegSig; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_16388[2]; - - /** @brief */ - RegAPEFwStatus_t FwStatus; - - /** @brief */ - RegAPEFwFeatures_t FwFeatures; - - /** @brief Unknown. */ - RegAPE4014_t _4014; - - /** @brief */ - RegAPEFwVersion_t FwVersion; - - /** @brief Specifies the offset of a scratchpad area, relative to the start of the APE SHM area (i.e., relative to APE_REG(0x4000)). */ - RegAPESegMessageBufferOffset_t SegMessageBufferOffset; - - /** @brief Specifies the size of the scratchpad area in bytes. */ - RegAPESegMessageBufferLength_t SegMessageBufferLength; - - /** @brief Unknown. Bootcode related. */ - RegAPE4024_t _4024; - - /** @brief Unknown. Bootcode related. */ - RegAPE4028_t _4028; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_16428[53]; - - /** @brief Set to APE_RCPU_MAGIC ('RCPU') by RX CPU. */ - RegAPERcpuSegSig_t RcpuSegSig; - - /** @brief Set to 0x34. */ - RegAPERcpuSegLength_t RcpuSegLength; - - /** @brief Incremented by RX CPU every boot. */ - RegAPERcpuInitCount_t RcpuInitCount; - - /** @brief Set to the bootcode version. e.g. 0x0127 -> v1.39. */ - RegAPERcpuFwVersion_t RcpuFwVersion; - - /** @brief Set to */ - RegAPERcpuCfgFeature_t RcpuCfgFeature; - - /** @brief Set to PCI Vendor/Device ID by S2. */ - RegAPERcpuPciVendorDeviceId_t RcpuPciVendorDeviceId; - - /** @brief Set to PCI Subsystem Vendor/Subsystem ID by S2. */ - RegAPERcpuPciSubsystemId_t RcpuPciSubsystemId; - - /** @brief Unknown. Incremented by frobnicating routine. */ - RegAPERcpuApeResetCount_t RcpuApeResetCount; - - /** @brief Unknown. Written by frobnicating routine. */ - RegAPERcpuLastApeStatus_t RcpuLastApeStatus; - - /** @brief Unknown. */ - RegAPERcpuLastApeFwStatus_t RcpuLastApeFwStatus; - - /** @brief Set from */ - RegAPERcpuCfgHw_t RcpuCfgHw; - - /** @brief Set from */ - RegAPERcpuCfgHw2_t RcpuCfgHw2; - - /** @brief Set from */ - RegAPERcpuCpmuStatus_t RcpuCpmuStatus; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_16692[51]; - - /** @brief Set to APE_HOST_MAGIC ('HOST') to indicate the section is valid. */ - RegAPEHostSegSig_t HostSegSig; - - /** @brief Set to 0x20. */ - RegAPEHostSegLen_t HostSegLen; - - /** @brief Incremented by host on every initialization. */ - RegAPEHostInitCount_t HostInitCount; - - /** @brief Linux sets this to 0xF0MM_mm00, where M is the major version of Linux and m is the minor version. */ - RegAPEHostDriverId_t HostDriverId; - - /** @brief */ - RegAPEHostBehavior_t HostBehavior; - - /** @brief In milliseconds. Set to 0 to disable heartbeating. */ - RegAPEHeartbeatInterval_t HeartbeatInterval; - - /** @brief */ - RegAPEHeartbeatCount_t HeartbeatCount; - - /** @brief */ - RegAPEHostDriverState_t HostDriverState; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_16928[1]; - - /** @brief */ - RegAPEWolSpeed_t WolSpeed; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_16936[54]; - - /** @brief */ - RegAPEEventStatus_t EventStatus; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_17156[1]; - - /** @brief This is set to APE_PROT_MAGIC ('PROT') on all functions. If it is 'PROT', the following fields (MAC0_HIGH/LOW) are valid */ - RegAPEProtMagic_t ProtMagic; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_17164[2]; - - /** @brief High 16 bits of MAC address 0. Only valid if */ - RegAPEProtMac0High_t ProtMac0High; - - /** @brief Low 16 bits of MAC address 0. */ - RegAPEProtMac0Low_t ProtMac0Low; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_17180[313]; - - /** @brief Set to NCSI_MAGIC ('NCSI') by APE firmware. NOTE: all words in the NCSI section are available in the function 0 SHM area only. */ - RegAPENcsiSig_t NcsiSig; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_18436[3]; - - /** @brief ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero. */ - RegAPENcsiBuildTime_t NcsiBuildTime; - - /** @brief */ - RegAPENcsiBuildTime2_t NcsiBuildTime2; - - /** @brief */ - RegAPENcsiBuildTime3_t NcsiBuildTime3; - - /** @brief ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero. */ - RegAPENcsiBuildDate_t NcsiBuildDate; - - /** @brief */ - RegAPENcsiBuildDate2_t NcsiBuildDate2; - - /** @brief */ - RegAPENcsiBuildDate3_t NcsiBuildDate3; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_18472[26]; - - /** @brief The APE code copies the contents of Chip ID to this word */ - RegAPEChipId_t ChipId; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_18580[27]; - - /** @brief */ - RegAPENcsiChannel0Info_t NcsiChannel0Info; - - /** @brief AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs. */ - RegAPENcsiChannel0Mcid_t NcsiChannel0Mcid; - - /** @brief Set via NCSI ENABLE AEN. */ - RegAPENcsiChannel0Aen_t NcsiChannel0Aen; - - /** @brief */ - RegAPENcsiChannel0Bfilt_t NcsiChannel0Bfilt; - - /** @brief */ - RegAPENcsiChannel0Mfilt_t NcsiChannel0Mfilt; - - /** @brief This is the "Link Settings" value from NCSI Set Link. */ - RegAPENcsiChannel0Setting1_t NcsiChannel0Setting1; - - /** @brief This is the "OEM Settings" value from NCSI Set Link. */ - RegAPENcsiChannel0Setting2_t NcsiChannel0Setting2; - - /** @brief Receives VLAN mode from NCSI specification "Enable VLAN" command. */ - RegAPENcsiChannel0Vlan_t NcsiChannel0Vlan; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_18720[1]; - - /** @brief Lower 16 bits of this word contains upper 16 bits of the MAC. */ - RegAPENcsiChannel0AltHostMacHigh_t NcsiChannel0AltHostMacHigh; - - /** @brief Lower 16 bits of this word contains mid 16 bits of the MAC. */ - RegAPENcsiChannel0AltHostMacMid_t NcsiChannel0AltHostMacMid; - - /** @brief Lower 16 bits of this word contains low 16 bits of the MAC. */ - RegAPENcsiChannel0AltHostMacLow_t NcsiChannel0AltHostMacLow; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_18736[1]; - - /** @brief Lower 16 bits of this word contains upper 16 bits of the MAC. */ - RegAPENcsiChannel0Mac0High_t NcsiChannel0Mac0High; - - /** @brief Lower 16 bits of this word contains mid 16 bits of the MAC. */ - RegAPENcsiChannel0Mac0Mid_t NcsiChannel0Mac0Mid; - - /** @brief Lower 16 bits of this word contains low 16 bits of the MAC. */ - RegAPENcsiChannel0Mac0Low_t NcsiChannel0Mac0Low; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_18752[1]; - - /** @brief Lower 16 bits of this word contains upper 16 bits of the MAC. */ - RegAPENcsiChannel0Mac1High_t NcsiChannel0Mac1High; - - /** @brief Lower 16 bits of this word contains mid 16 bits of the MAC. */ - RegAPENcsiChannel0Mac1Mid_t NcsiChannel0Mac1Mid; - - /** @brief Lower 16 bits of this word contains low 16 bits of the MAC. */ - RegAPENcsiChannel0Mac1Low_t NcsiChannel0Mac1Low; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_18768[1]; - - /** @brief Lower 16 bits of this word contains upper 16 bits of the MAC. */ - RegAPENcsiChannel0Mac2High_t NcsiChannel0Mac2High; - - /** @brief Lower 16 bits of this word contains mid 16 bits of the MAC. */ - RegAPENcsiChannel0Mac2Mid_t NcsiChannel0Mac2Mid; - - /** @brief Lower 16 bits of this word contains low 16 bits of the MAC. */ - RegAPENcsiChannel0Mac2Low_t NcsiChannel0Mac2Low; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_18784[1]; - - /** @brief Lower 16 bits of this word contains upper 16 bits of the MAC. */ - RegAPENcsiChannel0Mac3High_t NcsiChannel0Mac3High; - - /** @brief Lower 16 bits of this word contains mid 16 bits of the MAC. */ - RegAPENcsiChannel0Mac3Mid_t NcsiChannel0Mac3Mid; - - /** @brief Lower 16 bits of this word contains low 16 bits of the MAC. */ - RegAPENcsiChannel0Mac3Low_t NcsiChannel0Mac3Low; - - /** @brief Nonzero indicates VLAN field is valid */ - RegAPENcsiChannel0Mac0VlanValid_t NcsiChannel0Mac0VlanValid; - - /** @brief */ - RegAPENcsiChannel0Mac0Vlan_t NcsiChannel0Mac0Vlan; - - /** @brief Nonzero indicates VLAN field is valid */ - RegAPENcsiChannel0Mac1VlanValid_t NcsiChannel0Mac1VlanValid; - - /** @brief */ - RegAPENcsiChannel0Mac1Vlan_t NcsiChannel0Mac1Vlan; - - /** @brief */ - RegAPENcsiChannel0Status_t NcsiChannel0Status; - - /** @brief */ - RegAPENcsiChannel0ResetCount_t NcsiChannel0ResetCount; - - /** @brief */ - RegAPENcsiChannel0Pxe_t NcsiChannel0Pxe; - - /** @brief */ - RegAPENcsiChannel0Dropfil_t NcsiChannel0Dropfil; - - /** @brief */ - RegAPENcsiChannel0Slink_t NcsiChannel0Slink; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_18836[3]; - - /** @brief */ - RegAPENcsiChannel0Dbg_t NcsiChannel0Dbg; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_18852[3]; - - /** @brief */ - RegAPENcsiChannel0CtrlstatRx_t NcsiChannel0CtrlstatRx; - - /** @brief Reserved bytes to pad out data structure. */ - BCM5719_APE_H_uint32_t reserved_18868[3731]; + BCM5719_APE_H_uint32_t reserved_268[8381]; /** @brief This register, and the following Per Lock Request registers work the same. The tg3 driver uses 0x0000_1000 (APELOCK_PER_REQ_DRIVER) for PHY ports (or always for function 0). */ RegAPEPerLockRequestPhy0_t PerLockRequestPhy0; diff --git a/ipxact/APE.xml b/ipxact/APE.xml index cd7a7ae..1b79605 100644 --- a/ipxact/APE.xml +++ b/ipxact/APE.xml @@ -98,5 +98,73 @@ <ipxact:volatile>false</ipxact:volatile> </ipxact:addressBlock> </ipxact:memoryMap> + + <!-- APE SHM Registers: 0x6022_0000 to 0x6022_0FFF--> + <ipxact:memoryMap> + <ipxact:name>SHM</ipxact:name> + <ipxact:description>Device SHM Registers, function 0</ipxact:description> + <ipxact:addressBlock> + <ipxact:name>SHM</ipxact:name> + <ipxact:description>Device SHM Registers, function 0</ipxact:description> + <ipxact:baseAddress>0x60220000</ipxact:baseAddress> + <!-- LINK: addressBlockDefinitionGroup: see 6.9.3, Address blockdefinition group --> + <!-- LINK: memoryBlockData: see 6.9.4, memoryBlockData group --> + <ipxact:usage>register</ipxact:usage> + <ipxact:volatile>false</ipxact:volatile> + </ipxact:addressBlock> + <ipxact:addressUnitBits>8</ipxact:addressUnitBits> + </ipxact:memoryMap> + + <!-- APE SHM Registers: 0x6022_1000 to 0x6022_1FFF--> + <ipxact:memoryMap> + <ipxact:name>SHM1</ipxact:name> + <ipxact:description>Device SHM Registers, function 1</ipxact:description> + <ipxact:addressBlock> + <ipxact:name>SHM1</ipxact:name> + <ipxact:description>Device SHM Registers, function 1</ipxact:description> + <ipxact:typeIdentifier>SHM</ipxact:typeIdentifier>> + <ipxact:baseAddress>0x60221000</ipxact:baseAddress> + <!-- LINK: addressBlockDefinitionGroup: see 6.9.3, Address blockdefinition group --> + <!-- LINK: memoryBlockData: see 6.9.4, memoryBlockData group --> + <ipxact:usage>register</ipxact:usage> + <ipxact:volatile>false</ipxact:volatile> + </ipxact:addressBlock> + <ipxact:addressUnitBits>8</ipxact:addressUnitBits> + </ipxact:memoryMap> + + <!-- APE SHM Registers: 0x6022_2000 to 0x6022_2FFF--> + <ipxact:memoryMap> + <ipxact:name>SHM2</ipxact:name> + <ipxact:description>Device SHM Registers, function 2</ipxact:description> + <ipxact:addressBlock> + <ipxact:name>SHM2</ipxact:name> + <ipxact:description>Device SHM Registers, function 2</ipxact:description> + <ipxact:typeIdentifier>SHM</ipxact:typeIdentifier>> + <ipxact:baseAddress>0x60222000</ipxact:baseAddress> + <!-- LINK: addressBlockDefinitionGroup: see 6.9.3, Address blockdefinition group --> + <!-- LINK: memoryBlockData: see 6.9.4, memoryBlockData group --> + <ipxact:usage>register</ipxact:usage> + <ipxact:volatile>false</ipxact:volatile> + </ipxact:addressBlock> + <ipxact:addressUnitBits>8</ipxact:addressUnitBits> + </ipxact:memoryMap> + + <!-- APE SHM Registers: 0x6022_3000 to 0x6022_3FFF--> + <ipxact:memoryMap> + <ipxact:name>SHM3</ipxact:name> + <ipxact:description>Device SHM Registers, function 3</ipxact:description> + <ipxact:addressBlock> + <ipxact:name>SHM3</ipxact:name> + <ipxact:description>Device SHM Registers, function 3</ipxact:description> + <ipxact:typeIdentifier>SHM</ipxact:typeIdentifier>> + <ipxact:baseAddress>0x60223000</ipxact:baseAddress> + <!-- LINK: addressBlockDefinitionGroup: see 6.9.3, Address blockdefinition group --> + <!-- LINK: memoryBlockData: see 6.9.4, memoryBlockData group --> + <ipxact:usage>register</ipxact:usage> + <ipxact:volatile>false</ipxact:volatile> + </ipxact:addressBlock> + <ipxact:addressUnitBits>8</ipxact:addressUnitBits> + </ipxact:memoryMap> + </ipxact:memoryMaps> </ipxact:component> diff --git a/ipxact/SHM.xml b/ipxact/SHM.xml new file mode 100644 index 0000000..52cdc00 --- /dev/null +++ b/ipxact/SHM.xml @@ -0,0 +1,1077 @@ +<?xml version="1.0" encoding="UTF-8"?> +<ipxact:component xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:ipxact="http://www.accellera.org/XMLSchema/IPXACT/1685-2014" xsi:schemaLocation="http://www.accellera.org/images/XMLSchema/IPXACT/1685-2014/index.xsd"> + <ipxact:vendor>meklort</ipxact:vendor> + <ipxact:library><PROJECT></ipxact:library> + <ipxact:name>SHM Register Definitions</ipxact:name> + <ipxact:version>1.0</ipxact:version> + <ipxact:memoryMaps> + <!-- APE SHM Registers: 0xC001_4000 to C001_5FFF (MIPS)--> + <!-- APE SHM Registers: 0x6022_0000 to A022_0FFF (APE, function 0)--> + <!-- APE SHM Registers: 0x6022_1000 to A022_1FFF (APE, function 1)--> + <!-- APE SHM Registers: 0x6022_2000 to A022_2FFF (APE, function 2)--> + <!-- APE SHM Registers: 0x6022_3000 to A022_3FFF (APE, function 3)--> + <ipxact:memoryMap> + <ipxact:name>SHM</ipxact:name> + <ipxact:description>Device APE SHM Registers</ipxact:description> + <ipxact:addressBlock> + <ipxact:name>SHM</ipxact:name> + <ipxact:typeIdentifier>SHM</ipxact:typeIdentifier>> + <ipxact:description>Device APE SHM Registers</ipxact:description> + <ipxact:baseAddress>0xC0014000</ipxact:baseAddress> + <!-- LINK: addressBlockDefinitionGroup: see 6.9.3, Address blockdefinition group --> + <!-- LINK: memoryBlockData: see 6.9.4, memoryBlockData group --> + <ipxact:register> + <ipxact:name>SEG_SIG</ipxact:name> + <ipxact:description>APE_APE_MAGIC ('APE!') when all is well.</ipxact:description> + <ipxact:addressOffset>0x0</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>FW_STATUS</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0xc</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>Ready</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>unknown_31_28</ipxact:name> + <ipxact:description>If this is all-ones, it appears to mean the APE FW is halted.</ipxact:description> + <ipxact:bitOffset>28</ipxact:bitOffset> + <ipxact:bitWidth>4</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>FW_FEATURES</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x10</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>NCSI</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>4014</ipxact:name> + <ipxact:description>Unknown.</ipxact:description> + <ipxact:addressOffset>0x14</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>FW_VERSION</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x18</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>Build</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Revision</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Minor</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Major</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>24</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>SEG_MESSAGE_BUFFER_OFFSET</ipxact:name> + <ipxact:description>Specifies the offset of a scratchpad area, relative to the start of the APE SHM area (i.e., relative to APE_REG(0x4000)).</ipxact:description> + <ipxact:addressOffset>0x1c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>SEG_MESSAGE_BUFFER_LENGTH</ipxact:name> + <ipxact:description>Specifies the size of the scratchpad area in bytes.</ipxact:description> + <ipxact:addressOffset>0x20</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>4024</ipxact:name> + <ipxact:description>Unknown. Bootcode related.</ipxact:description> + <ipxact:addressOffset>0x24</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>4028</ipxact:name> + <ipxact:description>Unknown. Bootcode related.</ipxact:description> + <ipxact:addressOffset>0x28</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_SEG_SIG</ipxact:name> + <ipxact:description>Set to APE_RCPU_MAGIC ('RCPU') by RX CPU.</ipxact:description> + <ipxact:addressOffset>0x100</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>Sig</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>32</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + <ipxact:enumeratedValues> + <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> + <ipxact:enumeratedValue> + <ipxact:name>RCPU_MAGIC</ipxact:name> + <ipxact:value>0x52435055</ipxact:value> + </ipxact:enumeratedValue> + </ipxact:enumeratedValues> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_SEG_LENGTH</ipxact:name> + <ipxact:description>Set to 0x34.</ipxact:description> + <ipxact:addressOffset>0x104</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_INIT_COUNT</ipxact:name> + <ipxact:description>Incremented by RX CPU every boot.</ipxact:description> + <ipxact:addressOffset>0x108</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_FW_VERSION</ipxact:name> + <ipxact:description>Set to the bootcode version. e.g. 0x0127 -> v1.39.</ipxact:description> + <ipxact:addressOffset>0x10c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_CFG_FEATURE</ipxact:name> + <ipxact:description>Set to </ipxact:description> + <ipxact:addressOffset>0x110</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_PCI_VENDOR_DEVICE_ID</ipxact:name> + <ipxact:description>Set to PCI Vendor/Device ID by S2.</ipxact:description> + <ipxact:addressOffset>0x114</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_PCI_SUBSYSTEM_ID</ipxact:name> + <ipxact:description>Set to PCI Subsystem Vendor/Subsystem ID by S2.</ipxact:description> + <ipxact:addressOffset>0x118</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_APE_RESET_COUNT</ipxact:name> + <ipxact:description>Unknown. Incremented by frobnicating routine.</ipxact:description> + <ipxact:addressOffset>0x11c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_LAST_APE_STATUS</ipxact:name> + <ipxact:description>Unknown. Written by frobnicating routine.</ipxact:description> + <ipxact:addressOffset>0x120</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_LAST_APE_FW_STATUS</ipxact:name> + <ipxact:description>Unknown. </ipxact:description> + <ipxact:addressOffset>0x124</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_CFG_HW</ipxact:name> + <ipxact:description>Set from </ipxact:description> + <ipxact:addressOffset>0x128</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_CFG_HW_2</ipxact:name> + <ipxact:description>Set from </ipxact:description> + <ipxact:addressOffset>0x12c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>RCPU_CPMU_STATUS</ipxact:name> + <ipxact:description>Set from </ipxact:description> + <ipxact:addressOffset>0x130</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>Address</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>16</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + <ipxact:enumeratedValues> + <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> + <ipxact:enumeratedValue> + <ipxact:name>ADDRESS</ipxact:name> + <ipxact:value>0x362C</ipxact:value> + </ipxact:enumeratedValue> + </ipxact:enumeratedValues> + </ipxact:field> + <ipxact:field> + <ipxact:name>Status</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>16</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>HOST_SEG_SIG</ipxact:name> + <ipxact:description>Set to APE_HOST_MAGIC ('HOST') to indicate the section is valid.</ipxact:description> + <ipxact:addressOffset>0x200</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>HOST_SEG_LEN</ipxact:name> + <ipxact:description>Set to 0x20.</ipxact:description> + <ipxact:addressOffset>0x204</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>HOST_INIT_COUNT</ipxact:name> + <ipxact:description>Incremented by host on every initialization.</ipxact:description> + <ipxact:addressOffset>0x208</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>HOST_DRIVER_ID</ipxact:name> + <ipxact:description>Linux sets this to 0xF0MM_mm00, where M is the major version of Linux and m is the minor version.</ipxact:description> + <ipxact:addressOffset>0x20c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>HOST_BEHAVIOR</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x210</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>No PHYLock</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>HEARTBEAT_INTERVAL</ipxact:name> + <ipxact:description>In milliseconds. Set to 0 to disable heartbeating.</ipxact:description> + <ipxact:addressOffset>0x214</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>HEARTBEAT_COUNT</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x218</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>HOST_DRIVER_STATE</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x21c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>WOL_SPEED</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x224</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>EVENT_STATUS</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x300</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>Driver Event</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>4</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Command</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>8</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + <ipxact:enumeratedValues> + <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> + <ipxact:enumeratedValue> + <ipxact:name>State Change</ipxact:name> + <ipxact:value>5</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>Scratchpad Read</ipxact:name> + <ipxact:value>22</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>Scratchpad Write</ipxact:name> + <ipxact:value>23</ipxact:value> + </ipxact:enumeratedValue> + </ipxact:enumeratedValues> + </ipxact:field> + <ipxact:field> + <ipxact:name>State</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>16</ipxact:bitOffset> + <ipxact:bitWidth>3</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + <ipxact:enumeratedValues> + <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> + <ipxact:enumeratedValue> + <ipxact:name>Start</ipxact:name> + <ipxact:value>1</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>Unload</ipxact:name> + <ipxact:value>2</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>WOL</ipxact:name> + <ipxact:value>3</ipxact:value> + </ipxact:enumeratedValue> + <ipxact:enumeratedValue> + <ipxact:name>Suspend</ipxact:name> + <ipxact:value>4</ipxact:value> + </ipxact:enumeratedValue> + </ipxact:enumeratedValues> + </ipxact:field> + <ipxact:field> + <ipxact:name>Pending</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>31</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>PROT_MAGIC</ipxact:name> + <ipxact:description>This is set to APE_PROT_MAGIC ('PROT') on all functions. If it is 'PROT', the following fields (MAC0_HIGH/LOW) are valid</ipxact:description> + <ipxact:addressOffset>0x308</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>PROT_MAC0_HIGH</ipxact:name> + <ipxact:description>High 16 bits of MAC address 0. Only valid if </ipxact:description> + <ipxact:addressOffset>0x314</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>PROT_MAC0_LOW</ipxact:name> + <ipxact:description>Low 16 bits of MAC address 0.</ipxact:description> + <ipxact:addressOffset>0x318</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_SIG</ipxact:name> + <ipxact:description>Set to NCSI_MAGIC ('NCSI') by APE firmware. NOTE: all words in the NCSI section are available in the function 0 SHM area only.</ipxact:description> + <ipxact:addressOffset>0x800</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_BUILD_TIME</ipxact:name> + <ipxact:description>ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero.</ipxact:description> + <ipxact:addressOffset>0x810</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_BUILD_TIME_2</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x814</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_BUILD_TIME_3</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x818</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_BUILD_DATE</ipxact:name> + <ipxact:description>ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero.</ipxact:description> + <ipxact:addressOffset>0x81c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_BUILD_DATE_2</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x820</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_BUILD_DATE_3</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x824</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>CHIP_ID</ipxact:name> + <ipxact:description>The APE code copies the contents of Chip ID to this word</ipxact:description> + <ipxact:addressOffset>0x890</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_INFO</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x900</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>Enabled</ipxact:name> + <ipxact:description>This can be modified via NCSI SELECT PACKAGE and NCSI DESELECT PACKAGE.</ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>TX Passthrough</ipxact:name> + <ipxact:description>TX passthrough has been enabled by BMC NCSI command.</ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Ready</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>2</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Init</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>3</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>MFILT</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>4</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>BFILT</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>5</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>SERDES</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>6</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>VLAN</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>B2H</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>10</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>B2N</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>11</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>EEE</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>12</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Driver</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>14</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>PDead</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>15</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MCID</ipxact:name> + <ipxact:description>AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs.</ipxact:description> + <ipxact:addressOffset>0x904</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_AEN</ipxact:name> + <ipxact:description>Set via NCSI ENABLE AEN.</ipxact:description> + <ipxact:addressOffset>0x908</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>Enable Link Status Change AEN</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Enable Configuration Required AEN</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Enable Host NC Driver Status Change AEN</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>2</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_BFILT</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x90c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>ARP Packet</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>DHCP Client Packet</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>DHCP Server Packet</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>2</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>NetBIOS Packet</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>3</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MFILT</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x910</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>IPv6 Neighbour Advertisement</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>IPv6 Router Advertisement</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>DHCPv6 Relay and Server Multicast</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>2</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_SETTING_1</ipxact:name> + <ipxact:description>This is the "Link Settings" value from NCSI Set Link.</ipxact:description> + <ipxact:addressOffset>0x914</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>Autonegotiation enabled</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Link Speed 10M enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Link Speed 100M enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>2</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Link Speed 100M enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>2</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Link Speed 1000M enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>3</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Link Speed 10G enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>4</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Half duplex enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>8</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Full duplex enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>9</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Pause capability enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>10</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Asymmetric pause capability enable</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>11</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>OEM link settings field valid</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>12</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_SETTING_2</ipxact:name> + <ipxact:description>This is the "OEM Settings" value from NCSI Set Link.</ipxact:description> + <ipxact:addressOffset>0x918</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_VLAN</ipxact:name> + <ipxact:description>Receives VLAN mode from NCSI specification "Enable VLAN" command.</ipxact:description> + <ipxact:addressOffset>0x91c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_ALT_HOST_MAC_HIGH</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x924</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_ALT_HOST_MAC_MID</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x928</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_ALT_HOST_MAC_LOW</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x92c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC0_HIGH</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x934</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC0_MID</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x938</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC0_LOW</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x93c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC1_HIGH</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x944</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC1_MID</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x948</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC1_LOW</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x94c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC2_HIGH</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x954</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC2_MID</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x958</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC2_LOW</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x95c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC3_HIGH</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x964</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC3_MID</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x968</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC3_LOW</ipxact:name> + <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description> + <ipxact:addressOffset>0x96c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC0_VLAN_VALID</ipxact:name> + <ipxact:description>Nonzero indicates VLAN field is valid</ipxact:description> + <ipxact:addressOffset>0x970</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC0_VLAN</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x974</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC1_VLAN_VALID</ipxact:name> + <ipxact:description>Nonzero indicates VLAN field is valid</ipxact:description> + <ipxact:addressOffset>0x978</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_MAC1_VLAN</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x97c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_STATUS</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x980</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + <ipxact:field> + <ipxact:name>Link up</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>0</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Link Status</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:bitOffset>1</ipxact:bitOffset> + <ipxact:bitWidth>4</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>SERDES</ipxact:name> + <ipxact:description>Set from MII_REG_CONTROL__AUTO_NEGOTIATION_ENABLE. Set unconditionally in SERDES case.</ipxact:description> + <ipxact:bitOffset>5</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Autonegotiation Complete</ipxact:name> + <ipxact:description>Set if autonegotiation is complete.</ipxact:description> + <ipxact:bitOffset>6</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Link Speed 1000M Full Duplex Capable</ipxact:name> + <ipxact:description>Link partner 1000BASE-T full duplex capable</ipxact:description> + <ipxact:bitOffset>9</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + <ipxact:field> + <ipxact:name>Link Speed 1000M Hals Duplex Capable</ipxact:name> + <ipxact:description>Link partner 1000BASE-T half duplex capable</ipxact:description> + <ipxact:bitOffset>10</ipxact:bitOffset> + <ipxact:bitWidth>1</ipxact:bitWidth> + <ipxact:access>read-write</ipxact:access> + </ipxact:field> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_RESET_COUNT</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x984</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_PXE</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x988</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_DROPFIL</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x98c</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_SLINK</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x990</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_DBG</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x9a0</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + <ipxact:register> + <ipxact:name>NCSI_CHANNEL0_CTRLSTAT_RX</ipxact:name> + <ipxact:description></ipxact:description> + <ipxact:addressOffset>0x9b0</ipxact:addressOffset> + <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> + <ipxact:size>32</ipxact:size> + <ipxact:volatile>true</ipxact:volatile> + </ipxact:register> + </ipxact:addressBlock> + <ipxact:addressUnitBits>8</ipxact:addressUnitBits> + </ipxact:memoryMap> + </ipxact:memoryMaps> +</ipxact:component> diff --git a/ipxact/bcm5719.xml b/ipxact/bcm5719.xml index 4690ecc..a4620b0 100644 --- a/ipxact/bcm5719.xml +++ b/ipxact/bcm5719.xml @@ -1371,1059 +1371,6 @@ </ipxact:field> </ipxact:register> <ipxact:register> - <ipxact:name>SEG_SIG</ipxact:name> - <ipxact:description>APE_APE_MAGIC ('APE!') when all is well.</ipxact:description> - <ipxact:addressOffset>0x4000</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>FW_STATUS</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x400c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Ready</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>unknown_31_28</ipxact:name> - <ipxact:description>If this is all-ones, it appears to mean the APE FW is halted.</ipxact:description> - <ipxact:bitOffset>28</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>FW_FEATURES</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4010</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>NCSI</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>4014</ipxact:name> - <ipxact:description>Unknown.</ipxact:description> - <ipxact:addressOffset>0x4014</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>FW_VERSION</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4018</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Build</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Revision</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Minor</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Major</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>SEG_MESSAGE_BUFFER_OFFSET</ipxact:name> - <ipxact:description>Specifies the offset of a scratchpad area, relative to the start of the APE SHM area (i.e., relative to APE_REG(0x4000)).</ipxact:description> - <ipxact:addressOffset>0x401c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>SEG_MESSAGE_BUFFER_LENGTH</ipxact:name> - <ipxact:description>Specifies the size of the scratchpad area in bytes.</ipxact:description> - <ipxact:addressOffset>0x4020</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>4024</ipxact:name> - <ipxact:description>Unknown. Bootcode related.</ipxact:description> - <ipxact:addressOffset>0x4024</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>4028</ipxact:name> - <ipxact:description>Unknown. Bootcode related.</ipxact:description> - <ipxact:addressOffset>0x4028</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_SEG_SIG</ipxact:name> - <ipxact:description>Set to APE_RCPU_MAGIC ('RCPU') by RX CPU.</ipxact:description> - <ipxact:addressOffset>0x4100</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Sig</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>32</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>RCPU_MAGIC</ipxact:name> - <ipxact:value>0x52435055</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_SEG_LENGTH</ipxact:name> - <ipxact:description>Set to 0x34.</ipxact:description> - <ipxact:addressOffset>0x4104</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_INIT_COUNT</ipxact:name> - <ipxact:description>Incremented by RX CPU every boot.</ipxact:description> - <ipxact:addressOffset>0x4108</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_FW_VERSION</ipxact:name> - <ipxact:description>Set to the bootcode version. e.g. 0x0127 -> v1.39.</ipxact:description> - <ipxact:addressOffset>0x410c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_CFG_FEATURE</ipxact:name> - <ipxact:description>Set to </ipxact:description> - <ipxact:addressOffset>0x4110</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_PCI_VENDOR_DEVICE_ID</ipxact:name> - <ipxact:description>Set to PCI Vendor/Device ID by S2.</ipxact:description> - <ipxact:addressOffset>0x4114</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_PCI_SUBSYSTEM_ID</ipxact:name> - <ipxact:description>Set to PCI Subsystem Vendor/Subsystem ID by S2.</ipxact:description> - <ipxact:addressOffset>0x4118</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_APE_RESET_COUNT</ipxact:name> - <ipxact:description>Unknown. Incremented by frobnicating routine.</ipxact:description> - <ipxact:addressOffset>0x411c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_LAST_APE_STATUS</ipxact:name> - <ipxact:description>Unknown. Written by frobnicating routine.</ipxact:description> - <ipxact:addressOffset>0x4120</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_LAST_APE_FW_STATUS</ipxact:name> - <ipxact:description>Unknown. </ipxact:description> - <ipxact:addressOffset>0x4124</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_CFG_HW</ipxact:name> - <ipxact:description>Set from </ipxact:description> - <ipxact:addressOffset>0x4128</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_CFG_HW_2</ipxact:name> - <ipxact:description>Set from </ipxact:description> - <ipxact:addressOffset>0x412c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>RCPU_CPMU_STATUS</ipxact:name> - <ipxact:description>Set from </ipxact:description> - <ipxact:addressOffset>0x4130</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Address</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>16</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>ADDRESS</ipxact:name> - <ipxact:value>0x362C</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> - <ipxact:field> - <ipxact:name>Status</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>16</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>HOST_SEG_SIG</ipxact:name> - <ipxact:description>Set to APE_HOST_MAGIC ('HOST') to indicate the section is valid.</ipxact:description> - <ipxact:addressOffset>0x4200</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>HOST_SEG_LEN</ipxact:name> - <ipxact:description>Set to 0x20.</ipxact:description> - <ipxact:addressOffset>0x4204</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>HOST_INIT_COUNT</ipxact:name> - <ipxact:description>Incremented by host on every initialization.</ipxact:description> - <ipxact:addressOffset>0x4208</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>HOST_DRIVER_ID</ipxact:name> - <ipxact:description>Linux sets this to 0xF0MM_mm00, where M is the major version of Linux and m is the minor version.</ipxact:description> - <ipxact:addressOffset>0x420c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>HOST_BEHAVIOR</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4210</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>No PHYLock</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>HEARTBEAT_INTERVAL</ipxact:name> - <ipxact:description>In milliseconds. Set to 0 to disable heartbeating.</ipxact:description> - <ipxact:addressOffset>0x4214</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>HEARTBEAT_COUNT</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4218</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>HOST_DRIVER_STATE</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x421c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>WOL_SPEED</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4224</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>EVENT_STATUS</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4300</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Driver Event</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Command</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>8</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>State Change</ipxact:name> - <ipxact:value>5</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Scratchpad Read</ipxact:name> - <ipxact:value>22</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Scratchpad Write</ipxact:name> - <ipxact:value>23</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> - <ipxact:field> - <ipxact:name>State</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>16</ipxact:bitOffset> - <ipxact:bitWidth>3</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>Start</ipxact:name> - <ipxact:value>1</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Unload</ipxact:name> - <ipxact:value>2</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>WOL</ipxact:name> - <ipxact:value>3</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Suspend</ipxact:name> - <ipxact:value>4</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> - <ipxact:field> - <ipxact:name>Pending</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>31</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>PROT_MAGIC</ipxact:name> - <ipxact:description>This is set to APE_PROT_MAGIC ('PROT') on all functions. If it is 'PROT', the following fields (MAC0_HIGH/LOW) are valid</ipxact:description> - <ipxact:addressOffset>0x4308</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>PROT_MAC0_HIGH</ipxact:name> - <ipxact:description>High 16 bits of MAC address 0. Only valid if </ipxact:description> - <ipxact:addressOffset>0x4314</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>PROT_MAC0_LOW</ipxact:name> - <ipxact:description>Low 16 bits of MAC address 0.</ipxact:description> - <ipxact:addressOffset>0x4318</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_SIG</ipxact:name> - <ipxact:description>Set to NCSI_MAGIC ('NCSI') by APE firmware. NOTE: all words in the NCSI section are available in the function 0 SHM area only.</ipxact:description> - <ipxact:addressOffset>0x4800</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_BUILD_TIME</ipxact:name> - <ipxact:description>ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero.</ipxact:description> - <ipxact:addressOffset>0x4810</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_BUILD_TIME_2</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4814</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_BUILD_TIME_3</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4818</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_BUILD_DATE</ipxact:name> - <ipxact:description>ASCII string spanning three 32-bit words. Unused trailing bytes are set to zero.</ipxact:description> - <ipxact:addressOffset>0x481c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_BUILD_DATE_2</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4820</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_BUILD_DATE_3</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4824</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>CHIP_ID</ipxact:name> - <ipxact:description>The APE code copies the contents of Chip ID to this word</ipxact:description> - <ipxact:addressOffset>0x4890</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_INFO</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4900</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Enabled</ipxact:name> - <ipxact:description>This can be modified via NCSI SELECT PACKAGE and NCSI DESELECT PACKAGE.</ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>TX Passthrough</ipxact:name> - <ipxact:description>TX passthrough has been enabled by BMC NCSI command.</ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Ready</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Init</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>3</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>MFILT</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>BFILT</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>5</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>SERDES</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>6</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>VLAN</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>B2H</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>10</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>B2N</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>11</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>EEE</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Driver</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>14</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>PDead</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>15</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MCID</ipxact:name> - <ipxact:description>AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs.</ipxact:description> - <ipxact:addressOffset>0x4904</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_AEN</ipxact:name> - <ipxact:description>Set via NCSI ENABLE AEN.</ipxact:description> - <ipxact:addressOffset>0x4908</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Enable Link Status Change AEN</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Enable Configuration Required AEN</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Enable Host NC Driver Status Change AEN</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_BFILT</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x490c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>ARP Packet</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>DHCP Client Packet</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>DHCP Server Packet</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>NetBIOS Packet</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>3</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MFILT</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4910</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>IPv6 Neighbour Advertisement</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>IPv6 Router Advertisement</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>DHCPv6 Relay and Server Multicast</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_SETTING_1</ipxact:name> - <ipxact:description>This is the "Link Settings" value from NCSI Set Link.</ipxact:description> - <ipxact:addressOffset>0x4914</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Autonegotiation enabled</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Link Speed 10M enable</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Link Speed 100M enable</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Link Speed 100M enable</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Link Speed 1000M enable</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>3</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Link Speed 10G enable</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Half duplex enable</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Full duplex enable</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>9</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Pause capability enable</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>10</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Asymmetric pause capability enable</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>11</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>OEM link settings field valid</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_SETTING_2</ipxact:name> - <ipxact:description>This is the "OEM Settings" value from NCSI Set Link.</ipxact:description> - <ipxact:addressOffset>0x4918</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_VLAN</ipxact:name> - <ipxact:description>Receives VLAN mode from NCSI specification "Enable VLAN" command.</ipxact:description> - <ipxact:addressOffset>0x491c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_ALT_HOST_MAC_HIGH</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x4924</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_ALT_HOST_MAC_MID</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x4928</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_ALT_HOST_MAC_LOW</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x492c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC0_HIGH</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x4934</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC0_MID</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x4938</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC0_LOW</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x493c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC1_HIGH</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x4944</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC1_MID</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x4948</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC1_LOW</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x494c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC2_HIGH</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x4954</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC2_MID</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x4958</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC2_LOW</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x495c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC3_HIGH</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains upper 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x4964</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC3_MID</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains mid 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x4968</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC3_LOW</ipxact:name> - <ipxact:description>Lower 16 bits of this word contains low 16 bits of the MAC.</ipxact:description> - <ipxact:addressOffset>0x496c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC0_VLAN_VALID</ipxact:name> - <ipxact:description>Nonzero indicates VLAN field is valid</ipxact:description> - <ipxact:addressOffset>0x4970</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC0_VLAN</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4974</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC1_VLAN_VALID</ipxact:name> - <ipxact:description>Nonzero indicates VLAN field is valid</ipxact:description> - <ipxact:addressOffset>0x4978</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_MAC1_VLAN</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x497c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_STATUS</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4980</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Link up</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Link Status</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>SERDES</ipxact:name> - <ipxact:description>Set from MII_REG_CONTROL__AUTO_NEGOTIATION_ENABLE. Set unconditionally in SERDES case.</ipxact:description> - <ipxact:bitOffset>5</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Autonegotiation Complete</ipxact:name> - <ipxact:description>Set if autonegotiation is complete.</ipxact:description> - <ipxact:bitOffset>6</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Link Speed 1000M Full Duplex Capable</ipxact:name> - <ipxact:description>Link partner 1000BASE-T full duplex capable</ipxact:description> - <ipxact:bitOffset>9</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Link Speed 1000M Hals Duplex Capable</ipxact:name> - <ipxact:description>Link partner 1000BASE-T half duplex capable</ipxact:description> - <ipxact:bitOffset>10</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_RESET_COUNT</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4984</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_PXE</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4988</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_DROPFIL</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x498c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_SLINK</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x4990</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_DBG</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x49a0</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - <ipxact:register> - <ipxact:name>NCSI_CHANNEL0_CTRLSTAT_RX</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:addressOffset>0x49b0</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - </ipxact:register> - - - - <ipxact:register> <ipxact:name>PER_LOCK_REQUEST_PHY0</ipxact:name> <ipxact:description>This register, and the following Per Lock Request registers work the same. The tg3 driver uses 0x0000_1000 (APELOCK_PER_REQ_DRIVER) for PHY ports (or always for function 0).</ipxact:description> <ipxact:addressOffset>0x8400</ipxact:addressOffset> @@ -3227,6 +2174,22 @@ <ipxact:addressUnitBits>8</ipxact:addressUnitBits> </ipxact:memoryMap> + <!-- APE Registers: 0xC001_4000 to C001_5FFF--> + <ipxact:memoryMap> + <ipxact:name>SHM</ipxact:name> + <ipxact:description>Device SHM Registers</ipxact:description> + <ipxact:addressBlock> + <ipxact:name>SHM</ipxact:name> + <ipxact:description>Device SHM Registers</ipxact:description> + <ipxact:baseAddress>0xC0014000</ipxact:baseAddress> + <!-- LINK: addressBlockDefinitionGroup: see 6.9.3, Address blockdefinition group --> + <!-- LINK: memoryBlockData: see 6.9.4, memoryBlockData group --> + <ipxact:usage>register</ipxact:usage> + <ipxact:volatile>false</ipxact:volatile> + </ipxact:addressBlock> + <ipxact:addressUnitBits>8</ipxact:addressUnitBits> + </ipxact:memoryMap> + <!-- Device NVM Registers: 0xC000_7000 to C000_7080 --> <ipxact:memoryMap> <ipxact:name>NVM</ipxact:name> diff --git a/ipxact/regen.sh b/ipxact/regen.sh index 6253fcb..8de1139 100755 --- a/ipxact/regen.sh +++ b/ipxact/regen.sh @@ -5,7 +5,7 @@ PROJECT=bcm5719 echo "Regenerating Bcm5719 header" -${IPXACT} -p ${PROJECT} DEVICE.xml NVM.xml bcm5719.xml bcm5719_full.xml +${IPXACT} -p ${PROJECT} SHM.xml DEVICE.xml NVM.xml bcm5719.xml bcm5719_full.xml ${IPXACT} -p ${PROJECT} bcm5719_full.xml bcm5719.h @@ -14,6 +14,7 @@ mv bcm5719_MII.h ../libs/MII/include/ mv bcm5719_DEVICE.h ../include/ mv bcm5719_GEN.h ../include/ mv bcm5719_APE.h ../include/ +mv bcm5719_SHM.h ../include/ mv bcm5719_RXMBUF.h ../include mv bcm5719_SDBCACHE.h ../include mv bcm5719_TXMBUF.h ../include @@ -39,5 +40,5 @@ ${IPXACT} -p ${PROJECT} NVIC.xml APE_full.xml APE.h mv APE_NVIC.h ../include/ # ${IPXACT} -p ${PROJECT} NVIC.xml APE_full.xml APE.s -${IPXACT} -p ${PROJECT} NVIC.xml APE_full.xml -t asym APE_sym.s +${IPXACT} -p ${PROJECT} SHM.xml NVIC.xml APE_full.xml -t asym APE_sym.s mv *.s ../libs/bcm5719/ diff --git a/libs/bcm5719/APE_sym.s b/libs/bcm5719/APE_sym.s index df23eb1..ca1184e 100644 --- a/libs/bcm5719/APE_sym.s +++ b/libs/bcm5719/APE_sym.s @@ -68,4 +68,20 @@ .equ NVM, 0x60240000 .size NVM, 0x3c +.global SHM +.equ SHM, 0x60220000 +.size SHM, 0x9b4 + +.global SHM1 +.equ SHM1, 0x60221000 +.size SHM1, 0x0 + +.global SHM2 +.equ SHM2, 0x60222000 +.size SHM2, 0x0 + +.global SHM3 +.equ SHM3, 0x60223000 +.size SHM3, 0x0 + diff --git a/libs/bcm5719/bcm5719_sym.s b/libs/bcm5719/bcm5719_sym.s index 7b9561a..b08df7e 100644 --- a/libs/bcm5719/bcm5719_sym.s +++ b/libs/bcm5719/bcm5719_sym.s @@ -76,6 +76,10 @@ .equ SDBCACHE, 0x20000 .size SDBCACHE, 0xc800 +.global SHM +.equ SHM, 0xc0014000 +.size SHM, 0x9b4 + .global TXMBUF .equ TXMBUF, 0x2c800 .size TXMBUF, 0x7400 diff --git a/simulator/CMakeLists.txt b/simulator/CMakeLists.txt index 47513b6..c6df00f 100644 --- a/simulator/CMakeLists.txt +++ b/simulator/CMakeLists.txt @@ -3,15 +3,17 @@ project(simulator) simulator_add_library(${PROJECT_NAME} STATIC HAL.cpp - bcm5719_DEVICE_mmap.cpp bcm5719_DEVICE.cpp bcm5719_GEN_mmap.cpp bcm5719_GEN.cpp bcm5719_NVM_mmap.cpp bcm5719_NVM.cpp + # APE Speciifc registers bcm5719_APE.cpp bcm5719_APE_mmap.cpp + bcm5719_SHM.cpp + bcm5719_SHM_mmap.cpp ) include_directories(../libs/NVRam) diff --git a/simulator/HAL.cpp b/simulator/HAL.cpp index 716650e..73f421a 100644 --- a/simulator/HAL.cpp +++ b/simulator/HAL.cpp @@ -3,6 +3,7 @@ #include <bcm5719_DEVICE.h> #include <bcm5719_APE.h> +#include <bcm5719_SHM.h> #include <bcm5719_GEN.h> #include <dirent.h> #include <endian.h> @@ -248,10 +249,14 @@ bool initHAL(const char *pci_path, int wanted_function) init_bcm5719_GEN(); init_bcm5719_GEN_mmap(&DEVICEBase[0x8000 + 0xB50]); // 0x8000 for windowed area - init_bcm5719_APE(); - init_bcm5719_APE_mmap(APEBase); init_bcm5719_NVM(); init_bcm5719_NVM_mmap(&DEVICEBase[0x7000]); + init_bcm5719_APE(); + init_bcm5719_APE_mmap(APEBase); + + init_bcm5719_SHM(); + init_bcm5719_SHM_mmap(&DAPEBase[0x4000]); + return true; } diff --git a/simulator/bcm5719_APE.cpp b/simulator/bcm5719_APE.cpp index f1533cb..5f7b0f0 100644 --- a/simulator/bcm5719_APE.cpp +++ b/simulator/bcm5719_APE.cpp @@ -83,160 +83,6 @@ void init_bcm5719_APE(void) /** @brief Bitmap for @ref APE_t.Cm3. */ - /** @brief Bitmap for @ref APE_t.SegSig. */ - - /** @brief Bitmap for @ref APE_t.FwStatus. */ - - /** @brief Bitmap for @ref APE_t.FwFeatures. */ - - /** @brief Bitmap for @ref APE_t.4014. */ - - /** @brief Bitmap for @ref APE_t.FwVersion. */ - - /** @brief Bitmap for @ref APE_t.SegMessageBufferOffset. */ - - /** @brief Bitmap for @ref APE_t.SegMessageBufferLength. */ - - /** @brief Bitmap for @ref APE_t.4024. */ - - /** @brief Bitmap for @ref APE_t.4028. */ - - /** @brief Bitmap for @ref APE_t.RcpuSegSig. */ - - /** @brief Bitmap for @ref APE_t.RcpuSegLength. */ - - /** @brief Bitmap for @ref APE_t.RcpuInitCount. */ - - /** @brief Bitmap for @ref APE_t.RcpuFwVersion. */ - - /** @brief Bitmap for @ref APE_t.RcpuCfgFeature. */ - - /** @brief Bitmap for @ref APE_t.RcpuPciVendorDeviceId. */ - - /** @brief Bitmap for @ref APE_t.RcpuPciSubsystemId. */ - - /** @brief Bitmap for @ref APE_t.RcpuApeResetCount. */ - - /** @brief Bitmap for @ref APE_t.RcpuLastApeStatus. */ - - /** @brief Bitmap for @ref APE_t.RcpuLastApeFwStatus. */ - - /** @brief Bitmap for @ref APE_t.RcpuCfgHw. */ - - /** @brief Bitmap for @ref APE_t.RcpuCfgHw2. */ - - /** @brief Bitmap for @ref APE_t.RcpuCpmuStatus. */ - - /** @brief Bitmap for @ref APE_t.HostSegSig. */ - - /** @brief Bitmap for @ref APE_t.HostSegLen. */ - - /** @brief Bitmap for @ref APE_t.HostInitCount. */ - - /** @brief Bitmap for @ref APE_t.HostDriverId. */ - - /** @brief Bitmap for @ref APE_t.HostBehavior. */ - - /** @brief Bitmap for @ref APE_t.HeartbeatInterval. */ - - /** @brief Bitmap for @ref APE_t.HeartbeatCount. */ - - /** @brief Bitmap for @ref APE_t.HostDriverState. */ - - /** @brief Bitmap for @ref APE_t.WolSpeed. */ - - /** @brief Bitmap for @ref APE_t.EventStatus. */ - - /** @brief Bitmap for @ref APE_t.ProtMagic. */ - - /** @brief Bitmap for @ref APE_t.ProtMac0High. */ - - /** @brief Bitmap for @ref APE_t.ProtMac0Low. */ - - /** @brief Bitmap for @ref APE_t.NcsiSig. */ - - /** @brief Bitmap for @ref APE_t.NcsiBuildTime. */ - - /** @brief Bitmap for @ref APE_t.NcsiBuildTime2. */ - - /** @brief Bitmap for @ref APE_t.NcsiBuildTime3. */ - - /** @brief Bitmap for @ref APE_t.NcsiBuildDate. */ - - /** @brief Bitmap for @ref APE_t.NcsiBuildDate2. */ - - /** @brief Bitmap for @ref APE_t.NcsiBuildDate3. */ - - /** @brief Bitmap for @ref APE_t.ChipId. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Info. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mcid. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Aen. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Bfilt. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mfilt. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Setting1. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Setting2. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Vlan. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0AltHostMacHigh. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0AltHostMacMid. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0AltHostMacLow. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0High. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0Mid. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0Low. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1High. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1Mid. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1Low. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac2High. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac2Mid. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac2Low. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac3High. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac3Mid. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac3Low. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0VlanValid. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0Vlan. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1VlanValid. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1Vlan. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Status. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0ResetCount. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Pxe. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Dropfil. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Slink. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Dbg. */ - - /** @brief Bitmap for @ref APE_t.NcsiChannel0CtrlstatRx. */ - /** @brief Bitmap for @ref APE_t.PerLockRequestPhy0. */ /** @brief Bitmap for @ref APE_t.PerLockRequestGrc. */ diff --git a/simulator/bcm5719_APE_mmap.cpp b/simulator/bcm5719_APE_mmap.cpp index 60aad9e..6b035a5 100644 --- a/simulator/bcm5719_APE_mmap.cpp +++ b/simulator/bcm5719_APE_mmap.cpp @@ -166,391 +166,6 @@ void init_bcm5719_APE_mmap(void *base) APE.Cm3.r32.installReadCallback(read_from_ram, &APE_Cm3_r32); APE.Cm3.r32.installWriteCallback(write_to_ram, &APE_Cm3_r32); - /** @brief Bitmap for @ref APE_t.SegSig. */ - static ram_offset_t APE_SegSig_r32((uint8_t *)base, (uint32_t)16384); - APE.SegSig.r32.installReadCallback(read_from_ram, &APE_SegSig_r32); - APE.SegSig.r32.installWriteCallback(write_to_ram, &APE_SegSig_r32); - - /** @brief Bitmap for @ref APE_t.FwStatus. */ - static ram_offset_t APE_FwStatus_r32((uint8_t *)base, (uint32_t)16396); - APE.FwStatus.r32.installReadCallback(read_from_ram, &APE_FwStatus_r32); - APE.FwStatus.r32.installWriteCallback(write_to_ram, &APE_FwStatus_r32); - - /** @brief Bitmap for @ref APE_t.FwFeatures. */ - static ram_offset_t APE_FwFeatures_r32((uint8_t *)base, (uint32_t)16400); - APE.FwFeatures.r32.installReadCallback(read_from_ram, &APE_FwFeatures_r32); - APE.FwFeatures.r32.installWriteCallback(write_to_ram, &APE_FwFeatures_r32); - - /** @brief Bitmap for @ref APE_t.4014. */ - static ram_offset_t APE__4014_r32((uint8_t *)base, (uint32_t)16404); - APE._4014.r32.installReadCallback(read_from_ram, &APE__4014_r32); - APE._4014.r32.installWriteCallback(write_to_ram, &APE__4014_r32); - - /** @brief Bitmap for @ref APE_t.FwVersion. */ - static ram_offset_t APE_FwVersion_r32((uint8_t *)base, (uint32_t)16408); - APE.FwVersion.r32.installReadCallback(read_from_ram, &APE_FwVersion_r32); - APE.FwVersion.r32.installWriteCallback(write_to_ram, &APE_FwVersion_r32); - - /** @brief Bitmap for @ref APE_t.SegMessageBufferOffset. */ - static ram_offset_t APE_SegMessageBufferOffset_r32((uint8_t *)base, (uint32_t)16412); - APE.SegMessageBufferOffset.r32.installReadCallback(read_from_ram, &APE_SegMessageBufferOffset_r32); - APE.SegMessageBufferOffset.r32.installWriteCallback(write_to_ram, &APE_SegMessageBufferOffset_r32); - - /** @brief Bitmap for @ref APE_t.SegMessageBufferLength. */ - static ram_offset_t APE_SegMessageBufferLength_r32((uint8_t *)base, (uint32_t)16416); - APE.SegMessageBufferLength.r32.installReadCallback(read_from_ram, &APE_SegMessageBufferLength_r32); - APE.SegMessageBufferLength.r32.installWriteCallback(write_to_ram, &APE_SegMessageBufferLength_r32); - - /** @brief Bitmap for @ref APE_t.4024. */ - static ram_offset_t APE__4024_r32((uint8_t *)base, (uint32_t)16420); - APE._4024.r32.installReadCallback(read_from_ram, &APE__4024_r32); - APE._4024.r32.installWriteCallback(write_to_ram, &APE__4024_r32); - - /** @brief Bitmap for @ref APE_t.4028. */ - static ram_offset_t APE__4028_r32((uint8_t *)base, (uint32_t)16424); - APE._4028.r32.installReadCallback(read_from_ram, &APE__4028_r32); - APE._4028.r32.installWriteCallback(write_to_ram, &APE__4028_r32); - - /** @brief Bitmap for @ref APE_t.RcpuSegSig. */ - static ram_offset_t APE_RcpuSegSig_r32((uint8_t *)base, (uint32_t)16640); - APE.RcpuSegSig.r32.installReadCallback(read_from_ram, &APE_RcpuSegSig_r32); - APE.RcpuSegSig.r32.installWriteCallback(write_to_ram, &APE_RcpuSegSig_r32); - - /** @brief Bitmap for @ref APE_t.RcpuSegLength. */ - static ram_offset_t APE_RcpuSegLength_r32((uint8_t *)base, (uint32_t)16644); - APE.RcpuSegLength.r32.installReadCallback(read_from_ram, &APE_RcpuSegLength_r32); - APE.RcpuSegLength.r32.installWriteCallback(write_to_ram, &APE_RcpuSegLength_r32); - - /** @brief Bitmap for @ref APE_t.RcpuInitCount. */ - static ram_offset_t APE_RcpuInitCount_r32((uint8_t *)base, (uint32_t)16648); - APE.RcpuInitCount.r32.installReadCallback(read_from_ram, &APE_RcpuInitCount_r32); - APE.RcpuInitCount.r32.installWriteCallback(write_to_ram, &APE_RcpuInitCount_r32); - - /** @brief Bitmap for @ref APE_t.RcpuFwVersion. */ - static ram_offset_t APE_RcpuFwVersion_r32((uint8_t *)base, (uint32_t)16652); - APE.RcpuFwVersion.r32.installReadCallback(read_from_ram, &APE_RcpuFwVersion_r32); - APE.RcpuFwVersion.r32.installWriteCallback(write_to_ram, &APE_RcpuFwVersion_r32); - - /** @brief Bitmap for @ref APE_t.RcpuCfgFeature. */ - static ram_offset_t APE_RcpuCfgFeature_r32((uint8_t *)base, (uint32_t)16656); - APE.RcpuCfgFeature.r32.installReadCallback(read_from_ram, &APE_RcpuCfgFeature_r32); - APE.RcpuCfgFeature.r32.installWriteCallback(write_to_ram, &APE_RcpuCfgFeature_r32); - - /** @brief Bitmap for @ref APE_t.RcpuPciVendorDeviceId. */ - static ram_offset_t APE_RcpuPciVendorDeviceId_r32((uint8_t *)base, (uint32_t)16660); - APE.RcpuPciVendorDeviceId.r32.installReadCallback(read_from_ram, &APE_RcpuPciVendorDeviceId_r32); - APE.RcpuPciVendorDeviceId.r32.installWriteCallback(write_to_ram, &APE_RcpuPciVendorDeviceId_r32); - - /** @brief Bitmap for @ref APE_t.RcpuPciSubsystemId. */ - static ram_offset_t APE_RcpuPciSubsystemId_r32((uint8_t *)base, (uint32_t)16664); - APE.RcpuPciSubsystemId.r32.installReadCallback(read_from_ram, &APE_RcpuPciSubsystemId_r32); - APE.RcpuPciSubsystemId.r32.installWriteCallback(write_to_ram, &APE_RcpuPciSubsystemId_r32); - - /** @brief Bitmap for @ref APE_t.RcpuApeResetCount. */ - static ram_offset_t APE_RcpuApeResetCount_r32((uint8_t *)base, (uint32_t)16668); - APE.RcpuApeResetCount.r32.installReadCallback(read_from_ram, &APE_RcpuApeResetCount_r32); - APE.RcpuApeResetCount.r32.installWriteCallback(write_to_ram, &APE_RcpuApeResetCount_r32); - - /** @brief Bitmap for @ref APE_t.RcpuLastApeStatus. */ - static ram_offset_t APE_RcpuLastApeStatus_r32((uint8_t *)base, (uint32_t)16672); - APE.RcpuLastApeStatus.r32.installReadCallback(read_from_ram, &APE_RcpuLastApeStatus_r32); - APE.RcpuLastApeStatus.r32.installWriteCallback(write_to_ram, &APE_RcpuLastApeStatus_r32); - - /** @brief Bitmap for @ref APE_t.RcpuLastApeFwStatus. */ - static ram_offset_t APE_RcpuLastApeFwStatus_r32((uint8_t *)base, (uint32_t)16676); - APE.RcpuLastApeFwStatus.r32.installReadCallback(read_from_ram, &APE_RcpuLastApeFwStatus_r32); - APE.RcpuLastApeFwStatus.r32.installWriteCallback(write_to_ram, &APE_RcpuLastApeFwStatus_r32); - - /** @brief Bitmap for @ref APE_t.RcpuCfgHw. */ - static ram_offset_t APE_RcpuCfgHw_r32((uint8_t *)base, (uint32_t)16680); - APE.RcpuCfgHw.r32.installReadCallback(read_from_ram, &APE_RcpuCfgHw_r32); - APE.RcpuCfgHw.r32.installWriteCallback(write_to_ram, &APE_RcpuCfgHw_r32); - - /** @brief Bitmap for @ref APE_t.RcpuCfgHw2. */ - static ram_offset_t APE_RcpuCfgHw2_r32((uint8_t *)base, (uint32_t)16684); - APE.RcpuCfgHw2.r32.installReadCallback(read_from_ram, &APE_RcpuCfgHw2_r32); - APE.RcpuCfgHw2.r32.installWriteCallback(write_to_ram, &APE_RcpuCfgHw2_r32); - - /** @brief Bitmap for @ref APE_t.RcpuCpmuStatus. */ - static ram_offset_t APE_RcpuCpmuStatus_r32((uint8_t *)base, (uint32_t)16688); - APE.RcpuCpmuStatus.r32.installReadCallback(read_from_ram, &APE_RcpuCpmuStatus_r32); - APE.RcpuCpmuStatus.r32.installWriteCallback(write_to_ram, &APE_RcpuCpmuStatus_r32); - - /** @brief Bitmap for @ref APE_t.HostSegSig. */ - static ram_offset_t APE_HostSegSig_r32((uint8_t *)base, (uint32_t)16896); - APE.HostSegSig.r32.installReadCallback(read_from_ram, &APE_HostSegSig_r32); - APE.HostSegSig.r32.installWriteCallback(write_to_ram, &APE_HostSegSig_r32); - - /** @brief Bitmap for @ref APE_t.HostSegLen. */ - static ram_offset_t APE_HostSegLen_r32((uint8_t *)base, (uint32_t)16900); - APE.HostSegLen.r32.installReadCallback(read_from_ram, &APE_HostSegLen_r32); - APE.HostSegLen.r32.installWriteCallback(write_to_ram, &APE_HostSegLen_r32); - - /** @brief Bitmap for @ref APE_t.HostInitCount. */ - static ram_offset_t APE_HostInitCount_r32((uint8_t *)base, (uint32_t)16904); - APE.HostInitCount.r32.installReadCallback(read_from_ram, &APE_HostInitCount_r32); - APE.HostInitCount.r32.installWriteCallback(write_to_ram, &APE_HostInitCount_r32); - - /** @brief Bitmap for @ref APE_t.HostDriverId. */ - static ram_offset_t APE_HostDriverId_r32((uint8_t *)base, (uint32_t)16908); - APE.HostDriverId.r32.installReadCallback(read_from_ram, &APE_HostDriverId_r32); - APE.HostDriverId.r32.installWriteCallback(write_to_ram, &APE_HostDriverId_r32); - - /** @brief Bitmap for @ref APE_t.HostBehavior. */ - static ram_offset_t APE_HostBehavior_r32((uint8_t *)base, (uint32_t)16912); - APE.HostBehavior.r32.installReadCallback(read_from_ram, &APE_HostBehavior_r32); - APE.HostBehavior.r32.installWriteCallback(write_to_ram, &APE_HostBehavior_r32); - - /** @brief Bitmap for @ref APE_t.HeartbeatInterval. */ - static ram_offset_t APE_HeartbeatInterval_r32((uint8_t *)base, (uint32_t)16916); - APE.HeartbeatInterval.r32.installReadCallback(read_from_ram, &APE_HeartbeatInterval_r32); - APE.HeartbeatInterval.r32.installWriteCallback(write_to_ram, &APE_HeartbeatInterval_r32); - - /** @brief Bitmap for @ref APE_t.HeartbeatCount. */ - static ram_offset_t APE_HeartbeatCount_r32((uint8_t *)base, (uint32_t)16920); - APE.HeartbeatCount.r32.installReadCallback(read_from_ram, &APE_HeartbeatCount_r32); - APE.HeartbeatCount.r32.installWriteCallback(write_to_ram, &APE_HeartbeatCount_r32); - - /** @brief Bitmap for @ref APE_t.HostDriverState. */ - static ram_offset_t APE_HostDriverState_r32((uint8_t *)base, (uint32_t)16924); - APE.HostDriverState.r32.installReadCallback(read_from_ram, &APE_HostDriverState_r32); - APE.HostDriverState.r32.installWriteCallback(write_to_ram, &APE_HostDriverState_r32); - - /** @brief Bitmap for @ref APE_t.WolSpeed. */ - static ram_offset_t APE_WolSpeed_r32((uint8_t *)base, (uint32_t)16932); - APE.WolSpeed.r32.installReadCallback(read_from_ram, &APE_WolSpeed_r32); - APE.WolSpeed.r32.installWriteCallback(write_to_ram, &APE_WolSpeed_r32); - - /** @brief Bitmap for @ref APE_t.EventStatus. */ - static ram_offset_t APE_EventStatus_r32((uint8_t *)base, (uint32_t)17152); - APE.EventStatus.r32.installReadCallback(read_from_ram, &APE_EventStatus_r32); - APE.EventStatus.r32.installWriteCallback(write_to_ram, &APE_EventStatus_r32); - - /** @brief Bitmap for @ref APE_t.ProtMagic. */ - static ram_offset_t APE_ProtMagic_r32((uint8_t *)base, (uint32_t)17160); - APE.ProtMagic.r32.installReadCallback(read_from_ram, &APE_ProtMagic_r32); - APE.ProtMagic.r32.installWriteCallback(write_to_ram, &APE_ProtMagic_r32); - - /** @brief Bitmap for @ref APE_t.ProtMac0High. */ - static ram_offset_t APE_ProtMac0High_r32((uint8_t *)base, (uint32_t)17172); - APE.ProtMac0High.r32.installReadCallback(read_from_ram, &APE_ProtMac0High_r32); - APE.ProtMac0High.r32.installWriteCallback(write_to_ram, &APE_ProtMac0High_r32); - - /** @brief Bitmap for @ref APE_t.ProtMac0Low. */ - static ram_offset_t APE_ProtMac0Low_r32((uint8_t *)base, (uint32_t)17176); - APE.ProtMac0Low.r32.installReadCallback(read_from_ram, &APE_ProtMac0Low_r32); - APE.ProtMac0Low.r32.installWriteCallback(write_to_ram, &APE_ProtMac0Low_r32); - - /** @brief Bitmap for @ref APE_t.NcsiSig. */ - static ram_offset_t APE_NcsiSig_r32((uint8_t *)base, (uint32_t)18432); - APE.NcsiSig.r32.installReadCallback(read_from_ram, &APE_NcsiSig_r32); - APE.NcsiSig.r32.installWriteCallback(write_to_ram, &APE_NcsiSig_r32); - - /** @brief Bitmap for @ref APE_t.NcsiBuildTime. */ - static ram_offset_t APE_NcsiBuildTime_r32((uint8_t *)base, (uint32_t)18448); - APE.NcsiBuildTime.r32.installReadCallback(read_from_ram, &APE_NcsiBuildTime_r32); - APE.NcsiBuildTime.r32.installWriteCallback(write_to_ram, &APE_NcsiBuildTime_r32); - - /** @brief Bitmap for @ref APE_t.NcsiBuildTime2. */ - static ram_offset_t APE_NcsiBuildTime2_r32((uint8_t *)base, (uint32_t)18452); - APE.NcsiBuildTime2.r32.installReadCallback(read_from_ram, &APE_NcsiBuildTime2_r32); - APE.NcsiBuildTime2.r32.installWriteCallback(write_to_ram, &APE_NcsiBuildTime2_r32); - - /** @brief Bitmap for @ref APE_t.NcsiBuildTime3. */ - static ram_offset_t APE_NcsiBuildTime3_r32((uint8_t *)base, (uint32_t)18456); - APE.NcsiBuildTime3.r32.installReadCallback(read_from_ram, &APE_NcsiBuildTime3_r32); - APE.NcsiBuildTime3.r32.installWriteCallback(write_to_ram, &APE_NcsiBuildTime3_r32); - - /** @brief Bitmap for @ref APE_t.NcsiBuildDate. */ - static ram_offset_t APE_NcsiBuildDate_r32((uint8_t *)base, (uint32_t)18460); - APE.NcsiBuildDate.r32.installReadCallback(read_from_ram, &APE_NcsiBuildDate_r32); - APE.NcsiBuildDate.r32.installWriteCallback(write_to_ram, &APE_NcsiBuildDate_r32); - - /** @brief Bitmap for @ref APE_t.NcsiBuildDate2. */ - static ram_offset_t APE_NcsiBuildDate2_r32((uint8_t *)base, (uint32_t)18464); - APE.NcsiBuildDate2.r32.installReadCallback(read_from_ram, &APE_NcsiBuildDate2_r32); - APE.NcsiBuildDate2.r32.installWriteCallback(write_to_ram, &APE_NcsiBuildDate2_r32); - - /** @brief Bitmap for @ref APE_t.NcsiBuildDate3. */ - static ram_offset_t APE_NcsiBuildDate3_r32((uint8_t *)base, (uint32_t)18468); - APE.NcsiBuildDate3.r32.installReadCallback(read_from_ram, &APE_NcsiBuildDate3_r32); - APE.NcsiBuildDate3.r32.installWriteCallback(write_to_ram, &APE_NcsiBuildDate3_r32); - - /** @brief Bitmap for @ref APE_t.ChipId. */ - static ram_offset_t APE_ChipId_r32((uint8_t *)base, (uint32_t)18576); - APE.ChipId.r32.installReadCallback(read_from_ram, &APE_ChipId_r32); - APE.ChipId.r32.installWriteCallback(write_to_ram, &APE_ChipId_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Info. */ - static ram_offset_t APE_NcsiChannel0Info_r32((uint8_t *)base, (uint32_t)18688); - APE.NcsiChannel0Info.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Info_r32); - APE.NcsiChannel0Info.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Info_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mcid. */ - static ram_offset_t APE_NcsiChannel0Mcid_r32((uint8_t *)base, (uint32_t)18692); - APE.NcsiChannel0Mcid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mcid_r32); - APE.NcsiChannel0Mcid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mcid_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Aen. */ - static ram_offset_t APE_NcsiChannel0Aen_r32((uint8_t *)base, (uint32_t)18696); - APE.NcsiChannel0Aen.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Aen_r32); - APE.NcsiChannel0Aen.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Aen_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Bfilt. */ - static ram_offset_t APE_NcsiChannel0Bfilt_r32((uint8_t *)base, (uint32_t)18700); - APE.NcsiChannel0Bfilt.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Bfilt_r32); - APE.NcsiChannel0Bfilt.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Bfilt_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mfilt. */ - static ram_offset_t APE_NcsiChannel0Mfilt_r32((uint8_t *)base, (uint32_t)18704); - APE.NcsiChannel0Mfilt.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mfilt_r32); - APE.NcsiChannel0Mfilt.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mfilt_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Setting1. */ - static ram_offset_t APE_NcsiChannel0Setting1_r32((uint8_t *)base, (uint32_t)18708); - APE.NcsiChannel0Setting1.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Setting1_r32); - APE.NcsiChannel0Setting1.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Setting1_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Setting2. */ - static ram_offset_t APE_NcsiChannel0Setting2_r32((uint8_t *)base, (uint32_t)18712); - APE.NcsiChannel0Setting2.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Setting2_r32); - APE.NcsiChannel0Setting2.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Setting2_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Vlan. */ - static ram_offset_t APE_NcsiChannel0Vlan_r32((uint8_t *)base, (uint32_t)18716); - APE.NcsiChannel0Vlan.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Vlan_r32); - APE.NcsiChannel0Vlan.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Vlan_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0AltHostMacHigh. */ - static ram_offset_t APE_NcsiChannel0AltHostMacHigh_r32((uint8_t *)base, (uint32_t)18724); - APE.NcsiChannel0AltHostMacHigh.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0AltHostMacHigh_r32); - APE.NcsiChannel0AltHostMacHigh.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0AltHostMacHigh_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0AltHostMacMid. */ - static ram_offset_t APE_NcsiChannel0AltHostMacMid_r32((uint8_t *)base, (uint32_t)18728); - APE.NcsiChannel0AltHostMacMid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0AltHostMacMid_r32); - APE.NcsiChannel0AltHostMacMid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0AltHostMacMid_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0AltHostMacLow. */ - static ram_offset_t APE_NcsiChannel0AltHostMacLow_r32((uint8_t *)base, (uint32_t)18732); - APE.NcsiChannel0AltHostMacLow.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0AltHostMacLow_r32); - APE.NcsiChannel0AltHostMacLow.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0AltHostMacLow_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0High. */ - static ram_offset_t APE_NcsiChannel0Mac0High_r32((uint8_t *)base, (uint32_t)18740); - APE.NcsiChannel0Mac0High.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac0High_r32); - APE.NcsiChannel0Mac0High.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac0High_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0Mid. */ - static ram_offset_t APE_NcsiChannel0Mac0Mid_r32((uint8_t *)base, (uint32_t)18744); - APE.NcsiChannel0Mac0Mid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac0Mid_r32); - APE.NcsiChannel0Mac0Mid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac0Mid_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0Low. */ - static ram_offset_t APE_NcsiChannel0Mac0Low_r32((uint8_t *)base, (uint32_t)18748); - APE.NcsiChannel0Mac0Low.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac0Low_r32); - APE.NcsiChannel0Mac0Low.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac0Low_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1High. */ - static ram_offset_t APE_NcsiChannel0Mac1High_r32((uint8_t *)base, (uint32_t)18756); - APE.NcsiChannel0Mac1High.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac1High_r32); - APE.NcsiChannel0Mac1High.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac1High_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1Mid. */ - static ram_offset_t APE_NcsiChannel0Mac1Mid_r32((uint8_t *)base, (uint32_t)18760); - APE.NcsiChannel0Mac1Mid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac1Mid_r32); - APE.NcsiChannel0Mac1Mid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac1Mid_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1Low. */ - static ram_offset_t APE_NcsiChannel0Mac1Low_r32((uint8_t *)base, (uint32_t)18764); - APE.NcsiChannel0Mac1Low.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac1Low_r32); - APE.NcsiChannel0Mac1Low.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac1Low_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac2High. */ - static ram_offset_t APE_NcsiChannel0Mac2High_r32((uint8_t *)base, (uint32_t)18772); - APE.NcsiChannel0Mac2High.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac2High_r32); - APE.NcsiChannel0Mac2High.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac2High_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac2Mid. */ - static ram_offset_t APE_NcsiChannel0Mac2Mid_r32((uint8_t *)base, (uint32_t)18776); - APE.NcsiChannel0Mac2Mid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac2Mid_r32); - APE.NcsiChannel0Mac2Mid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac2Mid_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac2Low. */ - static ram_offset_t APE_NcsiChannel0Mac2Low_r32((uint8_t *)base, (uint32_t)18780); - APE.NcsiChannel0Mac2Low.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac2Low_r32); - APE.NcsiChannel0Mac2Low.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac2Low_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac3High. */ - static ram_offset_t APE_NcsiChannel0Mac3High_r32((uint8_t *)base, (uint32_t)18788); - APE.NcsiChannel0Mac3High.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac3High_r32); - APE.NcsiChannel0Mac3High.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac3High_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac3Mid. */ - static ram_offset_t APE_NcsiChannel0Mac3Mid_r32((uint8_t *)base, (uint32_t)18792); - APE.NcsiChannel0Mac3Mid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac3Mid_r32); - APE.NcsiChannel0Mac3Mid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac3Mid_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac3Low. */ - static ram_offset_t APE_NcsiChannel0Mac3Low_r32((uint8_t *)base, (uint32_t)18796); - APE.NcsiChannel0Mac3Low.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac3Low_r32); - APE.NcsiChannel0Mac3Low.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac3Low_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0VlanValid. */ - static ram_offset_t APE_NcsiChannel0Mac0VlanValid_r32((uint8_t *)base, (uint32_t)18800); - APE.NcsiChannel0Mac0VlanValid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac0VlanValid_r32); - APE.NcsiChannel0Mac0VlanValid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac0VlanValid_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac0Vlan. */ - static ram_offset_t APE_NcsiChannel0Mac0Vlan_r32((uint8_t *)base, (uint32_t)18804); - APE.NcsiChannel0Mac0Vlan.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac0Vlan_r32); - APE.NcsiChannel0Mac0Vlan.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac0Vlan_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1VlanValid. */ - static ram_offset_t APE_NcsiChannel0Mac1VlanValid_r32((uint8_t *)base, (uint32_t)18808); - APE.NcsiChannel0Mac1VlanValid.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac1VlanValid_r32); - APE.NcsiChannel0Mac1VlanValid.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac1VlanValid_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Mac1Vlan. */ - static ram_offset_t APE_NcsiChannel0Mac1Vlan_r32((uint8_t *)base, (uint32_t)18812); - APE.NcsiChannel0Mac1Vlan.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Mac1Vlan_r32); - APE.NcsiChannel0Mac1Vlan.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Mac1Vlan_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Status. */ - static ram_offset_t APE_NcsiChannel0Status_r32((uint8_t *)base, (uint32_t)18816); - APE.NcsiChannel0Status.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Status_r32); - APE.NcsiChannel0Status.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Status_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0ResetCount. */ - static ram_offset_t APE_NcsiChannel0ResetCount_r32((uint8_t *)base, (uint32_t)18820); - APE.NcsiChannel0ResetCount.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0ResetCount_r32); - APE.NcsiChannel0ResetCount.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0ResetCount_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Pxe. */ - static ram_offset_t APE_NcsiChannel0Pxe_r32((uint8_t *)base, (uint32_t)18824); - APE.NcsiChannel0Pxe.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Pxe_r32); - APE.NcsiChannel0Pxe.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Pxe_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Dropfil. */ - static ram_offset_t APE_NcsiChannel0Dropfil_r32((uint8_t *)base, (uint32_t)18828); - APE.NcsiChannel0Dropfil.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Dropfil_r32); - APE.NcsiChannel0Dropfil.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Dropfil_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Slink. */ - static ram_offset_t APE_NcsiChannel0Slink_r32((uint8_t *)base, (uint32_t)18832); - APE.NcsiChannel0Slink.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Slink_r32); - APE.NcsiChannel0Slink.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Slink_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0Dbg. */ - static ram_offset_t APE_NcsiChannel0Dbg_r32((uint8_t *)base, (uint32_t)18848); - APE.NcsiChannel0Dbg.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0Dbg_r32); - APE.NcsiChannel0Dbg.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0Dbg_r32); - - /** @brief Bitmap for @ref APE_t.NcsiChannel0CtrlstatRx. */ - static ram_offset_t APE_NcsiChannel0CtrlstatRx_r32((uint8_t *)base, (uint32_t)18864); - APE.NcsiChannel0CtrlstatRx.r32.installReadCallback(read_from_ram, &APE_NcsiChannel0CtrlstatRx_r32); - APE.NcsiChannel0CtrlstatRx.r32.installWriteCallback(write_to_ram, &APE_NcsiChannel0CtrlstatRx_r32); - /** @brief Bitmap for @ref APE_t.PerLockRequestPhy0. */ static ram_offset_t APE_PerLockRequestPhy0_r32((uint8_t *)base, (uint32_t)33792); APE.PerLockRequestPhy0.r32.installReadCallback(read_from_ram, &APE_PerLockRequestPhy0_r32); diff --git a/simulator/bcm5719_SHM.cpp b/simulator/bcm5719_SHM.cpp new file mode 100644 index 0000000..a369dfa --- /dev/null +++ b/simulator/bcm5719_SHM.cpp @@ -0,0 +1,207 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file bcm5719_SHM.cpp +/// +/// @project bcm5719 +/// +/// @brief bcm5719_SHM +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <bcm5719_SHM.h> + +SHM_t SHM; + +void init_bcm5719_SHM(void) +{ + /** @brief Component Registers for @ref SHM. */ + /** @brief Bitmap for @ref SHM_t.SegSig. */ + + /** @brief Bitmap for @ref SHM_t.FwStatus. */ + + /** @brief Bitmap for @ref SHM_t.FwFeatures. */ + + /** @brief Bitmap for @ref SHM_t.4014. */ + + /** @brief Bitmap for @ref SHM_t.FwVersion. */ + + /** @brief Bitmap for @ref SHM_t.SegMessageBufferOffset. */ + + /** @brief Bitmap for @ref SHM_t.SegMessageBufferLength. */ + + /** @brief Bitmap for @ref SHM_t.4024. */ + + /** @brief Bitmap for @ref SHM_t.4028. */ + + /** @brief Bitmap for @ref SHM_t.RcpuSegSig. */ + + /** @brief Bitmap for @ref SHM_t.RcpuSegLength. */ + + /** @brief Bitmap for @ref SHM_t.RcpuInitCount. */ + + /** @brief Bitmap for @ref SHM_t.RcpuFwVersion. */ + + /** @brief Bitmap for @ref SHM_t.RcpuCfgFeature. */ + + /** @brief Bitmap for @ref SHM_t.RcpuPciVendorDeviceId. */ + + /** @brief Bitmap for @ref SHM_t.RcpuPciSubsystemId. */ + + /** @brief Bitmap for @ref SHM_t.RcpuApeResetCount. */ + + /** @brief Bitmap for @ref SHM_t.RcpuLastApeStatus. */ + + /** @brief Bitmap for @ref SHM_t.RcpuLastApeFwStatus. */ + + /** @brief Bitmap for @ref SHM_t.RcpuCfgHw. */ + + /** @brief Bitmap for @ref SHM_t.RcpuCfgHw2. */ + + /** @brief Bitmap for @ref SHM_t.RcpuCpmuStatus. */ + + /** @brief Bitmap for @ref SHM_t.HostSegSig. */ + + /** @brief Bitmap for @ref SHM_t.HostSegLen. */ + + /** @brief Bitmap for @ref SHM_t.HostInitCount. */ + + /** @brief Bitmap for @ref SHM_t.HostDriverId. */ + + /** @brief Bitmap for @ref SHM_t.HostBehavior. */ + + /** @brief Bitmap for @ref SHM_t.HeartbeatInterval. */ + + /** @brief Bitmap for @ref SHM_t.HeartbeatCount. */ + + /** @brief Bitmap for @ref SHM_t.HostDriverState. */ + + /** @brief Bitmap for @ref SHM_t.WolSpeed. */ + + /** @brief Bitmap for @ref SHM_t.EventStatus. */ + + /** @brief Bitmap for @ref SHM_t.ProtMagic. */ + + /** @brief Bitmap for @ref SHM_t.ProtMac0High. */ + + /** @brief Bitmap for @ref SHM_t.ProtMac0Low. */ + + /** @brief Bitmap for @ref SHM_t.NcsiSig. */ + + /** @brief Bitmap for @ref SHM_t.NcsiBuildTime. */ + + /** @brief Bitmap for @ref SHM_t.NcsiBuildTime2. */ + + /** @brief Bitmap for @ref SHM_t.NcsiBuildTime3. */ + + /** @brief Bitmap for @ref SHM_t.NcsiBuildDate. */ + + /** @brief Bitmap for @ref SHM_t.NcsiBuildDate2. */ + + /** @brief Bitmap for @ref SHM_t.NcsiBuildDate3. */ + + /** @brief Bitmap for @ref SHM_t.ChipId. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Info. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mcid. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Aen. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Bfilt. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mfilt. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Setting1. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Setting2. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Vlan. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0AltHostMacHigh. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0AltHostMacMid. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0AltHostMacLow. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac0High. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac0Mid. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac0Low. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac1High. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac1Mid. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac1Low. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac2High. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac2Mid. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac2Low. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac3High. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac3Mid. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac3Low. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac0VlanValid. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac0Vlan. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac1VlanValid. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac1Vlan. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Status. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0ResetCount. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Pxe. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Dropfil. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Slink. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Dbg. */ + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0CtrlstatRx. */ + + +} diff --git a/simulator/bcm5719_SHM_mmap.cpp b/simulator/bcm5719_SHM_mmap.cpp new file mode 100644 index 0000000..751e26b --- /dev/null +++ b/simulator/bcm5719_SHM_mmap.cpp @@ -0,0 +1,470 @@ +//////////////////////////////////////////////////////////////////////////////// +/// +/// @file bcm5719_SHM_mmap.cpp +/// +/// @project bcm5719 +/// +/// @brief bcm5719_SHM_mmap +/// +//////////////////////////////////////////////////////////////////////////////// +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// @copyright Copyright (c) 2018, Evan Lojewski +/// @cond +/// +/// All rights reserved. +/// +/// Redistribution and use in source and binary forms, with or without +/// modification, are permitted provided that the following conditions are met: +/// 1. Redistributions of source code must retain the above copyright notice, +/// this list of conditions and the following disclaimer. +/// 2. Redistributions in binary form must reproduce the above copyright notice, +/// this list of conditions and the following disclaimer in the documentation +/// and/or other materials provided with the distribution. +/// 3. Neither the name of the <organization> nor the +/// names of its contributors may be used to endorse or promote products +/// derived from this software without specific prior written permission. +/// +//////////////////////////////////////////////////////////////////////////////// +/// +/// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +/// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +/// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +/// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +/// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +/// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +/// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +/// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +/// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +/// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +/// POSSIBILITY OF SUCH DAMAGE. +/// @endcond +//////////////////////////////////////////////////////////////////////////////// + +#include <stdint.h> +#include <utility> +#include <bcm5719_SHM.h> + +#ifdef __ppc64__ +#define BARRIER() do { asm volatile ("sync 0\neieio\n" ::: "memory"); } while(0) +#else +#define BARRIER() do { asm volatile ("" ::: "memory"); } while(0) +#endif + +typedef std::pair<uint8_t *, uint32_t> ram_offset_t; + +static uint32_t read_from_ram(uint32_t val, void *args) +{ + ram_offset_t *loc = (ram_offset_t *)args; + + uint8_t *base = loc->first; + base += loc->second; + + BARRIER(); + return *(uint32_t *)base; +} + +static uint32_t write_to_ram(uint32_t val, void *args) +{ + ram_offset_t *loc = (ram_offset_t *)args; + + uint8_t *base = loc->first; + base += loc->second; + + BARRIER(); + *(uint32_t *)base = val; + BARRIER(); + return val; +} + +void init_bcm5719_SHM_mmap(void *base) +{ + /** @brief Component Registers for @ref SHM. */ + /** @brief Bitmap for @ref SHM_t.SegSig. */ + static ram_offset_t SHM_SegSig_r32((uint8_t *)base, (uint32_t)0); + SHM.SegSig.r32.installReadCallback(read_from_ram, &SHM_SegSig_r32); + SHM.SegSig.r32.installWriteCallback(write_to_ram, &SHM_SegSig_r32); + + /** @brief Bitmap for @ref SHM_t.FwStatus. */ + static ram_offset_t SHM_FwStatus_r32((uint8_t *)base, (uint32_t)12); + SHM.FwStatus.r32.installReadCallback(read_from_ram, &SHM_FwStatus_r32); + SHM.FwStatus.r32.installWriteCallback(write_to_ram, &SHM_FwStatus_r32); + + /** @brief Bitmap for @ref SHM_t.FwFeatures. */ + static ram_offset_t SHM_FwFeatures_r32((uint8_t *)base, (uint32_t)16); + SHM.FwFeatures.r32.installReadCallback(read_from_ram, &SHM_FwFeatures_r32); + SHM.FwFeatures.r32.installWriteCallback(write_to_ram, &SHM_FwFeatures_r32); + + /** @brief Bitmap for @ref SHM_t.4014. */ + static ram_offset_t SHM__4014_r32((uint8_t *)base, (uint32_t)20); + SHM._4014.r32.installReadCallback(read_from_ram, &SHM__4014_r32); + SHM._4014.r32.installWriteCallback(write_to_ram, &SHM__4014_r32); + + /** @brief Bitmap for @ref SHM_t.FwVersion. */ + static ram_offset_t SHM_FwVersion_r32((uint8_t *)base, (uint32_t)24); + SHM.FwVersion.r32.installReadCallback(read_from_ram, &SHM_FwVersion_r32); + SHM.FwVersion.r32.installWriteCallback(write_to_ram, &SHM_FwVersion_r32); + + /** @brief Bitmap for @ref SHM_t.SegMessageBufferOffset. */ + static ram_offset_t SHM_SegMessageBufferOffset_r32((uint8_t *)base, (uint32_t)28); + SHM.SegMessageBufferOffset.r32.installReadCallback(read_from_ram, &SHM_SegMessageBufferOffset_r32); + SHM.SegMessageBufferOffset.r32.installWriteCallback(write_to_ram, &SHM_SegMessageBufferOffset_r32); + + /** @brief Bitmap for @ref SHM_t.SegMessageBufferLength. */ + static ram_offset_t SHM_SegMessageBufferLength_r32((uint8_t *)base, (uint32_t)32); + SHM.SegMessageBufferLength.r32.installReadCallback(read_from_ram, &SHM_SegMessageBufferLength_r32); + SHM.SegMessageBufferLength.r32.installWriteCallback(write_to_ram, &SHM_SegMessageBufferLength_r32); + + /** @brief Bitmap for @ref SHM_t.4024. */ + static ram_offset_t SHM__4024_r32((uint8_t *)base, (uint32_t)36); + SHM._4024.r32.installReadCallback(read_from_ram, &SHM__4024_r32); + SHM._4024.r32.installWriteCallback(write_to_ram, &SHM__4024_r32); + + /** @brief Bitmap for @ref SHM_t.4028. */ + static ram_offset_t SHM__4028_r32((uint8_t *)base, (uint32_t)40); + SHM._4028.r32.installReadCallback(read_from_ram, &SHM__4028_r32); + SHM._4028.r32.installWriteCallback(write_to_ram, &SHM__4028_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuSegSig. */ + static ram_offset_t SHM_RcpuSegSig_r32((uint8_t *)base, (uint32_t)256); + SHM.RcpuSegSig.r32.installReadCallback(read_from_ram, &SHM_RcpuSegSig_r32); + SHM.RcpuSegSig.r32.installWriteCallback(write_to_ram, &SHM_RcpuSegSig_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuSegLength. */ + static ram_offset_t SHM_RcpuSegLength_r32((uint8_t *)base, (uint32_t)260); + SHM.RcpuSegLength.r32.installReadCallback(read_from_ram, &SHM_RcpuSegLength_r32); + SHM.RcpuSegLength.r32.installWriteCallback(write_to_ram, &SHM_RcpuSegLength_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuInitCount. */ + static ram_offset_t SHM_RcpuInitCount_r32((uint8_t *)base, (uint32_t)264); + SHM.RcpuInitCount.r32.installReadCallback(read_from_ram, &SHM_RcpuInitCount_r32); + SHM.RcpuInitCount.r32.installWriteCallback(write_to_ram, &SHM_RcpuInitCount_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuFwVersion. */ + static ram_offset_t SHM_RcpuFwVersion_r32((uint8_t *)base, (uint32_t)268); + SHM.RcpuFwVersion.r32.installReadCallback(read_from_ram, &SHM_RcpuFwVersion_r32); + SHM.RcpuFwVersion.r32.installWriteCallback(write_to_ram, &SHM_RcpuFwVersion_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuCfgFeature. */ + static ram_offset_t SHM_RcpuCfgFeature_r32((uint8_t *)base, (uint32_t)272); + SHM.RcpuCfgFeature.r32.installReadCallback(read_from_ram, &SHM_RcpuCfgFeature_r32); + SHM.RcpuCfgFeature.r32.installWriteCallback(write_to_ram, &SHM_RcpuCfgFeature_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuPciVendorDeviceId. */ + static ram_offset_t SHM_RcpuPciVendorDeviceId_r32((uint8_t *)base, (uint32_t)276); + SHM.RcpuPciVendorDeviceId.r32.installReadCallback(read_from_ram, &SHM_RcpuPciVendorDeviceId_r32); + SHM.RcpuPciVendorDeviceId.r32.installWriteCallback(write_to_ram, &SHM_RcpuPciVendorDeviceId_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuPciSubsystemId. */ + static ram_offset_t SHM_RcpuPciSubsystemId_r32((uint8_t *)base, (uint32_t)280); + SHM.RcpuPciSubsystemId.r32.installReadCallback(read_from_ram, &SHM_RcpuPciSubsystemId_r32); + SHM.RcpuPciSubsystemId.r32.installWriteCallback(write_to_ram, &SHM_RcpuPciSubsystemId_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuApeResetCount. */ + static ram_offset_t SHM_RcpuApeResetCount_r32((uint8_t *)base, (uint32_t)284); + SHM.RcpuApeResetCount.r32.installReadCallback(read_from_ram, &SHM_RcpuApeResetCount_r32); + SHM.RcpuApeResetCount.r32.installWriteCallback(write_to_ram, &SHM_RcpuApeResetCount_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuLastApeStatus. */ + static ram_offset_t SHM_RcpuLastApeStatus_r32((uint8_t *)base, (uint32_t)288); + SHM.RcpuLastApeStatus.r32.installReadCallback(read_from_ram, &SHM_RcpuLastApeStatus_r32); + SHM.RcpuLastApeStatus.r32.installWriteCallback(write_to_ram, &SHM_RcpuLastApeStatus_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuLastApeFwStatus. */ + static ram_offset_t SHM_RcpuLastApeFwStatus_r32((uint8_t *)base, (uint32_t)292); + SHM.RcpuLastApeFwStatus.r32.installReadCallback(read_from_ram, &SHM_RcpuLastApeFwStatus_r32); + SHM.RcpuLastApeFwStatus.r32.installWriteCallback(write_to_ram, &SHM_RcpuLastApeFwStatus_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuCfgHw. */ + static ram_offset_t SHM_RcpuCfgHw_r32((uint8_t *)base, (uint32_t)296); + SHM.RcpuCfgHw.r32.installReadCallback(read_from_ram, &SHM_RcpuCfgHw_r32); + SHM.RcpuCfgHw.r32.installWriteCallback(write_to_ram, &SHM_RcpuCfgHw_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuCfgHw2. */ + static ram_offset_t SHM_RcpuCfgHw2_r32((uint8_t *)base, (uint32_t)300); + SHM.RcpuCfgHw2.r32.installReadCallback(read_from_ram, &SHM_RcpuCfgHw2_r32); + SHM.RcpuCfgHw2.r32.installWriteCallback(write_to_ram, &SHM_RcpuCfgHw2_r32); + + /** @brief Bitmap for @ref SHM_t.RcpuCpmuStatus. */ + static ram_offset_t SHM_RcpuCpmuStatus_r32((uint8_t *)base, (uint32_t)304); + SHM.RcpuCpmuStatus.r32.installReadCallback(read_from_ram, &SHM_RcpuCpmuStatus_r32); + SHM.RcpuCpmuStatus.r32.installWriteCallback(write_to_ram, &SHM_RcpuCpmuStatus_r32); + + /** @brief Bitmap for @ref SHM_t.HostSegSig. */ + static ram_offset_t SHM_HostSegSig_r32((uint8_t *)base, (uint32_t)512); + SHM.HostSegSig.r32.installReadCallback(read_from_ram, &SHM_HostSegSig_r32); + SHM.HostSegSig.r32.installWriteCallback(write_to_ram, &SHM_HostSegSig_r32); + + /** @brief Bitmap for @ref SHM_t.HostSegLen. */ + static ram_offset_t SHM_HostSegLen_r32((uint8_t *)base, (uint32_t)516); + SHM.HostSegLen.r32.installReadCallback(read_from_ram, &SHM_HostSegLen_r32); + SHM.HostSegLen.r32.installWriteCallback(write_to_ram, &SHM_HostSegLen_r32); + + /** @brief Bitmap for @ref SHM_t.HostInitCount. */ + static ram_offset_t SHM_HostInitCount_r32((uint8_t *)base, (uint32_t)520); + SHM.HostInitCount.r32.installReadCallback(read_from_ram, &SHM_HostInitCount_r32); + SHM.HostInitCount.r32.installWriteCallback(write_to_ram, &SHM_HostInitCount_r32); + + /** @brief Bitmap for @ref SHM_t.HostDriverId. */ + static ram_offset_t SHM_HostDriverId_r32((uint8_t *)base, (uint32_t)524); + SHM.HostDriverId.r32.installReadCallback(read_from_ram, &SHM_HostDriverId_r32); + SHM.HostDriverId.r32.installWriteCallback(write_to_ram, &SHM_HostDriverId_r32); + + /** @brief Bitmap for @ref SHM_t.HostBehavior. */ + static ram_offset_t SHM_HostBehavior_r32((uint8_t *)base, (uint32_t)528); + SHM.HostBehavior.r32.installReadCallback(read_from_ram, &SHM_HostBehavior_r32); + SHM.HostBehavior.r32.installWriteCallback(write_to_ram, &SHM_HostBehavior_r32); + + /** @brief Bitmap for @ref SHM_t.HeartbeatInterval. */ + static ram_offset_t SHM_HeartbeatInterval_r32((uint8_t *)base, (uint32_t)532); + SHM.HeartbeatInterval.r32.installReadCallback(read_from_ram, &SHM_HeartbeatInterval_r32); + SHM.HeartbeatInterval.r32.installWriteCallback(write_to_ram, &SHM_HeartbeatInterval_r32); + + /** @brief Bitmap for @ref SHM_t.HeartbeatCount. */ + static ram_offset_t SHM_HeartbeatCount_r32((uint8_t *)base, (uint32_t)536); + SHM.HeartbeatCount.r32.installReadCallback(read_from_ram, &SHM_HeartbeatCount_r32); + SHM.HeartbeatCount.r32.installWriteCallback(write_to_ram, &SHM_HeartbeatCount_r32); + + /** @brief Bitmap for @ref SHM_t.HostDriverState. */ + static ram_offset_t SHM_HostDriverState_r32((uint8_t *)base, (uint32_t)540); + SHM.HostDriverState.r32.installReadCallback(read_from_ram, &SHM_HostDriverState_r32); + SHM.HostDriverState.r32.installWriteCallback(write_to_ram, &SHM_HostDriverState_r32); + + /** @brief Bitmap for @ref SHM_t.WolSpeed. */ + static ram_offset_t SHM_WolSpeed_r32((uint8_t *)base, (uint32_t)548); + SHM.WolSpeed.r32.installReadCallback(read_from_ram, &SHM_WolSpeed_r32); + SHM.WolSpeed.r32.installWriteCallback(write_to_ram, &SHM_WolSpeed_r32); + + /** @brief Bitmap for @ref SHM_t.EventStatus. */ + static ram_offset_t SHM_EventStatus_r32((uint8_t *)base, (uint32_t)768); + SHM.EventStatus.r32.installReadCallback(read_from_ram, &SHM_EventStatus_r32); + SHM.EventStatus.r32.installWriteCallback(write_to_ram, &SHM_EventStatus_r32); + + /** @brief Bitmap for @ref SHM_t.ProtMagic. */ + static ram_offset_t SHM_ProtMagic_r32((uint8_t *)base, (uint32_t)776); + SHM.ProtMagic.r32.installReadCallback(read_from_ram, &SHM_ProtMagic_r32); + SHM.ProtMagic.r32.installWriteCallback(write_to_ram, &SHM_ProtMagic_r32); + + /** @brief Bitmap for @ref SHM_t.ProtMac0High. */ + static ram_offset_t SHM_ProtMac0High_r32((uint8_t *)base, (uint32_t)788); + SHM.ProtMac0High.r32.installReadCallback(read_from_ram, &SHM_ProtMac0High_r32); + SHM.ProtMac0High.r32.installWriteCallback(write_to_ram, &SHM_ProtMac0High_r32); + + /** @brief Bitmap for @ref SHM_t.ProtMac0Low. */ + static ram_offset_t SHM_ProtMac0Low_r32((uint8_t *)base, (uint32_t)792); + SHM.ProtMac0Low.r32.installReadCallback(read_from_ram, &SHM_ProtMac0Low_r32); + SHM.ProtMac0Low.r32.installWriteCallback(write_to_ram, &SHM_ProtMac0Low_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiSig. */ + static ram_offset_t SHM_NcsiSig_r32((uint8_t *)base, (uint32_t)2048); + SHM.NcsiSig.r32.installReadCallback(read_from_ram, &SHM_NcsiSig_r32); + SHM.NcsiSig.r32.installWriteCallback(write_to_ram, &SHM_NcsiSig_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiBuildTime. */ + static ram_offset_t SHM_NcsiBuildTime_r32((uint8_t *)base, (uint32_t)2064); + SHM.NcsiBuildTime.r32.installReadCallback(read_from_ram, &SHM_NcsiBuildTime_r32); + SHM.NcsiBuildTime.r32.installWriteCallback(write_to_ram, &SHM_NcsiBuildTime_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiBuildTime2. */ + static ram_offset_t SHM_NcsiBuildTime2_r32((uint8_t *)base, (uint32_t)2068); + SHM.NcsiBuildTime2.r32.installReadCallback(read_from_ram, &SHM_NcsiBuildTime2_r32); + SHM.NcsiBuildTime2.r32.installWriteCallback(write_to_ram, &SHM_NcsiBuildTime2_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiBuildTime3. */ + static ram_offset_t SHM_NcsiBuildTime3_r32((uint8_t *)base, (uint32_t)2072); + SHM.NcsiBuildTime3.r32.installReadCallback(read_from_ram, &SHM_NcsiBuildTime3_r32); + SHM.NcsiBuildTime3.r32.installWriteCallback(write_to_ram, &SHM_NcsiBuildTime3_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiBuildDate. */ + static ram_offset_t SHM_NcsiBuildDate_r32((uint8_t *)base, (uint32_t)2076); + SHM.NcsiBuildDate.r32.installReadCallback(read_from_ram, &SHM_NcsiBuildDate_r32); + SHM.NcsiBuildDate.r32.installWriteCallback(write_to_ram, &SHM_NcsiBuildDate_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiBuildDate2. */ + static ram_offset_t SHM_NcsiBuildDate2_r32((uint8_t *)base, (uint32_t)2080); + SHM.NcsiBuildDate2.r32.installReadCallback(read_from_ram, &SHM_NcsiBuildDate2_r32); + SHM.NcsiBuildDate2.r32.installWriteCallback(write_to_ram, &SHM_NcsiBuildDate2_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiBuildDate3. */ + static ram_offset_t SHM_NcsiBuildDate3_r32((uint8_t *)base, (uint32_t)2084); + SHM.NcsiBuildDate3.r32.installReadCallback(read_from_ram, &SHM_NcsiBuildDate3_r32); + SHM.NcsiBuildDate3.r32.installWriteCallback(write_to_ram, &SHM_NcsiBuildDate3_r32); + + /** @brief Bitmap for @ref SHM_t.ChipId. */ + static ram_offset_t SHM_ChipId_r32((uint8_t *)base, (uint32_t)2192); + SHM.ChipId.r32.installReadCallback(read_from_ram, &SHM_ChipId_r32); + SHM.ChipId.r32.installWriteCallback(write_to_ram, &SHM_ChipId_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Info. */ + static ram_offset_t SHM_NcsiChannel0Info_r32((uint8_t *)base, (uint32_t)2304); + SHM.NcsiChannel0Info.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Info_r32); + SHM.NcsiChannel0Info.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Info_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mcid. */ + static ram_offset_t SHM_NcsiChannel0Mcid_r32((uint8_t *)base, (uint32_t)2308); + SHM.NcsiChannel0Mcid.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mcid_r32); + SHM.NcsiChannel0Mcid.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mcid_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Aen. */ + static ram_offset_t SHM_NcsiChannel0Aen_r32((uint8_t *)base, (uint32_t)2312); + SHM.NcsiChannel0Aen.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Aen_r32); + SHM.NcsiChannel0Aen.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Aen_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Bfilt. */ + static ram_offset_t SHM_NcsiChannel0Bfilt_r32((uint8_t *)base, (uint32_t)2316); + SHM.NcsiChannel0Bfilt.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Bfilt_r32); + SHM.NcsiChannel0Bfilt.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Bfilt_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mfilt. */ + static ram_offset_t SHM_NcsiChannel0Mfilt_r32((uint8_t *)base, (uint32_t)2320); + SHM.NcsiChannel0Mfilt.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mfilt_r32); + SHM.NcsiChannel0Mfilt.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mfilt_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Setting1. */ + static ram_offset_t SHM_NcsiChannel0Setting1_r32((uint8_t *)base, (uint32_t)2324); + SHM.NcsiChannel0Setting1.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Setting1_r32); + SHM.NcsiChannel0Setting1.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Setting1_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Setting2. */ + static ram_offset_t SHM_NcsiChannel0Setting2_r32((uint8_t *)base, (uint32_t)2328); + SHM.NcsiChannel0Setting2.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Setting2_r32); + SHM.NcsiChannel0Setting2.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Setting2_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Vlan. */ + static ram_offset_t SHM_NcsiChannel0Vlan_r32((uint8_t *)base, (uint32_t)2332); + SHM.NcsiChannel0Vlan.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Vlan_r32); + SHM.NcsiChannel0Vlan.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Vlan_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0AltHostMacHigh. */ + static ram_offset_t SHM_NcsiChannel0AltHostMacHigh_r32((uint8_t *)base, (uint32_t)2340); + SHM.NcsiChannel0AltHostMacHigh.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0AltHostMacHigh_r32); + SHM.NcsiChannel0AltHostMacHigh.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0AltHostMacHigh_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0AltHostMacMid. */ + static ram_offset_t SHM_NcsiChannel0AltHostMacMid_r32((uint8_t *)base, (uint32_t)2344); + SHM.NcsiChannel0AltHostMacMid.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0AltHostMacMid_r32); + SHM.NcsiChannel0AltHostMacMid.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0AltHostMacMid_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0AltHostMacLow. */ + static ram_offset_t SHM_NcsiChannel0AltHostMacLow_r32((uint8_t *)base, (uint32_t)2348); + SHM.NcsiChannel0AltHostMacLow.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0AltHostMacLow_r32); + SHM.NcsiChannel0AltHostMacLow.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0AltHostMacLow_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac0High. */ + static ram_offset_t SHM_NcsiChannel0Mac0High_r32((uint8_t *)base, (uint32_t)2356); + SHM.NcsiChannel0Mac0High.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac0High_r32); + SHM.NcsiChannel0Mac0High.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac0High_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac0Mid. */ + static ram_offset_t SHM_NcsiChannel0Mac0Mid_r32((uint8_t *)base, (uint32_t)2360); + SHM.NcsiChannel0Mac0Mid.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac0Mid_r32); + SHM.NcsiChannel0Mac0Mid.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac0Mid_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac0Low. */ + static ram_offset_t SHM_NcsiChannel0Mac0Low_r32((uint8_t *)base, (uint32_t)2364); + SHM.NcsiChannel0Mac0Low.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac0Low_r32); + SHM.NcsiChannel0Mac0Low.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac0Low_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac1High. */ + static ram_offset_t SHM_NcsiChannel0Mac1High_r32((uint8_t *)base, (uint32_t)2372); + SHM.NcsiChannel0Mac1High.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac1High_r32); + SHM.NcsiChannel0Mac1High.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac1High_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac1Mid. */ + static ram_offset_t SHM_NcsiChannel0Mac1Mid_r32((uint8_t *)base, (uint32_t)2376); + SHM.NcsiChannel0Mac1Mid.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac1Mid_r32); + SHM.NcsiChannel0Mac1Mid.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac1Mid_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac1Low. */ + static ram_offset_t SHM_NcsiChannel0Mac1Low_r32((uint8_t *)base, (uint32_t)2380); + SHM.NcsiChannel0Mac1Low.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac1Low_r32); + SHM.NcsiChannel0Mac1Low.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac1Low_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac2High. */ + static ram_offset_t SHM_NcsiChannel0Mac2High_r32((uint8_t *)base, (uint32_t)2388); + SHM.NcsiChannel0Mac2High.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac2High_r32); + SHM.NcsiChannel0Mac2High.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac2High_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac2Mid. */ + static ram_offset_t SHM_NcsiChannel0Mac2Mid_r32((uint8_t *)base, (uint32_t)2392); + SHM.NcsiChannel0Mac2Mid.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac2Mid_r32); + SHM.NcsiChannel0Mac2Mid.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac2Mid_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac2Low. */ + static ram_offset_t SHM_NcsiChannel0Mac2Low_r32((uint8_t *)base, (uint32_t)2396); + SHM.NcsiChannel0Mac2Low.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac2Low_r32); + SHM.NcsiChannel0Mac2Low.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac2Low_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac3High. */ + static ram_offset_t SHM_NcsiChannel0Mac3High_r32((uint8_t *)base, (uint32_t)2404); + SHM.NcsiChannel0Mac3High.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac3High_r32); + SHM.NcsiChannel0Mac3High.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac3High_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac3Mid. */ + static ram_offset_t SHM_NcsiChannel0Mac3Mid_r32((uint8_t *)base, (uint32_t)2408); + SHM.NcsiChannel0Mac3Mid.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac3Mid_r32); + SHM.NcsiChannel0Mac3Mid.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac3Mid_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac3Low. */ + static ram_offset_t SHM_NcsiChannel0Mac3Low_r32((uint8_t *)base, (uint32_t)2412); + SHM.NcsiChannel0Mac3Low.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac3Low_r32); + SHM.NcsiChannel0Mac3Low.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac3Low_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac0VlanValid. */ + static ram_offset_t SHM_NcsiChannel0Mac0VlanValid_r32((uint8_t *)base, (uint32_t)2416); + SHM.NcsiChannel0Mac0VlanValid.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac0VlanValid_r32); + SHM.NcsiChannel0Mac0VlanValid.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac0VlanValid_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac0Vlan. */ + static ram_offset_t SHM_NcsiChannel0Mac0Vlan_r32((uint8_t *)base, (uint32_t)2420); + SHM.NcsiChannel0Mac0Vlan.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac0Vlan_r32); + SHM.NcsiChannel0Mac0Vlan.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac0Vlan_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac1VlanValid. */ + static ram_offset_t SHM_NcsiChannel0Mac1VlanValid_r32((uint8_t *)base, (uint32_t)2424); + SHM.NcsiChannel0Mac1VlanValid.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac1VlanValid_r32); + SHM.NcsiChannel0Mac1VlanValid.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac1VlanValid_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Mac1Vlan. */ + static ram_offset_t SHM_NcsiChannel0Mac1Vlan_r32((uint8_t *)base, (uint32_t)2428); + SHM.NcsiChannel0Mac1Vlan.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Mac1Vlan_r32); + SHM.NcsiChannel0Mac1Vlan.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Mac1Vlan_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Status. */ + static ram_offset_t SHM_NcsiChannel0Status_r32((uint8_t *)base, (uint32_t)2432); + SHM.NcsiChannel0Status.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Status_r32); + SHM.NcsiChannel0Status.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Status_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0ResetCount. */ + static ram_offset_t SHM_NcsiChannel0ResetCount_r32((uint8_t *)base, (uint32_t)2436); + SHM.NcsiChannel0ResetCount.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0ResetCount_r32); + SHM.NcsiChannel0ResetCount.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0ResetCount_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Pxe. */ + static ram_offset_t SHM_NcsiChannel0Pxe_r32((uint8_t *)base, (uint32_t)2440); + SHM.NcsiChannel0Pxe.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Pxe_r32); + SHM.NcsiChannel0Pxe.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Pxe_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Dropfil. */ + static ram_offset_t SHM_NcsiChannel0Dropfil_r32((uint8_t *)base, (uint32_t)2444); + SHM.NcsiChannel0Dropfil.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Dropfil_r32); + SHM.NcsiChannel0Dropfil.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Dropfil_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Slink. */ + static ram_offset_t SHM_NcsiChannel0Slink_r32((uint8_t *)base, (uint32_t)2448); + SHM.NcsiChannel0Slink.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Slink_r32); + SHM.NcsiChannel0Slink.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Slink_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0Dbg. */ + static ram_offset_t SHM_NcsiChannel0Dbg_r32((uint8_t *)base, (uint32_t)2464); + SHM.NcsiChannel0Dbg.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0Dbg_r32); + SHM.NcsiChannel0Dbg.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0Dbg_r32); + + /** @brief Bitmap for @ref SHM_t.NcsiChannel0CtrlstatRx. */ + static ram_offset_t SHM_NcsiChannel0CtrlstatRx_r32((uint8_t *)base, (uint32_t)2480); + SHM.NcsiChannel0CtrlstatRx.r32.installReadCallback(read_from_ram, &SHM_NcsiChannel0CtrlstatRx_r32); + SHM.NcsiChannel0CtrlstatRx.r32.installWriteCallback(write_to_ram, &SHM_NcsiChannel0CtrlstatRx_r32); + + +} diff --git a/stage1/main.c b/stage1/main.c index 4df446b..5469fbd 100644 --- a/stage1/main.c +++ b/stage1/main.c @@ -60,6 +60,7 @@ #include <bcm5719_GEN.h> #include <bcm5719_DEVICE.h> #include <bcm5719_APE.h> +#include <bcm5719_SHM.h> #include <APE.h> #include <string.h> @@ -99,32 +100,32 @@ int main() init_hw(&gNVMContents); #endif - // Send configuration information to APE. - APE.RcpuFwVersion.r32 = 0x0127; - APE.RcpuCfgFeature.r32 = GEN.GenCfgFeature.r32; - APE.RcpuPciVendorDeviceId.r32 = DEVICE.PciVendorDeviceId.r32; - APE.RcpuPciSubsystemId.r32 = DEVICE.PciSubsystemId.r32; - APE.RcpuCfgHw.r32 = GEN.GenCfgHw.r32; - APE.RcpuCfgHw2.r32 = GEN.GenCfgHw2.r32; - APE.RcpuCpmuStatus.bits.Status = (DEVICE.Status.r32 & 0xFFFF0000) >> 16; - APE.RcpuCpmuStatus.bits.Address = APE_RCPU_CPMU_STATUS_ADDRESS_ADDRESS; - - if(APE_RCPU_SEG_SIG_SIG_RCPU_MAGIC != APE.RcpuSegSig.bits.Sig) + // Send configuration information to APE SHM. + SHM.RcpuFwVersion.r32 = 0x0127; + SHM.RcpuCfgFeature.r32 = GEN.GenCfgFeature.r32; + SHM.RcpuPciVendorDeviceId.r32 = DEVICE.PciVendorDeviceId.r32; + SHM.RcpuPciSubsystemId.r32 = DEVICE.PciSubsystemId.r32; + SHM.RcpuCfgHw.r32 = GEN.GenCfgHw.r32; + SHM.RcpuCfgHw2.r32 = GEN.GenCfgHw2.r32; + SHM.RcpuCpmuStatus.bits.Status = (DEVICE.Status.r32 & 0xFFFF0000) >> 16; + SHM.RcpuCpmuStatus.bits.Address = SHM_RCPU_CPMU_STATUS_ADDRESS_ADDRESS; + + if(SHM_RCPU_SEG_SIG_SIG_RCPU_MAGIC != SHM.RcpuSegSig.bits.Sig) { - APE.RcpuInitCount.r32 = 1; + SHM.RcpuInitCount.r32 = 1; } else { - APE.RcpuInitCount.r32 = APE.RcpuInitCount.r32 + 1; + SHM.RcpuInitCount.r32 = SHM.RcpuInitCount.r32 + 1; } - APE.RcpuApeResetCount.r32 = 0; - APE.RcpuLastApeStatus.r32 = 0; - APE.RcpuLastApeFwStatus.r32 = 0; + SHM.RcpuApeResetCount.r32 = 0; + SHM.RcpuLastApeStatus.r32 = 0; + SHM.RcpuLastApeFwStatus.r32 = 0; // Mark it as valid. - APE.RcpuSegLength.r32 = 0x34; - APE.RcpuSegSig.bits.Sig = APE_RCPU_SEG_SIG_SIG_RCPU_MAGIC; + SHM.RcpuSegLength.r32 = 0x34; + SHM.RcpuSegSig.bits.Sig = SHM_RCPU_SEG_SIG_SIG_RCPU_MAGIC; // Set GEN_FIRMWARE_MBOX to BOOTCODE_READY_MAGIC. |
