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-rw-r--r--simulator/CMakeLists.txt2
-rw-r--r--simulator/HAL.cpp7
-rw-r--r--simulator/bcm5719_APE_mmap.cpp8
-rw-r--r--simulator/bcm5719_DEVICE_mmap.cpp8
-rw-r--r--simulator/bcm5719_GEN_mmap.cpp8
-rw-r--r--simulator/bcm5719_MII_mmap.cpp8
-rw-r--r--simulator/bcm5719_NVM_mmap.cpp8
-rw-r--r--utils/bcmregtool/CMakeLists.txt6
-rw-r--r--utils/bcmregtool/main.cpp287
9 files changed, 291 insertions, 51 deletions
diff --git a/simulator/CMakeLists.txt b/simulator/CMakeLists.txt
index d3ff497..3853d50 100644
--- a/simulator/CMakeLists.txt
+++ b/simulator/CMakeLists.txt
@@ -6,6 +6,8 @@ simulator_add_library(${PROJECT_NAME} STATIC
bcm5719_DEVICE_mmap.cpp
bcm5719_DEVICE.cpp
+ bcm5719_GEN_mmap.cpp
+ bcm5719_GEN.cpp
bcm5719_NVM_mmap.cpp
bcm5719_NVM.cpp
bcm5719_APE.cpp
diff --git a/simulator/HAL.cpp b/simulator/HAL.cpp
index 80b9eaf..7b34af7 100644
--- a/simulator/HAL.cpp
+++ b/simulator/HAL.cpp
@@ -3,6 +3,7 @@
#include <bcm5719_DEVICE.h>
#include <bcm5719_APE.h>
+#include <bcm5719_GEN.h>
#include <dirent.h>
#include <endian.h>
#include <errno.h>
@@ -242,10 +243,14 @@ bool initHAL(const char *pci_path)
init_bcm5719_DEVICE();
init_bcm5719_DEVICE_mmap(DEVICEBase);
+
+ init_bcm5719_GEN();
+ init_bcm5719_GEN_mmap(&DEVICEBase[0x8000 + 0xB50]); // 0x8000 for windowed area
+
init_bcm5719_APE();
// init_bcm5719_APE_mmap();
init_bcm5719_NVM();
- init_bcm5719_NVM_mmap(DEVICEBase + 0x7000);
+ init_bcm5719_NVM_mmap(&DEVICEBase[0x7000]);
return true;
}
diff --git a/simulator/bcm5719_APE_mmap.cpp b/simulator/bcm5719_APE_mmap.cpp
index 5003e21..fe22cff 100644
--- a/simulator/bcm5719_APE_mmap.cpp
+++ b/simulator/bcm5719_APE_mmap.cpp
@@ -46,6 +46,12 @@
#include <utility>
#include <bcm5719_APE.h>
+#ifdef __ppc64__
+#define BARRIER() do { asm volatile ("sync 0\neieio\n" ::: "memory"); } while(0)
+#else
+#define BARRIER() do { asm volatile ("" ::: "memory"); } while(0)
+#endif
+
typedef std::pair<uint8_t *, uint32_t> ram_offset_t;
static uint32_t read_from_ram(uint32_t val, void *args)
@@ -55,6 +61,7 @@ static uint32_t read_from_ram(uint32_t val, void *args)
uint8_t *base = loc->first;
base += loc->second;
+ BARRIER();
return *(uint32_t *)base;
}
@@ -65,6 +72,7 @@ static uint32_t write_to_ram(uint32_t val, void *args)
uint8_t *base = loc->first;
base += loc->second;
+ BARRIER();
*(uint32_t *)base = val;
return val;
}
diff --git a/simulator/bcm5719_DEVICE_mmap.cpp b/simulator/bcm5719_DEVICE_mmap.cpp
index 0166258..f1df15e 100644
--- a/simulator/bcm5719_DEVICE_mmap.cpp
+++ b/simulator/bcm5719_DEVICE_mmap.cpp
@@ -46,6 +46,12 @@
#include <utility>
#include <bcm5719_DEVICE.h>
+#ifdef __ppc64__
+#define BARRIER() do { asm volatile ("sync 0\neieio\n" ::: "memory"); } while(0)
+#else
+#define BARRIER() do { asm volatile ("" ::: "memory"); } while(0)
+#endif
+
typedef std::pair<uint8_t *, uint32_t> ram_offset_t;
static uint32_t read_from_ram(uint32_t val, void *args)
@@ -55,6 +61,7 @@ static uint32_t read_from_ram(uint32_t val, void *args)
uint8_t *base = loc->first;
base += loc->second;
+ BARRIER();
return *(uint32_t *)base;
}
@@ -65,6 +72,7 @@ static uint32_t write_to_ram(uint32_t val, void *args)
uint8_t *base = loc->first;
base += loc->second;
+ BARRIER();
*(uint32_t *)base = val;
return val;
}
diff --git a/simulator/bcm5719_GEN_mmap.cpp b/simulator/bcm5719_GEN_mmap.cpp
index 8c694a1..35d67d0 100644
--- a/simulator/bcm5719_GEN_mmap.cpp
+++ b/simulator/bcm5719_GEN_mmap.cpp
@@ -46,6 +46,12 @@
#include <utility>
#include <bcm5719_GEN.h>
+#ifdef __ppc64__
+#define BARRIER() do { asm volatile ("sync 0\neieio\n" ::: "memory"); } while(0)
+#else
+#define BARRIER() do { asm volatile ("" ::: "memory"); } while(0)
+#endif
+
typedef std::pair<uint8_t *, uint32_t> ram_offset_t;
static uint32_t read_from_ram(uint32_t val, void *args)
@@ -55,6 +61,7 @@ static uint32_t read_from_ram(uint32_t val, void *args)
uint8_t *base = loc->first;
base += loc->second;
+ BARRIER();
return *(uint32_t *)base;
}
@@ -65,6 +72,7 @@ static uint32_t write_to_ram(uint32_t val, void *args)
uint8_t *base = loc->first;
base += loc->second;
+ BARRIER();
*(uint32_t *)base = val;
return val;
}
diff --git a/simulator/bcm5719_MII_mmap.cpp b/simulator/bcm5719_MII_mmap.cpp
index 76bd0a3..8a7e5de 100644
--- a/simulator/bcm5719_MII_mmap.cpp
+++ b/simulator/bcm5719_MII_mmap.cpp
@@ -46,6 +46,12 @@
#include <utility>
#include <bcm5719_MII.h>
+#ifdef __ppc64__
+#define BARRIER() do { asm volatile ("sync 0\neieio\n" ::: "memory"); } while(0)
+#else
+#define BARRIER() do { asm volatile ("" ::: "memory"); } while(0)
+#endif
+
typedef std::pair<uint8_t *, uint32_t> ram_offset_t;
static uint32_t read_from_ram(uint32_t val, void *args)
@@ -55,6 +61,7 @@ static uint32_t read_from_ram(uint32_t val, void *args)
uint8_t *base = loc->first;
base += loc->second;
+ BARRIER();
return *(uint32_t *)base;
}
@@ -65,6 +72,7 @@ static uint32_t write_to_ram(uint32_t val, void *args)
uint8_t *base = loc->first;
base += loc->second;
+ BARRIER();
*(uint32_t *)base = val;
return val;
}
diff --git a/simulator/bcm5719_NVM_mmap.cpp b/simulator/bcm5719_NVM_mmap.cpp
index a53d25a..a1c218a 100644
--- a/simulator/bcm5719_NVM_mmap.cpp
+++ b/simulator/bcm5719_NVM_mmap.cpp
@@ -46,6 +46,12 @@
#include <utility>
#include <bcm5719_NVM.h>
+#ifdef __ppc64__
+#define BARRIER() do { asm volatile ("sync 0\neieio\n" ::: "memory"); } while(0)
+#else
+#define BARRIER() do { asm volatile ("" ::: "memory"); } while(0)
+#endif
+
typedef std::pair<uint8_t *, uint32_t> ram_offset_t;
static uint32_t read_from_ram(uint32_t val, void *args)
@@ -55,6 +61,7 @@ static uint32_t read_from_ram(uint32_t val, void *args)
uint8_t *base = loc->first;
base += loc->second;
+ BARRIER();
return *(uint32_t *)base;
}
@@ -65,6 +72,7 @@ static uint32_t write_to_ram(uint32_t val, void *args)
uint8_t *base = loc->first;
base += loc->second;
+ BARRIER();
*(uint32_t *)base = val;
return val;
}
diff --git a/utils/bcmregtool/CMakeLists.txt b/utils/bcmregtool/CMakeLists.txt
index 8ae83fb..d06abcd 100644
--- a/utils/bcmregtool/CMakeLists.txt
+++ b/utils/bcmregtool/CMakeLists.txt
@@ -6,9 +6,7 @@ set(SOURCES
)
simulator_add_executable(${PROJECT_NAME} ${SOURCES})
-target_link_libraries(${PROJECT_NAME} PRIVATE NVRam)
-target_link_libraries(${PROJECT_NAME} PRIVATE VPD)
-
-target_link_libraries(${PROJECT_NAME} PRIVATE simulator)
+target_link_libraries(${PROJECT_NAME} PRIVATE NVRam VPD)
+target_link_libraries(${PROJECT_NAME} PRIVATE simulator OptParse)
INSTALL(TARGETS ${PROJECT_NAME} DESTINATION .)
diff --git a/utils/bcmregtool/main.cpp b/utils/bcmregtool/main.cpp
index 6860de4..30c370b 100644
--- a/utils/bcmregtool/main.cpp
+++ b/utils/bcmregtool/main.cpp
@@ -59,65 +59,260 @@
#include <sys/stat.h>
#include <sys/types.h>
#include <unistd.h>
+#include <OptionParser.h>
+#include <vector>
+#include <string>
+
+#include <bcm5719_GEN.h>
+
+using namespace std;
+using optparse::OptionParser;
+
+const char* regnames[32] = {
+ "$zero", /* Zero register - always 0 */
+ "$at", /* Assembler register */
+ "$v0", "$v1", /* Results */
+ "$a0", "$a1", "$a2", "$a3", /* Aguments */
+ "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7", /* Temp, not saved */
+ "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7", /* Saved registers */
+ "$t8", "$t9", /* Temp, not saved */
+ "$k0", "$k1", /* Kernel / OS */
+ "$gp", "$sp", "$fp", /* Pointers */
+ "$ra", /* return address */
+};
+
+void print_context(void)
+{
+ uint32_t r[32];
+ uint32_t pc;
+ uint32_t opcode;
+
+ // Read out the device context.
+ pc = DEVICE.RxRiscProgramCounter.r32;
+ opcode = DEVICE.RxRiscCurrentInstruction.r32;
+ r[0] = DEVICE.RxRiscRegister0.r32;
+ r[1] = DEVICE.RxRiscRegister1.r32;
+ r[2] = DEVICE.RxRiscRegister2.r32;
+ r[3] = DEVICE.RxRiscRegister3.r32;
+ r[4] = DEVICE.RxRiscRegister4.r32;
+ r[5] = DEVICE.RxRiscRegister5.r32;
+ r[6] = DEVICE.RxRiscRegister6.r32;
+ r[7] = DEVICE.RxRiscRegister7.r32;
+ r[8] = DEVICE.RxRiscRegister8.r32;
+ r[9] = DEVICE.RxRiscRegister9.r32;
+ r[10] = DEVICE.RxRiscRegister10.r32;
+ r[11] = DEVICE.RxRiscRegister11.r32;
+ r[12] = DEVICE.RxRiscRegister12.r32;
+ r[13] = DEVICE.RxRiscRegister13.r32;
+ r[14] = DEVICE.RxRiscRegister14.r32;
+ r[15] = DEVICE.RxRiscRegister15.r32;
+ r[16] = DEVICE.RxRiscRegister16.r32;
+ r[17] = DEVICE.RxRiscRegister17.r32;
+ r[18] = DEVICE.RxRiscRegister18.r32;
+ r[19] = DEVICE.RxRiscRegister19.r32;
+ r[20] = DEVICE.RxRiscRegister20.r32;
+ r[21] = DEVICE.RxRiscRegister21.r32;
+ r[22] = DEVICE.RxRiscRegister22.r32;
+ r[23] = DEVICE.RxRiscRegister23.r32;
+ r[24] = DEVICE.RxRiscRegister24.r32;
+ r[25] = DEVICE.RxRiscRegister25.r32;
+ r[26] = DEVICE.RxRiscRegister26.r32;
+ r[27] = DEVICE.RxRiscRegister27.r32;
+ r[28] = DEVICE.RxRiscRegister28.r32;
+ r[29] = DEVICE.RxRiscRegister29.r32;
+ r[30] = DEVICE.RxRiscRegister30.r32;
+ r[31] = DEVICE.RxRiscRegister31.r32;
+
+ printf("==== Context ===\n");
+ printf(" pc: 0x%08X opcode: 0x%08X\n", pc, opcode);
+ int numCols = 4;
+ int offset = 32 / numCols;
+ for(int i = 0; i < ARRAY_ELEMENTS(r)/4; i++)
+ {
+ for(int j = 0; j < numCols; j++)
+ {
+ printf("%5s: 0x%08X ", regnames[i + j*offset], r[i + j*offset]);
+ }
+ printf("\n");
+ }
+}
int main(int argc, char const *argv[])
{
+ OptionParser parser = OptionParser().description("BCM Register Utility");
+
+
+ parser.add_option("-r", "--reset")
+ .dest("reset")
+ .set_default("0")
+ .action("store_true")
+ .help("Issue a device reset request.");
+
+ parser.add_option("-s", "--step")
+ .dest("step")
+ .set_default("0")
+ .action("store_true")
+ .help("Single step the CPU.");
+
+ parser.add_option("-c", "--context")
+ .dest("context")
+ .set_default("0")
+ .action("store_true")
+ .help("Print the current CPU context.");
+
+ parser.add_option("-g", "--run")
+ .dest("run")
+ .set_default("0")
+ .action("store_true")
+ .help("Continue CPU execution.");
+
+ parser.add_option("-i", "--info")
+ .dest("info")
+ .set_default("0")
+ .action("store_true")
+ .help("Print device information registers.");
+
+
+ optparse::Values options = parser.parse_args(argc, argv);
+ vector<string> args = parser.args();
+
+
initHAL(NULL);
- printf("ChipId: %x\n", (uint32_t)DEVICE.ChipId.r32);
- printf("APEChipId: %x\n", (uint32_t)APE.ChipId.r32);
- // printf("RxRiscMode: %0x\n", DEVICE.RxRiscMode.r32);
- // printf("RxRiscStatus: %0x\n", DEVICE.RxRiscStatus.r32);
- // printf("RxRiscProgramCounter: %0x\n", DEVICE.RxRiscProgramCounter.r32);
- // printf("RxRiscRegister0: %0x\n", DEVICE.RxRiscRegister0.r32);
- // printf("RxRiscRegister1: %0x\n", DEVICE.RxRiscRegister1.r32);
- // printf("RxRiscRegister2: %0x\n", DEVICE.RxRiscRegister2.r32);
- // printf("RxRiscRegister3: %0x\n", DEVICE.RxRiscRegister3.r32);
- DEVICE.LinkStatusControl.r32 = 0xffffffff;
- printf("LinkStatusControl.NegotiatedLinkSpeed: %0x\n",
- (uint32_t)DEVICE.LinkStatusControl.bits.NegotiatedLinkSpeed);
- printf("LinkStatusControl.NegotiatedLinkWidth: %0x\n",
- (uint32_t)DEVICE.LinkStatusControl.bits.NegotiatedLinkWidth);
- printf("LinkStatusControl.r32: %0x\n",
- (uint32_t)DEVICE.LinkStatusControl.r32);
-
- DEVICE.LinkStatusControl.bits.NegotiatedLinkSpeed = 0;
- printf("LinkStatusControl.NegotiatedLinkSpeed: %0x\n",
- (uint32_t)DEVICE.LinkStatusControl.bits.NegotiatedLinkSpeed);
- printf("LinkStatusControl.NegotiatedLinkWidth: %0x\n",
- (uint32_t)DEVICE.LinkStatusControl.bits.NegotiatedLinkWidth);
- printf("LinkStatusControl.r32: %0x\n",
- (uint32_t)DEVICE.LinkStatusControl.r32);
+ if(options.get("reset"))
+ {
+ cout << "Resetting...\n";
+ RegDEVICERxRiscMode_t mode;
+ mode.r32 = 0;
+ mode.bits.Reset = 1;
+ DEVICE.RxRiscMode = mode;
+ exit(0);
+ }
- printf("EmacMode.PortMode: %0x\n", (uint32_t)DEVICE.EmacMode.bits.PortMode);
- printf("EmacMacAddresses0High: %0x\n",
- (uint32_t)DEVICE.EmacMacAddresses0High.r32);
- printf("EmacMacAddresses0Low: %0x\n",
- (uint32_t)DEVICE.EmacMacAddresses0Low.r32);
- printf("RxRiscMode: %0x\n", (uint32_t)DEVICE.RxRiscMode.r32);
+ if(options.get("step"))
+ {
+ cout << "Stepping...\n";
+ RegDEVICERxRiscMode_t mode;
+ mode.r32 = 0;
+ mode.bits.SingleStep = 1;
+ mode.bits.Halt = 1;
+ DEVICE.RxRiscMode = mode;
- // printf("HostDriverId: %0x\n", APE.HostDriverId.r32);
- // printf("RcpuPciSubsystemId: %0x\n", APE.RcpuPciSubsystemId.r32);
+ print_context();
+ exit(0);
+ }
+
+ if(options.get("context"))
+ {
+ print_context();
+ exit(0);
+ }
+
+ if(options.get("run"))
+ {
+ cout << "Running...\n";
+ RegDEVICERxRiscMode_t mode;
+ mode.r32 = 0; // Ensure single-step and halt are cleared
+ DEVICE.RxRiscMode = mode;
+ exit(0);
+ }
+
+
+ if(options.get("info"))
+ {
+ printf("Firmware Ver: 0x%08X\n", (uint32_t)GEN.GenFwVersion.r32);
+ printf("Chip Id: 0x%08X\n", (uint32_t)DEVICE.ChipId.r32);
+ printf("Vendor ID: 0x%08X\n", (uint32_t)DEVICE.PciVendorDeviceId.r32);
+ printf("Subsystem ID: 0x%08X\n", (uint32_t)DEVICE.PciSubsystemId.r32);
+ printf("Class Code Rev: 0x%08X\n", (uint32_t)DEVICE.PciClassCodeRevision.r32);
+ printf("Function En: 0x%X\n", (uint32_t)DEVICE.Status.bits.FunctionEnable);
+ printf("Function Num: %d\n", (uint32_t)DEVICE.Status.bits.FunctionNumber);
- // printf("\n\n=========\n\n");
- printf("Grab lock...\n");
- NVRam_acquireLock();
+ // GenCfgFeature
+ // GenCfgHw
+ // GenCfgShared
+ // GenCfgHw2
+ // GenCfg5
- NVRam_enable();
+ printf("\n");
- uint32_t length = NVRam_readWord(8); // current stage length
- uint32_t offset = NVRam_readWord(0xc); // current stage offset
- printf("NVRam_read(8) = %x\n", length);
- printf("NVRam_read(C) = %x\n", offset);
- // uint32_t next_stage_hdr = offset + (length*4);
- // uint32_t next_stage_size = next_stage_hdr + 4;
- // printf("NVRam_read(%x) = %x\n", next_stage_hdr,
- // NVRam_readWord(next_stage_hdr)); printf("NVRam_read(%x) = %x\n",
- // next_stage_size, NVRam_readWord(next_stage_size));
+ uint64_t serial = (((uint64_t)(DEVICE.PciSerialNumberHigh.r32)) << 32) | DEVICE.PciSerialNumberLow.r32;
+ printf("Serial Number: 0x%016lX\n", serial);
+
+ printf("\n");
+
+ printf("Power Budget[0]: 0x%08X\n", (uint32_t)DEVICE.PciPowerBudget0.r32);
+ printf("Power Budget[1]: 0x%08X\n", (uint32_t)DEVICE.PciPowerBudget1.r32);
+ printf("Power Budget[2]: 0x%08X\n", (uint32_t)DEVICE.PciPowerBudget2.r32);
+ printf("Power Budget[3]: 0x%08X\n", (uint32_t)DEVICE.PciPowerBudget3.r32);
+ printf("Power Budget[4]: 0x%08X\n", (uint32_t)DEVICE.PciPowerBudget4.r32);
+ printf("Power Budget[5]: 0x%08X\n", (uint32_t)DEVICE.PciPowerBudget5.r32);
+ printf("Power Budget[6]: 0x%08X\n", (uint32_t)DEVICE.PciPowerBudget6.r32);
+ printf("Power Budget[7]: 0x%08X\n", (uint32_t)DEVICE.PciPowerBudget7.r32);
+
+ printf("\n");
+
+ uint64_t mac0 = (((uint64_t)(DEVICE.EmacMacAddresses0High.r32)) << 32) | DEVICE.EmacMacAddresses0Low.r32;
+ uint64_t mac1 = (((uint64_t)(DEVICE.EmacMacAddresses1High.r32)) << 32) | DEVICE.EmacMacAddresses1Low.r32;
+ uint64_t mac2 = (((uint64_t)(DEVICE.EmacMacAddresses2High.r32)) << 32) | DEVICE.EmacMacAddresses2Low.r32;
+ uint64_t mac3 = (((uint64_t)(DEVICE.EmacMacAddresses3High.r32)) << 32) | DEVICE.EmacMacAddresses3Low.r32;
+ printf("MAC0: 0x%012lX\n", mac0);
+ printf("MAC1: 0x%012lX\n", mac1);
+ printf("MAC2: 0x%012lX\n", mac2);
+ printf("MAC3: 0x%012lX\n", mac3);
+
+ printf("\n");
+
+ // RegDEVICEStatus_t
+
+
+ // RegDEVICEFastBootProgramCounter_t
+ // RegDEVICEExpansionRomAddr_t
+
+ // RegDEVICEMiscellaneousLocalControl_t
+ // RegDEVICETimer_t
+
+ // RegDEVICEEmacMode_t
+ // RegDEVICELedControl_t
+
+ // RegDEVICEPciPowerConsumptionInfo_t
+ // RegDEVICEPciPowerDissipatedInfo_t
+
+ // RegDEVICEMtuSize_t
+
+ // RegDEVICEReceiveMacMode_t
+
+ // RegDEVICELinkAwarePowerModeClockPolicy_t
+ // RegDEVICEClockSpeedOverridePolicy_t
+ // RegDEVICEClockStatus_t
+ // RegDEVICETopLevelMiscellaneousControl1_t
+
+ // RegDEVICEMemoryArbiterMode_t
+
+ printf("Reg 6408: 0x%08X\n", (uint32_t)DEVICE._6408.r32);
+ printf("Reg 64c0: 0x%08X\n", (uint32_t)DEVICE._64c0.r32);
+ printf("Reg 64c8: 0x%08X\n", (uint32_t)DEVICE._64c8.r32);
+ printf("Reg 64dc: 0x%08X\n", (uint32_t)DEVICE._64dc.r32);
+ printf("Reg 6530: 0x%08X\n", (uint32_t)DEVICE._6530.r32);
+ printf("Reg 6550: 0x%08X\n", (uint32_t)DEVICE._6550.r32);
+ printf("Reg 65f4: 0x%08X\n", (uint32_t)DEVICE._65f4.r32);
+ printf("Reg 7c04: 0x%08X\n", (uint32_t)DEVICE._7c04.r32);
+
+ exit(0);
+ }
+
+
+ printf("APEChipId: %x\n", (uint32_t)APE.ChipId.r32);
+
+ printf("EmacMode.PortMode: %0x\n", (uint32_t)DEVICE.EmacMode.bits.PortMode);
+ printf("RxRiscMode: %0x\n", (uint32_t)DEVICE.RxRiscMode.r32);
+
+ // printf("HostDriverId: %0x\n", APE.HostDriverId.r32);
+ // printf("RcpuPciSubsystemId: %0x\n", APE.RcpuPciSubsystemId.r32);
- NVRam_releaseLock();
+ print_context();
return 0;
}
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