Regenerate headers + simulation code to allow arbitrary read/writes from the base component.

6 files changed, 150 insertions, 0 deletions

diff --git a/simulator/bcm5719_APE_mmap.cpp b/simulator/bcm5719_APE_mmap.cpp
index 6b035a5..4fec604 100644
--- a/simulator/bcm5719_APE_mmap.cpp
+++ b/simulator/bcm5719_APE_mmap.cpp
@@ -65,6 +65,15 @@ static uint32_t read_from_ram(uint32_t val, void *args)
     return *(uint32_t *)base;
 }
 
+static uint32_t read_from_ram_index(uint32_t index, void *args)
+{
+    uint8_t *base = (uint8_t *)args;
+    base += index;
+
+    BARRIER();
+    return *(uint32_t *)base;
+}
+
 static uint32_t write_to_ram(uint32_t val, void *args)
 {
     ram_offset_t *loc = (ram_offset_t *)args;
@@ -78,8 +87,24 @@ static uint32_t write_to_ram(uint32_t val, void *args)
     return val;
 }
 
+static void write_to_ram_index(uint32_t index, uint32_t val, void *args)
+{
+    uint8_t *base = (uint8_t *)args;
+    base += index;
+
+    BARRIER();
+    *(uint32_t *)base = val;
+    BARRIER();
+}
+
 void init_bcm5719_APE_mmap(void *base)
 {
+    APE.mIndexReadCallback = read_from_ram_index;
+    APE.mIndexReadCallbackArgs = base;
+
+    APE.mIndexWriteCallback = write_to_ram_index;
+    APE.mIndexWriteCallbackArgs = base;
+
     /** @brief Component Registers for @ref APE. */
     /** @brief Bitmap for @ref APE_t.Mode. */
     static ram_offset_t APE_Mode_r32((uint8_t *)base, (uint32_t)0);
diff --git a/simulator/bcm5719_DEVICE_mmap.cpp b/simulator/bcm5719_DEVICE_mmap.cpp
index 501e2ad..20932a4 100644
--- a/simulator/bcm5719_DEVICE_mmap.cpp
+++ b/simulator/bcm5719_DEVICE_mmap.cpp
@@ -65,6 +65,15 @@ static uint32_t read_from_ram(uint32_t val, void *args)
     return *(uint32_t *)base;
 }
 
+static uint32_t read_from_ram_index(uint32_t index, void *args)
+{
+    uint8_t *base = (uint8_t *)args;
+    base += index;
+
+    BARRIER();
+    return *(uint32_t *)base;
+}
+
 static uint32_t write_to_ram(uint32_t val, void *args)
 {
     ram_offset_t *loc = (ram_offset_t *)args;
@@ -78,8 +87,24 @@ static uint32_t write_to_ram(uint32_t val, void *args)
     return val;
 }
 
+static void write_to_ram_index(uint32_t index, uint32_t val, void *args)
+{
+    uint8_t *base = (uint8_t *)args;
+    base += index;
+
+    BARRIER();
+    *(uint32_t *)base = val;
+    BARRIER();
+}
+
 void init_bcm5719_DEVICE_mmap(void *base)
 {
+    DEVICE.mIndexReadCallback = read_from_ram_index;
+    DEVICE.mIndexReadCallbackArgs = base;
+
+    DEVICE.mIndexWriteCallback = write_to_ram_index;
+    DEVICE.mIndexWriteCallbackArgs = base;
+
     /** @brief Component Registers for @ref DEVICE. */
     /** @brief Bitmap for @ref DEVICE_t.MiscellaneousHostControl. */
     static ram_offset_t DEVICE_MiscellaneousHostControl_r32((uint8_t *)base, (uint32_t)104);
diff --git a/simulator/bcm5719_GEN_mmap.cpp b/simulator/bcm5719_GEN_mmap.cpp
index 0595d87..23d8b86 100644
--- a/simulator/bcm5719_GEN_mmap.cpp
+++ b/simulator/bcm5719_GEN_mmap.cpp
@@ -65,6 +65,15 @@ static uint32_t read_from_ram(uint32_t val, void *args)
     return *(uint32_t *)base;
 }
 
+static uint32_t read_from_ram_index(uint32_t index, void *args)
+{
+    uint8_t *base = (uint8_t *)args;
+    base += index;
+
+    BARRIER();
+    return *(uint32_t *)base;
+}
+
 static uint32_t write_to_ram(uint32_t val, void *args)
 {
     ram_offset_t *loc = (ram_offset_t *)args;
@@ -78,8 +87,24 @@ static uint32_t write_to_ram(uint32_t val, void *args)
     return val;
 }
 
+static void write_to_ram_index(uint32_t index, uint32_t val, void *args)
+{
+    uint8_t *base = (uint8_t *)args;
+    base += index;
+
+    BARRIER();
+    *(uint32_t *)base = val;
+    BARRIER();
+}
+
 void init_bcm5719_GEN_mmap(void *base)
 {
+    GEN.mIndexReadCallback = read_from_ram_index;
+    GEN.mIndexReadCallbackArgs = base;
+
+    GEN.mIndexWriteCallback = write_to_ram_index;
+    GEN.mIndexWriteCallbackArgs = base;
+
     /** @brief Component Registers for @ref GEN. */
     /** @brief Bitmap for @ref GEN_t.GenFwMbox. */
     static ram_offset_t GEN_GenFwMbox_r32((uint8_t *)base, (uint32_t)0);
diff --git a/simulator/bcm5719_MII_mmap.cpp b/simulator/bcm5719_MII_mmap.cpp
index 36b7712..f0d7044 100644
--- a/simulator/bcm5719_MII_mmap.cpp
+++ b/simulator/bcm5719_MII_mmap.cpp
@@ -65,6 +65,15 @@ static uint32_t read_from_ram(uint32_t val, void *args)
     return *(uint32_t *)base;
 }
 
+static uint32_t read_from_ram_index(uint32_t index, void *args)
+{
+    uint8_t *base = (uint8_t *)args;
+    base += index;
+
+    BARRIER();
+    return *(uint32_t *)base;
+}
+
 static uint32_t write_to_ram(uint32_t val, void *args)
 {
     ram_offset_t *loc = (ram_offset_t *)args;
@@ -78,8 +87,24 @@ static uint32_t write_to_ram(uint32_t val, void *args)
     return val;
 }
 
+static void write_to_ram_index(uint32_t index, uint32_t val, void *args)
+{
+    uint8_t *base = (uint8_t *)args;
+    base += index;
+
+    BARRIER();
+    *(uint32_t *)base = val;
+    BARRIER();
+}
+
 void init_bcm5719_MII_mmap(void *base)
 {
+    MII.mIndexReadCallback = read_from_ram_index;
+    MII.mIndexReadCallbackArgs = base;
+
+    MII.mIndexWriteCallback = write_to_ram_index;
+    MII.mIndexWriteCallbackArgs = base;
+
     /** @brief Component Registers for @ref MII. */
     /** @brief Bitmap for @ref MII_t.Control. */
     static ram_offset_t MII_Control_r16((uint8_t *)base, (uint32_t)0);
diff --git a/simulator/bcm5719_NVM_mmap.cpp b/simulator/bcm5719_NVM_mmap.cpp
index 024d180..d0b9257 100644
--- a/simulator/bcm5719_NVM_mmap.cpp
+++ b/simulator/bcm5719_NVM_mmap.cpp
@@ -65,6 +65,15 @@ static uint32_t read_from_ram(uint32_t val, void *args)
     return *(uint32_t *)base;
 }
 
+static uint32_t read_from_ram_index(uint32_t index, void *args)
+{
+    uint8_t *base = (uint8_t *)args;
+    base += index;
+
+    BARRIER();
+    return *(uint32_t *)base;
+}
+
 static uint32_t write_to_ram(uint32_t val, void *args)
 {
     ram_offset_t *loc = (ram_offset_t *)args;
@@ -78,8 +87,24 @@ static uint32_t write_to_ram(uint32_t val, void *args)
     return val;
 }
 
+static void write_to_ram_index(uint32_t index, uint32_t val, void *args)
+{
+    uint8_t *base = (uint8_t *)args;
+    base += index;
+
+    BARRIER();
+    *(uint32_t *)base = val;
+    BARRIER();
+}
+
 void init_bcm5719_NVM_mmap(void *base)
 {
+    NVM.mIndexReadCallback = read_from_ram_index;
+    NVM.mIndexReadCallbackArgs = base;
+
+    NVM.mIndexWriteCallback = write_to_ram_index;
+    NVM.mIndexWriteCallbackArgs = base;
+
     /** @brief Component Registers for @ref NVM. */
     /** @brief Bitmap for @ref NVM_t.Command. */
     static ram_offset_t NVM_Command_r32((uint8_t *)base, (uint32_t)0);
diff --git a/simulator/bcm5719_SHM_mmap.cpp b/simulator/bcm5719_SHM_mmap.cpp
index 751e26b..bdcea46 100644
--- a/simulator/bcm5719_SHM_mmap.cpp
+++ b/simulator/bcm5719_SHM_mmap.cpp
@@ -65,6 +65,15 @@ static uint32_t read_from_ram(uint32_t val, void *args)
     return *(uint32_t *)base;
 }
 
+static uint32_t read_from_ram_index(uint32_t index, void *args)
+{
+    uint8_t *base = (uint8_t *)args;
+    base += index;
+
+    BARRIER();
+    return *(uint32_t *)base;
+}
+
 static uint32_t write_to_ram(uint32_t val, void *args)
 {
     ram_offset_t *loc = (ram_offset_t *)args;
@@ -78,8 +87,24 @@ static uint32_t write_to_ram(uint32_t val, void *args)
     return val;
 }
 
+static void write_to_ram_index(uint32_t index, uint32_t val, void *args)
+{
+    uint8_t *base = (uint8_t *)args;
+    base += index;
+
+    BARRIER();
+    *(uint32_t *)base = val;
+    BARRIER();
+}
+
 void init_bcm5719_SHM_mmap(void *base)
 {
+    SHM.mIndexReadCallback = read_from_ram_index;
+    SHM.mIndexReadCallbackArgs = base;
+
+    SHM.mIndexWriteCallback = write_to_ram_index;
+    SHM.mIndexWriteCallbackArgs = base;
+
     /** @brief Component Registers for @ref SHM. */
     /** @brief Bitmap for @ref SHM_t.SegSig. */
     static ram_offset_t SHM_SegSig_r32((uint8_t *)base, (uint32_t)0);