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| author | Lojewski, Evan <github@meklort.com> | 2019-05-11 08:31:30 -0600 |
|---|---|---|
| committer | Lojewski, Evan <github@meklort.com> | 2019-05-11 08:31:30 -0600 |
| commit | bc89c73168282c7de5eaa1ae836f3c1bd3c3fc5e (patch) | |
| tree | 9366e0e7464eda2a35e3bc5a39b1d3f8edf9a6f4 | |
| parent | a7c487b03ac7fed1f6d1ac87363feb7c5bd18484 (diff) | |
| download | bcm5719-ortega-bc89c73168282c7de5eaa1ae836f3c1bd3c3fc5e.tar.gz bcm5719-ortega-bc89c73168282c7de5eaa1ae836f3c1bd3c3fc5e.zip | |
Update register generation to use type identifieres for port0 - 3.
32 files changed, 256 insertions, 10555 deletions
diff --git a/include/APE_APE.h b/include/APE_APE.h index b1e4238..9c83870 100644 --- a/include/APE_APE.h +++ b/include/APE_APE.h @@ -539,7 +539,7 @@ typedef register_container RegAPEEvent_t { #define SET_APE_RXBUFOFFSET_FUNC0_FINISHED(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref APE_t.RxbufoffsetFunc0. */ -typedef register_container RegAPERxbufoffsetFunc0_t { +typedef register_container RegAPERxbufoffset_t { /** @brief 32bit direct register access. */ APE_APE_H_uint32_t r32; @@ -585,7 +585,7 @@ typedef register_container RegAPERxbufoffsetFunc0_t { /** @brief Print register value. */ void print(void) { r32.print(); } - RegAPERxbufoffsetFunc0_t() + RegAPERxbufoffset_t() { /** @brief constructor for @ref APE_t.RxbufoffsetFunc0. */ r32.setName("RxbufoffsetFunc0"); @@ -604,112 +604,15 @@ typedef register_container RegAPERxbufoffsetFunc0_t { bits.Finished.setBaseRegister(&r32); bits.Finished.setName("Finished"); } - RegAPERxbufoffsetFunc0_t& operator=(const RegAPERxbufoffsetFunc0_t& other) + RegAPERxbufoffset_t& operator=(const RegAPERxbufoffset_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ -} RegAPERxbufoffsetFunc0_t; +} RegAPERxbufoffset_t; #define REG_APE_RXBUFOFFSET_FUNC1 ((volatile APE_APE_H_uint32_t*)0x60200018) /* This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. */ -#define APE_RXBUFOFFSET_FUNC1_TAIL_SHIFT 0u -#define APE_RXBUFOFFSET_FUNC1_TAIL_MASK 0xfffu -#define GET_APE_RXBUFOFFSET_FUNC1_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_RXBUFOFFSET_FUNC1_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_RXBUFOFFSET_FUNC1_HEAD_SHIFT 12u -#define APE_RXBUFOFFSET_FUNC1_HEAD_MASK 0xfff000u -#define GET_APE_RXBUFOFFSET_FUNC1_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_RXBUFOFFSET_FUNC1_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_RXBUFOFFSET_FUNC1_TO_HOST_SHIFT 24u -#define APE_RXBUFOFFSET_FUNC1_TO_HOST_MASK 0x1000000u -#define GET_APE_RXBUFOFFSET_FUNC1_TO_HOST(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_APE_RXBUFOFFSET_FUNC1_TO_HOST(__val__) (((__val__) << 24u) & 0x1000000u) -#define APE_RXBUFOFFSET_FUNC1_IP_FRAG_SHIFT 25u -#define APE_RXBUFOFFSET_FUNC1_IP_FRAG_MASK 0x2000000u -#define GET_APE_RXBUFOFFSET_FUNC1_IP_FRAG(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_APE_RXBUFOFFSET_FUNC1_IP_FRAG(__val__) (((__val__) << 25u) & 0x2000000u) -#define APE_RXBUFOFFSET_FUNC1_COUNT_SHIFT 26u -#define APE_RXBUFOFFSET_FUNC1_COUNT_MASK 0x3c000000u -#define GET_APE_RXBUFOFFSET_FUNC1_COUNT(__reg__) (((__reg__) & 0x3c000000) >> 26u) -#define SET_APE_RXBUFOFFSET_FUNC1_COUNT(__val__) (((__val__) << 26u) & 0x3c000000u) -#define APE_RXBUFOFFSET_FUNC1_VALID_SHIFT 30u -#define APE_RXBUFOFFSET_FUNC1_VALID_MASK 0x40000000u -#define GET_APE_RXBUFOFFSET_FUNC1_VALID(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_APE_RXBUFOFFSET_FUNC1_VALID(__val__) (((__val__) << 30u) & 0x40000000u) - -/** @brief Register definition for @ref APE_t.RxbufoffsetFunc1. */ -typedef register_container RegAPERxbufoffsetFunc1_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, ToHost, 24, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, IPFrag, 25, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 26, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Valid, 30, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Valid, 30, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 26, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, IPFrag, 25, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, ToHost, 24, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxbufoffsetFunc1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxbufoffsetFunc1_t() - { - /** @brief constructor for @ref APE_t.RxbufoffsetFunc1. */ - r32.setName("RxbufoffsetFunc1"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.ToHost.setBaseRegister(&r32); - bits.ToHost.setName("ToHost"); - bits.IPFrag.setBaseRegister(&r32); - bits.IPFrag.setName("IPFrag"); - bits.Count.setBaseRegister(&r32); - bits.Count.setName("Count"); - bits.Valid.setBaseRegister(&r32); - bits.Valid.setName("Valid"); - } - RegAPERxbufoffsetFunc1_t& operator=(const RegAPERxbufoffsetFunc1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxbufoffsetFunc1_t; - #define REG_APE_TX_TO_NET_DOORBELL_FUNC0 ((volatile APE_APE_H_uint32_t*)0x6020001c) /* Written on APE TX to network after filling 0xA002 buffer with packet. */ #define APE_TX_TO_NET_DOORBELL_FUNC0_TAIL_SHIFT 0u #define APE_TX_TO_NET_DOORBELL_FUNC0_TAIL_MASK 0xfffu @@ -729,7 +632,7 @@ typedef register_container RegAPERxbufoffsetFunc1_t { #define SET_APE_TX_TO_NET_DOORBELL_FUNC0_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) /** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc0. */ -typedef register_container RegAPETxToNetDoorbellFunc0_t { +typedef register_container RegAPETxToNetDoorbell_t { /** @brief 32bit direct register access. */ APE_APE_H_uint32_t r32; @@ -767,7 +670,7 @@ typedef register_container RegAPETxToNetDoorbellFunc0_t { /** @brief Print register value. */ void print(void) { r32.print(); } - RegAPETxToNetDoorbellFunc0_t() + RegAPETxToNetDoorbell_t() { /** @brief constructor for @ref APE_t.TxToNetDoorbellFunc0. */ r32.setName("TxToNetDoorbellFunc0"); @@ -780,13 +683,13 @@ typedef register_container RegAPETxToNetDoorbellFunc0_t { bits.TXQueueFull.setBaseRegister(&r32); bits.TXQueueFull.setName("TXQueueFull"); } - RegAPETxToNetDoorbellFunc0_t& operator=(const RegAPETxToNetDoorbellFunc0_t& other) + RegAPETxToNetDoorbell_t& operator=(const RegAPETxToNetDoorbell_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ -} RegAPETxToNetDoorbellFunc0_t; +} RegAPETxToNetDoorbell_t; #define REG_APE_TX_STATE0 ((volatile APE_APE_H_uint32_t*)0x60200020) /* APE TX Status. */ #define APE_TX_STATE0_TAIL_SHIFT 0u @@ -972,7 +875,7 @@ typedef register_container RegAPELockGrantObsolete_t { #define SET_APE_RX_POOL_MODE_STATUS_0_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) /** @brief Register definition for @ref APE_t.RxPoolModeStatus0. */ -typedef register_container RegAPERxPoolModeStatus0_t { +typedef register_container RegAPERxPoolModeStatus_t { /** @brief 32bit direct register access. */ APE_APE_H_uint32_t r32; @@ -1030,7 +933,7 @@ typedef register_container RegAPERxPoolModeStatus0_t { /** @brief Print register value. */ void print(void) { r32.print(); } - RegAPERxPoolModeStatus0_t() + RegAPERxPoolModeStatus_t() { /** @brief constructor for @ref APE_t.RxPoolModeStatus0. */ r32.setName("RxPoolModeStatus0"); @@ -1049,130 +952,15 @@ typedef register_container RegAPERxPoolModeStatus0_t { bits.FullCount.setBaseRegister(&r32); bits.FullCount.setName("FullCount"); } - RegAPERxPoolModeStatus0_t& operator=(const RegAPERxPoolModeStatus0_t& other) + RegAPERxPoolModeStatus_t& operator=(const RegAPERxPoolModeStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ -} RegAPERxPoolModeStatus0_t; +} RegAPERxPoolModeStatus_t; #define REG_APE_RX_POOL_MODE_STATUS_1 ((volatile APE_APE_H_uint32_t*)0x6020007c) /* */ -#define APE_RX_POOL_MODE_STATUS_1_HALT_SHIFT 0u -#define APE_RX_POOL_MODE_STATUS_1_HALT_MASK 0x1u -#define GET_APE_RX_POOL_MODE_STATUS_1_HALT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_RX_POOL_MODE_STATUS_1_HALT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_RX_POOL_MODE_STATUS_1_HALT_DONE_SHIFT 1u -#define APE_RX_POOL_MODE_STATUS_1_HALT_DONE_MASK 0x2u -#define GET_APE_RX_POOL_MODE_STATUS_1_HALT_DONE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_RX_POOL_MODE_STATUS_1_HALT_DONE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_RX_POOL_MODE_STATUS_1_ENABLE_SHIFT 2u -#define APE_RX_POOL_MODE_STATUS_1_ENABLE_MASK 0x4u -#define GET_APE_RX_POOL_MODE_STATUS_1_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_RX_POOL_MODE_STATUS_1_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_RX_POOL_MODE_STATUS_1_EMPTY_SHIFT 4u -#define APE_RX_POOL_MODE_STATUS_1_EMPTY_MASK 0x10u -#define GET_APE_RX_POOL_MODE_STATUS_1_EMPTY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_RX_POOL_MODE_STATUS_1_EMPTY(__val__) (((__val__) << 4u) & 0x10u) -#define APE_RX_POOL_MODE_STATUS_1_ERROR_SHIFT 5u -#define APE_RX_POOL_MODE_STATUS_1_ERROR_MASK 0x20u -#define GET_APE_RX_POOL_MODE_STATUS_1_ERROR(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_RX_POOL_MODE_STATUS_1_ERROR(__val__) (((__val__) << 5u) & 0x20u) -#define APE_RX_POOL_MODE_STATUS_1_RESET_SHIFT 6u -#define APE_RX_POOL_MODE_STATUS_1_RESET_MASK 0x40u -#define GET_APE_RX_POOL_MODE_STATUS_1_RESET(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_RX_POOL_MODE_STATUS_1_RESET(__val__) (((__val__) << 6u) & 0x40u) -#define APE_RX_POOL_MODE_STATUS_1_FULL_COUNT_SHIFT 8u -#define APE_RX_POOL_MODE_STATUS_1_FULL_COUNT_MASK 0xffff00u -#define GET_APE_RX_POOL_MODE_STATUS_1_FULL_COUNT(__reg__) (((__reg__) & 0xffff00) >> 8u) -#define SET_APE_RX_POOL_MODE_STATUS_1_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) - -/** @brief Register definition for @ref APE_t.RxPoolModeStatus1. */ -typedef register_container RegAPERxPoolModeStatus1_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Halt, 0, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Enable, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Empty, 4, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Reset, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_24, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_24, 24, 8) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Reset, 6, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Empty, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Enable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Halt, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxPoolModeStatus1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxPoolModeStatus1_t() - { - /** @brief constructor for @ref APE_t.RxPoolModeStatus1. */ - r32.setName("RxPoolModeStatus1"); - bits.Halt.setBaseRegister(&r32); - bits.Halt.setName("Halt"); - bits.HaltDone.setBaseRegister(&r32); - bits.HaltDone.setName("HaltDone"); - bits.Enable.setBaseRegister(&r32); - bits.Enable.setName("Enable"); - bits.Empty.setBaseRegister(&r32); - bits.Empty.setName("Empty"); - bits.Error.setBaseRegister(&r32); - bits.Error.setName("Error"); - bits.Reset.setBaseRegister(&r32); - bits.Reset.setName("Reset"); - bits.FullCount.setBaseRegister(&r32); - bits.FullCount.setName("FullCount"); - } - RegAPERxPoolModeStatus1_t& operator=(const RegAPERxPoolModeStatus1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxPoolModeStatus1_t; - #define REG_APE_RX_POOL_RETIRE_0 ((volatile APE_APE_H_uint32_t*)0x60200080) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ #define APE_RX_POOL_RETIRE_0_TAIL_SHIFT 0u #define APE_RX_POOL_RETIRE_0_TAIL_MASK 0xfffu @@ -1190,10 +978,10 @@ typedef register_container RegAPERxPoolModeStatus1_t { #define APE_RX_POOL_RETIRE_0_STATE_MASK 0x6000000u #define GET_APE_RX_POOL_RETIRE_0_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) #define SET_APE_RX_POOL_RETIRE_0_STATE(__val__) (((__val__) << 25u) & 0x6000000u) -#define APE_RX_POOL_RETIRE_0_STATE_PROCESSING 0x0u -#define APE_RX_POOL_RETIRE_0_STATE_RETIRED_OK 0x1u -#define APE_RX_POOL_RETIRE_0_STATE_ERROR__FULL 0x2u -#define APE_RX_POOL_RETIRE_0_STATE_ERROR__IN_HALT 0x3u +#define APE_RX_POOL_RETIRE_STATE_PROCESSING 0x0u +#define APE_RX_POOL_RETIRE_STATE_RETIRED_OK 0x1u +#define APE_RX_POOL_RETIRE_STATE_ERROR__FULL 0x2u +#define APE_RX_POOL_RETIRE_STATE_ERROR__IN_HALT 0x3u #define APE_RX_POOL_RETIRE_0_COUNT_SHIFT 27u #define APE_RX_POOL_RETIRE_0_COUNT_MASK 0x78000000u @@ -1201,7 +989,7 @@ typedef register_container RegAPERxPoolModeStatus1_t { #define SET_APE_RX_POOL_RETIRE_0_COUNT(__val__) (((__val__) << 27u) & 0x78000000u) /** @brief Register definition for @ref APE_t.RxPoolRetire0. */ -typedef register_container RegAPERxPoolRetire0_t { +typedef register_container RegAPERxPoolRetire_t { /** @brief 32bit direct register access. */ APE_APE_H_uint32_t r32; @@ -1243,7 +1031,7 @@ typedef register_container RegAPERxPoolRetire0_t { /** @brief Print register value. */ void print(void) { r32.print(); } - RegAPERxPoolRetire0_t() + RegAPERxPoolRetire_t() { /** @brief constructor for @ref APE_t.RxPoolRetire0. */ r32.setName("RxPoolRetire0"); @@ -1258,107 +1046,15 @@ typedef register_container RegAPERxPoolRetire0_t { bits.Count.setBaseRegister(&r32); bits.Count.setName("Count"); } - RegAPERxPoolRetire0_t& operator=(const RegAPERxPoolRetire0_t& other) + RegAPERxPoolRetire_t& operator=(const RegAPERxPoolRetire_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ -} RegAPERxPoolRetire0_t; +} RegAPERxPoolRetire_t; #define REG_APE_RX_POOL_RETIRE_1 ((volatile APE_APE_H_uint32_t*)0x60200088) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ -#define APE_RX_POOL_RETIRE_1_TAIL_SHIFT 0u -#define APE_RX_POOL_RETIRE_1_TAIL_MASK 0xfffu -#define GET_APE_RX_POOL_RETIRE_1_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_RX_POOL_RETIRE_1_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_RX_POOL_RETIRE_1_HEAD_SHIFT 12u -#define APE_RX_POOL_RETIRE_1_HEAD_MASK 0xfff000u -#define GET_APE_RX_POOL_RETIRE_1_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_RX_POOL_RETIRE_1_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_RX_POOL_RETIRE_1_RETIRE_SHIFT 24u -#define APE_RX_POOL_RETIRE_1_RETIRE_MASK 0x1000000u -#define GET_APE_RX_POOL_RETIRE_1_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_APE_RX_POOL_RETIRE_1_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) -#define APE_RX_POOL_RETIRE_1_STATE_SHIFT 25u -#define APE_RX_POOL_RETIRE_1_STATE_MASK 0x6000000u -#define GET_APE_RX_POOL_RETIRE_1_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) -#define SET_APE_RX_POOL_RETIRE_1_STATE(__val__) (((__val__) << 25u) & 0x6000000u) -#define APE_RX_POOL_RETIRE_1_STATE_PROCESSING 0x0u -#define APE_RX_POOL_RETIRE_1_STATE_RETIRED_OK 0x1u -#define APE_RX_POOL_RETIRE_1_STATE_ERROR__FULL 0x2u -#define APE_RX_POOL_RETIRE_1_STATE_ERROR__IN_HALT 0x3u - -#define APE_RX_POOL_RETIRE_1_COUNT_SHIFT 27u -#define APE_RX_POOL_RETIRE_1_COUNT_MASK 0x78000000u -#define GET_APE_RX_POOL_RETIRE_1_COUNT(__reg__) (((__reg__) & 0x78000000) >> 27u) -#define SET_APE_RX_POOL_RETIRE_1_COUNT(__val__) (((__val__) << 27u) & 0x78000000u) - -/** @brief Register definition for @ref APE_t.RxPoolRetire1. */ -typedef register_container RegAPERxPoolRetire1_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 27, 4) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 27, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxPoolRetire1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxPoolRetire1_t() - { - /** @brief constructor for @ref APE_t.RxPoolRetire1. */ - r32.setName("RxPoolRetire1"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.Retire.setBaseRegister(&r32); - bits.Retire.setName("Retire"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - bits.Count.setBaseRegister(&r32); - bits.Count.setName("Count"); - } - RegAPERxPoolRetire1_t& operator=(const RegAPERxPoolRetire1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxPoolRetire1_t; - #define REG_APE_TX_TO_NET_POOL_MODE_STATUS_0 ((volatile APE_APE_H_uint32_t*)0x6020008c) /* */ #define APE_TX_TO_NET_POOL_MODE_STATUS_0_HALT_SHIFT 0u #define APE_TX_TO_NET_POOL_MODE_STATUS_0_HALT_MASK 0x1u @@ -1390,7 +1086,7 @@ typedef register_container RegAPERxPoolRetire1_t { #define SET_APE_TX_TO_NET_POOL_MODE_STATUS_0_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) /** @brief Register definition for @ref APE_t.TxToNetPoolModeStatus0. */ -typedef register_container RegAPETxToNetPoolModeStatus0_t { +typedef register_container RegAPETxToNetPoolModeStatus_t { /** @brief 32bit direct register access. */ APE_APE_H_uint32_t r32; @@ -1448,7 +1144,7 @@ typedef register_container RegAPETxToNetPoolModeStatus0_t { /** @brief Print register value. */ void print(void) { r32.print(); } - RegAPETxToNetPoolModeStatus0_t() + RegAPETxToNetPoolModeStatus_t() { /** @brief constructor for @ref APE_t.TxToNetPoolModeStatus0. */ r32.setName("TxToNetPoolModeStatus0"); @@ -1467,20 +1163,20 @@ typedef register_container RegAPETxToNetPoolModeStatus0_t { bits.FullCount.setBaseRegister(&r32); bits.FullCount.setName("FullCount"); } - RegAPETxToNetPoolModeStatus0_t& operator=(const RegAPETxToNetPoolModeStatus0_t& other) + RegAPETxToNetPoolModeStatus_t& operator=(const RegAPETxToNetPoolModeStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ -} RegAPETxToNetPoolModeStatus0_t; +} RegAPETxToNetPoolModeStatus_t; #define REG_APE_TX_TO_NET_BUFFER_ALLOCATOR_0 ((volatile APE_APE_H_uint32_t*)0x60200090) /* */ #define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_INDEX_SHIFT 0u #define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_INDEX_MASK 0xfffu #define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_0_INDEX(__reg__) (((__reg__) & 0xfff) >> 0u) #define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_0_INDEX(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_INDEX_BLOCK_SIZE 0x80u +#define APE_TX_TO_NET_BUFFER_ALLOCATOR_INDEX_BLOCK_SIZE 0x80u #define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_REQUEST_ALLOCATION_SHIFT 12u #define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_REQUEST_ALLOCATION_MASK 0x1000u @@ -1490,14 +1186,14 @@ typedef register_container RegAPETxToNetPoolModeStatus0_t { #define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE_MASK 0x6000u #define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) #define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE_PROCESSING 0x0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE_ALLOCATION_OK 0x1u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE_ERROR__EMPTY 0x2u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE_ERROR__IN_HALT 0x3u +#define APE_TX_TO_NET_BUFFER_ALLOCATOR_STATE_PROCESSING 0x0u +#define APE_TX_TO_NET_BUFFER_ALLOCATOR_STATE_ALLOCATION_OK 0x1u +#define APE_TX_TO_NET_BUFFER_ALLOCATOR_STATE_ERROR__EMPTY 0x2u +#define APE_TX_TO_NET_BUFFER_ALLOCATOR_STATE_ERROR__IN_HALT 0x3u /** @brief Register definition for @ref APE_t.TxToNetBufferAllocator0. */ -typedef register_container RegAPETxToNetBufferAllocator0_t { +typedef register_container RegAPETxToNetBufferAllocator_t { /** @brief 32bit direct register access. */ APE_APE_H_uint32_t r32; @@ -1531,7 +1227,7 @@ typedef register_container RegAPETxToNetBufferAllocator0_t { /** @brief Print register value. */ void print(void) { r32.print(); } - RegAPETxToNetBufferAllocator0_t() + RegAPETxToNetBufferAllocator_t() { /** @brief constructor for @ref APE_t.TxToNetBufferAllocator0. */ r32.setName("TxToNetBufferAllocator0"); @@ -1542,13 +1238,13 @@ typedef register_container RegAPETxToNetBufferAllocator0_t { bits.State.setBaseRegister(&r32); bits.State.setName("State"); } - RegAPETxToNetBufferAllocator0_t& operator=(const RegAPETxToNetBufferAllocator0_t& other) + RegAPETxToNetBufferAllocator_t& operator=(const RegAPETxToNetBufferAllocator_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ -} RegAPETxToNetBufferAllocator0_t; +} RegAPETxToNetBufferAllocator_t; #define REG_APE_TX_TO_NET_BUFFER_RETURN_0 ((volatile APE_APE_H_uint32_t*)0x60200094) /* */ /** @brief Register definition for @ref APE_t.TxToNetBufferReturn0. */ @@ -2124,1426 +1820,20 @@ typedef register_container RegAPECpuStatus_t { } RegAPECpuStatus_t; #define REG_APE_TX_TO_NET_POOL_MODE_STATUS_1 ((volatile APE_APE_H_uint32_t*)0x60200110) /* */ -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT_SHIFT 0u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT_MASK 0x1u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT_DONE_SHIFT 1u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT_DONE_MASK 0x2u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT_DONE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT_DONE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_ENABLE_SHIFT 2u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_ENABLE_MASK 0x4u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_EMPTY_SHIFT 4u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_EMPTY_MASK 0x10u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_EMPTY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_EMPTY(__val__) (((__val__) << 4u) & 0x10u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_ERROR_SHIFT 5u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_ERROR_MASK 0x20u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_ERROR(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_ERROR(__val__) (((__val__) << 5u) & 0x20u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_RESET_SHIFT 6u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_RESET_MASK 0x40u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_RESET(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_RESET(__val__) (((__val__) << 6u) & 0x40u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_FULL_COUNT_SHIFT 8u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_FULL_COUNT_MASK 0xffff00u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_FULL_COUNT(__reg__) (((__reg__) & 0xffff00) >> 8u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) - -/** @brief Register definition for @ref APE_t.TxToNetPoolModeStatus1. */ -typedef register_container RegAPETxToNetPoolModeStatus1_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Halt, 0, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief Must set Enable before the APE TX To Net Buffer Allocator will work. */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Enable, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Empty, 4, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Reset, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_24, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_24, 24, 8) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Reset, 6, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Empty, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief Must set Enable before the APE TX To Net Buffer Allocator will work. */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Enable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Halt, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetPoolModeStatus1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetPoolModeStatus1_t() - { - /** @brief constructor for @ref APE_t.TxToNetPoolModeStatus1. */ - r32.setName("TxToNetPoolModeStatus1"); - bits.Halt.setBaseRegister(&r32); - bits.Halt.setName("Halt"); - bits.HaltDone.setBaseRegister(&r32); - bits.HaltDone.setName("HaltDone"); - bits.Enable.setBaseRegister(&r32); - bits.Enable.setName("Enable"); - bits.Empty.setBaseRegister(&r32); - bits.Empty.setName("Empty"); - bits.Error.setBaseRegister(&r32); - bits.Error.setName("Error"); - bits.Reset.setBaseRegister(&r32); - bits.Reset.setName("Reset"); - bits.FullCount.setBaseRegister(&r32); - bits.FullCount.setName("FullCount"); - } - RegAPETxToNetPoolModeStatus1_t& operator=(const RegAPETxToNetPoolModeStatus1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetPoolModeStatus1_t; - #define REG_APE_TX_TO_NET_BUFFER_ALLOCATOR_1 ((volatile APE_APE_H_uint32_t*)0x60200114) /* */ -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_INDEX_SHIFT 0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_INDEX_MASK 0xfffu -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_1_INDEX(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_1_INDEX(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_INDEX_BLOCK_SIZE 0x80u - -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_REQUEST_ALLOCATION_SHIFT 12u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_REQUEST_ALLOCATION_MASK 0x1000u -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_1_REQUEST_ALLOCATION(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_1_REQUEST_ALLOCATION(__val__) (((__val__) << 12u) & 0x1000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE_SHIFT 13u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE_MASK 0x6000u -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE_PROCESSING 0x0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE_ALLOCATION_OK 0x1u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE_ERROR__EMPTY 0x2u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE_ERROR__IN_HALT 0x3u - - -/** @brief Register definition for @ref APE_t.TxToNetBufferAllocator1. */ -typedef register_container RegAPETxToNetBufferAllocator1_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Index, 0, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, RequestAllocation, 12, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 13, 2) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_15, 15, 17) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_15, 15, 17) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 13, 2) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, RequestAllocation, 12, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Index, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetBufferAllocator1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetBufferAllocator1_t() - { - /** @brief constructor for @ref APE_t.TxToNetBufferAllocator1. */ - r32.setName("TxToNetBufferAllocator1"); - bits.Index.setBaseRegister(&r32); - bits.Index.setName("Index"); - bits.RequestAllocation.setBaseRegister(&r32); - bits.RequestAllocation.setName("RequestAllocation"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - } - RegAPETxToNetBufferAllocator1_t& operator=(const RegAPETxToNetBufferAllocator1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetBufferAllocator1_t; - #define REG_APE_TX_TO_NET_DOORBELL_FUNC1 ((volatile APE_APE_H_uint32_t*)0x60200120) /* Written on APE TX to network after filling 0xA002 buffer with packet. */ -#define APE_TX_TO_NET_DOORBELL_FUNC1_TAIL_SHIFT 0u -#define APE_TX_TO_NET_DOORBELL_FUNC1_TAIL_MASK 0xfffu -#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_DOORBELL_FUNC1_HEAD_SHIFT 12u -#define APE_TX_TO_NET_DOORBELL_FUNC1_HEAD_MASK 0xfff000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH_MASK 0xf000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) -#define APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL_SHIFT 28u -#define APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL_MASK 0x10000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) - -/** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc1. */ -typedef register_container RegAPETxToNetDoorbellFunc1_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetDoorbellFunc1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetDoorbellFunc1_t() - { - /** @brief constructor for @ref APE_t.TxToNetDoorbellFunc1. */ - r32.setName("TxToNetDoorbellFunc1"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.Length.setBaseRegister(&r32); - bits.Length.setName("Length"); - bits.TXQueueFull.setBaseRegister(&r32); - bits.TXQueueFull.setName("TXQueueFull"); - } - RegAPETxToNetDoorbellFunc1_t& operator=(const RegAPETxToNetDoorbellFunc1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetDoorbellFunc1_t; - #define REG_APE_RXBUFOFFSET_FUNC2 ((volatile APE_APE_H_uint32_t*)0x60200200) /* This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. */ -#define APE_RXBUFOFFSET_FUNC2_TAIL_SHIFT 0u -#define APE_RXBUFOFFSET_FUNC2_TAIL_MASK 0xfffu -#define GET_APE_RXBUFOFFSET_FUNC2_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_RXBUFOFFSET_FUNC2_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_RXBUFOFFSET_FUNC2_HEAD_SHIFT 12u -#define APE_RXBUFOFFSET_FUNC2_HEAD_MASK 0xfff000u -#define GET_APE_RXBUFOFFSET_FUNC2_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_RXBUFOFFSET_FUNC2_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_RXBUFOFFSET_FUNC2_TO_HOST_SHIFT 24u -#define APE_RXBUFOFFSET_FUNC2_TO_HOST_MASK 0x1000000u -#define GET_APE_RXBUFOFFSET_FUNC2_TO_HOST(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_APE_RXBUFOFFSET_FUNC2_TO_HOST(__val__) (((__val__) << 24u) & 0x1000000u) -#define APE_RXBUFOFFSET_FUNC2_IP_FRAG_SHIFT 25u -#define APE_RXBUFOFFSET_FUNC2_IP_FRAG_MASK 0x2000000u -#define GET_APE_RXBUFOFFSET_FUNC2_IP_FRAG(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_APE_RXBUFOFFSET_FUNC2_IP_FRAG(__val__) (((__val__) << 25u) & 0x2000000u) -#define APE_RXBUFOFFSET_FUNC2_COUNT_SHIFT 26u -#define APE_RXBUFOFFSET_FUNC2_COUNT_MASK 0x3c000000u -#define GET_APE_RXBUFOFFSET_FUNC2_COUNT(__reg__) (((__reg__) & 0x3c000000) >> 26u) -#define SET_APE_RXBUFOFFSET_FUNC2_COUNT(__val__) (((__val__) << 26u) & 0x3c000000u) -#define APE_RXBUFOFFSET_FUNC2_VALID_SHIFT 30u -#define APE_RXBUFOFFSET_FUNC2_VALID_MASK 0x40000000u -#define GET_APE_RXBUFOFFSET_FUNC2_VALID(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_APE_RXBUFOFFSET_FUNC2_VALID(__val__) (((__val__) << 30u) & 0x40000000u) - -/** @brief Register definition for @ref APE_t.RxbufoffsetFunc2. */ -typedef register_container RegAPERxbufoffsetFunc2_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, ToHost, 24, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, IPFrag, 25, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 26, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Valid, 30, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Valid, 30, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 26, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, IPFrag, 25, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, ToHost, 24, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxbufoffsetFunc2"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxbufoffsetFunc2_t() - { - /** @brief constructor for @ref APE_t.RxbufoffsetFunc2. */ - r32.setName("RxbufoffsetFunc2"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.ToHost.setBaseRegister(&r32); - bits.ToHost.setName("ToHost"); - bits.IPFrag.setBaseRegister(&r32); - bits.IPFrag.setName("IPFrag"); - bits.Count.setBaseRegister(&r32); - bits.Count.setName("Count"); - bits.Valid.setBaseRegister(&r32); - bits.Valid.setName("Valid"); - } - RegAPERxbufoffsetFunc2_t& operator=(const RegAPERxbufoffsetFunc2_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxbufoffsetFunc2_t; - #define REG_APE_TX_TO_NET_DOORBELL_FUNC2 ((volatile APE_APE_H_uint32_t*)0x60200204) /* Written on APE TX to network after filling 0xA002 buffer with packet. */ -#define APE_TX_TO_NET_DOORBELL_FUNC2_TAIL_SHIFT 0u -#define APE_TX_TO_NET_DOORBELL_FUNC2_TAIL_MASK 0xfffu -#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_DOORBELL_FUNC2_HEAD_SHIFT 12u -#define APE_TX_TO_NET_DOORBELL_FUNC2_HEAD_MASK 0xfff000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH_MASK 0xf000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) -#define APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL_SHIFT 28u -#define APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL_MASK 0x10000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) - -/** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc2. */ -typedef register_container RegAPETxToNetDoorbellFunc2_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetDoorbellFunc2"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetDoorbellFunc2_t() - { - /** @brief constructor for @ref APE_t.TxToNetDoorbellFunc2. */ - r32.setName("TxToNetDoorbellFunc2"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.Length.setBaseRegister(&r32); - bits.Length.setName("Length"); - bits.TXQueueFull.setBaseRegister(&r32); - bits.TXQueueFull.setName("TXQueueFull"); - } - RegAPETxToNetDoorbellFunc2_t& operator=(const RegAPETxToNetDoorbellFunc2_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetDoorbellFunc2_t; - #define REG_APE_RX_POOL_MODE_STATUS_2 ((volatile APE_APE_H_uint32_t*)0x60200214) /* */ -#define APE_RX_POOL_MODE_STATUS_2_HALT_SHIFT 0u -#define APE_RX_POOL_MODE_STATUS_2_HALT_MASK 0x1u -#define GET_APE_RX_POOL_MODE_STATUS_2_HALT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_RX_POOL_MODE_STATUS_2_HALT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_RX_POOL_MODE_STATUS_2_HALT_DONE_SHIFT 1u -#define APE_RX_POOL_MODE_STATUS_2_HALT_DONE_MASK 0x2u -#define GET_APE_RX_POOL_MODE_STATUS_2_HALT_DONE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_RX_POOL_MODE_STATUS_2_HALT_DONE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_RX_POOL_MODE_STATUS_2_ENABLE_SHIFT 2u -#define APE_RX_POOL_MODE_STATUS_2_ENABLE_MASK 0x4u -#define GET_APE_RX_POOL_MODE_STATUS_2_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_RX_POOL_MODE_STATUS_2_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_RX_POOL_MODE_STATUS_2_EMPTY_SHIFT 4u -#define APE_RX_POOL_MODE_STATUS_2_EMPTY_MASK 0x10u -#define GET_APE_RX_POOL_MODE_STATUS_2_EMPTY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_RX_POOL_MODE_STATUS_2_EMPTY(__val__) (((__val__) << 4u) & 0x10u) -#define APE_RX_POOL_MODE_STATUS_2_ERROR_SHIFT 5u -#define APE_RX_POOL_MODE_STATUS_2_ERROR_MASK 0x20u -#define GET_APE_RX_POOL_MODE_STATUS_2_ERROR(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_RX_POOL_MODE_STATUS_2_ERROR(__val__) (((__val__) << 5u) & 0x20u) -#define APE_RX_POOL_MODE_STATUS_2_RESET_SHIFT 6u -#define APE_RX_POOL_MODE_STATUS_2_RESET_MASK 0x40u -#define GET_APE_RX_POOL_MODE_STATUS_2_RESET(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_RX_POOL_MODE_STATUS_2_RESET(__val__) (((__val__) << 6u) & 0x40u) -#define APE_RX_POOL_MODE_STATUS_2_FULL_COUNT_SHIFT 8u -#define APE_RX_POOL_MODE_STATUS_2_FULL_COUNT_MASK 0xffff00u -#define GET_APE_RX_POOL_MODE_STATUS_2_FULL_COUNT(__reg__) (((__reg__) & 0xffff00) >> 8u) -#define SET_APE_RX_POOL_MODE_STATUS_2_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) - -/** @brief Register definition for @ref APE_t.RxPoolModeStatus2. */ -typedef register_container RegAPERxPoolModeStatus2_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Halt, 0, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Enable, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Empty, 4, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Reset, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_24, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_24, 24, 8) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Reset, 6, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Empty, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Enable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Halt, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxPoolModeStatus2"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxPoolModeStatus2_t() - { - /** @brief constructor for @ref APE_t.RxPoolModeStatus2. */ - r32.setName("RxPoolModeStatus2"); - bits.Halt.setBaseRegister(&r32); - bits.Halt.setName("Halt"); - bits.HaltDone.setBaseRegister(&r32); - bits.HaltDone.setName("HaltDone"); - bits.Enable.setBaseRegister(&r32); - bits.Enable.setName("Enable"); - bits.Empty.setBaseRegister(&r32); - bits.Empty.setName("Empty"); - bits.Error.setBaseRegister(&r32); - bits.Error.setName("Error"); - bits.Reset.setBaseRegister(&r32); - bits.Reset.setName("Reset"); - bits.FullCount.setBaseRegister(&r32); - bits.FullCount.setName("FullCount"); - } - RegAPERxPoolModeStatus2_t& operator=(const RegAPERxPoolModeStatus2_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxPoolModeStatus2_t; - #define REG_APE_RX_POOL_RETIRE_2 ((volatile APE_APE_H_uint32_t*)0x60200218) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ -#define APE_RX_POOL_RETIRE_2_TAIL_SHIFT 0u -#define APE_RX_POOL_RETIRE_2_TAIL_MASK 0xfffu -#define GET_APE_RX_POOL_RETIRE_2_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_RX_POOL_RETIRE_2_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_RX_POOL_RETIRE_2_HEAD_SHIFT 12u -#define APE_RX_POOL_RETIRE_2_HEAD_MASK 0xfff000u -#define GET_APE_RX_POOL_RETIRE_2_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_RX_POOL_RETIRE_2_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_RX_POOL_RETIRE_2_RETIRE_SHIFT 24u -#define APE_RX_POOL_RETIRE_2_RETIRE_MASK 0x1000000u -#define GET_APE_RX_POOL_RETIRE_2_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_APE_RX_POOL_RETIRE_2_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) -#define APE_RX_POOL_RETIRE_2_STATE_SHIFT 25u -#define APE_RX_POOL_RETIRE_2_STATE_MASK 0x6000000u -#define GET_APE_RX_POOL_RETIRE_2_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) -#define SET_APE_RX_POOL_RETIRE_2_STATE(__val__) (((__val__) << 25u) & 0x6000000u) -#define APE_RX_POOL_RETIRE_2_STATE_PROCESSING 0x0u -#define APE_RX_POOL_RETIRE_2_STATE_RETIRED_OK 0x1u -#define APE_RX_POOL_RETIRE_2_STATE_ERROR__FULL 0x2u -#define APE_RX_POOL_RETIRE_2_STATE_ERROR__IN_HALT 0x3u - -#define APE_RX_POOL_RETIRE_2_COUNT_SHIFT 27u -#define APE_RX_POOL_RETIRE_2_COUNT_MASK 0x78000000u -#define GET_APE_RX_POOL_RETIRE_2_COUNT(__reg__) (((__reg__) & 0x78000000) >> 27u) -#define SET_APE_RX_POOL_RETIRE_2_COUNT(__val__) (((__val__) << 27u) & 0x78000000u) - -/** @brief Register definition for @ref APE_t.RxPoolRetire2. */ -typedef register_container RegAPERxPoolRetire2_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 27, 4) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 27, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxPoolRetire2"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxPoolRetire2_t() - { - /** @brief constructor for @ref APE_t.RxPoolRetire2. */ - r32.setName("RxPoolRetire2"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.Retire.setBaseRegister(&r32); - bits.Retire.setName("Retire"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - bits.Count.setBaseRegister(&r32); - bits.Count.setName("Count"); - } - RegAPERxPoolRetire2_t& operator=(const RegAPERxPoolRetire2_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxPoolRetire2_t; - #define REG_APE_TX_TO_NET_POOL_MODE_STATUS_2 ((volatile APE_APE_H_uint32_t*)0x60200220) /* */ -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT_SHIFT 0u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT_MASK 0x1u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT_DONE_SHIFT 1u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT_DONE_MASK 0x2u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT_DONE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT_DONE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_ENABLE_SHIFT 2u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_ENABLE_MASK 0x4u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_EMPTY_SHIFT 4u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_EMPTY_MASK 0x10u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_EMPTY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_EMPTY(__val__) (((__val__) << 4u) & 0x10u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_ERROR_SHIFT 5u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_ERROR_MASK 0x20u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_ERROR(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_ERROR(__val__) (((__val__) << 5u) & 0x20u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_RESET_SHIFT 6u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_RESET_MASK 0x40u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_RESET(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_RESET(__val__) (((__val__) << 6u) & 0x40u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_FULL_COUNT_SHIFT 8u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_FULL_COUNT_MASK 0xffff00u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_FULL_COUNT(__reg__) (((__reg__) & 0xffff00) >> 8u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) - -/** @brief Register definition for @ref APE_t.TxToNetPoolModeStatus2. */ -typedef register_container RegAPETxToNetPoolModeStatus2_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Halt, 0, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief Must set Enable before the APE TX To Net Buffer Allocator will work. */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Enable, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Empty, 4, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Reset, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_24, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_24, 24, 8) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Reset, 6, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Empty, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief Must set Enable before the APE TX To Net Buffer Allocator will work. */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Enable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Halt, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetPoolModeStatus2"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetPoolModeStatus2_t() - { - /** @brief constructor for @ref APE_t.TxToNetPoolModeStatus2. */ - r32.setName("TxToNetPoolModeStatus2"); - bits.Halt.setBaseRegister(&r32); - bits.Halt.setName("Halt"); - bits.HaltDone.setBaseRegister(&r32); - bits.HaltDone.setName("HaltDone"); - bits.Enable.setBaseRegister(&r32); - bits.Enable.setName("Enable"); - bits.Empty.setBaseRegister(&r32); - bits.Empty.setName("Empty"); - bits.Error.setBaseRegister(&r32); - bits.Error.setName("Error"); - bits.Reset.setBaseRegister(&r32); - bits.Reset.setName("Reset"); - bits.FullCount.setBaseRegister(&r32); - bits.FullCount.setName("FullCount"); - } - RegAPETxToNetPoolModeStatus2_t& operator=(const RegAPETxToNetPoolModeStatus2_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetPoolModeStatus2_t; - #define REG_APE_TX_TO_NET_BUFFER_ALLOCATOR_2 ((volatile APE_APE_H_uint32_t*)0x60200224) /* */ -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_INDEX_SHIFT 0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_INDEX_MASK 0xfffu -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_2_INDEX(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_2_INDEX(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_INDEX_BLOCK_SIZE 0x80u - -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_REQUEST_ALLOCATION_SHIFT 12u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_REQUEST_ALLOCATION_MASK 0x1000u -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_2_REQUEST_ALLOCATION(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_2_REQUEST_ALLOCATION(__val__) (((__val__) << 12u) & 0x1000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE_SHIFT 13u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE_MASK 0x6000u -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE_PROCESSING 0x0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE_ALLOCATION_OK 0x1u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE_ERROR__EMPTY 0x2u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE_ERROR__IN_HALT 0x3u - - -/** @brief Register definition for @ref APE_t.TxToNetBufferAllocator2. */ -typedef register_container RegAPETxToNetBufferAllocator2_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Index, 0, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, RequestAllocation, 12, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 13, 2) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_15, 15, 17) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_15, 15, 17) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 13, 2) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, RequestAllocation, 12, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Index, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetBufferAllocator2"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetBufferAllocator2_t() - { - /** @brief constructor for @ref APE_t.TxToNetBufferAllocator2. */ - r32.setName("TxToNetBufferAllocator2"); - bits.Index.setBaseRegister(&r32); - bits.Index.setName("Index"); - bits.RequestAllocation.setBaseRegister(&r32); - bits.RequestAllocation.setName("RequestAllocation"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - } - RegAPETxToNetBufferAllocator2_t& operator=(const RegAPETxToNetBufferAllocator2_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetBufferAllocator2_t; - #define REG_APE_RXBUFOFFSET_FUNC3 ((volatile APE_APE_H_uint32_t*)0x60200300) /* This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. */ -#define APE_RXBUFOFFSET_FUNC3_TAIL_SHIFT 0u -#define APE_RXBUFOFFSET_FUNC3_TAIL_MASK 0xfffu -#define GET_APE_RXBUFOFFSET_FUNC3_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_RXBUFOFFSET_FUNC3_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_RXBUFOFFSET_FUNC3_HEAD_SHIFT 12u -#define APE_RXBUFOFFSET_FUNC3_HEAD_MASK 0xfff000u -#define GET_APE_RXBUFOFFSET_FUNC3_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_RXBUFOFFSET_FUNC3_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_RXBUFOFFSET_FUNC3_TO_HOST_SHIFT 24u -#define APE_RXBUFOFFSET_FUNC3_TO_HOST_MASK 0x1000000u -#define GET_APE_RXBUFOFFSET_FUNC3_TO_HOST(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_APE_RXBUFOFFSET_FUNC3_TO_HOST(__val__) (((__val__) << 24u) & 0x1000000u) -#define APE_RXBUFOFFSET_FUNC3_IP_FRAG_SHIFT 25u -#define APE_RXBUFOFFSET_FUNC3_IP_FRAG_MASK 0x2000000u -#define GET_APE_RXBUFOFFSET_FUNC3_IP_FRAG(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_APE_RXBUFOFFSET_FUNC3_IP_FRAG(__val__) (((__val__) << 25u) & 0x2000000u) -#define APE_RXBUFOFFSET_FUNC3_COUNT_SHIFT 26u -#define APE_RXBUFOFFSET_FUNC3_COUNT_MASK 0x3c000000u -#define GET_APE_RXBUFOFFSET_FUNC3_COUNT(__reg__) (((__reg__) & 0x3c000000) >> 26u) -#define SET_APE_RXBUFOFFSET_FUNC3_COUNT(__val__) (((__val__) << 26u) & 0x3c000000u) -#define APE_RXBUFOFFSET_FUNC3_VALID_SHIFT 30u -#define APE_RXBUFOFFSET_FUNC3_VALID_MASK 0x40000000u -#define GET_APE_RXBUFOFFSET_FUNC3_VALID(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_APE_RXBUFOFFSET_FUNC3_VALID(__val__) (((__val__) << 30u) & 0x40000000u) - -/** @brief Register definition for @ref APE_t.RxbufoffsetFunc3. */ -typedef register_container RegAPERxbufoffsetFunc3_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, ToHost, 24, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, IPFrag, 25, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 26, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Valid, 30, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Valid, 30, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 26, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, IPFrag, 25, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, ToHost, 24, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxbufoffsetFunc3"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxbufoffsetFunc3_t() - { - /** @brief constructor for @ref APE_t.RxbufoffsetFunc3. */ - r32.setName("RxbufoffsetFunc3"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.ToHost.setBaseRegister(&r32); - bits.ToHost.setName("ToHost"); - bits.IPFrag.setBaseRegister(&r32); - bits.IPFrag.setName("IPFrag"); - bits.Count.setBaseRegister(&r32); - bits.Count.setName("Count"); - bits.Valid.setBaseRegister(&r32); - bits.Valid.setName("Valid"); - } - RegAPERxbufoffsetFunc3_t& operator=(const RegAPERxbufoffsetFunc3_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxbufoffsetFunc3_t; - #define REG_APE_TX_TO_NET_DOORBELL_FUNC3 ((volatile APE_APE_H_uint32_t*)0x60200304) /* Written on APE TX to network after filling 0xA002 buffer with packet. */ -#define APE_TX_TO_NET_DOORBELL_FUNC3_TAIL_SHIFT 0u -#define APE_TX_TO_NET_DOORBELL_FUNC3_TAIL_MASK 0xfffu -#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_DOORBELL_FUNC3_HEAD_SHIFT 12u -#define APE_TX_TO_NET_DOORBELL_FUNC3_HEAD_MASK 0xfff000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH_MASK 0xf000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) -#define APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL_SHIFT 28u -#define APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL_MASK 0x10000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) - -/** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc3. */ -typedef register_container RegAPETxToNetDoorbellFunc3_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_29, 29, 3) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, TXQueueFull, 28, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Length, 24, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetDoorbellFunc3"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetDoorbellFunc3_t() - { - /** @brief constructor for @ref APE_t.TxToNetDoorbellFunc3. */ - r32.setName("TxToNetDoorbellFunc3"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.Length.setBaseRegister(&r32); - bits.Length.setName("Length"); - bits.TXQueueFull.setBaseRegister(&r32); - bits.TXQueueFull.setName("TXQueueFull"); - } - RegAPETxToNetDoorbellFunc3_t& operator=(const RegAPETxToNetDoorbellFunc3_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetDoorbellFunc3_t; - #define REG_APE_RX_POOL_MODE_STATUS_3 ((volatile APE_APE_H_uint32_t*)0x60200314) /* */ -#define APE_RX_POOL_MODE_STATUS_3_HALT_SHIFT 0u -#define APE_RX_POOL_MODE_STATUS_3_HALT_MASK 0x1u -#define GET_APE_RX_POOL_MODE_STATUS_3_HALT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_RX_POOL_MODE_STATUS_3_HALT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_RX_POOL_MODE_STATUS_3_HALT_DONE_SHIFT 1u -#define APE_RX_POOL_MODE_STATUS_3_HALT_DONE_MASK 0x2u -#define GET_APE_RX_POOL_MODE_STATUS_3_HALT_DONE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_RX_POOL_MODE_STATUS_3_HALT_DONE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_RX_POOL_MODE_STATUS_3_ENABLE_SHIFT 2u -#define APE_RX_POOL_MODE_STATUS_3_ENABLE_MASK 0x4u -#define GET_APE_RX_POOL_MODE_STATUS_3_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_RX_POOL_MODE_STATUS_3_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_RX_POOL_MODE_STATUS_3_EMPTY_SHIFT 4u -#define APE_RX_POOL_MODE_STATUS_3_EMPTY_MASK 0x10u -#define GET_APE_RX_POOL_MODE_STATUS_3_EMPTY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_RX_POOL_MODE_STATUS_3_EMPTY(__val__) (((__val__) << 4u) & 0x10u) -#define APE_RX_POOL_MODE_STATUS_3_ERROR_SHIFT 5u -#define APE_RX_POOL_MODE_STATUS_3_ERROR_MASK 0x20u -#define GET_APE_RX_POOL_MODE_STATUS_3_ERROR(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_RX_POOL_MODE_STATUS_3_ERROR(__val__) (((__val__) << 5u) & 0x20u) -#define APE_RX_POOL_MODE_STATUS_3_RESET_SHIFT 6u -#define APE_RX_POOL_MODE_STATUS_3_RESET_MASK 0x40u -#define GET_APE_RX_POOL_MODE_STATUS_3_RESET(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_RX_POOL_MODE_STATUS_3_RESET(__val__) (((__val__) << 6u) & 0x40u) -#define APE_RX_POOL_MODE_STATUS_3_FULL_COUNT_SHIFT 8u -#define APE_RX_POOL_MODE_STATUS_3_FULL_COUNT_MASK 0xffff00u -#define GET_APE_RX_POOL_MODE_STATUS_3_FULL_COUNT(__reg__) (((__reg__) & 0xffff00) >> 8u) -#define SET_APE_RX_POOL_MODE_STATUS_3_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) - -/** @brief Register definition for @ref APE_t.RxPoolModeStatus3. */ -typedef register_container RegAPERxPoolModeStatus3_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Halt, 0, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Enable, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Empty, 4, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Reset, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_24, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_24, 24, 8) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Reset, 6, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Empty, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Enable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Halt, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxPoolModeStatus3"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxPoolModeStatus3_t() - { - /** @brief constructor for @ref APE_t.RxPoolModeStatus3. */ - r32.setName("RxPoolModeStatus3"); - bits.Halt.setBaseRegister(&r32); - bits.Halt.setName("Halt"); - bits.HaltDone.setBaseRegister(&r32); - bits.HaltDone.setName("HaltDone"); - bits.Enable.setBaseRegister(&r32); - bits.Enable.setName("Enable"); - bits.Empty.setBaseRegister(&r32); - bits.Empty.setName("Empty"); - bits.Error.setBaseRegister(&r32); - bits.Error.setName("Error"); - bits.Reset.setBaseRegister(&r32); - bits.Reset.setName("Reset"); - bits.FullCount.setBaseRegister(&r32); - bits.FullCount.setName("FullCount"); - } - RegAPERxPoolModeStatus3_t& operator=(const RegAPERxPoolModeStatus3_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxPoolModeStatus3_t; - #define REG_APE_RX_POOL_RETIRE_3 ((volatile APE_APE_H_uint32_t*)0x60200318) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ -#define APE_RX_POOL_RETIRE_3_TAIL_SHIFT 0u -#define APE_RX_POOL_RETIRE_3_TAIL_MASK 0xfffu -#define GET_APE_RX_POOL_RETIRE_3_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_RX_POOL_RETIRE_3_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_RX_POOL_RETIRE_3_HEAD_SHIFT 12u -#define APE_RX_POOL_RETIRE_3_HEAD_MASK 0xfff000u -#define GET_APE_RX_POOL_RETIRE_3_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_RX_POOL_RETIRE_3_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_RX_POOL_RETIRE_3_RETIRE_SHIFT 24u -#define APE_RX_POOL_RETIRE_3_RETIRE_MASK 0x1000000u -#define GET_APE_RX_POOL_RETIRE_3_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_APE_RX_POOL_RETIRE_3_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) -#define APE_RX_POOL_RETIRE_3_STATE_SHIFT 25u -#define APE_RX_POOL_RETIRE_3_STATE_MASK 0x6000000u -#define GET_APE_RX_POOL_RETIRE_3_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) -#define SET_APE_RX_POOL_RETIRE_3_STATE(__val__) (((__val__) << 25u) & 0x6000000u) -#define APE_RX_POOL_RETIRE_3_STATE_PROCESSING 0x0u -#define APE_RX_POOL_RETIRE_3_STATE_RETIRED_OK 0x1u -#define APE_RX_POOL_RETIRE_3_STATE_ERROR__FULL 0x2u -#define APE_RX_POOL_RETIRE_3_STATE_ERROR__IN_HALT 0x3u - -#define APE_RX_POOL_RETIRE_3_COUNT_SHIFT 27u -#define APE_RX_POOL_RETIRE_3_COUNT_MASK 0x78000000u -#define GET_APE_RX_POOL_RETIRE_3_COUNT(__reg__) (((__reg__) & 0x78000000) >> 27u) -#define SET_APE_RX_POOL_RETIRE_3_COUNT(__val__) (((__val__) << 27u) & 0x78000000u) - -/** @brief Register definition for @ref APE_t.RxPoolRetire3. */ -typedef register_container RegAPERxPoolRetire3_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 27, 4) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_31, 31, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Count, 27, 4) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 25, 2) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Retire, 24, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxPoolRetire3"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxPoolRetire3_t() - { - /** @brief constructor for @ref APE_t.RxPoolRetire3. */ - r32.setName("RxPoolRetire3"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.Retire.setBaseRegister(&r32); - bits.Retire.setName("Retire"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - bits.Count.setBaseRegister(&r32); - bits.Count.setName("Count"); - } - RegAPERxPoolRetire3_t& operator=(const RegAPERxPoolRetire3_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxPoolRetire3_t; - #define REG_APE_TX_TO_NET_POOL_MODE_STATUS_3 ((volatile APE_APE_H_uint32_t*)0x60200320) /* */ -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT_SHIFT 0u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT_MASK 0x1u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT_DONE_SHIFT 1u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT_DONE_MASK 0x2u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT_DONE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT_DONE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_ENABLE_SHIFT 2u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_ENABLE_MASK 0x4u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_EMPTY_SHIFT 4u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_EMPTY_MASK 0x10u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_EMPTY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_EMPTY(__val__) (((__val__) << 4u) & 0x10u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_ERROR_SHIFT 5u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_ERROR_MASK 0x20u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_ERROR(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_ERROR(__val__) (((__val__) << 5u) & 0x20u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_RESET_SHIFT 6u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_RESET_MASK 0x40u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_RESET(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_RESET(__val__) (((__val__) << 6u) & 0x40u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_FULL_COUNT_SHIFT 8u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_FULL_COUNT_MASK 0xffff00u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_FULL_COUNT(__reg__) (((__reg__) & 0xffff00) >> 8u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) - -/** @brief Register definition for @ref APE_t.TxToNetPoolModeStatus3. */ -typedef register_container RegAPETxToNetPoolModeStatus3_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Halt, 0, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief Must set Enable before the APE TX To Net Buffer Allocator will work. */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Enable, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Empty, 4, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Reset, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_24, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_24, 24, 8) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Reset, 6, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Empty, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief Must set Enable before the APE TX To Net Buffer Allocator will work. */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Enable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Halt, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetPoolModeStatus3"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetPoolModeStatus3_t() - { - /** @brief constructor for @ref APE_t.TxToNetPoolModeStatus3. */ - r32.setName("TxToNetPoolModeStatus3"); - bits.Halt.setBaseRegister(&r32); - bits.Halt.setName("Halt"); - bits.HaltDone.setBaseRegister(&r32); - bits.HaltDone.setName("HaltDone"); - bits.Enable.setBaseRegister(&r32); - bits.Enable.setName("Enable"); - bits.Empty.setBaseRegister(&r32); - bits.Empty.setName("Empty"); - bits.Error.setBaseRegister(&r32); - bits.Error.setName("Error"); - bits.Reset.setBaseRegister(&r32); - bits.Reset.setName("Reset"); - bits.FullCount.setBaseRegister(&r32); - bits.FullCount.setName("FullCount"); - } - RegAPETxToNetPoolModeStatus3_t& operator=(const RegAPETxToNetPoolModeStatus3_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetPoolModeStatus3_t; - #define REG_APE_TX_TO_NET_BUFFER_ALLOCATOR_3 ((volatile APE_APE_H_uint32_t*)0x60200324) /* */ -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_INDEX_SHIFT 0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_INDEX_MASK 0xfffu -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_3_INDEX(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_3_INDEX(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_INDEX_BLOCK_SIZE 0x80u - -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_REQUEST_ALLOCATION_SHIFT 12u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_REQUEST_ALLOCATION_MASK 0x1000u -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_3_REQUEST_ALLOCATION(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_3_REQUEST_ALLOCATION(__val__) (((__val__) << 12u) & 0x1000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE_SHIFT 13u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE_MASK 0x6000u -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE_PROCESSING 0x0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE_ALLOCATION_OK 0x1u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE_ERROR__EMPTY 0x2u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE_ERROR__IN_HALT 0x3u - - -/** @brief Register definition for @ref APE_t.TxToNetBufferAllocator3. */ -typedef register_container RegAPETxToNetBufferAllocator3_t { - /** @brief 32bit direct register access. */ - APE_APE_H_uint32_t r32; - - BITFIELD_BEGIN(APE_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Index, 0, 12) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, RequestAllocation, 12, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 13, 2) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_15, 15, 17) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, reserved_31_15, 15, 17) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, State, 13, 2) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, RequestAllocation, 12, 1) - /** @brief */ - BITFIELD_MEMBER(APE_APE_H_uint32_t, Index, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(APE_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetBufferAllocator3"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetBufferAllocator3_t() - { - /** @brief constructor for @ref APE_t.TxToNetBufferAllocator3. */ - r32.setName("TxToNetBufferAllocator3"); - bits.Index.setBaseRegister(&r32); - bits.Index.setName("Index"); - bits.RequestAllocation.setBaseRegister(&r32); - bits.RequestAllocation.setName("RequestAllocation"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - } - RegAPETxToNetBufferAllocator3_t& operator=(const RegAPETxToNetBufferAllocator3_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetBufferAllocator3_t; - /** @brief Component definition for @ref APE. */ typedef struct APE_t { /** @brief More of these bits can be found in diagnostic utilities, but they don't seem too interesting. */ @@ -3562,13 +1852,13 @@ typedef struct APE_t { APE_APE_H_uint32_t reserved_16[1]; /** @brief This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. The fields are block numbers (block size 128 bytes). */ - RegAPERxbufoffsetFunc0_t RxbufoffsetFunc0; + RegAPERxbufoffset_t RxbufoffsetFunc0; /** @brief This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. */ - RegAPERxbufoffsetFunc1_t RxbufoffsetFunc1; + RegAPERxbufoffset_t RxbufoffsetFunc1; /** @brief Written on APE TX to network after filling 0xA002 buffer with packet. */ - RegAPETxToNetDoorbellFunc0_t TxToNetDoorbellFunc0; + RegAPETxToNetDoorbell_t TxToNetDoorbellFunc0; /** @brief APE TX Status. */ RegAPETxState0_t TxState0; @@ -3592,25 +1882,25 @@ typedef struct APE_t { APE_APE_H_uint32_t reserved_80[10]; /** @brief */ - RegAPERxPoolModeStatus0_t RxPoolModeStatus0; + RegAPERxPoolModeStatus_t RxPoolModeStatus0; /** @brief */ - RegAPERxPoolModeStatus1_t RxPoolModeStatus1; + RegAPERxPoolModeStatus_t RxPoolModeStatus1; /** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ - RegAPERxPoolRetire0_t RxPoolRetire0; + RegAPERxPoolRetire_t RxPoolRetire0; /** @brief Reserved bytes to pad out data structure. */ APE_APE_H_uint32_t reserved_132[1]; /** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ - RegAPERxPoolRetire1_t RxPoolRetire1; + RegAPERxPoolRetire_t RxPoolRetire1; /** @brief */ - RegAPETxToNetPoolModeStatus0_t TxToNetPoolModeStatus0; + RegAPETxToNetPoolModeStatus_t TxToNetPoolModeStatus0; /** @brief */ - RegAPETxToNetBufferAllocator0_t TxToNetBufferAllocator0; + RegAPETxToNetBufferAllocator_t TxToNetBufferAllocator0; /** @brief */ RegAPETxToNetBufferReturn0_t TxToNetBufferReturn0; @@ -3667,70 +1957,70 @@ typedef struct APE_t { APE_APE_H_uint32_t reserved_268[1]; /** @brief */ - RegAPETxToNetPoolModeStatus1_t TxToNetPoolModeStatus1; + RegAPETxToNetPoolModeStatus_t TxToNetPoolModeStatus1; /** @brief */ - RegAPETxToNetBufferAllocator1_t TxToNetBufferAllocator1; + RegAPETxToNetBufferAllocator_t TxToNetBufferAllocator1; /** @brief Reserved bytes to pad out data structure. */ APE_APE_H_uint32_t reserved_280[2]; /** @brief Written on APE TX to network after filling 0xA002 buffer with packet. */ - RegAPETxToNetDoorbellFunc1_t TxToNetDoorbellFunc1; + RegAPETxToNetDoorbell_t TxToNetDoorbellFunc1; /** @brief Reserved bytes to pad out data structure. */ APE_APE_H_uint32_t reserved_292[55]; /** @brief This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. */ - RegAPERxbufoffsetFunc2_t RxbufoffsetFunc2; + RegAPERxbufoffset_t RxbufoffsetFunc2; /** @brief Written on APE TX to network after filling 0xA002 buffer with packet. */ - RegAPETxToNetDoorbellFunc2_t TxToNetDoorbellFunc2; + RegAPETxToNetDoorbell_t TxToNetDoorbellFunc2; /** @brief Reserved bytes to pad out data structure. */ APE_APE_H_uint32_t reserved_520[3]; /** @brief */ - RegAPERxPoolModeStatus2_t RxPoolModeStatus2; + RegAPERxPoolModeStatus_t RxPoolModeStatus2; /** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ - RegAPERxPoolRetire2_t RxPoolRetire2; + RegAPERxPoolRetire_t RxPoolRetire2; /** @brief Reserved bytes to pad out data structure. */ APE_APE_H_uint32_t reserved_540[1]; /** @brief */ - RegAPETxToNetPoolModeStatus2_t TxToNetPoolModeStatus2; + RegAPETxToNetPoolModeStatus_t TxToNetPoolModeStatus2; /** @brief */ - RegAPETxToNetBufferAllocator2_t TxToNetBufferAllocator2; + RegAPETxToNetBufferAllocator_t TxToNetBufferAllocator2; /** @brief Reserved bytes to pad out data structure. */ APE_APE_H_uint32_t reserved_552[54]; /** @brief This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. */ - RegAPERxbufoffsetFunc3_t RxbufoffsetFunc3; + RegAPERxbufoffset_t RxbufoffsetFunc3; /** @brief Written on APE TX to network after filling 0xA002 buffer with packet. */ - RegAPETxToNetDoorbellFunc3_t TxToNetDoorbellFunc3; + RegAPETxToNetDoorbell_t TxToNetDoorbellFunc3; /** @brief Reserved bytes to pad out data structure. */ APE_APE_H_uint32_t reserved_776[3]; /** @brief */ - RegAPERxPoolModeStatus3_t RxPoolModeStatus3; + RegAPERxPoolModeStatus_t RxPoolModeStatus3; /** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ - RegAPERxPoolRetire3_t RxPoolRetire3; + RegAPERxPoolRetire_t RxPoolRetire3; /** @brief Reserved bytes to pad out data structure. */ APE_APE_H_uint32_t reserved_796[1]; /** @brief */ - RegAPETxToNetPoolModeStatus3_t TxToNetPoolModeStatus3; + RegAPETxToNetPoolModeStatus_t TxToNetPoolModeStatus3; /** @brief */ - RegAPETxToNetBufferAllocator3_t TxToNetBufferAllocator3; + RegAPETxToNetBufferAllocator_t TxToNetBufferAllocator3; #ifdef CXX_SIMULATOR APE_t() diff --git a/include/APE_DEVICE1.h b/include/APE_DEVICE1.h index 589828c..59811db 100644 --- a/include/APE_DEVICE1.h +++ b/include/APE_DEVICE1.h @@ -83,333 +83,17 @@ typedef uint32_t APE_DEVICE1_H_uint32_t; #define REG_DEVICE1_SIZE (sizeof(DEVICE_t)) #define REG_DEVICE1_MISCELLANEOUS_HOST_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0050068) /* */ -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x1u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x2u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x4u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x8u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 4u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x10u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 5u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x20u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x40u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x80u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x100u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x200u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x400u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x800u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x1000u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__val__) (((__val__) << 12u) & 0x1000u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x2000u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x4000u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x8000u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_SHIFT 16u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_MASK 0xff0000u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__reg__) (((__reg__) & 0xff0000) >> 16u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__val__) (((__val__) << 16u) & 0xff0000u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_0 0x0u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_1 0x1u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_2 0x2u - -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_SHIFT 24u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_MASK 0xf000000u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__reg__) (((__reg__) & 0xf000000) >> 24u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__val__) (((__val__) << 24u) & 0xf000000u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_A 0x0u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_B 0x1u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_C 0x2u - -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 28u -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xf0000000u -#define GET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__reg__) (((__reg__) & 0xf0000000) >> 28u) -#define SET_DEVICE1_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__val__) (((__val__) << 28u) & 0xf0000000u) -#define DEVICE1_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_NEW_PRODUCT_MAPPING 0xfu - - #define REG_DEVICE1_PCI_STATE ((volatile APE_DEVICE1_H_uint32_t*)0xa0050070) /* */ -#define DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5u -#define DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x20u -#define GET_DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6u -#define DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x40u -#define GET_DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE1_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE1_PCI_STATE_VPD_AVAILABLE_SHIFT 7u -#define DEVICE1_PCI_STATE_VPD_AVAILABLE_MASK 0x80u -#define GET_DEVICE1_PCI_STATE_VPD_AVAILABLE(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE1_PCI_STATE_VPD_AVAILABLE(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE1_PCI_STATE_FLAT_VIEW_SHIFT 8u -#define DEVICE1_PCI_STATE_FLAT_VIEW_MASK 0x100u -#define GET_DEVICE1_PCI_STATE_FLAT_VIEW(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE1_PCI_STATE_FLAT_VIEW(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE1_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9u -#define DEVICE1_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0xe00u -#define GET_DEVICE1_PCI_STATE_MAX_PCI_TARGET_RETRY(__reg__) (((__reg__) & 0xe00) >> 9u) -#define SET_DEVICE1_PCI_STATE_MAX_PCI_TARGET_RETRY(__val__) (((__val__) << 9u) & 0xe00u) -#define DEVICE1_PCI_STATE_CONFIG_RETRY_SHIFT 15u -#define DEVICE1_PCI_STATE_CONFIG_RETRY_MASK 0x8000u -#define GET_DEVICE1_PCI_STATE_CONFIG_RETRY(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE1_PCI_STATE_CONFIG_RETRY(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE1_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_SHIFT 16u -#define DEVICE1_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_MASK 0x10000u -#define GET_DEVICE1_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE1_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE1_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_SHIFT 17u -#define DEVICE1_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_MASK 0x20000u -#define GET_DEVICE1_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__reg__) (((__reg__) & 0x20000) >> 17u) -#define SET_DEVICE1_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__val__) (((__val__) << 17u) & 0x20000u) -#define DEVICE1_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_SHIFT 18u -#define DEVICE1_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_MASK 0x40000u -#define GET_DEVICE1_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) -#define SET_DEVICE1_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) -#define DEVICE1_PCI_STATE_GENERATE_RESET_PLUS_SHIFT 19u -#define DEVICE1_PCI_STATE_GENERATE_RESET_PLUS_MASK 0x80000u -#define GET_DEVICE1_PCI_STATE_GENERATE_RESET_PLUS(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE1_PCI_STATE_GENERATE_RESET_PLUS(__val__) (((__val__) << 19u) & 0x80000u) - #define REG_DEVICE1_REGISTER_BASE ((volatile APE_DEVICE1_H_uint32_t*)0xa0050078) /* Local controller memory address of a register than can be written or read by writing to the register data register. */ #define REG_DEVICE1_MEMORY_BASE ((volatile APE_DEVICE1_H_uint32_t*)0xa005007c) /* Local controller memory address of the NIC memory region that can be accessed via Memory Window data register. */ #define REG_DEVICE1_REGISTER_DATA ((volatile APE_DEVICE1_H_uint32_t*)0xa0050080) /* Register Data at the location pointed by the Register Base Register. */ #define REG_DEVICE1_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX ((volatile APE_DEVICE1_H_uint32_t*)0xa0050088) /* UNDI Receive Return Ring Consumer Index Mailbox */ #define REG_DEVICE1_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa005008c) /* UNDI Receive Return Ring Consumer Index Mailbox */ #define REG_DEVICE1_LINK_STATUS_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa00500bc) /* PCIe standard register. */ -#define DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_SHIFT 16u -#define DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_MASK 0xf0000u -#define GET_DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__reg__) (((__reg__) & 0xf0000) >> 16u) -#define SET_DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__val__) (((__val__) << 16u) & 0xf0000u) -#define DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_1_0 0x1u -#define DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_2_0 0x2u - -#define DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20u -#define DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x3f00000u -#define GET_DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__reg__) (((__reg__) & 0x3f00000) >> 20u) -#define SET_DEVICE1_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__val__) (((__val__) << 20u) & 0x3f00000u) - #define REG_DEVICE1_APE_MEMORY_BASE ((volatile APE_DEVICE1_H_uint32_t*)0xa00500f8) /* APE Memory address to read/write using the APE Memory Data register.. */ #define REG_DEVICE1_APE_MEMORY_DATA ((volatile APE_DEVICE1_H_uint32_t*)0xa00500fc) /* APE Memory value at the location pointed by the Memory Base Register. */ #define REG_DEVICE1_EMAC_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0050400) /* */ -#define DEVICE1_EMAC_MODE_GLOBAL_RESET_SHIFT 0u -#define DEVICE1_EMAC_MODE_GLOBAL_RESET_MASK 0x1u -#define GET_DEVICE1_EMAC_MODE_GLOBAL_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE1_EMAC_MODE_GLOBAL_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE1_EMAC_MODE_HALF_DUPLEX_SHIFT 1u -#define DEVICE1_EMAC_MODE_HALF_DUPLEX_MASK 0x2u -#define GET_DEVICE1_EMAC_MODE_HALF_DUPLEX(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_EMAC_MODE_HALF_DUPLEX(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_EMAC_MODE_PORT_MODE_SHIFT 2u -#define DEVICE1_EMAC_MODE_PORT_MODE_MASK 0xcu -#define GET_DEVICE1_EMAC_MODE_PORT_MODE(__reg__) (((__reg__) & 0xc) >> 2u) -#define SET_DEVICE1_EMAC_MODE_PORT_MODE(__val__) (((__val__) << 2u) & 0xcu) -#define DEVICE1_EMAC_MODE_PORT_MODE_NONE 0x0u -#define DEVICE1_EMAC_MODE_PORT_MODE_10_DIV_100 0x1u -#define DEVICE1_EMAC_MODE_PORT_MODE_1000 0x2u -#define DEVICE1_EMAC_MODE_PORT_MODE_TBI 0x3u - -#define DEVICE1_EMAC_MODE_LOOPBACK_MODE_SHIFT 4u -#define DEVICE1_EMAC_MODE_LOOPBACK_MODE_MASK 0x10u -#define GET_DEVICE1_EMAC_MODE_LOOPBACK_MODE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE1_EMAC_MODE_LOOPBACK_MODE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE1_EMAC_MODE_TAGGED_MAC_CONTROL_SHIFT 7u -#define DEVICE1_EMAC_MODE_TAGGED_MAC_CONTROL_MASK 0x80u -#define GET_DEVICE1_EMAC_MODE_TAGGED_MAC_CONTROL(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE1_EMAC_MODE_TAGGED_MAC_CONTROL(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE1_EMAC_MODE_ENABLE_TX_BURSTING_SHIFT 8u -#define DEVICE1_EMAC_MODE_ENABLE_TX_BURSTING_MASK 0x100u -#define GET_DEVICE1_EMAC_MODE_ENABLE_TX_BURSTING(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE1_EMAC_MODE_ENABLE_TX_BURSTING(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE1_EMAC_MODE_MAX_DEFER_SHIFT 9u -#define DEVICE1_EMAC_MODE_MAX_DEFER_MASK 0x200u -#define GET_DEVICE1_EMAC_MODE_MAX_DEFER(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE1_EMAC_MODE_MAX_DEFER(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE1_EMAC_MODE_ENABLE_RX_STATISTICS_SHIFT 11u -#define DEVICE1_EMAC_MODE_ENABLE_RX_STATISTICS_MASK 0x800u -#define GET_DEVICE1_EMAC_MODE_ENABLE_RX_STATISTICS(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE1_EMAC_MODE_ENABLE_RX_STATISTICS(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE1_EMAC_MODE_CLEAR_RX_STATISTICS_SHIFT 12u -#define DEVICE1_EMAC_MODE_CLEAR_RX_STATISTICS_MASK 0x1000u -#define GET_DEVICE1_EMAC_MODE_CLEAR_RX_STATISTICS(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_DEVICE1_EMAC_MODE_CLEAR_RX_STATISTICS(__val__) (((__val__) << 12u) & 0x1000u) -#define DEVICE1_EMAC_MODE_FLUSH_RX_STATISTICS_SHIFT 13u -#define DEVICE1_EMAC_MODE_FLUSH_RX_STATISTICS_MASK 0x2000u -#define GET_DEVICE1_EMAC_MODE_FLUSH_RX_STATISTICS(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE1_EMAC_MODE_FLUSH_RX_STATISTICS(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE1_EMAC_MODE_ENABLE_TX_STATISTICS_SHIFT 14u -#define DEVICE1_EMAC_MODE_ENABLE_TX_STATISTICS_MASK 0x4000u -#define GET_DEVICE1_EMAC_MODE_ENABLE_TX_STATISTICS(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE1_EMAC_MODE_ENABLE_TX_STATISTICS(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE1_EMAC_MODE_CLEAR_TX_STATISTICS_SHIFT 15u -#define DEVICE1_EMAC_MODE_CLEAR_TX_STATISTICS_MASK 0x8000u -#define GET_DEVICE1_EMAC_MODE_CLEAR_TX_STATISTICS(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE1_EMAC_MODE_CLEAR_TX_STATISTICS(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE1_EMAC_MODE_FLUSH_TX_STATISTICS_SHIFT 16u -#define DEVICE1_EMAC_MODE_FLUSH_TX_STATISTICS_MASK 0x10000u -#define GET_DEVICE1_EMAC_MODE_FLUSH_TX_STATISTICS(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE1_EMAC_MODE_FLUSH_TX_STATISTICS(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE1_EMAC_MODE_SEND_CONFIG_COMMAND_SHIFT 17u -#define DEVICE1_EMAC_MODE_SEND_CONFIG_COMMAND_MASK 0x20000u -#define GET_DEVICE1_EMAC_MODE_SEND_CONFIG_COMMAND(__reg__) (((__reg__) & 0x20000) >> 17u) -#define SET_DEVICE1_EMAC_MODE_SEND_CONFIG_COMMAND(__val__) (((__val__) << 17u) & 0x20000u) -#define DEVICE1_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_SHIFT 18u -#define DEVICE1_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_MASK 0x40000u -#define GET_DEVICE1_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) -#define SET_DEVICE1_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) -#define DEVICE1_EMAC_MODE_ACPI_POWER_ON_ENABLE_SHIFT 19u -#define DEVICE1_EMAC_MODE_ACPI_POWER_ON_ENABLE_MASK 0x80000u -#define GET_DEVICE1_EMAC_MODE_ACPI_POWER_ON_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE1_EMAC_MODE_ACPI_POWER_ON_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) -#define DEVICE1_EMAC_MODE_ENABLE_TCE_SHIFT 21u -#define DEVICE1_EMAC_MODE_ENABLE_TCE_MASK 0x200000u -#define GET_DEVICE1_EMAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x200000) >> 21u) -#define SET_DEVICE1_EMAC_MODE_ENABLE_TCE(__val__) (((__val__) << 21u) & 0x200000u) -#define DEVICE1_EMAC_MODE_ENABLE_RDE_SHIFT 22u -#define DEVICE1_EMAC_MODE_ENABLE_RDE_MASK 0x400000u -#define GET_DEVICE1_EMAC_MODE_ENABLE_RDE(__reg__) (((__reg__) & 0x400000) >> 22u) -#define SET_DEVICE1_EMAC_MODE_ENABLE_RDE(__val__) (((__val__) << 22u) & 0x400000u) -#define DEVICE1_EMAC_MODE_ENABLE_FHDE_SHIFT 23u -#define DEVICE1_EMAC_MODE_ENABLE_FHDE_MASK 0x800000u -#define GET_DEVICE1_EMAC_MODE_ENABLE_FHDE(__reg__) (((__reg__) & 0x800000) >> 23u) -#define SET_DEVICE1_EMAC_MODE_ENABLE_FHDE(__val__) (((__val__) << 23u) & 0x800000u) -#define DEVICE1_EMAC_MODE_KEEP_FRAME_IN_WOL_SHIFT 24u -#define DEVICE1_EMAC_MODE_KEEP_FRAME_IN_WOL_MASK 0x1000000u -#define GET_DEVICE1_EMAC_MODE_KEEP_FRAME_IN_WOL(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_DEVICE1_EMAC_MODE_KEEP_FRAME_IN_WOL(__val__) (((__val__) << 24u) & 0x1000000u) -#define DEVICE1_EMAC_MODE_HALT_INTERESTING_PACKET_PME_SHIFT 25u -#define DEVICE1_EMAC_MODE_HALT_INTERESTING_PACKET_PME_MASK 0x2000000u -#define GET_DEVICE1_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_DEVICE1_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__val__) (((__val__) << 25u) & 0x2000000u) -#define DEVICE1_EMAC_MODE_FREE_RUNNING_ACPI_SHIFT 26u -#define DEVICE1_EMAC_MODE_FREE_RUNNING_ACPI_MASK 0x4000000u -#define GET_DEVICE1_EMAC_MODE_FREE_RUNNING_ACPI(__reg__) (((__reg__) & 0x4000000) >> 26u) -#define SET_DEVICE1_EMAC_MODE_FREE_RUNNING_ACPI(__val__) (((__val__) << 26u) & 0x4000000u) -#define DEVICE1_EMAC_MODE_ENABLE_APE_RX_PATH_SHIFT 27u -#define DEVICE1_EMAC_MODE_ENABLE_APE_RX_PATH_MASK 0x8000000u -#define GET_DEVICE1_EMAC_MODE_ENABLE_APE_RX_PATH(__reg__) (((__reg__) & 0x8000000) >> 27u) -#define SET_DEVICE1_EMAC_MODE_ENABLE_APE_RX_PATH(__val__) (((__val__) << 27u) & 0x8000000u) -#define DEVICE1_EMAC_MODE_ENABLE_APE_TX_PATH_SHIFT 28u -#define DEVICE1_EMAC_MODE_ENABLE_APE_TX_PATH_MASK 0x10000000u -#define GET_DEVICE1_EMAC_MODE_ENABLE_APE_TX_PATH(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_DEVICE1_EMAC_MODE_ENABLE_APE_TX_PATH(__val__) (((__val__) << 28u) & 0x10000000u) -#define DEVICE1_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_SHIFT 29u -#define DEVICE1_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_MASK 0x20000000u -#define GET_DEVICE1_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_DEVICE1_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__val__) (((__val__) << 29u) & 0x20000000u) - #define REG_DEVICE1_LED_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa005040c) /* */ -#define DEVICE1_LED_CONTROL_OVERRIDE_LINK_SHIFT 0u -#define DEVICE1_LED_CONTROL_OVERRIDE_LINK_MASK 0x1u -#define GET_DEVICE1_LED_CONTROL_OVERRIDE_LINK(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE1_LED_CONTROL_OVERRIDE_LINK(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE1_LED_CONTROL_LED_1000_SHIFT 1u -#define DEVICE1_LED_CONTROL_LED_1000_MASK 0x2u -#define GET_DEVICE1_LED_CONTROL_LED_1000(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_LED_CONTROL_LED_1000(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_LED_CONTROL_LED_100_SHIFT 2u -#define DEVICE1_LED_CONTROL_LED_100_MASK 0x4u -#define GET_DEVICE1_LED_CONTROL_LED_100(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE1_LED_CONTROL_LED_100(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE1_LED_CONTROL_LED_10_SHIFT 3u -#define DEVICE1_LED_CONTROL_LED_10_MASK 0x8u -#define GET_DEVICE1_LED_CONTROL_LED_10(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE1_LED_CONTROL_LED_10(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE1_LED_CONTROL_OVERRIDE_TRAFFIC_SHIFT 4u -#define DEVICE1_LED_CONTROL_OVERRIDE_TRAFFIC_MASK 0x10u -#define GET_DEVICE1_LED_CONTROL_OVERRIDE_TRAFFIC(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE1_LED_CONTROL_OVERRIDE_TRAFFIC(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE1_LED_CONTROL_LED_TRAFFIC_BLINK_SHIFT 5u -#define DEVICE1_LED_CONTROL_LED_TRAFFIC_BLINK_MASK 0x20u -#define GET_DEVICE1_LED_CONTROL_LED_TRAFFIC_BLINK(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE1_LED_CONTROL_LED_TRAFFIC_BLINK(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE1_LED_CONTROL_LED_TRAFFIC_SHIFT 6u -#define DEVICE1_LED_CONTROL_LED_TRAFFIC_MASK 0x40u -#define GET_DEVICE1_LED_CONTROL_LED_TRAFFIC(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE1_LED_CONTROL_LED_TRAFFIC(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE1_LED_CONTROL_LED_STATUS_1000_SHIFT 7u -#define DEVICE1_LED_CONTROL_LED_STATUS_1000_MASK 0x80u -#define GET_DEVICE1_LED_CONTROL_LED_STATUS_1000(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE1_LED_CONTROL_LED_STATUS_1000(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE1_LED_CONTROL_LED_STATUS_100_SHIFT 8u -#define DEVICE1_LED_CONTROL_LED_STATUS_100_MASK 0x100u -#define GET_DEVICE1_LED_CONTROL_LED_STATUS_100(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE1_LED_CONTROL_LED_STATUS_100(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE1_LED_CONTROL_LED_STATUS_10_SHIFT 9u -#define DEVICE1_LED_CONTROL_LED_STATUS_10_MASK 0x200u -#define GET_DEVICE1_LED_CONTROL_LED_STATUS_10(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE1_LED_CONTROL_LED_STATUS_10(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE1_LED_CONTROL_LED_STATUS_TRAFFIC_SHIFT 10u -#define DEVICE1_LED_CONTROL_LED_STATUS_TRAFFIC_MASK 0x400u -#define GET_DEVICE1_LED_CONTROL_LED_STATUS_TRAFFIC(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE1_LED_CONTROL_LED_STATUS_TRAFFIC(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE1_LED_CONTROL_LED_MODE_SHIFT 11u -#define DEVICE1_LED_CONTROL_LED_MODE_MASK 0x1800u -#define GET_DEVICE1_LED_CONTROL_LED_MODE(__reg__) (((__reg__) & 0x1800) >> 11u) -#define SET_DEVICE1_LED_CONTROL_LED_MODE(__val__) (((__val__) << 11u) & 0x1800u) -#define DEVICE1_LED_CONTROL_LED_MODE_MAC 0x0u -#define DEVICE1_LED_CONTROL_LED_MODE_PHY_MODE_1 0x1u -#define DEVICE1_LED_CONTROL_LED_MODE_PHY_MODE_2 0x2u -#define DEVICE1_LED_CONTROL_LED_MODE_PHY_MODE_1_ 0x3u - -#define DEVICE1_LED_CONTROL_MAC_MODE_SHIFT 13u -#define DEVICE1_LED_CONTROL_MAC_MODE_MASK 0x2000u -#define GET_DEVICE1_LED_CONTROL_MAC_MODE(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE1_LED_CONTROL_MAC_MODE(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE1_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_SHIFT 14u -#define DEVICE1_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_MASK 0x4000u -#define GET_DEVICE1_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE1_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE1_LED_CONTROL_BLINK_PERIOD_SHIFT 19u -#define DEVICE1_LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000u -#define GET_DEVICE1_LED_CONTROL_BLINK_PERIOD(__reg__) (((__reg__) & 0x7ff80000) >> 19u) -#define SET_DEVICE1_LED_CONTROL_BLINK_PERIOD(__val__) (((__val__) << 19u) & 0x7ff80000u) -#define DEVICE1_LED_CONTROL_OVERRIDE_BLINK_RATE_SHIFT 31u -#define DEVICE1_LED_CONTROL_OVERRIDE_BLINK_RATE_MASK 0x80000000u -#define GET_DEVICE1_LED_CONTROL_OVERRIDE_BLINK_RATE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE1_LED_CONTROL_OVERRIDE_BLINK_RATE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE1_EMAC_MAC_ADDRESSES_0_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050410) /* Upper 2-bytes of this node's MAC address. */ #define REG_DEVICE1_EMAC_MAC_ADDRESSES_0_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa0050414) /* Lower 4-byte of this node's MAC address. */ #define REG_DEVICE1_EMAC_MAC_ADDRESSES_1_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050418) /* Upper 2-bytes of this node's MAC address. */ @@ -421,671 +105,40 @@ typedef uint32_t APE_DEVICE1_H_uint32_t; #define REG_DEVICE1_WOL_PATTERN_POINTER ((volatile APE_DEVICE1_H_uint32_t*)0xa0050430) /* Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary). */ #define REG_DEVICE1_WOL_PATTERN_CFG ((volatile APE_DEVICE1_H_uint32_t*)0xa0050434) /* */ #define REG_DEVICE1_MTU_SIZE ((volatile APE_DEVICE1_H_uint32_t*)0xa005043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */ -#define DEVICE1_MTU_SIZE_MTU_SHIFT 0u -#define DEVICE1_MTU_SIZE_MTU_MASK 0xffffu -#define GET_DEVICE1_MTU_SIZE_MTU(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE1_MTU_SIZE_MTU(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE1_MII_COMMUNICATION ((volatile APE_DEVICE1_H_uint32_t*)0xa005044c) /* */ -#define DEVICE1_MII_COMMUNICATION_TRANSACTION_DATA_SHIFT 0u -#define DEVICE1_MII_COMMUNICATION_TRANSACTION_DATA_MASK 0xffffu -#define GET_DEVICE1_MII_COMMUNICATION_TRANSACTION_DATA(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE1_MII_COMMUNICATION_TRANSACTION_DATA(__val__) (((__val__) << 0u) & 0xffffu) -#define DEVICE1_MII_COMMUNICATION_REGISTER_ADDRESS_SHIFT 16u -#define DEVICE1_MII_COMMUNICATION_REGISTER_ADDRESS_MASK 0x1f0000u -#define GET_DEVICE1_MII_COMMUNICATION_REGISTER_ADDRESS(__reg__) (((__reg__) & 0x1f0000) >> 16u) -#define SET_DEVICE1_MII_COMMUNICATION_REGISTER_ADDRESS(__val__) (((__val__) << 16u) & 0x1f0000u) -#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_SHIFT 21u -#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_MASK 0x3e00000u -#define GET_DEVICE1_MII_COMMUNICATION_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e00000) >> 21u) -#define SET_DEVICE1_MII_COMMUNICATION_PHY_ADDRESS(__val__) (((__val__) << 21u) & 0x3e00000u) -#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_PHY_0 0x1u -#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_PHY_1 0x2u -#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_PHY_2 0x3u -#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_PHY_3 0x4u -#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0 0x8u -#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_SGMII_1 0x9u -#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_SGMII_2 0xau -#define DEVICE1_MII_COMMUNICATION_PHY_ADDRESS_SGMII_3 0xbu - -#define DEVICE1_MII_COMMUNICATION_COMMAND_SHIFT 26u -#define DEVICE1_MII_COMMUNICATION_COMMAND_MASK 0xc000000u -#define GET_DEVICE1_MII_COMMUNICATION_COMMAND(__reg__) (((__reg__) & 0xc000000) >> 26u) -#define SET_DEVICE1_MII_COMMUNICATION_COMMAND(__val__) (((__val__) << 26u) & 0xc000000u) -#define DEVICE1_MII_COMMUNICATION_COMMAND_WRITE 0x1u -#define DEVICE1_MII_COMMUNICATION_COMMAND_READ 0x2u - -#define DEVICE1_MII_COMMUNICATION_READ_FAILED_SHIFT 28u -#define DEVICE1_MII_COMMUNICATION_READ_FAILED_MASK 0x10000000u -#define GET_DEVICE1_MII_COMMUNICATION_READ_FAILED(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_DEVICE1_MII_COMMUNICATION_READ_FAILED(__val__) (((__val__) << 28u) & 0x10000000u) -#define DEVICE1_MII_COMMUNICATION_START_DIV_BUSY_SHIFT 29u -#define DEVICE1_MII_COMMUNICATION_START_DIV_BUSY_MASK 0x20000000u -#define GET_DEVICE1_MII_COMMUNICATION_START_DIV_BUSY(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_DEVICE1_MII_COMMUNICATION_START_DIV_BUSY(__val__) (((__val__) << 29u) & 0x20000000u) - #define REG_DEVICE1_MII_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0050454) /* */ -#define DEVICE1_MII_MODE_PHY_ADDRESS_SHIFT 5u -#define DEVICE1_MII_MODE_PHY_ADDRESS_MASK 0x3e0u -#define GET_DEVICE1_MII_MODE_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e0) >> 5u) -#define SET_DEVICE1_MII_MODE_PHY_ADDRESS(__val__) (((__val__) << 5u) & 0x3e0u) -#define DEVICE1_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_SHIFT 15u -#define DEVICE1_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_MASK 0x8000u -#define GET_DEVICE1_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE1_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE1_MII_MODE_MII_CLOCK_COUNT_SHIFT 16u -#define DEVICE1_MII_MODE_MII_CLOCK_COUNT_MASK 0x1f0000u -#define GET_DEVICE1_MII_MODE_MII_CLOCK_COUNT(__reg__) (((__reg__) & 0x1f0000) >> 16u) -#define SET_DEVICE1_MII_MODE_MII_CLOCK_COUNT(__val__) (((__val__) << 16u) & 0x1f0000u) - #define REG_DEVICE1_TRANSMIT_MAC_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa005045c) /* */ -#define DEVICE1_TRANSMIT_MAC_MODE_RESET_SHIFT 0u -#define DEVICE1_TRANSMIT_MAC_MODE_RESET_MASK 0x1u -#define GET_DEVICE1_TRANSMIT_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE1_TRANSMIT_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TCE_SHIFT 1u -#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TCE_MASK 0x2u -#define GET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TCE(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_SHIFT 4u -#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_MASK 0x10u -#define GET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_SHIFT 5u -#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_MASK 0x20u -#define GET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_SHIFT 6u -#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_MASK 0x40u -#define GET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE1_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_SHIFT 7u -#define DEVICE1_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_MASK 0x80u -#define GET_DEVICE1_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE1_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE1_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_SHIFT 8u -#define DEVICE1_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_MASK 0x100u -#define GET_DEVICE1_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE1_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_SHIFT 9u -#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_MASK 0x200u -#define GET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_SHIFT 10u -#define DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_MASK 0x400u -#define GET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE1_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__val__) (((__val__) << 10u) & 0x400u) - #define REG_DEVICE1_RECEIVE_MAC_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0050468) /* */ -#define DEVICE1_RECEIVE_MAC_MODE_RESET_SHIFT 0u -#define DEVICE1_RECEIVE_MAC_MODE_RESET_MASK 0x1u -#define GET_DEVICE1_RECEIVE_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE1_RECEIVE_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE1_RECEIVE_MAC_MODE_ENABLE_SHIFT 1u -#define DEVICE1_RECEIVE_MAC_MODE_ENABLE_MASK 0x2u -#define GET_DEVICE1_RECEIVE_MAC_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_RECEIVE_MAC_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_SHIFT 8u -#define DEVICE1_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_MASK 0x100u -#define GET_DEVICE1_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE1_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE1_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_SHIFT 25u -#define DEVICE1_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_MASK 0x2000000u -#define GET_DEVICE1_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_DEVICE1_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__val__) (((__val__) << 25u) & 0x2000000u) - #define REG_DEVICE1_PERFECT_MATCH1_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050540) /* */ -#define DEVICE1_PERFECT_MATCH1_HIGH_HIGH_SHIFT 0u -#define DEVICE1_PERFECT_MATCH1_HIGH_HIGH_MASK 0xffffu -#define GET_DEVICE1_PERFECT_MATCH1_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE1_PERFECT_MATCH1_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE1_PERFECT_MATCH1_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa0050544) /* */ -#define DEVICE1_PERFECT_MATCH1_LOW_LOW_SHIFT 0u -#define DEVICE1_PERFECT_MATCH1_LOW_LOW_MASK 0xffffffffu -#define GET_DEVICE1_PERFECT_MATCH1_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE1_PERFECT_MATCH1_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) - #define REG_DEVICE1_PERFECT_MATCH2_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050548) /* */ -#define DEVICE1_PERFECT_MATCH2_HIGH_HIGH_SHIFT 0u -#define DEVICE1_PERFECT_MATCH2_HIGH_HIGH_MASK 0xffffu -#define GET_DEVICE1_PERFECT_MATCH2_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE1_PERFECT_MATCH2_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE1_PERFECT_MATCH2_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa005054c) /* */ -#define DEVICE1_PERFECT_MATCH2_LOW_LOW_SHIFT 0u -#define DEVICE1_PERFECT_MATCH2_LOW_LOW_MASK 0xffffffffu -#define GET_DEVICE1_PERFECT_MATCH2_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE1_PERFECT_MATCH2_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) - #define REG_DEVICE1_PERFECT_MATCH3_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050550) /* */ -#define DEVICE1_PERFECT_MATCH3_HIGH_HIGH_SHIFT 0u -#define DEVICE1_PERFECT_MATCH3_HIGH_HIGH_MASK 0xffffu -#define GET_DEVICE1_PERFECT_MATCH3_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE1_PERFECT_MATCH3_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE1_PERFECT_MATCH3_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa0050554) /* */ -#define DEVICE1_PERFECT_MATCH3_LOW_LOW_SHIFT 0u -#define DEVICE1_PERFECT_MATCH3_LOW_LOW_MASK 0xffffffffu -#define GET_DEVICE1_PERFECT_MATCH3_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE1_PERFECT_MATCH3_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) - #define REG_DEVICE1_PERFECT_MATCH4_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0050558) /* */ -#define DEVICE1_PERFECT_MATCH4_HIGH_HIGH_SHIFT 0u -#define DEVICE1_PERFECT_MATCH4_HIGH_HIGH_MASK 0xffffu -#define GET_DEVICE1_PERFECT_MATCH4_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE1_PERFECT_MATCH4_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE1_PERFECT_MATCH4_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa005055c) /* */ -#define DEVICE1_PERFECT_MATCH4_LOW_LOW_SHIFT 0u -#define DEVICE1_PERFECT_MATCH4_LOW_LOW_MASK 0xffffffffu -#define GET_DEVICE1_PERFECT_MATCH4_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE1_PERFECT_MATCH4_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) - #define REG_DEVICE1_SGMII_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa00505b4) /* This register reflects various status of the respective SGMII port when enabled. */ -#define DEVICE1_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 0u -#define DEVICE1_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x1u -#define GET_DEVICE1_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE1_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE1_SGMII_STATUS_LINK_STATUS_SHIFT 1u -#define DEVICE1_SGMII_STATUS_LINK_STATUS_MASK 0x2u -#define GET_DEVICE1_SGMII_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_SGMII_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_SGMII_STATUS_DUPLEX_STATUS_SHIFT 2u -#define DEVICE1_SGMII_STATUS_DUPLEX_STATUS_MASK 0x4u -#define GET_DEVICE1_SGMII_STATUS_DUPLEX_STATUS(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE1_SGMII_STATUS_DUPLEX_STATUS(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE1_SGMII_STATUS_SPEED_1000_SHIFT 3u -#define DEVICE1_SGMII_STATUS_SPEED_1000_MASK 0x8u -#define GET_DEVICE1_SGMII_STATUS_SPEED_1000(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE1_SGMII_STATUS_SPEED_1000(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE1_SGMII_STATUS_SPEED_100_SHIFT 4u -#define DEVICE1_SGMII_STATUS_SPEED_100_MASK 0x10u -#define GET_DEVICE1_SGMII_STATUS_SPEED_100(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE1_SGMII_STATUS_SPEED_100(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE1_SGMII_STATUS_NEXT_PAGE_RX_SHIFT 5u -#define DEVICE1_SGMII_STATUS_NEXT_PAGE_RX_MASK 0x20u -#define GET_DEVICE1_SGMII_STATUS_NEXT_PAGE_RX(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE1_SGMII_STATUS_NEXT_PAGE_RX(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE1_SGMII_STATUS_PAUSE_RX_SHIFT 6u -#define DEVICE1_SGMII_STATUS_PAUSE_RX_MASK 0x40u -#define GET_DEVICE1_SGMII_STATUS_PAUSE_RX(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE1_SGMII_STATUS_PAUSE_RX(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE1_SGMII_STATUS_PAUSE_TX_SHIFT 7u -#define DEVICE1_SGMII_STATUS_PAUSE_TX_MASK 0x80u -#define GET_DEVICE1_SGMII_STATUS_PAUSE_TX(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE1_SGMII_STATUS_PAUSE_TX(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE1_SGMII_STATUS_MEDIA_SELECTION_MODE_SHIFT 8u -#define DEVICE1_SGMII_STATUS_MEDIA_SELECTION_MODE_MASK 0x100u -#define GET_DEVICE1_SGMII_STATUS_MEDIA_SELECTION_MODE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE1_SGMII_STATUS_MEDIA_SELECTION_MODE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE1_SGMII_STATUS_MEDIA_SELECTION_MODE_COPPER 0x0u -#define DEVICE1_SGMII_STATUS_MEDIA_SELECTION_MODE_SGMII 0x1u - -#define DEVICE1_SGMII_STATUS_PCS_CRS_DETECT_SHIFT 9u -#define DEVICE1_SGMII_STATUS_PCS_CRS_DETECT_MASK 0x200u -#define GET_DEVICE1_SGMII_STATUS_PCS_CRS_DETECT(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE1_SGMII_STATUS_PCS_CRS_DETECT(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE1_SGMII_STATUS_EXTERNAL_CRS_DETECT_SHIFT 10u -#define DEVICE1_SGMII_STATUS_EXTERNAL_CRS_DETECT_MASK 0x400u -#define GET_DEVICE1_SGMII_STATUS_EXTERNAL_CRS_DETECT(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE1_SGMII_STATUS_EXTERNAL_CRS_DETECT(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE1_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_SHIFT 16u -#define DEVICE1_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_MASK 0xffff0000u -#define GET_DEVICE1_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_DEVICE1_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_DEVICE1_CPMU_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0053600) /* */ -#define DEVICE1_CPMU_CONTROL_CPMU_SOFTWARE_RESET_SHIFT 0u -#define DEVICE1_CPMU_CONTROL_CPMU_SOFTWARE_RESET_MASK 0x1u -#define GET_DEVICE1_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE1_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE1_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 1u -#define DEVICE1_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x2u -#define GET_DEVICE1_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_CPMU_CONTROL_POWER_DOWN_SHIFT 2u -#define DEVICE1_CPMU_CONTROL_POWER_DOWN_MASK 0x4u -#define GET_DEVICE1_CPMU_CONTROL_POWER_DOWN(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE1_CPMU_CONTROL_POWER_DOWN(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE1_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_SHIFT 4u -#define DEVICE1_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_MASK 0x10u -#define GET_DEVICE1_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE1_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE1_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_SHIFT 5u -#define DEVICE1_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_MASK 0x20u -#define GET_DEVICE1_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE1_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE1_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_SHIFT 9u -#define DEVICE1_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_MASK 0x200u -#define GET_DEVICE1_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE1_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE1_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_SHIFT 10u -#define DEVICE1_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_MASK 0x400u -#define GET_DEVICE1_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE1_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE1_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_SHIFT 14u -#define DEVICE1_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_MASK 0x4000u -#define GET_DEVICE1_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE1_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE1_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_SHIFT 16u -#define DEVICE1_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_MASK 0x10000u -#define GET_DEVICE1_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE1_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE1_CPMU_CONTROL_LEGACY_TIMER_ENABLE_SHIFT 18u -#define DEVICE1_CPMU_CONTROL_LEGACY_TIMER_ENABLE_MASK 0x40000u -#define GET_DEVICE1_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) -#define SET_DEVICE1_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) -#define DEVICE1_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_SHIFT 19u -#define DEVICE1_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_MASK 0x80000u -#define GET_DEVICE1_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE1_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 19u) & 0x80000u) -#define DEVICE1_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_SHIFT 28u -#define DEVICE1_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_MASK 0x10000000u -#define GET_DEVICE1_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_DEVICE1_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__val__) (((__val__) << 28u) & 0x10000000u) - #define REG_DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE1_H_uint32_t*)0xa0053610) /* */ -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u -#define GET_DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) -#define SET_DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_60_0MHZ 0x1u -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_30_0MHZ 0x3u -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_15_0MHZ 0x5u -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_7_5MHZ 0x7u -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_75MHZ 0x9u -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ 0x11u -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_6_25MHZ 0x13u -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_125MHZ 0x15u -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_1_563MHZ 0x17u -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_781KHZ 0x19u -#define DEVICE1_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ_DIV_1_25MHZ 0x1fu - - #define REG_DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY ((volatile APE_DEVICE1_H_uint32_t*)0xa0053624) /* */ -#define DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u -#define DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u -#define GET_DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) -#define SET_DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) -#define DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_SHIFT 31u -#define DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_MASK 0x80000000u -#define GET_DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE1_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE1_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa005362c) /* */ -#define DEVICE1_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_SHIFT 0u -#define DEVICE1_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_MASK 0xfu -#define GET_DEVICE1_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__reg__) (((__reg__) & 0xf) >> 0u) -#define SET_DEVICE1_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__val__) (((__val__) << 0u) & 0xfu) -#define DEVICE1_STATUS_CPMU_POWER_STATE_SHIFT 4u -#define DEVICE1_STATUS_CPMU_POWER_STATE_MASK 0x70u -#define GET_DEVICE1_STATUS_CPMU_POWER_STATE(__reg__) (((__reg__) & 0x70) >> 4u) -#define SET_DEVICE1_STATUS_CPMU_POWER_STATE(__val__) (((__val__) << 4u) & 0x70u) -#define DEVICE1_STATUS_ENERGY_DETECT_STATUS_SHIFT 7u -#define DEVICE1_STATUS_ENERGY_DETECT_STATUS_MASK 0x80u -#define GET_DEVICE1_STATUS_ENERGY_DETECT_STATUS(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE1_STATUS_ENERGY_DETECT_STATUS(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE1_STATUS_POWER_STATE_SHIFT 8u -#define DEVICE1_STATUS_POWER_STATE_MASK 0x300u -#define GET_DEVICE1_STATUS_POWER_STATE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE1_STATUS_POWER_STATE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE1_STATUS_VMAIN_POWER_STATUS_SHIFT 13u -#define DEVICE1_STATUS_VMAIN_POWER_STATUS_MASK 0x2000u -#define GET_DEVICE1_STATUS_VMAIN_POWER_STATUS(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE1_STATUS_VMAIN_POWER_STATUS(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_SHIFT 14u -#define DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_MASK 0x4000u -#define GET_DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_SHIFT 15u -#define DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_MASK 0x8000u -#define GET_DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE1_STATUS_NCSI_DLL_LOCK_STATUS_SHIFT 16u -#define DEVICE1_STATUS_NCSI_DLL_LOCK_STATUS_MASK 0x10000u -#define GET_DEVICE1_STATUS_NCSI_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE1_STATUS_NCSI_DLL_LOCK_STATUS(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE1_STATUS_GPHY_DLL_LOCK_STATUS_SHIFT 17u -#define DEVICE1_STATUS_GPHY_DLL_LOCK_STATUS_MASK 0x20000u -#define GET_DEVICE1_STATUS_GPHY_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x20000) >> 17u) -#define SET_DEVICE1_STATUS_GPHY_DLL_LOCK_STATUS(__val__) (((__val__) << 17u) & 0x20000u) -#define DEVICE1_STATUS_LINK_IDLE_STATUS_SHIFT 18u -#define DEVICE1_STATUS_LINK_IDLE_STATUS_MASK 0x40000u -#define GET_DEVICE1_STATUS_LINK_IDLE_STATUS(__reg__) (((__reg__) & 0x40000) >> 18u) -#define SET_DEVICE1_STATUS_LINK_IDLE_STATUS(__val__) (((__val__) << 18u) & 0x40000u) -#define DEVICE1_STATUS_ETHERNET_LINK_STATUS_SHIFT 19u -#define DEVICE1_STATUS_ETHERNET_LINK_STATUS_MASK 0x180000u -#define GET_DEVICE1_STATUS_ETHERNET_LINK_STATUS(__reg__) (((__reg__) & 0x180000) >> 19u) -#define SET_DEVICE1_STATUS_ETHERNET_LINK_STATUS(__val__) (((__val__) << 19u) & 0x180000u) -#define DEVICE1_STATUS_ETHERNET_LINK_STATUS_1000_MB 0x0u -#define DEVICE1_STATUS_ETHERNET_LINK_STATUS_100_MB 0x1u -#define DEVICE1_STATUS_ETHERNET_LINK_STATUS_10_MB 0x2u -#define DEVICE1_STATUS_ETHERNET_LINK_STATUS_NO_LINK 0x3u - -#define DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_SHIFT 21u -#define DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_MASK 0x200000u -#define GET_DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x200000) >> 21u) -#define SET_DEVICE1_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 21u) & 0x200000u) -#define DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_SHIFT 22u -#define DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_MASK 0x400000u -#define GET_DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x400000) >> 22u) -#define SET_DEVICE1_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 22u) & 0x400000u) -#define DEVICE1_STATUS_APE_STATUS_SHIFT 23u -#define DEVICE1_STATUS_APE_STATUS_MASK 0x1800000u -#define GET_DEVICE1_STATUS_APE_STATUS(__reg__) (((__reg__) & 0x1800000) >> 23u) -#define SET_DEVICE1_STATUS_APE_STATUS(__val__) (((__val__) << 23u) & 0x1800000u) -#define DEVICE1_STATUS_APE_STATUS_ACTIVE 0x0u -#define DEVICE1_STATUS_APE_STATUS_SLEEP 0x1u -#define DEVICE1_STATUS_APE_STATUS_DEEP_SLEEP 0x2u - -#define DEVICE1_STATUS_FUNCTION_ENABLE_SHIFT 25u -#define DEVICE1_STATUS_FUNCTION_ENABLE_MASK 0x3e000000u -#define GET_DEVICE1_STATUS_FUNCTION_ENABLE(__reg__) (((__reg__) & 0x3e000000) >> 25u) -#define SET_DEVICE1_STATUS_FUNCTION_ENABLE(__val__) (((__val__) << 25u) & 0x3e000000u) -#define DEVICE1_STATUS_FUNCTION_NUMBER_SHIFT 30u -#define DEVICE1_STATUS_FUNCTION_NUMBER_MASK 0xc0000000u -#define GET_DEVICE1_STATUS_FUNCTION_NUMBER(__reg__) (((__reg__) & 0xc0000000) >> 30u) -#define SET_DEVICE1_STATUS_FUNCTION_NUMBER(__val__) (((__val__) << 30u) & 0xc0000000u) - #define REG_DEVICE1_CLOCK_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa0053630) /* */ #define REG_DEVICE1_GPHY_CONTROL_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa0053638) /* */ -#define DEVICE1_GPHY_CONTROL_STATUS_GPHY_IDDQ_SHIFT 0u -#define DEVICE1_GPHY_CONTROL_STATUS_GPHY_IDDQ_MASK 0x1u -#define GET_DEVICE1_GPHY_CONTROL_STATUS_GPHY_IDDQ(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE1_GPHY_CONTROL_STATUS_GPHY_IDDQ(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE1_GPHY_CONTROL_STATUS_BIAS_IDDQ_SHIFT 1u -#define DEVICE1_GPHY_CONTROL_STATUS_BIAS_IDDQ_MASK 0x2u -#define GET_DEVICE1_GPHY_CONTROL_STATUS_BIAS_IDDQ(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_GPHY_CONTROL_STATUS_BIAS_IDDQ(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_SHIFT 2u -#define DEVICE1_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_MASK 0x4u -#define GET_DEVICE1_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE1_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE1_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 3u -#define DEVICE1_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x8u -#define GET_DEVICE1_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE1_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE1_GPHY_CONTROL_STATUS_POWER_DOWN_SHIFT 4u -#define DEVICE1_GPHY_CONTROL_STATUS_POWER_DOWN_MASK 0x10u -#define GET_DEVICE1_GPHY_CONTROL_STATUS_POWER_DOWN(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE1_GPHY_CONTROL_STATUS_POWER_DOWN(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE1_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_SHIFT 15u -#define DEVICE1_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_MASK 0x8000u -#define GET_DEVICE1_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE1_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE1_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_SHIFT 25u -#define DEVICE1_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_MASK 0x2000000u -#define GET_DEVICE1_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_DEVICE1_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__val__) (((__val__) << 25u) & 0x2000000u) -#define DEVICE1_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_SHIFT 26u -#define DEVICE1_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_MASK 0x4000000u -#define GET_DEVICE1_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__reg__) (((__reg__) & 0x4000000) >> 26u) -#define SET_DEVICE1_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__val__) (((__val__) << 26u) & 0x4000000u) -#define DEVICE1_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_SHIFT 27u -#define DEVICE1_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_MASK 0x8000000u -#define GET_DEVICE1_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__reg__) (((__reg__) & 0x8000000) >> 27u) -#define SET_DEVICE1_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__val__) (((__val__) << 27u) & 0x8000000u) - #define REG_DEVICE1_CHIP_ID ((volatile APE_DEVICE1_H_uint32_t*)0xa0053658) /* */ #define REG_DEVICE1_MUTEX_REQUEST ((volatile APE_DEVICE1_H_uint32_t*)0xa005365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */ #define REG_DEVICE1_MUTEX_GRANT ((volatile APE_DEVICE1_H_uint32_t*)0xa0053660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */ #define REG_DEVICE1_GPHY_STRAP ((volatile APE_DEVICE1_H_uint32_t*)0xa0053664) /* */ -#define DEVICE1_GPHY_STRAP_TXMBUF_ECC_ENABLE_SHIFT 2u -#define DEVICE1_GPHY_STRAP_TXMBUF_ECC_ENABLE_MASK 0x4u -#define GET_DEVICE1_GPHY_STRAP_TXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE1_GPHY_STRAP_TXMBUF_ECC_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE1_GPHY_STRAP_RXMBUF_ECC_ENABLE_SHIFT 3u -#define DEVICE1_GPHY_STRAP_RXMBUF_ECC_ENABLE_MASK 0x8u -#define GET_DEVICE1_GPHY_STRAP_RXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE1_GPHY_STRAP_RXMBUF_ECC_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE1_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_SHIFT 4u -#define DEVICE1_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_MASK 0x10u -#define GET_DEVICE1_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE1_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__val__) (((__val__) << 4u) & 0x10u) - #define REG_DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile APE_DEVICE1_H_uint32_t*)0xa005367c) /* */ -#define DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_SHIFT 4u -#define DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_MASK 0x10u -#define GET_DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_SHIFT 5u -#define DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_MASK 0x20u -#define GET_DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE1_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__val__) (((__val__) << 5u) & 0x20u) - #define REG_DEVICE1_EEE_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa00536b0) /* */ -#define DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI_SHIFT 0u -#define DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI_MASK 0x1u -#define GET_DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI_SHIFT 1u -#define DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI_MASK 0x2u -#define GET_DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_EEE_MODE_APE_TX_DETECTION_ENABLE_SHIFT 2u -#define DEVICE1_EEE_MODE_APE_TX_DETECTION_ENABLE_MASK 0x4u -#define GET_DEVICE1_EEE_MODE_APE_TX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE1_EEE_MODE_APE_TX_DETECTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE1_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_SHIFT 3u -#define DEVICE1_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_MASK 0x8u -#define GET_DEVICE1_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE1_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE1_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_SHIFT 4u -#define DEVICE1_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_MASK 0x10u -#define GET_DEVICE1_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE1_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_SHIFT 5u -#define DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_MASK 0x20u -#define GET_DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE1_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE1_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_SHIFT 6u -#define DEVICE1_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_MASK 0x40u -#define GET_DEVICE1_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE1_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE1_EEE_MODE_USER_LPI_ENABLE_SHIFT 7u -#define DEVICE1_EEE_MODE_USER_LPI_ENABLE_MASK 0x80u -#define GET_DEVICE1_EEE_MODE_USER_LPI_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE1_EEE_MODE_USER_LPI_ENABLE(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE1_EEE_MODE_TX_LPI_ENABLE_SHIFT 8u -#define DEVICE1_EEE_MODE_TX_LPI_ENABLE_MASK 0x100u -#define GET_DEVICE1_EEE_MODE_TX_LPI_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE1_EEE_MODE_TX_LPI_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE1_EEE_MODE_RX_LPI_ENABLE_SHIFT 9u -#define DEVICE1_EEE_MODE_RX_LPI_ENABLE_MASK 0x200u -#define GET_DEVICE1_EEE_MODE_RX_LPI_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE1_EEE_MODE_RX_LPI_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE1_EEE_MODE_AUTO_WAKE_ENABLE_SHIFT 10u -#define DEVICE1_EEE_MODE_AUTO_WAKE_ENABLE_MASK 0x400u -#define GET_DEVICE1_EEE_MODE_AUTO_WAKE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE1_EEE_MODE_AUTO_WAKE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE1_EEE_MODE_BLOCK_TIME_SHIFT 11u -#define DEVICE1_EEE_MODE_BLOCK_TIME_MASK 0x7f800u -#define GET_DEVICE1_EEE_MODE_BLOCK_TIME(__reg__) (((__reg__) & 0x7f800) >> 11u) -#define SET_DEVICE1_EEE_MODE_BLOCK_TIME(__val__) (((__val__) << 11u) & 0x7f800u) -#define DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_SHIFT 19u -#define DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_MASK 0x80000u -#define GET_DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE1_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) - #define REG_DEVICE1_EEE_LINK_IDLE_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa00536bc) /* */ -#define DEVICE1_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_SHIFT 2u -#define DEVICE1_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_MASK 0x4u -#define GET_DEVICE1_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE1_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__val__) (((__val__) << 2u) & 0x4u) - #define REG_DEVICE1_EEE_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa00536d0) /* */ -#define DEVICE1_EEE_CONTROL_EXIT_TIME_SHIFT 0u -#define DEVICE1_EEE_CONTROL_EXIT_TIME_MASK 0xffffu -#define GET_DEVICE1_EEE_CONTROL_EXIT_TIME(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE1_EEE_CONTROL_EXIT_TIME(__val__) (((__val__) << 0u) & 0xffffu) -#define DEVICE1_EEE_CONTROL_MINIMUM_ASSERT_SHIFT 16u -#define DEVICE1_EEE_CONTROL_MINIMUM_ASSERT_MASK 0xffff0000u -#define GET_DEVICE1_EEE_CONTROL_MINIMUM_ASSERT(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_DEVICE1_EEE_CONTROL_MINIMUM_ASSERT(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_DEVICE1_GLOBAL_MUTEX_REQUEST ((volatile APE_DEVICE1_H_uint32_t*)0xa00536f0) /* */ #define REG_DEVICE1_GLOBAL_MUTEX_GRANT ((volatile APE_DEVICE1_H_uint32_t*)0xa00536f4) /* */ #define REG_DEVICE1_MEMORY_ARBITER_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0054000) /* */ -#define DEVICE1_MEMORY_ARBITER_MODE_ENABLE_SHIFT 1u -#define DEVICE1_MEMORY_ARBITER_MODE_ENABLE_MASK 0x2u -#define GET_DEVICE1_MEMORY_ARBITER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_MEMORY_ARBITER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) - #define REG_DEVICE1_BUFFER_MANAGER_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0054400) /* */ -#define DEVICE1_BUFFER_MANAGER_MODE_ENABLE_SHIFT 1u -#define DEVICE1_BUFFER_MANAGER_MODE_ENABLE_MASK 0x2u -#define GET_DEVICE1_BUFFER_MANAGER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_BUFFER_MANAGER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_SHIFT 2u -#define DEVICE1_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_MASK 0x4u -#define GET_DEVICE1_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE1_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE1_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_SHIFT 5u -#define DEVICE1_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_MASK 0x20u -#define GET_DEVICE1_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE1_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__val__) (((__val__) << 5u) & 0x20u) - #define REG_DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0054910) /* */ -#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_SHIFT 16u -#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_MASK 0x30000u -#define GET_DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__reg__) (((__reg__) & 0x30000) >> 16u) -#define SET_DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__val__) (((__val__) << 16u) & 0x30000u) -#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_128B 0x0u -#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_256B 0x1u -#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_512B 0x2u -#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_4K 0x3u - -#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_SHIFT 18u -#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_MASK 0xc0000u -#define GET_DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__reg__) (((__reg__) & 0xc0000) >> 18u) -#define SET_DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__val__) (((__val__) << 18u) & 0xc0000u) -#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_128B 0x0u -#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_256B 0x1u -#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_512B 0x2u -#define DEVICE1_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_4K 0x3u - - #define REG_DEVICE1_RX_RISC_MODE ((volatile APE_DEVICE1_H_uint32_t*)0xa0055000) /* */ -#define DEVICE1_RX_RISC_MODE_RESET_SHIFT 0u -#define DEVICE1_RX_RISC_MODE_RESET_MASK 0x1u -#define GET_DEVICE1_RX_RISC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE1_RX_RISC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE1_RX_RISC_MODE_SINGLE_STEP_SHIFT 1u -#define DEVICE1_RX_RISC_MODE_SINGLE_STEP_MASK 0x2u -#define GET_DEVICE1_RX_RISC_MODE_SINGLE_STEP(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_RX_RISC_MODE_SINGLE_STEP(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_RX_RISC_MODE_PAGE_0_DATA_HALT_SHIFT 2u -#define DEVICE1_RX_RISC_MODE_PAGE_0_DATA_HALT_MASK 0x4u -#define GET_DEVICE1_RX_RISC_MODE_PAGE_0_DATA_HALT(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE1_RX_RISC_MODE_PAGE_0_DATA_HALT(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE1_RX_RISC_MODE_PAGE_0_INSTR_HALT_SHIFT 3u -#define DEVICE1_RX_RISC_MODE_PAGE_0_INSTR_HALT_MASK 0x8u -#define GET_DEVICE1_RX_RISC_MODE_PAGE_0_INSTR_HALT(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE1_RX_RISC_MODE_PAGE_0_INSTR_HALT(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE1_RX_RISC_MODE_ENABLE_DATA_CACHE_SHIFT 5u -#define DEVICE1_RX_RISC_MODE_ENABLE_DATA_CACHE_MASK 0x20u -#define GET_DEVICE1_RX_RISC_MODE_ENABLE_DATA_CACHE(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE1_RX_RISC_MODE_ENABLE_DATA_CACHE(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE1_RX_RISC_MODE_ROM_FAIL_SHIFT 6u -#define DEVICE1_RX_RISC_MODE_ROM_FAIL_MASK 0x40u -#define GET_DEVICE1_RX_RISC_MODE_ROM_FAIL(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE1_RX_RISC_MODE_ROM_FAIL(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE1_RX_RISC_MODE_ENABLE_WATCHDOG_SHIFT 7u -#define DEVICE1_RX_RISC_MODE_ENABLE_WATCHDOG_MASK 0x80u -#define GET_DEVICE1_RX_RISC_MODE_ENABLE_WATCHDOG(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE1_RX_RISC_MODE_ENABLE_WATCHDOG(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE1_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_SHIFT 8u -#define DEVICE1_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_MASK 0x100u -#define GET_DEVICE1_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE1_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE1_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_SHIFT 9u -#define DEVICE1_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_MASK 0x200u -#define GET_DEVICE1_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE1_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE1_RX_RISC_MODE_HALT_SHIFT 10u -#define DEVICE1_RX_RISC_MODE_HALT_MASK 0x400u -#define GET_DEVICE1_RX_RISC_MODE_HALT(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE1_RX_RISC_MODE_HALT(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE1_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_SHIFT 11u -#define DEVICE1_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_MASK 0x800u -#define GET_DEVICE1_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE1_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE1_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_SHIFT 12u -#define DEVICE1_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_MASK 0x1000u -#define GET_DEVICE1_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_DEVICE1_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__val__) (((__val__) << 12u) & 0x1000u) -#define DEVICE1_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_SHIFT 13u -#define DEVICE1_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_MASK 0x2000u -#define GET_DEVICE1_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE1_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE1_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_SHIFT 14u -#define DEVICE1_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_MASK 0x4000u -#define GET_DEVICE1_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE1_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__val__) (((__val__) << 14u) & 0x4000u) - #define REG_DEVICE1_RX_RISC_STATUS ((volatile APE_DEVICE1_H_uint32_t*)0xa0055004) /* */ -#define DEVICE1_RX_RISC_STATUS_HARDWARE_BREAKPOINT_SHIFT 0u -#define DEVICE1_RX_RISC_STATUS_HARDWARE_BREAKPOINT_MASK 0x1u -#define GET_DEVICE1_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE1_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE1_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_SHIFT 1u -#define DEVICE1_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_MASK 0x2u -#define GET_DEVICE1_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION_SHIFT 2u -#define DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION_MASK 0x4u -#define GET_DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE1_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_SHIFT 3u -#define DEVICE1_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_MASK 0x8u -#define GET_DEVICE1_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE1_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE1_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_SHIFT 4u -#define DEVICE1_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_MASK 0x10u -#define GET_DEVICE1_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE1_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE1_RX_RISC_STATUS_INVALID_DATA_ACCESS_SHIFT 5u -#define DEVICE1_RX_RISC_STATUS_INVALID_DATA_ACCESS_MASK 0x20u -#define GET_DEVICE1_RX_RISC_STATUS_INVALID_DATA_ACCESS(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE1_RX_RISC_STATUS_INVALID_DATA_ACCESS(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_SHIFT 6u -#define DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_MASK 0x40u -#define GET_DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE1_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE1_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_SHIFT 7u -#define DEVICE1_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_MASK 0x80u -#define GET_DEVICE1_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE1_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE1_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_SHIFT 8u -#define DEVICE1_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_MASK 0x100u -#define GET_DEVICE1_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE1_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE1_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_SHIFT 9u -#define DEVICE1_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_MASK 0x200u -#define GET_DEVICE1_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE1_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE1_RX_RISC_STATUS_HALTED_SHIFT 10u -#define DEVICE1_RX_RISC_STATUS_HALTED_MASK 0x400u -#define GET_DEVICE1_RX_RISC_STATUS_HALTED(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE1_RX_RISC_STATUS_HALTED(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE1_RX_RISC_STATUS_UNKNOWN_SHIFT 11u -#define DEVICE1_RX_RISC_STATUS_UNKNOWN_MASK 0x800u -#define GET_DEVICE1_RX_RISC_STATUS_UNKNOWN(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE1_RX_RISC_STATUS_UNKNOWN(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE1_RX_RISC_STATUS_DATA_ACCESS_STALL_SHIFT 14u -#define DEVICE1_RX_RISC_STATUS_DATA_ACCESS_STALL_MASK 0x4000u -#define GET_DEVICE1_RX_RISC_STATUS_DATA_ACCESS_STALL(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE1_RX_RISC_STATUS_DATA_ACCESS_STALL(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE1_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_SHIFT 15u -#define DEVICE1_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_MASK 0x8000u -#define GET_DEVICE1_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE1_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE1_RX_RISC_STATUS_BLOCKING_READ_SHIFT 31u -#define DEVICE1_RX_RISC_STATUS_BLOCKING_READ_MASK 0x80000000u -#define GET_DEVICE1_RX_RISC_STATUS_BLOCKING_READ(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE1_RX_RISC_STATUS_BLOCKING_READ(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE1_RX_RISC_PROGRAM_COUNTER ((volatile APE_DEVICE1_H_uint32_t*)0xa005501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ #define REG_DEVICE1_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE1_H_uint32_t*)0xa0055020) /* This undocumented register contains the current word located at the program counter address loaded in */ #define REG_DEVICE1_RX_RISC_HARDWARE_BREAKPOINT ((volatile APE_DEVICE1_H_uint32_t*)0xa0055034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ @@ -1125,32 +178,9 @@ typedef uint32_t APE_DEVICE1_H_uint32_t; #define REG_DEVICE1_PCI_POWER_CONSUMPTION_INFO ((volatile APE_DEVICE1_H_uint32_t*)0xa0056410) /* This undocumented register is used to set PCIe Power Consumption information as reported in configuration space. It is loaded from NVM configuration data. */ #define REG_DEVICE1_PCI_POWER_DISSIPATED_INFO ((volatile APE_DEVICE1_H_uint32_t*)0xa0056414) /* This undocumented register is used to set PCIe Power Dissipated information as reported in configuration space. It is loaded from NVM configuration data. */ #define REG_DEVICE1_PCI_VPD_REQUEST ((volatile APE_DEVICE1_H_uint32_t*)0xa005642c) /* This undocumented register appears to be used to implement the PCI VPD capability. It is set to the VPD offset which was requested by the host by writing to the VPD register. */ -#define DEVICE1_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_SHIFT 16u -#define DEVICE1_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_MASK 0x7fff0000u -#define GET_DEVICE1_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__reg__) (((__reg__) & 0x7fff0000) >> 16u) -#define SET_DEVICE1_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__val__) (((__val__) << 16u) & 0x7fff0000u) - #define REG_DEVICE1_PCI_VPD_RESPONSE ((volatile APE_DEVICE1_H_uint32_t*)0xa0056430) /* This undocumented register appears to be used to implement the PCI VPD capability. Bootcode writes the 32 bits of data loaded from the word requested by */ #define REG_DEVICE1_PCI_VENDOR_DEVICE_ID ((volatile APE_DEVICE1_H_uint32_t*)0xa0056434) /* This is the undocumented register used to set the PCI Vendor/Device ID, which is configurable from NVM. */ -#define DEVICE1_PCI_VENDOR_DEVICE_ID_DEVICE_ID_SHIFT 0u -#define DEVICE1_PCI_VENDOR_DEVICE_ID_DEVICE_ID_MASK 0xffffu -#define GET_DEVICE1_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE1_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__val__) (((__val__) << 0u) & 0xffffu) -#define DEVICE1_PCI_VENDOR_DEVICE_ID_VENDOR_ID_SHIFT 16u -#define DEVICE1_PCI_VENDOR_DEVICE_ID_VENDOR_ID_MASK 0xffff0000u -#define GET_DEVICE1_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_DEVICE1_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_DEVICE1_PCI_SUBSYSTEM_ID ((volatile APE_DEVICE1_H_uint32_t*)0xa0056438) /* This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM. */ -#define DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0u -#define DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_MASK 0xffffu -#define GET_DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__val__) (((__val__) << 0u) & 0xffffu) -#define DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_SHIFT 16u -#define DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_MASK 0xffff0000u -#define GET_DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_DEVICE1_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_DEVICE1_PCI_CLASS_CODE_REVISION ((volatile APE_DEVICE1_H_uint32_t*)0xa005643c) /* This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed. */ #define REG_DEVICE1_64C0 ((volatile APE_DEVICE1_H_uint32_t*)0xa00564c0) /* */ #define REG_DEVICE1_64C8 ((volatile APE_DEVICE1_H_uint32_t*)0xa00564c8) /* */ @@ -1158,548 +188,28 @@ typedef uint32_t APE_DEVICE1_H_uint32_t; #define REG_DEVICE1_PCI_SERIAL_NUMBER_LOW ((volatile APE_DEVICE1_H_uint32_t*)0xa0056504) /* This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ #define REG_DEVICE1_PCI_SERIAL_NUMBER_HIGH ((volatile APE_DEVICE1_H_uint32_t*)0xa0056508) /* This sets the high 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ #define REG_DEVICE1_PCI_POWER_BUDGET_0 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056510) /* Used to report power budget capability data to the host. The values are loaded from NVM, and up to eight values may be specified. */ -#define DEVICE1_PCI_POWER_BUDGET_0_BASE_POWER_SHIFT 0u -#define DEVICE1_PCI_POWER_BUDGET_0_BASE_POWER_MASK 0xffu -#define GET_DEVICE1_PCI_POWER_BUDGET_0_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE1_PCI_POWER_BUDGET_0_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE_SHIFT 8u -#define DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE_MASK 0x300u -#define GET_DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE_1_0X 0x0u -#define DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE_0_1X 0x1u -#define DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE_0_01X 0x2u -#define DEVICE1_PCI_POWER_BUDGET_0_DATA_SCALE_0_001X 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_0_PM_SUB_STATE_SHIFT 10u -#define DEVICE1_PCI_POWER_BUDGET_0_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE1_PCI_POWER_BUDGET_0_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE1_PCI_POWER_BUDGET_0_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE1_PCI_POWER_BUDGET_0_PM_STATE_SHIFT 13u -#define DEVICE1_PCI_POWER_BUDGET_0_PM_STATE_MASK 0x6000u -#define GET_DEVICE1_PCI_POWER_BUDGET_0_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE1_PCI_POWER_BUDGET_0_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE1_PCI_POWER_BUDGET_0_PM_STATE_D0 0x0u -#define DEVICE1_PCI_POWER_BUDGET_0_PM_STATE_D1 0x1u -#define DEVICE1_PCI_POWER_BUDGET_0_PM_STATE_D2 0x2u -#define DEVICE1_PCI_POWER_BUDGET_0_PM_STATE_D3 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_SHIFT 15u -#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_MASK 0x38000u -#define GET_DEVICE1_PCI_POWER_BUDGET_0_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE1_PCI_POWER_BUDGET_0_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_PME_AUX 0x0u -#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_AUXILIARY 0x1u -#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_IDLE 0x2u -#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_SUSTAINED 0x3u -#define DEVICE1_PCI_POWER_BUDGET_0_TYPE_MAXIMUM 0x7u - -#define DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL_SHIFT 18u -#define DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_12V 0x0u -#define DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE1_PCI_POWER_BUDGET_0_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE1_PCI_POWER_BUDGET_1 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056514) /* See */ -#define DEVICE1_PCI_POWER_BUDGET_1_BASE_POWER_SHIFT 0u -#define DEVICE1_PCI_POWER_BUDGET_1_BASE_POWER_MASK 0xffu -#define GET_DEVICE1_PCI_POWER_BUDGET_1_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE1_PCI_POWER_BUDGET_1_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE_SHIFT 8u -#define DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE_MASK 0x300u -#define GET_DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE_1_0X 0x0u -#define DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE_0_1X 0x1u -#define DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE_0_01X 0x2u -#define DEVICE1_PCI_POWER_BUDGET_1_DATA_SCALE_0_001X 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_1_PM_SUB_STATE_SHIFT 10u -#define DEVICE1_PCI_POWER_BUDGET_1_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE1_PCI_POWER_BUDGET_1_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE1_PCI_POWER_BUDGET_1_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE1_PCI_POWER_BUDGET_1_PM_STATE_SHIFT 13u -#define DEVICE1_PCI_POWER_BUDGET_1_PM_STATE_MASK 0x6000u -#define GET_DEVICE1_PCI_POWER_BUDGET_1_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE1_PCI_POWER_BUDGET_1_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE1_PCI_POWER_BUDGET_1_PM_STATE_D0 0x0u -#define DEVICE1_PCI_POWER_BUDGET_1_PM_STATE_D1 0x1u -#define DEVICE1_PCI_POWER_BUDGET_1_PM_STATE_D2 0x2u -#define DEVICE1_PCI_POWER_BUDGET_1_PM_STATE_D3 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_SHIFT 15u -#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_MASK 0x38000u -#define GET_DEVICE1_PCI_POWER_BUDGET_1_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE1_PCI_POWER_BUDGET_1_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_PME_AUX 0x0u -#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_AUXILIARY 0x1u -#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_IDLE 0x2u -#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_SUSTAINED 0x3u -#define DEVICE1_PCI_POWER_BUDGET_1_TYPE_MAXIMUM 0x7u - -#define DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL_SHIFT 18u -#define DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_12V 0x0u -#define DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE1_PCI_POWER_BUDGET_1_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE1_PCI_POWER_BUDGET_2 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056518) /* See */ -#define DEVICE1_PCI_POWER_BUDGET_2_BASE_POWER_SHIFT 0u -#define DEVICE1_PCI_POWER_BUDGET_2_BASE_POWER_MASK 0xffu -#define GET_DEVICE1_PCI_POWER_BUDGET_2_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE1_PCI_POWER_BUDGET_2_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE_SHIFT 8u -#define DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE_MASK 0x300u -#define GET_DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE_1_0X 0x0u -#define DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE_0_1X 0x1u -#define DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE_0_01X 0x2u -#define DEVICE1_PCI_POWER_BUDGET_2_DATA_SCALE_0_001X 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_2_PM_SUB_STATE_SHIFT 10u -#define DEVICE1_PCI_POWER_BUDGET_2_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE1_PCI_POWER_BUDGET_2_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE1_PCI_POWER_BUDGET_2_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE1_PCI_POWER_BUDGET_2_PM_STATE_SHIFT 13u -#define DEVICE1_PCI_POWER_BUDGET_2_PM_STATE_MASK 0x6000u -#define GET_DEVICE1_PCI_POWER_BUDGET_2_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE1_PCI_POWER_BUDGET_2_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE1_PCI_POWER_BUDGET_2_PM_STATE_D0 0x0u -#define DEVICE1_PCI_POWER_BUDGET_2_PM_STATE_D1 0x1u -#define DEVICE1_PCI_POWER_BUDGET_2_PM_STATE_D2 0x2u -#define DEVICE1_PCI_POWER_BUDGET_2_PM_STATE_D3 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_SHIFT 15u -#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_MASK 0x38000u -#define GET_DEVICE1_PCI_POWER_BUDGET_2_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE1_PCI_POWER_BUDGET_2_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_PME_AUX 0x0u -#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_AUXILIARY 0x1u -#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_IDLE 0x2u -#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_SUSTAINED 0x3u -#define DEVICE1_PCI_POWER_BUDGET_2_TYPE_MAXIMUM 0x7u - -#define DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL_SHIFT 18u -#define DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_12V 0x0u -#define DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE1_PCI_POWER_BUDGET_2_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE1_PCI_POWER_BUDGET_3 ((volatile APE_DEVICE1_H_uint32_t*)0xa005651c) /* See */ -#define DEVICE1_PCI_POWER_BUDGET_3_BASE_POWER_SHIFT 0u -#define DEVICE1_PCI_POWER_BUDGET_3_BASE_POWER_MASK 0xffu -#define GET_DEVICE1_PCI_POWER_BUDGET_3_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE1_PCI_POWER_BUDGET_3_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE_SHIFT 8u -#define DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE_MASK 0x300u -#define GET_DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE_1_0X 0x0u -#define DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE_0_1X 0x1u -#define DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE_0_01X 0x2u -#define DEVICE1_PCI_POWER_BUDGET_3_DATA_SCALE_0_001X 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_3_PM_SUB_STATE_SHIFT 10u -#define DEVICE1_PCI_POWER_BUDGET_3_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE1_PCI_POWER_BUDGET_3_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE1_PCI_POWER_BUDGET_3_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE1_PCI_POWER_BUDGET_3_PM_STATE_SHIFT 13u -#define DEVICE1_PCI_POWER_BUDGET_3_PM_STATE_MASK 0x6000u -#define GET_DEVICE1_PCI_POWER_BUDGET_3_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE1_PCI_POWER_BUDGET_3_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE1_PCI_POWER_BUDGET_3_PM_STATE_D0 0x0u -#define DEVICE1_PCI_POWER_BUDGET_3_PM_STATE_D1 0x1u -#define DEVICE1_PCI_POWER_BUDGET_3_PM_STATE_D2 0x2u -#define DEVICE1_PCI_POWER_BUDGET_3_PM_STATE_D3 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_SHIFT 15u -#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_MASK 0x38000u -#define GET_DEVICE1_PCI_POWER_BUDGET_3_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE1_PCI_POWER_BUDGET_3_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_PME_AUX 0x0u -#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_AUXILIARY 0x1u -#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_IDLE 0x2u -#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_SUSTAINED 0x3u -#define DEVICE1_PCI_POWER_BUDGET_3_TYPE_MAXIMUM 0x7u - -#define DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL_SHIFT 18u -#define DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_12V 0x0u -#define DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE1_PCI_POWER_BUDGET_3_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE1_PCI_POWER_BUDGET_4 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056520) /* See */ -#define DEVICE1_PCI_POWER_BUDGET_4_BASE_POWER_SHIFT 0u -#define DEVICE1_PCI_POWER_BUDGET_4_BASE_POWER_MASK 0xffu -#define GET_DEVICE1_PCI_POWER_BUDGET_4_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE1_PCI_POWER_BUDGET_4_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE_SHIFT 8u -#define DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE_MASK 0x300u -#define GET_DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE_1_0X 0x0u -#define DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE_0_1X 0x1u -#define DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE_0_01X 0x2u -#define DEVICE1_PCI_POWER_BUDGET_4_DATA_SCALE_0_001X 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_4_PM_SUB_STATE_SHIFT 10u -#define DEVICE1_PCI_POWER_BUDGET_4_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE1_PCI_POWER_BUDGET_4_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE1_PCI_POWER_BUDGET_4_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE1_PCI_POWER_BUDGET_4_PM_STATE_SHIFT 13u -#define DEVICE1_PCI_POWER_BUDGET_4_PM_STATE_MASK 0x6000u -#define GET_DEVICE1_PCI_POWER_BUDGET_4_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE1_PCI_POWER_BUDGET_4_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE1_PCI_POWER_BUDGET_4_PM_STATE_D0 0x0u -#define DEVICE1_PCI_POWER_BUDGET_4_PM_STATE_D1 0x1u -#define DEVICE1_PCI_POWER_BUDGET_4_PM_STATE_D2 0x2u -#define DEVICE1_PCI_POWER_BUDGET_4_PM_STATE_D3 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_SHIFT 15u -#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_MASK 0x38000u -#define GET_DEVICE1_PCI_POWER_BUDGET_4_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE1_PCI_POWER_BUDGET_4_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_PME_AUX 0x0u -#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_AUXILIARY 0x1u -#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_IDLE 0x2u -#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_SUSTAINED 0x3u -#define DEVICE1_PCI_POWER_BUDGET_4_TYPE_MAXIMUM 0x7u - -#define DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL_SHIFT 18u -#define DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_12V 0x0u -#define DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE1_PCI_POWER_BUDGET_4_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE1_PCI_POWER_BUDGET_5 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056524) /* See */ -#define DEVICE1_PCI_POWER_BUDGET_5_BASE_POWER_SHIFT 0u -#define DEVICE1_PCI_POWER_BUDGET_5_BASE_POWER_MASK 0xffu -#define GET_DEVICE1_PCI_POWER_BUDGET_5_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE1_PCI_POWER_BUDGET_5_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE_SHIFT 8u -#define DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE_MASK 0x300u -#define GET_DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE_1_0X 0x0u -#define DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE_0_1X 0x1u -#define DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE_0_01X 0x2u -#define DEVICE1_PCI_POWER_BUDGET_5_DATA_SCALE_0_001X 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_5_PM_SUB_STATE_SHIFT 10u -#define DEVICE1_PCI_POWER_BUDGET_5_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE1_PCI_POWER_BUDGET_5_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE1_PCI_POWER_BUDGET_5_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE1_PCI_POWER_BUDGET_5_PM_STATE_SHIFT 13u -#define DEVICE1_PCI_POWER_BUDGET_5_PM_STATE_MASK 0x6000u -#define GET_DEVICE1_PCI_POWER_BUDGET_5_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE1_PCI_POWER_BUDGET_5_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE1_PCI_POWER_BUDGET_5_PM_STATE_D0 0x0u -#define DEVICE1_PCI_POWER_BUDGET_5_PM_STATE_D1 0x1u -#define DEVICE1_PCI_POWER_BUDGET_5_PM_STATE_D2 0x2u -#define DEVICE1_PCI_POWER_BUDGET_5_PM_STATE_D3 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_SHIFT 15u -#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_MASK 0x38000u -#define GET_DEVICE1_PCI_POWER_BUDGET_5_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE1_PCI_POWER_BUDGET_5_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_PME_AUX 0x0u -#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_AUXILIARY 0x1u -#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_IDLE 0x2u -#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_SUSTAINED 0x3u -#define DEVICE1_PCI_POWER_BUDGET_5_TYPE_MAXIMUM 0x7u - -#define DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL_SHIFT 18u -#define DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_12V 0x0u -#define DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE1_PCI_POWER_BUDGET_5_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE1_PCI_POWER_BUDGET_6 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056528) /* See */ -#define DEVICE1_PCI_POWER_BUDGET_6_BASE_POWER_SHIFT 0u -#define DEVICE1_PCI_POWER_BUDGET_6_BASE_POWER_MASK 0xffu -#define GET_DEVICE1_PCI_POWER_BUDGET_6_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE1_PCI_POWER_BUDGET_6_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE_SHIFT 8u -#define DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE_MASK 0x300u -#define GET_DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE_1_0X 0x0u -#define DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE_0_1X 0x1u -#define DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE_0_01X 0x2u -#define DEVICE1_PCI_POWER_BUDGET_6_DATA_SCALE_0_001X 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_6_PM_SUB_STATE_SHIFT 10u -#define DEVICE1_PCI_POWER_BUDGET_6_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE1_PCI_POWER_BUDGET_6_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE1_PCI_POWER_BUDGET_6_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE1_PCI_POWER_BUDGET_6_PM_STATE_SHIFT 13u -#define DEVICE1_PCI_POWER_BUDGET_6_PM_STATE_MASK 0x6000u -#define GET_DEVICE1_PCI_POWER_BUDGET_6_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE1_PCI_POWER_BUDGET_6_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE1_PCI_POWER_BUDGET_6_PM_STATE_D0 0x0u -#define DEVICE1_PCI_POWER_BUDGET_6_PM_STATE_D1 0x1u -#define DEVICE1_PCI_POWER_BUDGET_6_PM_STATE_D2 0x2u -#define DEVICE1_PCI_POWER_BUDGET_6_PM_STATE_D3 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_SHIFT 15u -#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_MASK 0x38000u -#define GET_DEVICE1_PCI_POWER_BUDGET_6_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE1_PCI_POWER_BUDGET_6_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_PME_AUX 0x0u -#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_AUXILIARY 0x1u -#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_IDLE 0x2u -#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_SUSTAINED 0x3u -#define DEVICE1_PCI_POWER_BUDGET_6_TYPE_MAXIMUM 0x7u - -#define DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL_SHIFT 18u -#define DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_12V 0x0u -#define DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE1_PCI_POWER_BUDGET_6_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE1_PCI_POWER_BUDGET_7 ((volatile APE_DEVICE1_H_uint32_t*)0xa005652c) /* See */ -#define DEVICE1_PCI_POWER_BUDGET_7_BASE_POWER_SHIFT 0u -#define DEVICE1_PCI_POWER_BUDGET_7_BASE_POWER_MASK 0xffu -#define GET_DEVICE1_PCI_POWER_BUDGET_7_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE1_PCI_POWER_BUDGET_7_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE_SHIFT 8u -#define DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE_MASK 0x300u -#define GET_DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE_1_0X 0x0u -#define DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE_0_1X 0x1u -#define DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE_0_01X 0x2u -#define DEVICE1_PCI_POWER_BUDGET_7_DATA_SCALE_0_001X 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_7_PM_SUB_STATE_SHIFT 10u -#define DEVICE1_PCI_POWER_BUDGET_7_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE1_PCI_POWER_BUDGET_7_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE1_PCI_POWER_BUDGET_7_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE1_PCI_POWER_BUDGET_7_PM_STATE_SHIFT 13u -#define DEVICE1_PCI_POWER_BUDGET_7_PM_STATE_MASK 0x6000u -#define GET_DEVICE1_PCI_POWER_BUDGET_7_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE1_PCI_POWER_BUDGET_7_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE1_PCI_POWER_BUDGET_7_PM_STATE_D0 0x0u -#define DEVICE1_PCI_POWER_BUDGET_7_PM_STATE_D1 0x1u -#define DEVICE1_PCI_POWER_BUDGET_7_PM_STATE_D2 0x2u -#define DEVICE1_PCI_POWER_BUDGET_7_PM_STATE_D3 0x3u - -#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_SHIFT 15u -#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_MASK 0x38000u -#define GET_DEVICE1_PCI_POWER_BUDGET_7_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE1_PCI_POWER_BUDGET_7_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_PME_AUX 0x0u -#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_AUXILIARY 0x1u -#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_IDLE 0x2u -#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_SUSTAINED 0x3u -#define DEVICE1_PCI_POWER_BUDGET_7_TYPE_MAXIMUM 0x7u - -#define DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL_SHIFT 18u -#define DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_12V 0x0u -#define DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE1_PCI_POWER_BUDGET_7_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE1_6530 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056530) /* */ #define REG_DEVICE1_6550 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056550) /* The LSB in this undocumented and unknown register is set if the device is a LOM (LAN-on-Motherboard) design (i.e., builtin to a system and not an expansion card). */ #define REG_DEVICE1_65F4 ((volatile APE_DEVICE1_H_uint32_t*)0xa00565f4) /* */ #define REG_DEVICE1_GRC_MODE_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0056800) /* */ -#define DEVICE1_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_SHIFT 19u -#define DEVICE1_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_MASK 0x80000u -#define GET_DEVICE1_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE1_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) -#define DEVICE1_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_SHIFT 21u -#define DEVICE1_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_MASK 0x200000u -#define GET_DEVICE1_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__reg__) (((__reg__) & 0x200000) >> 21u) -#define SET_DEVICE1_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__val__) (((__val__) << 21u) & 0x200000u) -#define DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_SHIFT 22u -#define DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_MASK 0x400000u -#define GET_DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__reg__) (((__reg__) & 0x400000) >> 22u) -#define SET_DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__val__) (((__val__) << 22u) & 0x400000u) -#define DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_SHIFT 29u -#define DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_MASK 0x20000000u -#define GET_DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__val__) (((__val__) << 29u) & 0x20000000u) -#define DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_SHIFT 31u -#define DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_MASK 0x80000000u -#define GET_DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE1_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE1_MISCELLANEOUS_CONFIG ((volatile APE_DEVICE1_H_uint32_t*)0xa0056804) /* */ -#define DEVICE1_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 1u -#define DEVICE1_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x2u -#define GET_DEVICE1_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE1_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE1_MISCELLANEOUS_CONFIG_ALL_SHIFT 1u -#define DEVICE1_MISCELLANEOUS_CONFIG_ALL_MASK 0xfffffffeu -#define GET_DEVICE1_MISCELLANEOUS_CONFIG_ALL(__reg__) (((__reg__) & 0xfffffffe) >> 1u) -#define SET_DEVICE1_MISCELLANEOUS_CONFIG_ALL(__val__) (((__val__) << 1u) & 0xfffffffeu) - #define REG_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0056808) /* */ -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_SHIFT 8u -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_MASK 0x100u -#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_SHIFT 9u -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_MASK 0x200u -#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_SHIFT 10u -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_MASK 0x400u -#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_SHIFT 11u -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_MASK 0x800u -#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_SHIFT 12u -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_MASK 0x1000u -#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__val__) (((__val__) << 12u) & 0x1000u) -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_SHIFT 13u -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_MASK 0x2000u -#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_SHIFT 14u -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_MASK 0x4000u -#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_SHIFT 15u -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_MASK 0x8000u -#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_SHIFT 16u -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_MASK 0x10000u -#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_SHIFT 24u -#define DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_MASK 0x1000000u -#define GET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_DEVICE1_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__val__) (((__val__) << 24u) & 0x1000000u) - #define REG_DEVICE1_TIMER ((volatile APE_DEVICE1_H_uint32_t*)0xa005680c) /* 32-bit free-running counter */ #define REG_DEVICE1_RX_CPU_EVENT ((volatile APE_DEVICE1_H_uint32_t*)0xa0056810) /* */ -#define DEVICE1_RX_CPU_EVENT_MAC_ATTENTION_SHIFT 25u -#define DEVICE1_RX_CPU_EVENT_MAC_ATTENTION_MASK 0x2000000u -#define GET_DEVICE1_RX_CPU_EVENT_MAC_ATTENTION(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_DEVICE1_RX_CPU_EVENT_MAC_ATTENTION(__val__) (((__val__) << 25u) & 0x2000000u) -#define DEVICE1_RX_CPU_EVENT_RX_CPU_ATTENTION_SHIFT 26u -#define DEVICE1_RX_CPU_EVENT_RX_CPU_ATTENTION_MASK 0x4000000u -#define GET_DEVICE1_RX_CPU_EVENT_RX_CPU_ATTENTION(__reg__) (((__reg__) & 0x4000000) >> 26u) -#define SET_DEVICE1_RX_CPU_EVENT_RX_CPU_ATTENTION(__val__) (((__val__) << 26u) & 0x4000000u) -#define DEVICE1_RX_CPU_EVENT_TIMER_SHIFT 29u -#define DEVICE1_RX_CPU_EVENT_TIMER_MASK 0x20000000u -#define GET_DEVICE1_RX_CPU_EVENT_TIMER(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_DEVICE1_RX_CPU_EVENT_TIMER(__val__) (((__val__) << 29u) & 0x20000000u) -#define DEVICE1_RX_CPU_EVENT_VPD_ATTENTION_SHIFT 30u -#define DEVICE1_RX_CPU_EVENT_VPD_ATTENTION_MASK 0x40000000u -#define GET_DEVICE1_RX_CPU_EVENT_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_DEVICE1_RX_CPU_EVENT_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) - #define REG_DEVICE1_6838 ((volatile APE_DEVICE1_H_uint32_t*)0xa0056838) /* Unknown. Used by PXE agent. */ #define REG_DEVICE1_MDI_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0056844) /* The register manual only mentions this in the changelog; it was removed from the manual in a previous revision. :| */ #define REG_DEVICE1_RX_CPU_EVENT_ENABLE ((volatile APE_DEVICE1_H_uint32_t*)0xa005684c) /* */ -#define DEVICE1_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_SHIFT 30u -#define DEVICE1_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_MASK 0x40000000u -#define GET_DEVICE1_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_DEVICE1_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) - #define REG_DEVICE1_FAST_BOOT_PROGRAM_COUNTER ((volatile APE_DEVICE1_H_uint32_t*)0xa0056894) /* */ -#define DEVICE1_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_SHIFT 0u -#define DEVICE1_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_MASK 0x7fffffffu -#define GET_DEVICE1_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__reg__) (((__reg__) & 0x7fffffff) >> 0u) -#define SET_DEVICE1_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__val__) (((__val__) << 0u) & 0x7fffffffu) -#define DEVICE1_FAST_BOOT_PROGRAM_COUNTER_ENABLE_SHIFT 31u -#define DEVICE1_FAST_BOOT_PROGRAM_COUNTER_ENABLE_MASK 0x80000000u -#define GET_DEVICE1_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE1_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE1_EXPANSION_ROM_ADDR ((volatile APE_DEVICE1_H_uint32_t*)0xa00568ec) /* Expansion ROM base address, expect to be d- word aligned. */ #define REG_DEVICE1_68F0 ((volatile APE_DEVICE1_H_uint32_t*)0xa00568f0) /* */ #define REG_DEVICE1_EAV_REF_CLOCK_CONTROL ((volatile APE_DEVICE1_H_uint32_t*)0xa0056908) /* */ -#define DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SHIFT 16u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_MASK 0x30000u -#define GET_DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__reg__) (((__reg__) & 0x30000) >> 16u) -#define SET_DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__val__) (((__val__) << 16u) & 0x30000u) -#define DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_0_ 0x0u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_1_ 0x1u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_0_ 0x2u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_1_ 0x3u - -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SHIFT 18u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_MASK 0x1c0000u -#define GET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_NOT_USED 0x0u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_0_ 0x4u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_1_ 0x5u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_0_ 0x6u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_1_ 0x7u - -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SHIFT 21u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_MASK 0xe00000u -#define GET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__reg__) (((__reg__) & 0xe00000) >> 21u) -#define SET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__val__) (((__val__) << 21u) & 0xe00000u) -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_NOT_USED 0x0u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_0_ 0x4u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_1_ 0x5u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_0_ 0x6u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_1_ 0x7u - -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SHIFT 24u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_MASK 0x7000000u -#define GET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__reg__) (((__reg__) & 0x7000000) >> 24u) -#define SET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__val__) (((__val__) << 24u) & 0x7000000u) -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_NOT_USED 0x0u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_0_ 0x4u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_1_ 0x5u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_0_ 0x6u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_1_ 0x7u - -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SHIFT 27u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_MASK 0x38000000u -#define GET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__reg__) (((__reg__) & 0x38000000) >> 27u) -#define SET_DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__val__) (((__val__) << 27u) & 0x38000000u) -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_NOT_USED 0x0u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_0_ 0x4u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_1_ 0x5u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_0_ 0x6u -#define DEVICE1_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_1_ 0x7u - - #define REG_DEVICE1_7C04 ((volatile APE_DEVICE1_H_uint32_t*)0xa0057c04) /* PCIe-related. tg3 driver calls this */ /** @brief Device Registers, function 1 */ extern volatile DEVICE_t DEVICE1; diff --git a/include/APE_DEVICE2.h b/include/APE_DEVICE2.h index 8a35530..b1605d9 100644 --- a/include/APE_DEVICE2.h +++ b/include/APE_DEVICE2.h @@ -83,333 +83,17 @@ typedef uint32_t APE_DEVICE2_H_uint32_t; #define REG_DEVICE2_SIZE (sizeof(DEVICE_t)) #define REG_DEVICE2_MISCELLANEOUS_HOST_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0060068) /* */ -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x1u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x2u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x4u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x8u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 4u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x10u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 5u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x20u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x40u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x80u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x100u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x200u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x400u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x800u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x1000u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__val__) (((__val__) << 12u) & 0x1000u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x2000u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x4000u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x8000u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_SHIFT 16u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_MASK 0xff0000u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__reg__) (((__reg__) & 0xff0000) >> 16u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__val__) (((__val__) << 16u) & 0xff0000u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_0 0x0u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_1 0x1u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_2 0x2u - -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_SHIFT 24u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_MASK 0xf000000u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__reg__) (((__reg__) & 0xf000000) >> 24u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__val__) (((__val__) << 24u) & 0xf000000u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_A 0x0u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_B 0x1u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_C 0x2u - -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 28u -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xf0000000u -#define GET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__reg__) (((__reg__) & 0xf0000000) >> 28u) -#define SET_DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__val__) (((__val__) << 28u) & 0xf0000000u) -#define DEVICE2_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_NEW_PRODUCT_MAPPING 0xfu - - #define REG_DEVICE2_PCI_STATE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060070) /* */ -#define DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5u -#define DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x20u -#define GET_DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6u -#define DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x40u -#define GET_DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE2_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE2_PCI_STATE_VPD_AVAILABLE_SHIFT 7u -#define DEVICE2_PCI_STATE_VPD_AVAILABLE_MASK 0x80u -#define GET_DEVICE2_PCI_STATE_VPD_AVAILABLE(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE2_PCI_STATE_VPD_AVAILABLE(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE2_PCI_STATE_FLAT_VIEW_SHIFT 8u -#define DEVICE2_PCI_STATE_FLAT_VIEW_MASK 0x100u -#define GET_DEVICE2_PCI_STATE_FLAT_VIEW(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE2_PCI_STATE_FLAT_VIEW(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE2_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9u -#define DEVICE2_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0xe00u -#define GET_DEVICE2_PCI_STATE_MAX_PCI_TARGET_RETRY(__reg__) (((__reg__) & 0xe00) >> 9u) -#define SET_DEVICE2_PCI_STATE_MAX_PCI_TARGET_RETRY(__val__) (((__val__) << 9u) & 0xe00u) -#define DEVICE2_PCI_STATE_CONFIG_RETRY_SHIFT 15u -#define DEVICE2_PCI_STATE_CONFIG_RETRY_MASK 0x8000u -#define GET_DEVICE2_PCI_STATE_CONFIG_RETRY(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE2_PCI_STATE_CONFIG_RETRY(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE2_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_SHIFT 16u -#define DEVICE2_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_MASK 0x10000u -#define GET_DEVICE2_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE2_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE2_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_SHIFT 17u -#define DEVICE2_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_MASK 0x20000u -#define GET_DEVICE2_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__reg__) (((__reg__) & 0x20000) >> 17u) -#define SET_DEVICE2_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__val__) (((__val__) << 17u) & 0x20000u) -#define DEVICE2_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_SHIFT 18u -#define DEVICE2_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_MASK 0x40000u -#define GET_DEVICE2_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) -#define SET_DEVICE2_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) -#define DEVICE2_PCI_STATE_GENERATE_RESET_PLUS_SHIFT 19u -#define DEVICE2_PCI_STATE_GENERATE_RESET_PLUS_MASK 0x80000u -#define GET_DEVICE2_PCI_STATE_GENERATE_RESET_PLUS(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE2_PCI_STATE_GENERATE_RESET_PLUS(__val__) (((__val__) << 19u) & 0x80000u) - #define REG_DEVICE2_REGISTER_BASE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060078) /* Local controller memory address of a register than can be written or read by writing to the register data register. */ #define REG_DEVICE2_MEMORY_BASE ((volatile APE_DEVICE2_H_uint32_t*)0xa006007c) /* Local controller memory address of the NIC memory region that can be accessed via Memory Window data register. */ #define REG_DEVICE2_REGISTER_DATA ((volatile APE_DEVICE2_H_uint32_t*)0xa0060080) /* Register Data at the location pointed by the Register Base Register. */ #define REG_DEVICE2_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX ((volatile APE_DEVICE2_H_uint32_t*)0xa0060088) /* UNDI Receive Return Ring Consumer Index Mailbox */ #define REG_DEVICE2_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006008c) /* UNDI Receive Return Ring Consumer Index Mailbox */ #define REG_DEVICE2_LINK_STATUS_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00600bc) /* PCIe standard register. */ -#define DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_SHIFT 16u -#define DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_MASK 0xf0000u -#define GET_DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__reg__) (((__reg__) & 0xf0000) >> 16u) -#define SET_DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__val__) (((__val__) << 16u) & 0xf0000u) -#define DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_1_0 0x1u -#define DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_2_0 0x2u - -#define DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20u -#define DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x3f00000u -#define GET_DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__reg__) (((__reg__) & 0x3f00000) >> 20u) -#define SET_DEVICE2_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__val__) (((__val__) << 20u) & 0x3f00000u) - #define REG_DEVICE2_APE_MEMORY_BASE ((volatile APE_DEVICE2_H_uint32_t*)0xa00600f8) /* APE Memory address to read/write using the APE Memory Data register.. */ #define REG_DEVICE2_APE_MEMORY_DATA ((volatile APE_DEVICE2_H_uint32_t*)0xa00600fc) /* APE Memory value at the location pointed by the Memory Base Register. */ #define REG_DEVICE2_EMAC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060400) /* */ -#define DEVICE2_EMAC_MODE_GLOBAL_RESET_SHIFT 0u -#define DEVICE2_EMAC_MODE_GLOBAL_RESET_MASK 0x1u -#define GET_DEVICE2_EMAC_MODE_GLOBAL_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE2_EMAC_MODE_GLOBAL_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE2_EMAC_MODE_HALF_DUPLEX_SHIFT 1u -#define DEVICE2_EMAC_MODE_HALF_DUPLEX_MASK 0x2u -#define GET_DEVICE2_EMAC_MODE_HALF_DUPLEX(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_EMAC_MODE_HALF_DUPLEX(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_EMAC_MODE_PORT_MODE_SHIFT 2u -#define DEVICE2_EMAC_MODE_PORT_MODE_MASK 0xcu -#define GET_DEVICE2_EMAC_MODE_PORT_MODE(__reg__) (((__reg__) & 0xc) >> 2u) -#define SET_DEVICE2_EMAC_MODE_PORT_MODE(__val__) (((__val__) << 2u) & 0xcu) -#define DEVICE2_EMAC_MODE_PORT_MODE_NONE 0x0u -#define DEVICE2_EMAC_MODE_PORT_MODE_10_DIV_100 0x1u -#define DEVICE2_EMAC_MODE_PORT_MODE_1000 0x2u -#define DEVICE2_EMAC_MODE_PORT_MODE_TBI 0x3u - -#define DEVICE2_EMAC_MODE_LOOPBACK_MODE_SHIFT 4u -#define DEVICE2_EMAC_MODE_LOOPBACK_MODE_MASK 0x10u -#define GET_DEVICE2_EMAC_MODE_LOOPBACK_MODE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE2_EMAC_MODE_LOOPBACK_MODE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE2_EMAC_MODE_TAGGED_MAC_CONTROL_SHIFT 7u -#define DEVICE2_EMAC_MODE_TAGGED_MAC_CONTROL_MASK 0x80u -#define GET_DEVICE2_EMAC_MODE_TAGGED_MAC_CONTROL(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE2_EMAC_MODE_TAGGED_MAC_CONTROL(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE2_EMAC_MODE_ENABLE_TX_BURSTING_SHIFT 8u -#define DEVICE2_EMAC_MODE_ENABLE_TX_BURSTING_MASK 0x100u -#define GET_DEVICE2_EMAC_MODE_ENABLE_TX_BURSTING(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE2_EMAC_MODE_ENABLE_TX_BURSTING(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE2_EMAC_MODE_MAX_DEFER_SHIFT 9u -#define DEVICE2_EMAC_MODE_MAX_DEFER_MASK 0x200u -#define GET_DEVICE2_EMAC_MODE_MAX_DEFER(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE2_EMAC_MODE_MAX_DEFER(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE2_EMAC_MODE_ENABLE_RX_STATISTICS_SHIFT 11u -#define DEVICE2_EMAC_MODE_ENABLE_RX_STATISTICS_MASK 0x800u -#define GET_DEVICE2_EMAC_MODE_ENABLE_RX_STATISTICS(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE2_EMAC_MODE_ENABLE_RX_STATISTICS(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE2_EMAC_MODE_CLEAR_RX_STATISTICS_SHIFT 12u -#define DEVICE2_EMAC_MODE_CLEAR_RX_STATISTICS_MASK 0x1000u -#define GET_DEVICE2_EMAC_MODE_CLEAR_RX_STATISTICS(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_DEVICE2_EMAC_MODE_CLEAR_RX_STATISTICS(__val__) (((__val__) << 12u) & 0x1000u) -#define DEVICE2_EMAC_MODE_FLUSH_RX_STATISTICS_SHIFT 13u -#define DEVICE2_EMAC_MODE_FLUSH_RX_STATISTICS_MASK 0x2000u -#define GET_DEVICE2_EMAC_MODE_FLUSH_RX_STATISTICS(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE2_EMAC_MODE_FLUSH_RX_STATISTICS(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE2_EMAC_MODE_ENABLE_TX_STATISTICS_SHIFT 14u -#define DEVICE2_EMAC_MODE_ENABLE_TX_STATISTICS_MASK 0x4000u -#define GET_DEVICE2_EMAC_MODE_ENABLE_TX_STATISTICS(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE2_EMAC_MODE_ENABLE_TX_STATISTICS(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE2_EMAC_MODE_CLEAR_TX_STATISTICS_SHIFT 15u -#define DEVICE2_EMAC_MODE_CLEAR_TX_STATISTICS_MASK 0x8000u -#define GET_DEVICE2_EMAC_MODE_CLEAR_TX_STATISTICS(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE2_EMAC_MODE_CLEAR_TX_STATISTICS(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE2_EMAC_MODE_FLUSH_TX_STATISTICS_SHIFT 16u -#define DEVICE2_EMAC_MODE_FLUSH_TX_STATISTICS_MASK 0x10000u -#define GET_DEVICE2_EMAC_MODE_FLUSH_TX_STATISTICS(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE2_EMAC_MODE_FLUSH_TX_STATISTICS(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE2_EMAC_MODE_SEND_CONFIG_COMMAND_SHIFT 17u -#define DEVICE2_EMAC_MODE_SEND_CONFIG_COMMAND_MASK 0x20000u -#define GET_DEVICE2_EMAC_MODE_SEND_CONFIG_COMMAND(__reg__) (((__reg__) & 0x20000) >> 17u) -#define SET_DEVICE2_EMAC_MODE_SEND_CONFIG_COMMAND(__val__) (((__val__) << 17u) & 0x20000u) -#define DEVICE2_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_SHIFT 18u -#define DEVICE2_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_MASK 0x40000u -#define GET_DEVICE2_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) -#define SET_DEVICE2_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) -#define DEVICE2_EMAC_MODE_ACPI_POWER_ON_ENABLE_SHIFT 19u -#define DEVICE2_EMAC_MODE_ACPI_POWER_ON_ENABLE_MASK 0x80000u -#define GET_DEVICE2_EMAC_MODE_ACPI_POWER_ON_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE2_EMAC_MODE_ACPI_POWER_ON_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) -#define DEVICE2_EMAC_MODE_ENABLE_TCE_SHIFT 21u -#define DEVICE2_EMAC_MODE_ENABLE_TCE_MASK 0x200000u -#define GET_DEVICE2_EMAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x200000) >> 21u) -#define SET_DEVICE2_EMAC_MODE_ENABLE_TCE(__val__) (((__val__) << 21u) & 0x200000u) -#define DEVICE2_EMAC_MODE_ENABLE_RDE_SHIFT 22u -#define DEVICE2_EMAC_MODE_ENABLE_RDE_MASK 0x400000u -#define GET_DEVICE2_EMAC_MODE_ENABLE_RDE(__reg__) (((__reg__) & 0x400000) >> 22u) -#define SET_DEVICE2_EMAC_MODE_ENABLE_RDE(__val__) (((__val__) << 22u) & 0x400000u) -#define DEVICE2_EMAC_MODE_ENABLE_FHDE_SHIFT 23u -#define DEVICE2_EMAC_MODE_ENABLE_FHDE_MASK 0x800000u -#define GET_DEVICE2_EMAC_MODE_ENABLE_FHDE(__reg__) (((__reg__) & 0x800000) >> 23u) -#define SET_DEVICE2_EMAC_MODE_ENABLE_FHDE(__val__) (((__val__) << 23u) & 0x800000u) -#define DEVICE2_EMAC_MODE_KEEP_FRAME_IN_WOL_SHIFT 24u -#define DEVICE2_EMAC_MODE_KEEP_FRAME_IN_WOL_MASK 0x1000000u -#define GET_DEVICE2_EMAC_MODE_KEEP_FRAME_IN_WOL(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_DEVICE2_EMAC_MODE_KEEP_FRAME_IN_WOL(__val__) (((__val__) << 24u) & 0x1000000u) -#define DEVICE2_EMAC_MODE_HALT_INTERESTING_PACKET_PME_SHIFT 25u -#define DEVICE2_EMAC_MODE_HALT_INTERESTING_PACKET_PME_MASK 0x2000000u -#define GET_DEVICE2_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_DEVICE2_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__val__) (((__val__) << 25u) & 0x2000000u) -#define DEVICE2_EMAC_MODE_FREE_RUNNING_ACPI_SHIFT 26u -#define DEVICE2_EMAC_MODE_FREE_RUNNING_ACPI_MASK 0x4000000u -#define GET_DEVICE2_EMAC_MODE_FREE_RUNNING_ACPI(__reg__) (((__reg__) & 0x4000000) >> 26u) -#define SET_DEVICE2_EMAC_MODE_FREE_RUNNING_ACPI(__val__) (((__val__) << 26u) & 0x4000000u) -#define DEVICE2_EMAC_MODE_ENABLE_APE_RX_PATH_SHIFT 27u -#define DEVICE2_EMAC_MODE_ENABLE_APE_RX_PATH_MASK 0x8000000u -#define GET_DEVICE2_EMAC_MODE_ENABLE_APE_RX_PATH(__reg__) (((__reg__) & 0x8000000) >> 27u) -#define SET_DEVICE2_EMAC_MODE_ENABLE_APE_RX_PATH(__val__) (((__val__) << 27u) & 0x8000000u) -#define DEVICE2_EMAC_MODE_ENABLE_APE_TX_PATH_SHIFT 28u -#define DEVICE2_EMAC_MODE_ENABLE_APE_TX_PATH_MASK 0x10000000u -#define GET_DEVICE2_EMAC_MODE_ENABLE_APE_TX_PATH(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_DEVICE2_EMAC_MODE_ENABLE_APE_TX_PATH(__val__) (((__val__) << 28u) & 0x10000000u) -#define DEVICE2_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_SHIFT 29u -#define DEVICE2_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_MASK 0x20000000u -#define GET_DEVICE2_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_DEVICE2_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__val__) (((__val__) << 29u) & 0x20000000u) - #define REG_DEVICE2_LED_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa006040c) /* */ -#define DEVICE2_LED_CONTROL_OVERRIDE_LINK_SHIFT 0u -#define DEVICE2_LED_CONTROL_OVERRIDE_LINK_MASK 0x1u -#define GET_DEVICE2_LED_CONTROL_OVERRIDE_LINK(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE2_LED_CONTROL_OVERRIDE_LINK(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE2_LED_CONTROL_LED_1000_SHIFT 1u -#define DEVICE2_LED_CONTROL_LED_1000_MASK 0x2u -#define GET_DEVICE2_LED_CONTROL_LED_1000(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_LED_CONTROL_LED_1000(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_LED_CONTROL_LED_100_SHIFT 2u -#define DEVICE2_LED_CONTROL_LED_100_MASK 0x4u -#define GET_DEVICE2_LED_CONTROL_LED_100(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE2_LED_CONTROL_LED_100(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE2_LED_CONTROL_LED_10_SHIFT 3u -#define DEVICE2_LED_CONTROL_LED_10_MASK 0x8u -#define GET_DEVICE2_LED_CONTROL_LED_10(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE2_LED_CONTROL_LED_10(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE2_LED_CONTROL_OVERRIDE_TRAFFIC_SHIFT 4u -#define DEVICE2_LED_CONTROL_OVERRIDE_TRAFFIC_MASK 0x10u -#define GET_DEVICE2_LED_CONTROL_OVERRIDE_TRAFFIC(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE2_LED_CONTROL_OVERRIDE_TRAFFIC(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE2_LED_CONTROL_LED_TRAFFIC_BLINK_SHIFT 5u -#define DEVICE2_LED_CONTROL_LED_TRAFFIC_BLINK_MASK 0x20u -#define GET_DEVICE2_LED_CONTROL_LED_TRAFFIC_BLINK(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE2_LED_CONTROL_LED_TRAFFIC_BLINK(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE2_LED_CONTROL_LED_TRAFFIC_SHIFT 6u -#define DEVICE2_LED_CONTROL_LED_TRAFFIC_MASK 0x40u -#define GET_DEVICE2_LED_CONTROL_LED_TRAFFIC(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE2_LED_CONTROL_LED_TRAFFIC(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE2_LED_CONTROL_LED_STATUS_1000_SHIFT 7u -#define DEVICE2_LED_CONTROL_LED_STATUS_1000_MASK 0x80u -#define GET_DEVICE2_LED_CONTROL_LED_STATUS_1000(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE2_LED_CONTROL_LED_STATUS_1000(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE2_LED_CONTROL_LED_STATUS_100_SHIFT 8u -#define DEVICE2_LED_CONTROL_LED_STATUS_100_MASK 0x100u -#define GET_DEVICE2_LED_CONTROL_LED_STATUS_100(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE2_LED_CONTROL_LED_STATUS_100(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE2_LED_CONTROL_LED_STATUS_10_SHIFT 9u -#define DEVICE2_LED_CONTROL_LED_STATUS_10_MASK 0x200u -#define GET_DEVICE2_LED_CONTROL_LED_STATUS_10(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE2_LED_CONTROL_LED_STATUS_10(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE2_LED_CONTROL_LED_STATUS_TRAFFIC_SHIFT 10u -#define DEVICE2_LED_CONTROL_LED_STATUS_TRAFFIC_MASK 0x400u -#define GET_DEVICE2_LED_CONTROL_LED_STATUS_TRAFFIC(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE2_LED_CONTROL_LED_STATUS_TRAFFIC(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE2_LED_CONTROL_LED_MODE_SHIFT 11u -#define DEVICE2_LED_CONTROL_LED_MODE_MASK 0x1800u -#define GET_DEVICE2_LED_CONTROL_LED_MODE(__reg__) (((__reg__) & 0x1800) >> 11u) -#define SET_DEVICE2_LED_CONTROL_LED_MODE(__val__) (((__val__) << 11u) & 0x1800u) -#define DEVICE2_LED_CONTROL_LED_MODE_MAC 0x0u -#define DEVICE2_LED_CONTROL_LED_MODE_PHY_MODE_1 0x1u -#define DEVICE2_LED_CONTROL_LED_MODE_PHY_MODE_2 0x2u -#define DEVICE2_LED_CONTROL_LED_MODE_PHY_MODE_1_ 0x3u - -#define DEVICE2_LED_CONTROL_MAC_MODE_SHIFT 13u -#define DEVICE2_LED_CONTROL_MAC_MODE_MASK 0x2000u -#define GET_DEVICE2_LED_CONTROL_MAC_MODE(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE2_LED_CONTROL_MAC_MODE(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE2_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_SHIFT 14u -#define DEVICE2_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_MASK 0x4000u -#define GET_DEVICE2_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE2_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE2_LED_CONTROL_BLINK_PERIOD_SHIFT 19u -#define DEVICE2_LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000u -#define GET_DEVICE2_LED_CONTROL_BLINK_PERIOD(__reg__) (((__reg__) & 0x7ff80000) >> 19u) -#define SET_DEVICE2_LED_CONTROL_BLINK_PERIOD(__val__) (((__val__) << 19u) & 0x7ff80000u) -#define DEVICE2_LED_CONTROL_OVERRIDE_BLINK_RATE_SHIFT 31u -#define DEVICE2_LED_CONTROL_OVERRIDE_BLINK_RATE_MASK 0x80000000u -#define GET_DEVICE2_LED_CONTROL_OVERRIDE_BLINK_RATE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE2_LED_CONTROL_OVERRIDE_BLINK_RATE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE2_EMAC_MAC_ADDRESSES_0_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060410) /* Upper 2-bytes of this node's MAC address. */ #define REG_DEVICE2_EMAC_MAC_ADDRESSES_0_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0060414) /* Lower 4-byte of this node's MAC address. */ #define REG_DEVICE2_EMAC_MAC_ADDRESSES_1_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060418) /* Upper 2-bytes of this node's MAC address. */ @@ -421,671 +105,40 @@ typedef uint32_t APE_DEVICE2_H_uint32_t; #define REG_DEVICE2_WOL_PATTERN_POINTER ((volatile APE_DEVICE2_H_uint32_t*)0xa0060430) /* Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary). */ #define REG_DEVICE2_WOL_PATTERN_CFG ((volatile APE_DEVICE2_H_uint32_t*)0xa0060434) /* */ #define REG_DEVICE2_MTU_SIZE ((volatile APE_DEVICE2_H_uint32_t*)0xa006043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */ -#define DEVICE2_MTU_SIZE_MTU_SHIFT 0u -#define DEVICE2_MTU_SIZE_MTU_MASK 0xffffu -#define GET_DEVICE2_MTU_SIZE_MTU(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE2_MTU_SIZE_MTU(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE2_MII_COMMUNICATION ((volatile APE_DEVICE2_H_uint32_t*)0xa006044c) /* */ -#define DEVICE2_MII_COMMUNICATION_TRANSACTION_DATA_SHIFT 0u -#define DEVICE2_MII_COMMUNICATION_TRANSACTION_DATA_MASK 0xffffu -#define GET_DEVICE2_MII_COMMUNICATION_TRANSACTION_DATA(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE2_MII_COMMUNICATION_TRANSACTION_DATA(__val__) (((__val__) << 0u) & 0xffffu) -#define DEVICE2_MII_COMMUNICATION_REGISTER_ADDRESS_SHIFT 16u -#define DEVICE2_MII_COMMUNICATION_REGISTER_ADDRESS_MASK 0x1f0000u -#define GET_DEVICE2_MII_COMMUNICATION_REGISTER_ADDRESS(__reg__) (((__reg__) & 0x1f0000) >> 16u) -#define SET_DEVICE2_MII_COMMUNICATION_REGISTER_ADDRESS(__val__) (((__val__) << 16u) & 0x1f0000u) -#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SHIFT 21u -#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_MASK 0x3e00000u -#define GET_DEVICE2_MII_COMMUNICATION_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e00000) >> 21u) -#define SET_DEVICE2_MII_COMMUNICATION_PHY_ADDRESS(__val__) (((__val__) << 21u) & 0x3e00000u) -#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_PHY_0 0x1u -#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_PHY_1 0x2u -#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_PHY_2 0x3u -#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_PHY_3 0x4u -#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0 0x8u -#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SGMII_1 0x9u -#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SGMII_2 0xau -#define DEVICE2_MII_COMMUNICATION_PHY_ADDRESS_SGMII_3 0xbu - -#define DEVICE2_MII_COMMUNICATION_COMMAND_SHIFT 26u -#define DEVICE2_MII_COMMUNICATION_COMMAND_MASK 0xc000000u -#define GET_DEVICE2_MII_COMMUNICATION_COMMAND(__reg__) (((__reg__) & 0xc000000) >> 26u) -#define SET_DEVICE2_MII_COMMUNICATION_COMMAND(__val__) (((__val__) << 26u) & 0xc000000u) -#define DEVICE2_MII_COMMUNICATION_COMMAND_WRITE 0x1u -#define DEVICE2_MII_COMMUNICATION_COMMAND_READ 0x2u - -#define DEVICE2_MII_COMMUNICATION_READ_FAILED_SHIFT 28u -#define DEVICE2_MII_COMMUNICATION_READ_FAILED_MASK 0x10000000u -#define GET_DEVICE2_MII_COMMUNICATION_READ_FAILED(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_DEVICE2_MII_COMMUNICATION_READ_FAILED(__val__) (((__val__) << 28u) & 0x10000000u) -#define DEVICE2_MII_COMMUNICATION_START_DIV_BUSY_SHIFT 29u -#define DEVICE2_MII_COMMUNICATION_START_DIV_BUSY_MASK 0x20000000u -#define GET_DEVICE2_MII_COMMUNICATION_START_DIV_BUSY(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_DEVICE2_MII_COMMUNICATION_START_DIV_BUSY(__val__) (((__val__) << 29u) & 0x20000000u) - #define REG_DEVICE2_MII_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060454) /* */ -#define DEVICE2_MII_MODE_PHY_ADDRESS_SHIFT 5u -#define DEVICE2_MII_MODE_PHY_ADDRESS_MASK 0x3e0u -#define GET_DEVICE2_MII_MODE_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e0) >> 5u) -#define SET_DEVICE2_MII_MODE_PHY_ADDRESS(__val__) (((__val__) << 5u) & 0x3e0u) -#define DEVICE2_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_SHIFT 15u -#define DEVICE2_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_MASK 0x8000u -#define GET_DEVICE2_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE2_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE2_MII_MODE_MII_CLOCK_COUNT_SHIFT 16u -#define DEVICE2_MII_MODE_MII_CLOCK_COUNT_MASK 0x1f0000u -#define GET_DEVICE2_MII_MODE_MII_CLOCK_COUNT(__reg__) (((__reg__) & 0x1f0000) >> 16u) -#define SET_DEVICE2_MII_MODE_MII_CLOCK_COUNT(__val__) (((__val__) << 16u) & 0x1f0000u) - #define REG_DEVICE2_TRANSMIT_MAC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa006045c) /* */ -#define DEVICE2_TRANSMIT_MAC_MODE_RESET_SHIFT 0u -#define DEVICE2_TRANSMIT_MAC_MODE_RESET_MASK 0x1u -#define GET_DEVICE2_TRANSMIT_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE2_TRANSMIT_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TCE_SHIFT 1u -#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TCE_MASK 0x2u -#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TCE(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_SHIFT 4u -#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_MASK 0x10u -#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_SHIFT 5u -#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_MASK 0x20u -#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_SHIFT 6u -#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_MASK 0x40u -#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE2_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_SHIFT 7u -#define DEVICE2_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_MASK 0x80u -#define GET_DEVICE2_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE2_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE2_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_SHIFT 8u -#define DEVICE2_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_MASK 0x100u -#define GET_DEVICE2_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE2_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_SHIFT 9u -#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_MASK 0x200u -#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_SHIFT 10u -#define DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_MASK 0x400u -#define GET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE2_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__val__) (((__val__) << 10u) & 0x400u) - #define REG_DEVICE2_RECEIVE_MAC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0060468) /* */ -#define DEVICE2_RECEIVE_MAC_MODE_RESET_SHIFT 0u -#define DEVICE2_RECEIVE_MAC_MODE_RESET_MASK 0x1u -#define GET_DEVICE2_RECEIVE_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE2_RECEIVE_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE2_RECEIVE_MAC_MODE_ENABLE_SHIFT 1u -#define DEVICE2_RECEIVE_MAC_MODE_ENABLE_MASK 0x2u -#define GET_DEVICE2_RECEIVE_MAC_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_RECEIVE_MAC_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_SHIFT 8u -#define DEVICE2_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_MASK 0x100u -#define GET_DEVICE2_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE2_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE2_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_SHIFT 25u -#define DEVICE2_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_MASK 0x2000000u -#define GET_DEVICE2_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_DEVICE2_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__val__) (((__val__) << 25u) & 0x2000000u) - #define REG_DEVICE2_PERFECT_MATCH1_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060540) /* */ -#define DEVICE2_PERFECT_MATCH1_HIGH_HIGH_SHIFT 0u -#define DEVICE2_PERFECT_MATCH1_HIGH_HIGH_MASK 0xffffu -#define GET_DEVICE2_PERFECT_MATCH1_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE2_PERFECT_MATCH1_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE2_PERFECT_MATCH1_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0060544) /* */ -#define DEVICE2_PERFECT_MATCH1_LOW_LOW_SHIFT 0u -#define DEVICE2_PERFECT_MATCH1_LOW_LOW_MASK 0xffffffffu -#define GET_DEVICE2_PERFECT_MATCH1_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE2_PERFECT_MATCH1_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) - #define REG_DEVICE2_PERFECT_MATCH2_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060548) /* */ -#define DEVICE2_PERFECT_MATCH2_HIGH_HIGH_SHIFT 0u -#define DEVICE2_PERFECT_MATCH2_HIGH_HIGH_MASK 0xffffu -#define GET_DEVICE2_PERFECT_MATCH2_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE2_PERFECT_MATCH2_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE2_PERFECT_MATCH2_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006054c) /* */ -#define DEVICE2_PERFECT_MATCH2_LOW_LOW_SHIFT 0u -#define DEVICE2_PERFECT_MATCH2_LOW_LOW_MASK 0xffffffffu -#define GET_DEVICE2_PERFECT_MATCH2_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE2_PERFECT_MATCH2_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) - #define REG_DEVICE2_PERFECT_MATCH3_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060550) /* */ -#define DEVICE2_PERFECT_MATCH3_HIGH_HIGH_SHIFT 0u -#define DEVICE2_PERFECT_MATCH3_HIGH_HIGH_MASK 0xffffu -#define GET_DEVICE2_PERFECT_MATCH3_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE2_PERFECT_MATCH3_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE2_PERFECT_MATCH3_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0060554) /* */ -#define DEVICE2_PERFECT_MATCH3_LOW_LOW_SHIFT 0u -#define DEVICE2_PERFECT_MATCH3_LOW_LOW_MASK 0xffffffffu -#define GET_DEVICE2_PERFECT_MATCH3_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE2_PERFECT_MATCH3_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) - #define REG_DEVICE2_PERFECT_MATCH4_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0060558) /* */ -#define DEVICE2_PERFECT_MATCH4_HIGH_HIGH_SHIFT 0u -#define DEVICE2_PERFECT_MATCH4_HIGH_HIGH_MASK 0xffffu -#define GET_DEVICE2_PERFECT_MATCH4_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE2_PERFECT_MATCH4_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE2_PERFECT_MATCH4_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa006055c) /* */ -#define DEVICE2_PERFECT_MATCH4_LOW_LOW_SHIFT 0u -#define DEVICE2_PERFECT_MATCH4_LOW_LOW_MASK 0xffffffffu -#define GET_DEVICE2_PERFECT_MATCH4_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE2_PERFECT_MATCH4_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) - #define REG_DEVICE2_SGMII_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa00605b4) /* This register reflects various status of the respective SGMII port when enabled. */ -#define DEVICE2_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 0u -#define DEVICE2_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x1u -#define GET_DEVICE2_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE2_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE2_SGMII_STATUS_LINK_STATUS_SHIFT 1u -#define DEVICE2_SGMII_STATUS_LINK_STATUS_MASK 0x2u -#define GET_DEVICE2_SGMII_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_SGMII_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_SGMII_STATUS_DUPLEX_STATUS_SHIFT 2u -#define DEVICE2_SGMII_STATUS_DUPLEX_STATUS_MASK 0x4u -#define GET_DEVICE2_SGMII_STATUS_DUPLEX_STATUS(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE2_SGMII_STATUS_DUPLEX_STATUS(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE2_SGMII_STATUS_SPEED_1000_SHIFT 3u -#define DEVICE2_SGMII_STATUS_SPEED_1000_MASK 0x8u -#define GET_DEVICE2_SGMII_STATUS_SPEED_1000(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE2_SGMII_STATUS_SPEED_1000(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE2_SGMII_STATUS_SPEED_100_SHIFT 4u -#define DEVICE2_SGMII_STATUS_SPEED_100_MASK 0x10u -#define GET_DEVICE2_SGMII_STATUS_SPEED_100(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE2_SGMII_STATUS_SPEED_100(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE2_SGMII_STATUS_NEXT_PAGE_RX_SHIFT 5u -#define DEVICE2_SGMII_STATUS_NEXT_PAGE_RX_MASK 0x20u -#define GET_DEVICE2_SGMII_STATUS_NEXT_PAGE_RX(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE2_SGMII_STATUS_NEXT_PAGE_RX(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE2_SGMII_STATUS_PAUSE_RX_SHIFT 6u -#define DEVICE2_SGMII_STATUS_PAUSE_RX_MASK 0x40u -#define GET_DEVICE2_SGMII_STATUS_PAUSE_RX(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE2_SGMII_STATUS_PAUSE_RX(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE2_SGMII_STATUS_PAUSE_TX_SHIFT 7u -#define DEVICE2_SGMII_STATUS_PAUSE_TX_MASK 0x80u -#define GET_DEVICE2_SGMII_STATUS_PAUSE_TX(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE2_SGMII_STATUS_PAUSE_TX(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE_SHIFT 8u -#define DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE_MASK 0x100u -#define GET_DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE_COPPER 0x0u -#define DEVICE2_SGMII_STATUS_MEDIA_SELECTION_MODE_SGMII 0x1u - -#define DEVICE2_SGMII_STATUS_PCS_CRS_DETECT_SHIFT 9u -#define DEVICE2_SGMII_STATUS_PCS_CRS_DETECT_MASK 0x200u -#define GET_DEVICE2_SGMII_STATUS_PCS_CRS_DETECT(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE2_SGMII_STATUS_PCS_CRS_DETECT(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE2_SGMII_STATUS_EXTERNAL_CRS_DETECT_SHIFT 10u -#define DEVICE2_SGMII_STATUS_EXTERNAL_CRS_DETECT_MASK 0x400u -#define GET_DEVICE2_SGMII_STATUS_EXTERNAL_CRS_DETECT(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE2_SGMII_STATUS_EXTERNAL_CRS_DETECT(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE2_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_SHIFT 16u -#define DEVICE2_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_MASK 0xffff0000u -#define GET_DEVICE2_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_DEVICE2_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_DEVICE2_CPMU_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0063600) /* */ -#define DEVICE2_CPMU_CONTROL_CPMU_SOFTWARE_RESET_SHIFT 0u -#define DEVICE2_CPMU_CONTROL_CPMU_SOFTWARE_RESET_MASK 0x1u -#define GET_DEVICE2_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE2_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE2_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 1u -#define DEVICE2_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x2u -#define GET_DEVICE2_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_CPMU_CONTROL_POWER_DOWN_SHIFT 2u -#define DEVICE2_CPMU_CONTROL_POWER_DOWN_MASK 0x4u -#define GET_DEVICE2_CPMU_CONTROL_POWER_DOWN(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE2_CPMU_CONTROL_POWER_DOWN(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE2_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_SHIFT 4u -#define DEVICE2_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_MASK 0x10u -#define GET_DEVICE2_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE2_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE2_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_SHIFT 5u -#define DEVICE2_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_MASK 0x20u -#define GET_DEVICE2_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE2_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE2_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_SHIFT 9u -#define DEVICE2_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_MASK 0x200u -#define GET_DEVICE2_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE2_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE2_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_SHIFT 10u -#define DEVICE2_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_MASK 0x400u -#define GET_DEVICE2_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE2_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE2_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_SHIFT 14u -#define DEVICE2_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_MASK 0x4000u -#define GET_DEVICE2_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE2_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE2_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_SHIFT 16u -#define DEVICE2_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_MASK 0x10000u -#define GET_DEVICE2_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE2_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE2_CPMU_CONTROL_LEGACY_TIMER_ENABLE_SHIFT 18u -#define DEVICE2_CPMU_CONTROL_LEGACY_TIMER_ENABLE_MASK 0x40000u -#define GET_DEVICE2_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) -#define SET_DEVICE2_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) -#define DEVICE2_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_SHIFT 19u -#define DEVICE2_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_MASK 0x80000u -#define GET_DEVICE2_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE2_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 19u) & 0x80000u) -#define DEVICE2_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_SHIFT 28u -#define DEVICE2_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_MASK 0x10000000u -#define GET_DEVICE2_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_DEVICE2_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__val__) (((__val__) << 28u) & 0x10000000u) - #define REG_DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE2_H_uint32_t*)0xa0063610) /* */ -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u -#define GET_DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) -#define SET_DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_60_0MHZ 0x1u -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_30_0MHZ 0x3u -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_15_0MHZ 0x5u -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_7_5MHZ 0x7u -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_75MHZ 0x9u -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ 0x11u -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_6_25MHZ 0x13u -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_125MHZ 0x15u -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_1_563MHZ 0x17u -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_781KHZ 0x19u -#define DEVICE2_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ_DIV_1_25MHZ 0x1fu - - #define REG_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY ((volatile APE_DEVICE2_H_uint32_t*)0xa0063624) /* */ -#define DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u -#define DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u -#define GET_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) -#define SET_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) -#define DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_SHIFT 31u -#define DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_MASK 0x80000000u -#define GET_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE2_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE2_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa006362c) /* */ -#define DEVICE2_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_SHIFT 0u -#define DEVICE2_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_MASK 0xfu -#define GET_DEVICE2_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__reg__) (((__reg__) & 0xf) >> 0u) -#define SET_DEVICE2_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__val__) (((__val__) << 0u) & 0xfu) -#define DEVICE2_STATUS_CPMU_POWER_STATE_SHIFT 4u -#define DEVICE2_STATUS_CPMU_POWER_STATE_MASK 0x70u -#define GET_DEVICE2_STATUS_CPMU_POWER_STATE(__reg__) (((__reg__) & 0x70) >> 4u) -#define SET_DEVICE2_STATUS_CPMU_POWER_STATE(__val__) (((__val__) << 4u) & 0x70u) -#define DEVICE2_STATUS_ENERGY_DETECT_STATUS_SHIFT 7u -#define DEVICE2_STATUS_ENERGY_DETECT_STATUS_MASK 0x80u -#define GET_DEVICE2_STATUS_ENERGY_DETECT_STATUS(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE2_STATUS_ENERGY_DETECT_STATUS(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE2_STATUS_POWER_STATE_SHIFT 8u -#define DEVICE2_STATUS_POWER_STATE_MASK 0x300u -#define GET_DEVICE2_STATUS_POWER_STATE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE2_STATUS_POWER_STATE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE2_STATUS_VMAIN_POWER_STATUS_SHIFT 13u -#define DEVICE2_STATUS_VMAIN_POWER_STATUS_MASK 0x2000u -#define GET_DEVICE2_STATUS_VMAIN_POWER_STATUS(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE2_STATUS_VMAIN_POWER_STATUS(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_SHIFT 14u -#define DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_MASK 0x4000u -#define GET_DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_SHIFT 15u -#define DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_MASK 0x8000u -#define GET_DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE2_STATUS_NCSI_DLL_LOCK_STATUS_SHIFT 16u -#define DEVICE2_STATUS_NCSI_DLL_LOCK_STATUS_MASK 0x10000u -#define GET_DEVICE2_STATUS_NCSI_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE2_STATUS_NCSI_DLL_LOCK_STATUS(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE2_STATUS_GPHY_DLL_LOCK_STATUS_SHIFT 17u -#define DEVICE2_STATUS_GPHY_DLL_LOCK_STATUS_MASK 0x20000u -#define GET_DEVICE2_STATUS_GPHY_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x20000) >> 17u) -#define SET_DEVICE2_STATUS_GPHY_DLL_LOCK_STATUS(__val__) (((__val__) << 17u) & 0x20000u) -#define DEVICE2_STATUS_LINK_IDLE_STATUS_SHIFT 18u -#define DEVICE2_STATUS_LINK_IDLE_STATUS_MASK 0x40000u -#define GET_DEVICE2_STATUS_LINK_IDLE_STATUS(__reg__) (((__reg__) & 0x40000) >> 18u) -#define SET_DEVICE2_STATUS_LINK_IDLE_STATUS(__val__) (((__val__) << 18u) & 0x40000u) -#define DEVICE2_STATUS_ETHERNET_LINK_STATUS_SHIFT 19u -#define DEVICE2_STATUS_ETHERNET_LINK_STATUS_MASK 0x180000u -#define GET_DEVICE2_STATUS_ETHERNET_LINK_STATUS(__reg__) (((__reg__) & 0x180000) >> 19u) -#define SET_DEVICE2_STATUS_ETHERNET_LINK_STATUS(__val__) (((__val__) << 19u) & 0x180000u) -#define DEVICE2_STATUS_ETHERNET_LINK_STATUS_1000_MB 0x0u -#define DEVICE2_STATUS_ETHERNET_LINK_STATUS_100_MB 0x1u -#define DEVICE2_STATUS_ETHERNET_LINK_STATUS_10_MB 0x2u -#define DEVICE2_STATUS_ETHERNET_LINK_STATUS_NO_LINK 0x3u - -#define DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_SHIFT 21u -#define DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_MASK 0x200000u -#define GET_DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x200000) >> 21u) -#define SET_DEVICE2_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 21u) & 0x200000u) -#define DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_SHIFT 22u -#define DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_MASK 0x400000u -#define GET_DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x400000) >> 22u) -#define SET_DEVICE2_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 22u) & 0x400000u) -#define DEVICE2_STATUS_APE_STATUS_SHIFT 23u -#define DEVICE2_STATUS_APE_STATUS_MASK 0x1800000u -#define GET_DEVICE2_STATUS_APE_STATUS(__reg__) (((__reg__) & 0x1800000) >> 23u) -#define SET_DEVICE2_STATUS_APE_STATUS(__val__) (((__val__) << 23u) & 0x1800000u) -#define DEVICE2_STATUS_APE_STATUS_ACTIVE 0x0u -#define DEVICE2_STATUS_APE_STATUS_SLEEP 0x1u -#define DEVICE2_STATUS_APE_STATUS_DEEP_SLEEP 0x2u - -#define DEVICE2_STATUS_FUNCTION_ENABLE_SHIFT 25u -#define DEVICE2_STATUS_FUNCTION_ENABLE_MASK 0x3e000000u -#define GET_DEVICE2_STATUS_FUNCTION_ENABLE(__reg__) (((__reg__) & 0x3e000000) >> 25u) -#define SET_DEVICE2_STATUS_FUNCTION_ENABLE(__val__) (((__val__) << 25u) & 0x3e000000u) -#define DEVICE2_STATUS_FUNCTION_NUMBER_SHIFT 30u -#define DEVICE2_STATUS_FUNCTION_NUMBER_MASK 0xc0000000u -#define GET_DEVICE2_STATUS_FUNCTION_NUMBER(__reg__) (((__reg__) & 0xc0000000) >> 30u) -#define SET_DEVICE2_STATUS_FUNCTION_NUMBER(__val__) (((__val__) << 30u) & 0xc0000000u) - #define REG_DEVICE2_CLOCK_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa0063630) /* */ #define REG_DEVICE2_GPHY_CONTROL_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa0063638) /* */ -#define DEVICE2_GPHY_CONTROL_STATUS_GPHY_IDDQ_SHIFT 0u -#define DEVICE2_GPHY_CONTROL_STATUS_GPHY_IDDQ_MASK 0x1u -#define GET_DEVICE2_GPHY_CONTROL_STATUS_GPHY_IDDQ(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE2_GPHY_CONTROL_STATUS_GPHY_IDDQ(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE2_GPHY_CONTROL_STATUS_BIAS_IDDQ_SHIFT 1u -#define DEVICE2_GPHY_CONTROL_STATUS_BIAS_IDDQ_MASK 0x2u -#define GET_DEVICE2_GPHY_CONTROL_STATUS_BIAS_IDDQ(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_GPHY_CONTROL_STATUS_BIAS_IDDQ(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_SHIFT 2u -#define DEVICE2_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_MASK 0x4u -#define GET_DEVICE2_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE2_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE2_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 3u -#define DEVICE2_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x8u -#define GET_DEVICE2_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE2_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE2_GPHY_CONTROL_STATUS_POWER_DOWN_SHIFT 4u -#define DEVICE2_GPHY_CONTROL_STATUS_POWER_DOWN_MASK 0x10u -#define GET_DEVICE2_GPHY_CONTROL_STATUS_POWER_DOWN(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE2_GPHY_CONTROL_STATUS_POWER_DOWN(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE2_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_SHIFT 15u -#define DEVICE2_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_MASK 0x8000u -#define GET_DEVICE2_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE2_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE2_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_SHIFT 25u -#define DEVICE2_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_MASK 0x2000000u -#define GET_DEVICE2_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_DEVICE2_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__val__) (((__val__) << 25u) & 0x2000000u) -#define DEVICE2_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_SHIFT 26u -#define DEVICE2_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_MASK 0x4000000u -#define GET_DEVICE2_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__reg__) (((__reg__) & 0x4000000) >> 26u) -#define SET_DEVICE2_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__val__) (((__val__) << 26u) & 0x4000000u) -#define DEVICE2_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_SHIFT 27u -#define DEVICE2_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_MASK 0x8000000u -#define GET_DEVICE2_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__reg__) (((__reg__) & 0x8000000) >> 27u) -#define SET_DEVICE2_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__val__) (((__val__) << 27u) & 0x8000000u) - #define REG_DEVICE2_CHIP_ID ((volatile APE_DEVICE2_H_uint32_t*)0xa0063658) /* */ #define REG_DEVICE2_MUTEX_REQUEST ((volatile APE_DEVICE2_H_uint32_t*)0xa006365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */ #define REG_DEVICE2_MUTEX_GRANT ((volatile APE_DEVICE2_H_uint32_t*)0xa0063660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */ #define REG_DEVICE2_GPHY_STRAP ((volatile APE_DEVICE2_H_uint32_t*)0xa0063664) /* */ -#define DEVICE2_GPHY_STRAP_TXMBUF_ECC_ENABLE_SHIFT 2u -#define DEVICE2_GPHY_STRAP_TXMBUF_ECC_ENABLE_MASK 0x4u -#define GET_DEVICE2_GPHY_STRAP_TXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE2_GPHY_STRAP_TXMBUF_ECC_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE2_GPHY_STRAP_RXMBUF_ECC_ENABLE_SHIFT 3u -#define DEVICE2_GPHY_STRAP_RXMBUF_ECC_ENABLE_MASK 0x8u -#define GET_DEVICE2_GPHY_STRAP_RXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE2_GPHY_STRAP_RXMBUF_ECC_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE2_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_SHIFT 4u -#define DEVICE2_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_MASK 0x10u -#define GET_DEVICE2_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE2_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__val__) (((__val__) << 4u) & 0x10u) - #define REG_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile APE_DEVICE2_H_uint32_t*)0xa006367c) /* */ -#define DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_SHIFT 4u -#define DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_MASK 0x10u -#define GET_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_SHIFT 5u -#define DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_MASK 0x20u -#define GET_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE2_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__val__) (((__val__) << 5u) & 0x20u) - #define REG_DEVICE2_EEE_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa00636b0) /* */ -#define DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_SHIFT 0u -#define DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_MASK 0x1u -#define GET_DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_SHIFT 1u -#define DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_MASK 0x2u -#define GET_DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_EEE_MODE_APE_TX_DETECTION_ENABLE_SHIFT 2u -#define DEVICE2_EEE_MODE_APE_TX_DETECTION_ENABLE_MASK 0x4u -#define GET_DEVICE2_EEE_MODE_APE_TX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE2_EEE_MODE_APE_TX_DETECTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE2_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_SHIFT 3u -#define DEVICE2_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_MASK 0x8u -#define GET_DEVICE2_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE2_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE2_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_SHIFT 4u -#define DEVICE2_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_MASK 0x10u -#define GET_DEVICE2_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE2_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_SHIFT 5u -#define DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_MASK 0x20u -#define GET_DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE2_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE2_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_SHIFT 6u -#define DEVICE2_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_MASK 0x40u -#define GET_DEVICE2_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE2_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE2_EEE_MODE_USER_LPI_ENABLE_SHIFT 7u -#define DEVICE2_EEE_MODE_USER_LPI_ENABLE_MASK 0x80u -#define GET_DEVICE2_EEE_MODE_USER_LPI_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE2_EEE_MODE_USER_LPI_ENABLE(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE2_EEE_MODE_TX_LPI_ENABLE_SHIFT 8u -#define DEVICE2_EEE_MODE_TX_LPI_ENABLE_MASK 0x100u -#define GET_DEVICE2_EEE_MODE_TX_LPI_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE2_EEE_MODE_TX_LPI_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE2_EEE_MODE_RX_LPI_ENABLE_SHIFT 9u -#define DEVICE2_EEE_MODE_RX_LPI_ENABLE_MASK 0x200u -#define GET_DEVICE2_EEE_MODE_RX_LPI_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE2_EEE_MODE_RX_LPI_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE2_EEE_MODE_AUTO_WAKE_ENABLE_SHIFT 10u -#define DEVICE2_EEE_MODE_AUTO_WAKE_ENABLE_MASK 0x400u -#define GET_DEVICE2_EEE_MODE_AUTO_WAKE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE2_EEE_MODE_AUTO_WAKE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE2_EEE_MODE_BLOCK_TIME_SHIFT 11u -#define DEVICE2_EEE_MODE_BLOCK_TIME_MASK 0x7f800u -#define GET_DEVICE2_EEE_MODE_BLOCK_TIME(__reg__) (((__reg__) & 0x7f800) >> 11u) -#define SET_DEVICE2_EEE_MODE_BLOCK_TIME(__val__) (((__val__) << 11u) & 0x7f800u) -#define DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_SHIFT 19u -#define DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_MASK 0x80000u -#define GET_DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE2_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) - #define REG_DEVICE2_EEE_LINK_IDLE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00636bc) /* */ -#define DEVICE2_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_SHIFT 2u -#define DEVICE2_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_MASK 0x4u -#define GET_DEVICE2_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE2_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__val__) (((__val__) << 2u) & 0x4u) - #define REG_DEVICE2_EEE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa00636d0) /* */ -#define DEVICE2_EEE_CONTROL_EXIT_TIME_SHIFT 0u -#define DEVICE2_EEE_CONTROL_EXIT_TIME_MASK 0xffffu -#define GET_DEVICE2_EEE_CONTROL_EXIT_TIME(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE2_EEE_CONTROL_EXIT_TIME(__val__) (((__val__) << 0u) & 0xffffu) -#define DEVICE2_EEE_CONTROL_MINIMUM_ASSERT_SHIFT 16u -#define DEVICE2_EEE_CONTROL_MINIMUM_ASSERT_MASK 0xffff0000u -#define GET_DEVICE2_EEE_CONTROL_MINIMUM_ASSERT(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_DEVICE2_EEE_CONTROL_MINIMUM_ASSERT(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_DEVICE2_GLOBAL_MUTEX_REQUEST ((volatile APE_DEVICE2_H_uint32_t*)0xa00636f0) /* */ #define REG_DEVICE2_GLOBAL_MUTEX_GRANT ((volatile APE_DEVICE2_H_uint32_t*)0xa00636f4) /* */ #define REG_DEVICE2_MEMORY_ARBITER_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0064000) /* */ -#define DEVICE2_MEMORY_ARBITER_MODE_ENABLE_SHIFT 1u -#define DEVICE2_MEMORY_ARBITER_MODE_ENABLE_MASK 0x2u -#define GET_DEVICE2_MEMORY_ARBITER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_MEMORY_ARBITER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) - #define REG_DEVICE2_BUFFER_MANAGER_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0064400) /* */ -#define DEVICE2_BUFFER_MANAGER_MODE_ENABLE_SHIFT 1u -#define DEVICE2_BUFFER_MANAGER_MODE_ENABLE_MASK 0x2u -#define GET_DEVICE2_BUFFER_MANAGER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_BUFFER_MANAGER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_SHIFT 2u -#define DEVICE2_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_MASK 0x4u -#define GET_DEVICE2_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE2_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE2_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_SHIFT 5u -#define DEVICE2_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_MASK 0x20u -#define GET_DEVICE2_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE2_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__val__) (((__val__) << 5u) & 0x20u) - #define REG_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0064910) /* */ -#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_SHIFT 16u -#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_MASK 0x30000u -#define GET_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__reg__) (((__reg__) & 0x30000) >> 16u) -#define SET_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__val__) (((__val__) << 16u) & 0x30000u) -#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_128B 0x0u -#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_256B 0x1u -#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_512B 0x2u -#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_4K 0x3u - -#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_SHIFT 18u -#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_MASK 0xc0000u -#define GET_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__reg__) (((__reg__) & 0xc0000) >> 18u) -#define SET_DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__val__) (((__val__) << 18u) & 0xc0000u) -#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_128B 0x0u -#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_256B 0x1u -#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_512B 0x2u -#define DEVICE2_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_4K 0x3u - - #define REG_DEVICE2_RX_RISC_MODE ((volatile APE_DEVICE2_H_uint32_t*)0xa0065000) /* */ -#define DEVICE2_RX_RISC_MODE_RESET_SHIFT 0u -#define DEVICE2_RX_RISC_MODE_RESET_MASK 0x1u -#define GET_DEVICE2_RX_RISC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE2_RX_RISC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE2_RX_RISC_MODE_SINGLE_STEP_SHIFT 1u -#define DEVICE2_RX_RISC_MODE_SINGLE_STEP_MASK 0x2u -#define GET_DEVICE2_RX_RISC_MODE_SINGLE_STEP(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_RX_RISC_MODE_SINGLE_STEP(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_RX_RISC_MODE_PAGE_0_DATA_HALT_SHIFT 2u -#define DEVICE2_RX_RISC_MODE_PAGE_0_DATA_HALT_MASK 0x4u -#define GET_DEVICE2_RX_RISC_MODE_PAGE_0_DATA_HALT(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE2_RX_RISC_MODE_PAGE_0_DATA_HALT(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE2_RX_RISC_MODE_PAGE_0_INSTR_HALT_SHIFT 3u -#define DEVICE2_RX_RISC_MODE_PAGE_0_INSTR_HALT_MASK 0x8u -#define GET_DEVICE2_RX_RISC_MODE_PAGE_0_INSTR_HALT(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE2_RX_RISC_MODE_PAGE_0_INSTR_HALT(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE2_RX_RISC_MODE_ENABLE_DATA_CACHE_SHIFT 5u -#define DEVICE2_RX_RISC_MODE_ENABLE_DATA_CACHE_MASK 0x20u -#define GET_DEVICE2_RX_RISC_MODE_ENABLE_DATA_CACHE(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE2_RX_RISC_MODE_ENABLE_DATA_CACHE(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE2_RX_RISC_MODE_ROM_FAIL_SHIFT 6u -#define DEVICE2_RX_RISC_MODE_ROM_FAIL_MASK 0x40u -#define GET_DEVICE2_RX_RISC_MODE_ROM_FAIL(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE2_RX_RISC_MODE_ROM_FAIL(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE2_RX_RISC_MODE_ENABLE_WATCHDOG_SHIFT 7u -#define DEVICE2_RX_RISC_MODE_ENABLE_WATCHDOG_MASK 0x80u -#define GET_DEVICE2_RX_RISC_MODE_ENABLE_WATCHDOG(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE2_RX_RISC_MODE_ENABLE_WATCHDOG(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE2_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_SHIFT 8u -#define DEVICE2_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_MASK 0x100u -#define GET_DEVICE2_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE2_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE2_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_SHIFT 9u -#define DEVICE2_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_MASK 0x200u -#define GET_DEVICE2_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE2_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE2_RX_RISC_MODE_HALT_SHIFT 10u -#define DEVICE2_RX_RISC_MODE_HALT_MASK 0x400u -#define GET_DEVICE2_RX_RISC_MODE_HALT(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE2_RX_RISC_MODE_HALT(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE2_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_SHIFT 11u -#define DEVICE2_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_MASK 0x800u -#define GET_DEVICE2_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE2_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE2_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_SHIFT 12u -#define DEVICE2_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_MASK 0x1000u -#define GET_DEVICE2_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_DEVICE2_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__val__) (((__val__) << 12u) & 0x1000u) -#define DEVICE2_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_SHIFT 13u -#define DEVICE2_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_MASK 0x2000u -#define GET_DEVICE2_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE2_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE2_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_SHIFT 14u -#define DEVICE2_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_MASK 0x4000u -#define GET_DEVICE2_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE2_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__val__) (((__val__) << 14u) & 0x4000u) - #define REG_DEVICE2_RX_RISC_STATUS ((volatile APE_DEVICE2_H_uint32_t*)0xa0065004) /* */ -#define DEVICE2_RX_RISC_STATUS_HARDWARE_BREAKPOINT_SHIFT 0u -#define DEVICE2_RX_RISC_STATUS_HARDWARE_BREAKPOINT_MASK 0x1u -#define GET_DEVICE2_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE2_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE2_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_SHIFT 1u -#define DEVICE2_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_MASK 0x2u -#define GET_DEVICE2_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_SHIFT 2u -#define DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_MASK 0x4u -#define GET_DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE2_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_SHIFT 3u -#define DEVICE2_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_MASK 0x8u -#define GET_DEVICE2_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE2_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE2_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_SHIFT 4u -#define DEVICE2_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_MASK 0x10u -#define GET_DEVICE2_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE2_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE2_RX_RISC_STATUS_INVALID_DATA_ACCESS_SHIFT 5u -#define DEVICE2_RX_RISC_STATUS_INVALID_DATA_ACCESS_MASK 0x20u -#define GET_DEVICE2_RX_RISC_STATUS_INVALID_DATA_ACCESS(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE2_RX_RISC_STATUS_INVALID_DATA_ACCESS(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_SHIFT 6u -#define DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_MASK 0x40u -#define GET_DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE2_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE2_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_SHIFT 7u -#define DEVICE2_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_MASK 0x80u -#define GET_DEVICE2_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE2_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE2_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_SHIFT 8u -#define DEVICE2_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_MASK 0x100u -#define GET_DEVICE2_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE2_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE2_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_SHIFT 9u -#define DEVICE2_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_MASK 0x200u -#define GET_DEVICE2_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE2_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE2_RX_RISC_STATUS_HALTED_SHIFT 10u -#define DEVICE2_RX_RISC_STATUS_HALTED_MASK 0x400u -#define GET_DEVICE2_RX_RISC_STATUS_HALTED(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE2_RX_RISC_STATUS_HALTED(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE2_RX_RISC_STATUS_UNKNOWN_SHIFT 11u -#define DEVICE2_RX_RISC_STATUS_UNKNOWN_MASK 0x800u -#define GET_DEVICE2_RX_RISC_STATUS_UNKNOWN(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE2_RX_RISC_STATUS_UNKNOWN(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE2_RX_RISC_STATUS_DATA_ACCESS_STALL_SHIFT 14u -#define DEVICE2_RX_RISC_STATUS_DATA_ACCESS_STALL_MASK 0x4000u -#define GET_DEVICE2_RX_RISC_STATUS_DATA_ACCESS_STALL(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE2_RX_RISC_STATUS_DATA_ACCESS_STALL(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE2_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_SHIFT 15u -#define DEVICE2_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_MASK 0x8000u -#define GET_DEVICE2_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE2_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE2_RX_RISC_STATUS_BLOCKING_READ_SHIFT 31u -#define DEVICE2_RX_RISC_STATUS_BLOCKING_READ_MASK 0x80000000u -#define GET_DEVICE2_RX_RISC_STATUS_BLOCKING_READ(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE2_RX_RISC_STATUS_BLOCKING_READ(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE2_RX_RISC_PROGRAM_COUNTER ((volatile APE_DEVICE2_H_uint32_t*)0xa006501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ #define REG_DEVICE2_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE2_H_uint32_t*)0xa0065020) /* This undocumented register contains the current word located at the program counter address loaded in */ #define REG_DEVICE2_RX_RISC_HARDWARE_BREAKPOINT ((volatile APE_DEVICE2_H_uint32_t*)0xa0065034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ @@ -1125,32 +178,9 @@ typedef uint32_t APE_DEVICE2_H_uint32_t; #define REG_DEVICE2_PCI_POWER_CONSUMPTION_INFO ((volatile APE_DEVICE2_H_uint32_t*)0xa0066410) /* This undocumented register is used to set PCIe Power Consumption information as reported in configuration space. It is loaded from NVM configuration data. */ #define REG_DEVICE2_PCI_POWER_DISSIPATED_INFO ((volatile APE_DEVICE2_H_uint32_t*)0xa0066414) /* This undocumented register is used to set PCIe Power Dissipated information as reported in configuration space. It is loaded from NVM configuration data. */ #define REG_DEVICE2_PCI_VPD_REQUEST ((volatile APE_DEVICE2_H_uint32_t*)0xa006642c) /* This undocumented register appears to be used to implement the PCI VPD capability. It is set to the VPD offset which was requested by the host by writing to the VPD register. */ -#define DEVICE2_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_SHIFT 16u -#define DEVICE2_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_MASK 0x7fff0000u -#define GET_DEVICE2_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__reg__) (((__reg__) & 0x7fff0000) >> 16u) -#define SET_DEVICE2_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__val__) (((__val__) << 16u) & 0x7fff0000u) - #define REG_DEVICE2_PCI_VPD_RESPONSE ((volatile APE_DEVICE2_H_uint32_t*)0xa0066430) /* This undocumented register appears to be used to implement the PCI VPD capability. Bootcode writes the 32 bits of data loaded from the word requested by */ #define REG_DEVICE2_PCI_VENDOR_DEVICE_ID ((volatile APE_DEVICE2_H_uint32_t*)0xa0066434) /* This is the undocumented register used to set the PCI Vendor/Device ID, which is configurable from NVM. */ -#define DEVICE2_PCI_VENDOR_DEVICE_ID_DEVICE_ID_SHIFT 0u -#define DEVICE2_PCI_VENDOR_DEVICE_ID_DEVICE_ID_MASK 0xffffu -#define GET_DEVICE2_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE2_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__val__) (((__val__) << 0u) & 0xffffu) -#define DEVICE2_PCI_VENDOR_DEVICE_ID_VENDOR_ID_SHIFT 16u -#define DEVICE2_PCI_VENDOR_DEVICE_ID_VENDOR_ID_MASK 0xffff0000u -#define GET_DEVICE2_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_DEVICE2_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_DEVICE2_PCI_SUBSYSTEM_ID ((volatile APE_DEVICE2_H_uint32_t*)0xa0066438) /* This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM. */ -#define DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0u -#define DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_MASK 0xffffu -#define GET_DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__val__) (((__val__) << 0u) & 0xffffu) -#define DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_SHIFT 16u -#define DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_MASK 0xffff0000u -#define GET_DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_DEVICE2_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_DEVICE2_PCI_CLASS_CODE_REVISION ((volatile APE_DEVICE2_H_uint32_t*)0xa006643c) /* This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed. */ #define REG_DEVICE2_64C0 ((volatile APE_DEVICE2_H_uint32_t*)0xa00664c0) /* */ #define REG_DEVICE2_64C8 ((volatile APE_DEVICE2_H_uint32_t*)0xa00664c8) /* */ @@ -1158,548 +188,28 @@ typedef uint32_t APE_DEVICE2_H_uint32_t; #define REG_DEVICE2_PCI_SERIAL_NUMBER_LOW ((volatile APE_DEVICE2_H_uint32_t*)0xa0066504) /* This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ #define REG_DEVICE2_PCI_SERIAL_NUMBER_HIGH ((volatile APE_DEVICE2_H_uint32_t*)0xa0066508) /* This sets the high 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ #define REG_DEVICE2_PCI_POWER_BUDGET_0 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066510) /* Used to report power budget capability data to the host. The values are loaded from NVM, and up to eight values may be specified. */ -#define DEVICE2_PCI_POWER_BUDGET_0_BASE_POWER_SHIFT 0u -#define DEVICE2_PCI_POWER_BUDGET_0_BASE_POWER_MASK 0xffu -#define GET_DEVICE2_PCI_POWER_BUDGET_0_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE2_PCI_POWER_BUDGET_0_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_SHIFT 8u -#define DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_MASK 0x300u -#define GET_DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_1_0X 0x0u -#define DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_0_1X 0x1u -#define DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_0_01X 0x2u -#define DEVICE2_PCI_POWER_BUDGET_0_DATA_SCALE_0_001X 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_0_PM_SUB_STATE_SHIFT 10u -#define DEVICE2_PCI_POWER_BUDGET_0_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE2_PCI_POWER_BUDGET_0_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE2_PCI_POWER_BUDGET_0_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_SHIFT 13u -#define DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_MASK 0x6000u -#define GET_DEVICE2_PCI_POWER_BUDGET_0_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE2_PCI_POWER_BUDGET_0_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_D0 0x0u -#define DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_D1 0x1u -#define DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_D2 0x2u -#define DEVICE2_PCI_POWER_BUDGET_0_PM_STATE_D3 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_SHIFT 15u -#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_MASK 0x38000u -#define GET_DEVICE2_PCI_POWER_BUDGET_0_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE2_PCI_POWER_BUDGET_0_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_PME_AUX 0x0u -#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_AUXILIARY 0x1u -#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_IDLE 0x2u -#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_SUSTAINED 0x3u -#define DEVICE2_PCI_POWER_BUDGET_0_TYPE_MAXIMUM 0x7u - -#define DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_SHIFT 18u -#define DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_12V 0x0u -#define DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE2_PCI_POWER_BUDGET_0_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE2_PCI_POWER_BUDGET_1 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066514) /* See */ -#define DEVICE2_PCI_POWER_BUDGET_1_BASE_POWER_SHIFT 0u -#define DEVICE2_PCI_POWER_BUDGET_1_BASE_POWER_MASK 0xffu -#define GET_DEVICE2_PCI_POWER_BUDGET_1_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE2_PCI_POWER_BUDGET_1_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_SHIFT 8u -#define DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_MASK 0x300u -#define GET_DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_1_0X 0x0u -#define DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_0_1X 0x1u -#define DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_0_01X 0x2u -#define DEVICE2_PCI_POWER_BUDGET_1_DATA_SCALE_0_001X 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_1_PM_SUB_STATE_SHIFT 10u -#define DEVICE2_PCI_POWER_BUDGET_1_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE2_PCI_POWER_BUDGET_1_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE2_PCI_POWER_BUDGET_1_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_SHIFT 13u -#define DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_MASK 0x6000u -#define GET_DEVICE2_PCI_POWER_BUDGET_1_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE2_PCI_POWER_BUDGET_1_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_D0 0x0u -#define DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_D1 0x1u -#define DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_D2 0x2u -#define DEVICE2_PCI_POWER_BUDGET_1_PM_STATE_D3 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_SHIFT 15u -#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_MASK 0x38000u -#define GET_DEVICE2_PCI_POWER_BUDGET_1_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE2_PCI_POWER_BUDGET_1_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_PME_AUX 0x0u -#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_AUXILIARY 0x1u -#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_IDLE 0x2u -#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_SUSTAINED 0x3u -#define DEVICE2_PCI_POWER_BUDGET_1_TYPE_MAXIMUM 0x7u - -#define DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_SHIFT 18u -#define DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_12V 0x0u -#define DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE2_PCI_POWER_BUDGET_1_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE2_PCI_POWER_BUDGET_2 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066518) /* See */ -#define DEVICE2_PCI_POWER_BUDGET_2_BASE_POWER_SHIFT 0u -#define DEVICE2_PCI_POWER_BUDGET_2_BASE_POWER_MASK 0xffu -#define GET_DEVICE2_PCI_POWER_BUDGET_2_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE2_PCI_POWER_BUDGET_2_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_SHIFT 8u -#define DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_MASK 0x300u -#define GET_DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_1_0X 0x0u -#define DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_0_1X 0x1u -#define DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_0_01X 0x2u -#define DEVICE2_PCI_POWER_BUDGET_2_DATA_SCALE_0_001X 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_2_PM_SUB_STATE_SHIFT 10u -#define DEVICE2_PCI_POWER_BUDGET_2_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE2_PCI_POWER_BUDGET_2_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE2_PCI_POWER_BUDGET_2_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_SHIFT 13u -#define DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_MASK 0x6000u -#define GET_DEVICE2_PCI_POWER_BUDGET_2_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE2_PCI_POWER_BUDGET_2_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_D0 0x0u -#define DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_D1 0x1u -#define DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_D2 0x2u -#define DEVICE2_PCI_POWER_BUDGET_2_PM_STATE_D3 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_SHIFT 15u -#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_MASK 0x38000u -#define GET_DEVICE2_PCI_POWER_BUDGET_2_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE2_PCI_POWER_BUDGET_2_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_PME_AUX 0x0u -#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_AUXILIARY 0x1u -#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_IDLE 0x2u -#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_SUSTAINED 0x3u -#define DEVICE2_PCI_POWER_BUDGET_2_TYPE_MAXIMUM 0x7u - -#define DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_SHIFT 18u -#define DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_12V 0x0u -#define DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE2_PCI_POWER_BUDGET_2_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE2_PCI_POWER_BUDGET_3 ((volatile APE_DEVICE2_H_uint32_t*)0xa006651c) /* See */ -#define DEVICE2_PCI_POWER_BUDGET_3_BASE_POWER_SHIFT 0u -#define DEVICE2_PCI_POWER_BUDGET_3_BASE_POWER_MASK 0xffu -#define GET_DEVICE2_PCI_POWER_BUDGET_3_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE2_PCI_POWER_BUDGET_3_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_SHIFT 8u -#define DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_MASK 0x300u -#define GET_DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_1_0X 0x0u -#define DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_0_1X 0x1u -#define DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_0_01X 0x2u -#define DEVICE2_PCI_POWER_BUDGET_3_DATA_SCALE_0_001X 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_3_PM_SUB_STATE_SHIFT 10u -#define DEVICE2_PCI_POWER_BUDGET_3_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE2_PCI_POWER_BUDGET_3_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE2_PCI_POWER_BUDGET_3_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_SHIFT 13u -#define DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_MASK 0x6000u -#define GET_DEVICE2_PCI_POWER_BUDGET_3_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE2_PCI_POWER_BUDGET_3_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_D0 0x0u -#define DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_D1 0x1u -#define DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_D2 0x2u -#define DEVICE2_PCI_POWER_BUDGET_3_PM_STATE_D3 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_SHIFT 15u -#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_MASK 0x38000u -#define GET_DEVICE2_PCI_POWER_BUDGET_3_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE2_PCI_POWER_BUDGET_3_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_PME_AUX 0x0u -#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_AUXILIARY 0x1u -#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_IDLE 0x2u -#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_SUSTAINED 0x3u -#define DEVICE2_PCI_POWER_BUDGET_3_TYPE_MAXIMUM 0x7u - -#define DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_SHIFT 18u -#define DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_12V 0x0u -#define DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE2_PCI_POWER_BUDGET_3_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE2_PCI_POWER_BUDGET_4 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066520) /* See */ -#define DEVICE2_PCI_POWER_BUDGET_4_BASE_POWER_SHIFT 0u -#define DEVICE2_PCI_POWER_BUDGET_4_BASE_POWER_MASK 0xffu -#define GET_DEVICE2_PCI_POWER_BUDGET_4_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE2_PCI_POWER_BUDGET_4_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_SHIFT 8u -#define DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_MASK 0x300u -#define GET_DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_1_0X 0x0u -#define DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_0_1X 0x1u -#define DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_0_01X 0x2u -#define DEVICE2_PCI_POWER_BUDGET_4_DATA_SCALE_0_001X 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_4_PM_SUB_STATE_SHIFT 10u -#define DEVICE2_PCI_POWER_BUDGET_4_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE2_PCI_POWER_BUDGET_4_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE2_PCI_POWER_BUDGET_4_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_SHIFT 13u -#define DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_MASK 0x6000u -#define GET_DEVICE2_PCI_POWER_BUDGET_4_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE2_PCI_POWER_BUDGET_4_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_D0 0x0u -#define DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_D1 0x1u -#define DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_D2 0x2u -#define DEVICE2_PCI_POWER_BUDGET_4_PM_STATE_D3 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_SHIFT 15u -#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_MASK 0x38000u -#define GET_DEVICE2_PCI_POWER_BUDGET_4_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE2_PCI_POWER_BUDGET_4_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_PME_AUX 0x0u -#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_AUXILIARY 0x1u -#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_IDLE 0x2u -#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_SUSTAINED 0x3u -#define DEVICE2_PCI_POWER_BUDGET_4_TYPE_MAXIMUM 0x7u - -#define DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_SHIFT 18u -#define DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_12V 0x0u -#define DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE2_PCI_POWER_BUDGET_4_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE2_PCI_POWER_BUDGET_5 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066524) /* See */ -#define DEVICE2_PCI_POWER_BUDGET_5_BASE_POWER_SHIFT 0u -#define DEVICE2_PCI_POWER_BUDGET_5_BASE_POWER_MASK 0xffu -#define GET_DEVICE2_PCI_POWER_BUDGET_5_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE2_PCI_POWER_BUDGET_5_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_SHIFT 8u -#define DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_MASK 0x300u -#define GET_DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_1_0X 0x0u -#define DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_0_1X 0x1u -#define DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_0_01X 0x2u -#define DEVICE2_PCI_POWER_BUDGET_5_DATA_SCALE_0_001X 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_5_PM_SUB_STATE_SHIFT 10u -#define DEVICE2_PCI_POWER_BUDGET_5_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE2_PCI_POWER_BUDGET_5_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE2_PCI_POWER_BUDGET_5_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_SHIFT 13u -#define DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_MASK 0x6000u -#define GET_DEVICE2_PCI_POWER_BUDGET_5_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE2_PCI_POWER_BUDGET_5_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_D0 0x0u -#define DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_D1 0x1u -#define DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_D2 0x2u -#define DEVICE2_PCI_POWER_BUDGET_5_PM_STATE_D3 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_SHIFT 15u -#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_MASK 0x38000u -#define GET_DEVICE2_PCI_POWER_BUDGET_5_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE2_PCI_POWER_BUDGET_5_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_PME_AUX 0x0u -#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_AUXILIARY 0x1u -#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_IDLE 0x2u -#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_SUSTAINED 0x3u -#define DEVICE2_PCI_POWER_BUDGET_5_TYPE_MAXIMUM 0x7u - -#define DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_SHIFT 18u -#define DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_12V 0x0u -#define DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE2_PCI_POWER_BUDGET_5_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE2_PCI_POWER_BUDGET_6 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066528) /* See */ -#define DEVICE2_PCI_POWER_BUDGET_6_BASE_POWER_SHIFT 0u -#define DEVICE2_PCI_POWER_BUDGET_6_BASE_POWER_MASK 0xffu -#define GET_DEVICE2_PCI_POWER_BUDGET_6_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE2_PCI_POWER_BUDGET_6_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_SHIFT 8u -#define DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_MASK 0x300u -#define GET_DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_1_0X 0x0u -#define DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_0_1X 0x1u -#define DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_0_01X 0x2u -#define DEVICE2_PCI_POWER_BUDGET_6_DATA_SCALE_0_001X 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_6_PM_SUB_STATE_SHIFT 10u -#define DEVICE2_PCI_POWER_BUDGET_6_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE2_PCI_POWER_BUDGET_6_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE2_PCI_POWER_BUDGET_6_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_SHIFT 13u -#define DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_MASK 0x6000u -#define GET_DEVICE2_PCI_POWER_BUDGET_6_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE2_PCI_POWER_BUDGET_6_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_D0 0x0u -#define DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_D1 0x1u -#define DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_D2 0x2u -#define DEVICE2_PCI_POWER_BUDGET_6_PM_STATE_D3 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_SHIFT 15u -#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_MASK 0x38000u -#define GET_DEVICE2_PCI_POWER_BUDGET_6_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE2_PCI_POWER_BUDGET_6_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_PME_AUX 0x0u -#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_AUXILIARY 0x1u -#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_IDLE 0x2u -#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_SUSTAINED 0x3u -#define DEVICE2_PCI_POWER_BUDGET_6_TYPE_MAXIMUM 0x7u - -#define DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_SHIFT 18u -#define DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_12V 0x0u -#define DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE2_PCI_POWER_BUDGET_6_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE2_PCI_POWER_BUDGET_7 ((volatile APE_DEVICE2_H_uint32_t*)0xa006652c) /* See */ -#define DEVICE2_PCI_POWER_BUDGET_7_BASE_POWER_SHIFT 0u -#define DEVICE2_PCI_POWER_BUDGET_7_BASE_POWER_MASK 0xffu -#define GET_DEVICE2_PCI_POWER_BUDGET_7_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE2_PCI_POWER_BUDGET_7_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_SHIFT 8u -#define DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_MASK 0x300u -#define GET_DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_1_0X 0x0u -#define DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_0_1X 0x1u -#define DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_0_01X 0x2u -#define DEVICE2_PCI_POWER_BUDGET_7_DATA_SCALE_0_001X 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_7_PM_SUB_STATE_SHIFT 10u -#define DEVICE2_PCI_POWER_BUDGET_7_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE2_PCI_POWER_BUDGET_7_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE2_PCI_POWER_BUDGET_7_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_SHIFT 13u -#define DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_MASK 0x6000u -#define GET_DEVICE2_PCI_POWER_BUDGET_7_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE2_PCI_POWER_BUDGET_7_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_D0 0x0u -#define DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_D1 0x1u -#define DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_D2 0x2u -#define DEVICE2_PCI_POWER_BUDGET_7_PM_STATE_D3 0x3u - -#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_SHIFT 15u -#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_MASK 0x38000u -#define GET_DEVICE2_PCI_POWER_BUDGET_7_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE2_PCI_POWER_BUDGET_7_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_PME_AUX 0x0u -#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_AUXILIARY 0x1u -#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_IDLE 0x2u -#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_SUSTAINED 0x3u -#define DEVICE2_PCI_POWER_BUDGET_7_TYPE_MAXIMUM 0x7u - -#define DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_SHIFT 18u -#define DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_12V 0x0u -#define DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE2_PCI_POWER_BUDGET_7_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE2_6530 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066530) /* */ #define REG_DEVICE2_6550 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066550) /* The LSB in this undocumented and unknown register is set if the device is a LOM (LAN-on-Motherboard) design (i.e., builtin to a system and not an expansion card). */ #define REG_DEVICE2_65F4 ((volatile APE_DEVICE2_H_uint32_t*)0xa00665f4) /* */ #define REG_DEVICE2_GRC_MODE_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0066800) /* */ -#define DEVICE2_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_SHIFT 19u -#define DEVICE2_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_MASK 0x80000u -#define GET_DEVICE2_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE2_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) -#define DEVICE2_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_SHIFT 21u -#define DEVICE2_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_MASK 0x200000u -#define GET_DEVICE2_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__reg__) (((__reg__) & 0x200000) >> 21u) -#define SET_DEVICE2_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__val__) (((__val__) << 21u) & 0x200000u) -#define DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_SHIFT 22u -#define DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_MASK 0x400000u -#define GET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__reg__) (((__reg__) & 0x400000) >> 22u) -#define SET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__val__) (((__val__) << 22u) & 0x400000u) -#define DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_SHIFT 29u -#define DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_MASK 0x20000000u -#define GET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__val__) (((__val__) << 29u) & 0x20000000u) -#define DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_SHIFT 31u -#define DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_MASK 0x80000000u -#define GET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE2_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE2_MISCELLANEOUS_CONFIG ((volatile APE_DEVICE2_H_uint32_t*)0xa0066804) /* */ -#define DEVICE2_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 1u -#define DEVICE2_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x2u -#define GET_DEVICE2_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE2_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE2_MISCELLANEOUS_CONFIG_ALL_SHIFT 1u -#define DEVICE2_MISCELLANEOUS_CONFIG_ALL_MASK 0xfffffffeu -#define GET_DEVICE2_MISCELLANEOUS_CONFIG_ALL(__reg__) (((__reg__) & 0xfffffffe) >> 1u) -#define SET_DEVICE2_MISCELLANEOUS_CONFIG_ALL(__val__) (((__val__) << 1u) & 0xfffffffeu) - #define REG_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0066808) /* */ -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_SHIFT 8u -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_MASK 0x100u -#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_SHIFT 9u -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_MASK 0x200u -#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_SHIFT 10u -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_MASK 0x400u -#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_SHIFT 11u -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_MASK 0x800u -#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_SHIFT 12u -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_MASK 0x1000u -#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__val__) (((__val__) << 12u) & 0x1000u) -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_SHIFT 13u -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_MASK 0x2000u -#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_SHIFT 14u -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_MASK 0x4000u -#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_SHIFT 15u -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_MASK 0x8000u -#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_SHIFT 16u -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_MASK 0x10000u -#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_SHIFT 24u -#define DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_MASK 0x1000000u -#define GET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_DEVICE2_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__val__) (((__val__) << 24u) & 0x1000000u) - #define REG_DEVICE2_TIMER ((volatile APE_DEVICE2_H_uint32_t*)0xa006680c) /* 32-bit free-running counter */ #define REG_DEVICE2_RX_CPU_EVENT ((volatile APE_DEVICE2_H_uint32_t*)0xa0066810) /* */ -#define DEVICE2_RX_CPU_EVENT_MAC_ATTENTION_SHIFT 25u -#define DEVICE2_RX_CPU_EVENT_MAC_ATTENTION_MASK 0x2000000u -#define GET_DEVICE2_RX_CPU_EVENT_MAC_ATTENTION(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_DEVICE2_RX_CPU_EVENT_MAC_ATTENTION(__val__) (((__val__) << 25u) & 0x2000000u) -#define DEVICE2_RX_CPU_EVENT_RX_CPU_ATTENTION_SHIFT 26u -#define DEVICE2_RX_CPU_EVENT_RX_CPU_ATTENTION_MASK 0x4000000u -#define GET_DEVICE2_RX_CPU_EVENT_RX_CPU_ATTENTION(__reg__) (((__reg__) & 0x4000000) >> 26u) -#define SET_DEVICE2_RX_CPU_EVENT_RX_CPU_ATTENTION(__val__) (((__val__) << 26u) & 0x4000000u) -#define DEVICE2_RX_CPU_EVENT_TIMER_SHIFT 29u -#define DEVICE2_RX_CPU_EVENT_TIMER_MASK 0x20000000u -#define GET_DEVICE2_RX_CPU_EVENT_TIMER(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_DEVICE2_RX_CPU_EVENT_TIMER(__val__) (((__val__) << 29u) & 0x20000000u) -#define DEVICE2_RX_CPU_EVENT_VPD_ATTENTION_SHIFT 30u -#define DEVICE2_RX_CPU_EVENT_VPD_ATTENTION_MASK 0x40000000u -#define GET_DEVICE2_RX_CPU_EVENT_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_DEVICE2_RX_CPU_EVENT_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) - #define REG_DEVICE2_6838 ((volatile APE_DEVICE2_H_uint32_t*)0xa0066838) /* Unknown. Used by PXE agent. */ #define REG_DEVICE2_MDI_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0066844) /* The register manual only mentions this in the changelog; it was removed from the manual in a previous revision. :| */ #define REG_DEVICE2_RX_CPU_EVENT_ENABLE ((volatile APE_DEVICE2_H_uint32_t*)0xa006684c) /* */ -#define DEVICE2_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_SHIFT 30u -#define DEVICE2_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_MASK 0x40000000u -#define GET_DEVICE2_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_DEVICE2_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) - #define REG_DEVICE2_FAST_BOOT_PROGRAM_COUNTER ((volatile APE_DEVICE2_H_uint32_t*)0xa0066894) /* */ -#define DEVICE2_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_SHIFT 0u -#define DEVICE2_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_MASK 0x7fffffffu -#define GET_DEVICE2_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__reg__) (((__reg__) & 0x7fffffff) >> 0u) -#define SET_DEVICE2_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__val__) (((__val__) << 0u) & 0x7fffffffu) -#define DEVICE2_FAST_BOOT_PROGRAM_COUNTER_ENABLE_SHIFT 31u -#define DEVICE2_FAST_BOOT_PROGRAM_COUNTER_ENABLE_MASK 0x80000000u -#define GET_DEVICE2_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE2_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE2_EXPANSION_ROM_ADDR ((volatile APE_DEVICE2_H_uint32_t*)0xa00668ec) /* Expansion ROM base address, expect to be d- word aligned. */ #define REG_DEVICE2_68F0 ((volatile APE_DEVICE2_H_uint32_t*)0xa00668f0) /* */ #define REG_DEVICE2_EAV_REF_CLOCK_CONTROL ((volatile APE_DEVICE2_H_uint32_t*)0xa0066908) /* */ -#define DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SHIFT 16u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_MASK 0x30000u -#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__reg__) (((__reg__) & 0x30000) >> 16u) -#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__val__) (((__val__) << 16u) & 0x30000u) -#define DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_0_ 0x0u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_1_ 0x1u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_0_ 0x2u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_1_ 0x3u - -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SHIFT 18u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_MASK 0x1c0000u -#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_NOT_USED 0x0u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_0_ 0x4u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_1_ 0x5u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_0_ 0x6u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_1_ 0x7u - -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SHIFT 21u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_MASK 0xe00000u -#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__reg__) (((__reg__) & 0xe00000) >> 21u) -#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__val__) (((__val__) << 21u) & 0xe00000u) -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_NOT_USED 0x0u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_0_ 0x4u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_1_ 0x5u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_0_ 0x6u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_1_ 0x7u - -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SHIFT 24u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_MASK 0x7000000u -#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__reg__) (((__reg__) & 0x7000000) >> 24u) -#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__val__) (((__val__) << 24u) & 0x7000000u) -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_NOT_USED 0x0u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_0_ 0x4u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_1_ 0x5u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_0_ 0x6u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_1_ 0x7u - -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SHIFT 27u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_MASK 0x38000000u -#define GET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__reg__) (((__reg__) & 0x38000000) >> 27u) -#define SET_DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__val__) (((__val__) << 27u) & 0x38000000u) -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_NOT_USED 0x0u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_0_ 0x4u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_1_ 0x5u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_0_ 0x6u -#define DEVICE2_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_1_ 0x7u - - #define REG_DEVICE2_7C04 ((volatile APE_DEVICE2_H_uint32_t*)0xa0067c04) /* PCIe-related. tg3 driver calls this */ /** @brief Device Registers, function 2 */ extern volatile DEVICE_t DEVICE2; diff --git a/include/APE_DEVICE3.h b/include/APE_DEVICE3.h index a2917b6..e274848 100644 --- a/include/APE_DEVICE3.h +++ b/include/APE_DEVICE3.h @@ -83,333 +83,17 @@ typedef uint32_t APE_DEVICE3_H_uint32_t; #define REG_DEVICE3_SIZE (sizeof(DEVICE_t)) #define REG_DEVICE3_MISCELLANEOUS_HOST_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0070068) /* */ -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x1u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x2u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x4u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x8u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 4u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x10u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_SHIFT 5u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY_MASK 0x20u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_DIV_WRITE_CAPABILITY(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x40u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x80u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x100u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x200u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x400u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x800u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x1000u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK(__val__) (((__val__) << 12u) & 0x1000u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x2000u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x4000u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x8000u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_SHIFT 16u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_MASK 0xff0000u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__reg__) (((__reg__) & 0xff0000) >> 16u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID(__val__) (((__val__) << 16u) & 0xff0000u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_0 0x0u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_1 0x1u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_METAL_REV_ID_2 0x2u - -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_SHIFT 24u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_MASK 0xf000000u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__reg__) (((__reg__) & 0xf000000) >> 24u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID(__val__) (((__val__) << 24u) & 0xf000000u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_A 0x0u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_B 0x1u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_ALL_LAYER_ID_C 0x2u - -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 28u -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xf0000000u -#define GET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__reg__) (((__reg__) & 0xf0000000) >> 28u) -#define SET_DEVICE3_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID(__val__) (((__val__) << 28u) & 0xf0000000u) -#define DEVICE3_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_NEW_PRODUCT_MAPPING 0xfu - - #define REG_DEVICE3_PCI_STATE ((volatile APE_DEVICE3_H_uint32_t*)0xa0070070) /* */ -#define DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5u -#define DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x20u -#define GET_DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_DESIRED(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6u -#define DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x40u -#define GET_DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE3_PCI_STATE_PCI_EXPANSION_ROM_RETRY(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE3_PCI_STATE_VPD_AVAILABLE_SHIFT 7u -#define DEVICE3_PCI_STATE_VPD_AVAILABLE_MASK 0x80u -#define GET_DEVICE3_PCI_STATE_VPD_AVAILABLE(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE3_PCI_STATE_VPD_AVAILABLE(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE3_PCI_STATE_FLAT_VIEW_SHIFT 8u -#define DEVICE3_PCI_STATE_FLAT_VIEW_MASK 0x100u -#define GET_DEVICE3_PCI_STATE_FLAT_VIEW(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE3_PCI_STATE_FLAT_VIEW(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE3_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9u -#define DEVICE3_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0xe00u -#define GET_DEVICE3_PCI_STATE_MAX_PCI_TARGET_RETRY(__reg__) (((__reg__) & 0xe00) >> 9u) -#define SET_DEVICE3_PCI_STATE_MAX_PCI_TARGET_RETRY(__val__) (((__val__) << 9u) & 0xe00u) -#define DEVICE3_PCI_STATE_CONFIG_RETRY_SHIFT 15u -#define DEVICE3_PCI_STATE_CONFIG_RETRY_MASK 0x8000u -#define GET_DEVICE3_PCI_STATE_CONFIG_RETRY(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE3_PCI_STATE_CONFIG_RETRY(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE3_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_SHIFT 16u -#define DEVICE3_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE_MASK 0x10000u -#define GET_DEVICE3_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE3_PCI_STATE_APE_CONTROL_REGISTER_WRITE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE3_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_SHIFT 17u -#define DEVICE3_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE_MASK 0x20000u -#define GET_DEVICE3_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__reg__) (((__reg__) & 0x20000) >> 17u) -#define SET_DEVICE3_PCI_STATE_APE_SHARED_MEMORY_WRITE_ENABLE(__val__) (((__val__) << 17u) & 0x20000u) -#define DEVICE3_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_SHIFT 18u -#define DEVICE3_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE_MASK 0x40000u -#define GET_DEVICE3_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) -#define SET_DEVICE3_PCI_STATE_APE_PROGRAM_SPACE_WRITE_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) -#define DEVICE3_PCI_STATE_GENERATE_RESET_PLUS_SHIFT 19u -#define DEVICE3_PCI_STATE_GENERATE_RESET_PLUS_MASK 0x80000u -#define GET_DEVICE3_PCI_STATE_GENERATE_RESET_PLUS(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE3_PCI_STATE_GENERATE_RESET_PLUS(__val__) (((__val__) << 19u) & 0x80000u) - #define REG_DEVICE3_REGISTER_BASE ((volatile APE_DEVICE3_H_uint32_t*)0xa0070078) /* Local controller memory address of a register than can be written or read by writing to the register data register. */ #define REG_DEVICE3_MEMORY_BASE ((volatile APE_DEVICE3_H_uint32_t*)0xa007007c) /* Local controller memory address of the NIC memory region that can be accessed via Memory Window data register. */ #define REG_DEVICE3_REGISTER_DATA ((volatile APE_DEVICE3_H_uint32_t*)0xa0070080) /* Register Data at the location pointed by the Register Base Register. */ #define REG_DEVICE3_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX ((volatile APE_DEVICE3_H_uint32_t*)0xa0070088) /* UNDI Receive Return Ring Consumer Index Mailbox */ #define REG_DEVICE3_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa007008c) /* UNDI Receive Return Ring Consumer Index Mailbox */ #define REG_DEVICE3_LINK_STATUS_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa00700bc) /* PCIe standard register. */ -#define DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_SHIFT 16u -#define DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_MASK 0xf0000u -#define GET_DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__reg__) (((__reg__) & 0xf0000) >> 16u) -#define SET_DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED(__val__) (((__val__) << 16u) & 0xf0000u) -#define DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_1_0 0x1u -#define DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_SPEED_PCIE_2_0 0x2u - -#define DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20u -#define DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x3f00000u -#define GET_DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__reg__) (((__reg__) & 0x3f00000) >> 20u) -#define SET_DEVICE3_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH(__val__) (((__val__) << 20u) & 0x3f00000u) - #define REG_DEVICE3_APE_MEMORY_BASE ((volatile APE_DEVICE3_H_uint32_t*)0xa00700f8) /* APE Memory address to read/write using the APE Memory Data register.. */ #define REG_DEVICE3_APE_MEMORY_DATA ((volatile APE_DEVICE3_H_uint32_t*)0xa00700fc) /* APE Memory value at the location pointed by the Memory Base Register. */ #define REG_DEVICE3_EMAC_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0070400) /* */ -#define DEVICE3_EMAC_MODE_GLOBAL_RESET_SHIFT 0u -#define DEVICE3_EMAC_MODE_GLOBAL_RESET_MASK 0x1u -#define GET_DEVICE3_EMAC_MODE_GLOBAL_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE3_EMAC_MODE_GLOBAL_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE3_EMAC_MODE_HALF_DUPLEX_SHIFT 1u -#define DEVICE3_EMAC_MODE_HALF_DUPLEX_MASK 0x2u -#define GET_DEVICE3_EMAC_MODE_HALF_DUPLEX(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_EMAC_MODE_HALF_DUPLEX(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_EMAC_MODE_PORT_MODE_SHIFT 2u -#define DEVICE3_EMAC_MODE_PORT_MODE_MASK 0xcu -#define GET_DEVICE3_EMAC_MODE_PORT_MODE(__reg__) (((__reg__) & 0xc) >> 2u) -#define SET_DEVICE3_EMAC_MODE_PORT_MODE(__val__) (((__val__) << 2u) & 0xcu) -#define DEVICE3_EMAC_MODE_PORT_MODE_NONE 0x0u -#define DEVICE3_EMAC_MODE_PORT_MODE_10_DIV_100 0x1u -#define DEVICE3_EMAC_MODE_PORT_MODE_1000 0x2u -#define DEVICE3_EMAC_MODE_PORT_MODE_TBI 0x3u - -#define DEVICE3_EMAC_MODE_LOOPBACK_MODE_SHIFT 4u -#define DEVICE3_EMAC_MODE_LOOPBACK_MODE_MASK 0x10u -#define GET_DEVICE3_EMAC_MODE_LOOPBACK_MODE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE3_EMAC_MODE_LOOPBACK_MODE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE3_EMAC_MODE_TAGGED_MAC_CONTROL_SHIFT 7u -#define DEVICE3_EMAC_MODE_TAGGED_MAC_CONTROL_MASK 0x80u -#define GET_DEVICE3_EMAC_MODE_TAGGED_MAC_CONTROL(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE3_EMAC_MODE_TAGGED_MAC_CONTROL(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE3_EMAC_MODE_ENABLE_TX_BURSTING_SHIFT 8u -#define DEVICE3_EMAC_MODE_ENABLE_TX_BURSTING_MASK 0x100u -#define GET_DEVICE3_EMAC_MODE_ENABLE_TX_BURSTING(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE3_EMAC_MODE_ENABLE_TX_BURSTING(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE3_EMAC_MODE_MAX_DEFER_SHIFT 9u -#define DEVICE3_EMAC_MODE_MAX_DEFER_MASK 0x200u -#define GET_DEVICE3_EMAC_MODE_MAX_DEFER(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE3_EMAC_MODE_MAX_DEFER(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE3_EMAC_MODE_ENABLE_RX_STATISTICS_SHIFT 11u -#define DEVICE3_EMAC_MODE_ENABLE_RX_STATISTICS_MASK 0x800u -#define GET_DEVICE3_EMAC_MODE_ENABLE_RX_STATISTICS(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE3_EMAC_MODE_ENABLE_RX_STATISTICS(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE3_EMAC_MODE_CLEAR_RX_STATISTICS_SHIFT 12u -#define DEVICE3_EMAC_MODE_CLEAR_RX_STATISTICS_MASK 0x1000u -#define GET_DEVICE3_EMAC_MODE_CLEAR_RX_STATISTICS(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_DEVICE3_EMAC_MODE_CLEAR_RX_STATISTICS(__val__) (((__val__) << 12u) & 0x1000u) -#define DEVICE3_EMAC_MODE_FLUSH_RX_STATISTICS_SHIFT 13u -#define DEVICE3_EMAC_MODE_FLUSH_RX_STATISTICS_MASK 0x2000u -#define GET_DEVICE3_EMAC_MODE_FLUSH_RX_STATISTICS(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE3_EMAC_MODE_FLUSH_RX_STATISTICS(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE3_EMAC_MODE_ENABLE_TX_STATISTICS_SHIFT 14u -#define DEVICE3_EMAC_MODE_ENABLE_TX_STATISTICS_MASK 0x4000u -#define GET_DEVICE3_EMAC_MODE_ENABLE_TX_STATISTICS(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE3_EMAC_MODE_ENABLE_TX_STATISTICS(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE3_EMAC_MODE_CLEAR_TX_STATISTICS_SHIFT 15u -#define DEVICE3_EMAC_MODE_CLEAR_TX_STATISTICS_MASK 0x8000u -#define GET_DEVICE3_EMAC_MODE_CLEAR_TX_STATISTICS(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE3_EMAC_MODE_CLEAR_TX_STATISTICS(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE3_EMAC_MODE_FLUSH_TX_STATISTICS_SHIFT 16u -#define DEVICE3_EMAC_MODE_FLUSH_TX_STATISTICS_MASK 0x10000u -#define GET_DEVICE3_EMAC_MODE_FLUSH_TX_STATISTICS(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE3_EMAC_MODE_FLUSH_TX_STATISTICS(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE3_EMAC_MODE_SEND_CONFIG_COMMAND_SHIFT 17u -#define DEVICE3_EMAC_MODE_SEND_CONFIG_COMMAND_MASK 0x20000u -#define GET_DEVICE3_EMAC_MODE_SEND_CONFIG_COMMAND(__reg__) (((__reg__) & 0x20000) >> 17u) -#define SET_DEVICE3_EMAC_MODE_SEND_CONFIG_COMMAND(__val__) (((__val__) << 17u) & 0x20000u) -#define DEVICE3_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_SHIFT 18u -#define DEVICE3_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE_MASK 0x40000u -#define GET_DEVICE3_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) -#define SET_DEVICE3_EMAC_MODE_MAGIC_PACKET_DETECTION_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) -#define DEVICE3_EMAC_MODE_ACPI_POWER_ON_ENABLE_SHIFT 19u -#define DEVICE3_EMAC_MODE_ACPI_POWER_ON_ENABLE_MASK 0x80000u -#define GET_DEVICE3_EMAC_MODE_ACPI_POWER_ON_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE3_EMAC_MODE_ACPI_POWER_ON_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) -#define DEVICE3_EMAC_MODE_ENABLE_TCE_SHIFT 21u -#define DEVICE3_EMAC_MODE_ENABLE_TCE_MASK 0x200000u -#define GET_DEVICE3_EMAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x200000) >> 21u) -#define SET_DEVICE3_EMAC_MODE_ENABLE_TCE(__val__) (((__val__) << 21u) & 0x200000u) -#define DEVICE3_EMAC_MODE_ENABLE_RDE_SHIFT 22u -#define DEVICE3_EMAC_MODE_ENABLE_RDE_MASK 0x400000u -#define GET_DEVICE3_EMAC_MODE_ENABLE_RDE(__reg__) (((__reg__) & 0x400000) >> 22u) -#define SET_DEVICE3_EMAC_MODE_ENABLE_RDE(__val__) (((__val__) << 22u) & 0x400000u) -#define DEVICE3_EMAC_MODE_ENABLE_FHDE_SHIFT 23u -#define DEVICE3_EMAC_MODE_ENABLE_FHDE_MASK 0x800000u -#define GET_DEVICE3_EMAC_MODE_ENABLE_FHDE(__reg__) (((__reg__) & 0x800000) >> 23u) -#define SET_DEVICE3_EMAC_MODE_ENABLE_FHDE(__val__) (((__val__) << 23u) & 0x800000u) -#define DEVICE3_EMAC_MODE_KEEP_FRAME_IN_WOL_SHIFT 24u -#define DEVICE3_EMAC_MODE_KEEP_FRAME_IN_WOL_MASK 0x1000000u -#define GET_DEVICE3_EMAC_MODE_KEEP_FRAME_IN_WOL(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_DEVICE3_EMAC_MODE_KEEP_FRAME_IN_WOL(__val__) (((__val__) << 24u) & 0x1000000u) -#define DEVICE3_EMAC_MODE_HALT_INTERESTING_PACKET_PME_SHIFT 25u -#define DEVICE3_EMAC_MODE_HALT_INTERESTING_PACKET_PME_MASK 0x2000000u -#define GET_DEVICE3_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_DEVICE3_EMAC_MODE_HALT_INTERESTING_PACKET_PME(__val__) (((__val__) << 25u) & 0x2000000u) -#define DEVICE3_EMAC_MODE_FREE_RUNNING_ACPI_SHIFT 26u -#define DEVICE3_EMAC_MODE_FREE_RUNNING_ACPI_MASK 0x4000000u -#define GET_DEVICE3_EMAC_MODE_FREE_RUNNING_ACPI(__reg__) (((__reg__) & 0x4000000) >> 26u) -#define SET_DEVICE3_EMAC_MODE_FREE_RUNNING_ACPI(__val__) (((__val__) << 26u) & 0x4000000u) -#define DEVICE3_EMAC_MODE_ENABLE_APE_RX_PATH_SHIFT 27u -#define DEVICE3_EMAC_MODE_ENABLE_APE_RX_PATH_MASK 0x8000000u -#define GET_DEVICE3_EMAC_MODE_ENABLE_APE_RX_PATH(__reg__) (((__reg__) & 0x8000000) >> 27u) -#define SET_DEVICE3_EMAC_MODE_ENABLE_APE_RX_PATH(__val__) (((__val__) << 27u) & 0x8000000u) -#define DEVICE3_EMAC_MODE_ENABLE_APE_TX_PATH_SHIFT 28u -#define DEVICE3_EMAC_MODE_ENABLE_APE_TX_PATH_MASK 0x10000000u -#define GET_DEVICE3_EMAC_MODE_ENABLE_APE_TX_PATH(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_DEVICE3_EMAC_MODE_ENABLE_APE_TX_PATH(__val__) (((__val__) << 28u) & 0x10000000u) -#define DEVICE3_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_SHIFT 29u -#define DEVICE3_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL_MASK 0x20000000u -#define GET_DEVICE3_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_DEVICE3_EMAC_MODE_MAC_LOOPBACK_MODE_CONTROL(__val__) (((__val__) << 29u) & 0x20000000u) - #define REG_DEVICE3_LED_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa007040c) /* */ -#define DEVICE3_LED_CONTROL_OVERRIDE_LINK_SHIFT 0u -#define DEVICE3_LED_CONTROL_OVERRIDE_LINK_MASK 0x1u -#define GET_DEVICE3_LED_CONTROL_OVERRIDE_LINK(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE3_LED_CONTROL_OVERRIDE_LINK(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE3_LED_CONTROL_LED_1000_SHIFT 1u -#define DEVICE3_LED_CONTROL_LED_1000_MASK 0x2u -#define GET_DEVICE3_LED_CONTROL_LED_1000(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_LED_CONTROL_LED_1000(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_LED_CONTROL_LED_100_SHIFT 2u -#define DEVICE3_LED_CONTROL_LED_100_MASK 0x4u -#define GET_DEVICE3_LED_CONTROL_LED_100(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE3_LED_CONTROL_LED_100(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE3_LED_CONTROL_LED_10_SHIFT 3u -#define DEVICE3_LED_CONTROL_LED_10_MASK 0x8u -#define GET_DEVICE3_LED_CONTROL_LED_10(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE3_LED_CONTROL_LED_10(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE3_LED_CONTROL_OVERRIDE_TRAFFIC_SHIFT 4u -#define DEVICE3_LED_CONTROL_OVERRIDE_TRAFFIC_MASK 0x10u -#define GET_DEVICE3_LED_CONTROL_OVERRIDE_TRAFFIC(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE3_LED_CONTROL_OVERRIDE_TRAFFIC(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE3_LED_CONTROL_LED_TRAFFIC_BLINK_SHIFT 5u -#define DEVICE3_LED_CONTROL_LED_TRAFFIC_BLINK_MASK 0x20u -#define GET_DEVICE3_LED_CONTROL_LED_TRAFFIC_BLINK(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE3_LED_CONTROL_LED_TRAFFIC_BLINK(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE3_LED_CONTROL_LED_TRAFFIC_SHIFT 6u -#define DEVICE3_LED_CONTROL_LED_TRAFFIC_MASK 0x40u -#define GET_DEVICE3_LED_CONTROL_LED_TRAFFIC(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE3_LED_CONTROL_LED_TRAFFIC(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE3_LED_CONTROL_LED_STATUS_1000_SHIFT 7u -#define DEVICE3_LED_CONTROL_LED_STATUS_1000_MASK 0x80u -#define GET_DEVICE3_LED_CONTROL_LED_STATUS_1000(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE3_LED_CONTROL_LED_STATUS_1000(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE3_LED_CONTROL_LED_STATUS_100_SHIFT 8u -#define DEVICE3_LED_CONTROL_LED_STATUS_100_MASK 0x100u -#define GET_DEVICE3_LED_CONTROL_LED_STATUS_100(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE3_LED_CONTROL_LED_STATUS_100(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE3_LED_CONTROL_LED_STATUS_10_SHIFT 9u -#define DEVICE3_LED_CONTROL_LED_STATUS_10_MASK 0x200u -#define GET_DEVICE3_LED_CONTROL_LED_STATUS_10(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE3_LED_CONTROL_LED_STATUS_10(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE3_LED_CONTROL_LED_STATUS_TRAFFIC_SHIFT 10u -#define DEVICE3_LED_CONTROL_LED_STATUS_TRAFFIC_MASK 0x400u -#define GET_DEVICE3_LED_CONTROL_LED_STATUS_TRAFFIC(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE3_LED_CONTROL_LED_STATUS_TRAFFIC(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE3_LED_CONTROL_LED_MODE_SHIFT 11u -#define DEVICE3_LED_CONTROL_LED_MODE_MASK 0x1800u -#define GET_DEVICE3_LED_CONTROL_LED_MODE(__reg__) (((__reg__) & 0x1800) >> 11u) -#define SET_DEVICE3_LED_CONTROL_LED_MODE(__val__) (((__val__) << 11u) & 0x1800u) -#define DEVICE3_LED_CONTROL_LED_MODE_MAC 0x0u -#define DEVICE3_LED_CONTROL_LED_MODE_PHY_MODE_1 0x1u -#define DEVICE3_LED_CONTROL_LED_MODE_PHY_MODE_2 0x2u -#define DEVICE3_LED_CONTROL_LED_MODE_PHY_MODE_1_ 0x3u - -#define DEVICE3_LED_CONTROL_MAC_MODE_SHIFT 13u -#define DEVICE3_LED_CONTROL_MAC_MODE_MASK 0x2000u -#define GET_DEVICE3_LED_CONTROL_MAC_MODE(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE3_LED_CONTROL_MAC_MODE(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE3_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_SHIFT 14u -#define DEVICE3_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE_MASK 0x4000u -#define GET_DEVICE3_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE3_LED_CONTROL_SHARED_TRAFFIC_DIV_LINK_LED_MODE(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE3_LED_CONTROL_BLINK_PERIOD_SHIFT 19u -#define DEVICE3_LED_CONTROL_BLINK_PERIOD_MASK 0x7ff80000u -#define GET_DEVICE3_LED_CONTROL_BLINK_PERIOD(__reg__) (((__reg__) & 0x7ff80000) >> 19u) -#define SET_DEVICE3_LED_CONTROL_BLINK_PERIOD(__val__) (((__val__) << 19u) & 0x7ff80000u) -#define DEVICE3_LED_CONTROL_OVERRIDE_BLINK_RATE_SHIFT 31u -#define DEVICE3_LED_CONTROL_OVERRIDE_BLINK_RATE_MASK 0x80000000u -#define GET_DEVICE3_LED_CONTROL_OVERRIDE_BLINK_RATE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE3_LED_CONTROL_OVERRIDE_BLINK_RATE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE3_EMAC_MAC_ADDRESSES_0_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070410) /* Upper 2-bytes of this node's MAC address. */ #define REG_DEVICE3_EMAC_MAC_ADDRESSES_0_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa0070414) /* Lower 4-byte of this node's MAC address. */ #define REG_DEVICE3_EMAC_MAC_ADDRESSES_1_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070418) /* Upper 2-bytes of this node's MAC address. */ @@ -421,671 +105,40 @@ typedef uint32_t APE_DEVICE3_H_uint32_t; #define REG_DEVICE3_WOL_PATTERN_POINTER ((volatile APE_DEVICE3_H_uint32_t*)0xa0070430) /* Specifies the offset into the 6KB BD memory for frame comparison. (Bits 3:0 are ignored to align the memory address to a natural 128-bit boundary). */ #define REG_DEVICE3_WOL_PATTERN_CFG ((volatile APE_DEVICE3_H_uint32_t*)0xa0070434) /* */ #define REG_DEVICE3_MTU_SIZE ((volatile APE_DEVICE3_H_uint32_t*)0xa007043c) /* 2-byte field which is the largest size frame that will be accepted without being marked as oversize. */ -#define DEVICE3_MTU_SIZE_MTU_SHIFT 0u -#define DEVICE3_MTU_SIZE_MTU_MASK 0xffffu -#define GET_DEVICE3_MTU_SIZE_MTU(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE3_MTU_SIZE_MTU(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE3_MII_COMMUNICATION ((volatile APE_DEVICE3_H_uint32_t*)0xa007044c) /* */ -#define DEVICE3_MII_COMMUNICATION_TRANSACTION_DATA_SHIFT 0u -#define DEVICE3_MII_COMMUNICATION_TRANSACTION_DATA_MASK 0xffffu -#define GET_DEVICE3_MII_COMMUNICATION_TRANSACTION_DATA(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE3_MII_COMMUNICATION_TRANSACTION_DATA(__val__) (((__val__) << 0u) & 0xffffu) -#define DEVICE3_MII_COMMUNICATION_REGISTER_ADDRESS_SHIFT 16u -#define DEVICE3_MII_COMMUNICATION_REGISTER_ADDRESS_MASK 0x1f0000u -#define GET_DEVICE3_MII_COMMUNICATION_REGISTER_ADDRESS(__reg__) (((__reg__) & 0x1f0000) >> 16u) -#define SET_DEVICE3_MII_COMMUNICATION_REGISTER_ADDRESS(__val__) (((__val__) << 16u) & 0x1f0000u) -#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_SHIFT 21u -#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_MASK 0x3e00000u -#define GET_DEVICE3_MII_COMMUNICATION_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e00000) >> 21u) -#define SET_DEVICE3_MII_COMMUNICATION_PHY_ADDRESS(__val__) (((__val__) << 21u) & 0x3e00000u) -#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_PHY_0 0x1u -#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_PHY_1 0x2u -#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_PHY_2 0x3u -#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_PHY_3 0x4u -#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_SGMII_0 0x8u -#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_SGMII_1 0x9u -#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_SGMII_2 0xau -#define DEVICE3_MII_COMMUNICATION_PHY_ADDRESS_SGMII_3 0xbu - -#define DEVICE3_MII_COMMUNICATION_COMMAND_SHIFT 26u -#define DEVICE3_MII_COMMUNICATION_COMMAND_MASK 0xc000000u -#define GET_DEVICE3_MII_COMMUNICATION_COMMAND(__reg__) (((__reg__) & 0xc000000) >> 26u) -#define SET_DEVICE3_MII_COMMUNICATION_COMMAND(__val__) (((__val__) << 26u) & 0xc000000u) -#define DEVICE3_MII_COMMUNICATION_COMMAND_WRITE 0x1u -#define DEVICE3_MII_COMMUNICATION_COMMAND_READ 0x2u - -#define DEVICE3_MII_COMMUNICATION_READ_FAILED_SHIFT 28u -#define DEVICE3_MII_COMMUNICATION_READ_FAILED_MASK 0x10000000u -#define GET_DEVICE3_MII_COMMUNICATION_READ_FAILED(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_DEVICE3_MII_COMMUNICATION_READ_FAILED(__val__) (((__val__) << 28u) & 0x10000000u) -#define DEVICE3_MII_COMMUNICATION_START_DIV_BUSY_SHIFT 29u -#define DEVICE3_MII_COMMUNICATION_START_DIV_BUSY_MASK 0x20000000u -#define GET_DEVICE3_MII_COMMUNICATION_START_DIV_BUSY(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_DEVICE3_MII_COMMUNICATION_START_DIV_BUSY(__val__) (((__val__) << 29u) & 0x20000000u) - #define REG_DEVICE3_MII_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0070454) /* */ -#define DEVICE3_MII_MODE_PHY_ADDRESS_SHIFT 5u -#define DEVICE3_MII_MODE_PHY_ADDRESS_MASK 0x3e0u -#define GET_DEVICE3_MII_MODE_PHY_ADDRESS(__reg__) (((__reg__) & 0x3e0) >> 5u) -#define SET_DEVICE3_MII_MODE_PHY_ADDRESS(__val__) (((__val__) << 5u) & 0x3e0u) -#define DEVICE3_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_SHIFT 15u -#define DEVICE3_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED_MASK 0x8000u -#define GET_DEVICE3_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE3_MII_MODE_CONSTANT_MDIO_DIV_MDC_CLOCK_SPEED(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE3_MII_MODE_MII_CLOCK_COUNT_SHIFT 16u -#define DEVICE3_MII_MODE_MII_CLOCK_COUNT_MASK 0x1f0000u -#define GET_DEVICE3_MII_MODE_MII_CLOCK_COUNT(__reg__) (((__reg__) & 0x1f0000) >> 16u) -#define SET_DEVICE3_MII_MODE_MII_CLOCK_COUNT(__val__) (((__val__) << 16u) & 0x1f0000u) - #define REG_DEVICE3_TRANSMIT_MAC_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa007045c) /* */ -#define DEVICE3_TRANSMIT_MAC_MODE_RESET_SHIFT 0u -#define DEVICE3_TRANSMIT_MAC_MODE_RESET_MASK 0x1u -#define GET_DEVICE3_TRANSMIT_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE3_TRANSMIT_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TCE_SHIFT 1u -#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TCE_MASK 0x2u -#define GET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TCE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TCE(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_SHIFT 4u -#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL_MASK 0x10u -#define GET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_FLOW_CONTROL(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_SHIFT 5u -#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF_MASK 0x20u -#define GET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_BIG_BACKOFF(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_SHIFT 6u -#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE_MASK 0x40u -#define GET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_LONG_PAUSE(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE3_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_SHIFT 7u -#define DEVICE3_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE_MASK 0x80u -#define GET_DEVICE3_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE3_TRANSMIT_MAC_MODE_LINK_AWARE_ENABLE(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE3_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_SHIFT 8u -#define DEVICE3_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE_MASK 0x100u -#define GET_DEVICE3_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE3_TRANSMIT_MAC_MODE_TXMBUF_CORRUPTION_LOCKUP_FIX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_SHIFT 9u -#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD_MASK 0x200u -#define GET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_ESP_OFFLOAD(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_SHIFT 10u -#define DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD_MASK 0x400u -#define GET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE3_TRANSMIT_MAC_MODE_ENABLE_TX_AH_OFFLOAD(__val__) (((__val__) << 10u) & 0x400u) - #define REG_DEVICE3_RECEIVE_MAC_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0070468) /* */ -#define DEVICE3_RECEIVE_MAC_MODE_RESET_SHIFT 0u -#define DEVICE3_RECEIVE_MAC_MODE_RESET_MASK 0x1u -#define GET_DEVICE3_RECEIVE_MAC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE3_RECEIVE_MAC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE3_RECEIVE_MAC_MODE_ENABLE_SHIFT 1u -#define DEVICE3_RECEIVE_MAC_MODE_ENABLE_MASK 0x2u -#define GET_DEVICE3_RECEIVE_MAC_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_RECEIVE_MAC_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_SHIFT 8u -#define DEVICE3_RECEIVE_MAC_MODE_PROMISCUOUS_MODE_MASK 0x100u -#define GET_DEVICE3_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE3_RECEIVE_MAC_MODE_PROMISCUOUS_MODE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE3_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_SHIFT 25u -#define DEVICE3_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE_MASK 0x2000000u -#define GET_DEVICE3_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_DEVICE3_RECEIVE_MAC_MODE_APE_PROMISCUOUS_MODE(__val__) (((__val__) << 25u) & 0x2000000u) - #define REG_DEVICE3_PERFECT_MATCH1_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070540) /* */ -#define DEVICE3_PERFECT_MATCH1_HIGH_HIGH_SHIFT 0u -#define DEVICE3_PERFECT_MATCH1_HIGH_HIGH_MASK 0xffffu -#define GET_DEVICE3_PERFECT_MATCH1_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE3_PERFECT_MATCH1_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE3_PERFECT_MATCH1_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa0070544) /* */ -#define DEVICE3_PERFECT_MATCH1_LOW_LOW_SHIFT 0u -#define DEVICE3_PERFECT_MATCH1_LOW_LOW_MASK 0xffffffffu -#define GET_DEVICE3_PERFECT_MATCH1_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE3_PERFECT_MATCH1_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) - #define REG_DEVICE3_PERFECT_MATCH2_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070548) /* */ -#define DEVICE3_PERFECT_MATCH2_HIGH_HIGH_SHIFT 0u -#define DEVICE3_PERFECT_MATCH2_HIGH_HIGH_MASK 0xffffu -#define GET_DEVICE3_PERFECT_MATCH2_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE3_PERFECT_MATCH2_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE3_PERFECT_MATCH2_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa007054c) /* */ -#define DEVICE3_PERFECT_MATCH2_LOW_LOW_SHIFT 0u -#define DEVICE3_PERFECT_MATCH2_LOW_LOW_MASK 0xffffffffu -#define GET_DEVICE3_PERFECT_MATCH2_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE3_PERFECT_MATCH2_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) - #define REG_DEVICE3_PERFECT_MATCH3_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070550) /* */ -#define DEVICE3_PERFECT_MATCH3_HIGH_HIGH_SHIFT 0u -#define DEVICE3_PERFECT_MATCH3_HIGH_HIGH_MASK 0xffffu -#define GET_DEVICE3_PERFECT_MATCH3_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE3_PERFECT_MATCH3_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE3_PERFECT_MATCH3_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa0070554) /* */ -#define DEVICE3_PERFECT_MATCH3_LOW_LOW_SHIFT 0u -#define DEVICE3_PERFECT_MATCH3_LOW_LOW_MASK 0xffffffffu -#define GET_DEVICE3_PERFECT_MATCH3_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE3_PERFECT_MATCH3_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) - #define REG_DEVICE3_PERFECT_MATCH4_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0070558) /* */ -#define DEVICE3_PERFECT_MATCH4_HIGH_HIGH_SHIFT 0u -#define DEVICE3_PERFECT_MATCH4_HIGH_HIGH_MASK 0xffffu -#define GET_DEVICE3_PERFECT_MATCH4_HIGH_HIGH(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE3_PERFECT_MATCH4_HIGH_HIGH(__val__) (((__val__) << 0u) & 0xffffu) - #define REG_DEVICE3_PERFECT_MATCH4_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa007055c) /* */ -#define DEVICE3_PERFECT_MATCH4_LOW_LOW_SHIFT 0u -#define DEVICE3_PERFECT_MATCH4_LOW_LOW_MASK 0xffffffffu -#define GET_DEVICE3_PERFECT_MATCH4_LOW_LOW(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_DEVICE3_PERFECT_MATCH4_LOW_LOW(__val__) (((__val__) << 0u) & 0xffffffffu) - #define REG_DEVICE3_SGMII_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa00705b4) /* This register reflects various status of the respective SGMII port when enabled. */ -#define DEVICE3_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 0u -#define DEVICE3_SGMII_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x1u -#define GET_DEVICE3_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE3_SGMII_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE3_SGMII_STATUS_LINK_STATUS_SHIFT 1u -#define DEVICE3_SGMII_STATUS_LINK_STATUS_MASK 0x2u -#define GET_DEVICE3_SGMII_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_SGMII_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_SGMII_STATUS_DUPLEX_STATUS_SHIFT 2u -#define DEVICE3_SGMII_STATUS_DUPLEX_STATUS_MASK 0x4u -#define GET_DEVICE3_SGMII_STATUS_DUPLEX_STATUS(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE3_SGMII_STATUS_DUPLEX_STATUS(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE3_SGMII_STATUS_SPEED_1000_SHIFT 3u -#define DEVICE3_SGMII_STATUS_SPEED_1000_MASK 0x8u -#define GET_DEVICE3_SGMII_STATUS_SPEED_1000(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE3_SGMII_STATUS_SPEED_1000(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE3_SGMII_STATUS_SPEED_100_SHIFT 4u -#define DEVICE3_SGMII_STATUS_SPEED_100_MASK 0x10u -#define GET_DEVICE3_SGMII_STATUS_SPEED_100(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE3_SGMII_STATUS_SPEED_100(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE3_SGMII_STATUS_NEXT_PAGE_RX_SHIFT 5u -#define DEVICE3_SGMII_STATUS_NEXT_PAGE_RX_MASK 0x20u -#define GET_DEVICE3_SGMII_STATUS_NEXT_PAGE_RX(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE3_SGMII_STATUS_NEXT_PAGE_RX(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE3_SGMII_STATUS_PAUSE_RX_SHIFT 6u -#define DEVICE3_SGMII_STATUS_PAUSE_RX_MASK 0x40u -#define GET_DEVICE3_SGMII_STATUS_PAUSE_RX(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE3_SGMII_STATUS_PAUSE_RX(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE3_SGMII_STATUS_PAUSE_TX_SHIFT 7u -#define DEVICE3_SGMII_STATUS_PAUSE_TX_MASK 0x80u -#define GET_DEVICE3_SGMII_STATUS_PAUSE_TX(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE3_SGMII_STATUS_PAUSE_TX(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE3_SGMII_STATUS_MEDIA_SELECTION_MODE_SHIFT 8u -#define DEVICE3_SGMII_STATUS_MEDIA_SELECTION_MODE_MASK 0x100u -#define GET_DEVICE3_SGMII_STATUS_MEDIA_SELECTION_MODE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE3_SGMII_STATUS_MEDIA_SELECTION_MODE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE3_SGMII_STATUS_MEDIA_SELECTION_MODE_COPPER 0x0u -#define DEVICE3_SGMII_STATUS_MEDIA_SELECTION_MODE_SGMII 0x1u - -#define DEVICE3_SGMII_STATUS_PCS_CRS_DETECT_SHIFT 9u -#define DEVICE3_SGMII_STATUS_PCS_CRS_DETECT_MASK 0x200u -#define GET_DEVICE3_SGMII_STATUS_PCS_CRS_DETECT(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE3_SGMII_STATUS_PCS_CRS_DETECT(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE3_SGMII_STATUS_EXTERNAL_CRS_DETECT_SHIFT 10u -#define DEVICE3_SGMII_STATUS_EXTERNAL_CRS_DETECT_MASK 0x400u -#define GET_DEVICE3_SGMII_STATUS_EXTERNAL_CRS_DETECT(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE3_SGMII_STATUS_EXTERNAL_CRS_DETECT(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE3_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_SHIFT 16u -#define DEVICE3_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY_MASK 0xffff0000u -#define GET_DEVICE3_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_DEVICE3_SGMII_STATUS_LINK_PARTNER_AUTONEGOTIATION_CAPABILITY(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_DEVICE3_CPMU_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0073600) /* */ -#define DEVICE3_CPMU_CONTROL_CPMU_SOFTWARE_RESET_SHIFT 0u -#define DEVICE3_CPMU_CONTROL_CPMU_SOFTWARE_RESET_MASK 0x1u -#define GET_DEVICE3_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE3_CPMU_CONTROL_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE3_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 1u -#define DEVICE3_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x2u -#define GET_DEVICE3_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_CPMU_CONTROL_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_CPMU_CONTROL_POWER_DOWN_SHIFT 2u -#define DEVICE3_CPMU_CONTROL_POWER_DOWN_MASK 0x4u -#define GET_DEVICE3_CPMU_CONTROL_POWER_DOWN(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE3_CPMU_CONTROL_POWER_DOWN(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE3_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_SHIFT 4u -#define DEVICE3_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE_MASK 0x10u -#define GET_DEVICE3_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE3_CPMU_CONTROL_APE_SLEEP_MODE_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE3_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_SHIFT 5u -#define DEVICE3_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE_MASK 0x20u -#define GET_DEVICE3_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE3_CPMU_CONTROL_APE_DEEP_SLEEP_MODE_ENABLE(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE3_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_SHIFT 9u -#define DEVICE3_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE_MASK 0x200u -#define GET_DEVICE3_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE3_CPMU_CONTROL_LINK_IDLE_POWER_MODE_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE3_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_SHIFT 10u -#define DEVICE3_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE_MASK 0x400u -#define GET_DEVICE3_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE3_CPMU_CONTROL_LINK_AWARE_POWER_MODE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE3_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_SHIFT 14u -#define DEVICE3_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE_MASK 0x4000u -#define GET_DEVICE3_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE3_CPMU_CONTROL_LINK_SPEED_POWER_MODE_ENABLE(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE3_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_SHIFT 16u -#define DEVICE3_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE_MASK 0x10000u -#define GET_DEVICE3_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE3_CPMU_CONTROL_GPHY_10MB_RECEIVE_ONLY_MODE_ENABLE(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE3_CPMU_CONTROL_LEGACY_TIMER_ENABLE_SHIFT 18u -#define DEVICE3_CPMU_CONTROL_LEGACY_TIMER_ENABLE_MASK 0x40000u -#define GET_DEVICE3_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__reg__) (((__reg__) & 0x40000) >> 18u) -#define SET_DEVICE3_CPMU_CONTROL_LEGACY_TIMER_ENABLE(__val__) (((__val__) << 18u) & 0x40000u) -#define DEVICE3_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_SHIFT 19u -#define DEVICE3_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN_MASK 0x80000u -#define GET_DEVICE3_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE3_CPMU_CONTROL_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 19u) & 0x80000u) -#define DEVICE3_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_SHIFT 28u -#define DEVICE3_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON_MASK 0x10000000u -#define GET_DEVICE3_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_DEVICE3_CPMU_CONTROL_SOFTWARE_CONTROLLED_GPHY_FORCE_DLL_ON(__val__) (((__val__) << 28u) & 0x10000000u) - #define REG_DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY ((volatile APE_DEVICE3_H_uint32_t*)0xa0073610) /* */ -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u -#define GET_DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) -#define SET_DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_60_0MHZ 0x1u -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_30_0MHZ 0x3u -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_15_0MHZ 0x5u -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_7_5MHZ 0x7u -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_75MHZ 0x9u -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ 0x11u -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_6_25MHZ 0x13u -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_3_125MHZ 0x15u -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_1_563MHZ 0x17u -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_781KHZ 0x19u -#define DEVICE3_LINK_AWARE_POWER_MODE_CLOCK_POLICY_MAC_CLOCK_SWITCH_12_5MHZ_DIV_1_25MHZ 0x1fu - - #define REG_DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY ((volatile APE_DEVICE3_H_uint32_t*)0xa0073624) /* */ -#define DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_SHIFT 16u -#define DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH_MASK 0x1f0000u -#define GET_DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__reg__) (((__reg__) & 0x1f0000) >> 16u) -#define SET_DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SWITCH(__val__) (((__val__) << 16u) & 0x1f0000u) -#define DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_SHIFT 31u -#define DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED_MASK 0x80000000u -#define GET_DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE3_CLOCK_SPEED_OVERRIDE_POLICY_MAC_CLOCK_SPEED_OVERRIDE_ENABLED(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE3_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa007362c) /* */ -#define DEVICE3_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_SHIFT 0u -#define DEVICE3_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE_MASK 0xfu -#define GET_DEVICE3_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__reg__) (((__reg__) & 0xf) >> 0u) -#define SET_DEVICE3_STATUS_POWER_MANAGEMENT_STATE_MACHINE_STATE(__val__) (((__val__) << 0u) & 0xfu) -#define DEVICE3_STATUS_CPMU_POWER_STATE_SHIFT 4u -#define DEVICE3_STATUS_CPMU_POWER_STATE_MASK 0x70u -#define GET_DEVICE3_STATUS_CPMU_POWER_STATE(__reg__) (((__reg__) & 0x70) >> 4u) -#define SET_DEVICE3_STATUS_CPMU_POWER_STATE(__val__) (((__val__) << 4u) & 0x70u) -#define DEVICE3_STATUS_ENERGY_DETECT_STATUS_SHIFT 7u -#define DEVICE3_STATUS_ENERGY_DETECT_STATUS_MASK 0x80u -#define GET_DEVICE3_STATUS_ENERGY_DETECT_STATUS(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE3_STATUS_ENERGY_DETECT_STATUS(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE3_STATUS_POWER_STATE_SHIFT 8u -#define DEVICE3_STATUS_POWER_STATE_MASK 0x300u -#define GET_DEVICE3_STATUS_POWER_STATE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE3_STATUS_POWER_STATE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE3_STATUS_VMAIN_POWER_STATUS_SHIFT 13u -#define DEVICE3_STATUS_VMAIN_POWER_STATUS_MASK 0x2000u -#define GET_DEVICE3_STATUS_VMAIN_POWER_STATUS(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE3_STATUS_VMAIN_POWER_STATUS(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_SHIFT 14u -#define DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0_MASK 0x4000u -#define GET_DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_SHIFT 15u -#define DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0_MASK 0x8000u -#define GET_DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_0(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE3_STATUS_NCSI_DLL_LOCK_STATUS_SHIFT 16u -#define DEVICE3_STATUS_NCSI_DLL_LOCK_STATUS_MASK 0x10000u -#define GET_DEVICE3_STATUS_NCSI_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE3_STATUS_NCSI_DLL_LOCK_STATUS(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE3_STATUS_GPHY_DLL_LOCK_STATUS_SHIFT 17u -#define DEVICE3_STATUS_GPHY_DLL_LOCK_STATUS_MASK 0x20000u -#define GET_DEVICE3_STATUS_GPHY_DLL_LOCK_STATUS(__reg__) (((__reg__) & 0x20000) >> 17u) -#define SET_DEVICE3_STATUS_GPHY_DLL_LOCK_STATUS(__val__) (((__val__) << 17u) & 0x20000u) -#define DEVICE3_STATUS_LINK_IDLE_STATUS_SHIFT 18u -#define DEVICE3_STATUS_LINK_IDLE_STATUS_MASK 0x40000u -#define GET_DEVICE3_STATUS_LINK_IDLE_STATUS(__reg__) (((__reg__) & 0x40000) >> 18u) -#define SET_DEVICE3_STATUS_LINK_IDLE_STATUS(__val__) (((__val__) << 18u) & 0x40000u) -#define DEVICE3_STATUS_ETHERNET_LINK_STATUS_SHIFT 19u -#define DEVICE3_STATUS_ETHERNET_LINK_STATUS_MASK 0x180000u -#define GET_DEVICE3_STATUS_ETHERNET_LINK_STATUS(__reg__) (((__reg__) & 0x180000) >> 19u) -#define SET_DEVICE3_STATUS_ETHERNET_LINK_STATUS(__val__) (((__val__) << 19u) & 0x180000u) -#define DEVICE3_STATUS_ETHERNET_LINK_STATUS_1000_MB 0x0u -#define DEVICE3_STATUS_ETHERNET_LINK_STATUS_100_MB 0x1u -#define DEVICE3_STATUS_ETHERNET_LINK_STATUS_10_MB 0x2u -#define DEVICE3_STATUS_ETHERNET_LINK_STATUS_NO_LINK 0x3u - -#define DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_SHIFT 21u -#define DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1_MASK 0x200000u -#define GET_DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x200000) >> 21u) -#define SET_DEVICE3_STATUS_WOL_MAGIC_PACKET_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 21u) & 0x200000u) -#define DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_SHIFT 22u -#define DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1_MASK 0x400000u -#define GET_DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__reg__) (((__reg__) & 0x400000) >> 22u) -#define SET_DEVICE3_STATUS_WOL_ACPI_DETECTION_ENABLE_PORT_1(__val__) (((__val__) << 22u) & 0x400000u) -#define DEVICE3_STATUS_APE_STATUS_SHIFT 23u -#define DEVICE3_STATUS_APE_STATUS_MASK 0x1800000u -#define GET_DEVICE3_STATUS_APE_STATUS(__reg__) (((__reg__) & 0x1800000) >> 23u) -#define SET_DEVICE3_STATUS_APE_STATUS(__val__) (((__val__) << 23u) & 0x1800000u) -#define DEVICE3_STATUS_APE_STATUS_ACTIVE 0x0u -#define DEVICE3_STATUS_APE_STATUS_SLEEP 0x1u -#define DEVICE3_STATUS_APE_STATUS_DEEP_SLEEP 0x2u - -#define DEVICE3_STATUS_FUNCTION_ENABLE_SHIFT 25u -#define DEVICE3_STATUS_FUNCTION_ENABLE_MASK 0x3e000000u -#define GET_DEVICE3_STATUS_FUNCTION_ENABLE(__reg__) (((__reg__) & 0x3e000000) >> 25u) -#define SET_DEVICE3_STATUS_FUNCTION_ENABLE(__val__) (((__val__) << 25u) & 0x3e000000u) -#define DEVICE3_STATUS_FUNCTION_NUMBER_SHIFT 30u -#define DEVICE3_STATUS_FUNCTION_NUMBER_MASK 0xc0000000u -#define GET_DEVICE3_STATUS_FUNCTION_NUMBER(__reg__) (((__reg__) & 0xc0000000) >> 30u) -#define SET_DEVICE3_STATUS_FUNCTION_NUMBER(__val__) (((__val__) << 30u) & 0xc0000000u) - #define REG_DEVICE3_CLOCK_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa0073630) /* */ #define REG_DEVICE3_GPHY_CONTROL_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa0073638) /* */ -#define DEVICE3_GPHY_CONTROL_STATUS_GPHY_IDDQ_SHIFT 0u -#define DEVICE3_GPHY_CONTROL_STATUS_GPHY_IDDQ_MASK 0x1u -#define GET_DEVICE3_GPHY_CONTROL_STATUS_GPHY_IDDQ(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE3_GPHY_CONTROL_STATUS_GPHY_IDDQ(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE3_GPHY_CONTROL_STATUS_BIAS_IDDQ_SHIFT 1u -#define DEVICE3_GPHY_CONTROL_STATUS_BIAS_IDDQ_MASK 0x2u -#define GET_DEVICE3_GPHY_CONTROL_STATUS_BIAS_IDDQ(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_GPHY_CONTROL_STATUS_BIAS_IDDQ(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_SHIFT 2u -#define DEVICE3_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET_MASK 0x4u -#define GET_DEVICE3_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE3_GPHY_CONTROL_STATUS_CPMU_SOFTWARE_RESET(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE3_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_SHIFT 3u -#define DEVICE3_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET_MASK 0x8u -#define GET_DEVICE3_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE3_GPHY_CONTROL_STATUS_CPMU_REGISTER_SOFTWARE_RESET(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE3_GPHY_CONTROL_STATUS_POWER_DOWN_SHIFT 4u -#define DEVICE3_GPHY_CONTROL_STATUS_POWER_DOWN_MASK 0x10u -#define GET_DEVICE3_GPHY_CONTROL_STATUS_POWER_DOWN(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE3_GPHY_CONTROL_STATUS_POWER_DOWN(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE3_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_SHIFT 15u -#define DEVICE3_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN_MASK 0x8000u -#define GET_DEVICE3_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE3_GPHY_CONTROL_STATUS_SGMII_DIV_PCS_POWER_DOWN(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE3_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_SHIFT 25u -#define DEVICE3_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS_MASK 0x2000000u -#define GET_DEVICE3_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_DEVICE3_GPHY_CONTROL_STATUS_NCSI_PLL_LOCK_STATUS(__val__) (((__val__) << 25u) & 0x2000000u) -#define DEVICE3_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_SHIFT 26u -#define DEVICE3_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE_MASK 0x4000000u -#define GET_DEVICE3_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__reg__) (((__reg__) & 0x4000000) >> 26u) -#define SET_DEVICE3_GPHY_CONTROL_STATUS_TLP_CLOCK_SOURCE(__val__) (((__val__) << 26u) & 0x4000000u) -#define DEVICE3_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_SHIFT 27u -#define DEVICE3_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN_MASK 0x8000000u -#define GET_DEVICE3_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__reg__) (((__reg__) & 0x8000000) >> 27u) -#define SET_DEVICE3_GPHY_CONTROL_STATUS_SWITCHING_REGULATOR_POWER_DOWN(__val__) (((__val__) << 27u) & 0x8000000u) - #define REG_DEVICE3_CHIP_ID ((volatile APE_DEVICE3_H_uint32_t*)0xa0073658) /* */ #define REG_DEVICE3_MUTEX_REQUEST ((volatile APE_DEVICE3_H_uint32_t*)0xa007365c) /* Writing a 1 to any of these bits pends a Mutex lock request on behalf of a software agent. The bit is subsequently latched by hardware and shall read 1 as long as the request is pending. Writing a 0 to a bit shall have no effect. */ #define REG_DEVICE3_MUTEX_GRANT ((volatile APE_DEVICE3_H_uint32_t*)0xa0073660) /* Reading this field shall return a maximum of one set bit at any time. The set bit shall point to the lock owner. If the Mutex is not locked, then a read shall return a value 0x0000. Writing a 1 to the already set bit shall relinquish the lock and the set bit shall be cleared. Writing a 1 to an unset bit shall cancel the corresponding pending request if there was one, and the pairing bit in the Mutex_Request_Reg shall be cleared. */ #define REG_DEVICE3_GPHY_STRAP ((volatile APE_DEVICE3_H_uint32_t*)0xa0073664) /* */ -#define DEVICE3_GPHY_STRAP_TXMBUF_ECC_ENABLE_SHIFT 2u -#define DEVICE3_GPHY_STRAP_TXMBUF_ECC_ENABLE_MASK 0x4u -#define GET_DEVICE3_GPHY_STRAP_TXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE3_GPHY_STRAP_TXMBUF_ECC_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE3_GPHY_STRAP_RXMBUF_ECC_ENABLE_SHIFT 3u -#define DEVICE3_GPHY_STRAP_RXMBUF_ECC_ENABLE_MASK 0x8u -#define GET_DEVICE3_GPHY_STRAP_RXMBUF_ECC_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE3_GPHY_STRAP_RXMBUF_ECC_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE3_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_SHIFT 4u -#define DEVICE3_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE_MASK 0x10u -#define GET_DEVICE3_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE3_GPHY_STRAP_RXCPU_SPAD_ECC_ENABLE(__val__) (((__val__) << 4u) & 0x10u) - #define REG_DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1 ((volatile APE_DEVICE3_H_uint32_t*)0xa007367c) /* */ -#define DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_SHIFT 4u -#define DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE_MASK 0x10u -#define GET_DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_NCSI_CLOCK_OUTPUT_DISABLE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_SHIFT 5u -#define DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE_MASK 0x20u -#define GET_DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE3_TOP_LEVEL_MISCELLANEOUS_CONTROL_1_LOW_POWER_IDDQ_MODE(__val__) (((__val__) << 5u) & 0x20u) - #define REG_DEVICE3_EEE_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa00736b0) /* */ -#define DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI_SHIFT 0u -#define DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI_MASK 0x1u -#define GET_DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI_SHIFT 1u -#define DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI_MASK 0x2u -#define GET_DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_EEE_MODE_APE_TX_DETECTION_ENABLE_SHIFT 2u -#define DEVICE3_EEE_MODE_APE_TX_DETECTION_ENABLE_MASK 0x4u -#define GET_DEVICE3_EEE_MODE_APE_TX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE3_EEE_MODE_APE_TX_DETECTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE3_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_SHIFT 3u -#define DEVICE3_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE_MASK 0x8u -#define GET_DEVICE3_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE3_EEE_MODE_EEE_LINK_IDLE_DETECTION_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE3_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_SHIFT 4u -#define DEVICE3_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE_MASK 0x10u -#define GET_DEVICE3_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE3_EEE_MODE_PCIE_L1_EXIT_DETECTION_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_SHIFT 5u -#define DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE_MASK 0x20u -#define GET_DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE3_EEE_MODE_RX_CPU_ALLOW_LPI_ENABLE(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE3_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_SHIFT 6u -#define DEVICE3_EEE_MODE_SEND_INDEX_DETECTION_ENABLE_MASK 0x40u -#define GET_DEVICE3_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE3_EEE_MODE_SEND_INDEX_DETECTION_ENABLE(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE3_EEE_MODE_USER_LPI_ENABLE_SHIFT 7u -#define DEVICE3_EEE_MODE_USER_LPI_ENABLE_MASK 0x80u -#define GET_DEVICE3_EEE_MODE_USER_LPI_ENABLE(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE3_EEE_MODE_USER_LPI_ENABLE(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE3_EEE_MODE_TX_LPI_ENABLE_SHIFT 8u -#define DEVICE3_EEE_MODE_TX_LPI_ENABLE_MASK 0x100u -#define GET_DEVICE3_EEE_MODE_TX_LPI_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE3_EEE_MODE_TX_LPI_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE3_EEE_MODE_RX_LPI_ENABLE_SHIFT 9u -#define DEVICE3_EEE_MODE_RX_LPI_ENABLE_MASK 0x200u -#define GET_DEVICE3_EEE_MODE_RX_LPI_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE3_EEE_MODE_RX_LPI_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE3_EEE_MODE_AUTO_WAKE_ENABLE_SHIFT 10u -#define DEVICE3_EEE_MODE_AUTO_WAKE_ENABLE_MASK 0x400u -#define GET_DEVICE3_EEE_MODE_AUTO_WAKE_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE3_EEE_MODE_AUTO_WAKE_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE3_EEE_MODE_BLOCK_TIME_SHIFT 11u -#define DEVICE3_EEE_MODE_BLOCK_TIME_MASK 0x7f800u -#define GET_DEVICE3_EEE_MODE_BLOCK_TIME(__reg__) (((__reg__) & 0x7f800) >> 11u) -#define SET_DEVICE3_EEE_MODE_BLOCK_TIME(__val__) (((__val__) << 11u) & 0x7f800u) -#define DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_SHIFT 19u -#define DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE_MASK 0x80000u -#define GET_DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE3_EEE_MODE_DRIVE_ALLOW_LPI_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) - #define REG_DEVICE3_EEE_LINK_IDLE_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa00736bc) /* */ -#define DEVICE3_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_SHIFT 2u -#define DEVICE3_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE_MASK 0x4u -#define GET_DEVICE3_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE3_EEE_LINK_IDLE_CONTROL_DEBUG_UART_IDLE(__val__) (((__val__) << 2u) & 0x4u) - #define REG_DEVICE3_EEE_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa00736d0) /* */ -#define DEVICE3_EEE_CONTROL_EXIT_TIME_SHIFT 0u -#define DEVICE3_EEE_CONTROL_EXIT_TIME_MASK 0xffffu -#define GET_DEVICE3_EEE_CONTROL_EXIT_TIME(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE3_EEE_CONTROL_EXIT_TIME(__val__) (((__val__) << 0u) & 0xffffu) -#define DEVICE3_EEE_CONTROL_MINIMUM_ASSERT_SHIFT 16u -#define DEVICE3_EEE_CONTROL_MINIMUM_ASSERT_MASK 0xffff0000u -#define GET_DEVICE3_EEE_CONTROL_MINIMUM_ASSERT(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_DEVICE3_EEE_CONTROL_MINIMUM_ASSERT(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_DEVICE3_GLOBAL_MUTEX_REQUEST ((volatile APE_DEVICE3_H_uint32_t*)0xa00736f0) /* */ #define REG_DEVICE3_GLOBAL_MUTEX_GRANT ((volatile APE_DEVICE3_H_uint32_t*)0xa00736f4) /* */ #define REG_DEVICE3_MEMORY_ARBITER_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0074000) /* */ -#define DEVICE3_MEMORY_ARBITER_MODE_ENABLE_SHIFT 1u -#define DEVICE3_MEMORY_ARBITER_MODE_ENABLE_MASK 0x2u -#define GET_DEVICE3_MEMORY_ARBITER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_MEMORY_ARBITER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) - #define REG_DEVICE3_BUFFER_MANAGER_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0074400) /* */ -#define DEVICE3_BUFFER_MANAGER_MODE_ENABLE_SHIFT 1u -#define DEVICE3_BUFFER_MANAGER_MODE_ENABLE_MASK 0x2u -#define GET_DEVICE3_BUFFER_MANAGER_MODE_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_BUFFER_MANAGER_MODE_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_SHIFT 2u -#define DEVICE3_BUFFER_MANAGER_MODE_ATTENTION_ENABLE_MASK 0x4u -#define GET_DEVICE3_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE3_BUFFER_MANAGER_MODE_ATTENTION_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE3_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_SHIFT 5u -#define DEVICE3_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER_MASK 0x20u -#define GET_DEVICE3_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE3_BUFFER_MANAGER_MODE_RESET_RXMBUF_POINTER(__val__) (((__val__) << 5u) & 0x20u) - #define REG_DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0074910) /* */ -#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_SHIFT 16u -#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_MASK 0x30000u -#define GET_DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__reg__) (((__reg__) & 0x30000) >> 16u) -#define SET_DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE(__val__) (((__val__) << 16u) & 0x30000u) -#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_128B 0x0u -#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_256B 0x1u -#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_512B 0x2u -#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_BD_RDMA_ENGINE_4K 0x3u - -#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_SHIFT 18u -#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_MASK 0xc0000u -#define GET_DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__reg__) (((__reg__) & 0xc0000) >> 18u) -#define SET_DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE(__val__) (((__val__) << 18u) & 0xc0000u) -#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_128B 0x0u -#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_256B 0x1u -#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_512B 0x2u -#define DEVICE3_LSO_NONLSO_BD_READ_DMA_CORRUPTION_ENABLE_CONTROL_PCI_REQUEST_BURST_LENGTH_FOR_NONLSO_RDMA_ENGINE_4K 0x3u - - #define REG_DEVICE3_RX_RISC_MODE ((volatile APE_DEVICE3_H_uint32_t*)0xa0075000) /* */ -#define DEVICE3_RX_RISC_MODE_RESET_SHIFT 0u -#define DEVICE3_RX_RISC_MODE_RESET_MASK 0x1u -#define GET_DEVICE3_RX_RISC_MODE_RESET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE3_RX_RISC_MODE_RESET(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE3_RX_RISC_MODE_SINGLE_STEP_SHIFT 1u -#define DEVICE3_RX_RISC_MODE_SINGLE_STEP_MASK 0x2u -#define GET_DEVICE3_RX_RISC_MODE_SINGLE_STEP(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_RX_RISC_MODE_SINGLE_STEP(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_RX_RISC_MODE_PAGE_0_DATA_HALT_SHIFT 2u -#define DEVICE3_RX_RISC_MODE_PAGE_0_DATA_HALT_MASK 0x4u -#define GET_DEVICE3_RX_RISC_MODE_PAGE_0_DATA_HALT(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE3_RX_RISC_MODE_PAGE_0_DATA_HALT(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE3_RX_RISC_MODE_PAGE_0_INSTR_HALT_SHIFT 3u -#define DEVICE3_RX_RISC_MODE_PAGE_0_INSTR_HALT_MASK 0x8u -#define GET_DEVICE3_RX_RISC_MODE_PAGE_0_INSTR_HALT(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE3_RX_RISC_MODE_PAGE_0_INSTR_HALT(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE3_RX_RISC_MODE_ENABLE_DATA_CACHE_SHIFT 5u -#define DEVICE3_RX_RISC_MODE_ENABLE_DATA_CACHE_MASK 0x20u -#define GET_DEVICE3_RX_RISC_MODE_ENABLE_DATA_CACHE(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE3_RX_RISC_MODE_ENABLE_DATA_CACHE(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE3_RX_RISC_MODE_ROM_FAIL_SHIFT 6u -#define DEVICE3_RX_RISC_MODE_ROM_FAIL_MASK 0x40u -#define GET_DEVICE3_RX_RISC_MODE_ROM_FAIL(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE3_RX_RISC_MODE_ROM_FAIL(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE3_RX_RISC_MODE_ENABLE_WATCHDOG_SHIFT 7u -#define DEVICE3_RX_RISC_MODE_ENABLE_WATCHDOG_MASK 0x80u -#define GET_DEVICE3_RX_RISC_MODE_ENABLE_WATCHDOG(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE3_RX_RISC_MODE_ENABLE_WATCHDOG(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE3_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_SHIFT 8u -#define DEVICE3_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE_MASK 0x100u -#define GET_DEVICE3_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE3_RX_RISC_MODE_ENABLE_INSTRUCTION_CACHE(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE3_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_SHIFT 9u -#define DEVICE3_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE_MASK 0x200u -#define GET_DEVICE3_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE3_RX_RISC_MODE_FLUSH_INSTRUCTION_CACHE(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE3_RX_RISC_MODE_HALT_SHIFT 10u -#define DEVICE3_RX_RISC_MODE_HALT_MASK 0x400u -#define GET_DEVICE3_RX_RISC_MODE_HALT(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE3_RX_RISC_MODE_HALT(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE3_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_SHIFT 11u -#define DEVICE3_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT_MASK 0x800u -#define GET_DEVICE3_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE3_RX_RISC_MODE_INVALID_DATA_ACCESS_HALT(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE3_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_SHIFT 12u -#define DEVICE3_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT_MASK 0x1000u -#define GET_DEVICE3_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_DEVICE3_RX_RISC_MODE_INVALID_INSTRUCTION_ACCESS_HALT(__val__) (((__val__) << 12u) & 0x1000u) -#define DEVICE3_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_SHIFT 13u -#define DEVICE3_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT_MASK 0x2000u -#define GET_DEVICE3_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE3_RX_RISC_MODE_ENABLE_MEMORY_ADDRESS_TRAP_HALT(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE3_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_SHIFT 14u -#define DEVICE3_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT_MASK 0x4000u -#define GET_DEVICE3_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE3_RX_RISC_MODE_ENABLE_REGISTER_ADDRESS_TRAP_HALT(__val__) (((__val__) << 14u) & 0x4000u) - #define REG_DEVICE3_RX_RISC_STATUS ((volatile APE_DEVICE3_H_uint32_t*)0xa0075004) /* */ -#define DEVICE3_RX_RISC_STATUS_HARDWARE_BREAKPOINT_SHIFT 0u -#define DEVICE3_RX_RISC_STATUS_HARDWARE_BREAKPOINT_MASK 0x1u -#define GET_DEVICE3_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_DEVICE3_RX_RISC_STATUS_HARDWARE_BREAKPOINT(__val__) (((__val__) << 0u) & 0x1u) -#define DEVICE3_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_SHIFT 1u -#define DEVICE3_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED_MASK 0x2u -#define GET_DEVICE3_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_RX_RISC_STATUS_HALT_INSTRUCTION_EXECUTED(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION_SHIFT 2u -#define DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION_MASK 0x4u -#define GET_DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION(__val__) (((__val__) << 2u) & 0x4u) -#define DEVICE3_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_SHIFT 3u -#define DEVICE3_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE_MASK 0x8u -#define GET_DEVICE3_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_DEVICE3_RX_RISC_STATUS_PAGE_0_DATA_REFEENCE(__val__) (((__val__) << 3u) & 0x8u) -#define DEVICE3_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_SHIFT 4u -#define DEVICE3_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE_MASK 0x10u -#define GET_DEVICE3_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_DEVICE3_RX_RISC_STATUS_PAGE_0_INSTRUCTION_REFERENCE(__val__) (((__val__) << 4u) & 0x10u) -#define DEVICE3_RX_RISC_STATUS_INVALID_DATA_ACCESS_SHIFT 5u -#define DEVICE3_RX_RISC_STATUS_INVALID_DATA_ACCESS_MASK 0x20u -#define GET_DEVICE3_RX_RISC_STATUS_INVALID_DATA_ACCESS(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_DEVICE3_RX_RISC_STATUS_INVALID_DATA_ACCESS(__val__) (((__val__) << 5u) & 0x20u) -#define DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_SHIFT 6u -#define DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH_MASK 0x40u -#define GET_DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_DEVICE3_RX_RISC_STATUS_INVALID_INSTRUCTION_FETCH(__val__) (((__val__) << 6u) & 0x40u) -#define DEVICE3_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_SHIFT 7u -#define DEVICE3_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT_MASK 0x80u -#define GET_DEVICE3_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__reg__) (((__reg__) & 0x80) >> 7u) -#define SET_DEVICE3_RX_RISC_STATUS_BAD_MEMORY_ALIGNMENT(__val__) (((__val__) << 7u) & 0x80u) -#define DEVICE3_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_SHIFT 8u -#define DEVICE3_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP_MASK 0x100u -#define GET_DEVICE3_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE3_RX_RISC_STATUS_MEMORY_ADDRESS_TRAP(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE3_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_SHIFT 9u -#define DEVICE3_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP_MASK 0x200u -#define GET_DEVICE3_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE3_RX_RISC_STATUS_REGISTER_ADDRESS_TRAP(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE3_RX_RISC_STATUS_HALTED_SHIFT 10u -#define DEVICE3_RX_RISC_STATUS_HALTED_MASK 0x400u -#define GET_DEVICE3_RX_RISC_STATUS_HALTED(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE3_RX_RISC_STATUS_HALTED(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE3_RX_RISC_STATUS_UNKNOWN_SHIFT 11u -#define DEVICE3_RX_RISC_STATUS_UNKNOWN_MASK 0x800u -#define GET_DEVICE3_RX_RISC_STATUS_UNKNOWN(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE3_RX_RISC_STATUS_UNKNOWN(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE3_RX_RISC_STATUS_DATA_ACCESS_STALL_SHIFT 14u -#define DEVICE3_RX_RISC_STATUS_DATA_ACCESS_STALL_MASK 0x4000u -#define GET_DEVICE3_RX_RISC_STATUS_DATA_ACCESS_STALL(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE3_RX_RISC_STATUS_DATA_ACCESS_STALL(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE3_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_SHIFT 15u -#define DEVICE3_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL_MASK 0x8000u -#define GET_DEVICE3_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE3_RX_RISC_STATUS_INSTRUCTION_FETCH_STALL(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE3_RX_RISC_STATUS_BLOCKING_READ_SHIFT 31u -#define DEVICE3_RX_RISC_STATUS_BLOCKING_READ_MASK 0x80000000u -#define GET_DEVICE3_RX_RISC_STATUS_BLOCKING_READ(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE3_RX_RISC_STATUS_BLOCKING_READ(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE3_RX_RISC_PROGRAM_COUNTER ((volatile APE_DEVICE3_H_uint32_t*)0xa007501c) /* The program counter register can be used to read or write the current Program Counter of the each CPU. Reads can occur at any time, however writes can only be performed when the CPU is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. 1s written to bits 1-0 are ignored. */ #define REG_DEVICE3_RX_RISC_CURRENT_INSTRUCTION ((volatile APE_DEVICE3_H_uint32_t*)0xa0075020) /* This undocumented register contains the current word located at the program counter address loaded in */ #define REG_DEVICE3_RX_RISC_HARDWARE_BREAKPOINT ((volatile APE_DEVICE3_H_uint32_t*)0xa0075034) /* This register is used to set a hardware breakpoint based on the RISC's program counter (PC). If the PC equals the value in this register, and the hardware breakpoint is enabled, the RISC is halted and the appropriate stopping condition is indicated in the RISC State Register. To enable the hardware breakpoint, simply write the byte address of the instruction to break on and clear the Disable Hardware Breakpoint bit. */ @@ -1125,32 +178,9 @@ typedef uint32_t APE_DEVICE3_H_uint32_t; #define REG_DEVICE3_PCI_POWER_CONSUMPTION_INFO ((volatile APE_DEVICE3_H_uint32_t*)0xa0076410) /* This undocumented register is used to set PCIe Power Consumption information as reported in configuration space. It is loaded from NVM configuration data. */ #define REG_DEVICE3_PCI_POWER_DISSIPATED_INFO ((volatile APE_DEVICE3_H_uint32_t*)0xa0076414) /* This undocumented register is used to set PCIe Power Dissipated information as reported in configuration space. It is loaded from NVM configuration data. */ #define REG_DEVICE3_PCI_VPD_REQUEST ((volatile APE_DEVICE3_H_uint32_t*)0xa007642c) /* This undocumented register appears to be used to implement the PCI VPD capability. It is set to the VPD offset which was requested by the host by writing to the VPD register. */ -#define DEVICE3_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_SHIFT 16u -#define DEVICE3_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET_MASK 0x7fff0000u -#define GET_DEVICE3_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__reg__) (((__reg__) & 0x7fff0000) >> 16u) -#define SET_DEVICE3_PCI_VPD_REQUEST_REQUESTED_VPD_OFFSET(__val__) (((__val__) << 16u) & 0x7fff0000u) - #define REG_DEVICE3_PCI_VPD_RESPONSE ((volatile APE_DEVICE3_H_uint32_t*)0xa0076430) /* This undocumented register appears to be used to implement the PCI VPD capability. Bootcode writes the 32 bits of data loaded from the word requested by */ #define REG_DEVICE3_PCI_VENDOR_DEVICE_ID ((volatile APE_DEVICE3_H_uint32_t*)0xa0076434) /* This is the undocumented register used to set the PCI Vendor/Device ID, which is configurable from NVM. */ -#define DEVICE3_PCI_VENDOR_DEVICE_ID_DEVICE_ID_SHIFT 0u -#define DEVICE3_PCI_VENDOR_DEVICE_ID_DEVICE_ID_MASK 0xffffu -#define GET_DEVICE3_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE3_PCI_VENDOR_DEVICE_ID_DEVICE_ID(__val__) (((__val__) << 0u) & 0xffffu) -#define DEVICE3_PCI_VENDOR_DEVICE_ID_VENDOR_ID_SHIFT 16u -#define DEVICE3_PCI_VENDOR_DEVICE_ID_VENDOR_ID_MASK 0xffff0000u -#define GET_DEVICE3_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_DEVICE3_PCI_VENDOR_DEVICE_ID_VENDOR_ID(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_DEVICE3_PCI_SUBSYSTEM_ID ((volatile APE_DEVICE3_H_uint32_t*)0xa0076438) /* This is the undocumented register used to set the PCI Subsystem/Subsystem Vendor ID, which is configurable from NVM. */ -#define DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0u -#define DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_MASK 0xffffu -#define GET_DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID(__val__) (((__val__) << 0u) & 0xffffu) -#define DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_SHIFT 16u -#define DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID_MASK 0xffff0000u -#define GET_DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_DEVICE3_PCI_SUBSYSTEM_ID_SUBSYSTEM_ID(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_DEVICE3_PCI_CLASS_CODE_REVISION ((volatile APE_DEVICE3_H_uint32_t*)0xa007643c) /* This undocumented register is suspected to set the class code and device revision in PCI configuration space. Unconfirmed. */ #define REG_DEVICE3_64C0 ((volatile APE_DEVICE3_H_uint32_t*)0xa00764c0) /* */ #define REG_DEVICE3_64C8 ((volatile APE_DEVICE3_H_uint32_t*)0xa00764c8) /* */ @@ -1158,548 +188,28 @@ typedef uint32_t APE_DEVICE3_H_uint32_t; #define REG_DEVICE3_PCI_SERIAL_NUMBER_LOW ((volatile APE_DEVICE3_H_uint32_t*)0xa0076504) /* This sets the low 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ #define REG_DEVICE3_PCI_SERIAL_NUMBER_HIGH ((volatile APE_DEVICE3_H_uint32_t*)0xa0076508) /* This sets the high 32 bits of the 64-bit device serial number, which isexposed as a PCIe capability in configuration space. */ #define REG_DEVICE3_PCI_POWER_BUDGET_0 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076510) /* Used to report power budget capability data to the host. The values are loaded from NVM, and up to eight values may be specified. */ -#define DEVICE3_PCI_POWER_BUDGET_0_BASE_POWER_SHIFT 0u -#define DEVICE3_PCI_POWER_BUDGET_0_BASE_POWER_MASK 0xffu -#define GET_DEVICE3_PCI_POWER_BUDGET_0_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE3_PCI_POWER_BUDGET_0_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE_SHIFT 8u -#define DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE_MASK 0x300u -#define GET_DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE_1_0X 0x0u -#define DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE_0_1X 0x1u -#define DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE_0_01X 0x2u -#define DEVICE3_PCI_POWER_BUDGET_0_DATA_SCALE_0_001X 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_0_PM_SUB_STATE_SHIFT 10u -#define DEVICE3_PCI_POWER_BUDGET_0_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE3_PCI_POWER_BUDGET_0_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE3_PCI_POWER_BUDGET_0_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE3_PCI_POWER_BUDGET_0_PM_STATE_SHIFT 13u -#define DEVICE3_PCI_POWER_BUDGET_0_PM_STATE_MASK 0x6000u -#define GET_DEVICE3_PCI_POWER_BUDGET_0_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE3_PCI_POWER_BUDGET_0_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE3_PCI_POWER_BUDGET_0_PM_STATE_D0 0x0u -#define DEVICE3_PCI_POWER_BUDGET_0_PM_STATE_D1 0x1u -#define DEVICE3_PCI_POWER_BUDGET_0_PM_STATE_D2 0x2u -#define DEVICE3_PCI_POWER_BUDGET_0_PM_STATE_D3 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_SHIFT 15u -#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_MASK 0x38000u -#define GET_DEVICE3_PCI_POWER_BUDGET_0_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE3_PCI_POWER_BUDGET_0_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_PME_AUX 0x0u -#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_AUXILIARY 0x1u -#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_IDLE 0x2u -#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_SUSTAINED 0x3u -#define DEVICE3_PCI_POWER_BUDGET_0_TYPE_MAXIMUM 0x7u - -#define DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL_SHIFT 18u -#define DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_12V 0x0u -#define DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE3_PCI_POWER_BUDGET_0_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE3_PCI_POWER_BUDGET_1 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076514) /* See */ -#define DEVICE3_PCI_POWER_BUDGET_1_BASE_POWER_SHIFT 0u -#define DEVICE3_PCI_POWER_BUDGET_1_BASE_POWER_MASK 0xffu -#define GET_DEVICE3_PCI_POWER_BUDGET_1_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE3_PCI_POWER_BUDGET_1_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE_SHIFT 8u -#define DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE_MASK 0x300u -#define GET_DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE_1_0X 0x0u -#define DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE_0_1X 0x1u -#define DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE_0_01X 0x2u -#define DEVICE3_PCI_POWER_BUDGET_1_DATA_SCALE_0_001X 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_1_PM_SUB_STATE_SHIFT 10u -#define DEVICE3_PCI_POWER_BUDGET_1_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE3_PCI_POWER_BUDGET_1_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE3_PCI_POWER_BUDGET_1_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE3_PCI_POWER_BUDGET_1_PM_STATE_SHIFT 13u -#define DEVICE3_PCI_POWER_BUDGET_1_PM_STATE_MASK 0x6000u -#define GET_DEVICE3_PCI_POWER_BUDGET_1_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE3_PCI_POWER_BUDGET_1_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE3_PCI_POWER_BUDGET_1_PM_STATE_D0 0x0u -#define DEVICE3_PCI_POWER_BUDGET_1_PM_STATE_D1 0x1u -#define DEVICE3_PCI_POWER_BUDGET_1_PM_STATE_D2 0x2u -#define DEVICE3_PCI_POWER_BUDGET_1_PM_STATE_D3 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_SHIFT 15u -#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_MASK 0x38000u -#define GET_DEVICE3_PCI_POWER_BUDGET_1_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE3_PCI_POWER_BUDGET_1_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_PME_AUX 0x0u -#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_AUXILIARY 0x1u -#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_IDLE 0x2u -#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_SUSTAINED 0x3u -#define DEVICE3_PCI_POWER_BUDGET_1_TYPE_MAXIMUM 0x7u - -#define DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL_SHIFT 18u -#define DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_12V 0x0u -#define DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE3_PCI_POWER_BUDGET_1_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE3_PCI_POWER_BUDGET_2 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076518) /* See */ -#define DEVICE3_PCI_POWER_BUDGET_2_BASE_POWER_SHIFT 0u -#define DEVICE3_PCI_POWER_BUDGET_2_BASE_POWER_MASK 0xffu -#define GET_DEVICE3_PCI_POWER_BUDGET_2_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE3_PCI_POWER_BUDGET_2_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE_SHIFT 8u -#define DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE_MASK 0x300u -#define GET_DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE_1_0X 0x0u -#define DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE_0_1X 0x1u -#define DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE_0_01X 0x2u -#define DEVICE3_PCI_POWER_BUDGET_2_DATA_SCALE_0_001X 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_2_PM_SUB_STATE_SHIFT 10u -#define DEVICE3_PCI_POWER_BUDGET_2_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE3_PCI_POWER_BUDGET_2_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE3_PCI_POWER_BUDGET_2_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE3_PCI_POWER_BUDGET_2_PM_STATE_SHIFT 13u -#define DEVICE3_PCI_POWER_BUDGET_2_PM_STATE_MASK 0x6000u -#define GET_DEVICE3_PCI_POWER_BUDGET_2_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE3_PCI_POWER_BUDGET_2_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE3_PCI_POWER_BUDGET_2_PM_STATE_D0 0x0u -#define DEVICE3_PCI_POWER_BUDGET_2_PM_STATE_D1 0x1u -#define DEVICE3_PCI_POWER_BUDGET_2_PM_STATE_D2 0x2u -#define DEVICE3_PCI_POWER_BUDGET_2_PM_STATE_D3 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_SHIFT 15u -#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_MASK 0x38000u -#define GET_DEVICE3_PCI_POWER_BUDGET_2_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE3_PCI_POWER_BUDGET_2_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_PME_AUX 0x0u -#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_AUXILIARY 0x1u -#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_IDLE 0x2u -#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_SUSTAINED 0x3u -#define DEVICE3_PCI_POWER_BUDGET_2_TYPE_MAXIMUM 0x7u - -#define DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL_SHIFT 18u -#define DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_12V 0x0u -#define DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE3_PCI_POWER_BUDGET_2_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE3_PCI_POWER_BUDGET_3 ((volatile APE_DEVICE3_H_uint32_t*)0xa007651c) /* See */ -#define DEVICE3_PCI_POWER_BUDGET_3_BASE_POWER_SHIFT 0u -#define DEVICE3_PCI_POWER_BUDGET_3_BASE_POWER_MASK 0xffu -#define GET_DEVICE3_PCI_POWER_BUDGET_3_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE3_PCI_POWER_BUDGET_3_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE_SHIFT 8u -#define DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE_MASK 0x300u -#define GET_DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE_1_0X 0x0u -#define DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE_0_1X 0x1u -#define DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE_0_01X 0x2u -#define DEVICE3_PCI_POWER_BUDGET_3_DATA_SCALE_0_001X 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_3_PM_SUB_STATE_SHIFT 10u -#define DEVICE3_PCI_POWER_BUDGET_3_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE3_PCI_POWER_BUDGET_3_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE3_PCI_POWER_BUDGET_3_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE3_PCI_POWER_BUDGET_3_PM_STATE_SHIFT 13u -#define DEVICE3_PCI_POWER_BUDGET_3_PM_STATE_MASK 0x6000u -#define GET_DEVICE3_PCI_POWER_BUDGET_3_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE3_PCI_POWER_BUDGET_3_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE3_PCI_POWER_BUDGET_3_PM_STATE_D0 0x0u -#define DEVICE3_PCI_POWER_BUDGET_3_PM_STATE_D1 0x1u -#define DEVICE3_PCI_POWER_BUDGET_3_PM_STATE_D2 0x2u -#define DEVICE3_PCI_POWER_BUDGET_3_PM_STATE_D3 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_SHIFT 15u -#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_MASK 0x38000u -#define GET_DEVICE3_PCI_POWER_BUDGET_3_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE3_PCI_POWER_BUDGET_3_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_PME_AUX 0x0u -#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_AUXILIARY 0x1u -#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_IDLE 0x2u -#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_SUSTAINED 0x3u -#define DEVICE3_PCI_POWER_BUDGET_3_TYPE_MAXIMUM 0x7u - -#define DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL_SHIFT 18u -#define DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_12V 0x0u -#define DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE3_PCI_POWER_BUDGET_3_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE3_PCI_POWER_BUDGET_4 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076520) /* See */ -#define DEVICE3_PCI_POWER_BUDGET_4_BASE_POWER_SHIFT 0u -#define DEVICE3_PCI_POWER_BUDGET_4_BASE_POWER_MASK 0xffu -#define GET_DEVICE3_PCI_POWER_BUDGET_4_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE3_PCI_POWER_BUDGET_4_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE_SHIFT 8u -#define DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE_MASK 0x300u -#define GET_DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE_1_0X 0x0u -#define DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE_0_1X 0x1u -#define DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE_0_01X 0x2u -#define DEVICE3_PCI_POWER_BUDGET_4_DATA_SCALE_0_001X 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_4_PM_SUB_STATE_SHIFT 10u -#define DEVICE3_PCI_POWER_BUDGET_4_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE3_PCI_POWER_BUDGET_4_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE3_PCI_POWER_BUDGET_4_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE3_PCI_POWER_BUDGET_4_PM_STATE_SHIFT 13u -#define DEVICE3_PCI_POWER_BUDGET_4_PM_STATE_MASK 0x6000u -#define GET_DEVICE3_PCI_POWER_BUDGET_4_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE3_PCI_POWER_BUDGET_4_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE3_PCI_POWER_BUDGET_4_PM_STATE_D0 0x0u -#define DEVICE3_PCI_POWER_BUDGET_4_PM_STATE_D1 0x1u -#define DEVICE3_PCI_POWER_BUDGET_4_PM_STATE_D2 0x2u -#define DEVICE3_PCI_POWER_BUDGET_4_PM_STATE_D3 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_SHIFT 15u -#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_MASK 0x38000u -#define GET_DEVICE3_PCI_POWER_BUDGET_4_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE3_PCI_POWER_BUDGET_4_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_PME_AUX 0x0u -#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_AUXILIARY 0x1u -#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_IDLE 0x2u -#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_SUSTAINED 0x3u -#define DEVICE3_PCI_POWER_BUDGET_4_TYPE_MAXIMUM 0x7u - -#define DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL_SHIFT 18u -#define DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_12V 0x0u -#define DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE3_PCI_POWER_BUDGET_4_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE3_PCI_POWER_BUDGET_5 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076524) /* See */ -#define DEVICE3_PCI_POWER_BUDGET_5_BASE_POWER_SHIFT 0u -#define DEVICE3_PCI_POWER_BUDGET_5_BASE_POWER_MASK 0xffu -#define GET_DEVICE3_PCI_POWER_BUDGET_5_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE3_PCI_POWER_BUDGET_5_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE_SHIFT 8u -#define DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE_MASK 0x300u -#define GET_DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE_1_0X 0x0u -#define DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE_0_1X 0x1u -#define DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE_0_01X 0x2u -#define DEVICE3_PCI_POWER_BUDGET_5_DATA_SCALE_0_001X 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_5_PM_SUB_STATE_SHIFT 10u -#define DEVICE3_PCI_POWER_BUDGET_5_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE3_PCI_POWER_BUDGET_5_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE3_PCI_POWER_BUDGET_5_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE3_PCI_POWER_BUDGET_5_PM_STATE_SHIFT 13u -#define DEVICE3_PCI_POWER_BUDGET_5_PM_STATE_MASK 0x6000u -#define GET_DEVICE3_PCI_POWER_BUDGET_5_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE3_PCI_POWER_BUDGET_5_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE3_PCI_POWER_BUDGET_5_PM_STATE_D0 0x0u -#define DEVICE3_PCI_POWER_BUDGET_5_PM_STATE_D1 0x1u -#define DEVICE3_PCI_POWER_BUDGET_5_PM_STATE_D2 0x2u -#define DEVICE3_PCI_POWER_BUDGET_5_PM_STATE_D3 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_SHIFT 15u -#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_MASK 0x38000u -#define GET_DEVICE3_PCI_POWER_BUDGET_5_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE3_PCI_POWER_BUDGET_5_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_PME_AUX 0x0u -#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_AUXILIARY 0x1u -#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_IDLE 0x2u -#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_SUSTAINED 0x3u -#define DEVICE3_PCI_POWER_BUDGET_5_TYPE_MAXIMUM 0x7u - -#define DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL_SHIFT 18u -#define DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_12V 0x0u -#define DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE3_PCI_POWER_BUDGET_5_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE3_PCI_POWER_BUDGET_6 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076528) /* See */ -#define DEVICE3_PCI_POWER_BUDGET_6_BASE_POWER_SHIFT 0u -#define DEVICE3_PCI_POWER_BUDGET_6_BASE_POWER_MASK 0xffu -#define GET_DEVICE3_PCI_POWER_BUDGET_6_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE3_PCI_POWER_BUDGET_6_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE_SHIFT 8u -#define DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE_MASK 0x300u -#define GET_DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE_1_0X 0x0u -#define DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE_0_1X 0x1u -#define DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE_0_01X 0x2u -#define DEVICE3_PCI_POWER_BUDGET_6_DATA_SCALE_0_001X 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_6_PM_SUB_STATE_SHIFT 10u -#define DEVICE3_PCI_POWER_BUDGET_6_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE3_PCI_POWER_BUDGET_6_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE3_PCI_POWER_BUDGET_6_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE3_PCI_POWER_BUDGET_6_PM_STATE_SHIFT 13u -#define DEVICE3_PCI_POWER_BUDGET_6_PM_STATE_MASK 0x6000u -#define GET_DEVICE3_PCI_POWER_BUDGET_6_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE3_PCI_POWER_BUDGET_6_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE3_PCI_POWER_BUDGET_6_PM_STATE_D0 0x0u -#define DEVICE3_PCI_POWER_BUDGET_6_PM_STATE_D1 0x1u -#define DEVICE3_PCI_POWER_BUDGET_6_PM_STATE_D2 0x2u -#define DEVICE3_PCI_POWER_BUDGET_6_PM_STATE_D3 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_SHIFT 15u -#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_MASK 0x38000u -#define GET_DEVICE3_PCI_POWER_BUDGET_6_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE3_PCI_POWER_BUDGET_6_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_PME_AUX 0x0u -#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_AUXILIARY 0x1u -#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_IDLE 0x2u -#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_SUSTAINED 0x3u -#define DEVICE3_PCI_POWER_BUDGET_6_TYPE_MAXIMUM 0x7u - -#define DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL_SHIFT 18u -#define DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_12V 0x0u -#define DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE3_PCI_POWER_BUDGET_6_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE3_PCI_POWER_BUDGET_7 ((volatile APE_DEVICE3_H_uint32_t*)0xa007652c) /* See */ -#define DEVICE3_PCI_POWER_BUDGET_7_BASE_POWER_SHIFT 0u -#define DEVICE3_PCI_POWER_BUDGET_7_BASE_POWER_MASK 0xffu -#define GET_DEVICE3_PCI_POWER_BUDGET_7_BASE_POWER(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_DEVICE3_PCI_POWER_BUDGET_7_BASE_POWER(__val__) (((__val__) << 0u) & 0xffu) -#define DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE_SHIFT 8u -#define DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE_MASK 0x300u -#define GET_DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE(__reg__) (((__reg__) & 0x300) >> 8u) -#define SET_DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE(__val__) (((__val__) << 8u) & 0x300u) -#define DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE_1_0X 0x0u -#define DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE_0_1X 0x1u -#define DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE_0_01X 0x2u -#define DEVICE3_PCI_POWER_BUDGET_7_DATA_SCALE_0_001X 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_7_PM_SUB_STATE_SHIFT 10u -#define DEVICE3_PCI_POWER_BUDGET_7_PM_SUB_STATE_MASK 0x1c00u -#define GET_DEVICE3_PCI_POWER_BUDGET_7_PM_SUB_STATE(__reg__) (((__reg__) & 0x1c00) >> 10u) -#define SET_DEVICE3_PCI_POWER_BUDGET_7_PM_SUB_STATE(__val__) (((__val__) << 10u) & 0x1c00u) -#define DEVICE3_PCI_POWER_BUDGET_7_PM_STATE_SHIFT 13u -#define DEVICE3_PCI_POWER_BUDGET_7_PM_STATE_MASK 0x6000u -#define GET_DEVICE3_PCI_POWER_BUDGET_7_PM_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_DEVICE3_PCI_POWER_BUDGET_7_PM_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define DEVICE3_PCI_POWER_BUDGET_7_PM_STATE_D0 0x0u -#define DEVICE3_PCI_POWER_BUDGET_7_PM_STATE_D1 0x1u -#define DEVICE3_PCI_POWER_BUDGET_7_PM_STATE_D2 0x2u -#define DEVICE3_PCI_POWER_BUDGET_7_PM_STATE_D3 0x3u - -#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_SHIFT 15u -#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_MASK 0x38000u -#define GET_DEVICE3_PCI_POWER_BUDGET_7_TYPE(__reg__) (((__reg__) & 0x38000) >> 15u) -#define SET_DEVICE3_PCI_POWER_BUDGET_7_TYPE(__val__) (((__val__) << 15u) & 0x38000u) -#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_PME_AUX 0x0u -#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_AUXILIARY 0x1u -#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_IDLE 0x2u -#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_SUSTAINED 0x3u -#define DEVICE3_PCI_POWER_BUDGET_7_TYPE_MAXIMUM 0x7u - -#define DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL_SHIFT 18u -#define DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL_MASK 0x1c0000u -#define GET_DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_12V 0x0u -#define DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_3_3V 0x1u -#define DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL_POWER_1_5V_OR_1_8V 0x2u -#define DEVICE3_PCI_POWER_BUDGET_7_POWER_RAIL_THERMAL 0x7u - - #define REG_DEVICE3_6530 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076530) /* */ #define REG_DEVICE3_6550 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076550) /* The LSB in this undocumented and unknown register is set if the device is a LOM (LAN-on-Motherboard) design (i.e., builtin to a system and not an expansion card). */ #define REG_DEVICE3_65F4 ((volatile APE_DEVICE3_H_uint32_t*)0xa00765f4) /* */ #define REG_DEVICE3_GRC_MODE_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0076800) /* */ -#define DEVICE3_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_SHIFT 19u -#define DEVICE3_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE_MASK 0x80000u -#define GET_DEVICE3_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__reg__) (((__reg__) & 0x80000) >> 19u) -#define SET_DEVICE3_GRC_MODE_CONTROL_TIME_SYNC_MODE_ENABLE(__val__) (((__val__) << 19u) & 0x80000u) -#define DEVICE3_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_SHIFT 21u -#define DEVICE3_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE_MASK 0x200000u -#define GET_DEVICE3_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__reg__) (((__reg__) & 0x200000) >> 21u) -#define SET_DEVICE3_GRC_MODE_CONTROL_NVRAM_WRITE_ENABLE(__val__) (((__val__) << 21u) & 0x200000u) -#define DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_SHIFT 22u -#define DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1_MASK 0x400000u -#define GET_DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__reg__) (((__reg__) & 0x400000) >> 22u) -#define SET_DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_1(__val__) (((__val__) << 22u) & 0x400000u) -#define DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_SHIFT 29u -#define DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2_MASK 0x20000000u -#define GET_DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_2(__val__) (((__val__) << 29u) & 0x20000000u) -#define DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_SHIFT 31u -#define DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3_MASK 0x80000000u -#define GET_DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE3_GRC_MODE_CONTROL_PCIE_TL_DIV_DL_DIV_PL_MAPPING_3(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE3_MISCELLANEOUS_CONFIG ((volatile APE_DEVICE3_H_uint32_t*)0xa0076804) /* */ -#define DEVICE3_MISCELLANEOUS_CONFIG_GRC_RESET_SHIFT 1u -#define DEVICE3_MISCELLANEOUS_CONFIG_GRC_RESET_MASK 0x2u -#define GET_DEVICE3_MISCELLANEOUS_CONFIG_GRC_RESET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_DEVICE3_MISCELLANEOUS_CONFIG_GRC_RESET(__val__) (((__val__) << 1u) & 0x2u) -#define DEVICE3_MISCELLANEOUS_CONFIG_ALL_SHIFT 1u -#define DEVICE3_MISCELLANEOUS_CONFIG_ALL_MASK 0xfffffffeu -#define GET_DEVICE3_MISCELLANEOUS_CONFIG_ALL(__reg__) (((__reg__) & 0xfffffffe) >> 1u) -#define SET_DEVICE3_MISCELLANEOUS_CONFIG_ALL(__val__) (((__val__) << 1u) & 0xfffffffeu) - #define REG_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0076808) /* */ -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_SHIFT 8u -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_MASK 0x100u -#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT(__val__) (((__val__) << 8u) & 0x100u) -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_SHIFT 9u -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT_MASK 0x200u -#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_INPUT(__val__) (((__val__) << 9u) & 0x200u) -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_SHIFT 10u -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT_MASK 0x400u -#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_INPUT(__val__) (((__val__) << 10u) & 0x400u) -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_SHIFT 11u -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE_MASK 0x800u -#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_ENABLE(__val__) (((__val__) << 11u) & 0x800u) -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_SHIFT 12u -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE_MASK 0x1000u -#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_ENABLE(__val__) (((__val__) << 12u) & 0x1000u) -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_SHIFT 13u -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE_MASK 0x2000u -#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__reg__) (((__reg__) & 0x2000) >> 13u) -#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_ENABLE(__val__) (((__val__) << 13u) & 0x2000u) -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_SHIFT 14u -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT_MASK 0x4000u -#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_OUTPUT(__val__) (((__val__) << 14u) & 0x4000u) -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_SHIFT 15u -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT_MASK 0x8000u -#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_1_OUTPUT(__val__) (((__val__) << 15u) & 0x8000u) -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_SHIFT 16u -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT_MASK 0x10000u -#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__reg__) (((__reg__) & 0x10000) >> 16u) -#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_GPIO_2_OUTPUT(__val__) (((__val__) << 16u) & 0x10000u) -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_SHIFT 24u -#define DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS_MASK 0x1000000u -#define GET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_DEVICE3_MISCELLANEOUS_LOCAL_CONTROL_AUTO_SEEPROM_ACCESS(__val__) (((__val__) << 24u) & 0x1000000u) - #define REG_DEVICE3_TIMER ((volatile APE_DEVICE3_H_uint32_t*)0xa007680c) /* 32-bit free-running counter */ #define REG_DEVICE3_RX_CPU_EVENT ((volatile APE_DEVICE3_H_uint32_t*)0xa0076810) /* */ -#define DEVICE3_RX_CPU_EVENT_MAC_ATTENTION_SHIFT 25u -#define DEVICE3_RX_CPU_EVENT_MAC_ATTENTION_MASK 0x2000000u -#define GET_DEVICE3_RX_CPU_EVENT_MAC_ATTENTION(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_DEVICE3_RX_CPU_EVENT_MAC_ATTENTION(__val__) (((__val__) << 25u) & 0x2000000u) -#define DEVICE3_RX_CPU_EVENT_RX_CPU_ATTENTION_SHIFT 26u -#define DEVICE3_RX_CPU_EVENT_RX_CPU_ATTENTION_MASK 0x4000000u -#define GET_DEVICE3_RX_CPU_EVENT_RX_CPU_ATTENTION(__reg__) (((__reg__) & 0x4000000) >> 26u) -#define SET_DEVICE3_RX_CPU_EVENT_RX_CPU_ATTENTION(__val__) (((__val__) << 26u) & 0x4000000u) -#define DEVICE3_RX_CPU_EVENT_TIMER_SHIFT 29u -#define DEVICE3_RX_CPU_EVENT_TIMER_MASK 0x20000000u -#define GET_DEVICE3_RX_CPU_EVENT_TIMER(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_DEVICE3_RX_CPU_EVENT_TIMER(__val__) (((__val__) << 29u) & 0x20000000u) -#define DEVICE3_RX_CPU_EVENT_VPD_ATTENTION_SHIFT 30u -#define DEVICE3_RX_CPU_EVENT_VPD_ATTENTION_MASK 0x40000000u -#define GET_DEVICE3_RX_CPU_EVENT_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_DEVICE3_RX_CPU_EVENT_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) - #define REG_DEVICE3_6838 ((volatile APE_DEVICE3_H_uint32_t*)0xa0076838) /* Unknown. Used by PXE agent. */ #define REG_DEVICE3_MDI_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0076844) /* The register manual only mentions this in the changelog; it was removed from the manual in a previous revision. :| */ #define REG_DEVICE3_RX_CPU_EVENT_ENABLE ((volatile APE_DEVICE3_H_uint32_t*)0xa007684c) /* */ -#define DEVICE3_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_SHIFT 30u -#define DEVICE3_RX_CPU_EVENT_ENABLE_VPD_ATTENTION_MASK 0x40000000u -#define GET_DEVICE3_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_DEVICE3_RX_CPU_EVENT_ENABLE_VPD_ATTENTION(__val__) (((__val__) << 30u) & 0x40000000u) - #define REG_DEVICE3_FAST_BOOT_PROGRAM_COUNTER ((volatile APE_DEVICE3_H_uint32_t*)0xa0076894) /* */ -#define DEVICE3_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_SHIFT 0u -#define DEVICE3_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER_MASK 0x7fffffffu -#define GET_DEVICE3_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__reg__) (((__reg__) & 0x7fffffff) >> 0u) -#define SET_DEVICE3_FAST_BOOT_PROGRAM_COUNTER_PROGRAM_COUNTER(__val__) (((__val__) << 0u) & 0x7fffffffu) -#define DEVICE3_FAST_BOOT_PROGRAM_COUNTER_ENABLE_SHIFT 31u -#define DEVICE3_FAST_BOOT_PROGRAM_COUNTER_ENABLE_MASK 0x80000000u -#define GET_DEVICE3_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_DEVICE3_FAST_BOOT_PROGRAM_COUNTER_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_DEVICE3_EXPANSION_ROM_ADDR ((volatile APE_DEVICE3_H_uint32_t*)0xa00768ec) /* Expansion ROM base address, expect to be d- word aligned. */ #define REG_DEVICE3_68F0 ((volatile APE_DEVICE3_H_uint32_t*)0xa00768f0) /* */ #define REG_DEVICE3_EAV_REF_CLOCK_CONTROL ((volatile APE_DEVICE3_H_uint32_t*)0xa0076908) /* */ -#define DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SHIFT 16u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_MASK 0x30000u -#define GET_DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__reg__) (((__reg__) & 0x30000) >> 16u) -#define SET_DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING(__val__) (((__val__) << 16u) & 0x30000u) -#define DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_0_ 0x0u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_SNAP_SHOT_1_ 0x1u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_0_ 0x2u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_TIMESYNC_GPIO_MAPPING_TIME_WATCHDOG_1_ 0x3u - -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SHIFT 18u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_MASK 0x1c0000u -#define GET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__reg__) (((__reg__) & 0x1c0000) >> 18u) -#define SET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING(__val__) (((__val__) << 18u) & 0x1c0000u) -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_NOT_USED 0x0u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_0_ 0x4u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_SNAP_SHOT_1_ 0x5u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_0_ 0x6u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_0_MAPPING_TIME_WATCHDOG_1_ 0x7u - -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SHIFT 21u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_MASK 0xe00000u -#define GET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__reg__) (((__reg__) & 0xe00000) >> 21u) -#define SET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING(__val__) (((__val__) << 21u) & 0xe00000u) -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_NOT_USED 0x0u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_0_ 0x4u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_SNAP_SHOT_1_ 0x5u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_0_ 0x6u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_1_MAPPING_TIME_WATCHDOG_1_ 0x7u - -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SHIFT 24u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_MASK 0x7000000u -#define GET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__reg__) (((__reg__) & 0x7000000) >> 24u) -#define SET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING(__val__) (((__val__) << 24u) & 0x7000000u) -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_NOT_USED 0x0u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_0_ 0x4u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_SNAP_SHOT_1_ 0x5u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_0_ 0x6u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_2_MAPPING_TIME_WATCHDOG_1_ 0x7u - -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SHIFT 27u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_MASK 0x38000000u -#define GET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__reg__) (((__reg__) & 0x38000000) >> 27u) -#define SET_DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING(__val__) (((__val__) << 27u) & 0x38000000u) -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_NOT_USED 0x0u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_0_ 0x4u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_SNAP_SHOT_1_ 0x5u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_0_ 0x6u -#define DEVICE3_EAV_REF_CLOCK_CONTROL_APE_GPIO_3_MAPPING_TIME_WATCHDOG_1_ 0x7u - - #define REG_DEVICE3_7C04 ((volatile APE_DEVICE3_H_uint32_t*)0xa0077c04) /* PCIe-related. tg3 driver calls this */ /** @brief Device Registers, function 3 */ extern volatile DEVICE_t DEVICE3; diff --git a/include/APE_FILTERS1.h b/include/APE_FILTERS1.h index 9474688..dad4fdf 100644 --- a/include/APE_FILTERS1.h +++ b/include/APE_FILTERS1.h @@ -83,98 +83,9 @@ typedef uint32_t APE_FILTERS1_H_uint32_t; #define REG_FILTERS1_SIZE (sizeof(FILTERS_t)) #define REG_FILTERS1_ELEMENT_CONFIG ((volatile APE_FILTERS1_H_uint32_t*)0xa0058000) /* Element Configuration Register. */ -#define FILTERS1_ELEMENT_CONFIG_RULE_OFFSET_SHIFT 0u -#define FILTERS1_ELEMENT_CONFIG_RULE_OFFSET_MASK 0xffu -#define GET_FILTERS1_ELEMENT_CONFIG_RULE_OFFSET(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_FILTERS1_ELEMENT_CONFIG_RULE_OFFSET(__val__) (((__val__) << 0u) & 0xffu) -#define FILTERS1_ELEMENT_CONFIG_RULE_CLASS_SHIFT 8u -#define FILTERS1_ELEMENT_CONFIG_RULE_CLASS_MASK 0x1f00u -#define GET_FILTERS1_ELEMENT_CONFIG_RULE_CLASS(__reg__) (((__reg__) & 0x1f00) >> 8u) -#define SET_FILTERS1_ELEMENT_CONFIG_RULE_CLASS(__val__) (((__val__) << 8u) & 0x1f00u) -#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_SHIFT 13u -#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_MASK 0xe000u -#define GET_FILTERS1_ELEMENT_CONFIG_RULE_HEADER(__reg__) (((__reg__) & 0xe000) >> 13u) -#define SET_FILTERS1_ELEMENT_CONFIG_RULE_HEADER(__val__) (((__val__) << 13u) & 0xe000u) -#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_SOF 0x0u -#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_IP 0x1u -#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_TCP 0x2u -#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_UDP 0x3u -#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_DATA 0x4u -#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_ICMPV4 0x5u -#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_ICMPV6 0x6u -#define FILTERS1_ELEMENT_CONFIG_RULE_HEADER_VLAN 0x7u - -#define FILTERS1_ELEMENT_CONFIG_RULE_OP_SHIFT 16u -#define FILTERS1_ELEMENT_CONFIG_RULE_OP_MASK 0x30000u -#define GET_FILTERS1_ELEMENT_CONFIG_RULE_OP(__reg__) (((__reg__) & 0x30000) >> 16u) -#define SET_FILTERS1_ELEMENT_CONFIG_RULE_OP(__val__) (((__val__) << 16u) & 0x30000u) -#define FILTERS1_ELEMENT_CONFIG_RULE_OP_EQ 0x0u -#define FILTERS1_ELEMENT_CONFIG_RULE_OP_NE 0x1u -#define FILTERS1_ELEMENT_CONFIG_RULE_OP_GT 0x2u -#define FILTERS1_ELEMENT_CONFIG_RULE_OP_LT 0x3u - -#define FILTERS1_ELEMENT_CONFIG_RULE_MAP_SHIFT 24u -#define FILTERS1_ELEMENT_CONFIG_RULE_MAP_MASK 0x1000000u -#define GET_FILTERS1_ELEMENT_CONFIG_RULE_MAP(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_FILTERS1_ELEMENT_CONFIG_RULE_MAP(__val__) (((__val__) << 24u) & 0x1000000u) -#define FILTERS1_ELEMENT_CONFIG_RULE_DISCARD_SHIFT 25u -#define FILTERS1_ELEMENT_CONFIG_RULE_DISCARD_MASK 0x2000000u -#define GET_FILTERS1_ELEMENT_CONFIG_RULE_DISCARD(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_FILTERS1_ELEMENT_CONFIG_RULE_DISCARD(__val__) (((__val__) << 25u) & 0x2000000u) -#define FILTERS1_ELEMENT_CONFIG_RULE_MASK_SHIFT 26u -#define FILTERS1_ELEMENT_CONFIG_RULE_MASK_MASK 0x4000000u -#define GET_FILTERS1_ELEMENT_CONFIG_RULE_MASK(__reg__) (((__reg__) & 0x4000000) >> 26u) -#define SET_FILTERS1_ELEMENT_CONFIG_RULE_MASK(__val__) (((__val__) << 26u) & 0x4000000u) -#define FILTERS1_ELEMENT_CONFIG_RULE_P3_SHIFT 27u -#define FILTERS1_ELEMENT_CONFIG_RULE_P3_MASK 0x8000000u -#define GET_FILTERS1_ELEMENT_CONFIG_RULE_P3(__reg__) (((__reg__) & 0x8000000) >> 27u) -#define SET_FILTERS1_ELEMENT_CONFIG_RULE_P3(__val__) (((__val__) << 27u) & 0x8000000u) -#define FILTERS1_ELEMENT_CONFIG_RULE_P2_SHIFT 28u -#define FILTERS1_ELEMENT_CONFIG_RULE_P2_MASK 0x10000000u -#define GET_FILTERS1_ELEMENT_CONFIG_RULE_P2(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_FILTERS1_ELEMENT_CONFIG_RULE_P2(__val__) (((__val__) << 28u) & 0x10000000u) -#define FILTERS1_ELEMENT_CONFIG_RULE_P1_SHIFT 29u -#define FILTERS1_ELEMENT_CONFIG_RULE_P1_MASK 0x20000000u -#define GET_FILTERS1_ELEMENT_CONFIG_RULE_P1(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_FILTERS1_ELEMENT_CONFIG_RULE_P1(__val__) (((__val__) << 29u) & 0x20000000u) -#define FILTERS1_ELEMENT_CONFIG_RULE_AND_SHIFT 30u -#define FILTERS1_ELEMENT_CONFIG_RULE_AND_MASK 0x40000000u -#define GET_FILTERS1_ELEMENT_CONFIG_RULE_AND(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_FILTERS1_ELEMENT_CONFIG_RULE_AND(__val__) (((__val__) << 30u) & 0x40000000u) -#define FILTERS1_ELEMENT_CONFIG_RULE_ENABLE_SHIFT 31u -#define FILTERS1_ELEMENT_CONFIG_RULE_ENABLE_MASK 0x80000000u -#define GET_FILTERS1_ELEMENT_CONFIG_RULE_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_FILTERS1_ELEMENT_CONFIG_RULE_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_FILTERS1_ELEMENT_PATTERN ((volatile APE_FILTERS1_H_uint32_t*)0xa0058080) /* If RULE_MASK is set, low 16 bits are a bitmask and high 16 bits are the value masked by it. If it is not set, the entire field is a 32-bit match value. */ #define REG_FILTERS1_RULE_CONFIGURATION ((volatile APE_FILTERS1_H_uint32_t*)0xa0058100) /* */ -#define FILTERS1_RULE_CONFIGURATION_FILTER_SET_DISABLE_SHIFT 0u -#define FILTERS1_RULE_CONFIGURATION_FILTER_SET_DISABLE_MASK 0x1u -#define GET_FILTERS1_RULE_CONFIGURATION_FILTER_SET_DISABLE(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_FILTERS1_RULE_CONFIGURATION_FILTER_SET_DISABLE(__val__) (((__val__) << 0u) & 0x1u) -#define FILTERS1_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_SHIFT 31u -#define FILTERS1_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_MASK 0x80000000u -#define GET_FILTERS1_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_FILTERS1_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_FILTERS1_RULE_SET ((volatile APE_FILTERS1_H_uint32_t*)0xa0058104) /* */ -#define FILTERS1_RULE_SET_ACTION_SHIFT 0u -#define FILTERS1_RULE_SET_ACTION_MASK 0x3u -#define GET_FILTERS1_RULE_SET_ACTION(__reg__) (((__reg__) & 0x3) >> 0u) -#define SET_FILTERS1_RULE_SET_ACTION(__val__) (((__val__) << 0u) & 0x3u) -#define FILTERS1_RULE_SET_ACTION_TO_APE_ONLY 0x0u -#define FILTERS1_RULE_SET_ACTION_TO_APE_AND_HOST 0x1u -#define FILTERS1_RULE_SET_ACTION_DISCARD 0x2u - -#define FILTERS1_RULE_SET_COUNT_SHIFT 3u -#define FILTERS1_RULE_SET_COUNT_MASK 0x7fff8u -#define GET_FILTERS1_RULE_SET_COUNT(__reg__) (((__reg__) & 0x7fff8) >> 3u) -#define SET_FILTERS1_RULE_SET_COUNT(__val__) (((__val__) << 3u) & 0x7fff8u) -#define FILTERS1_RULE_SET_ENABLE_SHIFT 31u -#define FILTERS1_RULE_SET_ENABLE_MASK 0x80000000u -#define GET_FILTERS1_RULE_SET_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_FILTERS1_RULE_SET_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_FILTERS1_RULE_MASK ((volatile APE_FILTERS1_H_uint32_t*)0xa0058184) /* */ /** @brief Management Filter Registers, function 1 */ extern volatile FILTERS_t FILTERS1; diff --git a/include/APE_FILTERS2.h b/include/APE_FILTERS2.h index 934df47..6262da5 100644 --- a/include/APE_FILTERS2.h +++ b/include/APE_FILTERS2.h @@ -83,98 +83,9 @@ typedef uint32_t APE_FILTERS2_H_uint32_t; #define REG_FILTERS2_SIZE (sizeof(FILTERS_t)) #define REG_FILTERS2_ELEMENT_CONFIG ((volatile APE_FILTERS2_H_uint32_t*)0xa0068000) /* Element Configuration Register. */ -#define FILTERS2_ELEMENT_CONFIG_RULE_OFFSET_SHIFT 0u -#define FILTERS2_ELEMENT_CONFIG_RULE_OFFSET_MASK 0xffu -#define GET_FILTERS2_ELEMENT_CONFIG_RULE_OFFSET(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_FILTERS2_ELEMENT_CONFIG_RULE_OFFSET(__val__) (((__val__) << 0u) & 0xffu) -#define FILTERS2_ELEMENT_CONFIG_RULE_CLASS_SHIFT 8u -#define FILTERS2_ELEMENT_CONFIG_RULE_CLASS_MASK 0x1f00u -#define GET_FILTERS2_ELEMENT_CONFIG_RULE_CLASS(__reg__) (((__reg__) & 0x1f00) >> 8u) -#define SET_FILTERS2_ELEMENT_CONFIG_RULE_CLASS(__val__) (((__val__) << 8u) & 0x1f00u) -#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_SHIFT 13u -#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_MASK 0xe000u -#define GET_FILTERS2_ELEMENT_CONFIG_RULE_HEADER(__reg__) (((__reg__) & 0xe000) >> 13u) -#define SET_FILTERS2_ELEMENT_CONFIG_RULE_HEADER(__val__) (((__val__) << 13u) & 0xe000u) -#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_SOF 0x0u -#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_IP 0x1u -#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_TCP 0x2u -#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_UDP 0x3u -#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_DATA 0x4u -#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_ICMPV4 0x5u -#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_ICMPV6 0x6u -#define FILTERS2_ELEMENT_CONFIG_RULE_HEADER_VLAN 0x7u - -#define FILTERS2_ELEMENT_CONFIG_RULE_OP_SHIFT 16u -#define FILTERS2_ELEMENT_CONFIG_RULE_OP_MASK 0x30000u -#define GET_FILTERS2_ELEMENT_CONFIG_RULE_OP(__reg__) (((__reg__) & 0x30000) >> 16u) -#define SET_FILTERS2_ELEMENT_CONFIG_RULE_OP(__val__) (((__val__) << 16u) & 0x30000u) -#define FILTERS2_ELEMENT_CONFIG_RULE_OP_EQ 0x0u -#define FILTERS2_ELEMENT_CONFIG_RULE_OP_NE 0x1u -#define FILTERS2_ELEMENT_CONFIG_RULE_OP_GT 0x2u -#define FILTERS2_ELEMENT_CONFIG_RULE_OP_LT 0x3u - -#define FILTERS2_ELEMENT_CONFIG_RULE_MAP_SHIFT 24u -#define FILTERS2_ELEMENT_CONFIG_RULE_MAP_MASK 0x1000000u -#define GET_FILTERS2_ELEMENT_CONFIG_RULE_MAP(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_FILTERS2_ELEMENT_CONFIG_RULE_MAP(__val__) (((__val__) << 24u) & 0x1000000u) -#define FILTERS2_ELEMENT_CONFIG_RULE_DISCARD_SHIFT 25u -#define FILTERS2_ELEMENT_CONFIG_RULE_DISCARD_MASK 0x2000000u -#define GET_FILTERS2_ELEMENT_CONFIG_RULE_DISCARD(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_FILTERS2_ELEMENT_CONFIG_RULE_DISCARD(__val__) (((__val__) << 25u) & 0x2000000u) -#define FILTERS2_ELEMENT_CONFIG_RULE_MASK_SHIFT 26u -#define FILTERS2_ELEMENT_CONFIG_RULE_MASK_MASK 0x4000000u -#define GET_FILTERS2_ELEMENT_CONFIG_RULE_MASK(__reg__) (((__reg__) & 0x4000000) >> 26u) -#define SET_FILTERS2_ELEMENT_CONFIG_RULE_MASK(__val__) (((__val__) << 26u) & 0x4000000u) -#define FILTERS2_ELEMENT_CONFIG_RULE_P3_SHIFT 27u -#define FILTERS2_ELEMENT_CONFIG_RULE_P3_MASK 0x8000000u -#define GET_FILTERS2_ELEMENT_CONFIG_RULE_P3(__reg__) (((__reg__) & 0x8000000) >> 27u) -#define SET_FILTERS2_ELEMENT_CONFIG_RULE_P3(__val__) (((__val__) << 27u) & 0x8000000u) -#define FILTERS2_ELEMENT_CONFIG_RULE_P2_SHIFT 28u -#define FILTERS2_ELEMENT_CONFIG_RULE_P2_MASK 0x10000000u -#define GET_FILTERS2_ELEMENT_CONFIG_RULE_P2(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_FILTERS2_ELEMENT_CONFIG_RULE_P2(__val__) (((__val__) << 28u) & 0x10000000u) -#define FILTERS2_ELEMENT_CONFIG_RULE_P1_SHIFT 29u -#define FILTERS2_ELEMENT_CONFIG_RULE_P1_MASK 0x20000000u -#define GET_FILTERS2_ELEMENT_CONFIG_RULE_P1(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_FILTERS2_ELEMENT_CONFIG_RULE_P1(__val__) (((__val__) << 29u) & 0x20000000u) -#define FILTERS2_ELEMENT_CONFIG_RULE_AND_SHIFT 30u -#define FILTERS2_ELEMENT_CONFIG_RULE_AND_MASK 0x40000000u -#define GET_FILTERS2_ELEMENT_CONFIG_RULE_AND(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_FILTERS2_ELEMENT_CONFIG_RULE_AND(__val__) (((__val__) << 30u) & 0x40000000u) -#define FILTERS2_ELEMENT_CONFIG_RULE_ENABLE_SHIFT 31u -#define FILTERS2_ELEMENT_CONFIG_RULE_ENABLE_MASK 0x80000000u -#define GET_FILTERS2_ELEMENT_CONFIG_RULE_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_FILTERS2_ELEMENT_CONFIG_RULE_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_FILTERS2_ELEMENT_PATTERN ((volatile APE_FILTERS2_H_uint32_t*)0xa0068080) /* If RULE_MASK is set, low 16 bits are a bitmask and high 16 bits are the value masked by it. If it is not set, the entire field is a 32-bit match value. */ #define REG_FILTERS2_RULE_CONFIGURATION ((volatile APE_FILTERS2_H_uint32_t*)0xa0068100) /* */ -#define FILTERS2_RULE_CONFIGURATION_FILTER_SET_DISABLE_SHIFT 0u -#define FILTERS2_RULE_CONFIGURATION_FILTER_SET_DISABLE_MASK 0x1u -#define GET_FILTERS2_RULE_CONFIGURATION_FILTER_SET_DISABLE(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_FILTERS2_RULE_CONFIGURATION_FILTER_SET_DISABLE(__val__) (((__val__) << 0u) & 0x1u) -#define FILTERS2_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_SHIFT 31u -#define FILTERS2_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_MASK 0x80000000u -#define GET_FILTERS2_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_FILTERS2_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_FILTERS2_RULE_SET ((volatile APE_FILTERS2_H_uint32_t*)0xa0068104) /* */ -#define FILTERS2_RULE_SET_ACTION_SHIFT 0u -#define FILTERS2_RULE_SET_ACTION_MASK 0x3u -#define GET_FILTERS2_RULE_SET_ACTION(__reg__) (((__reg__) & 0x3) >> 0u) -#define SET_FILTERS2_RULE_SET_ACTION(__val__) (((__val__) << 0u) & 0x3u) -#define FILTERS2_RULE_SET_ACTION_TO_APE_ONLY 0x0u -#define FILTERS2_RULE_SET_ACTION_TO_APE_AND_HOST 0x1u -#define FILTERS2_RULE_SET_ACTION_DISCARD 0x2u - -#define FILTERS2_RULE_SET_COUNT_SHIFT 3u -#define FILTERS2_RULE_SET_COUNT_MASK 0x7fff8u -#define GET_FILTERS2_RULE_SET_COUNT(__reg__) (((__reg__) & 0x7fff8) >> 3u) -#define SET_FILTERS2_RULE_SET_COUNT(__val__) (((__val__) << 3u) & 0x7fff8u) -#define FILTERS2_RULE_SET_ENABLE_SHIFT 31u -#define FILTERS2_RULE_SET_ENABLE_MASK 0x80000000u -#define GET_FILTERS2_RULE_SET_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_FILTERS2_RULE_SET_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_FILTERS2_RULE_MASK ((volatile APE_FILTERS2_H_uint32_t*)0xa0068184) /* */ /** @brief Management Filter Registers, function 2 */ extern volatile FILTERS_t FILTERS2; diff --git a/include/APE_FILTERS3.h b/include/APE_FILTERS3.h index d01670d..9b235a9 100644 --- a/include/APE_FILTERS3.h +++ b/include/APE_FILTERS3.h @@ -83,98 +83,9 @@ typedef uint32_t APE_FILTERS3_H_uint32_t; #define REG_FILTERS3_SIZE (sizeof(FILTERS_t)) #define REG_FILTERS3_ELEMENT_CONFIG ((volatile APE_FILTERS3_H_uint32_t*)0xa0078000) /* Element Configuration Register. */ -#define FILTERS3_ELEMENT_CONFIG_RULE_OFFSET_SHIFT 0u -#define FILTERS3_ELEMENT_CONFIG_RULE_OFFSET_MASK 0xffu -#define GET_FILTERS3_ELEMENT_CONFIG_RULE_OFFSET(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_FILTERS3_ELEMENT_CONFIG_RULE_OFFSET(__val__) (((__val__) << 0u) & 0xffu) -#define FILTERS3_ELEMENT_CONFIG_RULE_CLASS_SHIFT 8u -#define FILTERS3_ELEMENT_CONFIG_RULE_CLASS_MASK 0x1f00u -#define GET_FILTERS3_ELEMENT_CONFIG_RULE_CLASS(__reg__) (((__reg__) & 0x1f00) >> 8u) -#define SET_FILTERS3_ELEMENT_CONFIG_RULE_CLASS(__val__) (((__val__) << 8u) & 0x1f00u) -#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_SHIFT 13u -#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_MASK 0xe000u -#define GET_FILTERS3_ELEMENT_CONFIG_RULE_HEADER(__reg__) (((__reg__) & 0xe000) >> 13u) -#define SET_FILTERS3_ELEMENT_CONFIG_RULE_HEADER(__val__) (((__val__) << 13u) & 0xe000u) -#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_SOF 0x0u -#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_IP 0x1u -#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_TCP 0x2u -#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_UDP 0x3u -#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_DATA 0x4u -#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_ICMPV4 0x5u -#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_ICMPV6 0x6u -#define FILTERS3_ELEMENT_CONFIG_RULE_HEADER_VLAN 0x7u - -#define FILTERS3_ELEMENT_CONFIG_RULE_OP_SHIFT 16u -#define FILTERS3_ELEMENT_CONFIG_RULE_OP_MASK 0x30000u -#define GET_FILTERS3_ELEMENT_CONFIG_RULE_OP(__reg__) (((__reg__) & 0x30000) >> 16u) -#define SET_FILTERS3_ELEMENT_CONFIG_RULE_OP(__val__) (((__val__) << 16u) & 0x30000u) -#define FILTERS3_ELEMENT_CONFIG_RULE_OP_EQ 0x0u -#define FILTERS3_ELEMENT_CONFIG_RULE_OP_NE 0x1u -#define FILTERS3_ELEMENT_CONFIG_RULE_OP_GT 0x2u -#define FILTERS3_ELEMENT_CONFIG_RULE_OP_LT 0x3u - -#define FILTERS3_ELEMENT_CONFIG_RULE_MAP_SHIFT 24u -#define FILTERS3_ELEMENT_CONFIG_RULE_MAP_MASK 0x1000000u -#define GET_FILTERS3_ELEMENT_CONFIG_RULE_MAP(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_FILTERS3_ELEMENT_CONFIG_RULE_MAP(__val__) (((__val__) << 24u) & 0x1000000u) -#define FILTERS3_ELEMENT_CONFIG_RULE_DISCARD_SHIFT 25u -#define FILTERS3_ELEMENT_CONFIG_RULE_DISCARD_MASK 0x2000000u -#define GET_FILTERS3_ELEMENT_CONFIG_RULE_DISCARD(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_FILTERS3_ELEMENT_CONFIG_RULE_DISCARD(__val__) (((__val__) << 25u) & 0x2000000u) -#define FILTERS3_ELEMENT_CONFIG_RULE_MASK_SHIFT 26u -#define FILTERS3_ELEMENT_CONFIG_RULE_MASK_MASK 0x4000000u -#define GET_FILTERS3_ELEMENT_CONFIG_RULE_MASK(__reg__) (((__reg__) & 0x4000000) >> 26u) -#define SET_FILTERS3_ELEMENT_CONFIG_RULE_MASK(__val__) (((__val__) << 26u) & 0x4000000u) -#define FILTERS3_ELEMENT_CONFIG_RULE_P3_SHIFT 27u -#define FILTERS3_ELEMENT_CONFIG_RULE_P3_MASK 0x8000000u -#define GET_FILTERS3_ELEMENT_CONFIG_RULE_P3(__reg__) (((__reg__) & 0x8000000) >> 27u) -#define SET_FILTERS3_ELEMENT_CONFIG_RULE_P3(__val__) (((__val__) << 27u) & 0x8000000u) -#define FILTERS3_ELEMENT_CONFIG_RULE_P2_SHIFT 28u -#define FILTERS3_ELEMENT_CONFIG_RULE_P2_MASK 0x10000000u -#define GET_FILTERS3_ELEMENT_CONFIG_RULE_P2(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_FILTERS3_ELEMENT_CONFIG_RULE_P2(__val__) (((__val__) << 28u) & 0x10000000u) -#define FILTERS3_ELEMENT_CONFIG_RULE_P1_SHIFT 29u -#define FILTERS3_ELEMENT_CONFIG_RULE_P1_MASK 0x20000000u -#define GET_FILTERS3_ELEMENT_CONFIG_RULE_P1(__reg__) (((__reg__) & 0x20000000) >> 29u) -#define SET_FILTERS3_ELEMENT_CONFIG_RULE_P1(__val__) (((__val__) << 29u) & 0x20000000u) -#define FILTERS3_ELEMENT_CONFIG_RULE_AND_SHIFT 30u -#define FILTERS3_ELEMENT_CONFIG_RULE_AND_MASK 0x40000000u -#define GET_FILTERS3_ELEMENT_CONFIG_RULE_AND(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_FILTERS3_ELEMENT_CONFIG_RULE_AND(__val__) (((__val__) << 30u) & 0x40000000u) -#define FILTERS3_ELEMENT_CONFIG_RULE_ENABLE_SHIFT 31u -#define FILTERS3_ELEMENT_CONFIG_RULE_ENABLE_MASK 0x80000000u -#define GET_FILTERS3_ELEMENT_CONFIG_RULE_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_FILTERS3_ELEMENT_CONFIG_RULE_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_FILTERS3_ELEMENT_PATTERN ((volatile APE_FILTERS3_H_uint32_t*)0xa0078080) /* If RULE_MASK is set, low 16 bits are a bitmask and high 16 bits are the value masked by it. If it is not set, the entire field is a 32-bit match value. */ #define REG_FILTERS3_RULE_CONFIGURATION ((volatile APE_FILTERS3_H_uint32_t*)0xa0078100) /* */ -#define FILTERS3_RULE_CONFIGURATION_FILTER_SET_DISABLE_SHIFT 0u -#define FILTERS3_RULE_CONFIGURATION_FILTER_SET_DISABLE_MASK 0x1u -#define GET_FILTERS3_RULE_CONFIGURATION_FILTER_SET_DISABLE(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_FILTERS3_RULE_CONFIGURATION_FILTER_SET_DISABLE(__val__) (((__val__) << 0u) & 0x1u) -#define FILTERS3_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_SHIFT 31u -#define FILTERS3_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE_MASK 0x80000000u -#define GET_FILTERS3_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_FILTERS3_RULE_CONFIGURATION_DIRECT_IP_FRAGMENT_TO_APE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_FILTERS3_RULE_SET ((volatile APE_FILTERS3_H_uint32_t*)0xa0078104) /* */ -#define FILTERS3_RULE_SET_ACTION_SHIFT 0u -#define FILTERS3_RULE_SET_ACTION_MASK 0x3u -#define GET_FILTERS3_RULE_SET_ACTION(__reg__) (((__reg__) & 0x3) >> 0u) -#define SET_FILTERS3_RULE_SET_ACTION(__val__) (((__val__) << 0u) & 0x3u) -#define FILTERS3_RULE_SET_ACTION_TO_APE_ONLY 0x0u -#define FILTERS3_RULE_SET_ACTION_TO_APE_AND_HOST 0x1u -#define FILTERS3_RULE_SET_ACTION_DISCARD 0x2u - -#define FILTERS3_RULE_SET_COUNT_SHIFT 3u -#define FILTERS3_RULE_SET_COUNT_MASK 0x7fff8u -#define GET_FILTERS3_RULE_SET_COUNT(__reg__) (((__reg__) & 0x7fff8) >> 3u) -#define SET_FILTERS3_RULE_SET_COUNT(__val__) (((__val__) << 3u) & 0x7fff8u) -#define FILTERS3_RULE_SET_ENABLE_SHIFT 31u -#define FILTERS3_RULE_SET_ENABLE_MASK 0x80000000u -#define GET_FILTERS3_RULE_SET_ENABLE(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_FILTERS3_RULE_SET_ENABLE(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_FILTERS3_RULE_MASK ((volatile APE_FILTERS3_H_uint32_t*)0xa0078184) /* */ /** @brief Management Filter Registers, function 3 */ extern volatile FILTERS_t FILTERS3; diff --git a/include/APE_RX_PORT.h b/include/APE_RX_PORT0.h index d0b2449..c62d065 100644 --- a/include/APE_RX_PORT.h +++ b/include/APE_RX_PORT0.h @@ -1,10 +1,10 @@ //////////////////////////////////////////////////////////////////////////////// /// -/// @file APE_RX_PORT.h +/// @file APE_RX_PORT0.h /// /// @project ape /// -/// @brief APE_RX_PORT +/// @brief APE_RX_PORT0 /// //////////////////////////////////////////////////////////////////////////////// /// @@ -42,26 +42,26 @@ /// @endcond //////////////////////////////////////////////////////////////////////////////// -/** @defgroup APE_RX_PORT_H APE_RX_PORT */ -/** @addtogroup APE_RX_PORT_H +/** @defgroup APE_RX_PORT0_H APE_RX_PORT0 */ +/** @addtogroup APE_RX_PORT0_H * @{ */ -#ifndef APE_RX_PORT_H -#define APE_RX_PORT_H +#ifndef APE_RX_PORT0_H +#define APE_RX_PORT0_H #include <stdint.h> #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ -void init_APE_RX_PORT_sim(void* base); -void init_APE_RX_PORT(void); +void init_APE_RX_PORT0_sim(void* base); +void init_APE_RX_PORT0(void); #include <CXXRegister.h> -typedef CXXRegister<uint8_t, 0, 8> APE_RX_PORT_H_uint8_t; -typedef CXXRegister<uint16_t, 0, 16> APE_RX_PORT_H_uint16_t; -typedef CXXRegister<uint32_t, 0, 32> APE_RX_PORT_H_uint32_t; -#define APE_RX_PORT_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> -#define APE_RX_PORT_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> -#define APE_RX_PORT_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +typedef CXXRegister<uint8_t, 0, 8> APE_RX_PORT0_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_RX_PORT0_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_RX_PORT0_H_uint32_t; +#define APE_RX_PORT0_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_RX_PORT0_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_RX_PORT0_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> #define register_container struct #define volatile #define BITFIELD_BEGIN(__type__, __name__) struct { @@ -69,23 +69,23 @@ typedef CXXRegister<uint32_t, 0, 32> APE_RX_PORT_H_uint32_t; #define BITFIELD_END(__type__, __name__) } __name__; #else /* Firmware Data types */ -typedef uint8_t APE_RX_PORT_H_uint8_t; -typedef uint16_t APE_RX_PORT_H_uint16_t; -typedef uint32_t APE_RX_PORT_H_uint32_t; +typedef uint8_t APE_RX_PORT0_H_uint8_t; +typedef uint16_t APE_RX_PORT0_H_uint16_t; +typedef uint32_t APE_RX_PORT0_H_uint32_t; #define register_container union #define BITFIELD_BEGIN(__type__, __name__) struct { #define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; #define BITFIELD_END(__type__, __name__) } __name__; #endif /* !CXX_SIMULATOR */ -#define REG_RX_PORT_BASE ((volatile void*)0xa0000000) /* RX from network port, function 0 */ -#define REG_RX_PORT_SIZE (sizeof(RX_PORT_t)) +#define REG_RX_PORT0_BASE ((volatile void*)0xa0000000) /* RX from network port, function 0 */ +#define REG_RX_PORT0_SIZE (sizeof(RX_PORT_t)) -#define REG_RX_PORT_IN ((volatile APE_RX_PORT_H_uint32_t*)0xa0000000) /* This is the memory range into which frames are directed towards the APE by the hardware. */ -#define RX_PORT_IN_ALL_SHIFT 0u -#define RX_PORT_IN_ALL_MASK 0xffffffffu -#define GET_RX_PORT_IN_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_RX_PORT_IN_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) +#define REG_RX_PORT0_IN ((volatile APE_RX_PORT0_H_uint32_t*)0xa0000000) /* This is the memory range into which frames are directed towards the APE by the hardware. */ +#define RX_PORT0_IN_ALL_SHIFT 0u +#define RX_PORT0_IN_ALL_MASK 0xffffffffu +#define GET_RX_PORT0_IN_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_RX_PORT0_IN_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) #define RX_PORT_IN_ALL_CONTROL_WORD 0x0u #define RX_PORT_IN_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u #define RX_PORT_IN_ALL_FIRST_PAYLOAD_WORD 0xcu @@ -96,19 +96,19 @@ typedef uint32_t APE_RX_PORT_H_uint32_t; /** @brief Register definition for @ref RX_PORT_t.In. */ typedef register_container RegRX_PORTIn_t { /** @brief 32bit direct register access. */ - APE_RX_PORT_H_uint32_t r32; + APE_RX_PORT0_H_uint32_t r32; - BITFIELD_BEGIN(APE_RX_PORT_H_uint32_t, bits) + BITFIELD_BEGIN(APE_RX_PORT0_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief All bits */ - BITFIELD_MEMBER(APE_RX_PORT_H_uint32_t, all, 0, 32) + BITFIELD_MEMBER(APE_RX_PORT0_H_uint32_t, all, 0, 32) #elif defined(__BIG_ENDIAN__) /** @brief All bits */ - BITFIELD_MEMBER(APE_RX_PORT_H_uint32_t, all, 0, 32) + BITFIELD_MEMBER(APE_RX_PORT0_H_uint32_t, all, 0, 32) #else #error Unknown Endian #endif - BITFIELD_END(APE_RX_PORT_H_uint32_t, bits) + BITFIELD_END(APE_RX_PORT0_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "In"; } @@ -131,7 +131,7 @@ typedef register_container RegRX_PORTIn_t { #endif /* CXX_SIMULATOR */ } RegRX_PORTIn_t; -/** @brief Component definition for @ref RX_PORT. */ +/** @brief Component definition for @ref RX_PORT0. */ typedef struct RX_PORT_t { /** @brief This is the memory range into which frames are directed towards the APE by the hardware. */ RegRX_PORTIn_t In[4096]; @@ -157,7 +157,7 @@ typedef struct RX_PORT_t { } RX_PORT_t; /** @brief RX from network port, function 0 */ -extern volatile RX_PORT_t RX_PORT; +extern volatile RX_PORT_t RX_PORT0; @@ -170,6 +170,6 @@ extern volatile RX_PORT_t RX_PORT; #undef BITFIELD_MEMBER #undef BITFIELD_END -#endif /* !APE_RX_PORT_H */ +#endif /* !APE_RX_PORT0_H */ /** @} */ diff --git a/include/APE_RX_PORT1.h b/include/APE_RX_PORT1.h index 15751c5..aaf57d6 100644 --- a/include/APE_RX_PORT1.h +++ b/include/APE_RX_PORT1.h @@ -50,7 +50,7 @@ #define APE_RX_PORT1_H #include <stdint.h> -#include "APE_RX_PORT.h" +#include "APE_RX_PORT0.h" #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ void init_APE_RX_PORT1_sim(void* base); @@ -83,17 +83,6 @@ typedef uint32_t APE_RX_PORT1_H_uint32_t; #define REG_RX_PORT1_SIZE (sizeof(RX_PORT_t)) #define REG_RX_PORT1_IN ((volatile APE_RX_PORT1_H_uint32_t*)0xa0004000) /* This is the memory range into which frames are directed towards the APE by the hardware. */ -#define RX_PORT1_IN_ALL_SHIFT 0u -#define RX_PORT1_IN_ALL_MASK 0xffffffffu -#define GET_RX_PORT1_IN_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_RX_PORT1_IN_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) -#define RX_PORT1_IN_ALL_CONTROL_WORD 0x0u -#define RX_PORT1_IN_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u -#define RX_PORT1_IN_ALL_FIRST_PAYLOAD_WORD 0xcu -#define RX_PORT1_IN_ALL_BLOCK_WORDS 0x20u -#define RX_PORT1_IN_ALL_BLOCK_BYTES 0x80u - - /** @brief RX from network port, function 1 */ extern volatile RX_PORT_t RX_PORT1; diff --git a/include/APE_RX_PORT2.h b/include/APE_RX_PORT2.h index 273f63a..9792fb3 100644 --- a/include/APE_RX_PORT2.h +++ b/include/APE_RX_PORT2.h @@ -50,7 +50,7 @@ #define APE_RX_PORT2_H #include <stdint.h> -#include "APE_RX_PORT.h" +#include "APE_RX_PORT0.h" #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ void init_APE_RX_PORT2_sim(void* base); @@ -83,17 +83,6 @@ typedef uint32_t APE_RX_PORT2_H_uint32_t; #define REG_RX_PORT2_SIZE (sizeof(RX_PORT_t)) #define REG_RX_PORT2_IN ((volatile APE_RX_PORT2_H_uint32_t*)0xa0008000) /* This is the memory range into which frames are directed towards the APE by the hardware. */ -#define RX_PORT2_IN_ALL_SHIFT 0u -#define RX_PORT2_IN_ALL_MASK 0xffffffffu -#define GET_RX_PORT2_IN_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_RX_PORT2_IN_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) -#define RX_PORT2_IN_ALL_CONTROL_WORD 0x0u -#define RX_PORT2_IN_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u -#define RX_PORT2_IN_ALL_FIRST_PAYLOAD_WORD 0xcu -#define RX_PORT2_IN_ALL_BLOCK_WORDS 0x20u -#define RX_PORT2_IN_ALL_BLOCK_BYTES 0x80u - - /** @brief RX from network port, function 2 */ extern volatile RX_PORT_t RX_PORT2; diff --git a/include/APE_RX_PORT3.h b/include/APE_RX_PORT3.h index 7a87e79..0f6fd81 100644 --- a/include/APE_RX_PORT3.h +++ b/include/APE_RX_PORT3.h @@ -50,7 +50,7 @@ #define APE_RX_PORT3_H #include <stdint.h> -#include "APE_RX_PORT.h" +#include "APE_RX_PORT0.h" #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ void init_APE_RX_PORT3_sim(void* base); @@ -83,17 +83,6 @@ typedef uint32_t APE_RX_PORT3_H_uint32_t; #define REG_RX_PORT3_SIZE (sizeof(RX_PORT_t)) #define REG_RX_PORT3_IN ((volatile APE_RX_PORT3_H_uint32_t*)0xa000c000) /* This is the memory range into which frames are directed towards the APE by the hardware. */ -#define RX_PORT3_IN_ALL_SHIFT 0u -#define RX_PORT3_IN_ALL_MASK 0xffffffffu -#define GET_RX_PORT3_IN_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_RX_PORT3_IN_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) -#define RX_PORT3_IN_ALL_CONTROL_WORD 0x0u -#define RX_PORT3_IN_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u -#define RX_PORT3_IN_ALL_FIRST_PAYLOAD_WORD 0xcu -#define RX_PORT3_IN_ALL_BLOCK_WORDS 0x20u -#define RX_PORT3_IN_ALL_BLOCK_BYTES 0x80u - - /** @brief RX from network port, function 3 */ extern volatile RX_PORT_t RX_PORT3; diff --git a/include/APE_SHM1.h b/include/APE_SHM1.h index 8a5b6b9..cd2f495 100644 --- a/include/APE_SHM1.h +++ b/include/APE_SHM1.h @@ -83,74 +83,19 @@ typedef uint32_t APE_SHM1_H_uint32_t; #define REG_SHM1_SIZE (sizeof(SHM_t)) #define REG_SHM1_SEG_SIG ((volatile APE_SHM1_H_uint32_t*)0x60221000) /* APE_APE_MAGIC ('APE!') when all is well. */ -#define SHM1_SEG_SIG_SIG_SHIFT 0u -#define SHM1_SEG_SIG_SIG_MASK 0xffffffffu -#define GET_SHM1_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_SHM1_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) -#define SHM1_SEG_SIG_SIG_LOADER 0x10ad10adu - - #define REG_SHM1_APE_SEG_LENGTH ((volatile APE_SHM1_H_uint32_t*)0x60221004) /* Set to 0x34. */ #define REG_SHM1_FW_STATUS ((volatile APE_SHM1_H_uint32_t*)0x6022100c) /* */ -#define SHM1_FW_STATUS_READY_SHIFT 8u -#define SHM1_FW_STATUS_READY_MASK 0x100u -#define GET_SHM1_FW_STATUS_READY(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM1_FW_STATUS_READY(__val__) (((__val__) << 8u) & 0x100u) -#define SHM1_FW_STATUS_UNKNOWN_31_28_SHIFT 28u -#define SHM1_FW_STATUS_UNKNOWN_31_28_MASK 0xf0000000u -#define GET_SHM1_FW_STATUS_UNKNOWN_31_28(__reg__) (((__reg__) & 0xf0000000) >> 28u) -#define SET_SHM1_FW_STATUS_UNKNOWN_31_28(__val__) (((__val__) << 28u) & 0xf0000000u) - #define REG_SHM1_FW_FEATURES ((volatile APE_SHM1_H_uint32_t*)0x60221010) /* */ -#define SHM1_FW_FEATURES_NCSI_SHIFT 1u -#define SHM1_FW_FEATURES_NCSI_MASK 0x2u -#define GET_SHM1_FW_FEATURES_NCSI(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM1_FW_FEATURES_NCSI(__val__) (((__val__) << 1u) & 0x2u) - #define REG_SHM1_4014 ((volatile APE_SHM1_H_uint32_t*)0x60221014) /* Unknown. */ #define REG_SHM1_FW_VERSION ((volatile APE_SHM1_H_uint32_t*)0x60221018) /* */ -#define SHM1_FW_VERSION_BUILD_SHIFT 0u -#define SHM1_FW_VERSION_BUILD_MASK 0xffu -#define GET_SHM1_FW_VERSION_BUILD(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_SHM1_FW_VERSION_BUILD(__val__) (((__val__) << 0u) & 0xffu) -#define SHM1_FW_VERSION_REVISION_SHIFT 8u -#define SHM1_FW_VERSION_REVISION_MASK 0xff00u -#define GET_SHM1_FW_VERSION_REVISION(__reg__) (((__reg__) & 0xff00) >> 8u) -#define SET_SHM1_FW_VERSION_REVISION(__val__) (((__val__) << 8u) & 0xff00u) -#define SHM1_FW_VERSION_MINOR_SHIFT 16u -#define SHM1_FW_VERSION_MINOR_MASK 0xff0000u -#define GET_SHM1_FW_VERSION_MINOR(__reg__) (((__reg__) & 0xff0000) >> 16u) -#define SET_SHM1_FW_VERSION_MINOR(__val__) (((__val__) << 16u) & 0xff0000u) -#define SHM1_FW_VERSION_MAJOR_SHIFT 24u -#define SHM1_FW_VERSION_MAJOR_MASK 0xff000000u -#define GET_SHM1_FW_VERSION_MAJOR(__reg__) (((__reg__) & 0xff000000) >> 24u) -#define SET_SHM1_FW_VERSION_MAJOR(__val__) (((__val__) << 24u) & 0xff000000u) - #define REG_SHM1_SEG_MESSAGE_BUFFER_OFFSET ((volatile APE_SHM1_H_uint32_t*)0x6022101c) /* Specifies the offset of a scratchpad area, relative to the start of the APE SHM area (i.e., relative to APE_REG(0x4000)). */ #define REG_SHM1_SEG_MESSAGE_BUFFER_LENGTH ((volatile APE_SHM1_H_uint32_t*)0x60221020) /* Specifies the size of the scratchpad area in bytes. */ #define REG_SHM1_4024 ((volatile APE_SHM1_H_uint32_t*)0x60221024) /* Unknown. Bootcode related. */ #define REG_SHM1_4028 ((volatile APE_SHM1_H_uint32_t*)0x60221028) /* Unknown. Bootcode related. */ #define REG_SHM1_LOADER_COMMAND ((volatile APE_SHM1_H_uint32_t*)0x60221038) /* Command sent when using the the APE loader. Zero once handled. */ -#define SHM1_LOADER_COMMAND_COMMAND_SHIFT 0u -#define SHM1_LOADER_COMMAND_COMMAND_MASK 0xffffffffu -#define GET_SHM1_LOADER_COMMAND_COMMAND(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_SHM1_LOADER_COMMAND_COMMAND(__val__) (((__val__) << 0u) & 0xffffffffu) -#define SHM1_LOADER_COMMAND_COMMAND_NOP 0x0u -#define SHM1_LOADER_COMMAND_COMMAND_READ_MEM 0x1u -#define SHM1_LOADER_COMMAND_COMMAND_WRITE_MEM 0x2u -#define SHM1_LOADER_COMMAND_COMMAND_CALL 0x3u - - #define REG_SHM1_LOADER_ARG0 ((volatile APE_SHM1_H_uint32_t*)0x6022103c) /* Argument 0 for the APE loader. */ #define REG_SHM1_LOADER_ARG1 ((volatile APE_SHM1_H_uint32_t*)0x60221040) /* Argument 1 for the APE loader. */ #define REG_SHM1_RCPU_SEG_SIG ((volatile APE_SHM1_H_uint32_t*)0x60221100) /* Set to APE_RCPU_MAGIC ('RCPU') by RX CPU. */ -#define SHM1_RCPU_SEG_SIG_SIG_SHIFT 0u -#define SHM1_RCPU_SEG_SIG_SIG_MASK 0xffffffffu -#define GET_SHM1_RCPU_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_SHM1_RCPU_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) -#define SHM1_RCPU_SEG_SIG_SIG_RCPU_MAGIC 0x52435055u - - #define REG_SHM1_RCPU_SEG_LENGTH ((volatile APE_SHM1_H_uint32_t*)0x60221104) /* Set to 0x34. */ #define REG_SHM1_RCPU_INIT_COUNT ((volatile APE_SHM1_H_uint32_t*)0x60221108) /* Incremented by RX CPU every boot. */ #define REG_SHM1_RCPU_FW_VERSION ((volatile APE_SHM1_H_uint32_t*)0x6022110c) /* Set to the bootcode version. e.g. 0x0127 -> v1.39. */ @@ -163,58 +108,16 @@ typedef uint32_t APE_SHM1_H_uint32_t; #define REG_SHM1_RCPU_CFG_HW ((volatile APE_SHM1_H_uint32_t*)0x60221128) /* Set from */ #define REG_SHM1_RCPU_CFG_HW_2 ((volatile APE_SHM1_H_uint32_t*)0x6022112c) /* Set from */ #define REG_SHM1_RCPU_CPMU_STATUS ((volatile APE_SHM1_H_uint32_t*)0x60221130) /* Set from */ -#define SHM1_RCPU_CPMU_STATUS_ADDRESS_SHIFT 0u -#define SHM1_RCPU_CPMU_STATUS_ADDRESS_MASK 0xffffu -#define GET_SHM1_RCPU_CPMU_STATUS_ADDRESS(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_SHM1_RCPU_CPMU_STATUS_ADDRESS(__val__) (((__val__) << 0u) & 0xffffu) -#define SHM1_RCPU_CPMU_STATUS_ADDRESS_ADDRESS 0x362cu - -#define SHM1_RCPU_CPMU_STATUS_STATUS_SHIFT 16u -#define SHM1_RCPU_CPMU_STATUS_STATUS_MASK 0xffff0000u -#define GET_SHM1_RCPU_CPMU_STATUS_STATUS(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_SHM1_RCPU_CPMU_STATUS_STATUS(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_SHM1_HOST_SEG_SIG ((volatile APE_SHM1_H_uint32_t*)0x60221200) /* Set to APE_HOST_MAGIC ('HOST') to indicate the section is valid. */ #define REG_SHM1_HOST_SEG_LEN ((volatile APE_SHM1_H_uint32_t*)0x60221204) /* Set to 0x20. */ #define REG_SHM1_HOST_INIT_COUNT ((volatile APE_SHM1_H_uint32_t*)0x60221208) /* Incremented by host on every initialization. */ #define REG_SHM1_HOST_DRIVER_ID ((volatile APE_SHM1_H_uint32_t*)0x6022120c) /* Linux sets this to 0xF0MM_mm00, where M is the major version of Linux and m is the minor version. */ #define REG_SHM1_HOST_BEHAVIOR ((volatile APE_SHM1_H_uint32_t*)0x60221210) /* */ -#define SHM1_HOST_BEHAVIOR_NO_PHYLOCK_SHIFT 0u -#define SHM1_HOST_BEHAVIOR_NO_PHYLOCK_MASK 0x1u -#define GET_SHM1_HOST_BEHAVIOR_NO_PHYLOCK(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM1_HOST_BEHAVIOR_NO_PHYLOCK(__val__) (((__val__) << 0u) & 0x1u) - #define REG_SHM1_HEARTBEAT_INTERVAL ((volatile APE_SHM1_H_uint32_t*)0x60221214) /* In milliseconds. Set to 0 to disable heartbeating. */ #define REG_SHM1_HEARTBEAT_COUNT ((volatile APE_SHM1_H_uint32_t*)0x60221218) /* */ #define REG_SHM1_HOST_DRIVER_STATE ((volatile APE_SHM1_H_uint32_t*)0x6022121c) /* */ #define REG_SHM1_WOL_SPEED ((volatile APE_SHM1_H_uint32_t*)0x60221224) /* */ #define REG_SHM1_EVENT_STATUS ((volatile APE_SHM1_H_uint32_t*)0x60221300) /* */ -#define SHM1_EVENT_STATUS_DRIVER_EVENT_SHIFT 4u -#define SHM1_EVENT_STATUS_DRIVER_EVENT_MASK 0x10u -#define GET_SHM1_EVENT_STATUS_DRIVER_EVENT(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM1_EVENT_STATUS_DRIVER_EVENT(__val__) (((__val__) << 4u) & 0x10u) -#define SHM1_EVENT_STATUS_COMMAND_SHIFT 8u -#define SHM1_EVENT_STATUS_COMMAND_MASK 0xff00u -#define GET_SHM1_EVENT_STATUS_COMMAND(__reg__) (((__reg__) & 0xff00) >> 8u) -#define SET_SHM1_EVENT_STATUS_COMMAND(__val__) (((__val__) << 8u) & 0xff00u) -#define SHM1_EVENT_STATUS_COMMAND_STATE_CHANGE 0x5u -#define SHM1_EVENT_STATUS_COMMAND_SCRATCHPAD_READ 0x16u -#define SHM1_EVENT_STATUS_COMMAND_SCRATCHPAD_WRITE 0x17u - -#define SHM1_EVENT_STATUS_STATE_SHIFT 16u -#define SHM1_EVENT_STATUS_STATE_MASK 0x70000u -#define GET_SHM1_EVENT_STATUS_STATE(__reg__) (((__reg__) & 0x70000) >> 16u) -#define SET_SHM1_EVENT_STATUS_STATE(__val__) (((__val__) << 16u) & 0x70000u) -#define SHM1_EVENT_STATUS_STATE_START 0x1u -#define SHM1_EVENT_STATUS_STATE_UNLOAD 0x2u -#define SHM1_EVENT_STATUS_STATE_WOL 0x3u -#define SHM1_EVENT_STATUS_STATE_SUSPEND 0x4u - -#define SHM1_EVENT_STATUS_PENDING_SHIFT 31u -#define SHM1_EVENT_STATUS_PENDING_MASK 0x80000000u -#define GET_SHM1_EVENT_STATUS_PENDING(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_SHM1_EVENT_STATUS_PENDING(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_SHM1_PROT_MAGIC ((volatile APE_SHM1_H_uint32_t*)0x60221308) /* This is set to APE_PROT_MAGIC ('PROT') on all functions. If it is 'PROT', the following fields (MAC0_HIGH/LOW) are valid */ #define REG_SHM1_PROT_MAC0_HIGH ((volatile APE_SHM1_H_uint32_t*)0x60221314) /* High 16 bits of MAC address 0. Only valid if */ #define REG_SHM1_PROT_MAC0_LOW ((volatile APE_SHM1_H_uint32_t*)0x60221318) /* Low 16 bits of MAC address 0. */ diff --git a/include/APE_SHM2.h b/include/APE_SHM2.h index 313582a..bd92e45 100644 --- a/include/APE_SHM2.h +++ b/include/APE_SHM2.h @@ -83,74 +83,19 @@ typedef uint32_t APE_SHM2_H_uint32_t; #define REG_SHM2_SIZE (sizeof(SHM_t)) #define REG_SHM2_SEG_SIG ((volatile APE_SHM2_H_uint32_t*)0x60222000) /* APE_APE_MAGIC ('APE!') when all is well. */ -#define SHM2_SEG_SIG_SIG_SHIFT 0u -#define SHM2_SEG_SIG_SIG_MASK 0xffffffffu -#define GET_SHM2_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_SHM2_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) -#define SHM2_SEG_SIG_SIG_LOADER 0x10ad10adu - - #define REG_SHM2_APE_SEG_LENGTH ((volatile APE_SHM2_H_uint32_t*)0x60222004) /* Set to 0x34. */ #define REG_SHM2_FW_STATUS ((volatile APE_SHM2_H_uint32_t*)0x6022200c) /* */ -#define SHM2_FW_STATUS_READY_SHIFT 8u -#define SHM2_FW_STATUS_READY_MASK 0x100u -#define GET_SHM2_FW_STATUS_READY(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM2_FW_STATUS_READY(__val__) (((__val__) << 8u) & 0x100u) -#define SHM2_FW_STATUS_UNKNOWN_31_28_SHIFT 28u -#define SHM2_FW_STATUS_UNKNOWN_31_28_MASK 0xf0000000u -#define GET_SHM2_FW_STATUS_UNKNOWN_31_28(__reg__) (((__reg__) & 0xf0000000) >> 28u) -#define SET_SHM2_FW_STATUS_UNKNOWN_31_28(__val__) (((__val__) << 28u) & 0xf0000000u) - #define REG_SHM2_FW_FEATURES ((volatile APE_SHM2_H_uint32_t*)0x60222010) /* */ -#define SHM2_FW_FEATURES_NCSI_SHIFT 1u -#define SHM2_FW_FEATURES_NCSI_MASK 0x2u -#define GET_SHM2_FW_FEATURES_NCSI(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM2_FW_FEATURES_NCSI(__val__) (((__val__) << 1u) & 0x2u) - #define REG_SHM2_4014 ((volatile APE_SHM2_H_uint32_t*)0x60222014) /* Unknown. */ #define REG_SHM2_FW_VERSION ((volatile APE_SHM2_H_uint32_t*)0x60222018) /* */ -#define SHM2_FW_VERSION_BUILD_SHIFT 0u -#define SHM2_FW_VERSION_BUILD_MASK 0xffu -#define GET_SHM2_FW_VERSION_BUILD(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_SHM2_FW_VERSION_BUILD(__val__) (((__val__) << 0u) & 0xffu) -#define SHM2_FW_VERSION_REVISION_SHIFT 8u -#define SHM2_FW_VERSION_REVISION_MASK 0xff00u -#define GET_SHM2_FW_VERSION_REVISION(__reg__) (((__reg__) & 0xff00) >> 8u) -#define SET_SHM2_FW_VERSION_REVISION(__val__) (((__val__) << 8u) & 0xff00u) -#define SHM2_FW_VERSION_MINOR_SHIFT 16u -#define SHM2_FW_VERSION_MINOR_MASK 0xff0000u -#define GET_SHM2_FW_VERSION_MINOR(__reg__) (((__reg__) & 0xff0000) >> 16u) -#define SET_SHM2_FW_VERSION_MINOR(__val__) (((__val__) << 16u) & 0xff0000u) -#define SHM2_FW_VERSION_MAJOR_SHIFT 24u -#define SHM2_FW_VERSION_MAJOR_MASK 0xff000000u -#define GET_SHM2_FW_VERSION_MAJOR(__reg__) (((__reg__) & 0xff000000) >> 24u) -#define SET_SHM2_FW_VERSION_MAJOR(__val__) (((__val__) << 24u) & 0xff000000u) - #define REG_SHM2_SEG_MESSAGE_BUFFER_OFFSET ((volatile APE_SHM2_H_uint32_t*)0x6022201c) /* Specifies the offset of a scratchpad area, relative to the start of the APE SHM area (i.e., relative to APE_REG(0x4000)). */ #define REG_SHM2_SEG_MESSAGE_BUFFER_LENGTH ((volatile APE_SHM2_H_uint32_t*)0x60222020) /* Specifies the size of the scratchpad area in bytes. */ #define REG_SHM2_4024 ((volatile APE_SHM2_H_uint32_t*)0x60222024) /* Unknown. Bootcode related. */ #define REG_SHM2_4028 ((volatile APE_SHM2_H_uint32_t*)0x60222028) /* Unknown. Bootcode related. */ #define REG_SHM2_LOADER_COMMAND ((volatile APE_SHM2_H_uint32_t*)0x60222038) /* Command sent when using the the APE loader. Zero once handled. */ -#define SHM2_LOADER_COMMAND_COMMAND_SHIFT 0u -#define SHM2_LOADER_COMMAND_COMMAND_MASK 0xffffffffu -#define GET_SHM2_LOADER_COMMAND_COMMAND(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_SHM2_LOADER_COMMAND_COMMAND(__val__) (((__val__) << 0u) & 0xffffffffu) -#define SHM2_LOADER_COMMAND_COMMAND_NOP 0x0u -#define SHM2_LOADER_COMMAND_COMMAND_READ_MEM 0x1u -#define SHM2_LOADER_COMMAND_COMMAND_WRITE_MEM 0x2u -#define SHM2_LOADER_COMMAND_COMMAND_CALL 0x3u - - #define REG_SHM2_LOADER_ARG0 ((volatile APE_SHM2_H_uint32_t*)0x6022203c) /* Argument 0 for the APE loader. */ #define REG_SHM2_LOADER_ARG1 ((volatile APE_SHM2_H_uint32_t*)0x60222040) /* Argument 1 for the APE loader. */ #define REG_SHM2_RCPU_SEG_SIG ((volatile APE_SHM2_H_uint32_t*)0x60222100) /* Set to APE_RCPU_MAGIC ('RCPU') by RX CPU. */ -#define SHM2_RCPU_SEG_SIG_SIG_SHIFT 0u -#define SHM2_RCPU_SEG_SIG_SIG_MASK 0xffffffffu -#define GET_SHM2_RCPU_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_SHM2_RCPU_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) -#define SHM2_RCPU_SEG_SIG_SIG_RCPU_MAGIC 0x52435055u - - #define REG_SHM2_RCPU_SEG_LENGTH ((volatile APE_SHM2_H_uint32_t*)0x60222104) /* Set to 0x34. */ #define REG_SHM2_RCPU_INIT_COUNT ((volatile APE_SHM2_H_uint32_t*)0x60222108) /* Incremented by RX CPU every boot. */ #define REG_SHM2_RCPU_FW_VERSION ((volatile APE_SHM2_H_uint32_t*)0x6022210c) /* Set to the bootcode version. e.g. 0x0127 -> v1.39. */ @@ -163,58 +108,16 @@ typedef uint32_t APE_SHM2_H_uint32_t; #define REG_SHM2_RCPU_CFG_HW ((volatile APE_SHM2_H_uint32_t*)0x60222128) /* Set from */ #define REG_SHM2_RCPU_CFG_HW_2 ((volatile APE_SHM2_H_uint32_t*)0x6022212c) /* Set from */ #define REG_SHM2_RCPU_CPMU_STATUS ((volatile APE_SHM2_H_uint32_t*)0x60222130) /* Set from */ -#define SHM2_RCPU_CPMU_STATUS_ADDRESS_SHIFT 0u -#define SHM2_RCPU_CPMU_STATUS_ADDRESS_MASK 0xffffu -#define GET_SHM2_RCPU_CPMU_STATUS_ADDRESS(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_SHM2_RCPU_CPMU_STATUS_ADDRESS(__val__) (((__val__) << 0u) & 0xffffu) -#define SHM2_RCPU_CPMU_STATUS_ADDRESS_ADDRESS 0x362cu - -#define SHM2_RCPU_CPMU_STATUS_STATUS_SHIFT 16u -#define SHM2_RCPU_CPMU_STATUS_STATUS_MASK 0xffff0000u -#define GET_SHM2_RCPU_CPMU_STATUS_STATUS(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_SHM2_RCPU_CPMU_STATUS_STATUS(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_SHM2_HOST_SEG_SIG ((volatile APE_SHM2_H_uint32_t*)0x60222200) /* Set to APE_HOST_MAGIC ('HOST') to indicate the section is valid. */ #define REG_SHM2_HOST_SEG_LEN ((volatile APE_SHM2_H_uint32_t*)0x60222204) /* Set to 0x20. */ #define REG_SHM2_HOST_INIT_COUNT ((volatile APE_SHM2_H_uint32_t*)0x60222208) /* Incremented by host on every initialization. */ #define REG_SHM2_HOST_DRIVER_ID ((volatile APE_SHM2_H_uint32_t*)0x6022220c) /* Linux sets this to 0xF0MM_mm00, where M is the major version of Linux and m is the minor version. */ #define REG_SHM2_HOST_BEHAVIOR ((volatile APE_SHM2_H_uint32_t*)0x60222210) /* */ -#define SHM2_HOST_BEHAVIOR_NO_PHYLOCK_SHIFT 0u -#define SHM2_HOST_BEHAVIOR_NO_PHYLOCK_MASK 0x1u -#define GET_SHM2_HOST_BEHAVIOR_NO_PHYLOCK(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM2_HOST_BEHAVIOR_NO_PHYLOCK(__val__) (((__val__) << 0u) & 0x1u) - #define REG_SHM2_HEARTBEAT_INTERVAL ((volatile APE_SHM2_H_uint32_t*)0x60222214) /* In milliseconds. Set to 0 to disable heartbeating. */ #define REG_SHM2_HEARTBEAT_COUNT ((volatile APE_SHM2_H_uint32_t*)0x60222218) /* */ #define REG_SHM2_HOST_DRIVER_STATE ((volatile APE_SHM2_H_uint32_t*)0x6022221c) /* */ #define REG_SHM2_WOL_SPEED ((volatile APE_SHM2_H_uint32_t*)0x60222224) /* */ #define REG_SHM2_EVENT_STATUS ((volatile APE_SHM2_H_uint32_t*)0x60222300) /* */ -#define SHM2_EVENT_STATUS_DRIVER_EVENT_SHIFT 4u -#define SHM2_EVENT_STATUS_DRIVER_EVENT_MASK 0x10u -#define GET_SHM2_EVENT_STATUS_DRIVER_EVENT(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM2_EVENT_STATUS_DRIVER_EVENT(__val__) (((__val__) << 4u) & 0x10u) -#define SHM2_EVENT_STATUS_COMMAND_SHIFT 8u -#define SHM2_EVENT_STATUS_COMMAND_MASK 0xff00u -#define GET_SHM2_EVENT_STATUS_COMMAND(__reg__) (((__reg__) & 0xff00) >> 8u) -#define SET_SHM2_EVENT_STATUS_COMMAND(__val__) (((__val__) << 8u) & 0xff00u) -#define SHM2_EVENT_STATUS_COMMAND_STATE_CHANGE 0x5u -#define SHM2_EVENT_STATUS_COMMAND_SCRATCHPAD_READ 0x16u -#define SHM2_EVENT_STATUS_COMMAND_SCRATCHPAD_WRITE 0x17u - -#define SHM2_EVENT_STATUS_STATE_SHIFT 16u -#define SHM2_EVENT_STATUS_STATE_MASK 0x70000u -#define GET_SHM2_EVENT_STATUS_STATE(__reg__) (((__reg__) & 0x70000) >> 16u) -#define SET_SHM2_EVENT_STATUS_STATE(__val__) (((__val__) << 16u) & 0x70000u) -#define SHM2_EVENT_STATUS_STATE_START 0x1u -#define SHM2_EVENT_STATUS_STATE_UNLOAD 0x2u -#define SHM2_EVENT_STATUS_STATE_WOL 0x3u -#define SHM2_EVENT_STATUS_STATE_SUSPEND 0x4u - -#define SHM2_EVENT_STATUS_PENDING_SHIFT 31u -#define SHM2_EVENT_STATUS_PENDING_MASK 0x80000000u -#define GET_SHM2_EVENT_STATUS_PENDING(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_SHM2_EVENT_STATUS_PENDING(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_SHM2_PROT_MAGIC ((volatile APE_SHM2_H_uint32_t*)0x60222308) /* This is set to APE_PROT_MAGIC ('PROT') on all functions. If it is 'PROT', the following fields (MAC0_HIGH/LOW) are valid */ #define REG_SHM2_PROT_MAC0_HIGH ((volatile APE_SHM2_H_uint32_t*)0x60222314) /* High 16 bits of MAC address 0. Only valid if */ #define REG_SHM2_PROT_MAC0_LOW ((volatile APE_SHM2_H_uint32_t*)0x60222318) /* Low 16 bits of MAC address 0. */ diff --git a/include/APE_SHM3.h b/include/APE_SHM3.h index 914c1ad..d3deb09 100644 --- a/include/APE_SHM3.h +++ b/include/APE_SHM3.h @@ -83,74 +83,19 @@ typedef uint32_t APE_SHM3_H_uint32_t; #define REG_SHM3_SIZE (sizeof(SHM_t)) #define REG_SHM3_SEG_SIG ((volatile APE_SHM3_H_uint32_t*)0x60223000) /* APE_APE_MAGIC ('APE!') when all is well. */ -#define SHM3_SEG_SIG_SIG_SHIFT 0u -#define SHM3_SEG_SIG_SIG_MASK 0xffffffffu -#define GET_SHM3_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_SHM3_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) -#define SHM3_SEG_SIG_SIG_LOADER 0x10ad10adu - - #define REG_SHM3_APE_SEG_LENGTH ((volatile APE_SHM3_H_uint32_t*)0x60223004) /* Set to 0x34. */ #define REG_SHM3_FW_STATUS ((volatile APE_SHM3_H_uint32_t*)0x6022300c) /* */ -#define SHM3_FW_STATUS_READY_SHIFT 8u -#define SHM3_FW_STATUS_READY_MASK 0x100u -#define GET_SHM3_FW_STATUS_READY(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM3_FW_STATUS_READY(__val__) (((__val__) << 8u) & 0x100u) -#define SHM3_FW_STATUS_UNKNOWN_31_28_SHIFT 28u -#define SHM3_FW_STATUS_UNKNOWN_31_28_MASK 0xf0000000u -#define GET_SHM3_FW_STATUS_UNKNOWN_31_28(__reg__) (((__reg__) & 0xf0000000) >> 28u) -#define SET_SHM3_FW_STATUS_UNKNOWN_31_28(__val__) (((__val__) << 28u) & 0xf0000000u) - #define REG_SHM3_FW_FEATURES ((volatile APE_SHM3_H_uint32_t*)0x60223010) /* */ -#define SHM3_FW_FEATURES_NCSI_SHIFT 1u -#define SHM3_FW_FEATURES_NCSI_MASK 0x2u -#define GET_SHM3_FW_FEATURES_NCSI(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM3_FW_FEATURES_NCSI(__val__) (((__val__) << 1u) & 0x2u) - #define REG_SHM3_4014 ((volatile APE_SHM3_H_uint32_t*)0x60223014) /* Unknown. */ #define REG_SHM3_FW_VERSION ((volatile APE_SHM3_H_uint32_t*)0x60223018) /* */ -#define SHM3_FW_VERSION_BUILD_SHIFT 0u -#define SHM3_FW_VERSION_BUILD_MASK 0xffu -#define GET_SHM3_FW_VERSION_BUILD(__reg__) (((__reg__) & 0xff) >> 0u) -#define SET_SHM3_FW_VERSION_BUILD(__val__) (((__val__) << 0u) & 0xffu) -#define SHM3_FW_VERSION_REVISION_SHIFT 8u -#define SHM3_FW_VERSION_REVISION_MASK 0xff00u -#define GET_SHM3_FW_VERSION_REVISION(__reg__) (((__reg__) & 0xff00) >> 8u) -#define SET_SHM3_FW_VERSION_REVISION(__val__) (((__val__) << 8u) & 0xff00u) -#define SHM3_FW_VERSION_MINOR_SHIFT 16u -#define SHM3_FW_VERSION_MINOR_MASK 0xff0000u -#define GET_SHM3_FW_VERSION_MINOR(__reg__) (((__reg__) & 0xff0000) >> 16u) -#define SET_SHM3_FW_VERSION_MINOR(__val__) (((__val__) << 16u) & 0xff0000u) -#define SHM3_FW_VERSION_MAJOR_SHIFT 24u -#define SHM3_FW_VERSION_MAJOR_MASK 0xff000000u -#define GET_SHM3_FW_VERSION_MAJOR(__reg__) (((__reg__) & 0xff000000) >> 24u) -#define SET_SHM3_FW_VERSION_MAJOR(__val__) (((__val__) << 24u) & 0xff000000u) - #define REG_SHM3_SEG_MESSAGE_BUFFER_OFFSET ((volatile APE_SHM3_H_uint32_t*)0x6022301c) /* Specifies the offset of a scratchpad area, relative to the start of the APE SHM area (i.e., relative to APE_REG(0x4000)). */ #define REG_SHM3_SEG_MESSAGE_BUFFER_LENGTH ((volatile APE_SHM3_H_uint32_t*)0x60223020) /* Specifies the size of the scratchpad area in bytes. */ #define REG_SHM3_4024 ((volatile APE_SHM3_H_uint32_t*)0x60223024) /* Unknown. Bootcode related. */ #define REG_SHM3_4028 ((volatile APE_SHM3_H_uint32_t*)0x60223028) /* Unknown. Bootcode related. */ #define REG_SHM3_LOADER_COMMAND ((volatile APE_SHM3_H_uint32_t*)0x60223038) /* Command sent when using the the APE loader. Zero once handled. */ -#define SHM3_LOADER_COMMAND_COMMAND_SHIFT 0u -#define SHM3_LOADER_COMMAND_COMMAND_MASK 0xffffffffu -#define GET_SHM3_LOADER_COMMAND_COMMAND(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_SHM3_LOADER_COMMAND_COMMAND(__val__) (((__val__) << 0u) & 0xffffffffu) -#define SHM3_LOADER_COMMAND_COMMAND_NOP 0x0u -#define SHM3_LOADER_COMMAND_COMMAND_READ_MEM 0x1u -#define SHM3_LOADER_COMMAND_COMMAND_WRITE_MEM 0x2u -#define SHM3_LOADER_COMMAND_COMMAND_CALL 0x3u - - #define REG_SHM3_LOADER_ARG0 ((volatile APE_SHM3_H_uint32_t*)0x6022303c) /* Argument 0 for the APE loader. */ #define REG_SHM3_LOADER_ARG1 ((volatile APE_SHM3_H_uint32_t*)0x60223040) /* Argument 1 for the APE loader. */ #define REG_SHM3_RCPU_SEG_SIG ((volatile APE_SHM3_H_uint32_t*)0x60223100) /* Set to APE_RCPU_MAGIC ('RCPU') by RX CPU. */ -#define SHM3_RCPU_SEG_SIG_SIG_SHIFT 0u -#define SHM3_RCPU_SEG_SIG_SIG_MASK 0xffffffffu -#define GET_SHM3_RCPU_SEG_SIG_SIG(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_SHM3_RCPU_SEG_SIG_SIG(__val__) (((__val__) << 0u) & 0xffffffffu) -#define SHM3_RCPU_SEG_SIG_SIG_RCPU_MAGIC 0x52435055u - - #define REG_SHM3_RCPU_SEG_LENGTH ((volatile APE_SHM3_H_uint32_t*)0x60223104) /* Set to 0x34. */ #define REG_SHM3_RCPU_INIT_COUNT ((volatile APE_SHM3_H_uint32_t*)0x60223108) /* Incremented by RX CPU every boot. */ #define REG_SHM3_RCPU_FW_VERSION ((volatile APE_SHM3_H_uint32_t*)0x6022310c) /* Set to the bootcode version. e.g. 0x0127 -> v1.39. */ @@ -163,58 +108,16 @@ typedef uint32_t APE_SHM3_H_uint32_t; #define REG_SHM3_RCPU_CFG_HW ((volatile APE_SHM3_H_uint32_t*)0x60223128) /* Set from */ #define REG_SHM3_RCPU_CFG_HW_2 ((volatile APE_SHM3_H_uint32_t*)0x6022312c) /* Set from */ #define REG_SHM3_RCPU_CPMU_STATUS ((volatile APE_SHM3_H_uint32_t*)0x60223130) /* Set from */ -#define SHM3_RCPU_CPMU_STATUS_ADDRESS_SHIFT 0u -#define SHM3_RCPU_CPMU_STATUS_ADDRESS_MASK 0xffffu -#define GET_SHM3_RCPU_CPMU_STATUS_ADDRESS(__reg__) (((__reg__) & 0xffff) >> 0u) -#define SET_SHM3_RCPU_CPMU_STATUS_ADDRESS(__val__) (((__val__) << 0u) & 0xffffu) -#define SHM3_RCPU_CPMU_STATUS_ADDRESS_ADDRESS 0x362cu - -#define SHM3_RCPU_CPMU_STATUS_STATUS_SHIFT 16u -#define SHM3_RCPU_CPMU_STATUS_STATUS_MASK 0xffff0000u -#define GET_SHM3_RCPU_CPMU_STATUS_STATUS(__reg__) (((__reg__) & 0xffff0000) >> 16u) -#define SET_SHM3_RCPU_CPMU_STATUS_STATUS(__val__) (((__val__) << 16u) & 0xffff0000u) - #define REG_SHM3_HOST_SEG_SIG ((volatile APE_SHM3_H_uint32_t*)0x60223200) /* Set to APE_HOST_MAGIC ('HOST') to indicate the section is valid. */ #define REG_SHM3_HOST_SEG_LEN ((volatile APE_SHM3_H_uint32_t*)0x60223204) /* Set to 0x20. */ #define REG_SHM3_HOST_INIT_COUNT ((volatile APE_SHM3_H_uint32_t*)0x60223208) /* Incremented by host on every initialization. */ #define REG_SHM3_HOST_DRIVER_ID ((volatile APE_SHM3_H_uint32_t*)0x6022320c) /* Linux sets this to 0xF0MM_mm00, where M is the major version of Linux and m is the minor version. */ #define REG_SHM3_HOST_BEHAVIOR ((volatile APE_SHM3_H_uint32_t*)0x60223210) /* */ -#define SHM3_HOST_BEHAVIOR_NO_PHYLOCK_SHIFT 0u -#define SHM3_HOST_BEHAVIOR_NO_PHYLOCK_MASK 0x1u -#define GET_SHM3_HOST_BEHAVIOR_NO_PHYLOCK(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM3_HOST_BEHAVIOR_NO_PHYLOCK(__val__) (((__val__) << 0u) & 0x1u) - #define REG_SHM3_HEARTBEAT_INTERVAL ((volatile APE_SHM3_H_uint32_t*)0x60223214) /* In milliseconds. Set to 0 to disable heartbeating. */ #define REG_SHM3_HEARTBEAT_COUNT ((volatile APE_SHM3_H_uint32_t*)0x60223218) /* */ #define REG_SHM3_HOST_DRIVER_STATE ((volatile APE_SHM3_H_uint32_t*)0x6022321c) /* */ #define REG_SHM3_WOL_SPEED ((volatile APE_SHM3_H_uint32_t*)0x60223224) /* */ #define REG_SHM3_EVENT_STATUS ((volatile APE_SHM3_H_uint32_t*)0x60223300) /* */ -#define SHM3_EVENT_STATUS_DRIVER_EVENT_SHIFT 4u -#define SHM3_EVENT_STATUS_DRIVER_EVENT_MASK 0x10u -#define GET_SHM3_EVENT_STATUS_DRIVER_EVENT(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM3_EVENT_STATUS_DRIVER_EVENT(__val__) (((__val__) << 4u) & 0x10u) -#define SHM3_EVENT_STATUS_COMMAND_SHIFT 8u -#define SHM3_EVENT_STATUS_COMMAND_MASK 0xff00u -#define GET_SHM3_EVENT_STATUS_COMMAND(__reg__) (((__reg__) & 0xff00) >> 8u) -#define SET_SHM3_EVENT_STATUS_COMMAND(__val__) (((__val__) << 8u) & 0xff00u) -#define SHM3_EVENT_STATUS_COMMAND_STATE_CHANGE 0x5u -#define SHM3_EVENT_STATUS_COMMAND_SCRATCHPAD_READ 0x16u -#define SHM3_EVENT_STATUS_COMMAND_SCRATCHPAD_WRITE 0x17u - -#define SHM3_EVENT_STATUS_STATE_SHIFT 16u -#define SHM3_EVENT_STATUS_STATE_MASK 0x70000u -#define GET_SHM3_EVENT_STATUS_STATE(__reg__) (((__reg__) & 0x70000) >> 16u) -#define SET_SHM3_EVENT_STATUS_STATE(__val__) (((__val__) << 16u) & 0x70000u) -#define SHM3_EVENT_STATUS_STATE_START 0x1u -#define SHM3_EVENT_STATUS_STATE_UNLOAD 0x2u -#define SHM3_EVENT_STATUS_STATE_WOL 0x3u -#define SHM3_EVENT_STATUS_STATE_SUSPEND 0x4u - -#define SHM3_EVENT_STATUS_PENDING_SHIFT 31u -#define SHM3_EVENT_STATUS_PENDING_MASK 0x80000000u -#define GET_SHM3_EVENT_STATUS_PENDING(__reg__) (((__reg__) & 0x80000000) >> 31u) -#define SET_SHM3_EVENT_STATUS_PENDING(__val__) (((__val__) << 31u) & 0x80000000u) - #define REG_SHM3_PROT_MAGIC ((volatile APE_SHM3_H_uint32_t*)0x60223308) /* This is set to APE_PROT_MAGIC ('PROT') on all functions. If it is 'PROT', the following fields (MAC0_HIGH/LOW) are valid */ #define REG_SHM3_PROT_MAC0_HIGH ((volatile APE_SHM3_H_uint32_t*)0x60223314) /* High 16 bits of MAC address 0. Only valid if */ #define REG_SHM3_PROT_MAC0_LOW ((volatile APE_SHM3_H_uint32_t*)0x60223318) /* Low 16 bits of MAC address 0. */ diff --git a/include/APE_SHM_CHANNEL1.h b/include/APE_SHM_CHANNEL1.h index f709b69..aa5838d 100644 --- a/include/APE_SHM_CHANNEL1.h +++ b/include/APE_SHM_CHANNEL1.h @@ -83,148 +83,11 @@ typedef uint32_t APE_SHM_CHANNEL1_H_uint32_t; #define REG_SHM_CHANNEL1_SIZE (sizeof(SHM_CHANNEL_t)) #define REG_SHM_CHANNEL1_NCSI_CHANNEL_INFO ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a00) /* */ -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_ENABLED_SHIFT 0u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_ENABLED_MASK 0x1u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_TX_PASSTHROUGH_SHIFT 1u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_TX_PASSTHROUGH_MASK 0x2u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_TX_PASSTHROUGH(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_TX_PASSTHROUGH(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_READY_SHIFT 2u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_READY_MASK 0x4u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_READY(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_READY(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_INIT_SHIFT 3u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_INIT_MASK 0x8u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_INIT(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_INIT(__val__) (((__val__) << 3u) & 0x8u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_MFILT_SHIFT 4u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_MFILT_MASK 0x10u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_MFILT(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_MFILT(__val__) (((__val__) << 4u) & 0x10u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_BFILT_SHIFT 5u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_BFILT_MASK 0x20u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_BFILT(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_BFILT(__val__) (((__val__) << 5u) & 0x20u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_SERDES_SHIFT 6u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_SERDES_MASK 0x40u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_SERDES(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_SERDES(__val__) (((__val__) << 6u) & 0x40u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_VLAN_SHIFT 8u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_VLAN_MASK 0x100u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_VLAN(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_VLAN(__val__) (((__val__) << 8u) & 0x100u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2H_SHIFT 10u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2H_MASK 0x400u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2H(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2H(__val__) (((__val__) << 10u) & 0x400u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2N_SHIFT 11u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2N_MASK 0x800u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2N(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2N(__val__) (((__val__) << 11u) & 0x800u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_EEE_SHIFT 12u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_EEE_MASK 0x1000u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_EEE(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_EEE(__val__) (((__val__) << 12u) & 0x1000u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_DRIVER_SHIFT 14u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_DRIVER_MASK 0x4000u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_DRIVER(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_DRIVER(__val__) (((__val__) << 14u) & 0x4000u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_PDEAD_SHIFT 15u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_PDEAD_MASK 0x8000u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_PDEAD(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_PDEAD(__val__) (((__val__) << 15u) & 0x8000u) - #define REG_SHM_CHANNEL1_NCSI_CHANNEL_MCID ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a04) /* AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs. */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_AEN ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a08) /* Set via NCSI ENABLE AEN. */ -#define SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_SHIFT 0u -#define SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_MASK 0x1u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_SHIFT 1u -#define SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_MASK 0x2u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_SHIFT 2u -#define SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_MASK 0x4u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__val__) (((__val__) << 2u) & 0x4u) - #define REG_SHM_CHANNEL1_NCSI_CHANNEL_BFILT ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a0c) /* */ -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_ARP_PACKET_SHIFT 0u -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_ARP_PACKET_MASK 0x1u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_ARP_PACKET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_ARP_PACKET(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET_SHIFT 1u -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET_MASK 0x2u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET_SHIFT 2u -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET_MASK 0x4u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_NETBIOS_PACKET_SHIFT 3u -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_NETBIOS_PACKET_MASK 0x8u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_NETBIOS_PACKET(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_NETBIOS_PACKET(__val__) (((__val__) << 3u) & 0x8u) - #define REG_SHM_CHANNEL1_NCSI_CHANNEL_MFILT ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a10) /* */ -#define SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_SHIFT 0u -#define SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_MASK 0x1u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT_SHIFT 1u -#define SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT_MASK 0x2u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL1_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_SHIFT 2u -#define SHM_CHANNEL1_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_MASK 0x4u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__val__) (((__val__) << 2u) & 0x4u) - #define REG_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1 ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a14) /* This is the "Link Settings" value from NCSI Set Link. */ -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED_SHIFT 0u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED_MASK 0x1u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE_SHIFT 1u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE_MASK 0x2u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE_SHIFT 2u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE_MASK 0x4u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE_SHIFT 3u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE_MASK 0x8u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE_SHIFT 4u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE_MASK 0x10u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE_SHIFT 8u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE_MASK 0x100u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE_SHIFT 9u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE_MASK 0x200u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE_SHIFT 10u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE_MASK 0x400u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_SHIFT 11u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_MASK 0x800u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 11u) & 0x800u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_SHIFT 12u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_MASK 0x1000u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__val__) (((__val__) << 12u) & 0x1000u) - #define REG_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_2 ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a18) /* This is the "OEM Settings" value from NCSI Set Link. */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_VLAN ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a1c) /* Receives VLAN mode from NCSI specification "Enable VLAN" command. */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_ALT_HOST_MAC_HIGH ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a24) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */ @@ -247,31 +110,6 @@ typedef uint32_t APE_SHM_CHANNEL1_H_uint32_t; #define REG_SHM_CHANNEL1_NCSI_CHANNEL_MAC1_VLAN_VALID ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a78) /* Nonzero indicates VLAN field is valid */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_MAC1_VLAN ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a7c) /* */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_STATUS ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a80) /* */ -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_UP_SHIFT 0u -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_UP_MASK 0x1u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_UP(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_UP(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_STATUS_SHIFT 1u -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_STATUS_MASK 0x1eu -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x1e) >> 1u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x1eu) -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_SERDES_SHIFT 5u -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_SERDES_MASK 0x20u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_SERDES(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_SERDES(__val__) (((__val__) << 5u) & 0x20u) -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 6u -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x40u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 6u) & 0x40u) -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_SHIFT 9u -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_MASK 0x200u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__val__) (((__val__) << 9u) & 0x200u) -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_SHIFT 10u -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_MASK 0x400u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__val__) (((__val__) << 10u) & 0x400u) - #define REG_SHM_CHANNEL1_NCSI_CHANNEL_RESET_COUNT ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a84) /* */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_PXE ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a88) /* */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_DROPFIL ((volatile APE_SHM_CHANNEL1_H_uint32_t*)0x60220a8c) /* */ diff --git a/include/APE_SHM_CHANNEL2.h b/include/APE_SHM_CHANNEL2.h index 04f9093..2cf6d4a 100644 --- a/include/APE_SHM_CHANNEL2.h +++ b/include/APE_SHM_CHANNEL2.h @@ -83,148 +83,11 @@ typedef uint32_t APE_SHM_CHANNEL2_H_uint32_t; #define REG_SHM_CHANNEL2_SIZE (sizeof(SHM_CHANNEL_t)) #define REG_SHM_CHANNEL2_NCSI_CHANNEL_INFO ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b00) /* */ -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_ENABLED_SHIFT 0u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_ENABLED_MASK 0x1u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_TX_PASSTHROUGH_SHIFT 1u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_TX_PASSTHROUGH_MASK 0x2u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_TX_PASSTHROUGH(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_TX_PASSTHROUGH(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_READY_SHIFT 2u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_READY_MASK 0x4u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_READY(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_READY(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_INIT_SHIFT 3u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_INIT_MASK 0x8u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_INIT(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_INIT(__val__) (((__val__) << 3u) & 0x8u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_MFILT_SHIFT 4u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_MFILT_MASK 0x10u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_MFILT(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_MFILT(__val__) (((__val__) << 4u) & 0x10u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_BFILT_SHIFT 5u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_BFILT_MASK 0x20u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_BFILT(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_BFILT(__val__) (((__val__) << 5u) & 0x20u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_SERDES_SHIFT 6u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_SERDES_MASK 0x40u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_SERDES(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_SERDES(__val__) (((__val__) << 6u) & 0x40u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_VLAN_SHIFT 8u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_VLAN_MASK 0x100u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_VLAN(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_VLAN(__val__) (((__val__) << 8u) & 0x100u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2H_SHIFT 10u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2H_MASK 0x400u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2H(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2H(__val__) (((__val__) << 10u) & 0x400u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2N_SHIFT 11u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2N_MASK 0x800u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2N(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2N(__val__) (((__val__) << 11u) & 0x800u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_EEE_SHIFT 12u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_EEE_MASK 0x1000u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_EEE(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_EEE(__val__) (((__val__) << 12u) & 0x1000u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_DRIVER_SHIFT 14u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_DRIVER_MASK 0x4000u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_DRIVER(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_DRIVER(__val__) (((__val__) << 14u) & 0x4000u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_PDEAD_SHIFT 15u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_PDEAD_MASK 0x8000u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_PDEAD(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_PDEAD(__val__) (((__val__) << 15u) & 0x8000u) - #define REG_SHM_CHANNEL2_NCSI_CHANNEL_MCID ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b04) /* AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs. */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_AEN ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b08) /* Set via NCSI ENABLE AEN. */ -#define SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_SHIFT 0u -#define SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_MASK 0x1u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_SHIFT 1u -#define SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_MASK 0x2u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_SHIFT 2u -#define SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_MASK 0x4u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__val__) (((__val__) << 2u) & 0x4u) - #define REG_SHM_CHANNEL2_NCSI_CHANNEL_BFILT ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b0c) /* */ -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_ARP_PACKET_SHIFT 0u -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_ARP_PACKET_MASK 0x1u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_ARP_PACKET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_ARP_PACKET(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET_SHIFT 1u -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET_MASK 0x2u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET_SHIFT 2u -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET_MASK 0x4u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_NETBIOS_PACKET_SHIFT 3u -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_NETBIOS_PACKET_MASK 0x8u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_NETBIOS_PACKET(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_NETBIOS_PACKET(__val__) (((__val__) << 3u) & 0x8u) - #define REG_SHM_CHANNEL2_NCSI_CHANNEL_MFILT ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b10) /* */ -#define SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_SHIFT 0u -#define SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_MASK 0x1u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT_SHIFT 1u -#define SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT_MASK 0x2u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL2_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_SHIFT 2u -#define SHM_CHANNEL2_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_MASK 0x4u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__val__) (((__val__) << 2u) & 0x4u) - #define REG_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1 ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b14) /* This is the "Link Settings" value from NCSI Set Link. */ -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED_SHIFT 0u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED_MASK 0x1u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE_SHIFT 1u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE_MASK 0x2u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE_SHIFT 2u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE_MASK 0x4u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE_SHIFT 3u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE_MASK 0x8u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE_SHIFT 4u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE_MASK 0x10u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE_SHIFT 8u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE_MASK 0x100u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE_SHIFT 9u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE_MASK 0x200u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE_SHIFT 10u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE_MASK 0x400u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_SHIFT 11u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_MASK 0x800u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 11u) & 0x800u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_SHIFT 12u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_MASK 0x1000u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__val__) (((__val__) << 12u) & 0x1000u) - #define REG_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_2 ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b18) /* This is the "OEM Settings" value from NCSI Set Link. */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_VLAN ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b1c) /* Receives VLAN mode from NCSI specification "Enable VLAN" command. */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_ALT_HOST_MAC_HIGH ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b24) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */ @@ -247,31 +110,6 @@ typedef uint32_t APE_SHM_CHANNEL2_H_uint32_t; #define REG_SHM_CHANNEL2_NCSI_CHANNEL_MAC1_VLAN_VALID ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b78) /* Nonzero indicates VLAN field is valid */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_MAC1_VLAN ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b7c) /* */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_STATUS ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b80) /* */ -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_UP_SHIFT 0u -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_UP_MASK 0x1u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_UP(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_UP(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_STATUS_SHIFT 1u -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_STATUS_MASK 0x1eu -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x1e) >> 1u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x1eu) -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_SERDES_SHIFT 5u -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_SERDES_MASK 0x20u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_SERDES(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_SERDES(__val__) (((__val__) << 5u) & 0x20u) -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 6u -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x40u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 6u) & 0x40u) -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_SHIFT 9u -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_MASK 0x200u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__val__) (((__val__) << 9u) & 0x200u) -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_SHIFT 10u -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_MASK 0x400u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__val__) (((__val__) << 10u) & 0x400u) - #define REG_SHM_CHANNEL2_NCSI_CHANNEL_RESET_COUNT ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b84) /* */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_PXE ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b88) /* */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_DROPFIL ((volatile APE_SHM_CHANNEL2_H_uint32_t*)0x60220b8c) /* */ diff --git a/include/APE_SHM_CHANNEL3.h b/include/APE_SHM_CHANNEL3.h index dbd4643..907d2dc 100644 --- a/include/APE_SHM_CHANNEL3.h +++ b/include/APE_SHM_CHANNEL3.h @@ -83,148 +83,11 @@ typedef uint32_t APE_SHM_CHANNEL3_H_uint32_t; #define REG_SHM_CHANNEL3_SIZE (sizeof(SHM_CHANNEL_t)) #define REG_SHM_CHANNEL3_NCSI_CHANNEL_INFO ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c00) /* */ -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_ENABLED_SHIFT 0u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_ENABLED_MASK 0x1u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_TX_PASSTHROUGH_SHIFT 1u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_TX_PASSTHROUGH_MASK 0x2u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_TX_PASSTHROUGH(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_TX_PASSTHROUGH(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_READY_SHIFT 2u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_READY_MASK 0x4u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_READY(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_READY(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_INIT_SHIFT 3u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_INIT_MASK 0x8u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_INIT(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_INIT(__val__) (((__val__) << 3u) & 0x8u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_MFILT_SHIFT 4u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_MFILT_MASK 0x10u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_MFILT(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_MFILT(__val__) (((__val__) << 4u) & 0x10u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_BFILT_SHIFT 5u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_BFILT_MASK 0x20u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_BFILT(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_BFILT(__val__) (((__val__) << 5u) & 0x20u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_SERDES_SHIFT 6u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_SERDES_MASK 0x40u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_SERDES(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_SERDES(__val__) (((__val__) << 6u) & 0x40u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_VLAN_SHIFT 8u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_VLAN_MASK 0x100u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_VLAN(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_VLAN(__val__) (((__val__) << 8u) & 0x100u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2H_SHIFT 10u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2H_MASK 0x400u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2H(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2H(__val__) (((__val__) << 10u) & 0x400u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2N_SHIFT 11u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2N_MASK 0x800u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2N(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2N(__val__) (((__val__) << 11u) & 0x800u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_EEE_SHIFT 12u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_EEE_MASK 0x1000u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_EEE(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_EEE(__val__) (((__val__) << 12u) & 0x1000u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_DRIVER_SHIFT 14u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_DRIVER_MASK 0x4000u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_DRIVER(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_DRIVER(__val__) (((__val__) << 14u) & 0x4000u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_PDEAD_SHIFT 15u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_PDEAD_MASK 0x8000u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_PDEAD(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_PDEAD(__val__) (((__val__) << 15u) & 0x8000u) - #define REG_SHM_CHANNEL3_NCSI_CHANNEL_MCID ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c04) /* AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs. */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_AEN ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c08) /* Set via NCSI ENABLE AEN. */ -#define SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_SHIFT 0u -#define SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_MASK 0x1u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_SHIFT 1u -#define SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_MASK 0x2u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_SHIFT 2u -#define SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_MASK 0x4u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__val__) (((__val__) << 2u) & 0x4u) - #define REG_SHM_CHANNEL3_NCSI_CHANNEL_BFILT ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c0c) /* */ -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_ARP_PACKET_SHIFT 0u -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_ARP_PACKET_MASK 0x1u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_ARP_PACKET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_ARP_PACKET(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET_SHIFT 1u -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET_MASK 0x2u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET_SHIFT 2u -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET_MASK 0x4u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_NETBIOS_PACKET_SHIFT 3u -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_NETBIOS_PACKET_MASK 0x8u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_NETBIOS_PACKET(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_NETBIOS_PACKET(__val__) (((__val__) << 3u) & 0x8u) - #define REG_SHM_CHANNEL3_NCSI_CHANNEL_MFILT ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c10) /* */ -#define SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_SHIFT 0u -#define SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_MASK 0x1u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT_SHIFT 1u -#define SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT_MASK 0x2u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL3_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_SHIFT 2u -#define SHM_CHANNEL3_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_MASK 0x4u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__val__) (((__val__) << 2u) & 0x4u) - #define REG_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1 ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c14) /* This is the "Link Settings" value from NCSI Set Link. */ -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED_SHIFT 0u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED_MASK 0x1u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE_SHIFT 1u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE_MASK 0x2u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE_SHIFT 2u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE_MASK 0x4u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE_SHIFT 3u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE_MASK 0x8u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE_SHIFT 4u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE_MASK 0x10u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE_SHIFT 8u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE_MASK 0x100u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE_SHIFT 9u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE_MASK 0x200u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE_SHIFT 10u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE_MASK 0x400u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_SHIFT 11u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_MASK 0x800u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 11u) & 0x800u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_SHIFT 12u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_MASK 0x1000u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__val__) (((__val__) << 12u) & 0x1000u) - #define REG_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_2 ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c18) /* This is the "OEM Settings" value from NCSI Set Link. */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_VLAN ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c1c) /* Receives VLAN mode from NCSI specification "Enable VLAN" command. */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_ALT_HOST_MAC_HIGH ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c24) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */ @@ -247,31 +110,6 @@ typedef uint32_t APE_SHM_CHANNEL3_H_uint32_t; #define REG_SHM_CHANNEL3_NCSI_CHANNEL_MAC1_VLAN_VALID ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c78) /* Nonzero indicates VLAN field is valid */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_MAC1_VLAN ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c7c) /* */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_STATUS ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c80) /* */ -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_UP_SHIFT 0u -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_UP_MASK 0x1u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_UP(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_UP(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_STATUS_SHIFT 1u -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_STATUS_MASK 0x1eu -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x1e) >> 1u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x1eu) -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_SERDES_SHIFT 5u -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_SERDES_MASK 0x20u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_SERDES(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_SERDES(__val__) (((__val__) << 5u) & 0x20u) -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 6u -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x40u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 6u) & 0x40u) -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_SHIFT 9u -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_MASK 0x200u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__val__) (((__val__) << 9u) & 0x200u) -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_SHIFT 10u -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_MASK 0x400u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__val__) (((__val__) << 10u) & 0x400u) - #define REG_SHM_CHANNEL3_NCSI_CHANNEL_RESET_COUNT ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c84) /* */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_PXE ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c88) /* */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_DROPFIL ((volatile APE_SHM_CHANNEL3_H_uint32_t*)0x60220c8c) /* */ diff --git a/include/APE_TX_PORT.h b/include/APE_TX_PORT0.h index 33a127d..f397178 100644 --- a/include/APE_TX_PORT.h +++ b/include/APE_TX_PORT0.h @@ -1,10 +1,10 @@ //////////////////////////////////////////////////////////////////////////////// /// -/// @file APE_TX_PORT.h +/// @file APE_TX_PORT0.h /// /// @project ape /// -/// @brief APE_TX_PORT +/// @brief APE_TX_PORT0 /// //////////////////////////////////////////////////////////////////////////////// /// @@ -42,26 +42,26 @@ /// @endcond //////////////////////////////////////////////////////////////////////////////// -/** @defgroup APE_TX_PORT_H APE_TX_PORT */ -/** @addtogroup APE_TX_PORT_H +/** @defgroup APE_TX_PORT0_H APE_TX_PORT0 */ +/** @addtogroup APE_TX_PORT0_H * @{ */ -#ifndef APE_TX_PORT_H -#define APE_TX_PORT_H +#ifndef APE_TX_PORT0_H +#define APE_TX_PORT0_H #include <stdint.h> #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ -void init_APE_TX_PORT_sim(void* base); -void init_APE_TX_PORT(void); +void init_APE_TX_PORT0_sim(void* base); +void init_APE_TX_PORT0(void); #include <CXXRegister.h> -typedef CXXRegister<uint8_t, 0, 8> APE_TX_PORT_H_uint8_t; -typedef CXXRegister<uint16_t, 0, 16> APE_TX_PORT_H_uint16_t; -typedef CXXRegister<uint32_t, 0, 32> APE_TX_PORT_H_uint32_t; -#define APE_TX_PORT_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> -#define APE_TX_PORT_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> -#define APE_TX_PORT_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> +typedef CXXRegister<uint8_t, 0, 8> APE_TX_PORT0_H_uint8_t; +typedef CXXRegister<uint16_t, 0, 16> APE_TX_PORT0_H_uint16_t; +typedef CXXRegister<uint32_t, 0, 32> APE_TX_PORT0_H_uint32_t; +#define APE_TX_PORT0_H_uint8_t_bitfield(__pos__, __width__) CXXRegister<uint8_t, __pos__, __width__> +#define APE_TX_PORT0_H_uint16_t_bitfield(__pos__, __width__) CXXRegister<uint16_t, __pos__, __width__> +#define APE_TX_PORT0_H_uint32_t_bitfield(__pos__, __width__) CXXRegister<uint32_t, __pos__, __width__> #define register_container struct #define volatile #define BITFIELD_BEGIN(__type__, __name__) struct { @@ -69,23 +69,23 @@ typedef CXXRegister<uint32_t, 0, 32> APE_TX_PORT_H_uint32_t; #define BITFIELD_END(__type__, __name__) } __name__; #else /* Firmware Data types */ -typedef uint8_t APE_TX_PORT_H_uint8_t; -typedef uint16_t APE_TX_PORT_H_uint16_t; -typedef uint32_t APE_TX_PORT_H_uint32_t; +typedef uint8_t APE_TX_PORT0_H_uint8_t; +typedef uint16_t APE_TX_PORT0_H_uint16_t; +typedef uint32_t APE_TX_PORT0_H_uint32_t; #define register_container union #define BITFIELD_BEGIN(__type__, __name__) struct { #define BITFIELD_MEMBER(__type__, __name__, __offset__, __bits__) __type__ __name__:__bits__; #define BITFIELD_END(__type__, __name__) } __name__; #endif /* !CXX_SIMULATOR */ -#define REG_TX_PORT_BASE ((volatile void*)0xa0020000) /* TX to network port, function 0 */ -#define REG_TX_PORT_SIZE (sizeof(TX_PORT_t)) +#define REG_TX_PORT0_BASE ((volatile void*)0xa0020000) /* TX to network port, function 0 */ +#define REG_TX_PORT0_SIZE (sizeof(TX_PORT_t)) -#define REG_TX_PORT_OUT ((volatile APE_TX_PORT_H_uint32_t*)0xa0020000) /* This is the memory range into which frames are directed towards the network by the APE firmware. */ -#define TX_PORT_OUT_ALL_SHIFT 0u -#define TX_PORT_OUT_ALL_MASK 0xffffffffu -#define GET_TX_PORT_OUT_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_TX_PORT_OUT_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) +#define REG_TX_PORT0_OUT ((volatile APE_TX_PORT0_H_uint32_t*)0xa0020000) /* This is the memory range into which frames are directed towards the network by the APE firmware. */ +#define TX_PORT0_OUT_ALL_SHIFT 0u +#define TX_PORT0_OUT_ALL_MASK 0xffffffffu +#define GET_TX_PORT0_OUT_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) +#define SET_TX_PORT0_OUT_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) #define TX_PORT_OUT_ALL_CONTROL_WORD 0x0u #define TX_PORT_OUT_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u #define TX_PORT_OUT_ALL_FRAME_LEN_WORD 0x3u @@ -98,19 +98,19 @@ typedef uint32_t APE_TX_PORT_H_uint32_t; /** @brief Register definition for @ref TX_PORT_t.Out. */ typedef register_container RegTX_PORTOut_t { /** @brief 32bit direct register access. */ - APE_TX_PORT_H_uint32_t r32; + APE_TX_PORT0_H_uint32_t r32; - BITFIELD_BEGIN(APE_TX_PORT_H_uint32_t, bits) + BITFIELD_BEGIN(APE_TX_PORT0_H_uint32_t, bits) #if defined(__LITTLE_ENDIAN__) /** @brief All bits */ - BITFIELD_MEMBER(APE_TX_PORT_H_uint32_t, all, 0, 32) + BITFIELD_MEMBER(APE_TX_PORT0_H_uint32_t, all, 0, 32) #elif defined(__BIG_ENDIAN__) /** @brief All bits */ - BITFIELD_MEMBER(APE_TX_PORT_H_uint32_t, all, 0, 32) + BITFIELD_MEMBER(APE_TX_PORT0_H_uint32_t, all, 0, 32) #else #error Unknown Endian #endif - BITFIELD_END(APE_TX_PORT_H_uint32_t, bits) + BITFIELD_END(APE_TX_PORT0_H_uint32_t, bits) #ifdef CXX_SIMULATOR /** @brief Register name for use with the simulator. */ const char* getName(void) { return "Out"; } @@ -133,7 +133,7 @@ typedef register_container RegTX_PORTOut_t { #endif /* CXX_SIMULATOR */ } RegTX_PORTOut_t; -/** @brief Component definition for @ref TX_PORT. */ +/** @brief Component definition for @ref TX_PORT0. */ typedef struct TX_PORT_t { /** @brief This is the memory range into which frames are directed towards the network by the APE firmware. */ RegTX_PORTOut_t Out[2048]; @@ -159,7 +159,7 @@ typedef struct TX_PORT_t { } TX_PORT_t; /** @brief TX to network port, function 0 */ -extern volatile TX_PORT_t TX_PORT; +extern volatile TX_PORT_t TX_PORT0; @@ -172,6 +172,6 @@ extern volatile TX_PORT_t TX_PORT; #undef BITFIELD_MEMBER #undef BITFIELD_END -#endif /* !APE_TX_PORT_H */ +#endif /* !APE_TX_PORT0_H */ /** @} */ diff --git a/include/APE_TX_PORT1.h b/include/APE_TX_PORT1.h index aa8fedb..124dffd 100644 --- a/include/APE_TX_PORT1.h +++ b/include/APE_TX_PORT1.h @@ -50,7 +50,7 @@ #define APE_TX_PORT1_H #include <stdint.h> -#include "APE_TX_PORT.h" +#include "APE_TX_PORT0.h" #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ void init_APE_TX_PORT1_sim(void* base); @@ -83,19 +83,6 @@ typedef uint32_t APE_TX_PORT1_H_uint32_t; #define REG_TX_PORT1_SIZE (sizeof(TX_PORT_t)) #define REG_TX_PORT1_OUT ((volatile APE_TX_PORT1_H_uint32_t*)0xa0022000) /* This is the memory range into which frames are directed towards the network by the APE firmware. */ -#define TX_PORT1_OUT_ALL_SHIFT 0u -#define TX_PORT1_OUT_ALL_MASK 0xffffffffu -#define GET_TX_PORT1_OUT_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_TX_PORT1_OUT_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) -#define TX_PORT1_OUT_ALL_CONTROL_WORD 0x0u -#define TX_PORT1_OUT_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u -#define TX_PORT1_OUT_ALL_FRAME_LEN_WORD 0x3u -#define TX_PORT1_OUT_ALL_NUM_BLOCKS_WORD 0x9u -#define TX_PORT1_OUT_ALL_FIRST_PAYLOAD_WORD 0xcu -#define TX_PORT1_OUT_ALL_BLOCK_WORDS 0x20u -#define TX_PORT1_OUT_ALL_BLOCK_BYTES 0x80u - - /** @brief TX to network port, function 1 */ extern volatile TX_PORT_t TX_PORT1; diff --git a/include/APE_TX_PORT2.h b/include/APE_TX_PORT2.h index d37310c..a288f08 100644 --- a/include/APE_TX_PORT2.h +++ b/include/APE_TX_PORT2.h @@ -50,7 +50,7 @@ #define APE_TX_PORT2_H #include <stdint.h> -#include "APE_TX_PORT.h" +#include "APE_TX_PORT0.h" #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ void init_APE_TX_PORT2_sim(void* base); @@ -83,19 +83,6 @@ typedef uint32_t APE_TX_PORT2_H_uint32_t; #define REG_TX_PORT2_SIZE (sizeof(TX_PORT_t)) #define REG_TX_PORT2_OUT ((volatile APE_TX_PORT2_H_uint32_t*)0xa0024000) /* This is the memory range into which frames are directed towards the network by the APE firmware. */ -#define TX_PORT2_OUT_ALL_SHIFT 0u -#define TX_PORT2_OUT_ALL_MASK 0xffffffffu -#define GET_TX_PORT2_OUT_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_TX_PORT2_OUT_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) -#define TX_PORT2_OUT_ALL_CONTROL_WORD 0x0u -#define TX_PORT2_OUT_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u -#define TX_PORT2_OUT_ALL_FRAME_LEN_WORD 0x3u -#define TX_PORT2_OUT_ALL_NUM_BLOCKS_WORD 0x9u -#define TX_PORT2_OUT_ALL_FIRST_PAYLOAD_WORD 0xcu -#define TX_PORT2_OUT_ALL_BLOCK_WORDS 0x20u -#define TX_PORT2_OUT_ALL_BLOCK_BYTES 0x80u - - /** @brief TX to network port, function 2 */ extern volatile TX_PORT_t TX_PORT2; diff --git a/include/APE_TX_PORT3.h b/include/APE_TX_PORT3.h index 3dd308f..01109a5 100644 --- a/include/APE_TX_PORT3.h +++ b/include/APE_TX_PORT3.h @@ -50,7 +50,7 @@ #define APE_TX_PORT3_H #include <stdint.h> -#include "APE_TX_PORT.h" +#include "APE_TX_PORT0.h" #ifdef CXX_SIMULATOR /* Compiling c++ simulator code - uses register wrappers */ void init_APE_TX_PORT3_sim(void* base); @@ -83,19 +83,6 @@ typedef uint32_t APE_TX_PORT3_H_uint32_t; #define REG_TX_PORT3_SIZE (sizeof(TX_PORT_t)) #define REG_TX_PORT3_OUT ((volatile APE_TX_PORT3_H_uint32_t*)0xa0026000) /* This is the memory range into which frames are directed towards the network by the APE firmware. */ -#define TX_PORT3_OUT_ALL_SHIFT 0u -#define TX_PORT3_OUT_ALL_MASK 0xffffffffu -#define GET_TX_PORT3_OUT_ALL(__reg__) (((__reg__) & 0xffffffff) >> 0u) -#define SET_TX_PORT3_OUT_ALL(__val__) (((__val__) << 0u) & 0xffffffffu) -#define TX_PORT3_OUT_ALL_CONTROL_WORD 0x0u -#define TX_PORT3_OUT_ALL_ADDITIONAL_PAYLOAD_WORD 0x2u -#define TX_PORT3_OUT_ALL_FRAME_LEN_WORD 0x3u -#define TX_PORT3_OUT_ALL_NUM_BLOCKS_WORD 0x9u -#define TX_PORT3_OUT_ALL_FIRST_PAYLOAD_WORD 0xcu -#define TX_PORT3_OUT_ALL_BLOCK_WORDS 0x20u -#define TX_PORT3_OUT_ALL_BLOCK_BYTES 0x80u - - /** @brief TX to network port, function 3 */ extern volatile TX_PORT_t TX_PORT3; diff --git a/include/bcm5719_APE.h b/include/bcm5719_APE.h index b68518f..30d4a03 100644 --- a/include/bcm5719_APE.h +++ b/include/bcm5719_APE.h @@ -539,7 +539,7 @@ typedef register_container RegAPEEvent_t { #define SET_APE_RXBUFOFFSET_FUNC0_FINISHED(__val__) (((__val__) << 31u) & 0x80000000u) /** @brief Register definition for @ref APE_t.RxbufoffsetFunc0. */ -typedef register_container RegAPERxbufoffsetFunc0_t { +typedef register_container RegAPERxbufoffset_t { /** @brief 32bit direct register access. */ BCM5719_APE_H_uint32_t r32; @@ -585,7 +585,7 @@ typedef register_container RegAPERxbufoffsetFunc0_t { /** @brief Print register value. */ void print(void) { r32.print(); } - RegAPERxbufoffsetFunc0_t() + RegAPERxbufoffset_t() { /** @brief constructor for @ref APE_t.RxbufoffsetFunc0. */ r32.setName("RxbufoffsetFunc0"); @@ -604,112 +604,15 @@ typedef register_container RegAPERxbufoffsetFunc0_t { bits.Finished.setBaseRegister(&r32); bits.Finished.setName("Finished"); } - RegAPERxbufoffsetFunc0_t& operator=(const RegAPERxbufoffsetFunc0_t& other) + RegAPERxbufoffset_t& operator=(const RegAPERxbufoffset_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ -} RegAPERxbufoffsetFunc0_t; +} RegAPERxbufoffset_t; #define REG_APE_RXBUFOFFSET_FUNC1 ((volatile BCM5719_APE_H_uint32_t*)0xc0010018) /* This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. */ -#define APE_RXBUFOFFSET_FUNC1_TAIL_SHIFT 0u -#define APE_RXBUFOFFSET_FUNC1_TAIL_MASK 0xfffu -#define GET_APE_RXBUFOFFSET_FUNC1_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_RXBUFOFFSET_FUNC1_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_RXBUFOFFSET_FUNC1_HEAD_SHIFT 12u -#define APE_RXBUFOFFSET_FUNC1_HEAD_MASK 0xfff000u -#define GET_APE_RXBUFOFFSET_FUNC1_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_RXBUFOFFSET_FUNC1_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_RXBUFOFFSET_FUNC1_TO_HOST_SHIFT 24u -#define APE_RXBUFOFFSET_FUNC1_TO_HOST_MASK 0x1000000u -#define GET_APE_RXBUFOFFSET_FUNC1_TO_HOST(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_APE_RXBUFOFFSET_FUNC1_TO_HOST(__val__) (((__val__) << 24u) & 0x1000000u) -#define APE_RXBUFOFFSET_FUNC1_IP_FRAG_SHIFT 25u -#define APE_RXBUFOFFSET_FUNC1_IP_FRAG_MASK 0x2000000u -#define GET_APE_RXBUFOFFSET_FUNC1_IP_FRAG(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_APE_RXBUFOFFSET_FUNC1_IP_FRAG(__val__) (((__val__) << 25u) & 0x2000000u) -#define APE_RXBUFOFFSET_FUNC1_COUNT_SHIFT 26u -#define APE_RXBUFOFFSET_FUNC1_COUNT_MASK 0x3c000000u -#define GET_APE_RXBUFOFFSET_FUNC1_COUNT(__reg__) (((__reg__) & 0x3c000000) >> 26u) -#define SET_APE_RXBUFOFFSET_FUNC1_COUNT(__val__) (((__val__) << 26u) & 0x3c000000u) -#define APE_RXBUFOFFSET_FUNC1_VALID_SHIFT 30u -#define APE_RXBUFOFFSET_FUNC1_VALID_MASK 0x40000000u -#define GET_APE_RXBUFOFFSET_FUNC1_VALID(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_APE_RXBUFOFFSET_FUNC1_VALID(__val__) (((__val__) << 30u) & 0x40000000u) - -/** @brief Register definition for @ref APE_t.RxbufoffsetFunc1. */ -typedef register_container RegAPERxbufoffsetFunc1_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ToHost, 24, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPFrag, 25, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 26, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Valid, 30, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Valid, 30, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 26, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPFrag, 25, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ToHost, 24, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxbufoffsetFunc1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxbufoffsetFunc1_t() - { - /** @brief constructor for @ref APE_t.RxbufoffsetFunc1. */ - r32.setName("RxbufoffsetFunc1"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.ToHost.setBaseRegister(&r32); - bits.ToHost.setName("ToHost"); - bits.IPFrag.setBaseRegister(&r32); - bits.IPFrag.setName("IPFrag"); - bits.Count.setBaseRegister(&r32); - bits.Count.setName("Count"); - bits.Valid.setBaseRegister(&r32); - bits.Valid.setName("Valid"); - } - RegAPERxbufoffsetFunc1_t& operator=(const RegAPERxbufoffsetFunc1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxbufoffsetFunc1_t; - #define REG_APE_TX_TO_NET_DOORBELL_FUNC0 ((volatile BCM5719_APE_H_uint32_t*)0xc001001c) /* Written on APE TX to network after filling 0xA002 buffer with packet. */ #define APE_TX_TO_NET_DOORBELL_FUNC0_TAIL_SHIFT 0u #define APE_TX_TO_NET_DOORBELL_FUNC0_TAIL_MASK 0xfffu @@ -729,7 +632,7 @@ typedef register_container RegAPERxbufoffsetFunc1_t { #define SET_APE_TX_TO_NET_DOORBELL_FUNC0_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) /** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc0. */ -typedef register_container RegAPETxToNetDoorbellFunc0_t { +typedef register_container RegAPETxToNetDoorbell_t { /** @brief 32bit direct register access. */ BCM5719_APE_H_uint32_t r32; @@ -767,7 +670,7 @@ typedef register_container RegAPETxToNetDoorbellFunc0_t { /** @brief Print register value. */ void print(void) { r32.print(); } - RegAPETxToNetDoorbellFunc0_t() + RegAPETxToNetDoorbell_t() { /** @brief constructor for @ref APE_t.TxToNetDoorbellFunc0. */ r32.setName("TxToNetDoorbellFunc0"); @@ -780,13 +683,13 @@ typedef register_container RegAPETxToNetDoorbellFunc0_t { bits.TXQueueFull.setBaseRegister(&r32); bits.TXQueueFull.setName("TXQueueFull"); } - RegAPETxToNetDoorbellFunc0_t& operator=(const RegAPETxToNetDoorbellFunc0_t& other) + RegAPETxToNetDoorbell_t& operator=(const RegAPETxToNetDoorbell_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ -} RegAPETxToNetDoorbellFunc0_t; +} RegAPETxToNetDoorbell_t; #define REG_APE_TX_STATE0 ((volatile BCM5719_APE_H_uint32_t*)0xc0010020) /* APE TX Status. */ #define APE_TX_STATE0_TAIL_SHIFT 0u @@ -972,7 +875,7 @@ typedef register_container RegAPELockGrantObsolete_t { #define SET_APE_RX_POOL_MODE_STATUS_0_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) /** @brief Register definition for @ref APE_t.RxPoolModeStatus0. */ -typedef register_container RegAPERxPoolModeStatus0_t { +typedef register_container RegAPERxPoolModeStatus_t { /** @brief 32bit direct register access. */ BCM5719_APE_H_uint32_t r32; @@ -1030,7 +933,7 @@ typedef register_container RegAPERxPoolModeStatus0_t { /** @brief Print register value. */ void print(void) { r32.print(); } - RegAPERxPoolModeStatus0_t() + RegAPERxPoolModeStatus_t() { /** @brief constructor for @ref APE_t.RxPoolModeStatus0. */ r32.setName("RxPoolModeStatus0"); @@ -1049,130 +952,15 @@ typedef register_container RegAPERxPoolModeStatus0_t { bits.FullCount.setBaseRegister(&r32); bits.FullCount.setName("FullCount"); } - RegAPERxPoolModeStatus0_t& operator=(const RegAPERxPoolModeStatus0_t& other) + RegAPERxPoolModeStatus_t& operator=(const RegAPERxPoolModeStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ -} RegAPERxPoolModeStatus0_t; +} RegAPERxPoolModeStatus_t; #define REG_APE_RX_POOL_MODE_STATUS_1 ((volatile BCM5719_APE_H_uint32_t*)0xc001007c) /* */ -#define APE_RX_POOL_MODE_STATUS_1_HALT_SHIFT 0u -#define APE_RX_POOL_MODE_STATUS_1_HALT_MASK 0x1u -#define GET_APE_RX_POOL_MODE_STATUS_1_HALT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_RX_POOL_MODE_STATUS_1_HALT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_RX_POOL_MODE_STATUS_1_HALT_DONE_SHIFT 1u -#define APE_RX_POOL_MODE_STATUS_1_HALT_DONE_MASK 0x2u -#define GET_APE_RX_POOL_MODE_STATUS_1_HALT_DONE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_RX_POOL_MODE_STATUS_1_HALT_DONE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_RX_POOL_MODE_STATUS_1_ENABLE_SHIFT 2u -#define APE_RX_POOL_MODE_STATUS_1_ENABLE_MASK 0x4u -#define GET_APE_RX_POOL_MODE_STATUS_1_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_RX_POOL_MODE_STATUS_1_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_RX_POOL_MODE_STATUS_1_EMPTY_SHIFT 4u -#define APE_RX_POOL_MODE_STATUS_1_EMPTY_MASK 0x10u -#define GET_APE_RX_POOL_MODE_STATUS_1_EMPTY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_RX_POOL_MODE_STATUS_1_EMPTY(__val__) (((__val__) << 4u) & 0x10u) -#define APE_RX_POOL_MODE_STATUS_1_ERROR_SHIFT 5u -#define APE_RX_POOL_MODE_STATUS_1_ERROR_MASK 0x20u -#define GET_APE_RX_POOL_MODE_STATUS_1_ERROR(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_RX_POOL_MODE_STATUS_1_ERROR(__val__) (((__val__) << 5u) & 0x20u) -#define APE_RX_POOL_MODE_STATUS_1_RESET_SHIFT 6u -#define APE_RX_POOL_MODE_STATUS_1_RESET_MASK 0x40u -#define GET_APE_RX_POOL_MODE_STATUS_1_RESET(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_RX_POOL_MODE_STATUS_1_RESET(__val__) (((__val__) << 6u) & 0x40u) -#define APE_RX_POOL_MODE_STATUS_1_FULL_COUNT_SHIFT 8u -#define APE_RX_POOL_MODE_STATUS_1_FULL_COUNT_MASK 0xffff00u -#define GET_APE_RX_POOL_MODE_STATUS_1_FULL_COUNT(__reg__) (((__reg__) & 0xffff00) >> 8u) -#define SET_APE_RX_POOL_MODE_STATUS_1_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) - -/** @brief Register definition for @ref APE_t.RxPoolModeStatus1. */ -typedef register_container RegAPERxPoolModeStatus1_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halt, 0, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enable, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Empty, 4, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Reset, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_24, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_24, 24, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Reset, 6, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Empty, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halt, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxPoolModeStatus1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxPoolModeStatus1_t() - { - /** @brief constructor for @ref APE_t.RxPoolModeStatus1. */ - r32.setName("RxPoolModeStatus1"); - bits.Halt.setBaseRegister(&r32); - bits.Halt.setName("Halt"); - bits.HaltDone.setBaseRegister(&r32); - bits.HaltDone.setName("HaltDone"); - bits.Enable.setBaseRegister(&r32); - bits.Enable.setName("Enable"); - bits.Empty.setBaseRegister(&r32); - bits.Empty.setName("Empty"); - bits.Error.setBaseRegister(&r32); - bits.Error.setName("Error"); - bits.Reset.setBaseRegister(&r32); - bits.Reset.setName("Reset"); - bits.FullCount.setBaseRegister(&r32); - bits.FullCount.setName("FullCount"); - } - RegAPERxPoolModeStatus1_t& operator=(const RegAPERxPoolModeStatus1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxPoolModeStatus1_t; - #define REG_APE_RX_POOL_RETIRE_0 ((volatile BCM5719_APE_H_uint32_t*)0xc0010080) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ #define APE_RX_POOL_RETIRE_0_TAIL_SHIFT 0u #define APE_RX_POOL_RETIRE_0_TAIL_MASK 0xfffu @@ -1190,10 +978,10 @@ typedef register_container RegAPERxPoolModeStatus1_t { #define APE_RX_POOL_RETIRE_0_STATE_MASK 0x6000000u #define GET_APE_RX_POOL_RETIRE_0_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) #define SET_APE_RX_POOL_RETIRE_0_STATE(__val__) (((__val__) << 25u) & 0x6000000u) -#define APE_RX_POOL_RETIRE_0_STATE_PROCESSING 0x0u -#define APE_RX_POOL_RETIRE_0_STATE_RETIRED_OK 0x1u -#define APE_RX_POOL_RETIRE_0_STATE_ERROR__FULL 0x2u -#define APE_RX_POOL_RETIRE_0_STATE_ERROR__IN_HALT 0x3u +#define APE_RX_POOL_RETIRE_STATE_PROCESSING 0x0u +#define APE_RX_POOL_RETIRE_STATE_RETIRED_OK 0x1u +#define APE_RX_POOL_RETIRE_STATE_ERROR__FULL 0x2u +#define APE_RX_POOL_RETIRE_STATE_ERROR__IN_HALT 0x3u #define APE_RX_POOL_RETIRE_0_COUNT_SHIFT 27u #define APE_RX_POOL_RETIRE_0_COUNT_MASK 0x78000000u @@ -1201,7 +989,7 @@ typedef register_container RegAPERxPoolModeStatus1_t { #define SET_APE_RX_POOL_RETIRE_0_COUNT(__val__) (((__val__) << 27u) & 0x78000000u) /** @brief Register definition for @ref APE_t.RxPoolRetire0. */ -typedef register_container RegAPERxPoolRetire0_t { +typedef register_container RegAPERxPoolRetire_t { /** @brief 32bit direct register access. */ BCM5719_APE_H_uint32_t r32; @@ -1243,7 +1031,7 @@ typedef register_container RegAPERxPoolRetire0_t { /** @brief Print register value. */ void print(void) { r32.print(); } - RegAPERxPoolRetire0_t() + RegAPERxPoolRetire_t() { /** @brief constructor for @ref APE_t.RxPoolRetire0. */ r32.setName("RxPoolRetire0"); @@ -1258,107 +1046,15 @@ typedef register_container RegAPERxPoolRetire0_t { bits.Count.setBaseRegister(&r32); bits.Count.setName("Count"); } - RegAPERxPoolRetire0_t& operator=(const RegAPERxPoolRetire0_t& other) + RegAPERxPoolRetire_t& operator=(const RegAPERxPoolRetire_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ -} RegAPERxPoolRetire0_t; +} RegAPERxPoolRetire_t; #define REG_APE_RX_POOL_RETIRE_1 ((volatile BCM5719_APE_H_uint32_t*)0xc0010088) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ -#define APE_RX_POOL_RETIRE_1_TAIL_SHIFT 0u -#define APE_RX_POOL_RETIRE_1_TAIL_MASK 0xfffu -#define GET_APE_RX_POOL_RETIRE_1_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_RX_POOL_RETIRE_1_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_RX_POOL_RETIRE_1_HEAD_SHIFT 12u -#define APE_RX_POOL_RETIRE_1_HEAD_MASK 0xfff000u -#define GET_APE_RX_POOL_RETIRE_1_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_RX_POOL_RETIRE_1_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_RX_POOL_RETIRE_1_RETIRE_SHIFT 24u -#define APE_RX_POOL_RETIRE_1_RETIRE_MASK 0x1000000u -#define GET_APE_RX_POOL_RETIRE_1_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_APE_RX_POOL_RETIRE_1_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) -#define APE_RX_POOL_RETIRE_1_STATE_SHIFT 25u -#define APE_RX_POOL_RETIRE_1_STATE_MASK 0x6000000u -#define GET_APE_RX_POOL_RETIRE_1_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) -#define SET_APE_RX_POOL_RETIRE_1_STATE(__val__) (((__val__) << 25u) & 0x6000000u) -#define APE_RX_POOL_RETIRE_1_STATE_PROCESSING 0x0u -#define APE_RX_POOL_RETIRE_1_STATE_RETIRED_OK 0x1u -#define APE_RX_POOL_RETIRE_1_STATE_ERROR__FULL 0x2u -#define APE_RX_POOL_RETIRE_1_STATE_ERROR__IN_HALT 0x3u - -#define APE_RX_POOL_RETIRE_1_COUNT_SHIFT 27u -#define APE_RX_POOL_RETIRE_1_COUNT_MASK 0x78000000u -#define GET_APE_RX_POOL_RETIRE_1_COUNT(__reg__) (((__reg__) & 0x78000000) >> 27u) -#define SET_APE_RX_POOL_RETIRE_1_COUNT(__val__) (((__val__) << 27u) & 0x78000000u) - -/** @brief Register definition for @ref APE_t.RxPoolRetire1. */ -typedef register_container RegAPERxPoolRetire1_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 27, 4) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 27, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxPoolRetire1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxPoolRetire1_t() - { - /** @brief constructor for @ref APE_t.RxPoolRetire1. */ - r32.setName("RxPoolRetire1"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.Retire.setBaseRegister(&r32); - bits.Retire.setName("Retire"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - bits.Count.setBaseRegister(&r32); - bits.Count.setName("Count"); - } - RegAPERxPoolRetire1_t& operator=(const RegAPERxPoolRetire1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxPoolRetire1_t; - #define REG_APE_TX_TO_NET_POOL_MODE_STATUS_0 ((volatile BCM5719_APE_H_uint32_t*)0xc001008c) /* */ #define APE_TX_TO_NET_POOL_MODE_STATUS_0_HALT_SHIFT 0u #define APE_TX_TO_NET_POOL_MODE_STATUS_0_HALT_MASK 0x1u @@ -1390,7 +1086,7 @@ typedef register_container RegAPERxPoolRetire1_t { #define SET_APE_TX_TO_NET_POOL_MODE_STATUS_0_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) /** @brief Register definition for @ref APE_t.TxToNetPoolModeStatus0. */ -typedef register_container RegAPETxToNetPoolModeStatus0_t { +typedef register_container RegAPETxToNetPoolModeStatus_t { /** @brief 32bit direct register access. */ BCM5719_APE_H_uint32_t r32; @@ -1448,7 +1144,7 @@ typedef register_container RegAPETxToNetPoolModeStatus0_t { /** @brief Print register value. */ void print(void) { r32.print(); } - RegAPETxToNetPoolModeStatus0_t() + RegAPETxToNetPoolModeStatus_t() { /** @brief constructor for @ref APE_t.TxToNetPoolModeStatus0. */ r32.setName("TxToNetPoolModeStatus0"); @@ -1467,20 +1163,20 @@ typedef register_container RegAPETxToNetPoolModeStatus0_t { bits.FullCount.setBaseRegister(&r32); bits.FullCount.setName("FullCount"); } - RegAPETxToNetPoolModeStatus0_t& operator=(const RegAPETxToNetPoolModeStatus0_t& other) + RegAPETxToNetPoolModeStatus_t& operator=(const RegAPETxToNetPoolModeStatus_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ -} RegAPETxToNetPoolModeStatus0_t; +} RegAPETxToNetPoolModeStatus_t; #define REG_APE_TX_TO_NET_BUFFER_ALLOCATOR_0 ((volatile BCM5719_APE_H_uint32_t*)0xc0010090) /* */ #define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_INDEX_SHIFT 0u #define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_INDEX_MASK 0xfffu #define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_0_INDEX(__reg__) (((__reg__) & 0xfff) >> 0u) #define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_0_INDEX(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_INDEX_BLOCK_SIZE 0x80u +#define APE_TX_TO_NET_BUFFER_ALLOCATOR_INDEX_BLOCK_SIZE 0x80u #define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_REQUEST_ALLOCATION_SHIFT 12u #define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_REQUEST_ALLOCATION_MASK 0x1000u @@ -1490,14 +1186,14 @@ typedef register_container RegAPETxToNetPoolModeStatus0_t { #define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE_MASK 0x6000u #define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) #define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE_PROCESSING 0x0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE_ALLOCATION_OK 0x1u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE_ERROR__EMPTY 0x2u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_0_STATE_ERROR__IN_HALT 0x3u +#define APE_TX_TO_NET_BUFFER_ALLOCATOR_STATE_PROCESSING 0x0u +#define APE_TX_TO_NET_BUFFER_ALLOCATOR_STATE_ALLOCATION_OK 0x1u +#define APE_TX_TO_NET_BUFFER_ALLOCATOR_STATE_ERROR__EMPTY 0x2u +#define APE_TX_TO_NET_BUFFER_ALLOCATOR_STATE_ERROR__IN_HALT 0x3u /** @brief Register definition for @ref APE_t.TxToNetBufferAllocator0. */ -typedef register_container RegAPETxToNetBufferAllocator0_t { +typedef register_container RegAPETxToNetBufferAllocator_t { /** @brief 32bit direct register access. */ BCM5719_APE_H_uint32_t r32; @@ -1531,7 +1227,7 @@ typedef register_container RegAPETxToNetBufferAllocator0_t { /** @brief Print register value. */ void print(void) { r32.print(); } - RegAPETxToNetBufferAllocator0_t() + RegAPETxToNetBufferAllocator_t() { /** @brief constructor for @ref APE_t.TxToNetBufferAllocator0. */ r32.setName("TxToNetBufferAllocator0"); @@ -1542,13 +1238,13 @@ typedef register_container RegAPETxToNetBufferAllocator0_t { bits.State.setBaseRegister(&r32); bits.State.setName("State"); } - RegAPETxToNetBufferAllocator0_t& operator=(const RegAPETxToNetBufferAllocator0_t& other) + RegAPETxToNetBufferAllocator_t& operator=(const RegAPETxToNetBufferAllocator_t& other) { r32 = other.r32; return *this; } #endif /* CXX_SIMULATOR */ -} RegAPETxToNetBufferAllocator0_t; +} RegAPETxToNetBufferAllocator_t; #define REG_APE_TX_TO_NET_BUFFER_RETURN_0 ((volatile BCM5719_APE_H_uint32_t*)0xc0010094) /* */ /** @brief Register definition for @ref APE_t.TxToNetBufferReturn0. */ @@ -2124,1426 +1820,20 @@ typedef register_container RegAPECpuStatus_t { } RegAPECpuStatus_t; #define REG_APE_TX_TO_NET_POOL_MODE_STATUS_1 ((volatile BCM5719_APE_H_uint32_t*)0xc0010110) /* */ -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT_SHIFT 0u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT_MASK 0x1u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT_DONE_SHIFT 1u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT_DONE_MASK 0x2u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT_DONE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_HALT_DONE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_ENABLE_SHIFT 2u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_ENABLE_MASK 0x4u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_EMPTY_SHIFT 4u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_EMPTY_MASK 0x10u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_EMPTY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_EMPTY(__val__) (((__val__) << 4u) & 0x10u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_ERROR_SHIFT 5u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_ERROR_MASK 0x20u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_ERROR(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_ERROR(__val__) (((__val__) << 5u) & 0x20u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_RESET_SHIFT 6u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_RESET_MASK 0x40u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_RESET(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_RESET(__val__) (((__val__) << 6u) & 0x40u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_FULL_COUNT_SHIFT 8u -#define APE_TX_TO_NET_POOL_MODE_STATUS_1_FULL_COUNT_MASK 0xffff00u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_1_FULL_COUNT(__reg__) (((__reg__) & 0xffff00) >> 8u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_1_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) - -/** @brief Register definition for @ref APE_t.TxToNetPoolModeStatus1. */ -typedef register_container RegAPETxToNetPoolModeStatus1_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halt, 0, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief Must set Enable before the APE TX To Net Buffer Allocator will work. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enable, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Empty, 4, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Reset, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_24, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_24, 24, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Reset, 6, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Empty, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief Must set Enable before the APE TX To Net Buffer Allocator will work. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halt, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetPoolModeStatus1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetPoolModeStatus1_t() - { - /** @brief constructor for @ref APE_t.TxToNetPoolModeStatus1. */ - r32.setName("TxToNetPoolModeStatus1"); - bits.Halt.setBaseRegister(&r32); - bits.Halt.setName("Halt"); - bits.HaltDone.setBaseRegister(&r32); - bits.HaltDone.setName("HaltDone"); - bits.Enable.setBaseRegister(&r32); - bits.Enable.setName("Enable"); - bits.Empty.setBaseRegister(&r32); - bits.Empty.setName("Empty"); - bits.Error.setBaseRegister(&r32); - bits.Error.setName("Error"); - bits.Reset.setBaseRegister(&r32); - bits.Reset.setName("Reset"); - bits.FullCount.setBaseRegister(&r32); - bits.FullCount.setName("FullCount"); - } - RegAPETxToNetPoolModeStatus1_t& operator=(const RegAPETxToNetPoolModeStatus1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetPoolModeStatus1_t; - #define REG_APE_TX_TO_NET_BUFFER_ALLOCATOR_1 ((volatile BCM5719_APE_H_uint32_t*)0xc0010114) /* */ -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_INDEX_SHIFT 0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_INDEX_MASK 0xfffu -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_1_INDEX(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_1_INDEX(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_INDEX_BLOCK_SIZE 0x80u - -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_REQUEST_ALLOCATION_SHIFT 12u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_REQUEST_ALLOCATION_MASK 0x1000u -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_1_REQUEST_ALLOCATION(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_1_REQUEST_ALLOCATION(__val__) (((__val__) << 12u) & 0x1000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE_SHIFT 13u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE_MASK 0x6000u -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE_PROCESSING 0x0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE_ALLOCATION_OK 0x1u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE_ERROR__EMPTY 0x2u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_1_STATE_ERROR__IN_HALT 0x3u - - -/** @brief Register definition for @ref APE_t.TxToNetBufferAllocator1. */ -typedef register_container RegAPETxToNetBufferAllocator1_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Index, 0, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, RequestAllocation, 12, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 13, 2) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_15, 15, 17) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_15, 15, 17) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 13, 2) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, RequestAllocation, 12, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Index, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetBufferAllocator1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetBufferAllocator1_t() - { - /** @brief constructor for @ref APE_t.TxToNetBufferAllocator1. */ - r32.setName("TxToNetBufferAllocator1"); - bits.Index.setBaseRegister(&r32); - bits.Index.setName("Index"); - bits.RequestAllocation.setBaseRegister(&r32); - bits.RequestAllocation.setName("RequestAllocation"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - } - RegAPETxToNetBufferAllocator1_t& operator=(const RegAPETxToNetBufferAllocator1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetBufferAllocator1_t; - #define REG_APE_TX_TO_NET_DOORBELL_FUNC1 ((volatile BCM5719_APE_H_uint32_t*)0xc0010120) /* Written on APE TX to network after filling 0xA002 buffer with packet. */ -#define APE_TX_TO_NET_DOORBELL_FUNC1_TAIL_SHIFT 0u -#define APE_TX_TO_NET_DOORBELL_FUNC1_TAIL_MASK 0xfffu -#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_DOORBELL_FUNC1_HEAD_SHIFT 12u -#define APE_TX_TO_NET_DOORBELL_FUNC1_HEAD_MASK 0xfff000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH_MASK 0xf000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) -#define APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL_SHIFT 28u -#define APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL_MASK 0x10000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC1_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) - -/** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc1. */ -typedef register_container RegAPETxToNetDoorbellFunc1_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetDoorbellFunc1"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetDoorbellFunc1_t() - { - /** @brief constructor for @ref APE_t.TxToNetDoorbellFunc1. */ - r32.setName("TxToNetDoorbellFunc1"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.Length.setBaseRegister(&r32); - bits.Length.setName("Length"); - bits.TXQueueFull.setBaseRegister(&r32); - bits.TXQueueFull.setName("TXQueueFull"); - } - RegAPETxToNetDoorbellFunc1_t& operator=(const RegAPETxToNetDoorbellFunc1_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetDoorbellFunc1_t; - #define REG_APE_RXBUFOFFSET_FUNC2 ((volatile BCM5719_APE_H_uint32_t*)0xc0010200) /* This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. */ -#define APE_RXBUFOFFSET_FUNC2_TAIL_SHIFT 0u -#define APE_RXBUFOFFSET_FUNC2_TAIL_MASK 0xfffu -#define GET_APE_RXBUFOFFSET_FUNC2_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_RXBUFOFFSET_FUNC2_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_RXBUFOFFSET_FUNC2_HEAD_SHIFT 12u -#define APE_RXBUFOFFSET_FUNC2_HEAD_MASK 0xfff000u -#define GET_APE_RXBUFOFFSET_FUNC2_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_RXBUFOFFSET_FUNC2_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_RXBUFOFFSET_FUNC2_TO_HOST_SHIFT 24u -#define APE_RXBUFOFFSET_FUNC2_TO_HOST_MASK 0x1000000u -#define GET_APE_RXBUFOFFSET_FUNC2_TO_HOST(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_APE_RXBUFOFFSET_FUNC2_TO_HOST(__val__) (((__val__) << 24u) & 0x1000000u) -#define APE_RXBUFOFFSET_FUNC2_IP_FRAG_SHIFT 25u -#define APE_RXBUFOFFSET_FUNC2_IP_FRAG_MASK 0x2000000u -#define GET_APE_RXBUFOFFSET_FUNC2_IP_FRAG(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_APE_RXBUFOFFSET_FUNC2_IP_FRAG(__val__) (((__val__) << 25u) & 0x2000000u) -#define APE_RXBUFOFFSET_FUNC2_COUNT_SHIFT 26u -#define APE_RXBUFOFFSET_FUNC2_COUNT_MASK 0x3c000000u -#define GET_APE_RXBUFOFFSET_FUNC2_COUNT(__reg__) (((__reg__) & 0x3c000000) >> 26u) -#define SET_APE_RXBUFOFFSET_FUNC2_COUNT(__val__) (((__val__) << 26u) & 0x3c000000u) -#define APE_RXBUFOFFSET_FUNC2_VALID_SHIFT 30u -#define APE_RXBUFOFFSET_FUNC2_VALID_MASK 0x40000000u -#define GET_APE_RXBUFOFFSET_FUNC2_VALID(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_APE_RXBUFOFFSET_FUNC2_VALID(__val__) (((__val__) << 30u) & 0x40000000u) - -/** @brief Register definition for @ref APE_t.RxbufoffsetFunc2. */ -typedef register_container RegAPERxbufoffsetFunc2_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ToHost, 24, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPFrag, 25, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 26, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Valid, 30, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Valid, 30, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 26, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPFrag, 25, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ToHost, 24, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxbufoffsetFunc2"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxbufoffsetFunc2_t() - { - /** @brief constructor for @ref APE_t.RxbufoffsetFunc2. */ - r32.setName("RxbufoffsetFunc2"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.ToHost.setBaseRegister(&r32); - bits.ToHost.setName("ToHost"); - bits.IPFrag.setBaseRegister(&r32); - bits.IPFrag.setName("IPFrag"); - bits.Count.setBaseRegister(&r32); - bits.Count.setName("Count"); - bits.Valid.setBaseRegister(&r32); - bits.Valid.setName("Valid"); - } - RegAPERxbufoffsetFunc2_t& operator=(const RegAPERxbufoffsetFunc2_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxbufoffsetFunc2_t; - #define REG_APE_TX_TO_NET_DOORBELL_FUNC2 ((volatile BCM5719_APE_H_uint32_t*)0xc0010204) /* Written on APE TX to network after filling 0xA002 buffer with packet. */ -#define APE_TX_TO_NET_DOORBELL_FUNC2_TAIL_SHIFT 0u -#define APE_TX_TO_NET_DOORBELL_FUNC2_TAIL_MASK 0xfffu -#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_DOORBELL_FUNC2_HEAD_SHIFT 12u -#define APE_TX_TO_NET_DOORBELL_FUNC2_HEAD_MASK 0xfff000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH_MASK 0xf000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) -#define APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL_SHIFT 28u -#define APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL_MASK 0x10000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC2_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) - -/** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc2. */ -typedef register_container RegAPETxToNetDoorbellFunc2_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetDoorbellFunc2"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetDoorbellFunc2_t() - { - /** @brief constructor for @ref APE_t.TxToNetDoorbellFunc2. */ - r32.setName("TxToNetDoorbellFunc2"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.Length.setBaseRegister(&r32); - bits.Length.setName("Length"); - bits.TXQueueFull.setBaseRegister(&r32); - bits.TXQueueFull.setName("TXQueueFull"); - } - RegAPETxToNetDoorbellFunc2_t& operator=(const RegAPETxToNetDoorbellFunc2_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetDoorbellFunc2_t; - #define REG_APE_RX_POOL_MODE_STATUS_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0010214) /* */ -#define APE_RX_POOL_MODE_STATUS_2_HALT_SHIFT 0u -#define APE_RX_POOL_MODE_STATUS_2_HALT_MASK 0x1u -#define GET_APE_RX_POOL_MODE_STATUS_2_HALT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_RX_POOL_MODE_STATUS_2_HALT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_RX_POOL_MODE_STATUS_2_HALT_DONE_SHIFT 1u -#define APE_RX_POOL_MODE_STATUS_2_HALT_DONE_MASK 0x2u -#define GET_APE_RX_POOL_MODE_STATUS_2_HALT_DONE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_RX_POOL_MODE_STATUS_2_HALT_DONE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_RX_POOL_MODE_STATUS_2_ENABLE_SHIFT 2u -#define APE_RX_POOL_MODE_STATUS_2_ENABLE_MASK 0x4u -#define GET_APE_RX_POOL_MODE_STATUS_2_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_RX_POOL_MODE_STATUS_2_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_RX_POOL_MODE_STATUS_2_EMPTY_SHIFT 4u -#define APE_RX_POOL_MODE_STATUS_2_EMPTY_MASK 0x10u -#define GET_APE_RX_POOL_MODE_STATUS_2_EMPTY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_RX_POOL_MODE_STATUS_2_EMPTY(__val__) (((__val__) << 4u) & 0x10u) -#define APE_RX_POOL_MODE_STATUS_2_ERROR_SHIFT 5u -#define APE_RX_POOL_MODE_STATUS_2_ERROR_MASK 0x20u -#define GET_APE_RX_POOL_MODE_STATUS_2_ERROR(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_RX_POOL_MODE_STATUS_2_ERROR(__val__) (((__val__) << 5u) & 0x20u) -#define APE_RX_POOL_MODE_STATUS_2_RESET_SHIFT 6u -#define APE_RX_POOL_MODE_STATUS_2_RESET_MASK 0x40u -#define GET_APE_RX_POOL_MODE_STATUS_2_RESET(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_RX_POOL_MODE_STATUS_2_RESET(__val__) (((__val__) << 6u) & 0x40u) -#define APE_RX_POOL_MODE_STATUS_2_FULL_COUNT_SHIFT 8u -#define APE_RX_POOL_MODE_STATUS_2_FULL_COUNT_MASK 0xffff00u -#define GET_APE_RX_POOL_MODE_STATUS_2_FULL_COUNT(__reg__) (((__reg__) & 0xffff00) >> 8u) -#define SET_APE_RX_POOL_MODE_STATUS_2_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) - -/** @brief Register definition for @ref APE_t.RxPoolModeStatus2. */ -typedef register_container RegAPERxPoolModeStatus2_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halt, 0, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enable, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Empty, 4, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Reset, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_24, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_24, 24, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Reset, 6, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Empty, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halt, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxPoolModeStatus2"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxPoolModeStatus2_t() - { - /** @brief constructor for @ref APE_t.RxPoolModeStatus2. */ - r32.setName("RxPoolModeStatus2"); - bits.Halt.setBaseRegister(&r32); - bits.Halt.setName("Halt"); - bits.HaltDone.setBaseRegister(&r32); - bits.HaltDone.setName("HaltDone"); - bits.Enable.setBaseRegister(&r32); - bits.Enable.setName("Enable"); - bits.Empty.setBaseRegister(&r32); - bits.Empty.setName("Empty"); - bits.Error.setBaseRegister(&r32); - bits.Error.setName("Error"); - bits.Reset.setBaseRegister(&r32); - bits.Reset.setName("Reset"); - bits.FullCount.setBaseRegister(&r32); - bits.FullCount.setName("FullCount"); - } - RegAPERxPoolModeStatus2_t& operator=(const RegAPERxPoolModeStatus2_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxPoolModeStatus2_t; - #define REG_APE_RX_POOL_RETIRE_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0010218) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ -#define APE_RX_POOL_RETIRE_2_TAIL_SHIFT 0u -#define APE_RX_POOL_RETIRE_2_TAIL_MASK 0xfffu -#define GET_APE_RX_POOL_RETIRE_2_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_RX_POOL_RETIRE_2_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_RX_POOL_RETIRE_2_HEAD_SHIFT 12u -#define APE_RX_POOL_RETIRE_2_HEAD_MASK 0xfff000u -#define GET_APE_RX_POOL_RETIRE_2_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_RX_POOL_RETIRE_2_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_RX_POOL_RETIRE_2_RETIRE_SHIFT 24u -#define APE_RX_POOL_RETIRE_2_RETIRE_MASK 0x1000000u -#define GET_APE_RX_POOL_RETIRE_2_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_APE_RX_POOL_RETIRE_2_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) -#define APE_RX_POOL_RETIRE_2_STATE_SHIFT 25u -#define APE_RX_POOL_RETIRE_2_STATE_MASK 0x6000000u -#define GET_APE_RX_POOL_RETIRE_2_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) -#define SET_APE_RX_POOL_RETIRE_2_STATE(__val__) (((__val__) << 25u) & 0x6000000u) -#define APE_RX_POOL_RETIRE_2_STATE_PROCESSING 0x0u -#define APE_RX_POOL_RETIRE_2_STATE_RETIRED_OK 0x1u -#define APE_RX_POOL_RETIRE_2_STATE_ERROR__FULL 0x2u -#define APE_RX_POOL_RETIRE_2_STATE_ERROR__IN_HALT 0x3u - -#define APE_RX_POOL_RETIRE_2_COUNT_SHIFT 27u -#define APE_RX_POOL_RETIRE_2_COUNT_MASK 0x78000000u -#define GET_APE_RX_POOL_RETIRE_2_COUNT(__reg__) (((__reg__) & 0x78000000) >> 27u) -#define SET_APE_RX_POOL_RETIRE_2_COUNT(__val__) (((__val__) << 27u) & 0x78000000u) - -/** @brief Register definition for @ref APE_t.RxPoolRetire2. */ -typedef register_container RegAPERxPoolRetire2_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 27, 4) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 27, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxPoolRetire2"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxPoolRetire2_t() - { - /** @brief constructor for @ref APE_t.RxPoolRetire2. */ - r32.setName("RxPoolRetire2"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.Retire.setBaseRegister(&r32); - bits.Retire.setName("Retire"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - bits.Count.setBaseRegister(&r32); - bits.Count.setName("Count"); - } - RegAPERxPoolRetire2_t& operator=(const RegAPERxPoolRetire2_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxPoolRetire2_t; - #define REG_APE_TX_TO_NET_POOL_MODE_STATUS_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0010220) /* */ -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT_SHIFT 0u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT_MASK 0x1u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT_DONE_SHIFT 1u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT_DONE_MASK 0x2u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT_DONE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_HALT_DONE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_ENABLE_SHIFT 2u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_ENABLE_MASK 0x4u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_EMPTY_SHIFT 4u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_EMPTY_MASK 0x10u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_EMPTY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_EMPTY(__val__) (((__val__) << 4u) & 0x10u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_ERROR_SHIFT 5u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_ERROR_MASK 0x20u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_ERROR(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_ERROR(__val__) (((__val__) << 5u) & 0x20u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_RESET_SHIFT 6u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_RESET_MASK 0x40u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_RESET(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_RESET(__val__) (((__val__) << 6u) & 0x40u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_FULL_COUNT_SHIFT 8u -#define APE_TX_TO_NET_POOL_MODE_STATUS_2_FULL_COUNT_MASK 0xffff00u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_2_FULL_COUNT(__reg__) (((__reg__) & 0xffff00) >> 8u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_2_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) - -/** @brief Register definition for @ref APE_t.TxToNetPoolModeStatus2. */ -typedef register_container RegAPETxToNetPoolModeStatus2_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halt, 0, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief Must set Enable before the APE TX To Net Buffer Allocator will work. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enable, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Empty, 4, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Reset, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_24, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_24, 24, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Reset, 6, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Empty, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief Must set Enable before the APE TX To Net Buffer Allocator will work. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halt, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetPoolModeStatus2"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetPoolModeStatus2_t() - { - /** @brief constructor for @ref APE_t.TxToNetPoolModeStatus2. */ - r32.setName("TxToNetPoolModeStatus2"); - bits.Halt.setBaseRegister(&r32); - bits.Halt.setName("Halt"); - bits.HaltDone.setBaseRegister(&r32); - bits.HaltDone.setName("HaltDone"); - bits.Enable.setBaseRegister(&r32); - bits.Enable.setName("Enable"); - bits.Empty.setBaseRegister(&r32); - bits.Empty.setName("Empty"); - bits.Error.setBaseRegister(&r32); - bits.Error.setName("Error"); - bits.Reset.setBaseRegister(&r32); - bits.Reset.setName("Reset"); - bits.FullCount.setBaseRegister(&r32); - bits.FullCount.setName("FullCount"); - } - RegAPETxToNetPoolModeStatus2_t& operator=(const RegAPETxToNetPoolModeStatus2_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetPoolModeStatus2_t; - #define REG_APE_TX_TO_NET_BUFFER_ALLOCATOR_2 ((volatile BCM5719_APE_H_uint32_t*)0xc0010224) /* */ -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_INDEX_SHIFT 0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_INDEX_MASK 0xfffu -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_2_INDEX(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_2_INDEX(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_INDEX_BLOCK_SIZE 0x80u - -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_REQUEST_ALLOCATION_SHIFT 12u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_REQUEST_ALLOCATION_MASK 0x1000u -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_2_REQUEST_ALLOCATION(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_2_REQUEST_ALLOCATION(__val__) (((__val__) << 12u) & 0x1000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE_SHIFT 13u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE_MASK 0x6000u -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE_PROCESSING 0x0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE_ALLOCATION_OK 0x1u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE_ERROR__EMPTY 0x2u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_2_STATE_ERROR__IN_HALT 0x3u - - -/** @brief Register definition for @ref APE_t.TxToNetBufferAllocator2. */ -typedef register_container RegAPETxToNetBufferAllocator2_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Index, 0, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, RequestAllocation, 12, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 13, 2) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_15, 15, 17) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_15, 15, 17) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 13, 2) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, RequestAllocation, 12, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Index, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetBufferAllocator2"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetBufferAllocator2_t() - { - /** @brief constructor for @ref APE_t.TxToNetBufferAllocator2. */ - r32.setName("TxToNetBufferAllocator2"); - bits.Index.setBaseRegister(&r32); - bits.Index.setName("Index"); - bits.RequestAllocation.setBaseRegister(&r32); - bits.RequestAllocation.setName("RequestAllocation"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - } - RegAPETxToNetBufferAllocator2_t& operator=(const RegAPETxToNetBufferAllocator2_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetBufferAllocator2_t; - #define REG_APE_RXBUFOFFSET_FUNC3 ((volatile BCM5719_APE_H_uint32_t*)0xc0010300) /* This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. */ -#define APE_RXBUFOFFSET_FUNC3_TAIL_SHIFT 0u -#define APE_RXBUFOFFSET_FUNC3_TAIL_MASK 0xfffu -#define GET_APE_RXBUFOFFSET_FUNC3_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_RXBUFOFFSET_FUNC3_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_RXBUFOFFSET_FUNC3_HEAD_SHIFT 12u -#define APE_RXBUFOFFSET_FUNC3_HEAD_MASK 0xfff000u -#define GET_APE_RXBUFOFFSET_FUNC3_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_RXBUFOFFSET_FUNC3_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_RXBUFOFFSET_FUNC3_TO_HOST_SHIFT 24u -#define APE_RXBUFOFFSET_FUNC3_TO_HOST_MASK 0x1000000u -#define GET_APE_RXBUFOFFSET_FUNC3_TO_HOST(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_APE_RXBUFOFFSET_FUNC3_TO_HOST(__val__) (((__val__) << 24u) & 0x1000000u) -#define APE_RXBUFOFFSET_FUNC3_IP_FRAG_SHIFT 25u -#define APE_RXBUFOFFSET_FUNC3_IP_FRAG_MASK 0x2000000u -#define GET_APE_RXBUFOFFSET_FUNC3_IP_FRAG(__reg__) (((__reg__) & 0x2000000) >> 25u) -#define SET_APE_RXBUFOFFSET_FUNC3_IP_FRAG(__val__) (((__val__) << 25u) & 0x2000000u) -#define APE_RXBUFOFFSET_FUNC3_COUNT_SHIFT 26u -#define APE_RXBUFOFFSET_FUNC3_COUNT_MASK 0x3c000000u -#define GET_APE_RXBUFOFFSET_FUNC3_COUNT(__reg__) (((__reg__) & 0x3c000000) >> 26u) -#define SET_APE_RXBUFOFFSET_FUNC3_COUNT(__val__) (((__val__) << 26u) & 0x3c000000u) -#define APE_RXBUFOFFSET_FUNC3_VALID_SHIFT 30u -#define APE_RXBUFOFFSET_FUNC3_VALID_MASK 0x40000000u -#define GET_APE_RXBUFOFFSET_FUNC3_VALID(__reg__) (((__reg__) & 0x40000000) >> 30u) -#define SET_APE_RXBUFOFFSET_FUNC3_VALID(__val__) (((__val__) << 30u) & 0x40000000u) - -/** @brief Register definition for @ref APE_t.RxbufoffsetFunc3. */ -typedef register_container RegAPERxbufoffsetFunc3_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ToHost, 24, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPFrag, 25, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 26, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Valid, 30, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Valid, 30, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 26, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, IPFrag, 25, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, ToHost, 24, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxbufoffsetFunc3"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxbufoffsetFunc3_t() - { - /** @brief constructor for @ref APE_t.RxbufoffsetFunc3. */ - r32.setName("RxbufoffsetFunc3"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.ToHost.setBaseRegister(&r32); - bits.ToHost.setName("ToHost"); - bits.IPFrag.setBaseRegister(&r32); - bits.IPFrag.setName("IPFrag"); - bits.Count.setBaseRegister(&r32); - bits.Count.setName("Count"); - bits.Valid.setBaseRegister(&r32); - bits.Valid.setName("Valid"); - } - RegAPERxbufoffsetFunc3_t& operator=(const RegAPERxbufoffsetFunc3_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxbufoffsetFunc3_t; - #define REG_APE_TX_TO_NET_DOORBELL_FUNC3 ((volatile BCM5719_APE_H_uint32_t*)0xc0010304) /* Written on APE TX to network after filling 0xA002 buffer with packet. */ -#define APE_TX_TO_NET_DOORBELL_FUNC3_TAIL_SHIFT 0u -#define APE_TX_TO_NET_DOORBELL_FUNC3_TAIL_MASK 0xfffu -#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_DOORBELL_FUNC3_HEAD_SHIFT 12u -#define APE_TX_TO_NET_DOORBELL_FUNC3_HEAD_MASK 0xfff000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH_SHIFT 24u -#define APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH_MASK 0xf000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH(__reg__) (((__reg__) & 0xf000000) >> 24u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_LENGTH(__val__) (((__val__) << 24u) & 0xf000000u) -#define APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL_SHIFT 28u -#define APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL_MASK 0x10000000u -#define GET_APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL(__reg__) (((__reg__) & 0x10000000) >> 28u) -#define SET_APE_TX_TO_NET_DOORBELL_FUNC3_TX_QUEUE_FULL(__val__) (((__val__) << 28u) & 0x10000000u) - -/** @brief Register definition for @ref APE_t.TxToNetDoorbellFunc3. */ -typedef register_container RegAPETxToNetDoorbellFunc3_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_29, 29, 3) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, TXQueueFull, 28, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Length, 24, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetDoorbellFunc3"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetDoorbellFunc3_t() - { - /** @brief constructor for @ref APE_t.TxToNetDoorbellFunc3. */ - r32.setName("TxToNetDoorbellFunc3"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.Length.setBaseRegister(&r32); - bits.Length.setName("Length"); - bits.TXQueueFull.setBaseRegister(&r32); - bits.TXQueueFull.setName("TXQueueFull"); - } - RegAPETxToNetDoorbellFunc3_t& operator=(const RegAPETxToNetDoorbellFunc3_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetDoorbellFunc3_t; - #define REG_APE_RX_POOL_MODE_STATUS_3 ((volatile BCM5719_APE_H_uint32_t*)0xc0010314) /* */ -#define APE_RX_POOL_MODE_STATUS_3_HALT_SHIFT 0u -#define APE_RX_POOL_MODE_STATUS_3_HALT_MASK 0x1u -#define GET_APE_RX_POOL_MODE_STATUS_3_HALT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_RX_POOL_MODE_STATUS_3_HALT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_RX_POOL_MODE_STATUS_3_HALT_DONE_SHIFT 1u -#define APE_RX_POOL_MODE_STATUS_3_HALT_DONE_MASK 0x2u -#define GET_APE_RX_POOL_MODE_STATUS_3_HALT_DONE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_RX_POOL_MODE_STATUS_3_HALT_DONE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_RX_POOL_MODE_STATUS_3_ENABLE_SHIFT 2u -#define APE_RX_POOL_MODE_STATUS_3_ENABLE_MASK 0x4u -#define GET_APE_RX_POOL_MODE_STATUS_3_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_RX_POOL_MODE_STATUS_3_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_RX_POOL_MODE_STATUS_3_EMPTY_SHIFT 4u -#define APE_RX_POOL_MODE_STATUS_3_EMPTY_MASK 0x10u -#define GET_APE_RX_POOL_MODE_STATUS_3_EMPTY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_RX_POOL_MODE_STATUS_3_EMPTY(__val__) (((__val__) << 4u) & 0x10u) -#define APE_RX_POOL_MODE_STATUS_3_ERROR_SHIFT 5u -#define APE_RX_POOL_MODE_STATUS_3_ERROR_MASK 0x20u -#define GET_APE_RX_POOL_MODE_STATUS_3_ERROR(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_RX_POOL_MODE_STATUS_3_ERROR(__val__) (((__val__) << 5u) & 0x20u) -#define APE_RX_POOL_MODE_STATUS_3_RESET_SHIFT 6u -#define APE_RX_POOL_MODE_STATUS_3_RESET_MASK 0x40u -#define GET_APE_RX_POOL_MODE_STATUS_3_RESET(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_RX_POOL_MODE_STATUS_3_RESET(__val__) (((__val__) << 6u) & 0x40u) -#define APE_RX_POOL_MODE_STATUS_3_FULL_COUNT_SHIFT 8u -#define APE_RX_POOL_MODE_STATUS_3_FULL_COUNT_MASK 0xffff00u -#define GET_APE_RX_POOL_MODE_STATUS_3_FULL_COUNT(__reg__) (((__reg__) & 0xffff00) >> 8u) -#define SET_APE_RX_POOL_MODE_STATUS_3_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) - -/** @brief Register definition for @ref APE_t.RxPoolModeStatus3. */ -typedef register_container RegAPERxPoolModeStatus3_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halt, 0, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enable, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Empty, 4, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Reset, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_24, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_24, 24, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Reset, 6, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Empty, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halt, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxPoolModeStatus3"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxPoolModeStatus3_t() - { - /** @brief constructor for @ref APE_t.RxPoolModeStatus3. */ - r32.setName("RxPoolModeStatus3"); - bits.Halt.setBaseRegister(&r32); - bits.Halt.setName("Halt"); - bits.HaltDone.setBaseRegister(&r32); - bits.HaltDone.setName("HaltDone"); - bits.Enable.setBaseRegister(&r32); - bits.Enable.setName("Enable"); - bits.Empty.setBaseRegister(&r32); - bits.Empty.setName("Empty"); - bits.Error.setBaseRegister(&r32); - bits.Error.setName("Error"); - bits.Reset.setBaseRegister(&r32); - bits.Reset.setName("Reset"); - bits.FullCount.setBaseRegister(&r32); - bits.FullCount.setName("FullCount"); - } - RegAPERxPoolModeStatus3_t& operator=(const RegAPERxPoolModeStatus3_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxPoolModeStatus3_t; - #define REG_APE_RX_POOL_RETIRE_3 ((volatile BCM5719_APE_H_uint32_t*)0xc0010318) /* Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ -#define APE_RX_POOL_RETIRE_3_TAIL_SHIFT 0u -#define APE_RX_POOL_RETIRE_3_TAIL_MASK 0xfffu -#define GET_APE_RX_POOL_RETIRE_3_TAIL(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_RX_POOL_RETIRE_3_TAIL(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_RX_POOL_RETIRE_3_HEAD_SHIFT 12u -#define APE_RX_POOL_RETIRE_3_HEAD_MASK 0xfff000u -#define GET_APE_RX_POOL_RETIRE_3_HEAD(__reg__) (((__reg__) & 0xfff000) >> 12u) -#define SET_APE_RX_POOL_RETIRE_3_HEAD(__val__) (((__val__) << 12u) & 0xfff000u) -#define APE_RX_POOL_RETIRE_3_RETIRE_SHIFT 24u -#define APE_RX_POOL_RETIRE_3_RETIRE_MASK 0x1000000u -#define GET_APE_RX_POOL_RETIRE_3_RETIRE(__reg__) (((__reg__) & 0x1000000) >> 24u) -#define SET_APE_RX_POOL_RETIRE_3_RETIRE(__val__) (((__val__) << 24u) & 0x1000000u) -#define APE_RX_POOL_RETIRE_3_STATE_SHIFT 25u -#define APE_RX_POOL_RETIRE_3_STATE_MASK 0x6000000u -#define GET_APE_RX_POOL_RETIRE_3_STATE(__reg__) (((__reg__) & 0x6000000) >> 25u) -#define SET_APE_RX_POOL_RETIRE_3_STATE(__val__) (((__val__) << 25u) & 0x6000000u) -#define APE_RX_POOL_RETIRE_3_STATE_PROCESSING 0x0u -#define APE_RX_POOL_RETIRE_3_STATE_RETIRED_OK 0x1u -#define APE_RX_POOL_RETIRE_3_STATE_ERROR__FULL 0x2u -#define APE_RX_POOL_RETIRE_3_STATE_ERROR__IN_HALT 0x3u - -#define APE_RX_POOL_RETIRE_3_COUNT_SHIFT 27u -#define APE_RX_POOL_RETIRE_3_COUNT_MASK 0x78000000u -#define GET_APE_RX_POOL_RETIRE_3_COUNT(__reg__) (((__reg__) & 0x78000000) >> 27u) -#define SET_APE_RX_POOL_RETIRE_3_COUNT(__val__) (((__val__) << 27u) & 0x78000000u) - -/** @brief Register definition for @ref APE_t.RxPoolRetire3. */ -typedef register_container RegAPERxPoolRetire3_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 27, 4) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_31, 31, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Count, 27, 4) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 25, 2) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Retire, 24, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Head, 12, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Tail, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "RxPoolRetire3"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPERxPoolRetire3_t() - { - /** @brief constructor for @ref APE_t.RxPoolRetire3. */ - r32.setName("RxPoolRetire3"); - bits.Tail.setBaseRegister(&r32); - bits.Tail.setName("Tail"); - bits.Head.setBaseRegister(&r32); - bits.Head.setName("Head"); - bits.Retire.setBaseRegister(&r32); - bits.Retire.setName("Retire"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - bits.Count.setBaseRegister(&r32); - bits.Count.setName("Count"); - } - RegAPERxPoolRetire3_t& operator=(const RegAPERxPoolRetire3_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPERxPoolRetire3_t; - #define REG_APE_TX_TO_NET_POOL_MODE_STATUS_3 ((volatile BCM5719_APE_H_uint32_t*)0xc0010320) /* */ -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT_SHIFT 0u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT_MASK 0x1u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT(__val__) (((__val__) << 0u) & 0x1u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT_DONE_SHIFT 1u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT_DONE_MASK 0x2u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT_DONE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_HALT_DONE(__val__) (((__val__) << 1u) & 0x2u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_ENABLE_SHIFT 2u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_ENABLE_MASK 0x4u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_EMPTY_SHIFT 4u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_EMPTY_MASK 0x10u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_EMPTY(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_EMPTY(__val__) (((__val__) << 4u) & 0x10u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_ERROR_SHIFT 5u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_ERROR_MASK 0x20u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_ERROR(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_ERROR(__val__) (((__val__) << 5u) & 0x20u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_RESET_SHIFT 6u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_RESET_MASK 0x40u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_RESET(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_RESET(__val__) (((__val__) << 6u) & 0x40u) -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_FULL_COUNT_SHIFT 8u -#define APE_TX_TO_NET_POOL_MODE_STATUS_3_FULL_COUNT_MASK 0xffff00u -#define GET_APE_TX_TO_NET_POOL_MODE_STATUS_3_FULL_COUNT(__reg__) (((__reg__) & 0xffff00) >> 8u) -#define SET_APE_TX_TO_NET_POOL_MODE_STATUS_3_FULL_COUNT(__val__) (((__val__) << 8u) & 0xffff00u) - -/** @brief Register definition for @ref APE_t.TxToNetPoolModeStatus3. */ -typedef register_container RegAPETxToNetPoolModeStatus3_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halt, 0, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief Must set Enable before the APE TX To Net Buffer Allocator will work. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enable, 2, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Empty, 4, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Reset, 6, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_24, 24, 8) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_24, 24, 8) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, FullCount, 8, 16) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_7_7, 7, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Reset, 6, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Error, 5, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Empty, 4, 1) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_3_3, 3, 1) - /** @brief Must set Enable before the APE TX To Net Buffer Allocator will work. */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Enable, 2, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, HaltDone, 1, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Halt, 0, 1) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetPoolModeStatus3"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetPoolModeStatus3_t() - { - /** @brief constructor for @ref APE_t.TxToNetPoolModeStatus3. */ - r32.setName("TxToNetPoolModeStatus3"); - bits.Halt.setBaseRegister(&r32); - bits.Halt.setName("Halt"); - bits.HaltDone.setBaseRegister(&r32); - bits.HaltDone.setName("HaltDone"); - bits.Enable.setBaseRegister(&r32); - bits.Enable.setName("Enable"); - bits.Empty.setBaseRegister(&r32); - bits.Empty.setName("Empty"); - bits.Error.setBaseRegister(&r32); - bits.Error.setName("Error"); - bits.Reset.setBaseRegister(&r32); - bits.Reset.setName("Reset"); - bits.FullCount.setBaseRegister(&r32); - bits.FullCount.setName("FullCount"); - } - RegAPETxToNetPoolModeStatus3_t& operator=(const RegAPETxToNetPoolModeStatus3_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetPoolModeStatus3_t; - #define REG_APE_TX_TO_NET_BUFFER_ALLOCATOR_3 ((volatile BCM5719_APE_H_uint32_t*)0xc0010324) /* */ -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_INDEX_SHIFT 0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_INDEX_MASK 0xfffu -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_3_INDEX(__reg__) (((__reg__) & 0xfff) >> 0u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_3_INDEX(__val__) (((__val__) << 0u) & 0xfffu) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_INDEX_BLOCK_SIZE 0x80u - -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_REQUEST_ALLOCATION_SHIFT 12u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_REQUEST_ALLOCATION_MASK 0x1000u -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_3_REQUEST_ALLOCATION(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_3_REQUEST_ALLOCATION(__val__) (((__val__) << 12u) & 0x1000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE_SHIFT 13u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE_MASK 0x6000u -#define GET_APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE(__reg__) (((__reg__) & 0x6000) >> 13u) -#define SET_APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE(__val__) (((__val__) << 13u) & 0x6000u) -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE_PROCESSING 0x0u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE_ALLOCATION_OK 0x1u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE_ERROR__EMPTY 0x2u -#define APE_TX_TO_NET_BUFFER_ALLOCATOR_3_STATE_ERROR__IN_HALT 0x3u - - -/** @brief Register definition for @ref APE_t.TxToNetBufferAllocator3. */ -typedef register_container RegAPETxToNetBufferAllocator3_t { - /** @brief 32bit direct register access. */ - BCM5719_APE_H_uint32_t r32; - - BITFIELD_BEGIN(BCM5719_APE_H_uint32_t, bits) -#if defined(__LITTLE_ENDIAN__) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Index, 0, 12) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, RequestAllocation, 12, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 13, 2) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_15, 15, 17) -#elif defined(__BIG_ENDIAN__) - /** @brief Padding */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, reserved_31_15, 15, 17) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, State, 13, 2) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, RequestAllocation, 12, 1) - /** @brief */ - BITFIELD_MEMBER(BCM5719_APE_H_uint32_t, Index, 0, 12) -#else -#error Unknown Endian -#endif - BITFIELD_END(BCM5719_APE_H_uint32_t, bits) -#ifdef CXX_SIMULATOR - /** @brief Register name for use with the simulator. */ - const char* getName(void) { return "TxToNetBufferAllocator3"; } - - /** @brief Print register value. */ - void print(void) { r32.print(); } - - RegAPETxToNetBufferAllocator3_t() - { - /** @brief constructor for @ref APE_t.TxToNetBufferAllocator3. */ - r32.setName("TxToNetBufferAllocator3"); - bits.Index.setBaseRegister(&r32); - bits.Index.setName("Index"); - bits.RequestAllocation.setBaseRegister(&r32); - bits.RequestAllocation.setName("RequestAllocation"); - bits.State.setBaseRegister(&r32); - bits.State.setName("State"); - } - RegAPETxToNetBufferAllocator3_t& operator=(const RegAPETxToNetBufferAllocator3_t& other) - { - r32 = other.r32; - return *this; - } -#endif /* CXX_SIMULATOR */ -} RegAPETxToNetBufferAllocator3_t; - /** @brief Component definition for @ref APE. */ typedef struct APE_t { /** @brief More of these bits can be found in diagnostic utilities, but they don't seem too interesting. */ @@ -3562,13 +1852,13 @@ typedef struct APE_t { BCM5719_APE_H_uint32_t reserved_16[1]; /** @brief This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. The fields are block numbers (block size 128 bytes). */ - RegAPERxbufoffsetFunc0_t RxbufoffsetFunc0; + RegAPERxbufoffset_t RxbufoffsetFunc0; /** @brief This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. */ - RegAPERxbufoffsetFunc1_t RxbufoffsetFunc1; + RegAPERxbufoffset_t RxbufoffsetFunc1; /** @brief Written on APE TX to network after filling 0xA002 buffer with packet. */ - RegAPETxToNetDoorbellFunc0_t TxToNetDoorbellFunc0; + RegAPETxToNetDoorbell_t TxToNetDoorbellFunc0; /** @brief APE TX Status. */ RegAPETxState0_t TxState0; @@ -3592,25 +1882,25 @@ typedef struct APE_t { BCM5719_APE_H_uint32_t reserved_80[10]; /** @brief */ - RegAPERxPoolModeStatus0_t RxPoolModeStatus0; + RegAPERxPoolModeStatus_t RxPoolModeStatus0; /** @brief */ - RegAPERxPoolModeStatus1_t RxPoolModeStatus1; + RegAPERxPoolModeStatus_t RxPoolModeStatus1; /** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ - RegAPERxPoolRetire0_t RxPoolRetire0; + RegAPERxPoolRetire_t RxPoolRetire0; /** @brief Reserved bytes to pad out data structure. */ BCM5719_APE_H_uint32_t reserved_132[1]; /** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ - RegAPERxPoolRetire1_t RxPoolRetire1; + RegAPERxPoolRetire_t RxPoolRetire1; /** @brief */ - RegAPETxToNetPoolModeStatus0_t TxToNetPoolModeStatus0; + RegAPETxToNetPoolModeStatus_t TxToNetPoolModeStatus0; /** @brief */ - RegAPETxToNetBufferAllocator0_t TxToNetBufferAllocator0; + RegAPETxToNetBufferAllocator_t TxToNetBufferAllocator0; /** @brief */ RegAPETxToNetBufferReturn0_t TxToNetBufferReturn0; @@ -3667,70 +1957,70 @@ typedef struct APE_t { BCM5719_APE_H_uint32_t reserved_268[1]; /** @brief */ - RegAPETxToNetPoolModeStatus1_t TxToNetPoolModeStatus1; + RegAPETxToNetPoolModeStatus_t TxToNetPoolModeStatus1; /** @brief */ - RegAPETxToNetBufferAllocator1_t TxToNetBufferAllocator1; + RegAPETxToNetBufferAllocator_t TxToNetBufferAllocator1; /** @brief Reserved bytes to pad out data structure. */ BCM5719_APE_H_uint32_t reserved_280[2]; /** @brief Written on APE TX to network after filling 0xA002 buffer with packet. */ - RegAPETxToNetDoorbellFunc1_t TxToNetDoorbellFunc1; + RegAPETxToNetDoorbell_t TxToNetDoorbellFunc1; /** @brief Reserved bytes to pad out data structure. */ BCM5719_APE_H_uint32_t reserved_292[55]; /** @brief This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. */ - RegAPERxbufoffsetFunc2_t RxbufoffsetFunc2; + RegAPERxbufoffset_t RxbufoffsetFunc2; /** @brief Written on APE TX to network after filling 0xA002 buffer with packet. */ - RegAPETxToNetDoorbellFunc2_t TxToNetDoorbellFunc2; + RegAPETxToNetDoorbell_t TxToNetDoorbellFunc2; /** @brief Reserved bytes to pad out data structure. */ BCM5719_APE_H_uint32_t reserved_520[3]; /** @brief */ - RegAPERxPoolModeStatus2_t RxPoolModeStatus2; + RegAPERxPoolModeStatus_t RxPoolModeStatus2; /** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ - RegAPERxPoolRetire2_t RxPoolRetire2; + RegAPERxPoolRetire_t RxPoolRetire2; /** @brief Reserved bytes to pad out data structure. */ BCM5719_APE_H_uint32_t reserved_540[1]; /** @brief */ - RegAPETxToNetPoolModeStatus2_t TxToNetPoolModeStatus2; + RegAPETxToNetPoolModeStatus_t TxToNetPoolModeStatus2; /** @brief */ - RegAPETxToNetBufferAllocator2_t TxToNetBufferAllocator2; + RegAPETxToNetBufferAllocator_t TxToNetBufferAllocator2; /** @brief Reserved bytes to pad out data structure. */ BCM5719_APE_H_uint32_t reserved_552[54]; /** @brief This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. */ - RegAPERxbufoffsetFunc3_t RxbufoffsetFunc3; + RegAPERxbufoffset_t RxbufoffsetFunc3; /** @brief Written on APE TX to network after filling 0xA002 buffer with packet. */ - RegAPETxToNetDoorbellFunc3_t TxToNetDoorbellFunc3; + RegAPETxToNetDoorbell_t TxToNetDoorbellFunc3; /** @brief Reserved bytes to pad out data structure. */ BCM5719_APE_H_uint32_t reserved_776[3]; /** @brief */ - RegAPERxPoolModeStatus3_t RxPoolModeStatus3; + RegAPERxPoolModeStatus_t RxPoolModeStatus3; /** @brief Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame. */ - RegAPERxPoolRetire3_t RxPoolRetire3; + RegAPERxPoolRetire_t RxPoolRetire3; /** @brief Reserved bytes to pad out data structure. */ BCM5719_APE_H_uint32_t reserved_796[1]; /** @brief */ - RegAPETxToNetPoolModeStatus3_t TxToNetPoolModeStatus3; + RegAPETxToNetPoolModeStatus_t TxToNetPoolModeStatus3; /** @brief */ - RegAPETxToNetBufferAllocator3_t TxToNetBufferAllocator3; + RegAPETxToNetBufferAllocator_t TxToNetBufferAllocator3; #ifdef CXX_SIMULATOR APE_t() diff --git a/include/bcm5719_SHM_CHANNEL1.h b/include/bcm5719_SHM_CHANNEL1.h index df6b19c..3211bfc 100644 --- a/include/bcm5719_SHM_CHANNEL1.h +++ b/include/bcm5719_SHM_CHANNEL1.h @@ -83,148 +83,11 @@ typedef uint32_t BCM5719_SHM_CHANNEL1_H_uint32_t; #define REG_SHM_CHANNEL1_SIZE (sizeof(SHM_CHANNEL_t)) #define REG_SHM_CHANNEL1_NCSI_CHANNEL_INFO ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a00) /* */ -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_ENABLED_SHIFT 0u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_ENABLED_MASK 0x1u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_TX_PASSTHROUGH_SHIFT 1u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_TX_PASSTHROUGH_MASK 0x2u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_TX_PASSTHROUGH(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_TX_PASSTHROUGH(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_READY_SHIFT 2u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_READY_MASK 0x4u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_READY(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_READY(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_INIT_SHIFT 3u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_INIT_MASK 0x8u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_INIT(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_INIT(__val__) (((__val__) << 3u) & 0x8u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_MFILT_SHIFT 4u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_MFILT_MASK 0x10u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_MFILT(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_MFILT(__val__) (((__val__) << 4u) & 0x10u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_BFILT_SHIFT 5u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_BFILT_MASK 0x20u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_BFILT(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_BFILT(__val__) (((__val__) << 5u) & 0x20u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_SERDES_SHIFT 6u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_SERDES_MASK 0x40u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_SERDES(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_SERDES(__val__) (((__val__) << 6u) & 0x40u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_VLAN_SHIFT 8u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_VLAN_MASK 0x100u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_VLAN(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_VLAN(__val__) (((__val__) << 8u) & 0x100u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2H_SHIFT 10u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2H_MASK 0x400u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2H(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2H(__val__) (((__val__) << 10u) & 0x400u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2N_SHIFT 11u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2N_MASK 0x800u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2N(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_B2N(__val__) (((__val__) << 11u) & 0x800u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_EEE_SHIFT 12u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_EEE_MASK 0x1000u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_EEE(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_EEE(__val__) (((__val__) << 12u) & 0x1000u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_DRIVER_SHIFT 14u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_DRIVER_MASK 0x4000u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_DRIVER(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_DRIVER(__val__) (((__val__) << 14u) & 0x4000u) -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_PDEAD_SHIFT 15u -#define SHM_CHANNEL1_NCSI_CHANNEL_INFO_PDEAD_MASK 0x8000u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_PDEAD(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_INFO_PDEAD(__val__) (((__val__) << 15u) & 0x8000u) - #define REG_SHM_CHANNEL1_NCSI_CHANNEL_MCID ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a04) /* AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs. */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_AEN ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a08) /* Set via NCSI ENABLE AEN. */ -#define SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_SHIFT 0u -#define SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_MASK 0x1u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_SHIFT 1u -#define SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_MASK 0x2u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_SHIFT 2u -#define SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_MASK 0x4u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__val__) (((__val__) << 2u) & 0x4u) - #define REG_SHM_CHANNEL1_NCSI_CHANNEL_BFILT ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a0c) /* */ -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_ARP_PACKET_SHIFT 0u -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_ARP_PACKET_MASK 0x1u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_ARP_PACKET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_ARP_PACKET(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET_SHIFT 1u -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET_MASK 0x2u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET_SHIFT 2u -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET_MASK 0x4u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_NETBIOS_PACKET_SHIFT 3u -#define SHM_CHANNEL1_NCSI_CHANNEL_BFILT_NETBIOS_PACKET_MASK 0x8u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_NETBIOS_PACKET(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_BFILT_NETBIOS_PACKET(__val__) (((__val__) << 3u) & 0x8u) - #define REG_SHM_CHANNEL1_NCSI_CHANNEL_MFILT ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a10) /* */ -#define SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_SHIFT 0u -#define SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_MASK 0x1u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT_SHIFT 1u -#define SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT_MASK 0x2u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL1_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_SHIFT 2u -#define SHM_CHANNEL1_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_MASK 0x4u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__val__) (((__val__) << 2u) & 0x4u) - #define REG_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1 ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a14) /* This is the "Link Settings" value from NCSI Set Link. */ -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED_SHIFT 0u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED_MASK 0x1u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE_SHIFT 1u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE_MASK 0x2u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE_SHIFT 2u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE_MASK 0x4u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE_SHIFT 3u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE_MASK 0x8u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE_SHIFT 4u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE_MASK 0x10u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE_SHIFT 8u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE_MASK 0x100u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE_SHIFT 9u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE_MASK 0x200u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE_SHIFT 10u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE_MASK 0x400u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_SHIFT 11u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_MASK 0x800u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 11u) & 0x800u) -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_SHIFT 12u -#define SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_MASK 0x1000u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__val__) (((__val__) << 12u) & 0x1000u) - #define REG_SHM_CHANNEL1_NCSI_CHANNEL_SETTING_2 ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a18) /* This is the "OEM Settings" value from NCSI Set Link. */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_VLAN ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a1c) /* Receives VLAN mode from NCSI specification "Enable VLAN" command. */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_ALT_HOST_MAC_HIGH ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a24) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */ @@ -247,31 +110,6 @@ typedef uint32_t BCM5719_SHM_CHANNEL1_H_uint32_t; #define REG_SHM_CHANNEL1_NCSI_CHANNEL_MAC1_VLAN_VALID ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a78) /* Nonzero indicates VLAN field is valid */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_MAC1_VLAN ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a7c) /* */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_STATUS ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a80) /* */ -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_UP_SHIFT 0u -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_UP_MASK 0x1u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_UP(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_UP(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_STATUS_SHIFT 1u -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_STATUS_MASK 0x1eu -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x1e) >> 1u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x1eu) -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_SERDES_SHIFT 5u -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_SERDES_MASK 0x20u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_SERDES(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_SERDES(__val__) (((__val__) << 5u) & 0x20u) -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 6u -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x40u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 6u) & 0x40u) -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_SHIFT 9u -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_MASK 0x200u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__val__) (((__val__) << 9u) & 0x200u) -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_SHIFT 10u -#define SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_MASK 0x400u -#define GET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL1_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__val__) (((__val__) << 10u) & 0x400u) - #define REG_SHM_CHANNEL1_NCSI_CHANNEL_RESET_COUNT ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a84) /* */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_PXE ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a88) /* */ #define REG_SHM_CHANNEL1_NCSI_CHANNEL_DROPFIL ((volatile BCM5719_SHM_CHANNEL1_H_uint32_t*)0xc0014a8c) /* */ diff --git a/include/bcm5719_SHM_CHANNEL2.h b/include/bcm5719_SHM_CHANNEL2.h index fd8a3d6..b4222b2 100644 --- a/include/bcm5719_SHM_CHANNEL2.h +++ b/include/bcm5719_SHM_CHANNEL2.h @@ -83,148 +83,11 @@ typedef uint32_t BCM5719_SHM_CHANNEL2_H_uint32_t; #define REG_SHM_CHANNEL2_SIZE (sizeof(SHM_CHANNEL_t)) #define REG_SHM_CHANNEL2_NCSI_CHANNEL_INFO ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b00) /* */ -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_ENABLED_SHIFT 0u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_ENABLED_MASK 0x1u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_TX_PASSTHROUGH_SHIFT 1u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_TX_PASSTHROUGH_MASK 0x2u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_TX_PASSTHROUGH(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_TX_PASSTHROUGH(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_READY_SHIFT 2u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_READY_MASK 0x4u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_READY(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_READY(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_INIT_SHIFT 3u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_INIT_MASK 0x8u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_INIT(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_INIT(__val__) (((__val__) << 3u) & 0x8u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_MFILT_SHIFT 4u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_MFILT_MASK 0x10u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_MFILT(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_MFILT(__val__) (((__val__) << 4u) & 0x10u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_BFILT_SHIFT 5u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_BFILT_MASK 0x20u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_BFILT(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_BFILT(__val__) (((__val__) << 5u) & 0x20u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_SERDES_SHIFT 6u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_SERDES_MASK 0x40u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_SERDES(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_SERDES(__val__) (((__val__) << 6u) & 0x40u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_VLAN_SHIFT 8u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_VLAN_MASK 0x100u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_VLAN(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_VLAN(__val__) (((__val__) << 8u) & 0x100u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2H_SHIFT 10u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2H_MASK 0x400u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2H(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2H(__val__) (((__val__) << 10u) & 0x400u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2N_SHIFT 11u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2N_MASK 0x800u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2N(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_B2N(__val__) (((__val__) << 11u) & 0x800u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_EEE_SHIFT 12u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_EEE_MASK 0x1000u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_EEE(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_EEE(__val__) (((__val__) << 12u) & 0x1000u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_DRIVER_SHIFT 14u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_DRIVER_MASK 0x4000u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_DRIVER(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_DRIVER(__val__) (((__val__) << 14u) & 0x4000u) -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_PDEAD_SHIFT 15u -#define SHM_CHANNEL2_NCSI_CHANNEL_INFO_PDEAD_MASK 0x8000u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_PDEAD(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_INFO_PDEAD(__val__) (((__val__) << 15u) & 0x8000u) - #define REG_SHM_CHANNEL2_NCSI_CHANNEL_MCID ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b04) /* AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs. */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_AEN ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b08) /* Set via NCSI ENABLE AEN. */ -#define SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_SHIFT 0u -#define SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_MASK 0x1u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_SHIFT 1u -#define SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_MASK 0x2u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_SHIFT 2u -#define SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_MASK 0x4u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__val__) (((__val__) << 2u) & 0x4u) - #define REG_SHM_CHANNEL2_NCSI_CHANNEL_BFILT ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b0c) /* */ -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_ARP_PACKET_SHIFT 0u -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_ARP_PACKET_MASK 0x1u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_ARP_PACKET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_ARP_PACKET(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET_SHIFT 1u -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET_MASK 0x2u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET_SHIFT 2u -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET_MASK 0x4u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_NETBIOS_PACKET_SHIFT 3u -#define SHM_CHANNEL2_NCSI_CHANNEL_BFILT_NETBIOS_PACKET_MASK 0x8u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_NETBIOS_PACKET(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_BFILT_NETBIOS_PACKET(__val__) (((__val__) << 3u) & 0x8u) - #define REG_SHM_CHANNEL2_NCSI_CHANNEL_MFILT ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b10) /* */ -#define SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_SHIFT 0u -#define SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_MASK 0x1u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT_SHIFT 1u -#define SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT_MASK 0x2u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL2_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_SHIFT 2u -#define SHM_CHANNEL2_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_MASK 0x4u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__val__) (((__val__) << 2u) & 0x4u) - #define REG_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1 ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b14) /* This is the "Link Settings" value from NCSI Set Link. */ -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED_SHIFT 0u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED_MASK 0x1u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE_SHIFT 1u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE_MASK 0x2u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE_SHIFT 2u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE_MASK 0x4u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE_SHIFT 3u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE_MASK 0x8u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE_SHIFT 4u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE_MASK 0x10u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE_SHIFT 8u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE_MASK 0x100u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE_SHIFT 9u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE_MASK 0x200u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE_SHIFT 10u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE_MASK 0x400u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_SHIFT 11u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_MASK 0x800u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 11u) & 0x800u) -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_SHIFT 12u -#define SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_MASK 0x1000u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__val__) (((__val__) << 12u) & 0x1000u) - #define REG_SHM_CHANNEL2_NCSI_CHANNEL_SETTING_2 ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b18) /* This is the "OEM Settings" value from NCSI Set Link. */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_VLAN ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b1c) /* Receives VLAN mode from NCSI specification "Enable VLAN" command. */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_ALT_HOST_MAC_HIGH ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b24) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */ @@ -247,31 +110,6 @@ typedef uint32_t BCM5719_SHM_CHANNEL2_H_uint32_t; #define REG_SHM_CHANNEL2_NCSI_CHANNEL_MAC1_VLAN_VALID ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b78) /* Nonzero indicates VLAN field is valid */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_MAC1_VLAN ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b7c) /* */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_STATUS ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b80) /* */ -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_UP_SHIFT 0u -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_UP_MASK 0x1u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_UP(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_UP(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_STATUS_SHIFT 1u -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_STATUS_MASK 0x1eu -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x1e) >> 1u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x1eu) -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_SERDES_SHIFT 5u -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_SERDES_MASK 0x20u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_SERDES(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_SERDES(__val__) (((__val__) << 5u) & 0x20u) -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 6u -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x40u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 6u) & 0x40u) -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_SHIFT 9u -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_MASK 0x200u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__val__) (((__val__) << 9u) & 0x200u) -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_SHIFT 10u -#define SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_MASK 0x400u -#define GET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL2_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__val__) (((__val__) << 10u) & 0x400u) - #define REG_SHM_CHANNEL2_NCSI_CHANNEL_RESET_COUNT ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b84) /* */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_PXE ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b88) /* */ #define REG_SHM_CHANNEL2_NCSI_CHANNEL_DROPFIL ((volatile BCM5719_SHM_CHANNEL2_H_uint32_t*)0xc0014b8c) /* */ diff --git a/include/bcm5719_SHM_CHANNEL3.h b/include/bcm5719_SHM_CHANNEL3.h index 79be94d..bf1db4e 100644 --- a/include/bcm5719_SHM_CHANNEL3.h +++ b/include/bcm5719_SHM_CHANNEL3.h @@ -83,148 +83,11 @@ typedef uint32_t BCM5719_SHM_CHANNEL3_H_uint32_t; #define REG_SHM_CHANNEL3_SIZE (sizeof(SHM_CHANNEL_t)) #define REG_SHM_CHANNEL3_NCSI_CHANNEL_INFO ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c00) /* */ -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_ENABLED_SHIFT 0u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_ENABLED_MASK 0x1u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_TX_PASSTHROUGH_SHIFT 1u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_TX_PASSTHROUGH_MASK 0x2u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_TX_PASSTHROUGH(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_TX_PASSTHROUGH(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_READY_SHIFT 2u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_READY_MASK 0x4u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_READY(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_READY(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_INIT_SHIFT 3u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_INIT_MASK 0x8u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_INIT(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_INIT(__val__) (((__val__) << 3u) & 0x8u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_MFILT_SHIFT 4u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_MFILT_MASK 0x10u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_MFILT(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_MFILT(__val__) (((__val__) << 4u) & 0x10u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_BFILT_SHIFT 5u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_BFILT_MASK 0x20u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_BFILT(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_BFILT(__val__) (((__val__) << 5u) & 0x20u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_SERDES_SHIFT 6u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_SERDES_MASK 0x40u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_SERDES(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_SERDES(__val__) (((__val__) << 6u) & 0x40u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_VLAN_SHIFT 8u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_VLAN_MASK 0x100u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_VLAN(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_VLAN(__val__) (((__val__) << 8u) & 0x100u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2H_SHIFT 10u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2H_MASK 0x400u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2H(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2H(__val__) (((__val__) << 10u) & 0x400u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2N_SHIFT 11u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2N_MASK 0x800u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2N(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_B2N(__val__) (((__val__) << 11u) & 0x800u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_EEE_SHIFT 12u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_EEE_MASK 0x1000u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_EEE(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_EEE(__val__) (((__val__) << 12u) & 0x1000u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_DRIVER_SHIFT 14u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_DRIVER_MASK 0x4000u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_DRIVER(__reg__) (((__reg__) & 0x4000) >> 14u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_DRIVER(__val__) (((__val__) << 14u) & 0x4000u) -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_PDEAD_SHIFT 15u -#define SHM_CHANNEL3_NCSI_CHANNEL_INFO_PDEAD_MASK 0x8000u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_PDEAD(__reg__) (((__reg__) & 0x8000) >> 15u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_INFO_PDEAD(__val__) (((__val__) << 15u) & 0x8000u) - #define REG_SHM_CHANNEL3_NCSI_CHANNEL_MCID ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c04) /* AEN Management Controller ID, set by BMC when sending AEN ENABLE command and used when sending AENs. */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_AEN ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c08) /* Set via NCSI ENABLE AEN. */ -#define SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_SHIFT 0u -#define SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN_MASK 0x1u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_LINK_STATUS_CHANGE_AEN(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_SHIFT 1u -#define SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN_MASK 0x2u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_CONFIGURATION_REQUIRED_AEN(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_SHIFT 2u -#define SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN_MASK 0x4u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_AEN_ENABLE_HOST_NC_DRIVER_STATUS_CHANGE_AEN(__val__) (((__val__) << 2u) & 0x4u) - #define REG_SHM_CHANNEL3_NCSI_CHANNEL_BFILT ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c0c) /* */ -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_ARP_PACKET_SHIFT 0u -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_ARP_PACKET_MASK 0x1u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_ARP_PACKET(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_ARP_PACKET(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET_SHIFT 1u -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET_MASK 0x2u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_CLIENT_PACKET(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET_SHIFT 2u -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET_MASK 0x4u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_DHCP_SERVER_PACKET(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_NETBIOS_PACKET_SHIFT 3u -#define SHM_CHANNEL3_NCSI_CHANNEL_BFILT_NETBIOS_PACKET_MASK 0x8u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_NETBIOS_PACKET(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_BFILT_NETBIOS_PACKET(__val__) (((__val__) << 3u) & 0x8u) - #define REG_SHM_CHANNEL3_NCSI_CHANNEL_MFILT ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c10) /* */ -#define SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_SHIFT 0u -#define SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT_MASK 0x1u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_NEIGHBOUR_ADVERTISEMENT(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT_SHIFT 1u -#define SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT_MASK 0x2u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_MFILT_IPV6_ROUTER_ADVERTISEMENT(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL3_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_SHIFT 2u -#define SHM_CHANNEL3_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST_MASK 0x4u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_MFILT_DHCPV6_RELAY_AND_SERVER_MULTICAST(__val__) (((__val__) << 2u) & 0x4u) - #define REG_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1 ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c14) /* This is the "Link Settings" value from NCSI Set Link. */ -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED_SHIFT 0u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED_MASK 0x1u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_AUTONEGOTIATION_ENABLED(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE_SHIFT 1u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE_MASK 0x2u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE(__reg__) (((__reg__) & 0x2) >> 1u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10M_ENABLE(__val__) (((__val__) << 1u) & 0x2u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE_SHIFT 2u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE_MASK 0x4u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE(__reg__) (((__reg__) & 0x4) >> 2u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_100M_ENABLE(__val__) (((__val__) << 2u) & 0x4u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE_SHIFT 3u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE_MASK 0x8u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE(__reg__) (((__reg__) & 0x8) >> 3u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_1000M_ENABLE(__val__) (((__val__) << 3u) & 0x8u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE_SHIFT 4u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE_MASK 0x10u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE(__reg__) (((__reg__) & 0x10) >> 4u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_LINK_SPEED_10G_ENABLE(__val__) (((__val__) << 4u) & 0x10u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE_SHIFT 8u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE_MASK 0x100u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x100) >> 8u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_HALF_DUPLEX_ENABLE(__val__) (((__val__) << 8u) & 0x100u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE_SHIFT 9u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE_MASK 0x200u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_FULL_DUPLEX_ENABLE(__val__) (((__val__) << 9u) & 0x200u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE_SHIFT 10u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE_MASK 0x400u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 10u) & 0x400u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_SHIFT 11u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE_MASK 0x800u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__reg__) (((__reg__) & 0x800) >> 11u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_ASYMMETRIC_PAUSE_CAPABILITY_ENABLE(__val__) (((__val__) << 11u) & 0x800u) -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_SHIFT 12u -#define SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID_MASK 0x1000u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__reg__) (((__reg__) & 0x1000) >> 12u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_1_OEM_LINK_SETTINGS_FIELD_VALID(__val__) (((__val__) << 12u) & 0x1000u) - #define REG_SHM_CHANNEL3_NCSI_CHANNEL_SETTING_2 ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c18) /* This is the "OEM Settings" value from NCSI Set Link. */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_VLAN ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c1c) /* Receives VLAN mode from NCSI specification "Enable VLAN" command. */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_ALT_HOST_MAC_HIGH ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c24) /* Lower 16 bits of this word contains upper 16 bits of the MAC. */ @@ -247,31 +110,6 @@ typedef uint32_t BCM5719_SHM_CHANNEL3_H_uint32_t; #define REG_SHM_CHANNEL3_NCSI_CHANNEL_MAC1_VLAN_VALID ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c78) /* Nonzero indicates VLAN field is valid */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_MAC1_VLAN ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c7c) /* */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_STATUS ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c80) /* */ -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_UP_SHIFT 0u -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_UP_MASK 0x1u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_UP(__reg__) (((__reg__) & 0x1) >> 0u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_UP(__val__) (((__val__) << 0u) & 0x1u) -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_STATUS_SHIFT 1u -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_STATUS_MASK 0x1eu -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_STATUS(__reg__) (((__reg__) & 0x1e) >> 1u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_STATUS(__val__) (((__val__) << 1u) & 0x1eu) -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_SERDES_SHIFT 5u -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_SERDES_MASK 0x20u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_SERDES(__reg__) (((__reg__) & 0x20) >> 5u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_SERDES(__val__) (((__val__) << 5u) & 0x20u) -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE_SHIFT 6u -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE_MASK 0x40u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE(__reg__) (((__reg__) & 0x40) >> 6u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_AUTONEGOTIATION_COMPLETE(__val__) (((__val__) << 6u) & 0x40u) -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_SHIFT 9u -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE_MASK 0x200u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x200) >> 9u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_FULL_DUPLEX_CAPABLE(__val__) (((__val__) << 9u) & 0x200u) -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_SHIFT 10u -#define SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE_MASK 0x400u -#define GET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__reg__) (((__reg__) & 0x400) >> 10u) -#define SET_SHM_CHANNEL3_NCSI_CHANNEL_STATUS_LINK_SPEED_1000M_HALS_DUPLEX_CAPABLE(__val__) (((__val__) << 10u) & 0x400u) - #define REG_SHM_CHANNEL3_NCSI_CHANNEL_RESET_COUNT ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c84) /* */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_PXE ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c88) /* */ #define REG_SHM_CHANNEL3_NCSI_CHANNEL_DROPFIL ((volatile BCM5719_SHM_CHANNEL3_H_uint32_t*)0xc0014c8c) /* */ diff --git a/ipxact/APE.xml b/ipxact/APE.xml index 1ce1997..90bf6bd 100644 --- a/ipxact/APE.xml +++ b/ipxact/APE.xml @@ -61,10 +61,10 @@ </ipxact:memoryMap> <!-- RX port 0xA000_0000 to 0xA000_3FFF (APE, function 0) --> <ipxact:memoryMap> - <ipxact:name>RX_PORT</ipxact:name> + <ipxact:name>RX_PORT0</ipxact:name> <ipxact:description>RX from network port, function 0</ipxact:description> <ipxact:addressBlock> - <ipxact:name>RX_PORT</ipxact:name> + <ipxact:name>RX_PORT0</ipxact:name> <ipxact:description>RX from network port, function 0</ipxact:description> <ipxact:typeIdentifier>RX_PORT</ipxact:typeIdentifier> <ipxact:baseAddress>0xA0000000</ipxact:baseAddress> @@ -164,10 +164,10 @@ <!-- TX port 0xA002_0000 to 0xA002_1FFF (APE, function 0) --> <ipxact:memoryMap> - <ipxact:name>TX_PORT</ipxact:name> + <ipxact:name>TX_PORT0</ipxact:name> <ipxact:description>TX to network port, function 0</ipxact:description> <ipxact:addressBlock> - <ipxact:name>TX_PORT</ipxact:name> + <ipxact:name>TX_PORT0</ipxact:name> <ipxact:description>TX to network port, function 0</ipxact:description> <ipxact:typeIdentifier>TX_PORT</ipxact:typeIdentifier>> <ipxact:baseAddress>0xA0020000</ipxact:baseAddress> diff --git a/ipxact/APE_component.xml b/ipxact/APE_component.xml index dbe49e8..f0639cf 100644 --- a/ipxact/APE_component.xml +++ b/ipxact/APE_component.xml @@ -330,6 +330,7 @@ </ipxact:register> <ipxact:register> <ipxact:name>RXBufOffset Func0</ipxact:name> + <ipxact:typeIdentifier>RXBufOffset</ipxact:typeIdentifier> <ipxact:description>This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer. The fields are block numbers (block size 128 bytes).</ipxact:description> <ipxact:addressOffset>0x14</ipxact:addressOffset> <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> @@ -380,50 +381,13 @@ </ipxact:register> <ipxact:register> <ipxact:name>RXBufOffset Func1</ipxact:name> + <ipxact:typeIdentifier>RXBufOffset</ipxact:typeIdentifier> <ipxact:description>This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer.</ipxact:description> <ipxact:addressOffset>0x18</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Tail</ipxact:name> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Head</ipxact:name> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>To Host</ipxact:name> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>IP Frag</ipxact:name> - <ipxact:bitOffset>25</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Count</ipxact:name> - <ipxact:bitOffset>26</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Valid</ipxact:name> - <ipxact:bitOffset>30</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>TX To Net Doorbell Func0</ipxact:name> + <ipxact:typeIdentifier>TX To Net Doorbell</ipxact:typeIdentifier> <ipxact:description>Written on APE TX to network after filling 0xA002 buffer with packet.</ipxact:description> <ipxact:addressOffset>0x1c</ipxact:addressOffset> <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> @@ -512,6 +476,7 @@ </ipxact:register> <ipxact:register> <ipxact:name>RX Pool Mode Status 0</ipxact:name> + <ipxact:typeIdentifier>RX Pool Mode Status</ipxact:typeIdentifier>> <ipxact:description></ipxact:description> <ipxact:addressOffset>0x78</ipxact:addressOffset> <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> @@ -571,61 +536,11 @@ <ipxact:name>RX Pool Mode Status 1</ipxact:name> <ipxact:description></ipxact:description> <ipxact:addressOffset>0x7c</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Halt</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Halt Done</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Enable</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Empty</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Error</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>5</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Reset</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>6</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Full Count</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>16</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> + <ipxact:typeIdentifier>RX Pool Mode Status</ipxact:typeIdentifier>> </ipxact:register> <ipxact:register> <ipxact:name>RX Pool Retire 0</ipxact:name> + <ipxact:typeIdentifier>RX Pool Retire</ipxact:typeIdentifier> <ipxact:description>Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame.</ipxact:description> <ipxact:addressOffset>0x80</ipxact:addressOffset> <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> @@ -688,68 +603,13 @@ </ipxact:register> <ipxact:register> <ipxact:name>RX Pool Retire 1</ipxact:name> + <ipxact:typeIdentifier>RX Pool Retire</ipxact:typeIdentifier> <ipxact:description>Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame.</ipxact:description> <ipxact:addressOffset>0x88</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Tail</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Head</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Retire</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>State</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>25</ipxact:bitOffset> - <ipxact:bitWidth>2</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>Processing</ipxact:name> - <ipxact:value>0</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Retired OK</ipxact:name> - <ipxact:value>1</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Error: Full</ipxact:name> - <ipxact:value>2</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Error: In Halt</ipxact:name> - <ipxact:value>3</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> - <ipxact:field> - <ipxact:name>Count</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>27</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>TX To Net Pool Mode Status 0</ipxact:name> + <ipxact:typeIdentifier>TX To Net Pool Mode Status</ipxact:typeIdentifier> <ipxact:description></ipxact:description> <ipxact:addressOffset>0x8c</ipxact:addressOffset> <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> @@ -807,6 +667,7 @@ </ipxact:register> <ipxact:register> <ipxact:name>TX To Net Buffer Allocator 0</ipxact:name> + <ipxact:typeIdentifier>TX To Net Buffer Allocator</ipxact:typeIdentifier> <ipxact:description></ipxact:description> <ipxact:addressOffset>0x90</ipxact:addressOffset> <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> @@ -1130,761 +991,93 @@ </ipxact:register> <ipxact:register> <ipxact:name>TX To Net Pool Mode Status 1</ipxact:name> + <ipxact:typeIdentifier>TX To Net Pool Mode Status</ipxact:typeIdentifier> <ipxact:description></ipxact:description> <ipxact:addressOffset>0x110</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Halt</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Halt Done</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Enable</ipxact:name> - <ipxact:description>Must set Enable before the APE TX To Net Buffer Allocator will work.</ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Empty</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Error</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>5</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Reset</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>6</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Full Count</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>16</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>TX To Net Buffer Allocator 1</ipxact:name> + <ipxact:typeIdentifier>TX To Net Buffer Allocator</ipxact:typeIdentifier> <ipxact:description></ipxact:description> <ipxact:addressOffset>0x114</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Index</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>Block Size</ipxact:name> - <ipxact:value>128</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> - <ipxact:field> - <ipxact:name>Request Allocation</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>State</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>13</ipxact:bitOffset> - <ipxact:bitWidth>2</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>Processing</ipxact:name> - <ipxact:value>0</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Allocation OK</ipxact:name> - <ipxact:value>1</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Error: Empty</ipxact:name> - <ipxact:value>2</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Error: In Halt</ipxact:name> - <ipxact:value>3</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>TX To Net Doorbell Func1</ipxact:name> + <ipxact:typeIdentifier>TX To Net Doorbell</ipxact:typeIdentifier> <ipxact:description>Written on APE TX to network after filling 0xA002 buffer with packet.</ipxact:description> <ipxact:addressOffset>0x120</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Tail</ipxact:name> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Head</ipxact:name> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Length</ipxact:name> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>TX Queue Full</ipxact:name> - <ipxact:bitOffset>28</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>RXBufOffset Func2</ipxact:name> + <ipxact:typeIdentifier>RXBufOffset</ipxact:typeIdentifier> <ipxact:description>This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer.</ipxact:description> <ipxact:addressOffset>0x200</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Tail</ipxact:name> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Head</ipxact:name> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>To Host</ipxact:name> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>IP Frag</ipxact:name> - <ipxact:bitOffset>25</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Count</ipxact:name> - <ipxact:bitOffset>26</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Valid</ipxact:name> - <ipxact:bitOffset>30</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>TX To Net Doorbell Func2</ipxact:name> + <ipxact:typeIdentifier>TX To Net Doorbell</ipxact:typeIdentifier> <ipxact:description>Written on APE TX to network after filling 0xA002 buffer with packet.</ipxact:description> <ipxact:addressOffset>0x204</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Tail</ipxact:name> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Head</ipxact:name> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Length</ipxact:name> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>TX Queue Full</ipxact:name> - <ipxact:bitOffset>28</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>RX Pool Mode Status 2</ipxact:name> <ipxact:description></ipxact:description> <ipxact:addressOffset>0x214</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Halt</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Halt Done</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Enable</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Empty</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Error</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>5</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Reset</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>6</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Full Count</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>16</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> + <ipxact:typeIdentifier>RX Pool Mode Status</ipxact:typeIdentifier>> </ipxact:register> <ipxact:register> <ipxact:name>RX Pool Retire 2</ipxact:name> + <ipxact:typeIdentifier>RX Pool Retire</ipxact:typeIdentifier> <ipxact:description>Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame.</ipxact:description> <ipxact:addressOffset>0x218</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Tail</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Head</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Retire</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>State</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>25</ipxact:bitOffset> - <ipxact:bitWidth>2</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>Processing</ipxact:name> - <ipxact:value>0</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Retired OK</ipxact:name> - <ipxact:value>1</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Error: Full</ipxact:name> - <ipxact:value>2</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Error: In Halt</ipxact:name> - <ipxact:value>3</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> - <ipxact:field> - <ipxact:name>Count</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>27</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>TX To Net Pool Mode Status 2</ipxact:name> + <ipxact:typeIdentifier>TX To Net Pool Mode Status</ipxact:typeIdentifier> <ipxact:description></ipxact:description> <ipxact:addressOffset>0x220</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Halt</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Halt Done</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Enable</ipxact:name> - <ipxact:description>Must set Enable before the APE TX To Net Buffer Allocator will work.</ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Empty</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Error</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>5</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Reset</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>6</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Full Count</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>16</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>TX To Net Buffer Allocator 2</ipxact:name> + <ipxact:typeIdentifier>TX To Net Buffer Allocator</ipxact:typeIdentifier> <ipxact:description></ipxact:description> <ipxact:addressOffset>0x224</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Index</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>Block Size</ipxact:name> - <ipxact:value>128</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> - <ipxact:field> - <ipxact:name>Request Allocation</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>State</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>13</ipxact:bitOffset> - <ipxact:bitWidth>2</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>Processing</ipxact:name> - <ipxact:value>0</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Allocation OK</ipxact:name> - <ipxact:value>1</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Error: Empty</ipxact:name> - <ipxact:value>2</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Error: In Halt</ipxact:name> - <ipxact:value>3</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>RXBufOffset Func3</ipxact:name> + <ipxact:typeIdentifier>RXBufOffset</ipxact:typeIdentifier> <ipxact:description>This is examined on the APE Packet RX interrupt, and indicates the offset of an incoming (from-network) frame within the APE memory space, which provides access to the from-network RX buffer.</ipxact:description> <ipxact:addressOffset>0x300</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Tail</ipxact:name> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Head</ipxact:name> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>To Host</ipxact:name> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>IP Frag</ipxact:name> - <ipxact:bitOffset>25</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Count</ipxact:name> - <ipxact:bitOffset>26</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Valid</ipxact:name> - <ipxact:bitOffset>30</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>TX To Net Doorbell Func3</ipxact:name> + <ipxact:typeIdentifier>TX To Net Doorbell</ipxact:typeIdentifier> <ipxact:description>Written on APE TX to network after filling 0xA002 buffer with packet.</ipxact:description> <ipxact:addressOffset>0x304</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Tail</ipxact:name> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Head</ipxact:name> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Length</ipxact:name> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>TX Queue Full</ipxact:name> - <ipxact:bitOffset>28</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>RX Pool Mode Status 3</ipxact:name> <ipxact:description></ipxact:description> <ipxact:addressOffset>0x314</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Halt</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Halt Done</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Enable</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Empty</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Error</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>5</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Reset</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>6</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Full Count</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>16</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> + <ipxact:typeIdentifier>RX Pool Mode Status</ipxact:typeIdentifier>> </ipxact:register> <ipxact:register> <ipxact:name>RX Pool Retire 3</ipxact:name> + <ipxact:typeIdentifier>RX Pool Retire</ipxact:typeIdentifier> <ipxact:description>Used to indicate when the APE is done with a region of the 0xA000_0000 RX pool buffer so that it can be used to receive another frame.</ipxact:description> <ipxact:addressOffset>0x318</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Tail</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Head</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Retire</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>24</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>State</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>25</ipxact:bitOffset> - <ipxact:bitWidth>2</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>Processing</ipxact:name> - <ipxact:value>0</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Retired OK</ipxact:name> - <ipxact:value>1</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Error: Full</ipxact:name> - <ipxact:value>2</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Error: In Halt</ipxact:name> - <ipxact:value>3</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> - <ipxact:field> - <ipxact:name>Count</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>27</ipxact:bitOffset> - <ipxact:bitWidth>4</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>TX To Net Pool Mode Status 3</ipxact:name> + <ipxact:typeIdentifier>TX To Net Pool Mode Status</ipxact:typeIdentifier> <ipxact:description></ipxact:description> <ipxact:addressOffset>0x320</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Halt</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Halt Done</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>1</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Enable</ipxact:name> - <ipxact:description>Must set Enable before the APE TX To Net Buffer Allocator will work.</ipxact:description> - <ipxact:bitOffset>2</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Empty</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>4</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Error</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>5</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Reset</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>6</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>Full Count</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>8</ipxact:bitOffset> - <ipxact:bitWidth>16</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> </ipxact:register> <ipxact:register> <ipxact:name>TX To Net Buffer Allocator 3</ipxact:name> + <ipxact:typeIdentifier>TX To Net Buffer Allocator</ipxact:typeIdentifier> <ipxact:description></ipxact:description> <ipxact:addressOffset>0x324</ipxact:addressOffset> - <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group --> - <ipxact:size>32</ipxact:size> - <ipxact:volatile>true</ipxact:volatile> - <ipxact:field> - <ipxact:name>Index</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>0</ipxact:bitOffset> - <ipxact:bitWidth>12</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>Block Size</ipxact:name> - <ipxact:value>128</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> - <ipxact:field> - <ipxact:name>Request Allocation</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>12</ipxact:bitOffset> - <ipxact:bitWidth>1</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - </ipxact:field> - <ipxact:field> - <ipxact:name>State</ipxact:name> - <ipxact:description></ipxact:description> - <ipxact:bitOffset>13</ipxact:bitOffset> - <ipxact:bitWidth>2</ipxact:bitWidth> - <ipxact:access>read-write</ipxact:access> - <ipxact:enumeratedValues> - <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values --> - <ipxact:enumeratedValue> - <ipxact:name>Processing</ipxact:name> - <ipxact:value>0</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Allocation OK</ipxact:name> - <ipxact:value>1</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Error: Empty</ipxact:name> - <ipxact:value>2</ipxact:value> - </ipxact:enumeratedValue> - <ipxact:enumeratedValue> - <ipxact:name>Error: In Halt</ipxact:name> - <ipxact:value>3</ipxact:value> - </ipxact:enumeratedValue> - </ipxact:enumeratedValues> - </ipxact:field> </ipxact:register> </ipxact:addressBlock> <ipxact:addressUnitBits>8</ipxact:addressUnitBits> diff --git a/libs/bcm5719/APE_sym.s b/libs/bcm5719/APE_sym.s index 075d3dd..35546da 100644 --- a/libs/bcm5719/APE_sym.s +++ b/libs/bcm5719/APE_sym.s @@ -88,9 +88,9 @@ .equ NVM, 0x60240000 .size NVM, 0x3c -.global RX_PORT -.equ RX_PORT, 0xa0000000 -.size RX_PORT, 0x4000 +.global RX_PORT0 +.equ RX_PORT0, 0xa0000000 +.size RX_PORT0, 0x4000 .global RX_PORT1 .equ RX_PORT1, 0xa0004000 @@ -104,9 +104,9 @@ .equ RX_PORT3, 0xa000c000 .size RX_PORT3, 0x4000 -.global TX_PORT -.equ TX_PORT, 0xa0020000 -.size TX_PORT, 0x2000 +.global TX_PORT0 +.equ TX_PORT0, 0xa0020000 +.size TX_PORT0, 0x2000 .global TX_PORT1 .equ TX_PORT1, 0xa0022000 diff --git a/simulator/APE_TX_PORT.cpp b/simulator/APE_RX_PORT0.cpp index 0c23069..8a9b1c0 100644 --- a/simulator/APE_TX_PORT.cpp +++ b/simulator/APE_RX_PORT0.cpp @@ -1,10 +1,10 @@ //////////////////////////////////////////////////////////////////////////////// /// -/// @file APE_TX_PORT.cpp +/// @file APE_RX_PORT0.cpp /// /// @project ape /// -/// @brief APE_TX_PORT +/// @brief APE_RX_PORT0 /// //////////////////////////////////////////////////////////////////////////////// /// @@ -42,14 +42,14 @@ /// @endcond //////////////////////////////////////////////////////////////////////////////// -#include <APE_TX_PORT.h> +#include <APE_RX_PORT0.h> -TX_PORT_t TX_PORT; +RX_PORT_t RX_PORT0; -void init_APE_TX_PORT(void) +void init_APE_RX_PORT0(void) { - /** @brief Component Registers for @ref TX_PORT. */ - /** @brief Bitmap for @ref TX_PORT_t.Out. */ + /** @brief Component Registers for @ref RX_PORT0. */ + /** @brief Bitmap for @ref RX_PORT0_t.In. */ } diff --git a/simulator/APE_RX_PORT_sim.cpp b/simulator/APE_RX_PORT0_sim.cpp index 9f63ecb..3f357b7 100644 --- a/simulator/APE_RX_PORT_sim.cpp +++ b/simulator/APE_RX_PORT0_sim.cpp @@ -1,10 +1,10 @@ //////////////////////////////////////////////////////////////////////////////// /// -/// @file APE_RX_PORT_sim.cpp +/// @file APE_RX_PORT0_sim.cpp /// /// @project ape /// -/// @brief APE_RX_PORT_sim +/// @brief APE_RX_PORT0_sim /// //////////////////////////////////////////////////////////////////////////////// /// @@ -45,7 +45,7 @@ #include <stdint.h> #include <utility> #include <bcm5719_SHM.h> -#include <APE_RX_PORT.h> +#include <APE_RX_PORT0.h> static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) { @@ -76,23 +76,23 @@ static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) return val; } -void init_APE_RX_PORT_sim(void *arg0) +void init_APE_RX_PORT0_sim(void *arg0) { (void)arg0; // unused void* base = (void*)0xa0000000; - RX_PORT.mIndexReadCallback = loader_read_mem; - RX_PORT.mIndexReadCallbackArgs = base; + RX_PORT0.mIndexReadCallback = loader_read_mem; + RX_PORT0.mIndexReadCallbackArgs = base; - RX_PORT.mIndexWriteCallback = loader_write_mem; - RX_PORT.mIndexWriteCallbackArgs = base; + RX_PORT0.mIndexWriteCallback = loader_write_mem; + RX_PORT0.mIndexWriteCallbackArgs = base; - /** @brief Component Registers for @ref RX_PORT. */ - /** @brief Bitmap for @ref RX_PORT_t.In. */ + /** @brief Component Registers for @ref RX_PORT0. */ + /** @brief Bitmap for @ref RX_PORT0_t.In. */ for(int i = 0; i < 4096; i++) { - RX_PORT.In[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); - RX_PORT.In[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + RX_PORT0.In[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + RX_PORT0.In[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); } diff --git a/simulator/APE_RX_PORT.cpp b/simulator/APE_TX_PORT0.cpp index 4eb4e45..0e71fbe 100644 --- a/simulator/APE_RX_PORT.cpp +++ b/simulator/APE_TX_PORT0.cpp @@ -1,10 +1,10 @@ //////////////////////////////////////////////////////////////////////////////// /// -/// @file APE_RX_PORT.cpp +/// @file APE_TX_PORT0.cpp /// /// @project ape /// -/// @brief APE_RX_PORT +/// @brief APE_TX_PORT0 /// //////////////////////////////////////////////////////////////////////////////// /// @@ -42,14 +42,14 @@ /// @endcond //////////////////////////////////////////////////////////////////////////////// -#include <APE_RX_PORT.h> +#include <APE_TX_PORT0.h> -RX_PORT_t RX_PORT; +TX_PORT_t TX_PORT0; -void init_APE_RX_PORT(void) +void init_APE_TX_PORT0(void) { - /** @brief Component Registers for @ref RX_PORT. */ - /** @brief Bitmap for @ref RX_PORT_t.In. */ + /** @brief Component Registers for @ref TX_PORT0. */ + /** @brief Bitmap for @ref TX_PORT0_t.Out. */ } diff --git a/simulator/APE_TX_PORT_sim.cpp b/simulator/APE_TX_PORT0_sim.cpp index 1e7bac7..5fd048a 100644 --- a/simulator/APE_TX_PORT_sim.cpp +++ b/simulator/APE_TX_PORT0_sim.cpp @@ -1,10 +1,10 @@ //////////////////////////////////////////////////////////////////////////////// /// -/// @file APE_TX_PORT_sim.cpp +/// @file APE_TX_PORT0_sim.cpp /// /// @project ape /// -/// @brief APE_TX_PORT_sim +/// @brief APE_TX_PORT0_sim /// //////////////////////////////////////////////////////////////////////////////// /// @@ -45,7 +45,7 @@ #include <stdint.h> #include <utility> #include <bcm5719_SHM.h> -#include <APE_TX_PORT.h> +#include <APE_TX_PORT0.h> static uint32_t loader_read_mem(uint32_t val, uint32_t offset, void *args) { @@ -76,23 +76,23 @@ static uint32_t loader_write_mem(uint32_t val, uint32_t offset, void *args) return val; } -void init_APE_TX_PORT_sim(void *arg0) +void init_APE_TX_PORT0_sim(void *arg0) { (void)arg0; // unused void* base = (void*)0xa0020000; - TX_PORT.mIndexReadCallback = loader_read_mem; - TX_PORT.mIndexReadCallbackArgs = base; + TX_PORT0.mIndexReadCallback = loader_read_mem; + TX_PORT0.mIndexReadCallbackArgs = base; - TX_PORT.mIndexWriteCallback = loader_write_mem; - TX_PORT.mIndexWriteCallbackArgs = base; + TX_PORT0.mIndexWriteCallback = loader_write_mem; + TX_PORT0.mIndexWriteCallbackArgs = base; - /** @brief Component Registers for @ref TX_PORT. */ - /** @brief Bitmap for @ref TX_PORT_t.Out. */ + /** @brief Component Registers for @ref TX_PORT0. */ + /** @brief Bitmap for @ref TX_PORT0_t.Out. */ for(int i = 0; i < 2048; i++) { - TX_PORT.Out[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); - TX_PORT.Out[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); + TX_PORT0.Out[i].r32.installReadCallback(loader_read_mem, (uint8_t *)base); + TX_PORT0.Out[i].r32.installWriteCallback(loader_write_mem, (uint8_t *)base); } |
