Add in additional NVM configuration registers to the ipxact and regenerate.

8 files changed, 618 insertions, 5 deletions

diff --git a/include/bcm5719_DEVICE.h b/include/bcm5719_DEVICE.h
index 4c87130..de4eef8 100644
--- a/include/bcm5719_DEVICE.h
+++ b/include/bcm5719_DEVICE.h
@@ -4819,6 +4819,50 @@ typedef register_container RegDEVICEGrcModeControl_t {
 #endif /* CXX_SIMULATOR */
 } RegDEVICEGrcModeControl_t;
 
+#define REG_DEVICE_MISCELLANEOUS_CONFIG ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0006804) /*  */
+#define     DEVICE_MISCELLANEOUS_CONFIG_ALL_SHIFT 0u
+#define     DEVICE_MISCELLANEOUS_CONFIG_ALL_MASK  0xffffffffu
+#define GET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__reg__)  (((__reg__) & 0xffffffff) >> 0u)
+#define SET_DEVICE_MISCELLANEOUS_CONFIG_ALL(__val__)  (((__val__) << 0u) & 0xffffffffu)
+
+/** @brief Register definition for @ref DEVICE_t.MiscellaneousConfig. */
+typedef register_container RegDEVICEMiscellaneousConfig_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_DEVICE_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_DEVICE_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, all, 0, 32)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief  */
+        BITFIELD_MEMBER(BCM5719_DEVICE_H_uint32_t, all, 0, 32)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_DEVICE_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "MiscellaneousConfig"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegDEVICEMiscellaneousConfig_t()
+    {
+        /** @brief constructor for @ref DEVICE_t.MiscellaneousConfig. */
+        r32.setName("MiscellaneousConfig");
+        bits.all.setBaseRegister(&r32);
+        bits.all.setName("all");
+    }
+    RegDEVICEMiscellaneousConfig_t& operator=(const RegDEVICEMiscellaneousConfig_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
+} RegDEVICEMiscellaneousConfig_t;
+
 #define REG_DEVICE_MISCELLANEOUS_LOCAL_CONTROL ((volatile BCM5719_DEVICE_H_uint32_t*)0xc0006808) /*  */
 #define     DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_SHIFT 8u
 #define     DEVICE_MISCELLANEOUS_LOCAL_CONTROL_GPIO_0_INPUT_MASK  0x100u
@@ -5677,8 +5721,8 @@ typedef struct {
     /** @brief  */
     RegDEVICEGrcModeControl_t GrcModeControl;
 
-    /** @brief Reserved bytes to pad out data structure. */
-    BCM5719_DEVICE_H_uint32_t reserved_26628[1];
+    /** @brief  */
+    RegDEVICEMiscellaneousConfig_t MiscellaneousConfig;
 
     /** @brief  */
     RegDEVICEMiscellaneousLocalControl_t MiscellaneousLocalControl;
diff --git a/ipxact/bcm5719.xml b/ipxact/bcm5719.xml
index 13dc48f..8a4f66c 100644
--- a/ipxact/bcm5719.xml
+++ b/ipxact/bcm5719.xml
@@ -2044,6 +2044,50 @@
                     </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
+                    <ipxact:name>NVM_CFG_2</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x18</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>Erase Command</ipxact:name>
+                        <ipxact:description>This is the Flash page erase command.</ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>8</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Status Command</ipxact:name>
+                        <ipxact:description>This is the Flash status register read command.</ipxact:description>
+                        <ipxact:bitOffset>16</ipxact:bitOffset>
+                        <ipxact:bitWidth>8</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NVM_CFG_3</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x1c</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>Write Command</ipxact:name>
+                        <ipxact:description>Command to write a series of bytes into a selected page in the Flash device. Note: this write command wraps around to the beginning of the page after the internal address counter in the Flash device reaches the end of the page.</ipxact:description>
+                        <ipxact:bitOffset>8</ipxact:bitOffset>
+                        <ipxact:bitWidth>8</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Read Command</ipxact:name>
+                        <ipxact:description>This is the Flash/SEEPROM read command. Following this command, any number of bytes may be read up to the end of the flash memory.</ipxact:description>
+                        <ipxact:bitOffset>24</ipxact:bitOffset>
+                        <ipxact:bitWidth>8</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                </ipxact:register>
+                <ipxact:register>
                     <ipxact:name>SOFTWARE_ARBITRATION</ipxact:name>
                     <ipxact:description></ipxact:description>
                     <ipxact:addressOffset>0x20</ipxact:addressOffset>
@@ -2157,6 +2201,126 @@
                         <ipxact:access>read-write</ipxact:access>
                     </ipxact:field>
                 </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>NVM_WRITE_1</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x28</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>Write Enable Command</ipxact:name>
+                        <ipxact:description>Flash write enable command when device with protection function is used. This command will be issued by the flash interface state machine through SPI interface.</ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>8</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Write Disable Command</ipxact:name>
+                        <ipxact:description>Flash write disable command when device with protection function is used. This command will be issued by the flash interface state machine through SPI interface.</ipxact:description>
+                        <ipxact:bitOffset>8</ipxact:bitOffset>
+                        <ipxact:bitWidth>8</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                </ipxact:register>
+                <ipxact:register>
+                    <ipxact:name>ARBITRATION_WATCHDOG</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x2C</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>reserved</ipxact:name>
+                        <ipxact:description>Reserved</ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>32</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                </ipxact:register>
+
+                <ipxact:register>
+                    <ipxact:name>AUTO_SENSE_STATUS</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x30</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>Auto Config Busy</ipxact:name>
+                        <ipxact:description>Auto Configuration Busy</ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Auto Config Enable</ipxact:name>
+                        <ipxact:description>Auto config feature is enabled through pin strap.</ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Auto Config Successful</ipxact:name>
+                        <ipxact:description>Auto config is successful.</ipxact:description>
+                        <ipxact:bitOffset>4</ipxact:bitOffset>
+                        <ipxact:bitWidth>1</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Auto Config State</ipxact:name>
+                        <ipxact:description>Auto Config FSM state.</ipxact:description>
+                        <ipxact:bitOffset>8</ipxact:bitOffset>
+                        <ipxact:bitWidth>5</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                    <ipxact:field>
+                        <ipxact:name>Auto Detected Device ID</ipxact:name>
+                        <ipxact:description>Auto detected device ID.</ipxact:description>
+                        <ipxact:bitOffset>16</ipxact:bitOffset>
+                        <ipxact:bitWidth>5</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                        <ipxact:enumeratedValues>
+                            <!-- LINK: enumeratedValue: see 6.11.10, Enumeration values -->
+                            <ipxact:enumeratedValue>
+                                <ipxact:name>AT45DB011D</ipxact:name>
+                                <ipxact:value>4</ipxact:value>
+                            </ipxact:enumeratedValue>
+                            <ipxact:enumeratedValue>
+                                <ipxact:name>AT45DB021D</ipxact:name>
+                                <ipxact:value>3</ipxact:value>
+                            </ipxact:enumeratedValue>
+                            <ipxact:enumeratedValue>
+                                <ipxact:name>AT45DB041D</ipxact:name>
+                                <ipxact:value>0</ipxact:value>
+                            </ipxact:enumeratedValue>
+                            <ipxact:enumeratedValue>
+                                <ipxact:name>STM25PE10</ipxact:name>
+                                <ipxact:value>11</ipxact:value>
+                            </ipxact:enumeratedValue>
+                            <ipxact:enumeratedValue>
+                                <ipxact:name>STM25PE20</ipxact:name>
+                                <ipxact:value>10</ipxact:value>
+                            </ipxact:enumeratedValue>
+                            <ipxact:enumeratedValue>
+                                <ipxact:name>STM25PE40</ipxact:name>
+                                <ipxact:value>8</ipxact:value>
+                            </ipxact:enumeratedValue>
+                            <ipxact:enumeratedValue>
+                                <ipxact:name>STM45PE10</ipxact:name>
+                                <ipxact:value>12</ipxact:value>
+                            </ipxact:enumeratedValue>
+                            <ipxact:enumeratedValue>
+                                <ipxact:name>STM45PE20</ipxact:name>
+                                <ipxact:value>13</ipxact:value>
+                            </ipxact:enumeratedValue>
+                            <ipxact:enumeratedValue>
+                                <ipxact:name>STM45PE40</ipxact:name>
+                                <ipxact:value>14</ipxact:value>
+                            </ipxact:enumeratedValue>
+                        </ipxact:enumeratedValues>
+                    </ipxact:field>
+                </ipxact:register>
             </ipxact:addressBlock>
         </ipxact:memoryMap>
 
@@ -5650,6 +5814,21 @@
                     </ipxact:field>
                 </ipxact:register>
                 <ipxact:register>
+                    <ipxact:name>MISCELLANEOUS_CONFIG</ipxact:name>
+                    <ipxact:description></ipxact:description>
+                    <ipxact:addressOffset>0x6804</ipxact:addressOffset>
+                    <!-- LINK: registerDefinitionGroup: see 6.11.3, Register definition group -->
+                    <ipxact:size>32</ipxact:size>
+                    <ipxact:volatile>true</ipxact:volatile>
+                    <ipxact:field>
+                        <ipxact:name>all</ipxact:name>
+                        <ipxact:description></ipxact:description>
+                        <ipxact:bitOffset>0</ipxact:bitOffset>
+                        <ipxact:bitWidth>32</ipxact:bitWidth>
+                        <ipxact:access>read-write</ipxact:access>
+                    </ipxact:field>
+                </ipxact:register>
+                <ipxact:register>
                     <ipxact:name>MISCELLANEOUS_LOCAL_CONTROL</ipxact:name>
                     <ipxact:description></ipxact:description>
                     <ipxact:addressOffset>0x6808</ipxact:addressOffset>
diff --git a/libs/NVRam/bcm5719_NVM.h b/libs/NVRam/bcm5719_NVM.h
index 6cf44e8..7b40d6d 100644
--- a/libs/NVRam/bcm5719_NVM.h
+++ b/libs/NVRam/bcm5719_NVM.h
@@ -345,6 +345,130 @@ typedef register_container RegNVMNvmCfg1_t {
 #endif /* CXX_SIMULATOR */
 } RegNVMNvmCfg1_t;
 
+#define REG_NVM_NVM_CFG_2 ((volatile BCM5719_NVM_H_uint32_t*)0xc0007018) /*  */
+#define     NVM_NVM_CFG_2_ERASE_COMMAND_SHIFT 0u
+#define     NVM_NVM_CFG_2_ERASE_COMMAND_MASK  0xffu
+#define GET_NVM_NVM_CFG_2_ERASE_COMMAND(__reg__)  (((__reg__) & 0xff) >> 0u)
+#define SET_NVM_NVM_CFG_2_ERASE_COMMAND(__val__)  (((__val__) << 0u) & 0xffu)
+#define     NVM_NVM_CFG_2_STATUS_COMMAND_SHIFT 16u
+#define     NVM_NVM_CFG_2_STATUS_COMMAND_MASK  0xff0000u
+#define GET_NVM_NVM_CFG_2_STATUS_COMMAND(__reg__)  (((__reg__) & 0xff0000) >> 16u)
+#define SET_NVM_NVM_CFG_2_STATUS_COMMAND(__val__)  (((__val__) << 16u) & 0xff0000u)
+
+/** @brief Register definition for @ref NVM_t.NvmCfg2. */
+typedef register_container RegNVMNvmCfg2_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_NVM_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_NVM_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief This is the Flash page erase command. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, EraseCommand, 0, 8)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_15_8, 8, 8)
+        /** @brief This is the Flash status register read command. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, StatusCommand, 16, 8)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_31_24, 24, 8)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_31_24, 24, 8)
+        /** @brief This is the Flash status register read command. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, StatusCommand, 16, 8)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_15_8, 8, 8)
+        /** @brief This is the Flash page erase command. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, EraseCommand, 0, 8)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_NVM_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "NvmCfg2"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegNVMNvmCfg2_t()
+    {
+        /** @brief constructor for @ref NVM_t.NvmCfg2. */
+        r32.setName("NvmCfg2");
+        bits.EraseCommand.setBaseRegister(&r32);
+        bits.EraseCommand.setName("EraseCommand");
+        bits.StatusCommand.setBaseRegister(&r32);
+        bits.StatusCommand.setName("StatusCommand");
+    }
+    RegNVMNvmCfg2_t& operator=(const RegNVMNvmCfg2_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
+} RegNVMNvmCfg2_t;
+
+#define REG_NVM_NVM_CFG_3 ((volatile BCM5719_NVM_H_uint32_t*)0xc000701c) /*  */
+#define     NVM_NVM_CFG_3_WRITE_COMMAND_SHIFT 8u
+#define     NVM_NVM_CFG_3_WRITE_COMMAND_MASK  0xff00u
+#define GET_NVM_NVM_CFG_3_WRITE_COMMAND(__reg__)  (((__reg__) & 0xff00) >> 8u)
+#define SET_NVM_NVM_CFG_3_WRITE_COMMAND(__val__)  (((__val__) << 8u) & 0xff00u)
+#define     NVM_NVM_CFG_3_READ_COMMAND_SHIFT 24u
+#define     NVM_NVM_CFG_3_READ_COMMAND_MASK  0xff000000u
+#define GET_NVM_NVM_CFG_3_READ_COMMAND(__reg__)  (((__reg__) & 0xff000000) >> 24u)
+#define SET_NVM_NVM_CFG_3_READ_COMMAND(__val__)  (((__val__) << 24u) & 0xff000000u)
+
+/** @brief Register definition for @ref NVM_t.NvmCfg3. */
+typedef register_container RegNVMNvmCfg3_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_NVM_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_NVM_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_7_0, 0, 8)
+        /** @brief Command to write a series of bytes into a selected page in the Flash device. Note: this write command wraps around to the beginning of the page after the internal address counter in the Flash device reaches the end of the page. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, WriteCommand, 8, 8)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_23_16, 16, 8)
+        /** @brief This is the Flash/SEEPROM read command. Following this command, any number of bytes may be read up to the end of the flash memory. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, ReadCommand, 24, 8)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief This is the Flash/SEEPROM read command. Following this command, any number of bytes may be read up to the end of the flash memory. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, ReadCommand, 24, 8)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_23_16, 16, 8)
+        /** @brief Command to write a series of bytes into a selected page in the Flash device. Note: this write command wraps around to the beginning of the page after the internal address counter in the Flash device reaches the end of the page. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, WriteCommand, 8, 8)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_7_0, 0, 8)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_NVM_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "NvmCfg3"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegNVMNvmCfg3_t()
+    {
+        /** @brief constructor for @ref NVM_t.NvmCfg3. */
+        r32.setName("NvmCfg3");
+        bits.WriteCommand.setBaseRegister(&r32);
+        bits.WriteCommand.setName("WriteCommand");
+        bits.ReadCommand.setBaseRegister(&r32);
+        bits.ReadCommand.setName("ReadCommand");
+    }
+    RegNVMNvmCfg3_t& operator=(const RegNVMNvmCfg3_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
+} RegNVMNvmCfg3_t;
+
 #define REG_NVM_SOFTWARE_ARBITRATION ((volatile BCM5719_NVM_H_uint32_t*)0xc0007020) /*  */
 #define     NVM_SOFTWARE_ARBITRATION_REQ_SET0_SHIFT 0u
 #define     NVM_SOFTWARE_ARBITRATION_REQ_SET0_MASK  0x1u
@@ -561,6 +685,218 @@ typedef register_container RegNVMAccess_t {
 #endif /* CXX_SIMULATOR */
 } RegNVMAccess_t;
 
+#define REG_NVM_NVM_WRITE_1 ((volatile BCM5719_NVM_H_uint32_t*)0xc0007028) /*  */
+#define     NVM_NVM_WRITE_1_WRITE_ENABLE_COMMAND_SHIFT 0u
+#define     NVM_NVM_WRITE_1_WRITE_ENABLE_COMMAND_MASK  0xffu
+#define GET_NVM_NVM_WRITE_1_WRITE_ENABLE_COMMAND(__reg__)  (((__reg__) & 0xff) >> 0u)
+#define SET_NVM_NVM_WRITE_1_WRITE_ENABLE_COMMAND(__val__)  (((__val__) << 0u) & 0xffu)
+#define     NVM_NVM_WRITE_1_WRITE_DISABLE_COMMAND_SHIFT 8u
+#define     NVM_NVM_WRITE_1_WRITE_DISABLE_COMMAND_MASK  0xff00u
+#define GET_NVM_NVM_WRITE_1_WRITE_DISABLE_COMMAND(__reg__)  (((__reg__) & 0xff00) >> 8u)
+#define SET_NVM_NVM_WRITE_1_WRITE_DISABLE_COMMAND(__val__)  (((__val__) << 8u) & 0xff00u)
+
+/** @brief Register definition for @ref NVM_t.NvmWrite1. */
+typedef register_container RegNVMNvmWrite1_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_NVM_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_NVM_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief Flash write enable command when device with protection function is used. This command will be issued by the flash interface state machine through SPI interface. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, WriteEnableCommand, 0, 8)
+        /** @brief Flash write disable command when device with protection function is used. This command will be issued by the flash interface state machine through SPI interface. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, WriteDisableCommand, 8, 8)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_31_16, 16, 16)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_31_16, 16, 16)
+        /** @brief Flash write disable command when device with protection function is used. This command will be issued by the flash interface state machine through SPI interface. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, WriteDisableCommand, 8, 8)
+        /** @brief Flash write enable command when device with protection function is used. This command will be issued by the flash interface state machine through SPI interface. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, WriteEnableCommand, 0, 8)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_NVM_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "NvmWrite1"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegNVMNvmWrite1_t()
+    {
+        /** @brief constructor for @ref NVM_t.NvmWrite1. */
+        r32.setName("NvmWrite1");
+        bits.WriteEnableCommand.setBaseRegister(&r32);
+        bits.WriteEnableCommand.setName("WriteEnableCommand");
+        bits.WriteDisableCommand.setBaseRegister(&r32);
+        bits.WriteDisableCommand.setName("WriteDisableCommand");
+    }
+    RegNVMNvmWrite1_t& operator=(const RegNVMNvmWrite1_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
+} RegNVMNvmWrite1_t;
+
+#define REG_NVM_ARBITRATION_WATCHDOG ((volatile BCM5719_NVM_H_uint32_t*)0xc000702c) /*  */
+#define     NVM_ARBITRATION_WATCHDOG_RESERVED_SHIFT 0u
+#define     NVM_ARBITRATION_WATCHDOG_RESERVED_MASK  0xffffffffu
+#define GET_NVM_ARBITRATION_WATCHDOG_RESERVED(__reg__)  (((__reg__) & 0xffffffff) >> 0u)
+#define SET_NVM_ARBITRATION_WATCHDOG_RESERVED(__val__)  (((__val__) << 0u) & 0xffffffffu)
+
+/** @brief Register definition for @ref NVM_t.ArbitrationWatchdog. */
+typedef register_container RegNVMArbitrationWatchdog_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_NVM_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_NVM_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief Reserved */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved, 0, 32)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Reserved */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved, 0, 32)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_NVM_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "ArbitrationWatchdog"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegNVMArbitrationWatchdog_t()
+    {
+        /** @brief constructor for @ref NVM_t.ArbitrationWatchdog. */
+        r32.setName("ArbitrationWatchdog");
+        bits.reserved.setBaseRegister(&r32);
+        bits.reserved.setName("reserved");
+    }
+    RegNVMArbitrationWatchdog_t& operator=(const RegNVMArbitrationWatchdog_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
+} RegNVMArbitrationWatchdog_t;
+
+#define REG_NVM_AUTO_SENSE_STATUS ((volatile BCM5719_NVM_H_uint32_t*)0xc0007030) /*  */
+#define     NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_BUSY_SHIFT 0u
+#define     NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_BUSY_MASK  0x1u
+#define GET_NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_BUSY(__reg__)  (((__reg__) & 0x1) >> 0u)
+#define SET_NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_BUSY(__val__)  (((__val__) << 0u) & 0x1u)
+#define     NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_SUCCESSFUL_SHIFT 4u
+#define     NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_SUCCESSFUL_MASK  0x10u
+#define GET_NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_SUCCESSFUL(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_SUCCESSFUL(__val__)  (((__val__) << 4u) & 0x10u)
+#define     NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_ENABLE_SHIFT 4u
+#define     NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_ENABLE_MASK  0x10u
+#define GET_NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_ENABLE(__reg__)  (((__reg__) & 0x10) >> 4u)
+#define SET_NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_ENABLE(__val__)  (((__val__) << 4u) & 0x10u)
+#define     NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_STATE_SHIFT 8u
+#define     NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_STATE_MASK  0x1f00u
+#define GET_NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_STATE(__reg__)  (((__reg__) & 0x1f00) >> 8u)
+#define SET_NVM_AUTO_SENSE_STATUS_AUTO_CONFIG_STATE(__val__)  (((__val__) << 8u) & 0x1f00u)
+#define     NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID_SHIFT 16u
+#define     NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID_MASK  0x1f0000u
+#define GET_NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID(__reg__)  (((__reg__) & 0x1f0000) >> 16u)
+#define SET_NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID(__val__)  (((__val__) << 16u) & 0x1f0000u)
+#define     NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID_AT45DB041D 0x0u
+#define     NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID_AT45DB021D 0x3u
+#define     NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID_AT45DB011D 0x4u
+#define     NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID_STM25PE40 0x8u
+#define     NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID_STM25PE20 0xau
+#define     NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID_STM25PE10 0xbu
+#define     NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID_STM45PE10 0xcu
+#define     NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID_STM45PE20 0xdu
+#define     NVM_AUTO_SENSE_STATUS_AUTO_DETECTED_DEVICE_ID_STM45PE40 0xeu
+
+
+/** @brief Register definition for @ref NVM_t.AutoSenseStatus. */
+typedef register_container RegNVMAutoSenseStatus_t {
+    /** @brief 32bit direct register access. */
+    BCM5719_NVM_H_uint32_t r32;
+
+    BITFIELD_BEGIN(BCM5719_NVM_H_uint32_t, bits)
+#if defined(__LITTLE_ENDIAN__)
+        /** @brief Auto Configuration Busy */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, AutoConfigBusy, 0, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_3_1, 1, 3)
+        /** @brief Auto config is successful. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, AutoConfigSuccessful, 4, 1)
+        /** @brief Auto config feature is enabled through pin strap. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, AutoConfigEnable, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_7_5, 5, 3)
+        /** @brief Auto Config FSM state. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, AutoConfigState, 8, 5)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_15_13, 13, 3)
+        /** @brief Auto detected device ID. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, AutoDetectedDeviceID, 16, 5)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_31_21, 21, 11)
+#elif defined(__BIG_ENDIAN__)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_31_21, 21, 11)
+        /** @brief Auto detected device ID. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, AutoDetectedDeviceID, 16, 5)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_15_13, 13, 3)
+        /** @brief Auto Config FSM state. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, AutoConfigState, 8, 5)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_7_5, 5, 3)
+        /** @brief Auto config feature is enabled through pin strap. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, AutoConfigEnable, 4, 1)
+        /** @brief Auto config is successful. */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, AutoConfigSuccessful, 4, 1)
+        /** @brief Padding */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, reserved_3_1, 1, 3)
+        /** @brief Auto Configuration Busy */
+        BITFIELD_MEMBER(BCM5719_NVM_H_uint32_t, AutoConfigBusy, 0, 1)
+#else
+#error Unknown Endian
+#endif
+    BITFIELD_END(BCM5719_NVM_H_uint32_t, bits)
+#ifdef CXX_SIMULATOR
+    /** @brief Register name for use with the simulator. */
+    const char* getName(void) { return "AutoSenseStatus"; }
+
+    /** @brief Print register value. */
+    void print(void) { r32.print(); }
+
+    RegNVMAutoSenseStatus_t()
+    {
+        /** @brief constructor for @ref NVM_t.AutoSenseStatus. */
+        r32.setName("AutoSenseStatus");
+        bits.AutoConfigBusy.setBaseRegister(&r32);
+        bits.AutoConfigBusy.setName("AutoConfigBusy");
+        bits.AutoConfigSuccessful.setBaseRegister(&r32);
+        bits.AutoConfigSuccessful.setName("AutoConfigSuccessful");
+        bits.AutoConfigEnable.setBaseRegister(&r32);
+        bits.AutoConfigEnable.setName("AutoConfigEnable");
+        bits.AutoConfigState.setBaseRegister(&r32);
+        bits.AutoConfigState.setName("AutoConfigState");
+        bits.AutoDetectedDeviceID.setBaseRegister(&r32);
+        bits.AutoDetectedDeviceID.setName("AutoDetectedDeviceID");
+    }
+    RegNVMAutoSenseStatus_t& operator=(const RegNVMAutoSenseStatus_t& other)
+    {
+        r32 = other.r32;
+        return *this;
+    }
+#endif /* CXX_SIMULATOR */
+} RegNVMAutoSenseStatus_t;
+
 /** @brief Component definition for @ref NVM. */
 typedef struct {
     /** @brief  */
@@ -581,8 +917,11 @@ typedef struct {
     /** @brief  */
     RegNVMNvmCfg1_t NvmCfg1;
 
-    /** @brief Reserved bytes to pad out data structure. */
-    BCM5719_NVM_H_uint32_t reserved_24[2];
+    /** @brief  */
+    RegNVMNvmCfg2_t NvmCfg2;
+
+    /** @brief  */
+    RegNVMNvmCfg3_t NvmCfg3;
 
     /** @brief  */
     RegNVMSoftwareArbitration_t SoftwareArbitration;
@@ -590,6 +929,15 @@ typedef struct {
     /** @brief  */
     RegNVMAccess_t Access;
 
+    /** @brief  */
+    RegNVMNvmWrite1_t NvmWrite1;
+
+    /** @brief  */
+    RegNVMArbitrationWatchdog_t ArbitrationWatchdog;
+
+    /** @brief  */
+    RegNVMAutoSenseStatus_t AutoSenseStatus;
+
 } NVM_t;
 
 /** @brief Device Registers */
diff --git a/libs/bcm5719/bcm5719_sym.s b/libs/bcm5719/bcm5719_sym.s
index f006397..c83dfea 100644
--- a/libs/bcm5719/bcm5719_sym.s
+++ b/libs/bcm5719/bcm5719_sym.s
@@ -66,7 +66,7 @@
 
 .global NVM
 .equ    NVM, 0xc0007000
-.size   NVM, 0x28
+.size   NVM, 0x34
 
 .global RXMBUF
 .equ    RXMBUF, 0x10000
diff --git a/simulator/bcm5719_DEVICE.cpp b/simulator/bcm5719_DEVICE.cpp
index 1aab6d6..fe57af6 100644
--- a/simulator/bcm5719_DEVICE.cpp
+++ b/simulator/bcm5719_DEVICE.cpp
@@ -261,6 +261,8 @@ void init_bcm5719_DEVICE(void)
 
     /** @brief Bitmap for @ref DEVICE_t.GrcModeControl. */
 
+    /** @brief Bitmap for @ref DEVICE_t.MiscellaneousConfig. */
+
     /** @brief Bitmap for @ref DEVICE_t.MiscellaneousLocalControl. */
 
     /** @brief Bitmap for @ref DEVICE_t.Timer. */
diff --git a/simulator/bcm5719_DEVICE_mmap.cpp b/simulator/bcm5719_DEVICE_mmap.cpp
index 7cab06f..663deba 100644
--- a/simulator/bcm5719_DEVICE_mmap.cpp
+++ b/simulator/bcm5719_DEVICE_mmap.cpp
@@ -611,6 +611,11 @@ void init_bcm5719_DEVICE_mmap(void *base)
     DEVICE.GrcModeControl.r32.installReadCallback(read_from_ram, &DEVICE_GrcModeControl_r32);
     DEVICE.GrcModeControl.r32.installWriteCallback(write_to_ram, &DEVICE_GrcModeControl_r32);
 
+    /** @brief Bitmap for @ref DEVICE_t.MiscellaneousConfig. */
+    static ram_offset_t DEVICE_MiscellaneousConfig_r32((uint8_t *)base, (uint32_t)26628);
+    DEVICE.MiscellaneousConfig.r32.installReadCallback(read_from_ram, &DEVICE_MiscellaneousConfig_r32);
+    DEVICE.MiscellaneousConfig.r32.installWriteCallback(write_to_ram, &DEVICE_MiscellaneousConfig_r32);
+
     /** @brief Bitmap for @ref DEVICE_t.MiscellaneousLocalControl. */
     static ram_offset_t DEVICE_MiscellaneousLocalControl_r32((uint8_t *)base, (uint32_t)26632);
     DEVICE.MiscellaneousLocalControl.r32.installReadCallback(read_from_ram, &DEVICE_MiscellaneousLocalControl_r32);
diff --git a/simulator/bcm5719_NVM.cpp b/simulator/bcm5719_NVM.cpp
index 0ccda0d..c74a24e 100644
--- a/simulator/bcm5719_NVM.cpp
+++ b/simulator/bcm5719_NVM.cpp
@@ -59,9 +59,19 @@ void init_bcm5719_NVM(void)
 
     /** @brief Bitmap for @ref NVM_t.NvmCfg1. */
 
+    /** @brief Bitmap for @ref NVM_t.NvmCfg2. */
+
+    /** @brief Bitmap for @ref NVM_t.NvmCfg3. */
+
     /** @brief Bitmap for @ref NVM_t.SoftwareArbitration. */
 
     /** @brief Bitmap for @ref NVM_t.Access. */
 
+    /** @brief Bitmap for @ref NVM_t.NvmWrite1. */
+
+    /** @brief Bitmap for @ref NVM_t.ArbitrationWatchdog. */
+
+    /** @brief Bitmap for @ref NVM_t.AutoSenseStatus. */
+
 
 }
diff --git a/simulator/bcm5719_NVM_mmap.cpp b/simulator/bcm5719_NVM_mmap.cpp
index d42fdd3..365c41c 100644
--- a/simulator/bcm5719_NVM_mmap.cpp
+++ b/simulator/bcm5719_NVM_mmap.cpp
@@ -106,6 +106,16 @@ void init_bcm5719_NVM_mmap(void *base)
     NVM.NvmCfg1.r32.installReadCallback(read_from_ram, &NVM_NvmCfg1_r32);
     NVM.NvmCfg1.r32.installWriteCallback(write_to_ram, &NVM_NvmCfg1_r32);
 
+    /** @brief Bitmap for @ref NVM_t.NvmCfg2. */
+    static ram_offset_t NVM_NvmCfg2_r32((uint8_t *)base, (uint32_t)24);
+    NVM.NvmCfg2.r32.installReadCallback(read_from_ram, &NVM_NvmCfg2_r32);
+    NVM.NvmCfg2.r32.installWriteCallback(write_to_ram, &NVM_NvmCfg2_r32);
+
+    /** @brief Bitmap for @ref NVM_t.NvmCfg3. */
+    static ram_offset_t NVM_NvmCfg3_r32((uint8_t *)base, (uint32_t)28);
+    NVM.NvmCfg3.r32.installReadCallback(read_from_ram, &NVM_NvmCfg3_r32);
+    NVM.NvmCfg3.r32.installWriteCallback(write_to_ram, &NVM_NvmCfg3_r32);
+
     /** @brief Bitmap for @ref NVM_t.SoftwareArbitration. */
     static ram_offset_t NVM_SoftwareArbitration_r32((uint8_t *)base, (uint32_t)32);
     NVM.SoftwareArbitration.r32.installReadCallback(read_from_ram, &NVM_SoftwareArbitration_r32);
@@ -116,5 +126,20 @@ void init_bcm5719_NVM_mmap(void *base)
     NVM.Access.r32.installReadCallback(read_from_ram, &NVM_Access_r32);
     NVM.Access.r32.installWriteCallback(write_to_ram, &NVM_Access_r32);
 
+    /** @brief Bitmap for @ref NVM_t.NvmWrite1. */
+    static ram_offset_t NVM_NvmWrite1_r32((uint8_t *)base, (uint32_t)40);
+    NVM.NvmWrite1.r32.installReadCallback(read_from_ram, &NVM_NvmWrite1_r32);
+    NVM.NvmWrite1.r32.installWriteCallback(write_to_ram, &NVM_NvmWrite1_r32);
+
+    /** @brief Bitmap for @ref NVM_t.ArbitrationWatchdog. */
+    static ram_offset_t NVM_ArbitrationWatchdog_r32((uint8_t *)base, (uint32_t)44);
+    NVM.ArbitrationWatchdog.r32.installReadCallback(read_from_ram, &NVM_ArbitrationWatchdog_r32);
+    NVM.ArbitrationWatchdog.r32.installWriteCallback(write_to_ram, &NVM_ArbitrationWatchdog_r32);
+
+    /** @brief Bitmap for @ref NVM_t.AutoSenseStatus. */
+    static ram_offset_t NVM_AutoSenseStatus_r32((uint8_t *)base, (uint32_t)48);
+    NVM.AutoSenseStatus.r32.installReadCallback(read_from_ram, &NVM_AutoSenseStatus_r32);
+    NVM.AutoSenseStatus.r32.installWriteCallback(write_to_ram, &NVM_AutoSenseStatus_r32);
+
 
 }