; RUN: opt %loadPolly -polly-scops -analyze < %s | FileCheck %s ; This test case verifies that we generate numbered statement names in case ; no LLVM-IR names are used in the test case. We also verify, that we ; distinguish statements named with a number and unnamed statements that happen ; to have an index identical to a number used in a statement name. ; CHECK: Arrays { ; CHECK-NEXT: float MemRef0[*][%n]; // Element size 4 ; CHECK-NEXT: float MemRef1[*][%n]; // Element size 4 ; CHECK-NEXT: } ; CHECK-NEXT: Arrays (Bounds as pw_affs) { ; CHECK-NEXT: float MemRef0[*][ [n] -> { [] -> [(n)] } ]; // Element size 4 ; CHECK-NEXT: float MemRef1[*][ [n] -> { [] -> [(n)] } ]; // Element size 4 ; CHECK-NEXT: } ; CHECK: Statements { ; CHECK-NEXT: Stmt2 ; CHECK-NEXT: Domain := ; CHECK-NEXT: [n] -> { Stmt2[i0, i1] : 0 <= i0 < n and 0 <= i1 < n }; ; CHECK-NEXT: Schedule := ; CHECK-NEXT: [n] -> { Stmt2[i0, i1] -> [0, i0, i1, 0] }; ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: [n] -> { Stmt2[i0, i1] -> MemRef0[i0, i1] }; ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: [n] -> { Stmt2[i0, i1] -> MemRef1[i0, i1] }; ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: [n] -> { Stmt2[i0, i1] -> MemRef1[i0, i1] }; ; CHECK-NEXT: Stmt10 ; CHECK-NEXT: Domain := ; CHECK-NEXT: [n] -> { Stmt10[i0, i1] : 0 <= i0 < n and 0 <= i1 < n }; ; CHECK-NEXT: Schedule := ; CHECK-NEXT: [n] -> { Stmt10[i0, i1] -> [1, i0, i1, 0] }; ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: [n] -> { Stmt10[i0, i1] -> MemRef1[i0, i1] }; ; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: [n] -> { Stmt10[i0, i1] -> MemRef0[i0, i1] }; ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: [n] -> { Stmt10[i0, i1] -> MemRef0[i0, i1] }; ; CHECK-NEXT: Stmt_2 ; CHECK-NEXT: Domain := ; CHECK-NEXT: [n] -> { Stmt_2[i0, i1] : 0 <= i0 < n and 0 <= i1 < n }; ; CHECK-NEXT: Schedule := ; CHECK-NEXT: [n] -> { Stmt_2[i0, i1] -> [1, i0, i1, 1] }; ; CHECK-NEXT: MustWriteAccess := [Reduction Type: NONE] [Scalar: 0] ; CHECK-NEXT: [n] -> { Stmt_2[i0, i1] -> MemRef0[i0, i1] target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" ; Function Attrs: nounwind uwtable define void @vec3(i64 %n, float*, float*) #0 { br label %.split .split: ; preds = %0 br label %.preheader2.lr.ph .preheader2.lr.ph: ; preds = %.split br label %.preheader2 .preheader2: ; preds = %.preheader2.lr.ph, %15 %i.010 = phi i64 [ 0, %.preheader2.lr.ph ], [ %16, %15 ] br label %.lr.ph8 .lr.ph8: ; preds = %.preheader2 br label %4 ..preheader1_crit_edge: ; preds = %15 br label %.preheader1 .preheader1: ; preds = %..preheader1_crit_edge, %.split %3 = icmp sgt i64 %n, 0 br i1 %3, label %.preheader.lr.ph, label %"name" .preheader.lr.ph: ; preds = %.preheader1 br label %.preheader ;