{
   "arrays" : [
      {
         "name" : "MemRef_A",
         "sizes" : [ "*", "1024" ],
         "type" : "double"
      },
      {
         "name" : "MemRef_B",
         "sizes" : [ "*", "1056" ],
         "type" : "double"
      }
   ],
   "context" : "{  :  }",
   "location" : "pure_c_main.c:11-16",
   "name" : "%for.cond1.preheader---%for.end18",
   "statements" : [
      {
         "accesses" : [
            {
               "kind" : "read",
               "relation" : "{ Stmt2[i0, i1, i2] -> MemRef_A[i0, 4i2] }"
            },
            {
               "kind" : "read",
               "relation" : "{ Stmt2[i0, i1, i2] -> MemRef_beta[] }"
            },
            {
               "kind" : "write",
               "relation" : "{ Stmt2[i0, i1, i2] -> MemRef_B[i0, i1] }"
            },
            {
               "kind" : "read",
               "relation" : "{ Stmt2[i0, i1, i2] -> MemRef_A[i0, 1 + 4i2] }"
            },
            {
               "kind" : "write",
               "relation" : "{ Stmt2[i0, i1, i2] -> MemRef_B[i0, i1] }"
            },
            {
               "kind" : "read",
               "relation" : "{ Stmt2[i0, i1, i2] -> MemRef_A[i0, 2 + 4i2] }"
            },
            {
               "kind" : "write",
               "relation" : "{ Stmt2[i0, i1, i2] -> MemRef_B[i0, i1] }"
            },
            {
               "kind" : "read",
               "relation" : "{ Stmt2[i0, i1, i2] -> MemRef_A[i0, 3 + 4i2] }"
            },
            {
               "kind" : "write",
               "relation" : "{ Stmt2[i0, i1, i2] -> MemRef_B[i0, i1] }"
            }
         ],
         "domain" : "{ Stmt2[i0, i1, i2] : 0 <= i0 <= 1055 and 0 <= i1 <= 1055 and 0 <= i2 <= 255 }",
         "name" : "Stmt2",
         "schedule" : "{ Stmt2[i0, i1, i2] -> [i0, i1, i2] }"
      }
   ]
}